├── .gitattributes
├── LICENSE
├── README.md
└── Verilog
    ├── sim
        └── SPI_Slave_TB.sv
    └── source
        └── SPI_Slave.v


/.gitattributes:
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1 | # Auto detect text files and perform LF normalization
2 | * text=auto
3 | 


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/LICENSE:
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 1 | MIT License
 2 | 
 3 | Copyright (c) 2019 russell-merrick
 4 | 
 5 | Permission is hereby granted, free of charge, to any person obtaining a copy
 6 | of this software and associated documentation files (the "Software"), to deal
 7 | in the Software without restriction, including without limitation the rights
 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 9 | copies of the Software, and to permit persons to whom the Software is
10 | furnished to do so, subject to the following conditions:
11 | 
12 | The above copyright notice and this permission notice shall be included in all
13 | copies or substantial portions of the Software.
14 | 
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 | SOFTWARE.


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/README.md:
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1 | # spi-slave
2 | 


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/Verilog/sim/SPI_Slave_TB.sv:
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  1 | ///////////////////////////////////////////////////////////////////////////////
  2 | // Description:       Simple test bench for SPI Master and Slave modules
  3 | ///////////////////////////////////////////////////////////////////////////////
  4 | 
  5 | module SPI_Slave_TB ();
  6 |   
  7 |   parameter SPI_MODE = 1; // CPOL = 0, CPHA = 1
  8 |   parameter SPI_CLK_DELAY = 20;  // 2.5 MHz
  9 |   parameter MAIN_CLK_DELAY = 2;  // 25 MHz
 10 | 
 11 |   logic w_CPOL; // clock polarity
 12 |   logic w_CPHA; // clock phase
 13 | 
 14 |   assign w_CPOL = (SPI_MODE == 2) | (SPI_MODE == 3);
 15 |   assign w_CPHA = (SPI_MODE == 1) | (SPI_MODE == 3);
 16 | 
 17 |   logic r_Rst_L     = 1'b0;
 18 | 
 19 |   logic [7:0] dataPayload[0:255]; 
 20 |   logic [7:0] dataLength;
 21 |   
 22 |   // CPOL=0, clock idles 0.  CPOL=1, clock idles 1
 23 | //  logic r_SPI_Clk   = w_CPOL ? 1'b1 : 1'b0;
 24 |   logic w_SPI_Clk;
 25 |   logic r_SPI_En    = 1'b0;
 26 |   logic r_Clk       = 1'b0;
 27 |   logic w_SPI_CS_n;
 28 |   logic w_SPI_MOSI;
 29 |   logic w_SPI_MISO;
 30 | 
 31 |   // Master Specific
 32 |   logic [7:0] r_Master_TX_Byte = 0;
 33 |   logic r_Master_TX_DV = 1'b0;
 34 |   logic r_Master_CS_n = 1'b1;
 35 |   logic w_Master_TX_Ready;
 36 |   logic r_Master_RX_DV;
 37 |   logic [7:0] r_Master_RX_Byte;
 38 | 
 39 |   // Slave Specific
 40 |   logic       w_Slave_RX_DV, r_Slave_TX_DV;
 41 |   logic [7:0] w_Slave_RX_Byte, r_Slave_TX_Byte;
 42 | 
 43 |   // Clock Generators:
 44 |   always #(MAIN_CLK_DELAY) r_Clk = ~r_Clk;
 45 | 
 46 |   // Instantiate UUT
 47 |   SPI_Slave #(.SPI_MODE(SPI_MODE)) SPI_Slave_UUT
 48 |   (
 49 |    // Control/Data Signals,
 50 |    .i_Rst_L(r_Rst_L),      // FPGA Reset
 51 |    .i_Clk(r_Clk),          // FPGA Clock
 52 |    .o_RX_DV(w_Slave_RX_DV),      // Data Valid pulse (1 clock cycle)
 53 |    .o_RX_Byte(w_Slave_RX_Byte),  // Byte received on MOSI
 54 |    .i_TX_DV(w_Slave_RX_DV),      // Data Valid pulse
 55 |    .i_TX_Byte(w_Slave_RX_Byte),  // Byte to serialize to MISO (set up for loopback)
 56 | 
 57 |    // SPI Interface
 58 |    .i_SPI_Clk(w_SPI_Clk),
 59 |    .o_SPI_MISO(w_SPI_MISO),
 60 |    .i_SPI_MOSI(w_SPI_MOSI),
 61 |    .i_SPI_CS_n(r_Master_CS_n)
 62 |    );
 63 | 
 64 |   // Instantiate Master to drive Slave
 65 |   SPI_Master 
 66 |   #(.SPI_MODE(SPI_MODE),
 67 |     .CLKS_PER_HALF_BIT(2),
 68 |     .NUM_SLAVES(1)) SPI_Master_UUT
 69 |   (
 70 |    // Control/Data Signals,
 71 |    .i_Rst_L(r_Rst_L),     // FPGA Reset
 72 |    .i_Clk(r_Clk),         // FPGA Clock
 73 |    
 74 |    // TX (MOSI) Signals
 75 |    .i_TX_Byte(r_Master_TX_Byte),     // Byte to transmit on MOSI
 76 |    .i_TX_DV(r_Master_TX_DV),         // Data Valid Pulse with i_TX_Byte
 77 |    .o_TX_Ready(w_Master_TX_Ready),   // Transmit Ready for Byte
 78 |    
 79 |    // RX (MISO) Signals
 80 |    .o_RX_DV(r_Master_RX_DV),       // Data Valid pulse (1 clock cycle)
 81 |    .o_RX_Byte(r_Master_RX_Byte),   // Byte received on MISO
 82 | 
 83 |    // SPI Interface
 84 |    .o_SPI_Clk(w_SPI_Clk),
 85 |    .i_SPI_MISO(w_SPI_MISO),
 86 |    .o_SPI_MOSI(w_SPI_MOSI)
 87 |    );
 88 | 
 89 | 
 90 |   // Sends a single byte from master to slave.  Will drive CS on its own.
 91 |   task SendSingleByte(input [7:0] data);
 92 |     @(posedge r_Clk);
 93 |     r_Master_TX_Byte <= data;
 94 |     r_Master_TX_DV   <= 1'b1;
 95 |     r_Master_CS_n    <= 1'b0;
 96 |     @(posedge r_Clk);
 97 |     r_Master_TX_DV <= 1'b0;
 98 |     @(posedge w_Master_TX_Ready);
 99 |     r_Master_CS_n    <= 1'b1;    
100 |   endtask // SendSingleByte
101 | 
102 | 
103 |   // Sends a multi-byte transfer from master to slave.  Drives CS on its own.  
104 |   task SendMultiByte(input [7:0] data[0:255], input [7:0] length);
105 |     integer ii;
106 | 
107 |     @(posedge r_Clk);
108 |     r_Master_CS_n    <= 1'b0;
109 | 
110 |     for (ii=0; ii<length; ii++)
111 |     begin
112 |       @(posedge r_Clk);
113 |       r_Master_TX_Byte <= data[ii];
114 |       r_Master_TX_DV   <= 1'b1;
115 |       @(posedge r_Clk);
116 |       r_Master_TX_DV <= 1'b0;
117 |       @(posedge w_Master_TX_Ready);
118 |     end
119 |     r_Master_CS_n <= 1'b1;
120 |   endtask // SendMultiByte
121 | 
122 |     
123 |   initial
124 |     begin
125 |       repeat(10) @(posedge r_Clk);
126 |       r_Rst_L  = 1'b0;
127 |       repeat(10) @(posedge r_Clk);
128 |       r_Rst_L          = 1'b1;
129 |       r_Slave_TX_Byte <= 8'h5A;
130 |       r_Slave_TX_DV   <= 1'b1;
131 |       repeat(10) @(posedge r_Clk);
132 |       r_Slave_TX_DV   <= 1'b0;
133 |       SendSingleByte(8'hC1);
134 |       repeat(100) @(posedge r_Clk);
135 |       dataPayload[0]  = 8'h00;
136 |       dataPayload[1]  = 8'h01;
137 |       dataPayload[2]  = 8'h80;
138 |       dataPayload[3]  = 8'hFF;
139 |       dataPayload[4]  = 8'h55;
140 |       dataPayload[5]  = 8'hAA;
141 |       dataLength      = 6;
142 |       SendMultiByte(dataPayload, dataLength);
143 |       repeat(100) @(posedge r_Clk);
144 |       $finish();      
145 |     end // initial begin
146 | 
147 | endmodule // SPI_Slave
148 | 
149 | 
150 | 
151 | 


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/Verilog/source/SPI_Slave.v:
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  1 | ///////////////////////////////////////////////////////////////////////////////
  2 | // Description: SPI (Serial Peripheral Interface) Slave
  3 | //              Creates slave based on input configuration.
  4 | //              Receives a byte one bit at a time on MOSI
  5 | //              Will also push out byte data one bit at a time on MISO.  
  6 | //              Any data on input byte will be shipped out on MISO.
  7 | //              Supports multiple bytes per transaction when CS_n is kept 
  8 | //              low during the transaction.
  9 | //
 10 | // Note:        i_Clk must be at least 4x faster than i_SPI_Clk
 11 | //              MISO is tri-stated when not communicating.  Allows for multiple
 12 | //              SPI Slaves on the same interface.
 13 | //
 14 | // Parameters:  SPI_MODE, can be 0, 1, 2, or 3.  See above.
 15 | //              Can be configured in one of 4 modes:
 16 | //              Mode | Clock Polarity (CPOL/CKP) | Clock Phase (CPHA)
 17 | //               0   |             0             |        0
 18 | //               1   |             0             |        1
 19 | //               2   |             1             |        0
 20 | //               3   |             1             |        1
 21 | //              More info: https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus#Mode_numbers
 22 | ///////////////////////////////////////////////////////////////////////////////
 23 | 
 24 | module SPI_Slave
 25 |   #(parameter SPI_MODE = 0)
 26 |   (
 27 |    // Control/Data Signals,
 28 |    input            i_Rst_L,    // FPGA Reset, active low
 29 |    input            i_Clk,      // FPGA Clock
 30 |    output reg       o_RX_DV,    // Data Valid pulse (1 clock cycle)
 31 |    output reg [7:0] o_RX_Byte,  // Byte received on MOSI
 32 |    input            i_TX_DV,    // Data Valid pulse to register i_TX_Byte
 33 |    input  [7:0]     i_TX_Byte,  // Byte to serialize to MISO.
 34 | 
 35 |    // SPI Interface
 36 |    input      i_SPI_Clk,
 37 |    output reg o_SPI_MISO,
 38 |    input      i_SPI_MOSI,
 39 |    input      i_SPI_CS_n        // active low
 40 |    );
 41 | 
 42 | 
 43 |   // SPI Interface (All Runs at SPI Clock Domain)
 44 |   wire w_CPOL;     // Clock polarity
 45 |   wire w_CPHA;     // Clock phase
 46 |   wire w_SPI_Clk;  // Inverted/non-inverted depending on settings
 47 |   wire w_SPI_MISO_Mux;
 48 |   
 49 |   reg [2:0] r_RX_Bit_Count;
 50 |   reg [2:0] r_TX_Bit_Count;
 51 |   reg [7:0] r_Temp_RX_Byte;
 52 |   reg [7:0] r_RX_Byte;
 53 |   reg r_RX_Done, r2_RX_Done, r3_RX_Done;
 54 |   reg [7:0] r_TX_Byte;
 55 |   reg r_SPI_MISO_Bit, r_Preload_MISO;
 56 | 
 57 |   // CPOL: Clock Polarity
 58 |   // CPOL=0 means clock idles at 0, leading edge is rising edge.
 59 |   // CPOL=1 means clock idles at 1, leading edge is falling edge.
 60 |   assign w_CPOL  = (SPI_MODE == 2) | (SPI_MODE == 3);
 61 | 
 62 |   // CPHA: Clock Phase
 63 |   // CPHA=0 means the "out" side changes the data on trailing edge of clock
 64 |   //              the "in" side captures data on leading edge of clock
 65 |   // CPHA=1 means the "out" side changes the data on leading edge of clock
 66 |   //              the "in" side captures data on the trailing edge of clock
 67 |   assign w_CPHA  = (SPI_MODE == 1) | (SPI_MODE == 3);
 68 | 
 69 |   assign w_SPI_Clk = w_CPHA ? ~i_SPI_Clk : i_SPI_Clk;
 70 | 
 71 | 
 72 | 
 73 |   // Purpose: Recover SPI Byte in SPI Clock Domain
 74 |   // Samples line on correct edge of SPI Clock
 75 |   always @(posedge w_SPI_Clk or posedge i_SPI_CS_n)
 76 |   begin
 77 |     if (i_SPI_CS_n)
 78 |     begin
 79 |       r_RX_Bit_Count <= 0;
 80 |       r_RX_Done      <= 1'b0;
 81 |     end
 82 |     else
 83 |     begin
 84 |       r_RX_Bit_Count <= r_RX_Bit_Count + 1;
 85 | 
 86 |       // Receive in LSB, shift up to MSB
 87 |       r_Temp_RX_Byte <= {r_Temp_RX_Byte[6:0], i_SPI_MOSI};
 88 |     
 89 |       if (r_RX_Bit_Count == 3'b111)
 90 |       begin
 91 |         r_RX_Done <= 1'b1;
 92 |         r_RX_Byte <= {r_Temp_RX_Byte[6:0], i_SPI_MOSI};
 93 |       end
 94 |       else if (r_RX_Bit_Count == 3'b010)
 95 |       begin
 96 |         r_RX_Done <= 1'b0;        
 97 |       end
 98 | 
 99 |     end // else: !if(i_SPI_CS_n)
100 |   end // always @ (posedge w_SPI_Clk or posedge i_SPI_CS_n)
101 | 
102 | 
103 | 
104 |   // Purpose: Cross from SPI Clock Domain to main FPGA clock domain
105 |   // Assert o_RX_DV for 1 clock cycle when o_RX_Byte has valid data.
106 |   always @(posedge i_Clk or negedge i_Rst_L)
107 |   begin
108 |     if (~i_Rst_L)
109 |     begin
110 |       r2_RX_Done <= 1'b0;
111 |       r3_RX_Done <= 1'b0;
112 |       o_RX_DV    <= 1'b0;
113 |       o_RX_Byte  <= 8'h00;
114 |     end
115 |     else
116 |     begin
117 |       // Here is where clock domains are crossed.
118 |       // This will require timing constraint created, can set up long path.
119 |       r2_RX_Done <= r_RX_Done;
120 | 
121 |       r3_RX_Done <= r2_RX_Done;
122 | 
123 |       if (r3_RX_Done == 1'b0 && r2_RX_Done == 1'b1) // rising edge
124 |       begin
125 |         o_RX_DV   <= 1'b1;  // Pulse Data Valid 1 clock cycle
126 |         o_RX_Byte <= r_RX_Byte;
127 |       end
128 |       else
129 |       begin
130 |         o_RX_DV <= 1'b0;
131 |       end
132 |     end // else: !if(~i_Rst_L)
133 |   end // always @ (posedge i_Bus_Clk)
134 | 
135 | 
136 |   // Control preload signal.  Should be 1 when CS is high, but as soon as
137 |   // first clock edge is seen it goes low.
138 |   always @(posedge w_SPI_Clk or posedge i_SPI_CS_n)
139 |   begin
140 |     if (i_SPI_CS_n)
141 |     begin
142 |       r_Preload_MISO <= 1'b1;
143 |     end
144 |     else
145 |     begin
146 |       r_Preload_MISO <= 1'b0;
147 |     end
148 |   end
149 | 
150 | 
151 |   // Purpose: Transmits 1 SPI Byte whenever SPI clock is toggling
152 |   // Will transmit read data back to SW over MISO line.
153 |   // Want to put data on the line immediately when CS goes low.
154 |   always @(posedge w_SPI_Clk or posedge i_SPI_CS_n)
155 |   begin
156 |     if (i_SPI_CS_n)
157 |     begin
158 |       r_TX_Bit_Count <= 3'b111;  // Send MSb first
159 |       r_SPI_MISO_Bit <= r_TX_Byte[3'b111];  // Reset to MSb
160 |     end
161 |     else
162 |     begin
163 |       r_TX_Bit_Count <= r_TX_Bit_Count - 1;
164 | 
165 |       // Here is where data crosses clock domains from i_Clk to w_SPI_Clk
166 |       // Can set up a timing constraint with wide margin for data path.
167 |       r_SPI_MISO_Bit <= r_TX_Byte[r_TX_Bit_Count];
168 | 
169 |     end // else: !if(i_SPI_CS_n)
170 |   end // always @ (negedge w_SPI_Clk or posedge i_SPI_CS_n_SW)
171 | 
172 | 
173 |   // Purpose: Register TX Byte when DV pulse comes.  Keeps registed byte in 
174 |   // this module to get serialized and sent back to master.
175 |   always @(posedge i_Clk or negedge i_Rst_L)
176 |   begin
177 |     if (~i_Rst_L)
178 |     begin
179 |       r_TX_Byte <= 8'h00;
180 |     end
181 |     else
182 |     begin
183 |       if (i_TX_DV)
184 |       begin
185 |         r_TX_Byte <= i_TX_Byte; 
186 |       end
187 |     end // else: !if(~i_Rst_L)
188 |   end // always @ (posedge i_Clk or negedge i_Rst_L)
189 | 
190 |   // Preload MISO with top bit of send data when preload selector is high.
191 |   // Otherwise just send the normal MISO data
192 |   assign w_SPI_MISO_Mux = r_Preload_MISO ? r_TX_Byte[3'b111] : r_SPI_MISO_Bit;
193 | 
194 |   // Tri-state MISO when CS is high.  Allows for multiple slaves to talk.
195 |   assign o_SPI_MISO = i_SPI_CS_n ? 1'bZ : w_SPI_MISO_Mux;
196 | 
197 | endmodule // SPI_Slave
198 | 


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