├── README.TXT
├── USER
    ├── main.c
    ├── stm32f10x.h
    ├── JLinkSettings.ini
    ├── stm32f10x_it.h
    ├── system_stm32f10x.h
    ├── stm32f10x_it.c
    ├── stm32f10x_conf.h
    ├── DebugConfig
    │   ├── LED_STM32F103C8.dbgconf
    │   ├── LED_STM32F103ZE.dbgconf
    │   ├── LED_STM32F103C8_1.0.0.dbgconf
    │   └── LED_STM32F103ZE_1.0.0.dbgconf
    └── LED.uvoptx
├── keilkilll.bat
├── SYSTEM
    ├── sys
    │   ├── sys.c
    │   └── sys.h
    ├── delay
    │   ├── delay.c
    │   └── delay.h
    └── usart
    │   ├── usart.c
    │   └── usart.h
├── HARDWARE
    ├── KEY
    │   ├── key.c
    │   └── key.h
    └── TIMER
    │   ├── timer.c
    │   └── timer.h
├── STM32F10x_FWLib
    ├── src
    │   ├── stm32f10x_flash.c
    │   ├── stm32f10x_i2c.c
    │   ├── stm32f10x_usart.c
    │   ├── stm32f10x_crc.c
    │   ├── stm32f10x_iwdg.c
    │   ├── stm32f10x_dbgmcu.c
    │   ├── stm32f10x_wwdg.c
    │   ├── misc.c
    │   ├── stm32f10x_exti.c
    │   ├── stm32f10x_bkp.c
    │   ├── stm32f10x_pwr.c
    │   ├── stm32f10x_rtc.c
    │   └── stm32f10x_cec.c
    └── inc
    │   ├── stm32f10x_crc.h
    │   ├── stm32f10x_wwdg.h
    │   ├── stm32f10x_dbgmcu.h
    │   ├── stm32f10x_iwdg.h
    │   ├── stm32f10x_rtc.h
    │   ├── stm32f10x_pwr.h
    │   ├── stm32f10x_cec.h
    │   ├── stm32f10x_exti.h
    │   ├── stm32f10x_bkp.h
    │   └── misc.h
├── OBJ
    └── LED.hex
└── CORE
    └── startup_stm32f10x_md.s


/README.TXT:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/README.TXT


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/USER/main.c:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/USER/main.c


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/keilkilll.bat:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/keilkilll.bat


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/SYSTEM/sys/sys.c:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/SYSTEM/sys/sys.c


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/SYSTEM/sys/sys.h:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/SYSTEM/sys/sys.h


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/USER/stm32f10x.h:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/USER/stm32f10x.h


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/HARDWARE/KEY/key.c:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/HARDWARE/KEY/key.c


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/HARDWARE/KEY/key.h:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/HARDWARE/KEY/key.h


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/HARDWARE/TIMER/timer.c:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/HARDWARE/TIMER/timer.c


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/HARDWARE/TIMER/timer.h:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/HARDWARE/TIMER/timer.h


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/SYSTEM/delay/delay.c:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/SYSTEM/delay/delay.c


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/SYSTEM/delay/delay.h:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/SYSTEM/delay/delay.h


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/SYSTEM/usart/usart.c:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/SYSTEM/usart/usart.c


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/SYSTEM/usart/usart.h:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/SYSTEM/usart/usart.h


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/STM32F10x_FWLib/src/stm32f10x_flash.c:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/STM32F10x_FWLib/src/stm32f10x_flash.c


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/STM32F10x_FWLib/src/stm32f10x_i2c.c:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/STM32F10x_FWLib/src/stm32f10x_i2c.c


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/STM32F10x_FWLib/src/stm32f10x_usart.c:
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https://raw.githubusercontent.com/nanshoui163/KeyStateMachine2/HEAD/STM32F10x_FWLib/src/stm32f10x_usart.c


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/USER/JLinkSettings.ini:
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 1 | [BREAKPOINTS]
 2 | ForceImpTypeAny = 0
 3 | ShowInfoWin = 1
 4 | EnableFlashBP = 2
 5 | BPDuringExecution = 0
 6 | [CFI]
 7 | CFISize = 0x00
 8 | CFIAddr = 0x00
 9 | [CPU]
10 | OverrideMemMap = 0
11 | AllowSimulation = 1
12 | ScriptFile=""
13 | [FLASH]
14 | CacheExcludeSize = 0x00
15 | CacheExcludeAddr = 0x00
16 | MinNumBytesFlashDL = 0
17 | SkipProgOnCRCMatch = 1
18 | VerifyDownload = 1
19 | AllowCaching = 1
20 | EnableFlashDL = 2
21 | Override = 0
22 | Device="UNSPECIFIED"
23 | [GENERAL]
24 | WorkRAMSize = 0x00
25 | WorkRAMAddr = 0x00
26 | RAMUsageLimit = 0x00
27 | [SWO]
28 | SWOLogFile=""
29 | [MEM]
30 | RdOverrideOrMask = 0x00
31 | RdOverrideAndMask = 0xFFFFFFFF
32 | RdOverrideAddr = 0xFFFFFFFF
33 | WrOverrideOrMask = 0x00
34 | WrOverrideAndMask = 0xFFFFFFFF
35 | WrOverrideAddr = 0xFFFFFFFF
36 | 


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/USER/stm32f10x_it.h:
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 1 | /**
 2 |   ******************************************************************************
 3 |   * @file    GPIO/IOToggle/stm32f10x_it.h 
 4 |   * @author  MCD Application Team
 5 |   * @version V3.5.0
 6 |   * @date    08-April-2011
 7 |   * @brief   This file contains the headers of the interrupt handlers.
 8 |   ******************************************************************************
 9 |   * @attention
10 |   *
11 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 |   *
18 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
19 |   ******************************************************************************
20 |   */
21 | 
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_IT_H
24 | #define __STM32F10x_IT_H
25 | 
26 | /* Includes ------------------------------------------------------------------*/
27 | #include "stm32f10x.h"
28 | 
29 | /* Exported types ------------------------------------------------------------*/
30 | /* Exported constants --------------------------------------------------------*/
31 | /* Exported macro ------------------------------------------------------------*/
32 | /* Exported functions ------------------------------------------------------- */
33 | 
34 | void NMI_Handler(void);
35 | void HardFault_Handler(void);
36 | void MemManage_Handler(void);
37 | void BusFault_Handler(void);
38 | void UsageFault_Handler(void);
39 | void SVC_Handler(void);
40 | void DebugMon_Handler(void);
41 | void PendSV_Handler(void);
42 | void SysTick_Handler(void);
43 | 
44 | #endif /* __STM32F10x_IT_H */
45 | 
46 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
47 | 


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/USER/system_stm32f10x.h:
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 1 | /**
 2 |   ******************************************************************************
 3 |   * @file    system_stm32f10x.h
 4 |   * @author  MCD Application Team
 5 |   * @version V3.5.0
 6 |   * @date    11-March-2011
 7 |   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
 8 |   ******************************************************************************
 9 |   * @attention
10 |   *
11 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 |   *
18 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
19 |   ******************************************************************************
20 |   */
21 | 
22 | /** @addtogroup CMSIS
23 |   * @{
24 |   */
25 | 
26 | /** @addtogroup stm32f10x_system
27 |   * @{
28 |   */  
29 |   
30 | /**
31 |   * @brief Define to prevent recursive inclusion
32 |   */
33 | #ifndef __SYSTEM_STM32F10X_H
34 | #define __SYSTEM_STM32F10X_H
35 | 
36 | #ifdef __cplusplus
37 |  extern "C" {
38 | #endif 
39 | 
40 | /** @addtogroup STM32F10x_System_Includes
41 |   * @{
42 |   */
43 | 
44 | /**
45 |   * @}
46 |   */
47 | 
48 | 
49 | /** @addtogroup STM32F10x_System_Exported_types
50 |   * @{
51 |   */
52 | 
53 | extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
54 | 
55 | /**
56 |   * @}
57 |   */
58 | 
59 | /** @addtogroup STM32F10x_System_Exported_Constants
60 |   * @{
61 |   */
62 | 
63 | /**
64 |   * @}
65 |   */
66 | 
67 | /** @addtogroup STM32F10x_System_Exported_Macros
68 |   * @{
69 |   */
70 | 
71 | /**
72 |   * @}
73 |   */
74 | 
75 | /** @addtogroup STM32F10x_System_Exported_Functions
76 |   * @{
77 |   */
78 |   
79 | extern void SystemInit(void);
80 | extern void SystemCoreClockUpdate(void);
81 | /**
82 |   * @}
83 |   */
84 | 
85 | #ifdef __cplusplus
86 | }
87 | #endif
88 | 
89 | #endif /*__SYSTEM_STM32F10X_H */
90 | 
91 | /**
92 |   * @}
93 |   */
94 |   
95 | /**
96 |   * @}
97 |   */  
98 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
99 | 


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/STM32F10x_FWLib/inc/stm32f10x_crc.h:
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 1 | /**
 2 |   ******************************************************************************
 3 |   * @file    stm32f10x_crc.h
 4 |   * @author  MCD Application Team
 5 |   * @version V3.5.0
 6 |   * @date    11-March-2011
 7 |   * @brief   This file contains all the functions prototypes for the CRC firmware 
 8 |   *          library.
 9 |   ******************************************************************************
10 |   * @attention
11 |   *
12 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 |   *
19 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
20 |   ******************************************************************************
21 |   */
22 | 
23 | /* Define to prevent recursive inclusion -------------------------------------*/
24 | #ifndef __STM32F10x_CRC_H
25 | #define __STM32F10x_CRC_H
26 | 
27 | #ifdef __cplusplus
28 |  extern "C" {
29 | #endif
30 | 
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f10x.h"
33 | 
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
35 |   * @{
36 |   */
37 | 
38 | /** @addtogroup CRC
39 |   * @{
40 |   */
41 | 
42 | /** @defgroup CRC_Exported_Types
43 |   * @{
44 |   */
45 | 
46 | /**
47 |   * @}
48 |   */
49 | 
50 | /** @defgroup CRC_Exported_Constants
51 |   * @{
52 |   */
53 | 
54 | /**
55 |   * @}
56 |   */
57 | 
58 | /** @defgroup CRC_Exported_Macros
59 |   * @{
60 |   */
61 | 
62 | /**
63 |   * @}
64 |   */
65 | 
66 | /** @defgroup CRC_Exported_Functions
67 |   * @{
68 |   */
69 | 
70 | void CRC_ResetDR(void);
71 | uint32_t CRC_CalcCRC(uint32_t Data);
72 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
73 | uint32_t CRC_GetCRC(void);
74 | void CRC_SetIDRegister(uint8_t IDValue);
75 | uint8_t CRC_GetIDRegister(void);
76 | 
77 | #ifdef __cplusplus
78 | }
79 | #endif
80 | 
81 | #endif /* __STM32F10x_CRC_H */
82 | /**
83 |   * @}
84 |   */
85 | 
86 | /**
87 |   * @}
88 |   */
89 | 
90 | /**
91 |   * @}
92 |   */
93 | 
94 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
95 | 


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/USER/stm32f10x_it.c:
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 1 | /**
 2 |   ******************************************************************************
 3 |   * @file    GPIO/IOToggle/stm32f10x_it.c 
 4 |   * @author  MCD Application Team
 5 |   * @version V3.5.0
 6 |   * @date    08-April-2011
 7 |   * @brief   Main Interrupt Service Routines.
 8 |   *          This file provides template for all exceptions handler and peripherals
 9 |   *          interrupt service routine.
10 |   ******************************************************************************
11 |   * @attention
12 |   *
13 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
15 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
16 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
17 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
18 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 |   *
20 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
21 |   ******************************************************************************
22 |   */
23 | 
24 | /* Includes ------------------------------------------------------------------*/
25 | #include "stm32f10x_it.h" 
26 | 
27 | 
28 |  
29 | void NMI_Handler(void)
30 | {
31 | }
32 |  
33 | void HardFault_Handler(void)
34 | {
35 |   /* Go to infinite loop when Hard Fault exception occurs */
36 |   while (1)
37 |   {
38 |   }
39 | }
40 |  
41 | void MemManage_Handler(void)
42 | {
43 |   /* Go to infinite loop when Memory Manage exception occurs */
44 |   while (1)
45 |   {
46 |   }
47 | }
48 | 
49 |  
50 | void BusFault_Handler(void)
51 | {
52 |   /* Go to infinite loop when Bus Fault exception occurs */
53 |   while (1)
54 |   {
55 |   }
56 | }
57 |  
58 | void UsageFault_Handler(void)
59 | {
60 |   /* Go to infinite loop when Usage Fault exception occurs */
61 |   while (1)
62 |   {
63 |   }
64 | }
65 |  
66 | void SVC_Handler(void)
67 | {
68 | }
69 |  
70 | void DebugMon_Handler(void)
71 | {
72 | }
73 |  
74 | void PendSV_Handler(void)
75 | {
76 | }
77 |  
78 | void SysTick_Handler(void)
79 | {
80 | }
81 | 
82 | /******************************************************************************/
83 | /*                 STM32F10x Peripherals Interrupt Handlers                   */
84 | /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
85 | /*  available peripheral interrupt handler's name please refer to the startup */
86 | /*  file (startup_stm32f10x_xx.s).                                            */
87 | /******************************************************************************/
88 | 


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/USER/stm32f10x_conf.h:
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 1 | /**
 2 |   ******************************************************************************
 3 |   * @file    GPIO/IOToggle/stm32f10x_conf.h 
 4 |   * @author  MCD Application Team
 5 |   * @version V3.5.0
 6 |   * @date    08-April-2011
 7 |   * @brief   Library configuration file.
 8 |   ******************************************************************************
 9 |   * @attention
10 |   *
11 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 |   *
18 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
19 |   ******************************************************************************
20 |   */
21 | 
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_CONF_H
24 | #define __STM32F10x_CONF_H
25 | 
26 | /* Includes ------------------------------------------------------------------*/
27 | /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
28 | #include "stm32f10x_adc.h"
29 | #include "stm32f10x_bkp.h"
30 | #include "stm32f10x_can.h"
31 | #include "stm32f10x_cec.h"
32 | #include "stm32f10x_crc.h"
33 | #include "stm32f10x_dac.h"
34 | #include "stm32f10x_dbgmcu.h"
35 | #include "stm32f10x_dma.h"
36 | #include "stm32f10x_exti.h"
37 | #include "stm32f10x_flash.h"
38 | #include "stm32f10x_fsmc.h"
39 | #include "stm32f10x_gpio.h"
40 | #include "stm32f10x_i2c.h"
41 | #include "stm32f10x_iwdg.h"
42 | #include "stm32f10x_pwr.h"
43 | #include "stm32f10x_rcc.h"
44 | #include "stm32f10x_rtc.h"
45 | #include "stm32f10x_sdio.h"
46 | #include "stm32f10x_spi.h"
47 | #include "stm32f10x_tim.h"
48 | #include "stm32f10x_usart.h"
49 | #include "stm32f10x_wwdg.h"
50 | #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
51 | 
52 | /* Exported types ------------------------------------------------------------*/
53 | /* Exported constants --------------------------------------------------------*/
54 | /* Uncomment the line below to expanse the "assert_param" macro in the 
55 |    Standard Peripheral Library drivers code */
56 | /* #define USE_FULL_ASSERT    1 */
57 | 
58 | /* Exported macro ------------------------------------------------------------*/
59 | #ifdef  USE_FULL_ASSERT
60 | 
61 | /**
62 |   * @brief  The assert_param macro is used for function's parameters check.
63 |   * @param  expr: If expr is false, it calls assert_failed function which reports 
64 |   *         the name of the source file and the source line number of the call 
65 |   *         that failed. If expr is true, it returns no value.
66 |   * @retval None
67 |   */
68 |   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
69 | /* Exported functions ------------------------------------------------------- */
70 |   void assert_failed(uint8_t* file, uint32_t line);
71 | #else
72 |   #define assert_param(expr) ((void)0)
73 | #endif /* USE_FULL_ASSERT */
74 | 
75 | #endif /* __STM32F10x_CONF_H */
76 | 
77 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
78 | 


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/STM32F10x_FWLib/inc/stm32f10x_wwdg.h:
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  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_wwdg.h
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file contains all the functions prototypes for the WWDG firmware
  8 |   *          library.
  9 |   ******************************************************************************
 10 |   * @attention
 11 |   *
 12 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 13 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 14 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 15 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 16 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 17 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 18 |   *
 19 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 20 |   ******************************************************************************
 21 |   */
 22 | 
 23 | /* Define to prevent recursive inclusion -------------------------------------*/
 24 | #ifndef __STM32F10x_WWDG_H
 25 | #define __STM32F10x_WWDG_H
 26 | 
 27 | #ifdef __cplusplus
 28 |  extern "C" {
 29 | #endif
 30 | 
 31 | /* Includes ------------------------------------------------------------------*/
 32 | #include "stm32f10x.h"
 33 | 
 34 | /** @addtogroup STM32F10x_StdPeriph_Driver
 35 |   * @{
 36 |   */
 37 | 
 38 | /** @addtogroup WWDG
 39 |   * @{
 40 |   */ 
 41 | 
 42 | /** @defgroup WWDG_Exported_Types
 43 |   * @{
 44 |   */ 
 45 |   
 46 | /**
 47 |   * @}
 48 |   */ 
 49 | 
 50 | /** @defgroup WWDG_Exported_Constants
 51 |   * @{
 52 |   */ 
 53 |   
 54 | /** @defgroup WWDG_Prescaler 
 55 |   * @{
 56 |   */ 
 57 |   
 58 | #define WWDG_Prescaler_1    ((uint32_t)0x00000000)
 59 | #define WWDG_Prescaler_2    ((uint32_t)0x00000080)
 60 | #define WWDG_Prescaler_4    ((uint32_t)0x00000100)
 61 | #define WWDG_Prescaler_8    ((uint32_t)0x00000180)
 62 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
 63 |                                       ((PRESCALER) == WWDG_Prescaler_2) || \
 64 |                                       ((PRESCALER) == WWDG_Prescaler_4) || \
 65 |                                       ((PRESCALER) == WWDG_Prescaler_8))
 66 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
 67 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
 68 | 
 69 | /**
 70 |   * @}
 71 |   */ 
 72 | 
 73 | /**
 74 |   * @}
 75 |   */ 
 76 | 
 77 | /** @defgroup WWDG_Exported_Macros
 78 |   * @{
 79 |   */ 
 80 | /**
 81 |   * @}
 82 |   */ 
 83 | 
 84 | /** @defgroup WWDG_Exported_Functions
 85 |   * @{
 86 |   */ 
 87 |   
 88 | void WWDG_DeInit(void);
 89 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
 90 | void WWDG_SetWindowValue(uint8_t WindowValue);
 91 | void WWDG_EnableIT(void);
 92 | void WWDG_SetCounter(uint8_t Counter);
 93 | void WWDG_Enable(uint8_t Counter);
 94 | FlagStatus WWDG_GetFlagStatus(void);
 95 | void WWDG_ClearFlag(void);
 96 | 
 97 | #ifdef __cplusplus
 98 | }
 99 | #endif
100 | 
101 | #endif /* __STM32F10x_WWDG_H */
102 | 
103 | /**
104 |   * @}
105 |   */ 
106 | 
107 | /**
108 |   * @}
109 |   */ 
110 | 
111 | /**
112 |   * @}
113 |   */ 
114 | 
115 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
116 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/stm32f10x_crc.c:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_crc.c
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file provides all the CRC firmware functions.
  8 |   ******************************************************************************
  9 |   * @attention
 10 |   *
 11 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 12 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 13 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 14 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 15 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 16 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 17 |   *
 18 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 19 |   ******************************************************************************
 20 |   */
 21 | 
 22 | /* Includes ------------------------------------------------------------------*/
 23 | #include "stm32f10x_crc.h"
 24 | 
 25 | /** @addtogroup STM32F10x_StdPeriph_Driver
 26 |   * @{
 27 |   */
 28 | 
 29 | /** @defgroup CRC 
 30 |   * @brief CRC driver modules
 31 |   * @{
 32 |   */
 33 | 
 34 | /** @defgroup CRC_Private_TypesDefinitions
 35 |   * @{
 36 |   */
 37 | 
 38 | /**
 39 |   * @}
 40 |   */
 41 | 
 42 | /** @defgroup CRC_Private_Defines
 43 |   * @{
 44 |   */
 45 | 
 46 | /**
 47 |   * @}
 48 |   */
 49 | 
 50 | /** @defgroup CRC_Private_Macros
 51 |   * @{
 52 |   */
 53 | 
 54 | /**
 55 |   * @}
 56 |   */
 57 | 
 58 | /** @defgroup CRC_Private_Variables
 59 |   * @{
 60 |   */
 61 | 
 62 | /**
 63 |   * @}
 64 |   */
 65 | 
 66 | /** @defgroup CRC_Private_FunctionPrototypes
 67 |   * @{
 68 |   */
 69 | 
 70 | /**
 71 |   * @}
 72 |   */
 73 | 
 74 | /** @defgroup CRC_Private_Functions
 75 |   * @{
 76 |   */
 77 | 
 78 | /**
 79 |   * @brief  Resets the CRC Data register (DR).
 80 |   * @param  None
 81 |   * @retval None
 82 |   */
 83 | void CRC_ResetDR(void)
 84 | {
 85 |   /* Reset CRC generator */
 86 |   CRC->CR = CRC_CR_RESET;
 87 | }
 88 | 
 89 | /**
 90 |   * @brief  Computes the 32-bit CRC of a given data word(32-bit).
 91 |   * @param  Data: data word(32-bit) to compute its CRC
 92 |   * @retval 32-bit CRC
 93 |   */
 94 | uint32_t CRC_CalcCRC(uint32_t Data)
 95 | {
 96 |   CRC->DR = Data;
 97 |   
 98 |   return (CRC->DR);
 99 | }
100 | 
101 | /**
102 |   * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
103 |   * @param  pBuffer: pointer to the buffer containing the data to be computed
104 |   * @param  BufferLength: length of the buffer to be computed					
105 |   * @retval 32-bit CRC
106 |   */
107 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
108 | {
109 |   uint32_t index = 0;
110 |   
111 |   for(index = 0; index < BufferLength; index++)
112 |   {
113 |     CRC->DR = pBuffer[index];
114 |   }
115 |   return (CRC->DR);
116 | }
117 | 
118 | /**
119 |   * @brief  Returns the current CRC value.
120 |   * @param  None
121 |   * @retval 32-bit CRC
122 |   */
123 | uint32_t CRC_GetCRC(void)
124 | {
125 |   return (CRC->DR);
126 | }
127 | 
128 | /**
129 |   * @brief  Stores a 8-bit data in the Independent Data(ID) register.
130 |   * @param  IDValue: 8-bit value to be stored in the ID register 					
131 |   * @retval None
132 |   */
133 | void CRC_SetIDRegister(uint8_t IDValue)
134 | {
135 |   CRC->IDR = IDValue;
136 | }
137 | 
138 | /**
139 |   * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
140 |   * @param  None
141 |   * @retval 8-bit value of the ID register 
142 |   */
143 | uint8_t CRC_GetIDRegister(void)
144 | {
145 |   return (CRC->IDR);
146 | }
147 | 
148 | /**
149 |   * @}
150 |   */
151 | 
152 | /**
153 |   * @}
154 |   */
155 | 
156 | /**
157 |   * @}
158 |   */
159 | 
160 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
161 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_dbgmcu.h:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_dbgmcu.h
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file contains all the functions prototypes for the DBGMCU 
  8 |   *          firmware library.
  9 |   ******************************************************************************
 10 |   * @attention
 11 |   *
 12 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 13 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 14 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 15 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 16 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 17 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 18 |   *
 19 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 20 |   ******************************************************************************
 21 |   */
 22 | 
 23 | /* Define to prevent recursive inclusion -------------------------------------*/
 24 | #ifndef __STM32F10x_DBGMCU_H
 25 | #define __STM32F10x_DBGMCU_H
 26 | 
 27 | #ifdef __cplusplus
 28 |  extern "C" {
 29 | #endif
 30 | 
 31 | /* Includes ------------------------------------------------------------------*/
 32 | #include "stm32f10x.h"
 33 | 
 34 | /** @addtogroup STM32F10x_StdPeriph_Driver
 35 |   * @{
 36 |   */
 37 | 
 38 | /** @addtogroup DBGMCU
 39 |   * @{
 40 |   */
 41 | 
 42 | /** @defgroup DBGMCU_Exported_Types
 43 |   * @{
 44 |   */
 45 | 
 46 | /**
 47 |   * @}
 48 |   */
 49 | 
 50 | /** @defgroup DBGMCU_Exported_Constants
 51 |   * @{
 52 |   */
 53 | 
 54 | #define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
 55 | #define DBGMCU_STOP                  ((uint32_t)0x00000002)
 56 | #define DBGMCU_STANDBY               ((uint32_t)0x00000004)
 57 | #define DBGMCU_IWDG_STOP             ((uint32_t)0x00000100)
 58 | #define DBGMCU_WWDG_STOP             ((uint32_t)0x00000200)
 59 | #define DBGMCU_TIM1_STOP             ((uint32_t)0x00000400)
 60 | #define DBGMCU_TIM2_STOP             ((uint32_t)0x00000800)
 61 | #define DBGMCU_TIM3_STOP             ((uint32_t)0x00001000)
 62 | #define DBGMCU_TIM4_STOP             ((uint32_t)0x00002000)
 63 | #define DBGMCU_CAN1_STOP             ((uint32_t)0x00004000)
 64 | #define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)
 65 | #define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)
 66 | #define DBGMCU_TIM8_STOP             ((uint32_t)0x00020000)
 67 | #define DBGMCU_TIM5_STOP             ((uint32_t)0x00040000)
 68 | #define DBGMCU_TIM6_STOP             ((uint32_t)0x00080000)
 69 | #define DBGMCU_TIM7_STOP             ((uint32_t)0x00100000)
 70 | #define DBGMCU_CAN2_STOP             ((uint32_t)0x00200000)
 71 | #define DBGMCU_TIM15_STOP            ((uint32_t)0x00400000)
 72 | #define DBGMCU_TIM16_STOP            ((uint32_t)0x00800000)
 73 | #define DBGMCU_TIM17_STOP            ((uint32_t)0x01000000)
 74 | #define DBGMCU_TIM12_STOP            ((uint32_t)0x02000000)
 75 | #define DBGMCU_TIM13_STOP            ((uint32_t)0x04000000)
 76 | #define DBGMCU_TIM14_STOP            ((uint32_t)0x08000000)
 77 | #define DBGMCU_TIM9_STOP             ((uint32_t)0x10000000)
 78 | #define DBGMCU_TIM10_STOP            ((uint32_t)0x20000000)
 79 | #define DBGMCU_TIM11_STOP            ((uint32_t)0x40000000)
 80 |                                               
 81 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
 82 | /**
 83 |   * @}
 84 |   */ 
 85 | 
 86 | /** @defgroup DBGMCU_Exported_Macros
 87 |   * @{
 88 |   */
 89 | 
 90 | /**
 91 |   * @}
 92 |   */
 93 | 
 94 | /** @defgroup DBGMCU_Exported_Functions
 95 |   * @{
 96 |   */
 97 | 
 98 | uint32_t DBGMCU_GetREVID(void);
 99 | uint32_t DBGMCU_GetDEVID(void);
100 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
101 | 
102 | #ifdef __cplusplus
103 | }
104 | #endif
105 | 
106 | #endif /* __STM32F10x_DBGMCU_H */
107 | /**
108 |   * @}
109 |   */
110 | 
111 | /**
112 |   * @}
113 |   */
114 | 
115 | /**
116 |   * @}
117 |   */
118 | 
119 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
120 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_iwdg.h:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_iwdg.h
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file contains all the functions prototypes for the IWDG 
  8 |   *          firmware library.
  9 |   ******************************************************************************
 10 |   * @attention
 11 |   *
 12 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 13 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 14 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 15 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 16 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 17 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 18 |   *
 19 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 20 |   ******************************************************************************
 21 |   */
 22 | 
 23 | /* Define to prevent recursive inclusion -------------------------------------*/
 24 | #ifndef __STM32F10x_IWDG_H
 25 | #define __STM32F10x_IWDG_H
 26 | 
 27 | #ifdef __cplusplus
 28 |  extern "C" {
 29 | #endif
 30 | 
 31 | /* Includes ------------------------------------------------------------------*/
 32 | #include "stm32f10x.h"
 33 | 
 34 | /** @addtogroup STM32F10x_StdPeriph_Driver
 35 |   * @{
 36 |   */
 37 | 
 38 | /** @addtogroup IWDG
 39 |   * @{
 40 |   */
 41 | 
 42 | /** @defgroup IWDG_Exported_Types
 43 |   * @{
 44 |   */
 45 | 
 46 | /**
 47 |   * @}
 48 |   */
 49 | 
 50 | /** @defgroup IWDG_Exported_Constants
 51 |   * @{
 52 |   */
 53 | 
 54 | /** @defgroup IWDG_WriteAccess
 55 |   * @{
 56 |   */
 57 | 
 58 | #define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
 59 | #define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
 60 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
 61 |                                       ((ACCESS) == IWDG_WriteAccess_Disable))
 62 | /**
 63 |   * @}
 64 |   */
 65 | 
 66 | /** @defgroup IWDG_prescaler 
 67 |   * @{
 68 |   */
 69 | 
 70 | #define IWDG_Prescaler_4            ((uint8_t)0x00)
 71 | #define IWDG_Prescaler_8            ((uint8_t)0x01)
 72 | #define IWDG_Prescaler_16           ((uint8_t)0x02)
 73 | #define IWDG_Prescaler_32           ((uint8_t)0x03)
 74 | #define IWDG_Prescaler_64           ((uint8_t)0x04)
 75 | #define IWDG_Prescaler_128          ((uint8_t)0x05)
 76 | #define IWDG_Prescaler_256          ((uint8_t)0x06)
 77 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
 78 |                                       ((PRESCALER) == IWDG_Prescaler_8)  || \
 79 |                                       ((PRESCALER) == IWDG_Prescaler_16) || \
 80 |                                       ((PRESCALER) == IWDG_Prescaler_32) || \
 81 |                                       ((PRESCALER) == IWDG_Prescaler_64) || \
 82 |                                       ((PRESCALER) == IWDG_Prescaler_128)|| \
 83 |                                       ((PRESCALER) == IWDG_Prescaler_256))
 84 | /**
 85 |   * @}
 86 |   */
 87 | 
 88 | /** @defgroup IWDG_Flag 
 89 |   * @{
 90 |   */
 91 | 
 92 | #define IWDG_FLAG_PVU               ((uint16_t)0x0001)
 93 | #define IWDG_FLAG_RVU               ((uint16_t)0x0002)
 94 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
 95 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
 96 | /**
 97 |   * @}
 98 |   */
 99 | 
100 | /**
101 |   * @}
102 |   */
103 | 
104 | /** @defgroup IWDG_Exported_Macros
105 |   * @{
106 |   */
107 | 
108 | /**
109 |   * @}
110 |   */
111 | 
112 | /** @defgroup IWDG_Exported_Functions
113 |   * @{
114 |   */
115 | 
116 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
117 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
118 | void IWDG_SetReload(uint16_t Reload);
119 | void IWDG_ReloadCounter(void);
120 | void IWDG_Enable(void);
121 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
122 | 
123 | #ifdef __cplusplus
124 | }
125 | #endif
126 | 
127 | #endif /* __STM32F10x_IWDG_H */
128 | /**
129 |   * @}
130 |   */
131 | 
132 | /**
133 |   * @}
134 |   */
135 | 
136 | /**
137 |   * @}
138 |   */
139 | 
140 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
141 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_rtc.h:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_rtc.h
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file contains all the functions prototypes for the RTC firmware 
  8 |   *          library.
  9 |   ******************************************************************************
 10 |   * @attention
 11 |   *
 12 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 13 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 14 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 15 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 16 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 17 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 18 |   *
 19 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 20 |   ******************************************************************************
 21 |   */
 22 | 
 23 | /* Define to prevent recursive inclusion -------------------------------------*/
 24 | #ifndef __STM32F10x_RTC_H
 25 | #define __STM32F10x_RTC_H
 26 | 
 27 | #ifdef __cplusplus
 28 |  extern "C" {
 29 | #endif
 30 | 
 31 | /* Includes ------------------------------------------------------------------*/
 32 | #include "stm32f10x.h"
 33 | 
 34 | /** @addtogroup STM32F10x_StdPeriph_Driver
 35 |   * @{
 36 |   */
 37 | 
 38 | /** @addtogroup RTC
 39 |   * @{
 40 |   */ 
 41 | 
 42 | /** @defgroup RTC_Exported_Types
 43 |   * @{
 44 |   */ 
 45 | 
 46 | /**
 47 |   * @}
 48 |   */ 
 49 | 
 50 | /** @defgroup RTC_Exported_Constants
 51 |   * @{
 52 |   */
 53 | 
 54 | /** @defgroup RTC_interrupts_define 
 55 |   * @{
 56 |   */
 57 | 
 58 | #define RTC_IT_OW            ((uint16_t)0x0004)  /*!< Overflow interrupt */
 59 | #define RTC_IT_ALR           ((uint16_t)0x0002)  /*!< Alarm interrupt */
 60 | #define RTC_IT_SEC           ((uint16_t)0x0001)  /*!< Second interrupt */
 61 | #define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
 62 | #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
 63 |                            ((IT) == RTC_IT_SEC))
 64 | /**
 65 |   * @}
 66 |   */ 
 67 | 
 68 | /** @defgroup RTC_interrupts_flags 
 69 |   * @{
 70 |   */
 71 | 
 72 | #define RTC_FLAG_RTOFF       ((uint16_t)0x0020)  /*!< RTC Operation OFF flag */
 73 | #define RTC_FLAG_RSF         ((uint16_t)0x0008)  /*!< Registers Synchronized flag */
 74 | #define RTC_FLAG_OW          ((uint16_t)0x0004)  /*!< Overflow flag */
 75 | #define RTC_FLAG_ALR         ((uint16_t)0x0002)  /*!< Alarm flag */
 76 | #define RTC_FLAG_SEC         ((uint16_t)0x0001)  /*!< Second flag */
 77 | #define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
 78 | #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
 79 |                                ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
 80 |                                ((FLAG) == RTC_FLAG_SEC))
 81 | #define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
 82 | 
 83 | /**
 84 |   * @}
 85 |   */
 86 | 
 87 | /**
 88 |   * @}
 89 |   */
 90 | 
 91 | /** @defgroup RTC_Exported_Macros
 92 |   * @{
 93 |   */
 94 | 
 95 | /**
 96 |   * @}
 97 |   */
 98 | 
 99 | /** @defgroup RTC_Exported_Functions
100 |   * @{
101 |   */
102 | 
103 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
104 | void RTC_EnterConfigMode(void);
105 | void RTC_ExitConfigMode(void);
106 | uint32_t  RTC_GetCounter(void);
107 | void RTC_SetCounter(uint32_t CounterValue);
108 | void RTC_SetPrescaler(uint32_t PrescalerValue);
109 | void RTC_SetAlarm(uint32_t AlarmValue);
110 | uint32_t  RTC_GetDivider(void);
111 | void RTC_WaitForLastTask(void);
112 | void RTC_WaitForSynchro(void);
113 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
114 | void RTC_ClearFlag(uint16_t RTC_FLAG);
115 | ITStatus RTC_GetITStatus(uint16_t RTC_IT);
116 | void RTC_ClearITPendingBit(uint16_t RTC_IT);
117 | 
118 | #ifdef __cplusplus
119 | }
120 | #endif
121 | 
122 | #endif /* __STM32F10x_RTC_H */
123 | /**
124 |   * @}
125 |   */
126 | 
127 | /**
128 |   * @}
129 |   */
130 | 
131 | /**
132 |   * @}
133 |   */
134 | 
135 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
136 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_pwr.h:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_pwr.h
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file contains all the functions prototypes for the PWR firmware 
  8 |   *          library.
  9 |   ******************************************************************************
 10 |   * @attention
 11 |   *
 12 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 13 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 14 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 15 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 16 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 17 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 18 |   *
 19 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 20 |   ******************************************************************************
 21 |   */
 22 | 
 23 | /* Define to prevent recursive inclusion -------------------------------------*/
 24 | #ifndef __STM32F10x_PWR_H
 25 | #define __STM32F10x_PWR_H
 26 | 
 27 | #ifdef __cplusplus
 28 |  extern "C" {
 29 | #endif
 30 | 
 31 | /* Includes ------------------------------------------------------------------*/
 32 | #include "stm32f10x.h"
 33 | 
 34 | /** @addtogroup STM32F10x_StdPeriph_Driver
 35 |   * @{
 36 |   */
 37 | 
 38 | /** @addtogroup PWR
 39 |   * @{
 40 |   */ 
 41 | 
 42 | /** @defgroup PWR_Exported_Types
 43 |   * @{
 44 |   */ 
 45 | 
 46 | /**
 47 |   * @}
 48 |   */ 
 49 | 
 50 | /** @defgroup PWR_Exported_Constants
 51 |   * @{
 52 |   */ 
 53 | 
 54 | /** @defgroup PVD_detection_level 
 55 |   * @{
 56 |   */ 
 57 | 
 58 | #define PWR_PVDLevel_2V2          ((uint32_t)0x00000000)
 59 | #define PWR_PVDLevel_2V3          ((uint32_t)0x00000020)
 60 | #define PWR_PVDLevel_2V4          ((uint32_t)0x00000040)
 61 | #define PWR_PVDLevel_2V5          ((uint32_t)0x00000060)
 62 | #define PWR_PVDLevel_2V6          ((uint32_t)0x00000080)
 63 | #define PWR_PVDLevel_2V7          ((uint32_t)0x000000A0)
 64 | #define PWR_PVDLevel_2V8          ((uint32_t)0x000000C0)
 65 | #define PWR_PVDLevel_2V9          ((uint32_t)0x000000E0)
 66 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
 67 |                                  ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
 68 |                                  ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
 69 |                                  ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
 70 | /**
 71 |   * @}
 72 |   */
 73 | 
 74 | /** @defgroup Regulator_state_is_STOP_mode 
 75 |   * @{
 76 |   */
 77 | 
 78 | #define PWR_Regulator_ON          ((uint32_t)0x00000000)
 79 | #define PWR_Regulator_LowPower    ((uint32_t)0x00000001)
 80 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
 81 |                                      ((REGULATOR) == PWR_Regulator_LowPower))
 82 | /**
 83 |   * @}
 84 |   */
 85 | 
 86 | /** @defgroup STOP_mode_entry 
 87 |   * @{
 88 |   */
 89 | 
 90 | #define PWR_STOPEntry_WFI         ((uint8_t)0x01)
 91 | #define PWR_STOPEntry_WFE         ((uint8_t)0x02)
 92 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
 93 |  
 94 | /**
 95 |   * @}
 96 |   */
 97 | 
 98 | /** @defgroup PWR_Flag 
 99 |   * @{
100 |   */
101 | 
102 | #define PWR_FLAG_WU               ((uint32_t)0x00000001)
103 | #define PWR_FLAG_SB               ((uint32_t)0x00000002)
104 | #define PWR_FLAG_PVDO             ((uint32_t)0x00000004)
105 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
106 |                                ((FLAG) == PWR_FLAG_PVDO))
107 | 
108 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
109 | /**
110 |   * @}
111 |   */
112 | 
113 | /**
114 |   * @}
115 |   */
116 | 
117 | /** @defgroup PWR_Exported_Macros
118 |   * @{
119 |   */
120 | 
121 | /**
122 |   * @}
123 |   */
124 | 
125 | /** @defgroup PWR_Exported_Functions
126 |   * @{
127 |   */
128 | 
129 | void PWR_DeInit(void);
130 | void PWR_BackupAccessCmd(FunctionalState NewState);
131 | void PWR_PVDCmd(FunctionalState NewState);
132 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
133 | void PWR_WakeUpPinCmd(FunctionalState NewState);
134 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
135 | void PWR_EnterSTANDBYMode(void);
136 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
137 | void PWR_ClearFlag(uint32_t PWR_FLAG);
138 | 
139 | #ifdef __cplusplus
140 | }
141 | #endif
142 | 
143 | #endif /* __STM32F10x_PWR_H */
144 | /**
145 |   * @}
146 |   */
147 | 
148 | /**
149 |   * @}
150 |   */
151 | 
152 | /**
153 |   * @}
154 |   */
155 | 
156 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
157 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/stm32f10x_iwdg.c:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_iwdg.c
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file provides all the IWDG firmware functions.
  8 |   ******************************************************************************
  9 |   * @attention
 10 |   *
 11 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 12 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 13 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 14 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 15 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 16 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 17 |   *
 18 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 19 |   ******************************************************************************
 20 |   */
 21 | 
 22 | /* Includes ------------------------------------------------------------------*/
 23 | #include "stm32f10x_iwdg.h"
 24 | 
 25 | /** @addtogroup STM32F10x_StdPeriph_Driver
 26 |   * @{
 27 |   */
 28 | 
 29 | /** @defgroup IWDG 
 30 |   * @brief IWDG driver modules
 31 |   * @{
 32 |   */ 
 33 | 
 34 | /** @defgroup IWDG_Private_TypesDefinitions
 35 |   * @{
 36 |   */
 37 | 
 38 | /**
 39 |   * @}
 40 |   */
 41 | 
 42 | /** @defgroup IWDG_Private_Defines
 43 |   * @{
 44 |   */ 
 45 | 
 46 | /* ---------------------- IWDG registers bit mask ----------------------------*/
 47 | 
 48 | /* KR register bit mask */
 49 | #define KR_KEY_Reload    ((uint16_t)0xAAAA)
 50 | #define KR_KEY_Enable    ((uint16_t)0xCCCC)
 51 | 
 52 | /**
 53 |   * @}
 54 |   */ 
 55 | 
 56 | /** @defgroup IWDG_Private_Macros
 57 |   * @{
 58 |   */
 59 | 
 60 | /**
 61 |   * @}
 62 |   */
 63 | 
 64 | /** @defgroup IWDG_Private_Variables
 65 |   * @{
 66 |   */
 67 | 
 68 | /**
 69 |   * @}
 70 |   */
 71 | 
 72 | /** @defgroup IWDG_Private_FunctionPrototypes
 73 |   * @{
 74 |   */
 75 | 
 76 | /**
 77 |   * @}
 78 |   */
 79 | 
 80 | /** @defgroup IWDG_Private_Functions
 81 |   * @{
 82 |   */
 83 | 
 84 | /**
 85 |   * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
 86 |   * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
 87 |   *   This parameter can be one of the following values:
 88 |   *     @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
 89 |   *     @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
 90 |   * @retval None
 91 |   */
 92 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
 93 | {
 94 |   /* Check the parameters */
 95 |   assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
 96 |   IWDG->KR = IWDG_WriteAccess;
 97 | }
 98 | 
 99 | /**
100 |   * @brief  Sets IWDG Prescaler value.
101 |   * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
102 |   *   This parameter can be one of the following values:
103 |   *     @arg IWDG_Prescaler_4: IWDG prescaler set to 4
104 |   *     @arg IWDG_Prescaler_8: IWDG prescaler set to 8
105 |   *     @arg IWDG_Prescaler_16: IWDG prescaler set to 16
106 |   *     @arg IWDG_Prescaler_32: IWDG prescaler set to 32
107 |   *     @arg IWDG_Prescaler_64: IWDG prescaler set to 64
108 |   *     @arg IWDG_Prescaler_128: IWDG prescaler set to 128
109 |   *     @arg IWDG_Prescaler_256: IWDG prescaler set to 256
110 |   * @retval None
111 |   */
112 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
113 | {
114 |   /* Check the parameters */
115 |   assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
116 |   IWDG->PR = IWDG_Prescaler;
117 | }
118 | 
119 | /**
120 |   * @brief  Sets IWDG Reload value.
121 |   * @param  Reload: specifies the IWDG Reload value.
122 |   *   This parameter must be a number between 0 and 0x0FFF.
123 |   * @retval None
124 |   */
125 | void IWDG_SetReload(uint16_t Reload)
126 | {
127 |   /* Check the parameters */
128 |   assert_param(IS_IWDG_RELOAD(Reload));
129 |   IWDG->RLR = Reload;
130 | }
131 | 
132 | /**
133 |   * @brief  Reloads IWDG counter with value defined in the reload register
134 |   *   (write access to IWDG_PR and IWDG_RLR registers disabled).
135 |   * @param  None
136 |   * @retval None
137 |   */
138 | void IWDG_ReloadCounter(void)
139 | {
140 |   IWDG->KR = KR_KEY_Reload;
141 | }
142 | 
143 | /**
144 |   * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
145 |   * @param  None
146 |   * @retval None
147 |   */
148 | void IWDG_Enable(void)
149 | {
150 |   IWDG->KR = KR_KEY_Enable;
151 | }
152 | 
153 | /**
154 |   * @brief  Checks whether the specified IWDG flag is set or not.
155 |   * @param  IWDG_FLAG: specifies the flag to check.
156 |   *   This parameter can be one of the following values:
157 |   *     @arg IWDG_FLAG_PVU: Prescaler Value Update on going
158 |   *     @arg IWDG_FLAG_RVU: Reload Value Update on going
159 |   * @retval The new state of IWDG_FLAG (SET or RESET).
160 |   */
161 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
162 | {
163 |   FlagStatus bitstatus = RESET;
164 |   /* Check the parameters */
165 |   assert_param(IS_IWDG_FLAG(IWDG_FLAG));
166 |   if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
167 |   {
168 |     bitstatus = SET;
169 |   }
170 |   else
171 |   {
172 |     bitstatus = RESET;
173 |   }
174 |   /* Return the flag status */
175 |   return bitstatus;
176 | }
177 | 
178 | /**
179 |   * @}
180 |   */
181 | 
182 | /**
183 |   * @}
184 |   */
185 | 
186 | /**
187 |   * @}
188 |   */
189 | 
190 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
191 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/stm32f10x_dbgmcu.c:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_dbgmcu.c
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file provides all the DBGMCU firmware functions.
  8 |   ******************************************************************************
  9 |   * @attention
 10 |   *
 11 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 12 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 13 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 14 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 15 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 16 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 17 |   *
 18 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 19 |   ******************************************************************************
 20 |   */
 21 | 
 22 | /* Includes ------------------------------------------------------------------*/
 23 | #include "stm32f10x_dbgmcu.h"
 24 | 
 25 | /** @addtogroup STM32F10x_StdPeriph_Driver
 26 |   * @{
 27 |   */
 28 | 
 29 | /** @defgroup DBGMCU 
 30 |   * @brief DBGMCU driver modules
 31 |   * @{
 32 |   */ 
 33 | 
 34 | /** @defgroup DBGMCU_Private_TypesDefinitions
 35 |   * @{
 36 |   */
 37 | 
 38 | /**
 39 |   * @}
 40 |   */
 41 | 
 42 | /** @defgroup DBGMCU_Private_Defines
 43 |   * @{
 44 |   */
 45 | 
 46 | #define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
 47 | /**
 48 |   * @}
 49 |   */
 50 | 
 51 | /** @defgroup DBGMCU_Private_Macros
 52 |   * @{
 53 |   */
 54 | 
 55 | /**
 56 |   * @}
 57 |   */
 58 | 
 59 | /** @defgroup DBGMCU_Private_Variables
 60 |   * @{
 61 |   */
 62 | 
 63 | /**
 64 |   * @}
 65 |   */
 66 | 
 67 | /** @defgroup DBGMCU_Private_FunctionPrototypes
 68 |   * @{
 69 |   */
 70 | 
 71 | /**
 72 |   * @}
 73 |   */
 74 | 
 75 | /** @defgroup DBGMCU_Private_Functions
 76 |   * @{
 77 |   */
 78 | 
 79 | /**
 80 |   * @brief  Returns the device revision identifier.
 81 |   * @param  None
 82 |   * @retval Device revision identifier
 83 |   */
 84 | uint32_t DBGMCU_GetREVID(void)
 85 | {
 86 |    return(DBGMCU->IDCODE >> 16);
 87 | }
 88 | 
 89 | /**
 90 |   * @brief  Returns the device identifier.
 91 |   * @param  None
 92 |   * @retval Device identifier
 93 |   */
 94 | uint32_t DBGMCU_GetDEVID(void)
 95 | {
 96 |    return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
 97 | }
 98 | 
 99 | /**
100 |   * @brief  Configures the specified peripheral and low power mode behavior
101 |   *   when the MCU under Debug mode.
102 |   * @param  DBGMCU_Periph: specifies the peripheral and low power mode.
103 |   *   This parameter can be any combination of the following values:
104 |   *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode              
105 |   *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode               
106 |   *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode            
107 |   *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted          
108 |   *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted          
109 |   *     @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted          
110 |   *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted          
111 |   *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted          
112 |   *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted          
113 |   *     @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted           
114 |   *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
115 |   *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
116 |   *     @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted          
117 |   *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted          
118 |   *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted          
119 |   *     @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
120 |   *     @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted 
121 |   *     @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
122 |   *     @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
123 |   *     @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted                
124 |   *     @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
125 |   *     @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
126 |   *     @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
127 |   *     @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
128 |   *     @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
129 |   *     @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
130 |   * @param  NewState: new state of the specified peripheral in Debug mode.
131 |   *   This parameter can be: ENABLE or DISABLE.
132 |   * @retval None
133 |   */
134 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
135 | {
136 |   /* Check the parameters */
137 |   assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
138 |   assert_param(IS_FUNCTIONAL_STATE(NewState));
139 | 
140 |   if (NewState != DISABLE)
141 |   {
142 |     DBGMCU->CR |= DBGMCU_Periph;
143 |   }
144 |   else
145 |   {
146 |     DBGMCU->CR &= ~DBGMCU_Periph;
147 |   }
148 | }
149 | 
150 | /**
151 |   * @}
152 |   */
153 | 
154 | /**
155 |   * @}
156 |   */
157 | 
158 | /**
159 |   * @}
160 |   */
161 | 
162 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
163 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/stm32f10x_wwdg.c:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_wwdg.c
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file provides all the WWDG firmware functions.
  8 |   ******************************************************************************
  9 |   * @attention
 10 |   *
 11 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 12 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 13 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 14 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 15 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 16 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 17 |   *
 18 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 19 |   ******************************************************************************
 20 |   */
 21 | 
 22 | /* Includes ------------------------------------------------------------------*/
 23 | #include "stm32f10x_wwdg.h"
 24 | #include "stm32f10x_rcc.h"
 25 | 
 26 | /** @addtogroup STM32F10x_StdPeriph_Driver
 27 |   * @{
 28 |   */
 29 | 
 30 | /** @defgroup WWDG 
 31 |   * @brief WWDG driver modules
 32 |   * @{
 33 |   */
 34 | 
 35 | /** @defgroup WWDG_Private_TypesDefinitions
 36 |   * @{
 37 |   */
 38 | 
 39 | /**
 40 |   * @}
 41 |   */
 42 | 
 43 | /** @defgroup WWDG_Private_Defines
 44 |   * @{
 45 |   */
 46 | 
 47 | /* ----------- WWDG registers bit address in the alias region ----------- */
 48 | #define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
 49 | 
 50 | /* Alias word address of EWI bit */
 51 | #define CFR_OFFSET        (WWDG_OFFSET + 0x04)
 52 | #define EWI_BitNumber     0x09
 53 | #define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
 54 | 
 55 | /* --------------------- WWDG registers bit mask ------------------------ */
 56 | 
 57 | /* CR register bit mask */
 58 | #define CR_WDGA_Set       ((uint32_t)0x00000080)
 59 | 
 60 | /* CFR register bit mask */
 61 | #define CFR_WDGTB_Mask    ((uint32_t)0xFFFFFE7F)
 62 | #define CFR_W_Mask        ((uint32_t)0xFFFFFF80)
 63 | #define BIT_Mask          ((uint8_t)0x7F)
 64 | 
 65 | /**
 66 |   * @}
 67 |   */
 68 | 
 69 | /** @defgroup WWDG_Private_Macros
 70 |   * @{
 71 |   */
 72 | 
 73 | /**
 74 |   * @}
 75 |   */
 76 | 
 77 | /** @defgroup WWDG_Private_Variables
 78 |   * @{
 79 |   */
 80 | 
 81 | /**
 82 |   * @}
 83 |   */
 84 | 
 85 | /** @defgroup WWDG_Private_FunctionPrototypes
 86 |   * @{
 87 |   */
 88 | 
 89 | /**
 90 |   * @}
 91 |   */
 92 | 
 93 | /** @defgroup WWDG_Private_Functions
 94 |   * @{
 95 |   */
 96 | 
 97 | /**
 98 |   * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
 99 |   * @param  None
100 |   * @retval None
101 |   */
102 | void WWDG_DeInit(void)
103 | {
104 |   RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
105 |   RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
106 | }
107 | 
108 | /**
109 |   * @brief  Sets the WWDG Prescaler.
110 |   * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
111 |   *   This parameter can be one of the following values:
112 |   *     @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
113 |   *     @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
114 |   *     @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
115 |   *     @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
116 |   * @retval None
117 |   */
118 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
119 | {
120 |   uint32_t tmpreg = 0;
121 |   /* Check the parameters */
122 |   assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
123 |   /* Clear WDGTB[1:0] bits */
124 |   tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
125 |   /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
126 |   tmpreg |= WWDG_Prescaler;
127 |   /* Store the new value */
128 |   WWDG->CFR = tmpreg;
129 | }
130 | 
131 | /**
132 |   * @brief  Sets the WWDG window value.
133 |   * @param  WindowValue: specifies the window value to be compared to the downcounter.
134 |   *   This parameter value must be lower than 0x80.
135 |   * @retval None
136 |   */
137 | void WWDG_SetWindowValue(uint8_t WindowValue)
138 | {
139 |   __IO uint32_t tmpreg = 0;
140 | 
141 |   /* Check the parameters */
142 |   assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
143 |   /* Clear W[6:0] bits */
144 | 
145 |   tmpreg = WWDG->CFR & CFR_W_Mask;
146 | 
147 |   /* Set W[6:0] bits according to WindowValue value */
148 |   tmpreg |= WindowValue & (uint32_t) BIT_Mask;
149 | 
150 |   /* Store the new value */
151 |   WWDG->CFR = tmpreg;
152 | }
153 | 
154 | /**
155 |   * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
156 |   * @param  None
157 |   * @retval None
158 |   */
159 | void WWDG_EnableIT(void)
160 | {
161 |   *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
162 | }
163 | 
164 | /**
165 |   * @brief  Sets the WWDG counter value.
166 |   * @param  Counter: specifies the watchdog counter value.
167 |   *   This parameter must be a number between 0x40 and 0x7F.
168 |   * @retval None
169 |   */
170 | void WWDG_SetCounter(uint8_t Counter)
171 | {
172 |   /* Check the parameters */
173 |   assert_param(IS_WWDG_COUNTER(Counter));
174 |   /* Write to T[6:0] bits to configure the counter value, no need to do
175 |      a read-modify-write; writing a 0 to WDGA bit does nothing */
176 |   WWDG->CR = Counter & BIT_Mask;
177 | }
178 | 
179 | /**
180 |   * @brief  Enables WWDG and load the counter value.                  
181 |   * @param  Counter: specifies the watchdog counter value.
182 |   *   This parameter must be a number between 0x40 and 0x7F.
183 |   * @retval None
184 |   */
185 | void WWDG_Enable(uint8_t Counter)
186 | {
187 |   /* Check the parameters */
188 |   assert_param(IS_WWDG_COUNTER(Counter));
189 |   WWDG->CR = CR_WDGA_Set | Counter;
190 | }
191 | 
192 | /**
193 |   * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
194 |   * @param  None
195 |   * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
196 |   */
197 | FlagStatus WWDG_GetFlagStatus(void)
198 | {
199 |   return (FlagStatus)(WWDG->SR);
200 | }
201 | 
202 | /**
203 |   * @brief  Clears Early Wakeup interrupt flag.
204 |   * @param  None
205 |   * @retval None
206 |   */
207 | void WWDG_ClearFlag(void)
208 | {
209 |   WWDG->SR = (uint32_t)RESET;
210 | }
211 | 
212 | /**
213 |   * @}
214 |   */
215 | 
216 | /**
217 |   * @}
218 |   */
219 | 
220 | /**
221 |   * @}
222 |   */
223 | 
224 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
225 | 


--------------------------------------------------------------------------------
/USER/DebugConfig/LED_STM32F103C8.dbgconf:
--------------------------------------------------------------------------------
 1 | // <<< Use Configuration Wizard in Context Menu >>>
 2 | // <h> Debug MCU Configuration
 3 | //   <o0.0>    DBG_SLEEP
 4 | // <i> Debug Sleep Mode
 5 | // <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
 6 | // <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
 7 | //   <o0.1>    DBG_STOP
 8 | // <i> Debug Stop Mode
 9 | // <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
10 | // <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
11 | //   <o0.2>    DBG_STANDBY
12 | // <i> Debug Standby Mode
13 | // <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
14 | // <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
15 | //   <o0.8>    DBG_IWDG_STOP
16 | // <i> Debug independent watchdog stopped when core is halted
17 | // <i> 0: The watchdog counter clock continues even if the core is halted
18 | // <i> 1: The watchdog counter clock is stopped when the core is halted
19 | //   <o0.9>    DBG_WWDG_STOP
20 | // <i> Debug window watchdog stopped when core is halted
21 | // <i> 0: The window watchdog counter clock continues even if the core is halted
22 | // <i> 1: The window watchdog counter clock is stopped when the core is halted
23 | //   <o0.10>   DBG_TIM1_STOP
24 | // <i> Timer 1 counter stopped when core is halted
25 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
26 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
27 | //   <o0.11>   DBG_TIM2_STOP
28 | // <i> Timer 2 counter stopped when core is halted
29 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
30 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
31 | //   <o0.12>   DBG_TIM3_STOP
32 | // <i> Timer 3 counter stopped when core is halted
33 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
34 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
35 | //   <o0.13>   DBG_TIM4_STOP
36 | // <i> Timer 4 counter stopped when core is halted
37 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
38 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
39 | //   <o0.14>   DBG_CAN1_STOP
40 | // <i> Debug CAN1 stopped when Core is halted
41 | // <i> 0: Same behavior as in normal mode
42 | // <i> 1: CAN1 receive registers are frozen
43 | //   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
44 | // <i> I2C1 SMBUS timeout mode stopped when Core is halted
45 | // <i> 0: Same behavior as in normal mode
46 | // <i> 1: The SMBUS timeout is frozen
47 | //   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
48 | // <i> I2C2 SMBUS timeout mode stopped when Core is halted
49 | // <i> 0: Same behavior as in normal mode
50 | // <i> 1: The SMBUS timeout is frozen
51 | //   <o0.17>   DBG_TIM8_STOP
52 | // <i> Timer 8 counter stopped when core is halted
53 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
54 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
55 | //   <o0.18>   DBG_TIM5_STOP
56 | // <i> Timer 5 counter stopped when core is halted
57 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
58 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
59 | //   <o0.19>   DBG_TIM6_STOP
60 | // <i> Timer 6 counter stopped when core is halted
61 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
62 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
63 | //   <o0.20>   DBG_TIM7_STOP
64 | // <i> Timer 7 counter stopped when core is halted
65 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
66 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
67 | //   <o0.21>   DBG_CAN2_STOP
68 | // <i> Debug CAN2 stopped when Core is halted
69 | // <i> 0: Same behavior as in normal mode
70 | // <i> 1: CAN2 receive registers are frozen
71 | //   <o0.25>   DBG_TIM12_STOP
72 | // <i> Timer 12 counter stopped when core is halted
73 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
74 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
75 | //   <o0.26>   DBG_TIM13_STOP
76 | // <i> Timer 13 counter stopped when core is halted
77 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
78 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
79 | //   <o0.27>   DBG_TIM14_STOP
80 | // <i> Timer 14 counter stopped when core is halted
81 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
82 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
83 | //   <o0.28>   DBG_TIM9_STOP
84 | // <i> Timer 9 counter stopped when core is halted
85 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
86 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
87 | //   <o0.29>   DBG_TIM10_STOP
88 | // <i> Timer 10 counter stopped when core is halted
89 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
90 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
91 | //   <o0.30>   DBG_TIM11_STOP
92 | // <i> Timer 11 counter stopped when core is halted
93 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
94 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
95 | // </h>
96 | DbgMCU_CR = 0x00000007;
97 | // <<< end of configuration section >>>


--------------------------------------------------------------------------------
/USER/DebugConfig/LED_STM32F103ZE.dbgconf:
--------------------------------------------------------------------------------
 1 | // <<< Use Configuration Wizard in Context Menu >>>
 2 | // <h> Debug MCU Configuration
 3 | //   <o0.0>    DBG_SLEEP
 4 | // <i> Debug Sleep Mode
 5 | // <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
 6 | // <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
 7 | //   <o0.1>    DBG_STOP
 8 | // <i> Debug Stop Mode
 9 | // <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
10 | // <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
11 | //   <o0.2>    DBG_STANDBY
12 | // <i> Debug Standby Mode
13 | // <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
14 | // <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
15 | //   <o0.8>    DBG_IWDG_STOP
16 | // <i> Debug independent watchdog stopped when core is halted
17 | // <i> 0: The watchdog counter clock continues even if the core is halted
18 | // <i> 1: The watchdog counter clock is stopped when the core is halted
19 | //   <o0.9>    DBG_WWDG_STOP
20 | // <i> Debug window watchdog stopped when core is halted
21 | // <i> 0: The window watchdog counter clock continues even if the core is halted
22 | // <i> 1: The window watchdog counter clock is stopped when the core is halted
23 | //   <o0.10>   DBG_TIM1_STOP
24 | // <i> Timer 1 counter stopped when core is halted
25 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
26 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
27 | //   <o0.11>   DBG_TIM2_STOP
28 | // <i> Timer 2 counter stopped when core is halted
29 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
30 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
31 | //   <o0.12>   DBG_TIM3_STOP
32 | // <i> Timer 3 counter stopped when core is halted
33 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
34 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
35 | //   <o0.13>   DBG_TIM4_STOP
36 | // <i> Timer 4 counter stopped when core is halted
37 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
38 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
39 | //   <o0.14>   DBG_CAN1_STOP
40 | // <i> Debug CAN1 stopped when Core is halted
41 | // <i> 0: Same behavior as in normal mode
42 | // <i> 1: CAN1 receive registers are frozen
43 | //   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
44 | // <i> I2C1 SMBUS timeout mode stopped when Core is halted
45 | // <i> 0: Same behavior as in normal mode
46 | // <i> 1: The SMBUS timeout is frozen
47 | //   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
48 | // <i> I2C2 SMBUS timeout mode stopped when Core is halted
49 | // <i> 0: Same behavior as in normal mode
50 | // <i> 1: The SMBUS timeout is frozen
51 | //   <o0.17>   DBG_TIM8_STOP
52 | // <i> Timer 8 counter stopped when core is halted
53 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
54 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
55 | //   <o0.18>   DBG_TIM5_STOP
56 | // <i> Timer 5 counter stopped when core is halted
57 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
58 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
59 | //   <o0.19>   DBG_TIM6_STOP
60 | // <i> Timer 6 counter stopped when core is halted
61 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
62 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
63 | //   <o0.20>   DBG_TIM7_STOP
64 | // <i> Timer 7 counter stopped when core is halted
65 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
66 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
67 | //   <o0.21>   DBG_CAN2_STOP
68 | // <i> Debug CAN2 stopped when Core is halted
69 | // <i> 0: Same behavior as in normal mode
70 | // <i> 1: CAN2 receive registers are frozen
71 | //   <o0.25>   DBG_TIM12_STOP
72 | // <i> Timer 12 counter stopped when core is halted
73 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
74 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
75 | //   <o0.26>   DBG_TIM13_STOP
76 | // <i> Timer 13 counter stopped when core is halted
77 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
78 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
79 | //   <o0.27>   DBG_TIM14_STOP
80 | // <i> Timer 14 counter stopped when core is halted
81 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
82 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
83 | //   <o0.28>   DBG_TIM9_STOP
84 | // <i> Timer 9 counter stopped when core is halted
85 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
86 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
87 | //   <o0.29>   DBG_TIM10_STOP
88 | // <i> Timer 10 counter stopped when core is halted
89 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
90 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
91 | //   <o0.30>   DBG_TIM11_STOP
92 | // <i> Timer 11 counter stopped when core is halted
93 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
94 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
95 | // </h>
96 | DbgMCU_CR = 0x00000007;
97 | // <<< end of configuration section >>>


--------------------------------------------------------------------------------
/USER/DebugConfig/LED_STM32F103C8_1.0.0.dbgconf:
--------------------------------------------------------------------------------
 1 | // <<< Use Configuration Wizard in Context Menu >>>
 2 | // <h> Debug MCU Configuration
 3 | //   <o0.0>    DBG_SLEEP
 4 | // <i> Debug Sleep Mode
 5 | // <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
 6 | // <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
 7 | //   <o0.1>    DBG_STOP
 8 | // <i> Debug Stop Mode
 9 | // <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
10 | // <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
11 | //   <o0.2>    DBG_STANDBY
12 | // <i> Debug Standby Mode
13 | // <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
14 | // <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
15 | //   <o0.8>    DBG_IWDG_STOP
16 | // <i> Debug independent watchdog stopped when core is halted
17 | // <i> 0: The watchdog counter clock continues even if the core is halted
18 | // <i> 1: The watchdog counter clock is stopped when the core is halted
19 | //   <o0.9>    DBG_WWDG_STOP
20 | // <i> Debug window watchdog stopped when core is halted
21 | // <i> 0: The window watchdog counter clock continues even if the core is halted
22 | // <i> 1: The window watchdog counter clock is stopped when the core is halted
23 | //   <o0.10>   DBG_TIM1_STOP
24 | // <i> Timer 1 counter stopped when core is halted
25 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
26 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
27 | //   <o0.11>   DBG_TIM2_STOP
28 | // <i> Timer 2 counter stopped when core is halted
29 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
30 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
31 | //   <o0.12>   DBG_TIM3_STOP
32 | // <i> Timer 3 counter stopped when core is halted
33 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
34 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
35 | //   <o0.13>   DBG_TIM4_STOP
36 | // <i> Timer 4 counter stopped when core is halted
37 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
38 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
39 | //   <o0.14>   DBG_CAN1_STOP
40 | // <i> Debug CAN1 stopped when Core is halted
41 | // <i> 0: Same behavior as in normal mode
42 | // <i> 1: CAN1 receive registers are frozen
43 | //   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
44 | // <i> I2C1 SMBUS timeout mode stopped when Core is halted
45 | // <i> 0: Same behavior as in normal mode
46 | // <i> 1: The SMBUS timeout is frozen
47 | //   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
48 | // <i> I2C2 SMBUS timeout mode stopped when Core is halted
49 | // <i> 0: Same behavior as in normal mode
50 | // <i> 1: The SMBUS timeout is frozen
51 | //   <o0.17>   DBG_TIM8_STOP
52 | // <i> Timer 8 counter stopped when core is halted
53 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
54 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
55 | //   <o0.18>   DBG_TIM5_STOP
56 | // <i> Timer 5 counter stopped when core is halted
57 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
58 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
59 | //   <o0.19>   DBG_TIM6_STOP
60 | // <i> Timer 6 counter stopped when core is halted
61 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
62 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
63 | //   <o0.20>   DBG_TIM7_STOP
64 | // <i> Timer 7 counter stopped when core is halted
65 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
66 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
67 | //   <o0.21>   DBG_CAN2_STOP
68 | // <i> Debug CAN2 stopped when Core is halted
69 | // <i> 0: Same behavior as in normal mode
70 | // <i> 1: CAN2 receive registers are frozen
71 | //   <o0.25>   DBG_TIM12_STOP
72 | // <i> Timer 12 counter stopped when core is halted
73 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
74 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
75 | //   <o0.26>   DBG_TIM13_STOP
76 | // <i> Timer 13 counter stopped when core is halted
77 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
78 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
79 | //   <o0.27>   DBG_TIM14_STOP
80 | // <i> Timer 14 counter stopped when core is halted
81 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
82 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
83 | //   <o0.28>   DBG_TIM9_STOP
84 | // <i> Timer 9 counter stopped when core is halted
85 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
86 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
87 | //   <o0.29>   DBG_TIM10_STOP
88 | // <i> Timer 10 counter stopped when core is halted
89 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
90 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
91 | //   <o0.30>   DBG_TIM11_STOP
92 | // <i> Timer 11 counter stopped when core is halted
93 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
94 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
95 | // </h>
96 | DbgMCU_CR = 0x00000007;
97 | // <<< end of configuration section >>>


--------------------------------------------------------------------------------
/USER/DebugConfig/LED_STM32F103ZE_1.0.0.dbgconf:
--------------------------------------------------------------------------------
 1 | // <<< Use Configuration Wizard in Context Menu >>>
 2 | // <h> Debug MCU Configuration
 3 | //   <o0.0>    DBG_SLEEP
 4 | // <i> Debug Sleep Mode
 5 | // <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
 6 | // <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
 7 | //   <o0.1>    DBG_STOP
 8 | // <i> Debug Stop Mode
 9 | // <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
10 | // <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
11 | //   <o0.2>    DBG_STANDBY
12 | // <i> Debug Standby Mode
13 | // <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
14 | // <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
15 | //   <o0.8>    DBG_IWDG_STOP
16 | // <i> Debug independent watchdog stopped when core is halted
17 | // <i> 0: The watchdog counter clock continues even if the core is halted
18 | // <i> 1: The watchdog counter clock is stopped when the core is halted
19 | //   <o0.9>    DBG_WWDG_STOP
20 | // <i> Debug window watchdog stopped when core is halted
21 | // <i> 0: The window watchdog counter clock continues even if the core is halted
22 | // <i> 1: The window watchdog counter clock is stopped when the core is halted
23 | //   <o0.10>   DBG_TIM1_STOP
24 | // <i> Timer 1 counter stopped when core is halted
25 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
26 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
27 | //   <o0.11>   DBG_TIM2_STOP
28 | // <i> Timer 2 counter stopped when core is halted
29 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
30 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
31 | //   <o0.12>   DBG_TIM3_STOP
32 | // <i> Timer 3 counter stopped when core is halted
33 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
34 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
35 | //   <o0.13>   DBG_TIM4_STOP
36 | // <i> Timer 4 counter stopped when core is halted
37 | // <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
38 | // <i> 1: The clock of the involved Timer counter is stopped when the core is halted
39 | //   <o0.14>   DBG_CAN1_STOP
40 | // <i> Debug CAN1 stopped when Core is halted
41 | // <i> 0: Same behavior as in normal mode
42 | // <i> 1: CAN1 receive registers are frozen
43 | //   <o0.15>   DBG_I2C1_SMBUS_TIMEOUT
44 | // <i> I2C1 SMBUS timeout mode stopped when Core is halted
45 | // <i> 0: Same behavior as in normal mode
46 | // <i> 1: The SMBUS timeout is frozen
47 | //   <o0.16>   DBG_I2C2_SMBUS_TIMEOUT
48 | // <i> I2C2 SMBUS timeout mode stopped when Core is halted
49 | // <i> 0: Same behavior as in normal mode
50 | // <i> 1: The SMBUS timeout is frozen
51 | //   <o0.17>   DBG_TIM8_STOP
52 | // <i> Timer 8 counter stopped when core is halted
53 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
54 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
55 | //   <o0.18>   DBG_TIM5_STOP
56 | // <i> Timer 5 counter stopped when core is halted
57 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
58 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
59 | //   <o0.19>   DBG_TIM6_STOP
60 | // <i> Timer 6 counter stopped when core is halted
61 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
62 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
63 | //   <o0.20>   DBG_TIM7_STOP
64 | // <i> Timer 7 counter stopped when core is halted
65 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
66 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
67 | //   <o0.21>   DBG_CAN2_STOP
68 | // <i> Debug CAN2 stopped when Core is halted
69 | // <i> 0: Same behavior as in normal mode
70 | // <i> 1: CAN2 receive registers are frozen
71 | //   <o0.25>   DBG_TIM12_STOP
72 | // <i> Timer 12 counter stopped when core is halted
73 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
74 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
75 | //   <o0.26>   DBG_TIM13_STOP
76 | // <i> Timer 13 counter stopped when core is halted
77 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
78 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
79 | //   <o0.27>   DBG_TIM14_STOP
80 | // <i> Timer 14 counter stopped when core is halted
81 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
82 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
83 | //   <o0.28>   DBG_TIM9_STOP
84 | // <i> Timer 9 counter stopped when core is halted
85 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
86 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
87 | //   <o0.29>   DBG_TIM10_STOP
88 | // <i> Timer 10 counter stopped when core is halted
89 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
90 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
91 | //   <o0.30>   DBG_TIM11_STOP
92 | // <i> Timer 11 counter stopped when core is halted
93 | // <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
94 | // <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
95 | // </h>
96 | DbgMCU_CR = 0x00000007;
97 | // <<< end of configuration section >>>


--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_cec.h:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_cec.h
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file contains all the functions prototypes for the CEC firmware 
  8 |   *          library.
  9 |   ******************************************************************************
 10 |   * @attention
 11 |   *
 12 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 13 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 14 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 15 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 16 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 17 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 18 |   *
 19 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 20 |   ******************************************************************************
 21 |   */
 22 | 
 23 | /* Define to prevent recursive inclusion -------------------------------------*/
 24 | #ifndef __STM32F10x_CEC_H
 25 | #define __STM32F10x_CEC_H
 26 | 
 27 | #ifdef __cplusplus
 28 |  extern "C" {
 29 | #endif
 30 | 
 31 | /* Includes ------------------------------------------------------------------*/
 32 | #include "stm32f10x.h"
 33 | 
 34 | /** @addtogroup STM32F10x_StdPeriph_Driver
 35 |   * @{
 36 |   */
 37 | 
 38 | /** @addtogroup CEC
 39 |   * @{
 40 |   */
 41 |   
 42 | 
 43 | /** @defgroup CEC_Exported_Types
 44 |   * @{
 45 |   */
 46 |    
 47 | /** 
 48 |   * @brief  CEC Init structure definition  
 49 |   */ 
 50 | typedef struct
 51 | {
 52 |   uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. 
 53 |                                This parameter can be a value of @ref CEC_BitTiming_Mode */
 54 |   uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. 
 55 |                                This parameter can be a value of @ref CEC_BitPeriod_Mode */
 56 | }CEC_InitTypeDef;
 57 | 
 58 | /**
 59 |   * @}
 60 |   */
 61 | 
 62 | /** @defgroup CEC_Exported_Constants
 63 |   * @{
 64 |   */ 
 65 |   
 66 | /** @defgroup CEC_BitTiming_Mode 
 67 |   * @{
 68 |   */ 
 69 | #define CEC_BitTimingStdMode                    ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
 70 | #define CEC_BitTimingErrFreeMode                CEC_CFGR_BTEM   /*!< Bit timing error Free Mode */
 71 | 
 72 | #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
 73 |                                             ((MODE) == CEC_BitTimingErrFreeMode))
 74 | /**
 75 |   * @}
 76 |   */
 77 | 
 78 | /** @defgroup CEC_BitPeriod_Mode 
 79 |   * @{
 80 |   */ 
 81 | #define CEC_BitPeriodStdMode                    ((uint16_t)0x00) /*!< Bit period error Standard Mode */
 82 | #define CEC_BitPeriodFlexibleMode                CEC_CFGR_BPEM   /*!< Bit period error Flexible Mode */
 83 | 
 84 | #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
 85 |                                             ((MODE) == CEC_BitPeriodFlexibleMode))
 86 | /**
 87 |   * @}
 88 |   */ 
 89 | 
 90 | 
 91 | /** @defgroup CEC_interrupts_definition 
 92 |   * @{
 93 |   */ 
 94 | #define CEC_IT_TERR                              CEC_CSR_TERR
 95 | #define CEC_IT_TBTRF                             CEC_CSR_TBTRF
 96 | #define CEC_IT_RERR                              CEC_CSR_RERR
 97 | #define CEC_IT_RBTF                              CEC_CSR_RBTF
 98 | #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
 99 |                            ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
100 | /**
101 |   * @}
102 |   */ 
103 | 
104 | 
105 | /** @defgroup CEC_Own_Address 
106 |   * @{
107 |   */ 
108 | #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
109 | /**
110 |   * @}
111 |   */ 
112 | 
113 | /** @defgroup CEC_Prescaler 
114 |   * @{
115 |   */ 
116 | #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
117 | 
118 | /**
119 |   * @}
120 |   */
121 | 
122 | /** @defgroup CEC_flags_definition 
123 |   * @{
124 |   */
125 |    
126 | /** 
127 |   * @brief  ESR register flags  
128 |   */ 
129 | #define CEC_FLAG_BTE                            ((uint32_t)0x10010000)
130 | #define CEC_FLAG_BPE                            ((uint32_t)0x10020000)
131 | #define CEC_FLAG_RBTFE                          ((uint32_t)0x10040000)
132 | #define CEC_FLAG_SBE                            ((uint32_t)0x10080000)
133 | #define CEC_FLAG_ACKE                           ((uint32_t)0x10100000)
134 | #define CEC_FLAG_LINE                           ((uint32_t)0x10200000)
135 | #define CEC_FLAG_TBTFE                          ((uint32_t)0x10400000)
136 | 
137 | /** 
138 |   * @brief  CSR register flags  
139 |   */ 
140 | #define CEC_FLAG_TEOM                           ((uint32_t)0x00000002)  
141 | #define CEC_FLAG_TERR                           ((uint32_t)0x00000004)
142 | #define CEC_FLAG_TBTRF                          ((uint32_t)0x00000008)
143 | #define CEC_FLAG_RSOM                           ((uint32_t)0x00000010)
144 | #define CEC_FLAG_REOM                           ((uint32_t)0x00000020)
145 | #define CEC_FLAG_RERR                           ((uint32_t)0x00000040)
146 | #define CEC_FLAG_RBTF                           ((uint32_t)0x00000080)
147 | 
148 | #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
149 |                                
150 | #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
151 |                                ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
152 |                                ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
153 |                                ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
154 |                                ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
155 |                                ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
156 |                                ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
157 | 
158 | /**
159 |   * @}
160 |   */ 
161 | 
162 | /**
163 |   * @}
164 |   */ 
165 | 
166 | /** @defgroup CEC_Exported_Macros
167 |   * @{
168 |   */
169 |  
170 | /**
171 |   * @}
172 |   */
173 | 
174 | /** @defgroup CEC_Exported_Functions
175 |   * @{
176 |   */ 
177 | void CEC_DeInit(void);
178 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
179 | void CEC_Cmd(FunctionalState NewState);
180 | void CEC_ITConfig(FunctionalState NewState);
181 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
182 | void CEC_SetPrescaler(uint16_t CEC_Prescaler);
183 | void CEC_SendDataByte(uint8_t Data);
184 | uint8_t CEC_ReceiveDataByte(void);
185 | void CEC_StartOfMessage(void);
186 | void CEC_EndOfMessageCmd(FunctionalState NewState);
187 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
188 | void CEC_ClearFlag(uint32_t CEC_FLAG);
189 | ITStatus CEC_GetITStatus(uint8_t CEC_IT);
190 | void CEC_ClearITPendingBit(uint16_t CEC_IT);
191 | 
192 | #ifdef __cplusplus
193 | }
194 | #endif
195 | 
196 | #endif /* __STM32F10x_CEC_H */
197 | 
198 | /**
199 |   * @}
200 |   */ 
201 | 
202 | /**
203 |   * @}
204 |   */ 
205 | 
206 | /**
207 |   * @}
208 |   */ 
209 | 
210 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
211 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_exti.h:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_exti.h
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file contains all the functions prototypes for the EXTI firmware
  8 |   *          library.
  9 |   ******************************************************************************
 10 |   * @attention
 11 |   *
 12 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 13 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 14 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 15 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 16 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 17 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 18 |   *
 19 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 20 |   ******************************************************************************
 21 |   */
 22 | 
 23 | /* Define to prevent recursive inclusion -------------------------------------*/
 24 | #ifndef __STM32F10x_EXTI_H
 25 | #define __STM32F10x_EXTI_H
 26 | 
 27 | #ifdef __cplusplus
 28 |  extern "C" {
 29 | #endif
 30 | 
 31 | /* Includes ------------------------------------------------------------------*/
 32 | #include "stm32f10x.h"
 33 | 
 34 | /** @addtogroup STM32F10x_StdPeriph_Driver
 35 |   * @{
 36 |   */
 37 | 
 38 | /** @addtogroup EXTI
 39 |   * @{
 40 |   */
 41 | 
 42 | /** @defgroup EXTI_Exported_Types
 43 |   * @{
 44 |   */
 45 | 
 46 | /** 
 47 |   * @brief  EXTI mode enumeration  
 48 |   */
 49 | 
 50 | typedef enum
 51 | {
 52 |   EXTI_Mode_Interrupt = 0x00,
 53 |   EXTI_Mode_Event = 0x04
 54 | }EXTIMode_TypeDef;
 55 | 
 56 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
 57 | 
 58 | /** 
 59 |   * @brief  EXTI Trigger enumeration  
 60 |   */
 61 | 
 62 | typedef enum
 63 | {
 64 |   EXTI_Trigger_Rising = 0x08,
 65 |   EXTI_Trigger_Falling = 0x0C,  
 66 |   EXTI_Trigger_Rising_Falling = 0x10
 67 | }EXTITrigger_TypeDef;
 68 | 
 69 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
 70 |                                   ((TRIGGER) == EXTI_Trigger_Falling) || \
 71 |                                   ((TRIGGER) == EXTI_Trigger_Rising_Falling))
 72 | /** 
 73 |   * @brief  EXTI Init Structure definition  
 74 |   */
 75 | 
 76 | typedef struct
 77 | {
 78 |   uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
 79 |                                          This parameter can be any combination of @ref EXTI_Lines */
 80 |    
 81 |   EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
 82 |                                          This parameter can be a value of @ref EXTIMode_TypeDef */
 83 | 
 84 |   EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
 85 |                                          This parameter can be a value of @ref EXTIMode_TypeDef */
 86 | 
 87 |   FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
 88 |                                          This parameter can be set either to ENABLE or DISABLE */ 
 89 | }EXTI_InitTypeDef;
 90 | 
 91 | /**
 92 |   * @}
 93 |   */
 94 | 
 95 | /** @defgroup EXTI_Exported_Constants
 96 |   * @{
 97 |   */
 98 | 
 99 | /** @defgroup EXTI_Lines 
100 |   * @{
101 |   */
102 | 
103 | #define EXTI_Line0       ((uint32_t)0x00001)  /*!< External interrupt line 0 */
104 | #define EXTI_Line1       ((uint32_t)0x00002)  /*!< External interrupt line 1 */
105 | #define EXTI_Line2       ((uint32_t)0x00004)  /*!< External interrupt line 2 */
106 | #define EXTI_Line3       ((uint32_t)0x00008)  /*!< External interrupt line 3 */
107 | #define EXTI_Line4       ((uint32_t)0x00010)  /*!< External interrupt line 4 */
108 | #define EXTI_Line5       ((uint32_t)0x00020)  /*!< External interrupt line 5 */
109 | #define EXTI_Line6       ((uint32_t)0x00040)  /*!< External interrupt line 6 */
110 | #define EXTI_Line7       ((uint32_t)0x00080)  /*!< External interrupt line 7 */
111 | #define EXTI_Line8       ((uint32_t)0x00100)  /*!< External interrupt line 8 */
112 | #define EXTI_Line9       ((uint32_t)0x00200)  /*!< External interrupt line 9 */
113 | #define EXTI_Line10      ((uint32_t)0x00400)  /*!< External interrupt line 10 */
114 | #define EXTI_Line11      ((uint32_t)0x00800)  /*!< External interrupt line 11 */
115 | #define EXTI_Line12      ((uint32_t)0x01000)  /*!< External interrupt line 12 */
116 | #define EXTI_Line13      ((uint32_t)0x02000)  /*!< External interrupt line 13 */
117 | #define EXTI_Line14      ((uint32_t)0x04000)  /*!< External interrupt line 14 */
118 | #define EXTI_Line15      ((uint32_t)0x08000)  /*!< External interrupt line 15 */
119 | #define EXTI_Line16      ((uint32_t)0x10000)  /*!< External interrupt line 16 Connected to the PVD Output */
120 | #define EXTI_Line17      ((uint32_t)0x20000)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
121 | #define EXTI_Line18      ((uint32_t)0x40000)  /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
122 |                                                    Wakeup from suspend event */                                    
123 | #define EXTI_Line19      ((uint32_t)0x80000)  /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
124 |                                           
125 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
126 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
127 |                             ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
128 |                             ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
129 |                             ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
130 |                             ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
131 |                             ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
132 |                             ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
133 |                             ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
134 |                             ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
135 |                             ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
136 | 
137 |                     
138 | /**
139 |   * @}
140 |   */
141 | 
142 | /**
143 |   * @}
144 |   */
145 | 
146 | /** @defgroup EXTI_Exported_Macros
147 |   * @{
148 |   */
149 | 
150 | /**
151 |   * @}
152 |   */
153 | 
154 | /** @defgroup EXTI_Exported_Functions
155 |   * @{
156 |   */
157 | 
158 | void EXTI_DeInit(void);
159 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
160 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
161 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
162 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
163 | void EXTI_ClearFlag(uint32_t EXTI_Line);
164 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
165 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
166 | 
167 | #ifdef __cplusplus
168 | }
169 | #endif
170 | 
171 | #endif /* __STM32F10x_EXTI_H */
172 | /**
173 |   * @}
174 |   */
175 | 
176 | /**
177 |   * @}
178 |   */
179 | 
180 | /**
181 |   * @}
182 |   */
183 | 
184 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
185 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/misc.c:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    misc.c
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file provides all the miscellaneous firmware functions (add-on
  8 |   *          to CMSIS functions).
  9 |   ******************************************************************************
 10 |   * @attention
 11 |   *
 12 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 13 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 14 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 15 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 16 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 17 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 18 |   *
 19 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 20 |   ******************************************************************************
 21 |   */
 22 | 
 23 | /* Includes ------------------------------------------------------------------*/
 24 | #include "misc.h"
 25 | 
 26 | /** @addtogroup STM32F10x_StdPeriph_Driver
 27 |   * @{
 28 |   */
 29 | 
 30 | /** @defgroup MISC 
 31 |   * @brief MISC driver modules
 32 |   * @{
 33 |   */
 34 | 
 35 | /** @defgroup MISC_Private_TypesDefinitions
 36 |   * @{
 37 |   */
 38 | 
 39 | /**
 40 |   * @}
 41 |   */ 
 42 | 
 43 | /** @defgroup MISC_Private_Defines
 44 |   * @{
 45 |   */
 46 | 
 47 | #define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
 48 | /**
 49 |   * @}
 50 |   */
 51 | 
 52 | /** @defgroup MISC_Private_Macros
 53 |   * @{
 54 |   */
 55 | 
 56 | /**
 57 |   * @}
 58 |   */
 59 | 
 60 | /** @defgroup MISC_Private_Variables
 61 |   * @{
 62 |   */
 63 | 
 64 | /**
 65 |   * @}
 66 |   */
 67 | 
 68 | /** @defgroup MISC_Private_FunctionPrototypes
 69 |   * @{
 70 |   */
 71 | 
 72 | /**
 73 |   * @}
 74 |   */
 75 | 
 76 | /** @defgroup MISC_Private_Functions
 77 |   * @{
 78 |   */
 79 | 
 80 | /**
 81 |   * @brief  Configures the priority grouping: pre-emption priority and subpriority.
 82 |   * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
 83 |   *   This parameter can be one of the following values:
 84 |   *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
 85 |   *                                4 bits for subpriority
 86 |   *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
 87 |   *                                3 bits for subpriority
 88 |   *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
 89 |   *                                2 bits for subpriority
 90 |   *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
 91 |   *                                1 bits for subpriority
 92 |   *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
 93 |   *                                0 bits for subpriority
 94 |   * @retval None
 95 |   */
 96 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
 97 | {
 98 |   /* Check the parameters */
 99 |   assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
100 |   
101 |   /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
102 |   SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
103 | }
104 | 
105 | /**
106 |   * @brief  Initializes the NVIC peripheral according to the specified
107 |   *         parameters in the NVIC_InitStruct.
108 |   * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
109 |   *         the configuration information for the specified NVIC peripheral.
110 |   * @retval None
111 |   */
112 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
113 | {
114 |   uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
115 |   
116 |   /* Check the parameters */
117 |   assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
118 |   assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
119 |   assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
120 |     
121 |   if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
122 |   {
123 |     /* Compute the Corresponding IRQ Priority --------------------------------*/    
124 |     tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
125 |     tmppre = (0x4 - tmppriority);
126 |     tmpsub = tmpsub >> tmppriority;
127 | 
128 |     tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
129 |     tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
130 |     tmppriority = tmppriority << 0x04;
131 |         
132 |     NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
133 |     
134 |     /* Enable the Selected IRQ Channels --------------------------------------*/
135 |     NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
136 |       (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
137 |   }
138 |   else
139 |   {
140 |     /* Disable the Selected IRQ Channels -------------------------------------*/
141 |     NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
142 |       (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
143 |   }
144 | }
145 | 
146 | /**
147 |   * @brief  Sets the vector table location and Offset.
148 |   * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
149 |   *   This parameter can be one of the following values:
150 |   *     @arg NVIC_VectTab_RAM
151 |   *     @arg NVIC_VectTab_FLASH
152 |   * @param  Offset: Vector Table base offset field. This value must be a multiple 
153 |   *         of 0x200.
154 |   * @retval None
155 |   */
156 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
157 | { 
158 |   /* Check the parameters */
159 |   assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
160 |   assert_param(IS_NVIC_OFFSET(Offset));  
161 |    
162 |   SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
163 | }
164 | 
165 | /**
166 |   * @brief  Selects the condition for the system to enter low power mode.
167 |   * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
168 |   *   This parameter can be one of the following values:
169 |   *     @arg NVIC_LP_SEVONPEND
170 |   *     @arg NVIC_LP_SLEEPDEEP
171 |   *     @arg NVIC_LP_SLEEPONEXIT
172 |   * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
173 |   * @retval None
174 |   */
175 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
176 | {
177 |   /* Check the parameters */
178 |   assert_param(IS_NVIC_LP(LowPowerMode));
179 |   assert_param(IS_FUNCTIONAL_STATE(NewState));  
180 |   
181 |   if (NewState != DISABLE)
182 |   {
183 |     SCB->SCR |= LowPowerMode;
184 |   }
185 |   else
186 |   {
187 |     SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
188 |   }
189 | }
190 | 
191 | /**
192 |   * @brief  Configures the SysTick clock source.
193 |   * @param  SysTick_CLKSource: specifies the SysTick clock source.
194 |   *   This parameter can be one of the following values:
195 |   *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
196 |   *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
197 |   * @retval None
198 |   */
199 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
200 | {
201 |   /* Check the parameters */
202 |   assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
203 |   if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
204 |   {
205 |     SysTick->CTRL |= SysTick_CLKSource_HCLK;
206 |   }
207 |   else
208 |   {
209 |     SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
210 |   }
211 | }
212 | 
213 | /**
214 |   * @}
215 |   */
216 | 
217 | /**
218 |   * @}
219 |   */
220 | 
221 | /**
222 |   * @}
223 |   */
224 | 
225 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
226 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/stm32f10x_exti.c:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_exti.c
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file provides all the EXTI firmware functions.
  8 |   ******************************************************************************
  9 |   * @attention
 10 |   *
 11 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 12 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 13 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 14 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 15 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 16 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 17 |   *
 18 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 19 |   ******************************************************************************
 20 |   */
 21 | 
 22 | /* Includes ------------------------------------------------------------------*/
 23 | #include "stm32f10x_exti.h"
 24 | 
 25 | /** @addtogroup STM32F10x_StdPeriph_Driver
 26 |   * @{
 27 |   */
 28 | 
 29 | /** @defgroup EXTI 
 30 |   * @brief EXTI driver modules
 31 |   * @{
 32 |   */
 33 | 
 34 | /** @defgroup EXTI_Private_TypesDefinitions
 35 |   * @{
 36 |   */
 37 | 
 38 | /**
 39 |   * @}
 40 |   */
 41 | 
 42 | /** @defgroup EXTI_Private_Defines
 43 |   * @{
 44 |   */
 45 | 
 46 | #define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
 47 | 
 48 | /**
 49 |   * @}
 50 |   */
 51 | 
 52 | /** @defgroup EXTI_Private_Macros
 53 |   * @{
 54 |   */
 55 | 
 56 | /**
 57 |   * @}
 58 |   */
 59 | 
 60 | /** @defgroup EXTI_Private_Variables
 61 |   * @{
 62 |   */
 63 | 
 64 | /**
 65 |   * @}
 66 |   */
 67 | 
 68 | /** @defgroup EXTI_Private_FunctionPrototypes
 69 |   * @{
 70 |   */
 71 | 
 72 | /**
 73 |   * @}
 74 |   */
 75 | 
 76 | /** @defgroup EXTI_Private_Functions
 77 |   * @{
 78 |   */
 79 | 
 80 | /**
 81 |   * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
 82 |   * @param  None
 83 |   * @retval None
 84 |   */
 85 | void EXTI_DeInit(void)
 86 | {
 87 |   EXTI->IMR = 0x00000000;
 88 |   EXTI->EMR = 0x00000000;
 89 |   EXTI->RTSR = 0x00000000; 
 90 |   EXTI->FTSR = 0x00000000; 
 91 |   EXTI->PR = 0x000FFFFF;
 92 | }
 93 | 
 94 | /**
 95 |   * @brief  Initializes the EXTI peripheral according to the specified
 96 |   *         parameters in the EXTI_InitStruct.
 97 |   * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
 98 |   *         that contains the configuration information for the EXTI peripheral.
 99 |   * @retval None
100 |   */
101 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
102 | {
103 |   uint32_t tmp = 0;
104 | 
105 |   /* Check the parameters */
106 |   assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
107 |   assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
108 |   assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  
109 |   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
110 | 
111 |   tmp = (uint32_t)EXTI_BASE;
112 |      
113 |   if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
114 |   {
115 |     /* Clear EXTI line configuration */
116 |     EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
117 |     EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
118 |     
119 |     tmp += EXTI_InitStruct->EXTI_Mode;
120 | 
121 |     *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
122 | 
123 |     /* Clear Rising Falling edge configuration */
124 |     EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
125 |     EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
126 |     
127 |     /* Select the trigger for the selected external interrupts */
128 |     if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
129 |     {
130 |       /* Rising Falling edge */
131 |       EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
132 |       EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
133 |     }
134 |     else
135 |     {
136 |       tmp = (uint32_t)EXTI_BASE;
137 |       tmp += EXTI_InitStruct->EXTI_Trigger;
138 | 
139 |       *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
140 |     }
141 |   }
142 |   else
143 |   {
144 |     tmp += EXTI_InitStruct->EXTI_Mode;
145 | 
146 |     /* Disable the selected external lines */
147 |     *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
148 |   }
149 | }
150 | 
151 | /**
152 |   * @brief  Fills each EXTI_InitStruct member with its reset value.
153 |   * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
154 |   *         be initialized.
155 |   * @retval None
156 |   */
157 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
158 | {
159 |   EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
160 |   EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
161 |   EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
162 |   EXTI_InitStruct->EXTI_LineCmd = DISABLE;
163 | }
164 | 
165 | /**
166 |   * @brief  Generates a Software interrupt.
167 |   * @param  EXTI_Line: specifies the EXTI lines to be enabled or disabled.
168 |   *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
169 |   * @retval None
170 |   */
171 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
172 | {
173 |   /* Check the parameters */
174 |   assert_param(IS_EXTI_LINE(EXTI_Line));
175 |   
176 |   EXTI->SWIER |= EXTI_Line;
177 | }
178 | 
179 | /**
180 |   * @brief  Checks whether the specified EXTI line flag is set or not.
181 |   * @param  EXTI_Line: specifies the EXTI line flag to check.
182 |   *   This parameter can be:
183 |   *     @arg EXTI_Linex: External interrupt line x where x(0..19)
184 |   * @retval The new state of EXTI_Line (SET or RESET).
185 |   */
186 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
187 | {
188 |   FlagStatus bitstatus = RESET;
189 |   /* Check the parameters */
190 |   assert_param(IS_GET_EXTI_LINE(EXTI_Line));
191 |   
192 |   if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
193 |   {
194 |     bitstatus = SET;
195 |   }
196 |   else
197 |   {
198 |     bitstatus = RESET;
199 |   }
200 |   return bitstatus;
201 | }
202 | 
203 | /**
204 |   * @brief  Clears the EXTI's line pending flags.
205 |   * @param  EXTI_Line: specifies the EXTI lines flags to clear.
206 |   *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
207 |   * @retval None
208 |   */
209 | void EXTI_ClearFlag(uint32_t EXTI_Line)
210 | {
211 |   /* Check the parameters */
212 |   assert_param(IS_EXTI_LINE(EXTI_Line));
213 |   
214 |   EXTI->PR = EXTI_Line;
215 | }
216 | 
217 | /**
218 |   * @brief  Checks whether the specified EXTI line is asserted or not.
219 |   * @param  EXTI_Line: specifies the EXTI line to check.
220 |   *   This parameter can be:
221 |   *     @arg EXTI_Linex: External interrupt line x where x(0..19)
222 |   * @retval The new state of EXTI_Line (SET or RESET).
223 |   */
224 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
225 | {
226 |   ITStatus bitstatus = RESET;
227 |   uint32_t enablestatus = 0;
228 |   /* Check the parameters */
229 |   assert_param(IS_GET_EXTI_LINE(EXTI_Line));
230 |   
231 |   enablestatus =  EXTI->IMR & EXTI_Line;
232 |   if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
233 |   {
234 |     bitstatus = SET;
235 |   }
236 |   else
237 |   {
238 |     bitstatus = RESET;
239 |   }
240 |   return bitstatus;
241 | }
242 | 
243 | /**
244 |   * @brief  Clears the EXTI's line pending bits.
245 |   * @param  EXTI_Line: specifies the EXTI lines to clear.
246 |   *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
247 |   * @retval None
248 |   */
249 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
250 | {
251 |   /* Check the parameters */
252 |   assert_param(IS_EXTI_LINE(EXTI_Line));
253 |   
254 |   EXTI->PR = EXTI_Line;
255 | }
256 | 
257 | /**
258 |   * @}
259 |   */
260 | 
261 | /**
262 |   * @}
263 |   */
264 | 
265 | /**
266 |   * @}
267 |   */
268 | 
269 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
270 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/stm32f10x_bkp.h:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_bkp.h
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file contains all the functions prototypes for the BKP firmware 
  8 |   *          library.
  9 |   ******************************************************************************
 10 |   * @attention
 11 |   *
 12 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 13 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 14 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 15 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 16 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 17 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 18 |   *
 19 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 20 |   ******************************************************************************
 21 |   */
 22 | 
 23 | /* Define to prevent recursive inclusion -------------------------------------*/
 24 | #ifndef __STM32F10x_BKP_H
 25 | #define __STM32F10x_BKP_H
 26 | 
 27 | #ifdef __cplusplus
 28 |  extern "C" {
 29 | #endif
 30 | 
 31 | /* Includes ------------------------------------------------------------------*/
 32 | #include "stm32f10x.h"
 33 | 
 34 | /** @addtogroup STM32F10x_StdPeriph_Driver
 35 |   * @{
 36 |   */
 37 | 
 38 | /** @addtogroup BKP
 39 |   * @{
 40 |   */
 41 | 
 42 | /** @defgroup BKP_Exported_Types
 43 |   * @{
 44 |   */
 45 | 
 46 | /**
 47 |   * @}
 48 |   */
 49 | 
 50 | /** @defgroup BKP_Exported_Constants
 51 |   * @{
 52 |   */
 53 | 
 54 | /** @defgroup Tamper_Pin_active_level 
 55 |   * @{
 56 |   */
 57 | 
 58 | #define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
 59 | #define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
 60 | #define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
 61 |                                         ((LEVEL) == BKP_TamperPinLevel_Low))
 62 | /**
 63 |   * @}
 64 |   */
 65 | 
 66 | /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin 
 67 |   * @{
 68 |   */
 69 | 
 70 | #define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
 71 | #define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
 72 | #define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
 73 | #define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
 74 | #define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
 75 |                                           ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
 76 |                                           ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
 77 |                                           ((SOURCE) == BKP_RTCOutputSource_Second))
 78 | /**
 79 |   * @}
 80 |   */
 81 | 
 82 | /** @defgroup Data_Backup_Register 
 83 |   * @{
 84 |   */
 85 | 
 86 | #define BKP_DR1                           ((uint16_t)0x0004)
 87 | #define BKP_DR2                           ((uint16_t)0x0008)
 88 | #define BKP_DR3                           ((uint16_t)0x000C)
 89 | #define BKP_DR4                           ((uint16_t)0x0010)
 90 | #define BKP_DR5                           ((uint16_t)0x0014)
 91 | #define BKP_DR6                           ((uint16_t)0x0018)
 92 | #define BKP_DR7                           ((uint16_t)0x001C)
 93 | #define BKP_DR8                           ((uint16_t)0x0020)
 94 | #define BKP_DR9                           ((uint16_t)0x0024)
 95 | #define BKP_DR10                          ((uint16_t)0x0028)
 96 | #define BKP_DR11                          ((uint16_t)0x0040)
 97 | #define BKP_DR12                          ((uint16_t)0x0044)
 98 | #define BKP_DR13                          ((uint16_t)0x0048)
 99 | #define BKP_DR14                          ((uint16_t)0x004C)
100 | #define BKP_DR15                          ((uint16_t)0x0050)
101 | #define BKP_DR16                          ((uint16_t)0x0054)
102 | #define BKP_DR17                          ((uint16_t)0x0058)
103 | #define BKP_DR18                          ((uint16_t)0x005C)
104 | #define BKP_DR19                          ((uint16_t)0x0060)
105 | #define BKP_DR20                          ((uint16_t)0x0064)
106 | #define BKP_DR21                          ((uint16_t)0x0068)
107 | #define BKP_DR22                          ((uint16_t)0x006C)
108 | #define BKP_DR23                          ((uint16_t)0x0070)
109 | #define BKP_DR24                          ((uint16_t)0x0074)
110 | #define BKP_DR25                          ((uint16_t)0x0078)
111 | #define BKP_DR26                          ((uint16_t)0x007C)
112 | #define BKP_DR27                          ((uint16_t)0x0080)
113 | #define BKP_DR28                          ((uint16_t)0x0084)
114 | #define BKP_DR29                          ((uint16_t)0x0088)
115 | #define BKP_DR30                          ((uint16_t)0x008C)
116 | #define BKP_DR31                          ((uint16_t)0x0090)
117 | #define BKP_DR32                          ((uint16_t)0x0094)
118 | #define BKP_DR33                          ((uint16_t)0x0098)
119 | #define BKP_DR34                          ((uint16_t)0x009C)
120 | #define BKP_DR35                          ((uint16_t)0x00A0)
121 | #define BKP_DR36                          ((uint16_t)0x00A4)
122 | #define BKP_DR37                          ((uint16_t)0x00A8)
123 | #define BKP_DR38                          ((uint16_t)0x00AC)
124 | #define BKP_DR39                          ((uint16_t)0x00B0)
125 | #define BKP_DR40                          ((uint16_t)0x00B4)
126 | #define BKP_DR41                          ((uint16_t)0x00B8)
127 | #define BKP_DR42                          ((uint16_t)0x00BC)
128 | 
129 | #define IS_BKP_DR(DR) (((DR) == BKP_DR1)  || ((DR) == BKP_DR2)  || ((DR) == BKP_DR3)  || \
130 |                        ((DR) == BKP_DR4)  || ((DR) == BKP_DR5)  || ((DR) == BKP_DR6)  || \
131 |                        ((DR) == BKP_DR7)  || ((DR) == BKP_DR8)  || ((DR) == BKP_DR9)  || \
132 |                        ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
133 |                        ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
134 |                        ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
135 |                        ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
136 |                        ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
137 |                        ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
138 |                        ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
139 |                        ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
140 |                        ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
141 |                        ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
142 |                        ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
143 | 
144 | #define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
145 | /**
146 |   * @}
147 |   */
148 | 
149 | /**
150 |   * @}
151 |   */
152 | 
153 | /** @defgroup BKP_Exported_Macros
154 |   * @{
155 |   */
156 | 
157 | /**
158 |   * @}
159 |   */
160 | 
161 | /** @defgroup BKP_Exported_Functions
162 |   * @{
163 |   */
164 | 
165 | void BKP_DeInit(void);
166 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
167 | void BKP_TamperPinCmd(FunctionalState NewState);
168 | void BKP_ITConfig(FunctionalState NewState);
169 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
170 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
171 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
172 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
173 | FlagStatus BKP_GetFlagStatus(void);
174 | void BKP_ClearFlag(void);
175 | ITStatus BKP_GetITStatus(void);
176 | void BKP_ClearITPendingBit(void);
177 | 
178 | #ifdef __cplusplus
179 | }
180 | #endif
181 | 
182 | #endif /* __STM32F10x_BKP_H */
183 | /**
184 |   * @}
185 |   */
186 | 
187 | /**
188 |   * @}
189 |   */
190 | 
191 | /**
192 |   * @}
193 |   */
194 | 
195 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
196 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/inc/misc.h:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    misc.h
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file contains all the functions prototypes for the miscellaneous
  8 |   *          firmware library functions (add-on to CMSIS functions).
  9 |   ******************************************************************************
 10 |   * @attention
 11 |   *
 12 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 13 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 14 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 15 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 16 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 17 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 18 |   *
 19 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 20 |   ******************************************************************************
 21 |   */
 22 | 
 23 | /* Define to prevent recursive inclusion -------------------------------------*/
 24 | #ifndef __MISC_H
 25 | #define __MISC_H
 26 | 
 27 | #ifdef __cplusplus
 28 |  extern "C" {
 29 | #endif
 30 | 
 31 | /* Includes ------------------------------------------------------------------*/
 32 | #include "stm32f10x.h"
 33 | 
 34 | /** @addtogroup STM32F10x_StdPeriph_Driver
 35 |   * @{
 36 |   */
 37 | 
 38 | /** @addtogroup MISC
 39 |   * @{
 40 |   */
 41 | 
 42 | /** @defgroup MISC_Exported_Types
 43 |   * @{
 44 |   */
 45 | 
 46 | /** 
 47 |   * @brief  NVIC Init Structure definition  
 48 |   */
 49 | 
 50 | typedef struct
 51 | {
 52 |   uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
 53 |                                                    This parameter can be a value of @ref IRQn_Type 
 54 |                                                    (For the complete STM32 Devices IRQ Channels list, please
 55 |                                                     refer to stm32f10x.h file) */
 56 | 
 57 |   uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
 58 |                                                    specified in NVIC_IRQChannel. This parameter can be a value
 59 |                                                    between 0 and 15 as described in the table @ref NVIC_Priority_Table */
 60 | 
 61 |   uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
 62 |                                                    in NVIC_IRQChannel. This parameter can be a value
 63 |                                                    between 0 and 15 as described in the table @ref NVIC_Priority_Table */
 64 | 
 65 |   FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
 66 |                                                    will be enabled or disabled. 
 67 |                                                    This parameter can be set either to ENABLE or DISABLE */   
 68 | } NVIC_InitTypeDef;
 69 |  
 70 | /**
 71 |   * @}
 72 |   */
 73 | 
 74 | /** @defgroup NVIC_Priority_Table 
 75 |   * @{
 76 |   */
 77 | 
 78 | /**
 79 | @code  
 80 |  The table below gives the allowed values of the pre-emption priority and subpriority according
 81 |  to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
 82 |   ============================================================================================================================
 83 |     NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
 84 |   ============================================================================================================================
 85 |    NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
 86 |                          |                                   |                             |   4 bits for subpriority
 87 |   ----------------------------------------------------------------------------------------------------------------------------
 88 |    NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
 89 |                          |                                   |                             |   3 bits for subpriority
 90 |   ----------------------------------------------------------------------------------------------------------------------------    
 91 |    NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
 92 |                          |                                   |                             |   2 bits for subpriority
 93 |   ----------------------------------------------------------------------------------------------------------------------------    
 94 |    NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
 95 |                          |                                   |                             |   1 bits for subpriority
 96 |   ----------------------------------------------------------------------------------------------------------------------------    
 97 |    NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
 98 |                          |                                   |                             |   0 bits for subpriority                       
 99 |   ============================================================================================================================
100 | @endcode
101 | */
102 | 
103 | /**
104 |   * @}
105 |   */
106 | 
107 | /** @defgroup MISC_Exported_Constants
108 |   * @{
109 |   */
110 | 
111 | /** @defgroup Vector_Table_Base 
112 |   * @{
113 |   */
114 | 
115 | #define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
116 | #define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
117 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
118 |                                   ((VECTTAB) == NVIC_VectTab_FLASH))
119 | /**
120 |   * @}
121 |   */
122 | 
123 | /** @defgroup System_Low_Power 
124 |   * @{
125 |   */
126 | 
127 | #define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
128 | #define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
129 | #define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
130 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
131 |                         ((LP) == NVIC_LP_SLEEPDEEP) || \
132 |                         ((LP) == NVIC_LP_SLEEPONEXIT))
133 | /**
134 |   * @}
135 |   */
136 | 
137 | /** @defgroup Preemption_Priority_Group 
138 |   * @{
139 |   */
140 | 
141 | #define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
142 |                                                             4 bits for subpriority */
143 | #define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
144 |                                                             3 bits for subpriority */
145 | #define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
146 |                                                             2 bits for subpriority */
147 | #define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
148 |                                                             1 bits for subpriority */
149 | #define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
150 |                                                             0 bits for subpriority */
151 | 
152 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
153 |                                        ((GROUP) == NVIC_PriorityGroup_1) || \
154 |                                        ((GROUP) == NVIC_PriorityGroup_2) || \
155 |                                        ((GROUP) == NVIC_PriorityGroup_3) || \
156 |                                        ((GROUP) == NVIC_PriorityGroup_4))
157 | 
158 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
159 | 
160 | #define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
161 | 
162 | #define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
163 | 
164 | /**
165 |   * @}
166 |   */
167 | 
168 | /** @defgroup SysTick_clock_source 
169 |   * @{
170 |   */
171 | 
172 | #define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
173 | #define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
174 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
175 |                                        ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
176 | /**
177 |   * @}
178 |   */
179 | 
180 | /**
181 |   * @}
182 |   */
183 | 
184 | /** @defgroup MISC_Exported_Macros
185 |   * @{
186 |   */
187 | 
188 | /**
189 |   * @}
190 |   */
191 | 
192 | /** @defgroup MISC_Exported_Functions
193 |   * @{
194 |   */
195 | 
196 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
197 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
198 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
199 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
200 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
201 | 
202 | #ifdef __cplusplus
203 | }
204 | #endif
205 | 
206 | #endif /* __MISC_H */
207 | 
208 | /**
209 |   * @}
210 |   */
211 | 
212 | /**
213 |   * @}
214 |   */
215 | 
216 | /**
217 |   * @}
218 |   */
219 | 
220 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
221 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/stm32f10x_bkp.c:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_bkp.c
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file provides all the BKP firmware functions.
  8 |   ******************************************************************************
  9 |   * @attention
 10 |   *
 11 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 12 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 13 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 14 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 15 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 16 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 17 |   *
 18 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 19 |   ******************************************************************************
 20 |   */
 21 | 
 22 | /* Includes ------------------------------------------------------------------*/
 23 | #include "stm32f10x_bkp.h"
 24 | #include "stm32f10x_rcc.h"
 25 | 
 26 | /** @addtogroup STM32F10x_StdPeriph_Driver
 27 |   * @{
 28 |   */
 29 | 
 30 | /** @defgroup BKP 
 31 |   * @brief BKP driver modules
 32 |   * @{
 33 |   */
 34 | 
 35 | /** @defgroup BKP_Private_TypesDefinitions
 36 |   * @{
 37 |   */
 38 | 
 39 | /**
 40 |   * @}
 41 |   */
 42 | 
 43 | /** @defgroup BKP_Private_Defines
 44 |   * @{
 45 |   */
 46 | 
 47 | /* ------------ BKP registers bit address in the alias region --------------- */
 48 | #define BKP_OFFSET        (BKP_BASE - PERIPH_BASE)
 49 | 
 50 | /* --- CR Register ----*/
 51 | 
 52 | /* Alias word address of TPAL bit */
 53 | #define CR_OFFSET         (BKP_OFFSET + 0x30)
 54 | #define TPAL_BitNumber    0x01
 55 | #define CR_TPAL_BB        (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
 56 | 
 57 | /* Alias word address of TPE bit */
 58 | #define TPE_BitNumber     0x00
 59 | #define CR_TPE_BB         (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
 60 | 
 61 | /* --- CSR Register ---*/
 62 | 
 63 | /* Alias word address of TPIE bit */
 64 | #define CSR_OFFSET        (BKP_OFFSET + 0x34)
 65 | #define TPIE_BitNumber    0x02
 66 | #define CSR_TPIE_BB       (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
 67 | 
 68 | /* Alias word address of TIF bit */
 69 | #define TIF_BitNumber     0x09
 70 | #define CSR_TIF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
 71 | 
 72 | /* Alias word address of TEF bit */
 73 | #define TEF_BitNumber     0x08
 74 | #define CSR_TEF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
 75 | 
 76 | /* ---------------------- BKP registers bit mask ------------------------ */
 77 | 
 78 | /* RTCCR register bit mask */
 79 | #define RTCCR_CAL_MASK    ((uint16_t)0xFF80)
 80 | #define RTCCR_MASK        ((uint16_t)0xFC7F)
 81 | 
 82 | /**
 83 |   * @}
 84 |   */ 
 85 | 
 86 | 
 87 | /** @defgroup BKP_Private_Macros
 88 |   * @{
 89 |   */
 90 | 
 91 | /**
 92 |   * @}
 93 |   */
 94 | 
 95 | /** @defgroup BKP_Private_Variables
 96 |   * @{
 97 |   */
 98 | 
 99 | /**
100 |   * @}
101 |   */
102 | 
103 | /** @defgroup BKP_Private_FunctionPrototypes
104 |   * @{
105 |   */
106 | 
107 | /**
108 |   * @}
109 |   */
110 | 
111 | /** @defgroup BKP_Private_Functions
112 |   * @{
113 |   */
114 | 
115 | /**
116 |   * @brief  Deinitializes the BKP peripheral registers to their default reset values.
117 |   * @param  None
118 |   * @retval None
119 |   */
120 | void BKP_DeInit(void)
121 | {
122 |   RCC_BackupResetCmd(ENABLE);
123 |   RCC_BackupResetCmd(DISABLE);
124 | }
125 | 
126 | /**
127 |   * @brief  Configures the Tamper Pin active level.
128 |   * @param  BKP_TamperPinLevel: specifies the Tamper Pin active level.
129 |   *   This parameter can be one of the following values:
130 |   *     @arg BKP_TamperPinLevel_High: Tamper pin active on high level
131 |   *     @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
132 |   * @retval None
133 |   */
134 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
135 | {
136 |   /* Check the parameters */
137 |   assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
138 |   *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
139 | }
140 | 
141 | /**
142 |   * @brief  Enables or disables the Tamper Pin activation.
143 |   * @param  NewState: new state of the Tamper Pin activation.
144 |   *   This parameter can be: ENABLE or DISABLE.
145 |   * @retval None
146 |   */
147 | void BKP_TamperPinCmd(FunctionalState NewState)
148 | {
149 |   /* Check the parameters */
150 |   assert_param(IS_FUNCTIONAL_STATE(NewState));
151 |   *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
152 | }
153 | 
154 | /**
155 |   * @brief  Enables or disables the Tamper Pin Interrupt.
156 |   * @param  NewState: new state of the Tamper Pin Interrupt.
157 |   *   This parameter can be: ENABLE or DISABLE.
158 |   * @retval None
159 |   */
160 | void BKP_ITConfig(FunctionalState NewState)
161 | {
162 |   /* Check the parameters */
163 |   assert_param(IS_FUNCTIONAL_STATE(NewState));
164 |   *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
165 | }
166 | 
167 | /**
168 |   * @brief  Select the RTC output source to output on the Tamper pin.
169 |   * @param  BKP_RTCOutputSource: specifies the RTC output source.
170 |   *   This parameter can be one of the following values:
171 |   *     @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
172 |   *     @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
173 |   *                                          divided by 64 on the Tamper pin.
174 |   *     @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
175 |   *                                     the Tamper pin.
176 |   *     @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
177 |   *                                      the Tamper pin.  
178 |   * @retval None
179 |   */
180 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
181 | {
182 |   uint16_t tmpreg = 0;
183 |   /* Check the parameters */
184 |   assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
185 |   tmpreg = BKP->RTCCR;
186 |   /* Clear CCO, ASOE and ASOS bits */
187 |   tmpreg &= RTCCR_MASK;
188 |   
189 |   /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
190 |   tmpreg |= BKP_RTCOutputSource;
191 |   /* Store the new value */
192 |   BKP->RTCCR = tmpreg;
193 | }
194 | 
195 | /**
196 |   * @brief  Sets RTC Clock Calibration value.
197 |   * @param  CalibrationValue: specifies the RTC Clock Calibration value.
198 |   *   This parameter must be a number between 0 and 0x7F.
199 |   * @retval None
200 |   */
201 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
202 | {
203 |   uint16_t tmpreg = 0;
204 |   /* Check the parameters */
205 |   assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
206 |   tmpreg = BKP->RTCCR;
207 |   /* Clear CAL[6:0] bits */
208 |   tmpreg &= RTCCR_CAL_MASK;
209 |   /* Set CAL[6:0] bits according to CalibrationValue value */
210 |   tmpreg |= CalibrationValue;
211 |   /* Store the new value */
212 |   BKP->RTCCR = tmpreg;
213 | }
214 | 
215 | /**
216 |   * @brief  Writes user data to the specified Data Backup Register.
217 |   * @param  BKP_DR: specifies the Data Backup Register.
218 |   *   This parameter can be BKP_DRx where x:[1, 42]
219 |   * @param  Data: data to write
220 |   * @retval None
221 |   */
222 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
223 | {
224 |   __IO uint32_t tmp = 0;
225 | 
226 |   /* Check the parameters */
227 |   assert_param(IS_BKP_DR(BKP_DR));
228 | 
229 |   tmp = (uint32_t)BKP_BASE; 
230 |   tmp += BKP_DR;
231 | 
232 |   *(__IO uint32_t *) tmp = Data;
233 | }
234 | 
235 | /**
236 |   * @brief  Reads data from the specified Data Backup Register.
237 |   * @param  BKP_DR: specifies the Data Backup Register.
238 |   *   This parameter can be BKP_DRx where x:[1, 42]
239 |   * @retval The content of the specified Data Backup Register
240 |   */
241 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
242 | {
243 |   __IO uint32_t tmp = 0;
244 | 
245 |   /* Check the parameters */
246 |   assert_param(IS_BKP_DR(BKP_DR));
247 | 
248 |   tmp = (uint32_t)BKP_BASE; 
249 |   tmp += BKP_DR;
250 | 
251 |   return (*(__IO uint16_t *) tmp);
252 | }
253 | 
254 | /**
255 |   * @brief  Checks whether the Tamper Pin Event flag is set or not.
256 |   * @param  None
257 |   * @retval The new state of the Tamper Pin Event flag (SET or RESET).
258 |   */
259 | FlagStatus BKP_GetFlagStatus(void)
260 | {
261 |   return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
262 | }
263 | 
264 | /**
265 |   * @brief  Clears Tamper Pin Event pending flag.
266 |   * @param  None
267 |   * @retval None
268 |   */
269 | void BKP_ClearFlag(void)
270 | {
271 |   /* Set CTE bit to clear Tamper Pin Event flag */
272 |   BKP->CSR |= BKP_CSR_CTE;
273 | }
274 | 
275 | /**
276 |   * @brief  Checks whether the Tamper Pin Interrupt has occurred or not.
277 |   * @param  None
278 |   * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
279 |   */
280 | ITStatus BKP_GetITStatus(void)
281 | {
282 |   return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
283 | }
284 | 
285 | /**
286 |   * @brief  Clears Tamper Pin Interrupt pending bit.
287 |   * @param  None
288 |   * @retval None
289 |   */
290 | void BKP_ClearITPendingBit(void)
291 | {
292 |   /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
293 |   BKP->CSR |= BKP_CSR_CTI;
294 | }
295 | 
296 | /**
297 |   * @}
298 |   */
299 | 
300 | /**
301 |   * @}
302 |   */
303 | 
304 | /**
305 |   * @}
306 |   */
307 | 
308 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
309 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/stm32f10x_pwr.c:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_pwr.c
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file provides all the PWR firmware functions.
  8 |   ******************************************************************************
  9 |   * @attention
 10 |   *
 11 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 12 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 13 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 14 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 15 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 16 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 17 |   *
 18 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 19 |   ******************************************************************************
 20 |   */
 21 | 
 22 | /* Includes ------------------------------------------------------------------*/
 23 | #include "stm32f10x_pwr.h"
 24 | #include "stm32f10x_rcc.h"
 25 | 
 26 | /** @addtogroup STM32F10x_StdPeriph_Driver
 27 |   * @{
 28 |   */
 29 | 
 30 | /** @defgroup PWR 
 31 |   * @brief PWR driver modules
 32 |   * @{
 33 |   */ 
 34 | 
 35 | /** @defgroup PWR_Private_TypesDefinitions
 36 |   * @{
 37 |   */
 38 | 
 39 | /**
 40 |   * @}
 41 |   */
 42 | 
 43 | /** @defgroup PWR_Private_Defines
 44 |   * @{
 45 |   */
 46 | 
 47 | /* --------- PWR registers bit address in the alias region ---------- */
 48 | #define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
 49 | 
 50 | /* --- CR Register ---*/
 51 | 
 52 | /* Alias word address of DBP bit */
 53 | #define CR_OFFSET                (PWR_OFFSET + 0x00)
 54 | #define DBP_BitNumber            0x08
 55 | #define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
 56 | 
 57 | /* Alias word address of PVDE bit */
 58 | #define PVDE_BitNumber           0x04
 59 | #define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
 60 | 
 61 | /* --- CSR Register ---*/
 62 | 
 63 | /* Alias word address of EWUP bit */
 64 | #define CSR_OFFSET               (PWR_OFFSET + 0x04)
 65 | #define EWUP_BitNumber           0x08
 66 | #define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
 67 | 
 68 | /* ------------------ PWR registers bit mask ------------------------ */
 69 | 
 70 | /* CR register bit mask */
 71 | #define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
 72 | #define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
 73 | 
 74 | 
 75 | /**
 76 |   * @}
 77 |   */
 78 | 
 79 | /** @defgroup PWR_Private_Macros
 80 |   * @{
 81 |   */
 82 | 
 83 | /**
 84 |   * @}
 85 |   */
 86 | 
 87 | /** @defgroup PWR_Private_Variables
 88 |   * @{
 89 |   */
 90 | 
 91 | /**
 92 |   * @}
 93 |   */
 94 | 
 95 | /** @defgroup PWR_Private_FunctionPrototypes
 96 |   * @{
 97 |   */
 98 | 
 99 | /**
100 |   * @}
101 |   */
102 | 
103 | /** @defgroup PWR_Private_Functions
104 |   * @{
105 |   */
106 | 
107 | /**
108 |   * @brief  Deinitializes the PWR peripheral registers to their default reset values.
109 |   * @param  None
110 |   * @retval None
111 |   */
112 | void PWR_DeInit(void)
113 | {
114 |   RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
115 |   RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
116 | }
117 | 
118 | /**
119 |   * @brief  Enables or disables access to the RTC and backup registers.
120 |   * @param  NewState: new state of the access to the RTC and backup registers.
121 |   *   This parameter can be: ENABLE or DISABLE.
122 |   * @retval None
123 |   */
124 | void PWR_BackupAccessCmd(FunctionalState NewState)
125 | {
126 |   /* Check the parameters */
127 |   assert_param(IS_FUNCTIONAL_STATE(NewState));
128 |   *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
129 | }
130 | 
131 | /**
132 |   * @brief  Enables or disables the Power Voltage Detector(PVD).
133 |   * @param  NewState: new state of the PVD.
134 |   *   This parameter can be: ENABLE or DISABLE.
135 |   * @retval None
136 |   */
137 | void PWR_PVDCmd(FunctionalState NewState)
138 | {
139 |   /* Check the parameters */
140 |   assert_param(IS_FUNCTIONAL_STATE(NewState));
141 |   *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
142 | }
143 | 
144 | /**
145 |   * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
146 |   * @param  PWR_PVDLevel: specifies the PVD detection level
147 |   *   This parameter can be one of the following values:
148 |   *     @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
149 |   *     @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
150 |   *     @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
151 |   *     @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
152 |   *     @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
153 |   *     @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
154 |   *     @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
155 |   *     @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
156 |   * @retval None
157 |   */
158 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
159 | {
160 |   uint32_t tmpreg = 0;
161 |   /* Check the parameters */
162 |   assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
163 |   tmpreg = PWR->CR;
164 |   /* Clear PLS[7:5] bits */
165 |   tmpreg &= CR_PLS_MASK;
166 |   /* Set PLS[7:5] bits according to PWR_PVDLevel value */
167 |   tmpreg |= PWR_PVDLevel;
168 |   /* Store the new value */
169 |   PWR->CR = tmpreg;
170 | }
171 | 
172 | /**
173 |   * @brief  Enables or disables the WakeUp Pin functionality.
174 |   * @param  NewState: new state of the WakeUp Pin functionality.
175 |   *   This parameter can be: ENABLE or DISABLE.
176 |   * @retval None
177 |   */
178 | void PWR_WakeUpPinCmd(FunctionalState NewState)
179 | {
180 |   /* Check the parameters */
181 |   assert_param(IS_FUNCTIONAL_STATE(NewState));
182 |   *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
183 | }
184 | 
185 | /**
186 |   * @brief  Enters STOP mode.
187 |   * @param  PWR_Regulator: specifies the regulator state in STOP mode.
188 |   *   This parameter can be one of the following values:
189 |   *     @arg PWR_Regulator_ON: STOP mode with regulator ON
190 |   *     @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
191 |   * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
192 |   *   This parameter can be one of the following values:
193 |   *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
194 |   *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
195 |   * @retval None
196 |   */
197 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
198 | {
199 |   uint32_t tmpreg = 0;
200 |   /* Check the parameters */
201 |   assert_param(IS_PWR_REGULATOR(PWR_Regulator));
202 |   assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
203 |   
204 |   /* Select the regulator state in STOP mode ---------------------------------*/
205 |   tmpreg = PWR->CR;
206 |   /* Clear PDDS and LPDS bits */
207 |   tmpreg &= CR_DS_MASK;
208 |   /* Set LPDS bit according to PWR_Regulator value */
209 |   tmpreg |= PWR_Regulator;
210 |   /* Store the new value */
211 |   PWR->CR = tmpreg;
212 |   /* Set SLEEPDEEP bit of Cortex System Control Register */
213 |   SCB->SCR |= SCB_SCR_SLEEPDEEP;
214 |   
215 |   /* Select STOP mode entry --------------------------------------------------*/
216 |   if(PWR_STOPEntry == PWR_STOPEntry_WFI)
217 |   {   
218 |     /* Request Wait For Interrupt */
219 |     __WFI();
220 |   }
221 |   else
222 |   {
223 |     /* Request Wait For Event */
224 |     __WFE();
225 |   }
226 |   
227 |   /* Reset SLEEPDEEP bit of Cortex System Control Register */
228 |   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);  
229 | }
230 | 
231 | /**
232 |   * @brief  Enters STANDBY mode.
233 |   * @param  None
234 |   * @retval None
235 |   */
236 | void PWR_EnterSTANDBYMode(void)
237 | {
238 |   /* Clear Wake-up flag */
239 |   PWR->CR |= PWR_CR_CWUF;
240 |   /* Select STANDBY mode */
241 |   PWR->CR |= PWR_CR_PDDS;
242 |   /* Set SLEEPDEEP bit of Cortex System Control Register */
243 |   SCB->SCR |= SCB_SCR_SLEEPDEEP;
244 | /* This option is used to ensure that store operations are completed */
245 | #if defined ( __CC_ARM   )
246 |   __force_stores();
247 | #endif
248 |   /* Request Wait For Interrupt */
249 |   __WFI();
250 | }
251 | 
252 | /**
253 |   * @brief  Checks whether the specified PWR flag is set or not.
254 |   * @param  PWR_FLAG: specifies the flag to check.
255 |   *   This parameter can be one of the following values:
256 |   *     @arg PWR_FLAG_WU: Wake Up flag
257 |   *     @arg PWR_FLAG_SB: StandBy flag
258 |   *     @arg PWR_FLAG_PVDO: PVD Output
259 |   * @retval The new state of PWR_FLAG (SET or RESET).
260 |   */
261 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
262 | {
263 |   FlagStatus bitstatus = RESET;
264 |   /* Check the parameters */
265 |   assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
266 |   
267 |   if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
268 |   {
269 |     bitstatus = SET;
270 |   }
271 |   else
272 |   {
273 |     bitstatus = RESET;
274 |   }
275 |   /* Return the flag status */
276 |   return bitstatus;
277 | }
278 | 
279 | /**
280 |   * @brief  Clears the PWR's pending flags.
281 |   * @param  PWR_FLAG: specifies the flag to clear.
282 |   *   This parameter can be one of the following values:
283 |   *     @arg PWR_FLAG_WU: Wake Up flag
284 |   *     @arg PWR_FLAG_SB: StandBy flag
285 |   * @retval None
286 |   */
287 | void PWR_ClearFlag(uint32_t PWR_FLAG)
288 | {
289 |   /* Check the parameters */
290 |   assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
291 |          
292 |   PWR->CR |=  PWR_FLAG << 2;
293 | }
294 | 
295 | /**
296 |   * @}
297 |   */
298 | 
299 | /**
300 |   * @}
301 |   */
302 | 
303 | /**
304 |   * @}
305 |   */
306 | 
307 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
308 | 


--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/stm32f10x_rtc.c:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_rtc.c
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file provides all the RTC firmware functions.
  8 |   ******************************************************************************
  9 |   * @attention
 10 |   *
 11 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 12 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 13 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 14 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 15 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 16 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 17 |   *
 18 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 19 |   ******************************************************************************
 20 |   */
 21 | 
 22 | /* Includes ------------------------------------------------------------------*/
 23 | #include "stm32f10x_rtc.h"
 24 | 
 25 | /** @addtogroup STM32F10x_StdPeriph_Driver
 26 |   * @{
 27 |   */
 28 | 
 29 | /** @defgroup RTC 
 30 |   * @brief RTC driver modules
 31 |   * @{
 32 |   */
 33 | 
 34 | /** @defgroup RTC_Private_TypesDefinitions
 35 |   * @{
 36 |   */ 
 37 | /**
 38 |   * @}
 39 |   */
 40 | 
 41 | /** @defgroup RTC_Private_Defines
 42 |   * @{
 43 |   */
 44 | #define RTC_LSB_MASK     ((uint32_t)0x0000FFFF)  /*!< RTC LSB Mask */
 45 | #define PRLH_MSB_MASK    ((uint32_t)0x000F0000)  /*!< RTC Prescaler MSB Mask */
 46 | 
 47 | /**
 48 |   * @}
 49 |   */
 50 | 
 51 | /** @defgroup RTC_Private_Macros
 52 |   * @{
 53 |   */
 54 | 
 55 | /**
 56 |   * @}
 57 |   */
 58 | 
 59 | /** @defgroup RTC_Private_Variables
 60 |   * @{
 61 |   */
 62 | 
 63 | /**
 64 |   * @}
 65 |   */
 66 | 
 67 | /** @defgroup RTC_Private_FunctionPrototypes
 68 |   * @{
 69 |   */
 70 | 
 71 | /**
 72 |   * @}
 73 |   */
 74 | 
 75 | /** @defgroup RTC_Private_Functions
 76 |   * @{
 77 |   */
 78 | 
 79 | /**
 80 |   * @brief  Enables or disables the specified RTC interrupts.
 81 |   * @param  RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
 82 |   *   This parameter can be any combination of the following values:
 83 |   *     @arg RTC_IT_OW: Overflow interrupt
 84 |   *     @arg RTC_IT_ALR: Alarm interrupt
 85 |   *     @arg RTC_IT_SEC: Second interrupt
 86 |   * @param  NewState: new state of the specified RTC interrupts.
 87 |   *   This parameter can be: ENABLE or DISABLE.
 88 |   * @retval None
 89 |   */
 90 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
 91 | {
 92 |   /* Check the parameters */
 93 |   assert_param(IS_RTC_IT(RTC_IT));  
 94 |   assert_param(IS_FUNCTIONAL_STATE(NewState));
 95 |   
 96 |   if (NewState != DISABLE)
 97 |   {
 98 |     RTC->CRH |= RTC_IT;
 99 |   }
100 |   else
101 |   {
102 |     RTC->CRH &= (uint16_t)~RTC_IT;
103 |   }
104 | }
105 | 
106 | /**
107 |   * @brief  Enters the RTC configuration mode.
108 |   * @param  None
109 |   * @retval None
110 |   */
111 | void RTC_EnterConfigMode(void)
112 | {
113 |   /* Set the CNF flag to enter in the Configuration Mode */
114 |   RTC->CRL |= RTC_CRL_CNF;
115 | }
116 | 
117 | /**
118 |   * @brief  Exits from the RTC configuration mode.
119 |   * @param  None
120 |   * @retval None
121 |   */
122 | void RTC_ExitConfigMode(void)
123 | {
124 |   /* Reset the CNF flag to exit from the Configuration Mode */
125 |   RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); 
126 | }
127 | 
128 | /**
129 |   * @brief  Gets the RTC counter value.
130 |   * @param  None
131 |   * @retval RTC counter value.
132 |   */
133 | uint32_t RTC_GetCounter(void)
134 | {
135 |   uint16_t tmp = 0;
136 |   tmp = RTC->CNTL;
137 |   return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
138 | }
139 | 
140 | /**
141 |   * @brief  Sets the RTC counter value.
142 |   * @param  CounterValue: RTC counter new value.
143 |   * @retval None
144 |   */
145 | void RTC_SetCounter(uint32_t CounterValue)
146 | { 
147 |   RTC_EnterConfigMode();
148 |   /* Set RTC COUNTER MSB word */
149 |   RTC->CNTH = CounterValue >> 16;
150 |   /* Set RTC COUNTER LSB word */
151 |   RTC->CNTL = (CounterValue & RTC_LSB_MASK);
152 |   RTC_ExitConfigMode();
153 | }
154 | 
155 | /**
156 |   * @brief  Sets the RTC prescaler value.
157 |   * @param  PrescalerValue: RTC prescaler new value.
158 |   * @retval None
159 |   */
160 | void RTC_SetPrescaler(uint32_t PrescalerValue)
161 | {
162 |   /* Check the parameters */
163 |   assert_param(IS_RTC_PRESCALER(PrescalerValue));
164 |   
165 |   RTC_EnterConfigMode();
166 |   /* Set RTC PRESCALER MSB word */
167 |   RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
168 |   /* Set RTC PRESCALER LSB word */
169 |   RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
170 |   RTC_ExitConfigMode();
171 | }
172 | 
173 | /**
174 |   * @brief  Sets the RTC alarm value.
175 |   * @param  AlarmValue: RTC alarm new value.
176 |   * @retval None
177 |   */
178 | void RTC_SetAlarm(uint32_t AlarmValue)
179 | {  
180 |   RTC_EnterConfigMode();
181 |   /* Set the ALARM MSB word */
182 |   RTC->ALRH = AlarmValue >> 16;
183 |   /* Set the ALARM LSB word */
184 |   RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
185 |   RTC_ExitConfigMode();
186 | }
187 | 
188 | /**
189 |   * @brief  Gets the RTC divider value.
190 |   * @param  None
191 |   * @retval RTC Divider value.
192 |   */
193 | uint32_t RTC_GetDivider(void)
194 | {
195 |   uint32_t tmp = 0x00;
196 |   tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
197 |   tmp |= RTC->DIVL;
198 |   return tmp;
199 | }
200 | 
201 | /**
202 |   * @brief  Waits until last write operation on RTC registers has finished.
203 |   * @note   This function must be called before any write to RTC registers.
204 |   * @param  None
205 |   * @retval None
206 |   */
207 | void RTC_WaitForLastTask(void)
208 | {
209 |   /* Loop until RTOFF flag is set */
210 |   while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
211 |   {
212 |   }
213 | }
214 | 
215 | /**
216 |   * @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
217 |   *   are synchronized with RTC APB clock.
218 |   * @note   This function must be called before any read operation after an APB reset
219 |   *   or an APB clock stop.
220 |   * @param  None
221 |   * @retval None
222 |   */
223 | void RTC_WaitForSynchro(void)
224 | {
225 |   /* Clear RSF flag */
226 |   RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
227 |   /* Loop until RSF flag is set */
228 |   while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
229 |   {
230 |   }
231 | }
232 | 
233 | /**
234 |   * @brief  Checks whether the specified RTC flag is set or not.
235 |   * @param  RTC_FLAG: specifies the flag to check.
236 |   *   This parameter can be one the following values:
237 |   *     @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
238 |   *     @arg RTC_FLAG_RSF: Registers Synchronized flag
239 |   *     @arg RTC_FLAG_OW: Overflow flag
240 |   *     @arg RTC_FLAG_ALR: Alarm flag
241 |   *     @arg RTC_FLAG_SEC: Second flag
242 |   * @retval The new state of RTC_FLAG (SET or RESET).
243 |   */
244 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
245 | {
246 |   FlagStatus bitstatus = RESET;
247 |   
248 |   /* Check the parameters */
249 |   assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); 
250 |   
251 |   if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
252 |   {
253 |     bitstatus = SET;
254 |   }
255 |   else
256 |   {
257 |     bitstatus = RESET;
258 |   }
259 |   return bitstatus;
260 | }
261 | 
262 | /**
263 |   * @brief  Clears the RTC's pending flags.
264 |   * @param  RTC_FLAG: specifies the flag to clear.
265 |   *   This parameter can be any combination of the following values:
266 |   *     @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
267 |   *                        an APB reset or an APB Clock stop.
268 |   *     @arg RTC_FLAG_OW: Overflow flag
269 |   *     @arg RTC_FLAG_ALR: Alarm flag
270 |   *     @arg RTC_FLAG_SEC: Second flag
271 |   * @retval None
272 |   */
273 | void RTC_ClearFlag(uint16_t RTC_FLAG)
274 | {
275 |   /* Check the parameters */
276 |   assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); 
277 |     
278 |   /* Clear the corresponding RTC flag */
279 |   RTC->CRL &= (uint16_t)~RTC_FLAG;
280 | }
281 | 
282 | /**
283 |   * @brief  Checks whether the specified RTC interrupt has occurred or not.
284 |   * @param  RTC_IT: specifies the RTC interrupts sources to check.
285 |   *   This parameter can be one of the following values:
286 |   *     @arg RTC_IT_OW: Overflow interrupt
287 |   *     @arg RTC_IT_ALR: Alarm interrupt
288 |   *     @arg RTC_IT_SEC: Second interrupt
289 |   * @retval The new state of the RTC_IT (SET or RESET).
290 |   */
291 | ITStatus RTC_GetITStatus(uint16_t RTC_IT)
292 | {
293 |   ITStatus bitstatus = RESET;
294 |   /* Check the parameters */
295 |   assert_param(IS_RTC_GET_IT(RTC_IT)); 
296 |   
297 |   bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
298 |   if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
299 |   {
300 |     bitstatus = SET;
301 |   }
302 |   else
303 |   {
304 |     bitstatus = RESET;
305 |   }
306 |   return bitstatus;
307 | }
308 | 
309 | /**
310 |   * @brief  Clears the RTC's interrupt pending bits.
311 |   * @param  RTC_IT: specifies the interrupt pending bit to clear.
312 |   *   This parameter can be any combination of the following values:
313 |   *     @arg RTC_IT_OW: Overflow interrupt
314 |   *     @arg RTC_IT_ALR: Alarm interrupt
315 |   *     @arg RTC_IT_SEC: Second interrupt
316 |   * @retval None
317 |   */
318 | void RTC_ClearITPendingBit(uint16_t RTC_IT)
319 | {
320 |   /* Check the parameters */
321 |   assert_param(IS_RTC_IT(RTC_IT));  
322 |   
323 |   /* Clear the corresponding RTC pending bit */
324 |   RTC->CRL &= (uint16_t)~RTC_IT;
325 | }
326 | 
327 | /**
328 |   * @}
329 |   */
330 | 
331 | /**
332 |   * @}
333 |   */
334 | 
335 | /**
336 |   * @}
337 |   */
338 | 
339 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
340 | 


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--------------------------------------------------------------------------------
/STM32F10x_FWLib/src/stm32f10x_cec.c:
--------------------------------------------------------------------------------
  1 | /**
  2 |   ******************************************************************************
  3 |   * @file    stm32f10x_cec.c
  4 |   * @author  MCD Application Team
  5 |   * @version V3.5.0
  6 |   * @date    11-March-2011
  7 |   * @brief   This file provides all the CEC firmware functions.
  8 |   ******************************************************************************
  9 |   * @attention
 10 |   *
 11 |   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 12 |   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 13 |   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 14 |   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 15 |   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 16 |   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 17 |   *
 18 |   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 19 |   ******************************************************************************
 20 |   */
 21 | 
 22 | /* Includes ------------------------------------------------------------------*/
 23 | #include "stm32f10x_cec.h"
 24 | #include "stm32f10x_rcc.h"
 25 | 
 26 | /** @addtogroup STM32F10x_StdPeriph_Driver
 27 |   * @{
 28 |   */
 29 | 
 30 | /** @defgroup CEC 
 31 |   * @brief CEC driver modules
 32 |   * @{
 33 |   */
 34 | 
 35 | /** @defgroup CEC_Private_TypesDefinitions
 36 |   * @{
 37 |   */
 38 | 
 39 | /**
 40 |   * @}
 41 |   */
 42 | 
 43 | 
 44 | /** @defgroup CEC_Private_Defines
 45 |   * @{
 46 |   */ 
 47 | 
 48 | /* ------------ CEC registers bit address in the alias region ----------- */
 49 | #define CEC_OFFSET                (CEC_BASE - PERIPH_BASE)
 50 | 
 51 | /* --- CFGR Register ---*/
 52 | 
 53 | /* Alias word address of PE bit */
 54 | #define CFGR_OFFSET                 (CEC_OFFSET + 0x00)
 55 | #define PE_BitNumber                0x00
 56 | #define CFGR_PE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
 57 | 
 58 | /* Alias word address of IE bit */
 59 | #define IE_BitNumber                0x01
 60 | #define CFGR_IE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
 61 | 
 62 | /* --- CSR Register ---*/
 63 | 
 64 | /* Alias word address of TSOM bit */
 65 | #define CSR_OFFSET                  (CEC_OFFSET + 0x10)
 66 | #define TSOM_BitNumber              0x00
 67 | #define CSR_TSOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
 68 | 
 69 | /* Alias word address of TEOM bit */
 70 | #define TEOM_BitNumber              0x01
 71 | #define CSR_TEOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
 72 |   
 73 | #define CFGR_CLEAR_Mask            (uint8_t)(0xF3)        /* CFGR register Mask */
 74 | #define FLAG_Mask                  ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
 75 |  
 76 | /**
 77 |   * @}
 78 |   */ 
 79 | 
 80 | 
 81 | /** @defgroup CEC_Private_Macros
 82 |   * @{
 83 |   */ 
 84 | 
 85 | /**
 86 |   * @}
 87 |   */ 
 88 | 
 89 | 
 90 | /** @defgroup CEC_Private_Variables
 91 |   * @{
 92 |   */ 
 93 | 
 94 | /**
 95 |   * @}
 96 |   */ 
 97 | 
 98 | 
 99 | /** @defgroup CEC_Private_FunctionPrototypes
100 |   * @{
101 |   */
102 |  
103 | /**
104 |   * @}
105 |   */ 
106 | 
107 | 
108 | /** @defgroup CEC_Private_Functions
109 |   * @{
110 |   */ 
111 | 
112 | /**
113 |   * @brief  Deinitializes the CEC peripheral registers to their default reset 
114 |   *         values.
115 |   * @param  None
116 |   * @retval None
117 |   */
118 | void CEC_DeInit(void)
119 | {
120 |   /* Enable CEC reset state */
121 |   RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);  
122 |   /* Release CEC from reset state */
123 |   RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 
124 | }
125 | 
126 | 
127 | /**
128 |   * @brief  Initializes the CEC peripheral according to the specified 
129 |   *         parameters in the CEC_InitStruct.
130 |   * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
131 |   *         contains the configuration information for the specified
132 |   *         CEC peripheral.
133 |   * @retval None
134 |   */
135 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
136 | {
137 |   uint16_t tmpreg = 0;
138 |  
139 |   /* Check the parameters */
140 |   assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 
141 |   assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
142 |      
143 |   /*---------------------------- CEC CFGR Configuration -----------------*/
144 |   /* Get the CEC CFGR value */
145 |   tmpreg = CEC->CFGR;
146 |   
147 |   /* Clear BTEM and BPEM bits */
148 |   tmpreg &= CFGR_CLEAR_Mask;
149 |   
150 |   /* Configure CEC: Bit Timing Error and Bit Period Error */
151 |   tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
152 | 
153 |   /* Write to CEC CFGR  register*/
154 |   CEC->CFGR = tmpreg;
155 |   
156 | }
157 | 
158 | /**
159 |   * @brief  Enables or disables the specified CEC peripheral.
160 |   * @param  NewState: new state of the CEC peripheral. 
161 |   *     This parameter can be: ENABLE or DISABLE.
162 |   * @retval None
163 |   */
164 | void CEC_Cmd(FunctionalState NewState)
165 | {
166 |   /* Check the parameters */
167 |   assert_param(IS_FUNCTIONAL_STATE(NewState));
168 | 
169 |   *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
170 | 
171 |   if(NewState == DISABLE)
172 |   {
173 |     /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
174 |     while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
175 |     {
176 |     }  
177 |   }  
178 | }
179 | 
180 | /**
181 |   * @brief  Enables or disables the CEC interrupt.
182 |   * @param  NewState: new state of the CEC interrupt.
183 |   *   This parameter can be: ENABLE or DISABLE.
184 |   * @retval None
185 |   */
186 | void CEC_ITConfig(FunctionalState NewState)
187 | {
188 |   /* Check the parameters */
189 |   assert_param(IS_FUNCTIONAL_STATE(NewState));
190 | 
191 |   *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
192 | }
193 | 
194 | /**
195 |   * @brief  Defines the Own Address of the CEC device.
196 |   * @param  CEC_OwnAddress: The CEC own address
197 |   * @retval None
198 |   */
199 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
200 | {
201 |   /* Check the parameters */
202 |   assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
203 | 
204 |   /* Set the CEC own address */
205 |   CEC->OAR = CEC_OwnAddress;
206 | }
207 | 
208 | /**
209 |   * @brief  Sets the CEC prescaler value.
210 |   * @param  CEC_Prescaler: CEC prescaler new value
211 |   * @retval None
212 |   */
213 | void CEC_SetPrescaler(uint16_t CEC_Prescaler)
214 | {
215 |   /* Check the parameters */
216 |   assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
217 | 
218 |   /* Set the  Prescaler value*/
219 |   CEC->PRES = CEC_Prescaler;
220 | }
221 | 
222 | /**
223 |   * @brief  Transmits single data through the CEC peripheral.
224 |   * @param  Data: the data to transmit.
225 |   * @retval None
226 |   */
227 | void CEC_SendDataByte(uint8_t Data)
228 | {  
229 |   /* Transmit Data */
230 |   CEC->TXD = Data ;
231 | }
232 | 
233 | 
234 | /**
235 |   * @brief  Returns the most recent received data by the CEC peripheral.
236 |   * @param  None
237 |   * @retval The received data.
238 |   */
239 | uint8_t CEC_ReceiveDataByte(void)
240 | {
241 |   /* Receive Data */
242 |   return (uint8_t)(CEC->RXD);
243 | }
244 | 
245 | /**
246 |   * @brief  Starts a new message.
247 |   * @param  None
248 |   * @retval None
249 |   */
250 | void CEC_StartOfMessage(void)
251 | {  
252 |   /* Starts of new message */
253 |   *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
254 | }
255 | 
256 | /**
257 |   * @brief  Transmits message with or without an EOM bit.
258 |   * @param  NewState: new state of the CEC Tx End Of Message. 
259 |   *     This parameter can be: ENABLE or DISABLE.
260 |   * @retval None
261 |   */
262 | void CEC_EndOfMessageCmd(FunctionalState NewState)
263 | {   
264 |   /* Check the parameters */
265 |   assert_param(IS_FUNCTIONAL_STATE(NewState));
266 |   
267 |   /* The data byte will be transmitted with or without an EOM bit*/
268 |   *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
269 | }
270 | 
271 | /**
272 |   * @brief  Gets the CEC flag status
273 |   * @param  CEC_FLAG: specifies the CEC flag to check. 
274 |   *   This parameter can be one of the following values:
275 |   *     @arg CEC_FLAG_BTE: Bit Timing Error
276 |   *     @arg CEC_FLAG_BPE: Bit Period Error
277 |   *     @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
278 |   *     @arg CEC_FLAG_SBE: Start Bit Error
279 |   *     @arg CEC_FLAG_ACKE: Block Acknowledge Error
280 |   *     @arg CEC_FLAG_LINE: Line Error
281 |   *     @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
282 |   *     @arg CEC_FLAG_TEOM: Tx End Of Message 
283 |   *     @arg CEC_FLAG_TERR: Tx Error
284 |   *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
285 |   *     @arg CEC_FLAG_RSOM: Rx Start Of Message
286 |   *     @arg CEC_FLAG_REOM: Rx End Of Message
287 |   *     @arg CEC_FLAG_RERR: Rx Error
288 |   *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
289 |   * @retval The new state of CEC_FLAG (SET or RESET)
290 |   */
291 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) 
292 | {
293 |   FlagStatus bitstatus = RESET;
294 |   uint32_t cecreg = 0, cecbase = 0;
295 |   
296 |   /* Check the parameters */
297 |   assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
298 |  
299 |   /* Get the CEC peripheral base address */
300 |   cecbase = (uint32_t)(CEC_BASE);
301 |   
302 |   /* Read flag register index */
303 |   cecreg = CEC_FLAG >> 28;
304 |   
305 |   /* Get bit[23:0] of the flag */
306 |   CEC_FLAG &= FLAG_Mask;
307 |   
308 |   if(cecreg != 0)
309 |   {
310 |     /* Flag in CEC ESR Register */
311 |     CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
312 |     
313 |     /* Get the CEC ESR register address */
314 |     cecbase += 0xC;
315 |   }
316 |   else
317 |   {
318 |     /* Get the CEC CSR register address */
319 |     cecbase += 0x10;
320 |   }
321 |   
322 |   if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
323 |   {
324 |     /* CEC_FLAG is set */
325 |     bitstatus = SET;
326 |   }
327 |   else
328 |   {
329 |     /* CEC_FLAG is reset */
330 |     bitstatus = RESET;
331 |   }
332 |   
333 |   /* Return the CEC_FLAG status */
334 |   return  bitstatus;
335 | }
336 | 
337 | /**
338 |   * @brief  Clears the CEC's pending flags.
339 |   * @param  CEC_FLAG: specifies the flag to clear. 
340 |   *   This parameter can be any combination of the following values:
341 |   *     @arg CEC_FLAG_TERR: Tx Error
342 |   *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
343 |   *     @arg CEC_FLAG_RSOM: Rx Start Of Message
344 |   *     @arg CEC_FLAG_REOM: Rx End Of Message
345 |   *     @arg CEC_FLAG_RERR: Rx Error
346 |   *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
347 |   * @retval None
348 |   */
349 | void CEC_ClearFlag(uint32_t CEC_FLAG)
350 | { 
351 |   uint32_t tmp = 0x0;
352 |   
353 |   /* Check the parameters */
354 |   assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
355 | 
356 |   tmp = CEC->CSR & 0x2;
357 |        
358 |   /* Clear the selected CEC flags */
359 |   CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
360 | }
361 | 
362 | /**
363 |   * @brief  Checks whether the specified CEC interrupt has occurred or not.
364 |   * @param  CEC_IT: specifies the CEC interrupt source to check. 
365 |   *   This parameter can be one of the following values:
366 |   *     @arg CEC_IT_TERR: Tx Error
367 |   *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
368 |   *     @arg CEC_IT_RERR: Rx Error
369 |   *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
370 |   * @retval The new state of CEC_IT (SET or RESET).
371 |   */
372 | ITStatus CEC_GetITStatus(uint8_t CEC_IT)
373 | {
374 |   ITStatus bitstatus = RESET;
375 |   uint32_t enablestatus = 0;
376 |   
377 |   /* Check the parameters */
378 |    assert_param(IS_CEC_GET_IT(CEC_IT));
379 |    
380 |   /* Get the CEC IT enable bit status */
381 |   enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
382 |   
383 |   /* Check the status of the specified CEC interrupt */
384 |   if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
385 |   {
386 |     /* CEC_IT is set */
387 |     bitstatus = SET;
388 |   }
389 |   else
390 |   {
391 |     /* CEC_IT is reset */
392 |     bitstatus = RESET;
393 |   }
394 |   /* Return the CEC_IT status */
395 |   return  bitstatus;
396 | }
397 | 
398 | /**
399 |   * @brief  Clears the CEC's interrupt pending bits.
400 |   * @param  CEC_IT: specifies the CEC interrupt pending bit to clear.
401 |   *   This parameter can be any combination of the following values:
402 |   *     @arg CEC_IT_TERR: Tx Error
403 |   *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
404 |   *     @arg CEC_IT_RERR: Rx Error
405 |   *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
406 |   * @retval None
407 |   */
408 | void CEC_ClearITPendingBit(uint16_t CEC_IT)
409 | {
410 |   uint32_t tmp = 0x0;
411 |   
412 |   /* Check the parameters */
413 |   assert_param(IS_CEC_GET_IT(CEC_IT));
414 |   
415 |   tmp = CEC->CSR & 0x2;
416 |   
417 |   /* Clear the selected CEC interrupt pending bits */
418 |   CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
419 | }
420 | 
421 | /**
422 |   * @}
423 |   */ 
424 | 
425 | /**
426 |   * @}
427 |   */ 
428 | 
429 | /**
430 |   * @}
431 |   */ 
432 | 
433 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
434 | 


--------------------------------------------------------------------------------
/CORE/startup_stm32f10x_md.s:
--------------------------------------------------------------------------------
  1 | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
  2 | ;* File Name          : startup_stm32f10x_md.s
  3 | ;* Author             : MCD Application Team
  4 | ;* Version            : V3.5.0
  5 | ;* Date               : 11-March-2011
  6 | ;* Description        : STM32F10x Medium Density Devices vector table for MDK-ARM 
  7 | ;*                      toolchain.  
  8 | ;*                      This module performs:
  9 | ;*                      - Set the initial SP
 10 | ;*                      - Set the initial PC == Reset_Handler
 11 | ;*                      - Set the vector table entries with the exceptions ISR address
 12 | ;*                      - Configure the clock system
 13 | ;*                      - Branches to __main in the C library (which eventually
 14 | ;*                        calls main()).
 15 | ;*                      After Reset the CortexM3 processor is in Thread mode,
 16 | ;*                      priority is Privileged, and the Stack is set to Main.
 17 | ;* <<< Use Configuration Wizard in Context Menu >>>   
 18 | ;*******************************************************************************
 19 | ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 20 | ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
 21 | ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
 22 | ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
 23 | ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
 24 | ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 25 | ;*******************************************************************************
 26 | 
 27 | ; Amount of memory (in bytes) allocated for Stack
 28 | ; Tailor this value to your application needs
 29 | ; <h> Stack Configuration
 30 | ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 31 | ; </h>
 32 | 
 33 | Stack_Size      EQU     0x00000400
 34 | 
 35 |                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 36 | Stack_Mem       SPACE   Stack_Size
 37 | __initial_sp
 38 | 
 39 | 
 40 | ; <h> Heap Configuration
 41 | ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 42 | ; </h>
 43 | 
 44 | Heap_Size       EQU     0x00000200
 45 | 
 46 |                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 47 | __heap_base
 48 | Heap_Mem        SPACE   Heap_Size
 49 | __heap_limit
 50 | 
 51 |                 PRESERVE8
 52 |                 THUMB
 53 | 
 54 | 
 55 | ; Vector Table Mapped to Address 0 at Reset
 56 |                 AREA    RESET, DATA, READONLY
 57 |                 EXPORT  __Vectors
 58 |                 EXPORT  __Vectors_End
 59 |                 EXPORT  __Vectors_Size
 60 | 
 61 | __Vectors       DCD     __initial_sp               ; Top of Stack
 62 |                 DCD     Reset_Handler              ; Reset Handler
 63 |                 DCD     NMI_Handler                ; NMI Handler
 64 |                 DCD     HardFault_Handler          ; Hard Fault Handler
 65 |                 DCD     MemManage_Handler          ; MPU Fault Handler
 66 |                 DCD     BusFault_Handler           ; Bus Fault Handler
 67 |                 DCD     UsageFault_Handler         ; Usage Fault Handler
 68 |                 DCD     0                          ; Reserved
 69 |                 DCD     0                          ; Reserved
 70 |                 DCD     0                          ; Reserved
 71 |                 DCD     0                          ; Reserved
 72 |                 DCD     SVC_Handler                ; SVCall Handler
 73 |                 DCD     DebugMon_Handler           ; Debug Monitor Handler
 74 |                 DCD     0                          ; Reserved
 75 |                 DCD     PendSV_Handler             ; PendSV Handler
 76 |                 DCD     SysTick_Handler            ; SysTick Handler
 77 | 
 78 |                 ; External Interrupts
 79 |                 DCD     WWDG_IRQHandler            ; Window Watchdog
 80 |                 DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
 81 |                 DCD     TAMPER_IRQHandler          ; Tamper
 82 |                 DCD     RTC_IRQHandler             ; RTC
 83 |                 DCD     FLASH_IRQHandler           ; Flash
 84 |                 DCD     RCC_IRQHandler             ; RCC
 85 |                 DCD     EXTI0_IRQHandler           ; EXTI Line 0
 86 |                 DCD     EXTI1_IRQHandler           ; EXTI Line 1
 87 |                 DCD     EXTI2_IRQHandler           ; EXTI Line 2
 88 |                 DCD     EXTI3_IRQHandler           ; EXTI Line 3
 89 |                 DCD     EXTI4_IRQHandler           ; EXTI Line 4
 90 |                 DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
 91 |                 DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
 92 |                 DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
 93 |                 DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
 94 |                 DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
 95 |                 DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
 96 |                 DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
 97 |                 DCD     ADC1_2_IRQHandler          ; ADC1_2
 98 |                 DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
 99 |                 DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
100 |                 DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
101 |                 DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
102 |                 DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
103 |                 DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
104 |                 DCD     TIM1_UP_IRQHandler         ; TIM1 Update
105 |                 DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
106 |                 DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
107 |                 DCD     TIM2_IRQHandler            ; TIM2
108 |                 DCD     TIM3_IRQHandler            ; TIM3
109 |                 DCD     TIM4_IRQHandler            ; TIM4
110 |                 DCD     I2C1_EV_IRQHandler         ; I2C1 Event
111 |                 DCD     I2C1_ER_IRQHandler         ; I2C1 Error
112 |                 DCD     I2C2_EV_IRQHandler         ; I2C2 Event
113 |                 DCD     I2C2_ER_IRQHandler         ; I2C2 Error
114 |                 DCD     SPI1_IRQHandler            ; SPI1
115 |                 DCD     SPI2_IRQHandler            ; SPI2
116 |                 DCD     USART1_IRQHandler          ; USART1
117 |                 DCD     USART2_IRQHandler          ; USART2
118 |                 DCD     USART3_IRQHandler          ; USART3
119 |                 DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
120 |                 DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
121 |                 DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
122 | __Vectors_End
123 | 
124 | __Vectors_Size  EQU  __Vectors_End - __Vectors
125 | 
126 |                 AREA    |.text|, CODE, READONLY
127 | 
128 | ; Reset handler
129 | Reset_Handler    PROC
130 |                  EXPORT  Reset_Handler             [WEAK]
131 |      IMPORT  __main
132 |      IMPORT  SystemInit
133 |                  LDR     R0, =SystemInit
134 |                  BLX     R0
135 |                  LDR     R0, =__main
136 |                  BX      R0
137 |                  ENDP
138 | 
139 | ; Dummy Exception Handlers (infinite loops which can be modified)
140 | 
141 | NMI_Handler     PROC
142 |                 EXPORT  NMI_Handler                [WEAK]
143 |                 B       .
144 |                 ENDP
145 | HardFault_Handler\
146 |                 PROC
147 |                 EXPORT  HardFault_Handler          [WEAK]
148 |                 B       .
149 |                 ENDP
150 | MemManage_Handler\
151 |                 PROC
152 |                 EXPORT  MemManage_Handler          [WEAK]
153 |                 B       .
154 |                 ENDP
155 | BusFault_Handler\
156 |                 PROC
157 |                 EXPORT  BusFault_Handler           [WEAK]
158 |                 B       .
159 |                 ENDP
160 | UsageFault_Handler\
161 |                 PROC
162 |                 EXPORT  UsageFault_Handler         [WEAK]
163 |                 B       .
164 |                 ENDP
165 | SVC_Handler     PROC
166 |                 EXPORT  SVC_Handler                [WEAK]
167 |                 B       .
168 |                 ENDP
169 | DebugMon_Handler\
170 |                 PROC
171 |                 EXPORT  DebugMon_Handler           [WEAK]
172 |                 B       .
173 |                 ENDP
174 | PendSV_Handler  PROC
175 |                 EXPORT  PendSV_Handler             [WEAK]
176 |                 B       .
177 |                 ENDP
178 | SysTick_Handler PROC
179 |                 EXPORT  SysTick_Handler            [WEAK]
180 |                 B       .
181 |                 ENDP
182 | 
183 | Default_Handler PROC
184 | 
185 |                 EXPORT  WWDG_IRQHandler            [WEAK]
186 |                 EXPORT  PVD_IRQHandler             [WEAK]
187 |                 EXPORT  TAMPER_IRQHandler          [WEAK]
188 |                 EXPORT  RTC_IRQHandler             [WEAK]
189 |                 EXPORT  FLASH_IRQHandler           [WEAK]
190 |                 EXPORT  RCC_IRQHandler             [WEAK]
191 |                 EXPORT  EXTI0_IRQHandler           [WEAK]
192 |                 EXPORT  EXTI1_IRQHandler           [WEAK]
193 |                 EXPORT  EXTI2_IRQHandler           [WEAK]
194 |                 EXPORT  EXTI3_IRQHandler           [WEAK]
195 |                 EXPORT  EXTI4_IRQHandler           [WEAK]
196 |                 EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
197 |                 EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
198 |                 EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
199 |                 EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
200 |                 EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
201 |                 EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
202 |                 EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
203 |                 EXPORT  ADC1_2_IRQHandler          [WEAK]
204 |                 EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
205 |                 EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
206 |                 EXPORT  CAN1_RX1_IRQHandler        [WEAK]
207 |                 EXPORT  CAN1_SCE_IRQHandler        [WEAK]
208 |                 EXPORT  EXTI9_5_IRQHandler         [WEAK]
209 |                 EXPORT  TIM1_BRK_IRQHandler        [WEAK]
210 |                 EXPORT  TIM1_UP_IRQHandler         [WEAK]
211 |                 EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
212 |                 EXPORT  TIM1_CC_IRQHandler         [WEAK]
213 |                 EXPORT  TIM2_IRQHandler            [WEAK]
214 |                 EXPORT  TIM3_IRQHandler            [WEAK]
215 |                 EXPORT  TIM4_IRQHandler            [WEAK]
216 |                 EXPORT  I2C1_EV_IRQHandler         [WEAK]
217 |                 EXPORT  I2C1_ER_IRQHandler         [WEAK]
218 |                 EXPORT  I2C2_EV_IRQHandler         [WEAK]
219 |                 EXPORT  I2C2_ER_IRQHandler         [WEAK]
220 |                 EXPORT  SPI1_IRQHandler            [WEAK]
221 |                 EXPORT  SPI2_IRQHandler            [WEAK]
222 |                 EXPORT  USART1_IRQHandler          [WEAK]
223 |                 EXPORT  USART2_IRQHandler          [WEAK]
224 |                 EXPORT  USART3_IRQHandler          [WEAK]
225 |                 EXPORT  EXTI15_10_IRQHandler       [WEAK]
226 |                 EXPORT  RTCAlarm_IRQHandler        [WEAK]
227 |                 EXPORT  USBWakeUp_IRQHandler       [WEAK]
228 | 
229 | WWDG_IRQHandler
230 | PVD_IRQHandler
231 | TAMPER_IRQHandler
232 | RTC_IRQHandler
233 | FLASH_IRQHandler
234 | RCC_IRQHandler
235 | EXTI0_IRQHandler
236 | EXTI1_IRQHandler
237 | EXTI2_IRQHandler
238 | EXTI3_IRQHandler
239 | EXTI4_IRQHandler
240 | DMA1_Channel1_IRQHandler
241 | DMA1_Channel2_IRQHandler
242 | DMA1_Channel3_IRQHandler
243 | DMA1_Channel4_IRQHandler
244 | DMA1_Channel5_IRQHandler
245 | DMA1_Channel6_IRQHandler
246 | DMA1_Channel7_IRQHandler
247 | ADC1_2_IRQHandler
248 | USB_HP_CAN1_TX_IRQHandler
249 | USB_LP_CAN1_RX0_IRQHandler
250 | CAN1_RX1_IRQHandler
251 | CAN1_SCE_IRQHandler
252 | EXTI9_5_IRQHandler
253 | TIM1_BRK_IRQHandler
254 | TIM1_UP_IRQHandler
255 | TIM1_TRG_COM_IRQHandler
256 | TIM1_CC_IRQHandler
257 | TIM2_IRQHandler
258 | TIM3_IRQHandler
259 | TIM4_IRQHandler
260 | I2C1_EV_IRQHandler
261 | I2C1_ER_IRQHandler
262 | I2C2_EV_IRQHandler
263 | I2C2_ER_IRQHandler
264 | SPI1_IRQHandler
265 | SPI2_IRQHandler
266 | USART1_IRQHandler
267 | USART2_IRQHandler
268 | USART3_IRQHandler
269 | EXTI15_10_IRQHandler
270 | RTCAlarm_IRQHandler
271 | USBWakeUp_IRQHandler
272 | 
273 |                 B       .
274 | 
275 |                 ENDP
276 | 
277 |                 ALIGN
278 | 
279 | ;*******************************************************************************
280 | ; User Stack and Heap initialization
281 | ;*******************************************************************************
282 |                  IF      :DEF:__MICROLIB           
283 |                 
284 |                  EXPORT  __initial_sp
285 |                  EXPORT  __heap_base
286 |                  EXPORT  __heap_limit
287 |                 
288 |                  ELSE
289 |                 
290 |                  IMPORT  __use_two_region_memory
291 |                  EXPORT  __user_initial_stackheap
292 |                  
293 | __user_initial_stackheap
294 | 
295 |                  LDR     R0, =  Heap_Mem
296 |                  LDR     R1, =(Stack_Mem + Stack_Size)
297 |                  LDR     R2, = (Heap_Mem +  Heap_Size)
298 |                  LDR     R3, = Stack_Mem
299 |                  BX      LR
300 | 
301 |                  ALIGN
302 | 
303 |                  ENDIF
304 | 
305 |                  END
306 | 
307 | ;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
308 | 


--------------------------------------------------------------------------------
/USER/LED.uvoptx:
--------------------------------------------------------------------------------
  1 | <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
  2 | <ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
  3 | 
  4 |   <SchemaVersion>1.0</SchemaVersion>
  5 | 
  6 |   <Header>### uVision Project, (C) Keil Software</Header>
  7 | 
  8 |   <Extensions>
  9 |     <cExt>*.c</cExt>
 10 |     <aExt>*.s*; *.src; *.a*</aExt>
 11 |     <oExt>*.obj; *.o</oExt>
 12 |     <lExt>*.lib</lExt>
 13 |     <tExt>*.txt; *.h; *.inc</tExt>
 14 |     <pExt>*.plm</pExt>
 15 |     <CppX>*.cpp</CppX>
 16 |     <nMigrate>0</nMigrate>
 17 |   </Extensions>
 18 | 
 19 |   <DaveTm>
 20 |     <dwLowDateTime>0</dwLowDateTime>
 21 |     <dwHighDateTime>0</dwHighDateTime>
 22 |   </DaveTm>
 23 | 
 24 |   <Target>
 25 |     <TargetName>LED</TargetName>
 26 |     <ToolsetNumber>0x4</ToolsetNumber>
 27 |     <ToolsetName>ARM-ADS</ToolsetName>
 28 |     <TargetOption>
 29 |       <CLKADS>12000000</CLKADS>
 30 |       <OPTTT>
 31 |         <gFlags>1</gFlags>
 32 |         <BeepAtEnd>1</BeepAtEnd>
 33 |         <RunSim>0</RunSim>
 34 |         <RunTarget>1</RunTarget>
 35 |         <RunAbUc>0</RunAbUc>
 36 |       </OPTTT>
 37 |       <OPTHX>
 38 |         <HexSelection>1</HexSelection>
 39 |         <FlashByte>65535</FlashByte>
 40 |         <HexRangeLowAddress>0</HexRangeLowAddress>
 41 |         <HexRangeHighAddress>0</HexRangeHighAddress>
 42 |         <HexOffset>0</HexOffset>
 43 |       </OPTHX>
 44 |       <OPTLEX>
 45 |         <PageWidth>79</PageWidth>
 46 |         <PageLength>66</PageLength>
 47 |         <TabStop>8</TabStop>
 48 |         <ListingPath>.\Listings\</ListingPath>
 49 |       </OPTLEX>
 50 |       <ListingPage>
 51 |         <CreateCListing>1</CreateCListing>
 52 |         <CreateAListing>1</CreateAListing>
 53 |         <CreateLListing>1</CreateLListing>
 54 |         <CreateIListing>0</CreateIListing>
 55 |         <AsmCond>1</AsmCond>
 56 |         <AsmSymb>1</AsmSymb>
 57 |         <AsmXref>0</AsmXref>
 58 |         <CCond>1</CCond>
 59 |         <CCode>0</CCode>
 60 |         <CListInc>0</CListInc>
 61 |         <CSymb>0</CSymb>
 62 |         <LinkerCodeListing>0</LinkerCodeListing>
 63 |       </ListingPage>
 64 |       <OPTXL>
 65 |         <LMap>1</LMap>
 66 |         <LComments>1</LComments>
 67 |         <LGenerateSymbols>1</LGenerateSymbols>
 68 |         <LLibSym>1</LLibSym>
 69 |         <LLines>1</LLines>
 70 |         <LLocSym>1</LLocSym>
 71 |         <LPubSym>1</LPubSym>
 72 |         <LXref>0</LXref>
 73 |         <LExpSel>0</LExpSel>
 74 |       </OPTXL>
 75 |       <OPTFL>
 76 |         <tvExp>1</tvExp>
 77 |         <tvExpOptDlg>0</tvExpOptDlg>
 78 |         <IsCurrentTarget>1</IsCurrentTarget>
 79 |       </OPTFL>
 80 |       <CpuCode>18</CpuCode>
 81 |       <DebugOpt>
 82 |         <uSim>0</uSim>
 83 |         <uTrg>1</uTrg>
 84 |         <sLdApp>1</sLdApp>
 85 |         <sGomain>1</sGomain>
 86 |         <sRbreak>1</sRbreak>
 87 |         <sRwatch>1</sRwatch>
 88 |         <sRmem>1</sRmem>
 89 |         <sRfunc>1</sRfunc>
 90 |         <sRbox>1</sRbox>
 91 |         <tLdApp>1</tLdApp>
 92 |         <tGomain>1</tGomain>
 93 |         <tRbreak>1</tRbreak>
 94 |         <tRwatch>1</tRwatch>
 95 |         <tRmem>1</tRmem>
 96 |         <tRfunc>0</tRfunc>
 97 |         <tRbox>1</tRbox>
 98 |         <tRtrace>1</tRtrace>
 99 |         <sRSysVw>1</sRSysVw>
100 |         <tRSysVw>1</tRSysVw>
101 |         <sRunDeb>0</sRunDeb>
102 |         <sLrtime>0</sLrtime>
103 |         <bEvRecOn>1</bEvRecOn>
104 |         <nTsel>5</nTsel>
105 |         <sDll></sDll>
106 |         <sDllPa></sDllPa>
107 |         <sDlgDll></sDlgDll>
108 |         <sDlgPa></sDlgPa>
109 |         <sIfile></sIfile>
110 |         <tDll></tDll>
111 |         <tDllPa></tDllPa>
112 |         <tDlgDll></tDlgDll>
113 |         <tDlgPa></tDlgPa>
114 |         <tIfile></tIfile>
115 |         <pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
116 |       </DebugOpt>
117 |       <TargetDriverDllRegistry>
118 |         <SetRegEntry>
119 |           <Number>0</Number>
120 |           <Key>ST-LINKIII-KEIL_SWO</Key>
121 |           <Name>-U2C0A081B2315303030303032 -O206 -S1 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM)</Name>
122 |         </SetRegEntry>
123 |         <SetRegEntry>
124 |           <Number>0</Number>
125 |           <Key>UL2CM3</Key>
126 |           <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F10x_128 -FL020000 -FS08000000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM)</Name>
127 |         </SetRegEntry>
128 |         <SetRegEntry>
129 |           <Number>0</Number>
130 |           <Key>JL2CM3</Key>
131 |           <Name>-U799713843 -O78 -S1 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32F103ZE$Flash\STM32F10x_512.FLM)</Name>
132 |         </SetRegEntry>
133 |       </TargetDriverDllRegistry>
134 |       <Breakpoint/>
135 |       <Tracepoint>
136 |         <THDelay>0</THDelay>
137 |       </Tracepoint>
138 |       <DebugFlag>
139 |         <trace>0</trace>
140 |         <periodic>0</periodic>
141 |         <aLwin>0</aLwin>
142 |         <aCover>0</aCover>
143 |         <aSer1>0</aSer1>
144 |         <aSer2>0</aSer2>
145 |         <aPa>0</aPa>
146 |         <viewmode>0</viewmode>
147 |         <vrSel>0</vrSel>
148 |         <aSym>0</aSym>
149 |         <aTbox>0</aTbox>
150 |         <AscS1>0</AscS1>
151 |         <AscS2>0</AscS2>
152 |         <AscS3>0</AscS3>
153 |         <aSer3>0</aSer3>
154 |         <eProf>0</eProf>
155 |         <aLa>0</aLa>
156 |         <aPa1>0</aPa1>
157 |         <AscS4>0</AscS4>
158 |         <aSer4>0</aSer4>
159 |         <StkLoc>0</StkLoc>
160 |         <TrcWin>0</TrcWin>
161 |         <newCpu>0</newCpu>
162 |         <uProt>0</uProt>
163 |       </DebugFlag>
164 |       <LintExecutable></LintExecutable>
165 |       <LintConfigFile></LintConfigFile>
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