├── .gitattributes ├── .gitignore ├── Position.MP4 ├── README.md └── src ├── 24Cxx.c ├── 24Cxx.h ├── DSP281x_Adc.c ├── DSP281x_Adc.h ├── DSP281x_CSMPasswords.asm ├── DSP281x_CodeStartBranch.asm ├── DSP281x_CpuTimers.c ├── DSP281x_CpuTimers.h ├── DSP281x_DBGIER.asm ├── DSP281x_DefaultIsr.c ├── DSP281x_DefaultIsr.h ├── DSP281x_DevEmu.h ├── DSP281x_Device.h ├── DSP281x_ECan.c ├── DSP281x_ECan.h ├── DSP281x_Ev.c ├── DSP281x_Ev.h ├── DSP281x_Examples.h ├── DSP281x_GlobalPrototypes.h ├── DSP281x_GlobalVariableDefs.c ├── DSP281x_Gpio.c ├── DSP281x_Gpio.h ├── DSP281x_Headers_nonBIOS.cmd ├── DSP281x_InitPeripherals.c ├── DSP281x_Mcbsp.c ├── DSP281x_Mcbsp.h ├── DSP281x_MemCopy.c ├── DSP281x_PieCtrl.c ├── DSP281x_PieCtrl.h ├── DSP281x_PieVect.c ├── DSP281x_PieVect.h ├── DSP281x_SWPrioritizedDefaultIsr.c ├── DSP281x_SWPrioritizedIsrLevels.h ├── DSP281x_SWPrioritizedPieVect.c ├── DSP281x_Sci.c ├── DSP281x_Sci.h ├── DSP281x_Spi.c ├── DSP281x_Spi.h ├── DSP281x_SysCtrl.c ├── DSP281x_SysCtrl.h ├── DSP281x_XIntrupt.c ├── DSP281x_XIntrupt.h ├── DSP281x_Xintf.c ├── DSP281x_Xintf.h ├── DSP281x_XintfBootReset.asm ├── DSP281x_usDelay.asm ├── DSP28_Adc.h ├── DSP28_CpuTimers.h ├── DSP28_DefaultIsr.h ├── DSP28_DevEmu.h ├── DSP28_Device.h ├── DSP28_ECan.h ├── DSP28_Ev.h ├── DSP28_GlobalPrototypes.h ├── DSP28_Gpio.h ├── DSP28_Mcbsp.h ├── DSP28_PieCtrl.h ├── DSP28_PieVect.h ├── DSP28_Sci.c ├── DSP28_Sci.h ├── DSP28_Spi.h ├── DSP28_SysCtrl.h ├── DSP28_XIntrupt.h ├── DSP28_Xintf.h ├── F2812.cmd ├── F2812_EzDSP_RAM_lnk.cmd ├── Table.c ├── display.c ├── main.c └── pi.h /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | 4 | # Custom for Visual Studio 5 | *.cs diff=csharp 6 | *.sln merge=union 7 | *.csproj merge=union 8 | *.vbproj merge=union 9 | *.fsproj merge=union 10 | *.dbproj merge=union 11 | 12 | # Standard to msysgit 13 | *.doc diff=astextplain 14 | *.DOC diff=astextplain 15 | *.docx diff=astextplain 16 | *.DOCX diff=astextplain 17 | *.dot diff=astextplain 18 | *.DOT diff=astextplain 19 | *.pdf diff=astextplain 20 | *.PDF diff=astextplain 21 | *.rtf diff=astextplain 22 | *.RTF diff=astextplain 23 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Windows image file caches 2 | Thumbs.db 3 | ehthumbs.db 4 | 5 | # Folder config file 6 | Desktop.ini 7 | 8 | # Recycle Bin used on file shares 9 | $RECYCLE.BIN/ 10 | 11 | # Windows Installer files 12 | *.cab 13 | *.msi 14 | *.msm 15 | *.msp 16 | 17 | # ========================= 18 | # Operating System Files 19 | # ========================= 20 | 21 | # OSX 22 | # ========================= 23 | 24 | .DS_Store 25 | .AppleDouble 26 | .LSOverride 27 | 28 | # Icon must ends with two \r. 29 | Icon 30 | 31 | # Thumbnails 32 | ._* 33 | 34 | # Files that might appear on external disk 35 | .Spotlight-V100 36 | .Trashes 37 | -------------------------------------------------------------------------------- /Position.MP4: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/natsu1211/F2812_PMSM_SVPWM_PI/e61f8ed2da756a8a6a791fd4440c8b509083bb9c/Position.MP4 -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | F2812_PMSM_SVPWM_PI 2 | =================== 3 | 4 | This is a C language implementation of Space Vector Pulse Width Modulation(SVPWM) with speed, position and current PI controller for Permanent Magnet Synchronous Motor(PMSM). 5 | By this program, we can control the speed and position of PMSM accurately, which is suitable for industrial control. 6 | 7 | This program should excuted on Texas Instrument's DSP TMS320F2812 since some codes are hardware dependant. 8 | However, if you pay attention to the hardware dependant codes (especially the codes relevent to Event Manager), you can still port this program to other platform. 9 | 10 | main.c 11 | Program entry. Almost all logic is implemented in this file, including SVPWM and PI. 12 | 13 | display.c 14 | LED driver program based on BC7281 driver chip. Using to display the speed of motor. 15 | 16 | table.c 17 | Since TMS320F2812 is a 32-bit Fixed-point DSP, which means it's powerless when facing Float-point calculation. 18 | To accelerate the Float-point calculation, we store the results of trigonometric functions at certain interval in this table. Then we can query this table to approximate Float-point calculation. 19 | (Notice: these 3 files contain some Chinese character comments, which may not display properly in your editor or IDE.) 20 | 21 | Position.mp4 22 | Shows the position contorl of motor. 23 | 24 | Other files 25 | automatic generated by Texas Instrument's Code Composer Studio(CCS) IDE, provide initialization for different hardware module or memory configuration. 26 | -------------------------------------------------------------------------------- /src/24Cxx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/natsu1211/F2812_PMSM_SVPWM_PI/e61f8ed2da756a8a6a791fd4440c8b509083bb9c/src/24Cxx.c -------------------------------------------------------------------------------- /src/24Cxx.h: -------------------------------------------------------------------------------- 1 | #ifndef _24Cxx_H_ 2 | #define _24Cxx_H_ 3 | 4 | 5 | 6 | 7 | Uint16 Read24Cxx( Uint16 RomAddress, Uint16 number); 8 | Uint16 Write24Cxx(Uint16 Wdata, Uint16 RomAddress, Uint16 number); 9 | void Init24Cxx(void); 10 | 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /src/DSP281x_Adc.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Adc.c 4 | // 5 | // TITLE: DSP281x ADC Initialization & Support Functions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | ADC_usDELAY changed from 5000L to 8000L 13 | //########################################################################### 14 | 15 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 16 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 17 | 18 | #define ADC_usDELAY 8000L 19 | #define ADC_usDELAY2 20L 20 | 21 | //--------------------------------------------------------------------------- 22 | // InitAdc: 23 | //--------------------------------------------------------------------------- 24 | // This function initializes ADC to a known state. 25 | // 26 | void InitAdc(void) 27 | { 28 | extern void DSP28x_usDelay(Uint32 Count); 29 | 30 | // To powerup the ADC the ADCENCLK bit should be set first to enable 31 | // clocks, followed by powering up the bandgap and reference circuitry. 32 | // After a 5ms delay the rest of the ADC can be powered up. After ADC 33 | // powerup, another 20us delay is required before performing the first 34 | // ADC conversion. Please note that for the delay function below to 35 | // operate correctly the CPU_CLOCK_SPEED define statement in the 36 | // DSP28_Examples.h file must contain the correct CPU clock period in 37 | // nanoseconds. For example: 38 | 39 | AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3; // Power up bandgap/reference circuitry 40 | DELAY_US(ADC_usDELAY); // Delay before powering up rest of ADC 41 | AdcRegs.ADCTRL3.bit.ADCPWDN = 1; // Power up rest of ADC 42 | DELAY_US(ADC_usDELAY2); // Delay after powering up ADC 43 | } 44 | 45 | //=========================================================================== 46 | // No more. 47 | //=========================================================================== 48 | -------------------------------------------------------------------------------- /src/DSP281x_Adc.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Adc.h 4 | // 5 | // TITLE: DSP281x Device ADC Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Separated the MAX_CONV bit fields into two 13 | // | | | MAX_CONV1 // 3:0 14 | // | | | MAX_CONV2 // 6:4 15 | // | | | Added SEQ_OVRD bit to ADCTRL1 for RevC and after silicon 16 | //########################################################################### 17 | 18 | #ifndef DSP281x_ADC_H 19 | #define DSP281x_ADC_H 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | 26 | //--------------------------------------------------------------------------- 27 | // ADC Individual Register Bit Definitions: 28 | 29 | struct ADCTRL1_BITS { // bits description 30 | Uint16 rsvd1:4; // 3:0 reserved 31 | Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode 32 | Uint16 SEQ_OVRD:1; // 5 Sequencer override 33 | Uint16 CONT_RUN:1; // 6 Continuous run 34 | Uint16 CPS:1; // 7 ADC core clock pre-scalar 35 | Uint16 ACQ_PS:4; // 11:8 Acquisition window size 36 | Uint16 SUSMOD:2; // 13:12 Emulation suspend mode 37 | Uint16 RESET:1; // 14 ADC reset 38 | Uint16 rsvd2:1; // 15 reserved 39 | }; 40 | 41 | 42 | union ADCTRL1_REG { 43 | Uint16 all; 44 | struct ADCTRL1_BITS bit; 45 | }; 46 | 47 | 48 | struct ADCTRL2_BITS { // bits description 49 | Uint16 EVB_SOC_SEQ2:1; // 0 Event manager B SOC mask for SEQ2 50 | Uint16 rsvd1:1; // 1 reserved 51 | Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode 52 | Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable 53 | Uint16 rsvd2:1; // 4 reserved 54 | Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 55 | Uint16 RST_SEQ2:1; // 6 Reset SEQ2 56 | Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 57 | Uint16 EVA_SOC_SEQ1:1; // 8 Event manager A SOC mask for SEQ1 58 | Uint16 rsvd3:1; // 9 reserved 59 | Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode 60 | Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable 61 | Uint16 rsvd4:1; // 12 reserved 62 | Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 63 | Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 64 | Uint16 EVB_SOC_SEQ:1; // 15 EVB SOC enable 65 | }; 66 | 67 | 68 | union ADCTRL2_REG { 69 | Uint16 all; 70 | struct ADCTRL2_BITS bit; 71 | }; 72 | 73 | 74 | struct ADCASEQSR_BITS { // bits description 75 | Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state 76 | Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state 77 | Uint16 rsvd1:1; // 7 reserved 78 | Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status 79 | Uint16 rsvd2:4; // 15:12 reserved 80 | }; 81 | 82 | union ADCASEQSR_REG { 83 | Uint16 all; 84 | struct ADCASEQSR_BITS bit; 85 | }; 86 | 87 | 88 | struct ADCMAXCONV_BITS { // bits description 89 | Uint16 MAX_CONV1:4; // 3:0 Max number of conversions 90 | Uint16 MAX_CONV2:3; // 6:4 Max number of conversions 91 | Uint16 rsvd1:9; // 15:7 reserved 92 | }; 93 | 94 | union ADCMAXCONV_REG { 95 | Uint16 all; 96 | struct ADCMAXCONV_BITS bit; 97 | }; 98 | 99 | 100 | struct ADCCHSELSEQ1_BITS { // bits description 101 | Uint16 CONV00:4; // 3:0 Conversion selection 00 102 | Uint16 CONV01:4; // 7:4 Conversion selection 01 103 | Uint16 CONV02:4; // 11:8 Conversion selection 02 104 | Uint16 CONV03:4; // 15:12 Conversion selection 03 105 | }; 106 | 107 | union ADCCHSELSEQ1_REG{ 108 | Uint16 all; 109 | struct ADCCHSELSEQ1_BITS bit; 110 | }; 111 | 112 | struct ADCCHSELSEQ2_BITS { // bits description 113 | Uint16 CONV04:4; // 3:0 Conversion selection 04 114 | Uint16 CONV05:4; // 7:4 Conversion selection 05 115 | Uint16 CONV06:4; // 11:8 Conversion selection 06 116 | Uint16 CONV07:4; // 15:12 Conversion selection 07 117 | }; 118 | 119 | union ADCCHSELSEQ2_REG{ 120 | Uint16 all; 121 | struct ADCCHSELSEQ2_BITS bit; 122 | }; 123 | 124 | struct ADCCHSELSEQ3_BITS { // bits description 125 | Uint16 CONV08:4; // 3:0 Conversion selection 08 126 | Uint16 CONV09:4; // 7:4 Conversion selection 09 127 | Uint16 CONV10:4; // 11:8 Conversion selection 10 128 | Uint16 CONV11:4; // 15:12 Conversion selection 11 129 | }; 130 | 131 | union ADCCHSELSEQ3_REG{ 132 | Uint16 all; 133 | struct ADCCHSELSEQ3_BITS bit; 134 | }; 135 | 136 | struct ADCCHSELSEQ4_BITS { // bits description 137 | Uint16 CONV12:4; // 3:0 Conversion selection 12 138 | Uint16 CONV13:4; // 7:4 Conversion selection 13 139 | Uint16 CONV14:4; // 11:8 Conversion selection 14 140 | Uint16 CONV15:4; // 15:12 Conversion selection 15 141 | }; 142 | 143 | union ADCCHSELSEQ4_REG { 144 | Uint16 all; 145 | struct ADCCHSELSEQ4_BITS bit; 146 | }; 147 | 148 | struct ADCTRL3_BITS { // bits description 149 | Uint16 SMODE_SEL:1; // 0 Sampling mode select 150 | Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider 151 | Uint16 ADCPWDN:1; // 5 ADC powerdown 152 | Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down 153 | Uint16 rsvd1:8; // 15:8 reserved 154 | }; 155 | 156 | union ADCTRL3_REG { 157 | Uint16 all; 158 | struct ADCTRL3_BITS bit; 159 | }; 160 | 161 | 162 | struct ADCST_BITS { // bits description 163 | Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag 164 | Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag 165 | Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status 166 | Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status 167 | Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear 168 | Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear 169 | Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 170 | Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 171 | Uint16 rsvd1:8; // 15:8 reserved 172 | }; 173 | 174 | 175 | union ADCST_REG { 176 | Uint16 all; 177 | struct ADCST_BITS bit; 178 | }; 179 | 180 | 181 | struct ADC_REGS { 182 | union ADCTRL1_REG ADCTRL1; // ADC Control 1 183 | union ADCTRL2_REG ADCTRL2; // ADC Control 2 184 | union ADCMAXCONV_REG ADCMAXCONV; // Max conversions 185 | union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control 1 186 | union ADCCHSELSEQ2_REG ADCCHSELSEQ2; // Channel select sequencing control 2 187 | union ADCCHSELSEQ3_REG ADCCHSELSEQ3; // Channel select sequencing control 3 188 | union ADCCHSELSEQ4_REG ADCCHSELSEQ4; // Channel select sequencing control 4 189 | union ADCASEQSR_REG ADCASEQSR; // Autosequence status register 190 | Uint16 ADCRESULT0; // Conversion Result Buffer 0 191 | Uint16 ADCRESULT1; // Conversion Result Buffer 1 192 | Uint16 ADCRESULT2; // Conversion Result Buffer 2 193 | Uint16 ADCRESULT3; // Conversion Result Buffer 3 194 | Uint16 ADCRESULT4; // Conversion Result Buffer 4 195 | Uint16 ADCRESULT5; // Conversion Result Buffer 5 196 | Uint16 ADCRESULT6; // Conversion Result Buffer 6 197 | Uint16 ADCRESULT7; // Conversion Result Buffer 7 198 | Uint16 ADCRESULT8; // Conversion Result Buffer 8 199 | Uint16 ADCRESULT9; // Conversion Result Buffer 9 200 | Uint16 ADCRESULT10; // Conversion Result Buffer 10 201 | Uint16 ADCRESULT11; // Conversion Result Buffer 11 202 | Uint16 ADCRESULT12; // Conversion Result Buffer 12 203 | Uint16 ADCRESULT13; // Conversion Result Buffer 13 204 | Uint16 ADCRESULT14; // Conversion Result Buffer 14 205 | Uint16 ADCRESULT15; // Conversion Result Buffer 15 206 | union ADCTRL3_REG ADCTRL3; // ADC Control 3 207 | union ADCST_REG ADCST; // ADC Status Register 208 | }; 209 | 210 | 211 | //--------------------------------------------------------------------------- 212 | // ADC External References & Function Declarations: 213 | // 214 | extern volatile struct ADC_REGS AdcRegs; 215 | 216 | 217 | #ifdef __cplusplus 218 | } 219 | #endif /* extern "C" */ 220 | 221 | 222 | #endif // end of DSP281x_ADC_H definition 223 | 224 | //=========================================================================== 225 | // No more. 226 | //=========================================================================== 227 | -------------------------------------------------------------------------------- /src/DSP281x_CSMPasswords.asm: -------------------------------------------------------------------------------- 1 | ;//########################################################################### 2 | ;// 3 | ;// FILE: DSP281x_CSMPasswords.asm 4 | ;// 5 | ;// TITLE: DSP281x Code Security Module Passwords. 6 | ;// 7 | ;// DESCRIPTION: 8 | ;// 9 | ;// This file is used to specify password values to 10 | ;// program into the CSM password locations in Flash 11 | ;// at 0x3F7FF8 - 0x3F7FFF. 12 | ;// 13 | ;// In addition, the reserved locations 0x3F7F80 - 0X3f7ff5 are 14 | ;// all programmed to 0x0000 15 | ;// 16 | ;//########################################################################### 17 | ;// 18 | ;// Original source based on D.A. 19 | ;// 20 | ;// Ver | dd mmm yyyy | Who | Description of changes 21 | ;// =====|=============|======|=============================================== 22 | ;// 1.00| 11 Sep 2003 | L.H. | Original Release 23 | ;//########################################################################### 24 | 25 | 26 | ; The "csmpasswords" section contains the actual CSM passwords that will be 27 | ; linked and programmed into to the CSM password locations (PWL) in flash. 28 | ; These passwords must be known in order to unlock the CSM module. 29 | ; All 0xFFFF's (erased) is the default value for the password locations (PWL). 30 | 31 | ; It is recommended that all passwords be left as 0xFFFF during code 32 | ; development. Passwords of 0xFFFF do not activate code security and dummy 33 | ; reads of the CSM PWL registers is all that is required to unlock the CSM. 34 | ; When code development is complete, modify the passwords to activate the 35 | ; code security module. 36 | 37 | .sect "csmpasswds" 38 | 39 | .int 0xFFFF ;PWL0 (LSW of 128-bit password) 40 | .int 0xFFFF ;PWL1 41 | .int 0xFFFF ;PWL2 42 | .int 0xFFFF ;PWL3 43 | .int 0xFFFF ;PWL4 44 | .int 0xFFFF ;PWL5 45 | .int 0xFFFF ;PWL6 46 | .int 0xFFFF ;PWL7 (MSW of 128-bit password) 47 | 48 | ;---------------------------------------------------------------------- 49 | 50 | ; For code security operation, all addresses between 0x3F7F80 and 51 | ; 0X3f7ff5 cannot be used as program code or data. These locations 52 | ; must be programmed to 0x0000 when the code security password locations 53 | ; (PWL) are programmed. If security is not a concern, then these addresses 54 | ; can be used for code or data. 55 | 56 | ; The section "csm_rsvd" can be used to program these locations to 0x0000. 57 | 58 | .sect "csm_rsvd" 59 | .loop (3F7FF5h - 3F7F80h + 1) 60 | .int 0x0000 61 | .endloop 62 | 63 | ;---------------------------------------------------------------------- 64 | 65 | -------------------------------------------------------------------------------- /src/DSP281x_CodeStartBranch.asm: -------------------------------------------------------------------------------- 1 | ;//########################################################################### 2 | ;// 3 | ;// FILE: DSP281x_CodeStartBranch.asm 4 | ;// 5 | ;// TITLE: Branch for redirecting code execution after boot. 6 | ;// 7 | ;//########################################################################### 8 | ;// 9 | ;// Ver | dd mmm yyyy | Who | Description of changes 10 | ;// =====|=============|======|=============================================== 11 | ;// 1.00| 11 Sep 03 | L.H. | Updated based on D.A source to allow 12 | ;// | | | disabling the watchdog before branching to 13 | ;// | | | the C init routine. This is useful if the 14 | ;// | | | watchdog is timing out before main() is reached. 15 | ;//########################################################################### 16 | 17 | 18 | *********************************************************************** 19 | 20 | WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 21 | 22 | .ref _c_int00 23 | 24 | *********************************************************************** 25 | * Function: codestart section 26 | * 27 | * Description: Branch to code starting point 28 | *********************************************************************** 29 | 30 | .sect "codestart" 31 | 32 | code_start: 33 | .if WD_DISABLE == 1 34 | LB wd_disable ;Branch to watchdog disable code 35 | .else 36 | LB _c_int00 ;Branch to start of boot.asm in RTS library 37 | .endif 38 | 39 | ;end codestart section 40 | 41 | 42 | *********************************************************************** 43 | * Function: wd_disable 44 | * 45 | * Description: Disables the watchdog timer 46 | *********************************************************************** 47 | .if WD_DISABLE == 1 48 | 49 | .text 50 | wd_disable: 51 | SETC OBJMODE ;Set OBJMODE for 28x object code 52 | EALLOW ;Enable EALLOW protected register access 53 | MOVZ DP, #7029h>>6 ;Set data page for WDCR register 54 | MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD 55 | EDIS ;Disable EALLOW protected register access 56 | LB _c_int00 ;Branch to start of boot.asm in RTS library 57 | 58 | .endif 59 | 60 | ;end wd_disable 61 | 62 | 63 | 64 | .end 65 | 66 | ; end of file CodeStartBranch.asm -------------------------------------------------------------------------------- /src/DSP281x_CpuTimers.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_CpuTimers.c 4 | // 5 | // TITLE: DSP281x CPU 32-bit Timers Initialization & Support Functions. 6 | // 7 | // NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and 8 | // other realtime operating systems. 9 | // 10 | // Do not use these two timers in your application if you ever plan 11 | // on integrating DSP-BIOS or another realtime OS. 12 | // 13 | // For this reason, the code to manipulate these two timers is 14 | // commented out and not used in these examples. 15 | // 16 | //########################################################################### 17 | // 18 | // Ver | dd mmm yyyy | Who | Description of changes 19 | // =====|=============|======|=============================================== 20 | // 1.00| 11 Sep 2003 | L.H | Changes since previous version (v.58 Alpha) 21 | // | | | Removed some incorrect parameters in the timer 22 | // | | | setup that are not available on this device 23 | //########################################################################### 24 | 25 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 26 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 27 | 28 | struct CPUTIMER_VARS CpuTimer0; 29 | 30 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS 31 | //struct CPUTIMER_VARS CpuTimer1; 32 | //struct CPUTIMER_VARS CpuTimer2; 33 | 34 | //--------------------------------------------------------------------------- 35 | // InitCpuTimers: 36 | //--------------------------------------------------------------------------- 37 | // This function initializes all three CPU timers to a known state. 38 | // 39 | void InitCpuTimers(void) 40 | { 41 | // CPU Timer 0 42 | // Initialize address pointers to respective timer registers: 43 | CpuTimer0.RegsAddr = &CpuTimer0Regs; 44 | // Initialize timer period to maximum: 45 | CpuTimer0Regs.PRD.all = 0xFFFFFFFF; 46 | // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): 47 | CpuTimer0Regs.TPR.all = 0; 48 | CpuTimer0Regs.TPRH.all = 0; 49 | // Make sure timer is stopped: 50 | CpuTimer0Regs.TCR.bit.TSS = 1; 51 | // Reload all counter register with period value: 52 | CpuTimer0Regs.TCR.bit.TRB = 1; 53 | // Reset interrupt counters: 54 | CpuTimer0.InterruptCount = 0; 55 | 56 | 57 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS 58 | // Do not use these two timers if you ever plan on integrating 59 | // DSP-BIOS or another realtime OS. 60 | // 61 | // For this reason, the code to manipulate these two timers is 62 | // commented out and not used in these examples. 63 | 64 | // Initialize address pointers to respective timer registers: 65 | // CpuTimer1.RegsAddr = &CpuTimer1Regs; 66 | // CpuTimer2.RegsAddr = &CpuTimer2Regs; 67 | // Initialize timer period to maximum: 68 | // CpuTimer1Regs.PRD.all = 0xFFFFFFFF; 69 | // CpuTimer2Regs.PRD.all = 0xFFFFFFFF; 70 | // Make sure timers are stopped: 71 | // CpuTimer1Regs.TCR.bit.TSS = 1; 72 | // CpuTimer2Regs.TCR.bit.TSS = 1; 73 | // Reload all counter register with period value: 74 | // CpuTimer1Regs.TCR.bit.TRB = 1; 75 | // CpuTimer2Regs.TCR.bit.TRB = 1; 76 | // Reset interrupt counters: 77 | // CpuTimer1.InterruptCount = 0; 78 | // CpuTimer2.InterruptCount = 0; 79 | 80 | } 81 | 82 | //--------------------------------------------------------------------------- 83 | // ConfigCpuTimer: 84 | //--------------------------------------------------------------------------- 85 | // This function initializes the selected timer to the period specified 86 | // by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz" 87 | // and the period in "uSeconds". The timer is held in the stopped state 88 | // after configuration. 89 | // 90 | void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) 91 | { 92 | Uint32 temp; 93 | 94 | // Initialize timer period: 95 | Timer->CPUFreqInMHz = Freq; 96 | Timer->PeriodInUSec = Period; 97 | temp = (long) (Freq * Period); 98 | Timer->RegsAddr->PRD.all = temp; 99 | 100 | // Set pre-scale counter to divide by 1 (SYSCLKOUT): 101 | Timer->RegsAddr->TPR.all = 0; 102 | Timer->RegsAddr->TPRH.all = 0; 103 | 104 | // Initialize timer control register: 105 | Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer 106 | Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer 107 | Timer->RegsAddr->TCR.bit.SOFT = 1; 108 | Timer->RegsAddr->TCR.bit.FREE = 1; // Timer Free Run 109 | Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt 110 | 111 | // Reset interrupt counter: 112 | Timer->InterruptCount = 0; 113 | } 114 | 115 | //=========================================================================== 116 | // No more. 117 | //=========================================================================== 118 | -------------------------------------------------------------------------------- /src/DSP281x_CpuTimers.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_CpuTimers.h 4 | // 5 | // TITLE: DSP281x CPU 32-bit Timers Register Definitions. 6 | // 7 | // NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and 8 | // other realtime operating systems. 9 | // 10 | // Do not use these two timers in your application if you ever plan 11 | // on integrating DSP-BIOS or another realtime OS. 12 | // 13 | // For this reason, the code to manipulate these two timers is 14 | // commented out and not used in these examples. 15 | // 16 | //########################################################################### 17 | // 18 | // Ver | dd mmm yyyy | Who | Description of changes 19 | // =====|=============|======|=============================================== 20 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 21 | // | | | Corrected the definition of the TCR register 22 | //########################################################################### 23 | 24 | #ifndef DSP281x_CPU_TIMERS_H 25 | #define DSP281x_CPU_TIMERS_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | //--------------------------------------------------------------------------- 32 | // CPU Timer Register Bit Definitions: 33 | // 34 | // 35 | // TCR: Control register bit definitions: 36 | struct TCR_BITS { // bits description 37 | Uint16 rsvd1:4; // 3:0 reserved 38 | Uint16 TSS:1; // 4 Timer Start/Stop 39 | Uint16 TRB:1; // 5 Timer reload 40 | Uint16 rsvd2:4; // 9:6 reserved 41 | Uint16 SOFT:1; // 10 Emulation modes 42 | Uint16 FREE:1; // 11 43 | Uint16 rsvd3:2; // 12:13 reserved 44 | Uint16 TIE:1; // 14 Output enable 45 | Uint16 TIF:1; // 15 Interrupt flag 46 | }; 47 | 48 | union TCR_REG { 49 | Uint16 all; 50 | struct TCR_BITS bit; 51 | }; 52 | 53 | // TPR: Pre-scale low bit definitions: 54 | struct TPR_BITS { // bits description 55 | Uint16 TDDR:8; // 7:0 Divide-down low 56 | Uint16 PSC:8; // 15:8 Prescale counter low 57 | }; 58 | 59 | union TPR_REG { 60 | Uint16 all; 61 | struct TPR_BITS bit; 62 | }; 63 | 64 | // TPRH: Pre-scale high bit definitions: 65 | struct TPRH_BITS { // bits description 66 | Uint16 TDDRH:8; // 7:0 Divide-down high 67 | Uint16 PSCH:8; // 15:8 Prescale counter high 68 | }; 69 | 70 | union TPRH_REG { 71 | Uint16 all; 72 | struct TPRH_BITS bit; 73 | }; 74 | 75 | // TIM, TIMH: Timer register definitions: 76 | struct TIM_REG { 77 | Uint16 LSW; 78 | Uint16 MSW; 79 | }; 80 | 81 | union TIM_GROUP { 82 | Uint32 all; 83 | struct TIM_REG half; 84 | }; 85 | 86 | // PRD, PRDH: Period register definitions: 87 | struct PRD_REG { 88 | Uint16 LSW; 89 | Uint16 MSW; 90 | }; 91 | 92 | union PRD_GROUP { 93 | Uint32 all; 94 | struct PRD_REG half; 95 | }; 96 | 97 | //--------------------------------------------------------------------------- 98 | // CPU Timer Register File: 99 | // 100 | struct CPUTIMER_REGS { 101 | union TIM_GROUP TIM; // Timer counter register 102 | union PRD_GROUP PRD; // Period register 103 | union TCR_REG TCR; // Timer control register 104 | Uint16 rsvd1; // reserved 105 | union TPR_REG TPR; // Timer pre-scale low 106 | union TPRH_REG TPRH; // Timer pre-scale high 107 | }; 108 | 109 | //--------------------------------------------------------------------------- 110 | // CPU Timer Support Variables: 111 | // 112 | struct CPUTIMER_VARS { 113 | volatile struct CPUTIMER_REGS *RegsAddr; 114 | Uint32 InterruptCount; 115 | float CPUFreqInMHz; 116 | float PeriodInUSec; 117 | }; 118 | 119 | //--------------------------------------------------------------------------- 120 | // Function prototypes and external definitions: 121 | // 122 | void InitCpuTimers(void); 123 | void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); 124 | 125 | extern volatile struct CPUTIMER_REGS CpuTimer0Regs; 126 | extern struct CPUTIMER_VARS CpuTimer0; 127 | 128 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS 129 | //extern volatile struct CPUTIMER_REGS CpuTimer1Regs; 130 | //extern volatile struct CPUTIMER_REGS CpuTimer2Regs; 131 | 132 | //extern struct CPUTIMER_VARS CpuTimer1; 133 | //extern struct CPUTIMER_VARS CpuTimer2; 134 | 135 | //--------------------------------------------------------------------------- 136 | // Usefull Timer Operations: 137 | // 138 | // Start Timer: 139 | #define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 140 | 141 | // Stop Timer: 142 | #define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 143 | 144 | // Reload Timer With period Value: 145 | #define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 146 | 147 | // Read 32-Bit Timer Value: 148 | #define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all 149 | 150 | // Read 32-Bit Period Value: 151 | #define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all 152 | 153 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS 154 | // Do not use these two timers if you ever plan on integrating 155 | // DSP-BIOS or another realtime OS. 156 | // 157 | // For this reason, the code to manipulate these two timers is 158 | // commented out and not used in these examples. 159 | 160 | // Start Timer: 161 | //#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 162 | //#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 163 | 164 | // Stop Timer: 165 | //#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 166 | //#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 167 | 168 | // Reload Timer With period Value: 169 | //#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 170 | //#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 171 | 172 | // Read 32-Bit Timer Value: 173 | //#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all 174 | //#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all 175 | 176 | // Read 32-Bit Period Value: 177 | //#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all 178 | //#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all 179 | 180 | 181 | #ifdef __cplusplus 182 | } 183 | #endif /* extern "C" */ 184 | 185 | #endif // end of DSP281x_CPU_TIMERS_H definition 186 | 187 | 188 | //=========================================================================== 189 | // No more. 190 | //=========================================================================== 191 | -------------------------------------------------------------------------------- /src/DSP281x_DBGIER.asm: -------------------------------------------------------------------------------- 1 | ;//########################################################################### 2 | ;// 3 | ;// FILE: DSP281x_DBGIER.asm 4 | ;// 5 | ;// TITLE: Set the DBGIER register 6 | ;// 7 | ;// DESCRIPTION: 8 | ;// 9 | ;// Function to set the DBGIER register (for realtime emulation). 10 | ;// Function Prototype: void SetDBGIER(Uint16) 11 | ;// Useage: SetDBGIER(value); 12 | ;// Input Parameters: Uint16 value = value to put in DBGIER register. 13 | ;// Return Value: none 14 | ;// 15 | ;//########################################################################### 16 | ;// 17 | ;// Ver | dd mmm yyyy | Who | Description of changes 18 | ;// =====|=============|======|=============================================== 19 | ;// 1.00| 11 Sep 2003 | L.H. | No changes since v.58 20 | ;//########################################################################### 21 | .global _SetDBGIER 22 | .text 23 | 24 | _SetDBGIER: 25 | MOV *SP++,AL 26 | POP DBGIER 27 | LRETR 28 | -------------------------------------------------------------------------------- /src/DSP281x_DefaultIsr.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_DefaultIsr.h 4 | // 5 | // TITLE: DSP281x Devices Default Interrupt Service Routines Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Changed USER0-USER11 to USER1-USER12 to match the CPU guide 13 | //########################################################################### 14 | 15 | #ifndef DSP281x_DEFAULT_ISR_H 16 | #define DSP281x_DEFAULT_ISR_H 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | //--------------------------------------------------------------------------- 24 | // Default Interrupt Service Routine Declarations: 25 | // 26 | // The following function prototypes are for the 27 | // default ISR routines used with the default PIE vector table. 28 | // This default vector table is found in the DSP281x_PieVect.h 29 | // file. 30 | // 31 | 32 | // Non-Peripheral Interrupts: 33 | interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 34 | interrupt void INT14_ISR(void); // CPU-Timer2 35 | interrupt void DATALOG_ISR(void); // Datalogging interrupt 36 | interrupt void RTOSINT_ISR(void); // RTOS interrupt 37 | interrupt void EMUINT_ISR(void); // Emulation interrupt 38 | interrupt void NMI_ISR(void); // Non-maskable interrupt 39 | interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP 40 | interrupt void USER1_ISR(void); // User Defined trap 1 41 | interrupt void USER2_ISR(void); // User Defined trap 2 42 | interrupt void USER3_ISR(void); // User Defined trap 3 43 | interrupt void USER4_ISR(void); // User Defined trap 4 44 | interrupt void USER5_ISR(void); // User Defined trap 5 45 | interrupt void USER6_ISR(void); // User Defined trap 6 46 | interrupt void USER7_ISR(void); // User Defined trap 7 47 | interrupt void USER8_ISR(void); // User Defined trap 8 48 | interrupt void USER9_ISR(void); // User Defined trap 9 49 | interrupt void USER10_ISR(void); // User Defined trap 10 50 | interrupt void USER11_ISR(void); // User Defined trap 11 51 | interrupt void USER12_ISR(void); // User Defined trap 12 52 | 53 | // Group 1 PIE Interrupt Service Routines: 54 | interrupt void PDPINTA_ISR(void); // EV-A 55 | interrupt void PDPINTB_ISR(void); // EV-B 56 | interrupt void XINT1_ISR(void); 57 | interrupt void XINT2_ISR(void); 58 | interrupt void ADCINT_ISR(void); // ADC 59 | interrupt void TINT0_ISR(void); // Timer 0 60 | interrupt void WAKEINT_ISR(void); // WD 61 | 62 | // Group 2 PIE Interrupt Service Routines: 63 | interrupt void CMP1INT_ISR(void); // EV-A 64 | interrupt void CMP2INT_ISR(void); // EV-A 65 | interrupt void CMP3INT_ISR(void); // EV-A 66 | interrupt void T1PINT_ISR(void); // EV-A 67 | interrupt void T1CINT_ISR(void); // EV-A 68 | interrupt void T1UFINT_ISR(void); // EV-A 69 | interrupt void T1OFINT_ISR(void); // EV-A 70 | 71 | // Group 3 PIE Interrupt Service Routines: 72 | interrupt void T2PINT_ISR(void); // EV-A 73 | interrupt void T2CINT_ISR(void); // EV-A 74 | interrupt void T2UFINT_ISR(void); // EV-A 75 | interrupt void T2OFINT_ISR(void); // EV-A 76 | interrupt void CAPINT1_ISR(void); // EV-A 77 | interrupt void CAPINT2_ISR(void); // EV-A 78 | interrupt void CAPINT3_ISR(void); // EV-A 79 | 80 | // Group 4 PIE Interrupt Service Routines: 81 | interrupt void CMP4INT_ISR(void); // EV-B 82 | interrupt void CMP5INT_ISR(void); // EV-B 83 | interrupt void CMP6INT_ISR(void); // EV-B 84 | interrupt void T3PINT_ISR(void); // EV-B 85 | interrupt void T3CINT_ISR(void); // EV-B 86 | interrupt void T3UFINT_ISR(void); // EV-B 87 | interrupt void T3OFINT_ISR(void); // EV-B 88 | 89 | // Group 5 PIE Interrupt Service Routines: 90 | interrupt void T4PINT_ISR(void); // EV-B 91 | interrupt void T4CINT_ISR(void); // EV-B 92 | interrupt void T4UFINT_ISR(void); // EV-B 93 | interrupt void T4OFINT_ISR(void); // EV-B 94 | interrupt void CAPINT4_ISR(void); // EV-B 95 | interrupt void CAPINT5_ISR(void); // EV-B 96 | interrupt void CAPINT6_ISR(void); // EV-B 97 | 98 | // Group 6 PIE Interrupt Service Routines: 99 | interrupt void SPIRXINTA_ISR(void); // SPI 100 | interrupt void SPITXINTA_ISR(void); // SPI 101 | interrupt void MRINTA_ISR(void); // McBSP 102 | interrupt void MXINTA_ISR(void); // McBSP 103 | 104 | 105 | // Group 9 PIE Interrupt Service Routines: 106 | interrupt void SCIRXINTA_ISR(void); // SCI-A 107 | interrupt void SCITXINTA_ISR(void); // SCI-A 108 | interrupt void SCIRXINTB_ISR(void); // SCI-B 109 | interrupt void SCITXINTB_ISR(void); // SCI-B 110 | interrupt void ECAN0INTA_ISR(void); // eCAN 111 | interrupt void ECAN1INTA_ISR(void); // eCAN 112 | 113 | 114 | // Catch-all for Reserved Locations For testing purposes: 115 | interrupt void PIE_RESERVED(void); // Reserved for test 116 | interrupt void rsvd_ISR(void); // for test 117 | 118 | 119 | #ifdef __cplusplus 120 | } 121 | #endif /* extern "C" */ 122 | 123 | #endif // end of DSP281x_DEFAULT_ISR_H definition 124 | 125 | -------------------------------------------------------------------------------- /src/DSP281x_DevEmu.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_DevEmu.h 4 | // 5 | // TITLE: DSP281x Device Emulation Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | As of Rev C silicon, DEVICEID is a 16-bit 13 | // | | | register 14 | // | | | Commented out the DFT test registers. These 15 | // | | | are not needed as of Rev C silicon. 16 | //########################################################################### 17 | 18 | #ifndef DSP281x_DEV_EMU_H 19 | #define DSP281x_DEV_EMU_H 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | //--------------------------------------------------------------------------- 26 | // Device Emulation Register Bit Definitions: 27 | // 28 | // Device Configuration Register Bit Definitions 29 | struct DEVICECNF_BITS { // bits description 30 | Uint16 rsvd1:3; // 2:0 reserved 31 | Uint16 VMAPS:1; // 3 VMAP Status 32 | Uint16 rsvd2:1; // 4 reserved 33 | Uint16 XRSn:1; // 5 XRSn Signal Status 34 | Uint16 rsvd3:10; // 15:6 35 | Uint16 rsvd4:3; // 18:6 36 | Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection 37 | Uint16 rsvd5:12; // 31:20 reserved 38 | }; 39 | 40 | union DEVICECNF_REG { 41 | Uint32 all; 42 | struct DEVICECNF_BITS bit; 43 | }; 44 | 45 | 46 | // Device ID Register Bit Definitions 47 | struct DEVICEID_BITS { // bits description 48 | Uint16 REVID:16; // 15:0 Silicon revision 49 | }; 50 | 51 | union DEVICEID_REG { 52 | Uint32 all; 53 | struct DEVICEID_BITS bit; 54 | }; 55 | 56 | struct DEV_EMU_REGS { 57 | union DEVICECNF_REG DEVICECNF; // device configuration 58 | Uint16 rsvd1:1; // reserved 59 | union DEVICEID_REG DEVICEID; // Device ID 60 | Uint16 PROTSTART; // Write-Read protection start 61 | Uint16 PROTRANGE; // Write-Read protection range 62 | Uint16 rsvd2[202]; 63 | // These registers are no longer needed for Rev C and beyond 64 | // Uint16 M0RAMDFT; 65 | // Uint16 M1RAMDFT; 66 | // Uint16 L0RAMDFT; 67 | // Uint16 L1RAMDFT; 68 | // Uint16 H0RAMDFT; 69 | }; 70 | 71 | //--------------------------------------------------------------------------- 72 | // Device Emulation Register References & Function Declarations: 73 | // 74 | extern volatile struct DEV_EMU_REGS DevEmuRegs; 75 | 76 | #ifdef __cplusplus 77 | } 78 | #endif /* extern "C" */ 79 | 80 | #endif // end of DSP281x_DEV_EMU_H definition 81 | 82 | //=========================================================================== 83 | // No more. 84 | //=========================================================================== 85 | -------------------------------------------------------------------------------- /src/DSP281x_Device.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Device.h 4 | // 5 | // TITLE: DSP281x Device Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Added symbols created by the linker 13 | // | | | cmd file for relocating code. 14 | // | | | Added float to the datatype typedefs 15 | // | | | Added #if DSP28_DATA_TYPES wrapper around the 16 | // | | | typedefs 17 | // | | | Added DSP28_BIOS and DSP28_NONBIOS switches 18 | // | | | to include or not include the default ISR's 19 | // | | | Moved files and info specific to the DSP28 examples 20 | // | | | to DSP28_common\include\DSP28_Examples.h 21 | // | | | Changed F2812 -> DSP28_F2812 22 | // | | | Changed F2810 -> DSP28_F2810 23 | //########################################################################### 24 | 25 | #ifndef DSP281x_DEVICE_H 26 | #define DSP281x_DEVICE_H 27 | 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | 34 | #define TARGET 1 35 | //--------------------------------------------------------------------------- 36 | // User To Select Target Device: 37 | 38 | #define DSP28_F2812 TARGET 39 | #define DSP28_F2810 0 40 | 41 | //--------------------------------------------------------------------------- 42 | // Common CPU Definitions: 43 | // 44 | 45 | extern cregister volatile unsigned int IFR; 46 | extern cregister volatile unsigned int IER; 47 | 48 | #define EINT asm(" clrc INTM") 49 | #define DINT asm(" setc INTM") 50 | #define ERTM asm(" clrc DBGM") 51 | #define DRTM asm(" setc DBGM") 52 | #define EALLOW asm(" EALLOW") 53 | #define EDIS asm(" EDIS") 54 | #define ESTOP0 asm(" ESTOP0") 55 | 56 | #define M_INT1 0x0001 57 | #define M_INT2 0x0002 58 | #define M_INT3 0x0004 59 | #define M_INT4 0x0008 60 | #define M_INT5 0x0010 61 | #define M_INT6 0x0020 62 | #define M_INT7 0x0040 63 | #define M_INT8 0x0080 64 | #define M_INT9 0x0100 65 | #define M_INT10 0x0200 66 | #define M_INT11 0x0400 67 | #define M_INT12 0x0800 68 | #define M_INT13 0x1000 69 | #define M_INT14 0x2000 70 | #define M_DLOG 0x4000 71 | #define M_RTOS 0x8000 72 | 73 | #define BIT0 0x0001 74 | #define BIT1 0x0002 75 | #define BIT2 0x0004 76 | #define BIT3 0x0008 77 | #define BIT4 0x0010 78 | #define BIT5 0x0020 79 | #define BIT6 0x0040 80 | #define BIT7 0x0080 81 | #define BIT8 0x0100 82 | #define BIT9 0x0200 83 | #define BIT10 0x0400 84 | #define BIT11 0x0800 85 | #define BIT12 0x1000 86 | #define BIT13 0x2000 87 | #define BIT14 0x4000 88 | #define BIT15 0x8000 89 | 90 | 91 | 92 | //--------------------------------------------------------------------------- 93 | // For Portability, User Is Recommended To Use Following Data Type Size 94 | // Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: 95 | // 96 | 97 | #ifndef DSP28_DATA_TYPES 98 | #define DSP28_DATA_TYPES 99 | typedef int int16; 100 | typedef long int32; 101 | typedef unsigned int Uint16; 102 | typedef unsigned long Uint32; 103 | typedef float float32; 104 | typedef long double float64; 105 | #endif 106 | 107 | 108 | //--------------------------------------------------------------------------- 109 | // Include All Peripheral Header Files: 110 | // 111 | 112 | #include "DSP281x_SysCtrl.h" // System Control/Power Modes 113 | #include "DSP281x_DevEmu.h" // Device Emulation Registers 114 | #include "DSP281x_Xintf.h" // External Interface Registers 115 | #include "DSP281x_CpuTimers.h" // 32-bit CPU Timers 116 | #include "DSP281x_PieCtrl.h" // PIE Control Registers 117 | #include "DSP281x_PieVect.h" // PIE Vector Table 118 | #include "DSP281x_Spi.h" // SPI Registers 119 | #include "DSP281x_Sci.h" // SCI Registers 120 | #include "DSP281x_Mcbsp.h" // McBSP Registers 121 | #include "DSP281x_ECan.h" // Enhanced eCAN Registers 122 | #include "DSP281x_Gpio.h" // General Purpose I/O Registers 123 | #include "DSP281x_Ev.h" // Event Manager Registers 124 | #include "DSP281x_Adc.h" // ADC Registers 125 | #include "DSP281x_XIntrupt.h" // External Interrupts 126 | 127 | #ifdef __cplusplus 128 | } 129 | #endif /* extern "C" */ 130 | 131 | #endif // end of DSP281x_DEVICE_H definition 132 | 133 | 134 | //=========================================================================== 135 | // No more. 136 | //=========================================================================== 137 | -------------------------------------------------------------------------------- /src/DSP281x_ECan.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_ECan.c 4 | // 5 | // TITLE: DSP281x Enhanced CAN Initialization & Support Functions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | H.J. | Changes since previous version (v.58 Alpha) 12 | // | | | Added several initialization routines 13 | //########################################################################### 14 | 15 | #include "DSP281x_Device.h" // DSP28 Headerfile Include File 16 | #include "DSP281x_Examples.h" // DSP28 Examples Include File 17 | 18 | 19 | //--------------------------------------------------------------------------- 20 | // InitECan: 21 | //--------------------------------------------------------------------------- 22 | // This function initializes the eCAN module to a known state. 23 | // 24 | void InitECan(void) 25 | { 26 | 27 | long i; 28 | 29 | asm(" EALLOW"); 30 | 31 | /* Disable Watchdog */ 32 | DisableDog(); 33 | 34 | /* Enable peripheral clocks */ 35 | InitPeripheralClocks(); 36 | 37 | /* Set PLL multiplication factor */ 38 | InitPll(0xA); 39 | 40 | asm(" EALLOW"); 41 | 42 | /* Configure eCAN pins using GPIO regs*/ 43 | 44 | GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1; 45 | GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1; 46 | 47 | /* Configure eCAN RX and TX pins for eCAN transmissions using eCAN regs*/ 48 | 49 | ECanaRegs.CANTIOC.bit.TXFUNC = 1; 50 | ECanaRegs.CANRIOC.bit.RXFUNC = 1; 51 | 52 | /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ 53 | // HECC mode also enables time-stamping feature 54 | ECanaRegs.CANMC.bit.SCB = 1; 55 | 56 | /* Initialize all bits of 'Master Control Field' to zero */ 57 | // Some bits of MSGCTRL register come up in an unknown state. For proper operation, 58 | // all bits (including reserved bits) of MSGCTRL must be initialized to zero 59 | 60 | ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000; 61 | ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000; 62 | ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000; 63 | ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000; 64 | ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000; 65 | ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000; 66 | ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000; 67 | ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000; 68 | ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000; 69 | ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000; 70 | ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000; 71 | ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000; 72 | ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000; 73 | ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000; 74 | ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000; 75 | ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000; 76 | ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000; 77 | ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000; 78 | ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000; 79 | ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000; 80 | ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000; 81 | ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000; 82 | ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000; 83 | ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000; 84 | ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000; 85 | ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000; 86 | ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000; 87 | ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000; 88 | ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000; 89 | ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000; 90 | ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000; 91 | ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000; 92 | 93 | // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again 94 | // as a matter of precaution. 95 | 96 | /* Clear all TAn bits */ 97 | 98 | ECanaRegs.CANTA.all = 0xFFFFFFFF; 99 | 100 | /* Clear all RMPn bits */ 101 | 102 | ECanaRegs.CANRMP.all = 0xFFFFFFFF; 103 | 104 | /* Clear all interrupt flag bits */ 105 | 106 | ECanaRegs.CANGIF0.all = 0xFFFFFFFF; 107 | ECanaRegs.CANGIF1.all = 0xFFFFFFFF; 108 | 109 | /* Configure bit timing parameters */ 110 | 111 | ECanaRegs.CANMC.bit.CCR = 1 ; // Set CCR = 1 112 | 113 | while(ECanaRegs.CANES.bit.CCE != 1 ) {} // Wait for CCE bit to be set.. 114 | 115 | ECanaRegs.CANBTC.bit.BRPREG = 9; 116 | ECanaRegs.CANBTC.bit.TSEG2REG = 2; 117 | ECanaRegs.CANBTC.bit.TSEG1REG = 10; 118 | 119 | ECanaRegs.CANMC.bit.CCR = 0 ; // Set CCR = 0 120 | while(ECanaRegs.CANES.bit.CCE == !0 ) {} // Wait for CCE bit to be cleared.. 121 | 122 | /* Disable all Mailboxes */ 123 | 124 | ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs 125 | 126 | } 127 | 128 | /***************************************************/ 129 | /* Bit configuration parameters for 150 MHz SYSCLKOUT*/ 130 | /***************************************************/ 131 | /* 132 | 133 | The table below shows how BRP field must be changed to achieve different bit 134 | rates with a BT of 15, for a 80% SP: 135 | --------------------------------------------------- 136 | BT = 15, TSEG1 = 10, TSEG2 = 2, Sampling Point = 80% 137 | --------------------------------------------------- 138 | 1 Mbps : BRP+1 = 10 : CAN clock = 15 MHz 139 | 500 kbps : BRP+1 = 20 : CAN clock = 7.5 MHz 140 | 250 kbps : BRP+1 = 40 : CAN clock = 3.75 MHz 141 | 125 kbps : BRP+1 = 80 : CAN clock = 1.875 MHz 142 | 100 kbps : BRP+1 = 100 : CAN clock = 1.5 MHz 143 | 50 kbps : BRP+1 = 200 : CAN clock = 0.75 MHz 144 | 145 | The table below shows how to achieve different sampling points with a BT of 25: 146 | ------------------------------------------------------------- 147 | Achieving desired SP by changing TSEG1 & TSEG2 with BT = 25 148 | ------------------------------------------------------------- 149 | 150 | TSEG1 = 18, TSEG2 = 4, SP = 80% 151 | TSEG1 = 17, TSEG2 = 5, SP = 76% 152 | TSEG1 = 16, TSEG2 = 6, SP = 72% 153 | TSEG1 = 15, TSEG2 = 7, SP = 68% 154 | TSEG1 = 14, TSEG2 = 8, SP = 64% 155 | 156 | The table below shows how BRP field must be changed to achieve different bit 157 | rates with a BT of 25, for the sampling points shown above: 158 | 159 | 1 Mbps : BRP+1 = 6 160 | 500 kbps : BRP+1 = 12 161 | 250 kbps : BRP+1 = 24 162 | 125 kbps : BRP+1 = 48 163 | 100 kbps : BRP+1 = 60 164 | 50 kbps : BRP+1 = 120 165 | 166 | */ 167 | 168 | 169 | -------------------------------------------------------------------------------- /src/DSP281x_Ev.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Ev.c 4 | // 5 | // TITLE: DSP281x Event Manager Initialization & Support Functions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 15 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitEv: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes to a known state. 21 | // 22 | void InitEv(void) 23 | { 24 | 25 | } 26 | 27 | //=========================================================================== 28 | // No more. 29 | //=========================================================================== 30 | -------------------------------------------------------------------------------- /src/DSP281x_Examples.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Examples.h 4 | // 5 | // TITLE: DSP281x Device Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | First release. Seperated example specific headers 12 | // | | | from the DSP28 peripheral headers. 13 | // | | | Added DSP28_BIOS and DSP28_NONBIOS switches 14 | // | | | to include or not include the default ISR's 15 | //########################################################################### 16 | 17 | #ifndef DSP281x_EXAMPLES_H 18 | #define DSP281x_EXAMPLES_H 19 | 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | 26 | /*----------------------------------------------------------------------------- 27 | Specify the clock rate of the CPU (SYSCLKOUT) in nS. 28 | 29 | Take into account the input clock frequency and the PLL multiplier 30 | selected in step 1. 31 | 32 | Use one of the values provided, or define your own. 33 | The trailing L is required tells the compiler to treat 34 | the number as a 64-bit value. 35 | 36 | Only one statement should be uncommented. 37 | 38 | Example: CLKIN is a 30MHz crystal. 39 | 40 | In step 1 the user specified PLLCR = 0xA for a 41 | 150Mhz CPU clock (SYSCLKOUT = 150MHz). 42 | 43 | In this case, the CPU_RATE will be 6.667L 44 | Uncomment the line: #define CPU_RATE 6.667L 45 | -----------------------------------------------------------------------------*/ 46 | #define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) 47 | //#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) 48 | //#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) 49 | //#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) 50 | //#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) 51 | //#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) 52 | //#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) 53 | //#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) 54 | //#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) 55 | //#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) 56 | //#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) 57 | 58 | //---------------------------------------------------------------------------- 59 | 60 | 61 | 62 | //--------------------------------------------------------------------------- 63 | // Include Example Header Files: 64 | // 65 | 66 | #include "DSP281x_GlobalPrototypes.h" // Prototypes for global functions within the 67 | // .c files. 68 | 69 | #include "DSP281x_SWPrioritizedIsrLevels.h" // Used for Software Prioritization of ISR's 70 | 71 | 72 | // Include files not used with DSP/BIOS 73 | #ifndef DSP28_BIOS 74 | #include "DSP281x_DefaultISR.h" 75 | #endif 76 | 77 | 78 | // DO NOT MODIFY THIS LINE. 79 | #define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) 80 | 81 | 82 | #ifdef __cplusplus 83 | } 84 | #endif /* extern "C" */ 85 | 86 | #endif // end of DSP281x_EXAMPELS_H definition 87 | 88 | 89 | //=========================================================================== 90 | // No more. 91 | //=========================================================================== 92 | -------------------------------------------------------------------------------- /src/DSP281x_GlobalPrototypes.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_GlobalPrototypes.h 4 | // 5 | // TITLE: Global prototypes for DSP28 Examples 6 | //########################################################################### 7 | // 8 | // Ver | dd mmm yyyy | Who | Description of changes 9 | // =====|=============|======|=============================================== 10 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 11 | // | | | Corrected the filename and title in the 12 | // | | | header. 13 | // | | | Removed unused functions. Added InitPeripherals() 14 | //########################################################################### 15 | 16 | #ifndef DSP281x_GLOBALPROTOTYPES_H 17 | #define DSP281x_GLOBALPROTOTYPES_H 18 | 19 | 20 | #ifdef __cplusplus 21 | extern "C" { 22 | #endif 23 | 24 | /*---- shared global function prototypes -----------------------------------*/ 25 | extern void InitAdc(void); 26 | extern void InitPeripherals(void); 27 | extern void InitECan(void); 28 | extern void InitEv(void); 29 | extern void InitGpio(void); 30 | extern void InitMcbsp(void); 31 | extern void InitPieCtrl(void); 32 | extern void InitPieVectTable(void); 33 | extern void EnableInterrupts(void); 34 | extern void InitSci(void); 35 | extern void InitSpi(void); 36 | extern void InitSysCtrl(void); 37 | extern void InitXintf(void); 38 | extern void InitXIntrupt(void); 39 | extern void InitPll(Uint16 val); 40 | extern void InitPeripheralClocks(void); 41 | 42 | 43 | // Watchdog functions 44 | // DSP28_SysCtrl.c 45 | extern void KickDog(void); 46 | extern void DisableDog(void); 47 | 48 | // DSP28_DBGIER.asm 49 | extern void SetDBGIER(Uint16 dbgier); 50 | 51 | 52 | 53 | 54 | // CAUTION 55 | // This function MUST be executed out of RAM. Executing it 56 | // out of OTP/Flash will yield unpredictable results 57 | extern void InitFlash(void); 58 | 59 | 60 | void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); 61 | 62 | 63 | //--------------------------------------------------------------------------- 64 | // External symbols created by the linker cmd file 65 | // DSP28 examples will use these to relocate code from one LOAD location 66 | // in either Flash or XINTF to a different RUN location in internal 67 | // RAM 68 | extern Uint16 RamfuncsLoadStart; 69 | extern Uint16 RamfuncsLoadEnd; 70 | extern Uint16 RamfuncsRunStart; 71 | 72 | #ifdef __cplusplus 73 | } 74 | #endif /* extern "C" */ 75 | 76 | #endif // - end of DSP281x_GLOBALPROTOTYPES_H 77 | 78 | -------------------------------------------------------------------------------- /src/DSP281x_GlobalVariableDefs.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_GlobalVariableDefs.c 4 | // 5 | // TITLE: DSP281x Global Variables and Data Section Pragmas. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Added support for C++ 13 | //########################################################################### 14 | 15 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // Define Global Peripheral Variables: 19 | // 20 | 21 | #ifdef __cplusplus 22 | #pragma DATA_SECTION("AdcRegsFile") 23 | #else 24 | #pragma DATA_SECTION(AdcRegs,"AdcRegsFile"); 25 | #endif 26 | volatile struct ADC_REGS AdcRegs; 27 | 28 | 29 | #ifdef __cplusplus 30 | #pragma DATA_SECTION("CpuTimer0RegsFile") 31 | #else 32 | #pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); 33 | #endif 34 | volatile struct CPUTIMER_REGS CpuTimer0Regs; 35 | 36 | 37 | // CPU Timer 1 and Timer2 are reserved for BIOS and thus not used 38 | //#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); 39 | //volatile struct CPUTIMER_REGS CpuTimer1Regs; 40 | //#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); 41 | //volatile struct CPUTIMER_REGS CpuTimer2Regs; 42 | 43 | //---------------------------------------- 44 | #ifdef __cplusplus 45 | #pragma DATA_SECTION("ECanaRegsFile") 46 | #else 47 | #pragma DATA_SECTION(ECanaRegs,"ECanaRegsFile"); 48 | #endif 49 | volatile struct ECAN_REGS ECanaRegs; 50 | 51 | //---------------------------------------- 52 | #ifdef __cplusplus 53 | #pragma DATA_SECTION("ECanaMboxesFile") 54 | #else 55 | #pragma DATA_SECTION(ECanaMboxes,"ECanaMboxesFile"); 56 | #endif 57 | volatile struct ECAN_MBOXES ECanaMboxes; 58 | 59 | //---------------------------------------- 60 | #ifdef __cplusplus 61 | #pragma DATA_SECTION("ECanaLAMRegsFile") 62 | #else 63 | #pragma DATA_SECTION(ECanaLAMRegs,"ECanaLAMRegsFile"); 64 | #endif 65 | volatile struct LAM_REGS ECanaLAMRegs; 66 | 67 | //---------------------------------------- 68 | #ifdef __cplusplus 69 | #pragma DATA_SECTION("ECanaMOTSRegsFile") 70 | #else 71 | #pragma DATA_SECTION(ECanaMOTSRegs,"ECanaMOTSRegsFile"); 72 | #endif 73 | volatile struct MOTS_REGS ECanaMOTSRegs; 74 | 75 | 76 | //---------------------------------------- 77 | #ifdef __cplusplus 78 | #pragma DATA_SECTION("ECanaMOTORegsFile") 79 | #else 80 | #pragma DATA_SECTION(ECanaMOTORegs,"ECanaMOTORegsFile"); 81 | #endif 82 | volatile struct MOTO_REGS ECanaMOTORegs; 83 | 84 | //---------------------------------------- 85 | #ifdef __cplusplus 86 | #pragma DATA_SECTION("EvaRegsFile") 87 | #else 88 | #pragma DATA_SECTION(EvaRegs,"EvaRegsFile"); 89 | #endif 90 | volatile struct EVA_REGS EvaRegs; 91 | 92 | //---------------------------------------- 93 | #ifdef __cplusplus 94 | #pragma DATA_SECTION("EvbRegsFile") 95 | #else 96 | #pragma DATA_SECTION(EvbRegs,"EvbRegsFile"); 97 | #endif 98 | volatile struct EVB_REGS EvbRegs; 99 | 100 | //---------------------------------------- 101 | #ifdef __cplusplus 102 | #pragma DATA_SECTION("GpioDataRegsFile") 103 | #else 104 | #pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); 105 | #endif 106 | volatile struct GPIO_DATA_REGS GpioDataRegs; 107 | 108 | //---------------------------------------- 109 | #ifdef __cplusplus 110 | #pragma DATA_SECTION("GpioMuxRegsFile") 111 | #else 112 | #pragma DATA_SECTION(GpioMuxRegs,"GpioMuxRegsFile"); 113 | #endif 114 | volatile struct GPIO_MUX_REGS GpioMuxRegs; 115 | 116 | //---------------------------------------- 117 | #ifdef __cplusplus 118 | #pragma DATA_SECTION("McbspaRegsFile") 119 | #else 120 | #pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); 121 | #endif 122 | volatile struct MCBSP_REGS McbspaRegs; 123 | 124 | //---------------------------------------- 125 | #ifdef __cplusplus 126 | #pragma DATA_SECTION("PieCtrlRegsFile") 127 | #else 128 | #pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); 129 | #endif 130 | volatile struct PIE_CTRL_REGS PieCtrlRegs; 131 | 132 | //---------------------------------------- 133 | #ifdef __cplusplus 134 | #pragma DATA_SECTION("PieVectTableFile") 135 | #else 136 | #pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); 137 | #endif 138 | struct PIE_VECT_TABLE PieVectTable; 139 | 140 | //---------------------------------------- 141 | #ifdef __cplusplus 142 | #pragma DATA_SECTION("SciaRegsFile") 143 | #else 144 | #pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); 145 | #endif 146 | volatile struct SCI_REGS SciaRegs; 147 | 148 | //---------------------------------------- 149 | #ifdef __cplusplus 150 | #pragma DATA_SECTION("ScibRegsFile") 151 | #else 152 | #pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); 153 | #endif 154 | volatile struct SCI_REGS ScibRegs; 155 | 156 | //---------------------------------------- 157 | #ifdef __cplusplus 158 | #pragma DATA_SECTION("SpiaRegsFile") 159 | #else 160 | #pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); 161 | #endif 162 | volatile struct SPI_REGS SpiaRegs; 163 | 164 | //---------------------------------------- 165 | #ifdef __cplusplus 166 | #pragma DATA_SECTION("SysCtrlRegsFile") 167 | #else 168 | #pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile"); 169 | #endif 170 | volatile struct SYS_CTRL_REGS SysCtrlRegs; 171 | 172 | //---------------------------------------- 173 | #ifdef __cplusplus 174 | #pragma DATA_SECTION("DevEmuRegsFile") 175 | #else 176 | #pragma DATA_SECTION(DevEmuRegs,"DevEmuRegsFile"); 177 | #endif 178 | volatile struct DEV_EMU_REGS DevEmuRegs; 179 | 180 | //---------------------------------------- 181 | #ifdef __cplusplus 182 | #pragma DATA_SECTION("CsmRegsFile") 183 | #else 184 | #pragma DATA_SECTION(CsmRegs,"CsmRegsFile"); 185 | #endif 186 | volatile struct CSM_REGS CsmRegs; 187 | 188 | //---------------------------------------- 189 | #ifdef __cplusplus 190 | #pragma DATA_SECTION("CsmPwlFile") 191 | #else 192 | #pragma DATA_SECTION(CsmPwl,"CsmPwlFile"); 193 | #endif 194 | volatile struct CSM_PWL CsmPwl; 195 | 196 | 197 | //---------------------------------------- 198 | #ifdef __cplusplus 199 | #pragma DATA_SECTION("FlashRegsFile") 200 | #else 201 | #pragma DATA_SECTION(FlashRegs,"FlashRegsFile"); 202 | #endif 203 | volatile struct FLASH_REGS FlashRegs; 204 | 205 | #if DSP28_F2812 206 | //---------------------------------------- 207 | #ifdef __cplusplus 208 | #pragma DATA_SECTION("XintfRegsFile") 209 | #else 210 | #pragma DATA_SECTION(XintfRegs,"XintfRegsFile"); 211 | #endif 212 | volatile struct XINTF_REGS XintfRegs; 213 | #endif 214 | 215 | //---------------------------------------- 216 | #ifdef __cplusplus 217 | #pragma DATA_SECTION("XIntruptRegsFile") 218 | #else 219 | #pragma DATA_SECTION(XIntruptRegs,"XIntruptRegsFile"); 220 | #endif 221 | volatile struct XINTRUPT_REGS XIntruptRegs; 222 | 223 | 224 | 225 | // The following are provided to support alternate notation 226 | // that was used in an early version of the header files 227 | 228 | #define ADCRegs AdcRegs 229 | #define CPUTimer0Regs CpuTimer0Regs 230 | #define ECANARegs ECanaRegs 231 | #define ECANAMboxes ECanaMboxes 232 | #define EVARegs EvaRegs 233 | #define GPIODataRegs GpioDataRegs 234 | #define GPIOMuxRegs GpioMuxRegs 235 | #define MCBSPARegs McbspaRegs 236 | #define PIECtrlRegs PieCtrlRegs 237 | #define PIEVectTable PieVectTable 238 | #define SCIARegs SciaRegs 239 | #define SCIBRegs ScibRegs 240 | #define SYSCtrlRegs SysCtrlRegs 241 | #define DEVEmuRegs DevEmuRegs 242 | #define CSMRegs CsmRegs 243 | #define CSMPwl CsmPwl 244 | #define FLASHRegs FlashRegs 245 | #define XINTFRegs XintfRegs 246 | #define XINTRUPTRegs XIntruptRegs 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | -------------------------------------------------------------------------------- /src/DSP281x_Gpio.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Gpio.c 4 | // 5 | // TITLE: DSP281x General Purpose I/O Initialization & Support Functions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 15 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitGpio: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes the Gpio to a known state. 21 | // 22 | void InitGpio(void) 23 | { 24 | 25 | // Set GPIO A port pins,AL(Bits 7:0)(input)-AH(Bits 15:8) (output) 8bits 26 | // Input Qualifier =0, none 27 | EALLOW; 28 | GpioMuxRegs.GPAMUX.all=0x0000; 29 | GpioMuxRegs.GPADIR.all=0xFF00; // upper byte as output/low byte as input 30 | GpioMuxRegs.GPAQUAL.all=0x0000; // Input qualifier disabled 31 | 32 | // Set GPIO B port pins, configured as EVB signals 33 | // Input Qualifier =0, none 34 | // Set bits to 1 to configure peripherals signals on the pins 35 | GpioMuxRegs.GPBMUX.all=0xFFFF; 36 | GpioMuxRegs.GPBQUAL.all=0x0000; // Input qualifier disabled 37 | EDIS; 38 | 39 | } 40 | 41 | //=========================================================================== 42 | // No more. 43 | //=========================================================================== 44 | -------------------------------------------------------------------------------- /src/DSP281x_Headers_nonBIOS.cmd: -------------------------------------------------------------------------------- 1 | /* 2 | //########################################################################### 3 | // 4 | // FILE: DSP281x_Headers_nonBIOS.cmd 5 | // 6 | // TITLE: DSP281x Peripheral registers linker command file 7 | // 8 | // DESCRIPTION: 9 | // 10 | // This file is for use in Non-BIOS applications. 11 | // 12 | // Linker command file to place the peripheral structures 13 | // used within the DSP28 headerfiles into the correct memory 14 | // mapped locations. 15 | // 16 | // This version of the file includes the PieVectorTable structure. 17 | // For BIOS applications, please use the DSP281x_Headers_BIOS.cmd file 18 | // which does not include the PieVectorTable structure. 19 | // 20 | //########################################################################### 21 | // 22 | // Ver | dd mmm yyyy | Who | Description of changes 23 | // =====|=============|======|=============================================== 24 | // | 05 Mar 2003 | D.A. | Original based on DSP28 v0.58 25 | // 1.00| 11 Sep 2003 | L.H. | Integrated into DSP28 header files 26 | // | | | Added missing eCAN file sections 27 | // -----|-------------|------|----------------------------------------------- 28 | //########################################################################### 29 | */ 30 | -stack 400h 31 | MEMORY 32 | { 33 | PAGE 0: /* Program Memory */ 34 | 35 | PAGE 1: /* Data Memory */ 36 | 37 | DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ 38 | PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */ 39 | FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ 40 | CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ 41 | XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ 42 | CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 and Timer2 are reserved for BIOS)*/ 43 | PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ 44 | ECANA : origin = 0x006000, length = 0x000040 /* eCAN control and status registers */ 45 | ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN local acceptance masks */ 46 | ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN message object time stamps */ 47 | ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN object time-out registers */ 48 | ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN mailboxes */ 49 | SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ 50 | SPIA : origin = 0x007040, length = 0x000010 /* SPI registers */ 51 | SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ 52 | XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ 53 | GPIOMUX : origin = 0x0070C0, length = 0x000020 /* GPIO mux registers */ 54 | GPIODAT : origin = 0x0070E0, length = 0x000020 /* GPIO data registers */ 55 | ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ 56 | EVA : origin = 0x007400, length = 0x000040 /* Event Manager A registers */ 57 | EVB : origin = 0x007500, length = 0x000040 /* Event Manager B registers */ 58 | SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ 59 | MCBSPA : origin = 0x007800, length = 0x000040 /* McBSP registers */ 60 | CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ 61 | } 62 | 63 | 64 | SECTIONS 65 | { 66 | PieVectTableFile : > PIE_VECT, PAGE = 1 67 | 68 | /*** Peripheral Frame 0 Register Structures ***/ 69 | DevEmuRegsFile : > DEV_EMU, PAGE = 1 70 | FlashRegsFile : > FLASH_REGS, PAGE = 1 71 | CsmRegsFile : > CSM, PAGE = 1 72 | XintfRegsFile : > XINTF, PAGE = 1 73 | CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 74 | PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 75 | 76 | /*** Peripheral Frame 1 Register Structures ***/ 77 | SysCtrlRegsFile : > SYSTEM, PAGE = 1 78 | SpiaRegsFile : > SPIA, PAGE = 1 79 | SciaRegsFile : > SCIA, PAGE = 1 80 | XIntruptRegsFile : > XINTRUPT, PAGE = 1 81 | GpioMuxRegsFile : > GPIOMUX, PAGE = 1 82 | GpioDataRegsFile : > GPIODAT PAGE = 1 83 | AdcRegsFile : > ADC, PAGE = 1 84 | EvaRegsFile : > EVA, PAGE = 1 85 | EvbRegsFile : > EVB, PAGE = 1 86 | ScibRegsFile : > SCIB, PAGE = 1 87 | McbspaRegsFile : > MCBSPA, PAGE = 1 88 | 89 | /*** Peripheral Frame 2 Register Structures ***/ 90 | ECanaRegsFile : > ECANA, PAGE = 1 91 | ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 92 | ECanaMboxesFile : > ECANA_MBOX PAGE = 1 93 | ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 94 | ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 95 | 96 | /*** Code Security Module Register Structures ***/ 97 | CsmPwlFile : > CSM_PWL, PAGE = 1 98 | } 99 | 100 | 101 | /******************* end of file ************************/ -------------------------------------------------------------------------------- /src/DSP281x_InitPeripherals.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_InitPeripherals.c 4 | // 5 | // TITLE: DSP281x Device Initialization To Default State. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 15 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitPeripherals: 19 | //--------------------------------------------------------------------------- 20 | // The following function initializes the peripherals to a default state. 21 | // It calls each of the peripherals default initialization functions. 22 | // This function should be executed at boot time or on a soft reset. 23 | // 24 | void InitPeripherals(void) 25 | { 26 | 27 | #if DSP28_F2812 28 | // Initialize External Interface To default State: 29 | InitXintf(); 30 | #endif 31 | 32 | // Initialize CPU Timers To default State: 33 | InitCpuTimers(); 34 | 35 | // Initialize McBSP Peripheral To default State: 36 | InitMcbsp(); 37 | 38 | // Initialize Event Manager Peripheral To default State: 39 | InitEv(); 40 | 41 | // Initialize ADC Peripheral To default State: 42 | InitAdc(); 43 | 44 | // Initialize eCAN Peripheral To default State: 45 | InitECan(); 46 | 47 | // Initialize SPI Peripherals To default State: 48 | InitSpi(); 49 | 50 | // Initialize SCI Peripherals To default State: 51 | InitSci(); 52 | } 53 | 54 | //=========================================================================== 55 | // No more. 56 | //=========================================================================== 57 | -------------------------------------------------------------------------------- /src/DSP281x_Mcbsp.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_McBSP.c 4 | // 5 | // TITLE: DSP281x Device McBSP Initialization & Support Functions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 15 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitMcbsp: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes the McBSP to a known state. 21 | // 22 | void InitMcbsp(void) 23 | { 24 | 25 | //tbd... 26 | 27 | } 28 | 29 | //=========================================================================== 30 | // No more. 31 | //=========================================================================== 32 | -------------------------------------------------------------------------------- /src/DSP281x_MemCopy.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_MemCopy.c 4 | // 5 | // TITLE: Memory Copy Utility 6 | // 7 | // ASSUMPTIONS: 8 | // 9 | // 10 | // 11 | // DESCRIPTION: 12 | // 13 | // This function will copy the specified memory contents from 14 | // one location to another. 15 | // 16 | // Uint16 *SourceAddr Pointer to the first word to be moved 17 | // SourceAddr < SourceEndAddr 18 | // Uint16* SourceEndAddr Pointer to the last word to be moved 19 | // Uint16* DestAddr Pointer to the first destination word 20 | // 21 | // No checks are made for invalid memory locations or that the 22 | // end address is > then the first start address. 23 | // 24 | // 25 | //########################################################################### 26 | // 27 | // Ver | dd mmm yyyy | Who | Description of changes 28 | // =====|=============|======|=============================================== 29 | // 1.00| 11 Sep 2003 | L.H. | No changes since previous version (v.58 Alpha) 30 | // 31 | //########################################################################### 32 | 33 | #include "DSP281x_Device.h" 34 | 35 | void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr) 36 | { 37 | while(SourceAddr < SourceEndAddr) 38 | { 39 | *DestAddr++ = *SourceAddr++; 40 | } 41 | return; 42 | } 43 | -------------------------------------------------------------------------------- /src/DSP281x_PieCtrl.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_PieCtrl.c 4 | // 5 | // TITLE: DSP281x Device PIE Control Register Initialization Functions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Added ENPIE = 0 to the IntPieCtrl function 13 | // | | | Removed ENPIE = 1 from the IntPieCtrl function 14 | // | | | Created EnableInterrupts function 15 | //########################################################################### 16 | 17 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 18 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 19 | 20 | //--------------------------------------------------------------------------- 21 | // InitPieCtrl: 22 | //--------------------------------------------------------------------------- 23 | // This function initializes the PIE control registers to a known state. 24 | // 25 | void InitPieCtrl(void) 26 | { 27 | // Disable Interrupts at the CPU level: 28 | DINT; 29 | 30 | // Disable the PIE 31 | PieCtrlRegs.PIECRTL.bit.ENPIE = 0; 32 | 33 | // Clear all PIEIER registers: 34 | PieCtrlRegs.PIEIER1.all = 0; 35 | PieCtrlRegs.PIEIER2.all = 0; 36 | PieCtrlRegs.PIEIER3.all = 0; 37 | PieCtrlRegs.PIEIER4.all = 0; 38 | PieCtrlRegs.PIEIER5.all = 0; 39 | PieCtrlRegs.PIEIER6.all = 0; 40 | PieCtrlRegs.PIEIER7.all = 0; 41 | PieCtrlRegs.PIEIER8.all = 0; 42 | PieCtrlRegs.PIEIER9.all = 0; 43 | PieCtrlRegs.PIEIER10.all = 0; 44 | PieCtrlRegs.PIEIER11.all = 0; 45 | PieCtrlRegs.PIEIER12.all = 0; 46 | 47 | // Clear all PIEIFR registers: 48 | PieCtrlRegs.PIEIFR1.all = 0; 49 | PieCtrlRegs.PIEIFR2.all = 0; 50 | PieCtrlRegs.PIEIFR3.all = 0; 51 | PieCtrlRegs.PIEIFR4.all = 0; 52 | PieCtrlRegs.PIEIFR5.all = 0; 53 | PieCtrlRegs.PIEIFR6.all = 0; 54 | PieCtrlRegs.PIEIFR7.all = 0; 55 | PieCtrlRegs.PIEIFR8.all = 0; 56 | PieCtrlRegs.PIEIFR9.all = 0; 57 | PieCtrlRegs.PIEIFR10.all = 0; 58 | PieCtrlRegs.PIEIFR11.all = 0; 59 | PieCtrlRegs.PIEIFR12.all = 0; 60 | 61 | 62 | } 63 | 64 | //--------------------------------------------------------------------------- 65 | // EnableInterrupts: 66 | //--------------------------------------------------------------------------- 67 | // This function enables the PIE module and CPU interrupts 68 | // 69 | void EnableInterrupts() 70 | { 71 | 72 | // Enable the PIE 73 | PieCtrlRegs.PIECRTL.bit.ENPIE = 1; 74 | 75 | // Enables PIE to drive a pulse into the CPU 76 | PieCtrlRegs.PIEACK.all = 0xFFFF; 77 | 78 | // Enable Interrupts at the CPU level 79 | EINT; 80 | 81 | } 82 | 83 | 84 | //=========================================================================== 85 | // No more. 86 | //=========================================================================== 87 | -------------------------------------------------------------------------------- /src/DSP281x_PieCtrl.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_PieCtrl.h 4 | // 5 | // TITLE: DSP281x Device PIE Control Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | 15 | #ifndef DSP281x_PIE_CTRL_H 16 | #define DSP281x_PIE_CTRL_H 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //--------------------------------------------------------------------------- 23 | // PIE Control Register Bit Definitions: 24 | // 25 | // PIECTRL: Register bit definitions: 26 | struct PIECTRL_BITS { // bits description 27 | Uint16 ENPIE:1; // 0 Enable PIE block 28 | Uint16 PIEVECT:15; // 15:1 Fetched vector address 29 | }; 30 | 31 | union PIECTRL_REG { 32 | Uint16 all; 33 | struct PIECTRL_BITS bit; 34 | }; 35 | 36 | // PIEIER: Register bit definitions: 37 | struct PIEIER_BITS { // bits description 38 | Uint16 INTx1:1; // 0 INTx.1 39 | Uint16 INTx2:1; // 1 INTx.2 40 | Uint16 INTx3:1; // 2 INTx.3 41 | Uint16 INTx4:1; // 3 INTx.4 42 | Uint16 INTx5:1; // 4 INTx.5 43 | Uint16 INTx6:1; // 5 INTx.6 44 | Uint16 INTx7:1; // 6 INTx.7 45 | Uint16 INTx8:1; // 7 INTx.8 46 | Uint16 rsvd:8; // 15:8 reserved 47 | }; 48 | 49 | union PIEIER_REG { 50 | Uint16 all; 51 | struct PIEIER_BITS bit; 52 | }; 53 | 54 | // PIEIFR: Register bit definitions: 55 | struct PIEIFR_BITS { // bits description 56 | Uint16 INTx1:1; // 0 INTx.1 57 | Uint16 INTx2:1; // 1 INTx.2 58 | Uint16 INTx3:1; // 2 INTx.3 59 | Uint16 INTx4:1; // 3 INTx.4 60 | Uint16 INTx5:1; // 4 INTx.5 61 | Uint16 INTx6:1; // 5 INTx.6 62 | Uint16 INTx7:1; // 6 INTx.7 63 | Uint16 INTx8:1; // 7 INTx.8 64 | Uint16 rsvd:8; // 15:8 reserved 65 | }; 66 | 67 | union PIEIFR_REG { 68 | Uint16 all; 69 | struct PIEIFR_BITS bit; 70 | }; 71 | 72 | // PIEACK: Register bit definitions: 73 | struct PIEACK_BITS { // bits description 74 | Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 75 | Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 76 | Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 77 | Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 78 | Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 79 | Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 80 | Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 81 | Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 82 | Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 83 | Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 84 | Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 85 | Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 86 | Uint16 rsvd:4; // 15:12 reserved 87 | }; 88 | 89 | union PIEACK_REG { 90 | Uint16 all; 91 | struct PIEACK_BITS bit; 92 | }; 93 | 94 | //--------------------------------------------------------------------------- 95 | // PIE Control Register File: 96 | // 97 | struct PIE_CTRL_REGS { 98 | union PIECTRL_REG PIECRTL; // PIE control register 99 | union PIEACK_REG PIEACK; // PIE acknowledge 100 | union PIEIER_REG PIEIER1; // PIE INT1 IER register 101 | union PIEIFR_REG PIEIFR1; // PIE INT1 IFR register 102 | union PIEIER_REG PIEIER2; // PIE INT2 IER register 103 | union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register 104 | union PIEIER_REG PIEIER3; // PIE INT3 IER register 105 | union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register 106 | union PIEIER_REG PIEIER4; // PIE INT4 IER register 107 | union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register 108 | union PIEIER_REG PIEIER5; // PIE INT5 IER register 109 | union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register 110 | union PIEIER_REG PIEIER6; // PIE INT6 IER register 111 | union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register 112 | union PIEIER_REG PIEIER7; // PIE INT7 IER register 113 | union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register 114 | union PIEIER_REG PIEIER8; // PIE INT8 IER register 115 | union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register 116 | union PIEIER_REG PIEIER9; // PIE INT9 IER register 117 | union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register 118 | union PIEIER_REG PIEIER10; // PIE INT10 IER register 119 | union PIEIFR_REG PIEIFR10; // PIE INT10 IFR register 120 | union PIEIER_REG PIEIER11; // PIE INT11 IER register 121 | union PIEIFR_REG PIEIFR11; // PIE INT11 IFR register 122 | union PIEIER_REG PIEIER12; // PIE INT12 IER register 123 | union PIEIFR_REG PIEIFR12; // PIE INT12 IFR register 124 | }; 125 | 126 | #define PIEACK_GROUP1 0x0001; 127 | #define PIEACK_GROUP2 0x0002; 128 | #define PIEACK_GROUP3 0x0004; 129 | #define PIEACK_GROUP4 0x0008; 130 | #define PIEACK_GROUP5 0x0010; 131 | #define PIEACK_GROUP6 0x0020; 132 | #define PIEACK_GROUP7 0x0040; 133 | #define PIEACK_GROUP8 0x0080; 134 | #define PIEACK_GROUP9 0x0100; 135 | #define PIEACK_GROUP10 0x0200; 136 | #define PIEACK_GROUP11 0x0400; 137 | #define PIEACK_GROUP12 0x0800; 138 | 139 | //--------------------------------------------------------------------------- 140 | // PIE Control Registers External References & Function Declarations: 141 | // 142 | extern volatile struct PIE_CTRL_REGS PieCtrlRegs; 143 | 144 | 145 | #ifdef __cplusplus 146 | } 147 | #endif /* extern "C" */ 148 | 149 | #endif // end of DSP281x_PIE_CTRL_H definition 150 | 151 | //=========================================================================== 152 | // No more. 153 | //=========================================================================== 154 | -------------------------------------------------------------------------------- /src/DSP281x_PieVect.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_PieVect.c 4 | // 5 | // TITLE: DSP281x Devices PIE Vector Table Initialization Functions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Changed USER0-USER11 to USER1-USER12 to match the CPU guide 13 | //########################################################################### 14 | 15 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 16 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 17 | 18 | const struct PIE_VECT_TABLE PieVectTableInit = { 19 | 20 | PIE_RESERVED, // Reserved space 21 | PIE_RESERVED, 22 | PIE_RESERVED, 23 | PIE_RESERVED, 24 | PIE_RESERVED, 25 | PIE_RESERVED, 26 | PIE_RESERVED, 27 | PIE_RESERVED, 28 | PIE_RESERVED, 29 | PIE_RESERVED, 30 | PIE_RESERVED, 31 | PIE_RESERVED, 32 | PIE_RESERVED, 33 | 34 | 35 | // Non-Peripheral Interrupts 36 | INT13_ISR, // XINT13 or CPU-Timer 1 37 | INT14_ISR, // CPU-Timer2 38 | DATALOG_ISR, // Datalogging interrupt 39 | RTOSINT_ISR, // RTOS interrupt 40 | EMUINT_ISR, // Emulation interrupt 41 | NMI_ISR, // Non-maskable interrupt 42 | ILLEGAL_ISR, // Illegal operation TRAP 43 | USER1_ISR, // User Defined trap 1 44 | USER2_ISR, // User Defined trap 2 45 | USER3_ISR, // User Defined trap 3 46 | USER4_ISR, // User Defined trap 4 47 | USER5_ISR, // User Defined trap 5 48 | USER6_ISR, // User Defined trap 6 49 | USER7_ISR, // User Defined trap 7 50 | USER8_ISR, // User Defined trap 8 51 | USER9_ISR, // User Defined trap 9 52 | USER10_ISR, // User Defined trap 10 53 | USER11_ISR, // User Defined trap 11 54 | USER12_ISR, // User Defined trap 12 55 | 56 | 57 | // Group 1 PIE Vectors 58 | PDPINTA_ISR, // EV-A 59 | PDPINTB_ISR, // EV-B 60 | rsvd_ISR, 61 | XINT1_ISR, 62 | XINT2_ISR, 63 | ADCINT_ISR, // ADC 64 | TINT0_ISR, // Timer 0 65 | WAKEINT_ISR, // WD 66 | 67 | // Group 2 PIE Vectors 68 | CMP1INT_ISR, // EV-A 69 | CMP2INT_ISR, // EV-A 70 | CMP3INT_ISR, // EV-A 71 | T1PINT_ISR, // EV-A 72 | T1CINT_ISR, // EV-A 73 | T1UFINT_ISR, // EV-A 74 | T1OFINT_ISR, // EV-A 75 | rsvd_ISR, 76 | 77 | // Group 3 PIE Vectors 78 | T2PINT_ISR, // EV-A 79 | T2CINT_ISR, // EV-A 80 | T2UFINT_ISR, // EV-A 81 | T2OFINT_ISR, // EV-A 82 | CAPINT1_ISR, // EV-A 83 | CAPINT2_ISR, // EV-A 84 | CAPINT3_ISR, // EV-A 85 | rsvd_ISR, 86 | 87 | // Group 4 PIE Vectors 88 | CMP4INT_ISR, // EV-B 89 | CMP5INT_ISR, // EV-B 90 | CMP6INT_ISR, // EV-B 91 | T3PINT_ISR, // EV-B 92 | T3CINT_ISR, // EV-B 93 | T3UFINT_ISR, // EV-B 94 | T3OFINT_ISR, // EV-B 95 | rsvd_ISR, 96 | 97 | // Group 5 PIE Vectors 98 | T4PINT_ISR, // EV-B 99 | T4CINT_ISR, // EV-B 100 | T4UFINT_ISR, // EV-B 101 | T4OFINT_ISR, // EV-B 102 | CAPINT4_ISR, // EV-B 103 | CAPINT5_ISR, // EV-B 104 | CAPINT6_ISR, // EV-B 105 | rsvd_ISR, 106 | 107 | // Group 6 PIE Vectors 108 | SPIRXINTA_ISR, // SPI-A 109 | SPITXINTA_ISR, // SPI-A 110 | rsvd_ISR, 111 | rsvd_ISR, 112 | MRINTA_ISR, // McBSP-A 113 | MXINTA_ISR, // McBSP-A 114 | rsvd_ISR, 115 | rsvd_ISR, 116 | 117 | // Group 7 PIE Vectors 118 | rsvd_ISR, 119 | rsvd_ISR, 120 | rsvd_ISR, 121 | rsvd_ISR, 122 | rsvd_ISR, 123 | rsvd_ISR, 124 | rsvd_ISR, 125 | rsvd_ISR, 126 | 127 | // Group 8 PIE Vectors 128 | rsvd_ISR, 129 | rsvd_ISR, 130 | rsvd_ISR, 131 | rsvd_ISR, 132 | rsvd_ISR, 133 | rsvd_ISR, 134 | rsvd_ISR, 135 | rsvd_ISR, 136 | 137 | // Group 9 PIE Vectors 138 | SCIRXINTA_ISR, // SCI-A 139 | SCITXINTA_ISR, // SCI-A 140 | SCIRXINTB_ISR, // SCI-B 141 | SCITXINTB_ISR, // SCI-B 142 | ECAN0INTA_ISR, // eCAN 143 | ECAN1INTA_ISR, // eCAN 144 | rsvd_ISR, 145 | rsvd_ISR, 146 | 147 | // Group 10 PIE Vectors 148 | rsvd_ISR, 149 | rsvd_ISR, 150 | rsvd_ISR, 151 | rsvd_ISR, 152 | rsvd_ISR, 153 | rsvd_ISR, 154 | rsvd_ISR, 155 | rsvd_ISR, 156 | 157 | // Group 11 PIE Vectors 158 | rsvd_ISR, 159 | rsvd_ISR, 160 | rsvd_ISR, 161 | rsvd_ISR, 162 | rsvd_ISR, 163 | rsvd_ISR, 164 | rsvd_ISR, 165 | rsvd_ISR, 166 | 167 | // Group 12 PIE Vectors 168 | rsvd_ISR, 169 | rsvd_ISR, 170 | rsvd_ISR, 171 | rsvd_ISR, 172 | rsvd_ISR, 173 | rsvd_ISR, 174 | rsvd_ISR, 175 | rsvd_ISR, 176 | }; 177 | 178 | 179 | //--------------------------------------------------------------------------- 180 | // InitPieVectTable: 181 | //--------------------------------------------------------------------------- 182 | // This function initializes the PIE vector table to a known state. 183 | // This function must be executed after boot time. 184 | // 185 | 186 | void InitPieVectTable(void) 187 | { 188 | int16 i; 189 | Uint32 *Source = (void *) &PieVectTableInit; 190 | Uint32 *Dest = (void *) &PieVectTable; 191 | 192 | EALLOW; 193 | for(i=0; i < 128; i++) 194 | *Dest++ = *Source++; 195 | EDIS; 196 | 197 | // Enable the PIE Vector Table 198 | PieCtrlRegs.PIECRTL.bit.ENPIE = 1; 199 | 200 | } 201 | 202 | //=========================================================================== 203 | // No more. 204 | //=========================================================================== 205 | -------------------------------------------------------------------------------- /src/DSP281x_PieVect.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_PieVect.h 4 | // 5 | // TITLE: DSP281x Devices PIE Vector Table Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Changed USER0-USER11 to USER1-USER12 to match the CPU guide 13 | //########################################################################### 14 | 15 | #ifndef DSP281x_PIE_VECT_H 16 | #define DSP281x_PIE_VECT_H 17 | 18 | 19 | #ifdef __cplusplus 20 | extern "C" { 21 | #endif 22 | 23 | 24 | //--------------------------------------------------------------------------- 25 | // PIE Interrupt Vector Table Definition: 26 | // 27 | // Create a user type called PINT (pointer to interrupt): 28 | 29 | typedef interrupt void(*PINT)(void); 30 | 31 | // Define Vector Table: 32 | struct PIE_VECT_TABLE { 33 | 34 | // Reset is never fetched from this table. 35 | // It will always be fetched from 0x3FFFC0 in either 36 | // boot ROM or XINTF Zone 7 depending on the state of 37 | // the XMP/MC input signal. On the F2810 it is always 38 | // fetched from boot ROM. 39 | 40 | PINT PIE1_RESERVED; 41 | PINT PIE2_RESERVED; 42 | PINT PIE3_RESERVED; 43 | PINT PIE4_RESERVED; 44 | PINT PIE5_RESERVED; 45 | PINT PIE6_RESERVED; 46 | PINT PIE7_RESERVED; 47 | PINT PIE8_RESERVED; 48 | PINT PIE9_RESERVED; 49 | PINT PIE10_RESERVED; 50 | PINT PIE11_RESERVED; 51 | PINT PIE12_RESERVED; 52 | PINT PIE13_RESERVED; 53 | 54 | // Non-Peripheral Interrupts: 55 | PINT XINT13; // XINT13 56 | PINT TINT2; // CPU-Timer2 57 | PINT DATALOG; // Datalogging interrupt 58 | PINT RTOSINT; // RTOS interrupt 59 | PINT EMUINT; // Emulation interrupt 60 | PINT XNMI; // Non-maskable interrupt 61 | PINT ILLEGAL; // Illegal operation TRAP 62 | PINT USER1; // User Defined trap 1 63 | PINT USER2; // User Defined trap 2 64 | PINT USER3; // User Defined trap 3 65 | PINT USER4; // User Defined trap 4 66 | PINT USER5; // User Defined trap 5 67 | PINT USER6; // User Defined trap 6 68 | PINT USER7; // User Defined trap 7 69 | PINT USER8; // User Defined trap 8 70 | PINT USER9; // User Defined trap 9 71 | PINT USER10; // User Defined trap 10 72 | PINT USER11; // User Defined trap 11 73 | PINT USER12; // User Defined trap 12 74 | 75 | // Group 1 PIE Peripheral Vectors: 76 | PINT PDPINTA; // EV-A 77 | PINT PDPINTB; // EV-B 78 | PINT rsvd1_3; 79 | PINT XINT1; 80 | PINT XINT2; 81 | PINT ADCINT; // ADC 82 | PINT TINT0; // Timer 0 83 | PINT WAKEINT; // WD 84 | 85 | // Group 2 PIE Peripheral Vectors: 86 | PINT CMP1INT; // EV-A 87 | PINT CMP2INT; // EV-A 88 | PINT CMP3INT; // EV-A 89 | PINT T1PINT; // EV-A 90 | PINT T1CINT; // EV-A 91 | PINT T1UFINT; // EV-A 92 | PINT T1OFINT; // EV-A 93 | PINT rsvd2_8; 94 | 95 | // Group 3 PIE Peripheral Vectors: 96 | PINT T2PINT; // EV-A 97 | PINT T2CINT; // EV-A 98 | PINT T2UFINT; // EV-A 99 | PINT T2OFINT; // EV-A 100 | PINT CAPINT1; // EV-A 101 | PINT CAPINT2; // EV-A 102 | PINT CAPINT3; // EV-A 103 | PINT rsvd3_8; 104 | 105 | // Group 4 PIE Peripheral Vectors: 106 | PINT CMP4INT; // EV-B 107 | PINT CMP5INT; // EV-B 108 | PINT CMP6INT; // EV-B 109 | PINT T3PINT; // EV-B 110 | PINT T3CINT; // EV-B 111 | PINT T3UFINT; // EV-B 112 | PINT T3OFINT; // EV-B 113 | PINT rsvd4_8; 114 | 115 | // Group 5 PIE Peripheral Vectors: 116 | PINT T4PINT; // EV-B 117 | PINT T4CINT; // EV-B 118 | PINT T4UFINT; // EV-B 119 | PINT T4OFINT; // EV-B 120 | PINT CAPINT4; // EV-B 121 | PINT CAPINT5; // EV-B 122 | PINT CAPINT6; // EV-B 123 | PINT rsvd5_8; 124 | 125 | // Group 6 PIE Peripheral Vectors: 126 | PINT SPIRXINTA; // SPI-A 127 | PINT SPITXINTA; // SPI-A 128 | PINT rsvd6_3; 129 | PINT rsvd6_4; 130 | PINT MRINTA; // McBSP-A 131 | PINT MXINTA; // McBSP-A 132 | PINT rsvd6_7; 133 | PINT rsvd6_8; 134 | 135 | // Group 7 PIE Peripheral Vectors: 136 | PINT rsvd7_1; 137 | PINT rsvd7_2; 138 | PINT rsvd7_3; 139 | PINT rsvd7_4; 140 | PINT rsvd7_5; 141 | PINT rsvd7_6; 142 | PINT rsvd7_7; 143 | PINT rsvd7_8; 144 | 145 | // Group 8 PIE Peripheral Vectors: 146 | PINT rsvd8_1; 147 | PINT rsvd8_2; 148 | PINT rsvd8_3; 149 | PINT rsvd8_4; 150 | PINT rsvd8_5; 151 | PINT rsvd8_6; 152 | PINT rsvd8_7; 153 | PINT rsvd8_8; 154 | 155 | // Group 9 PIE Peripheral Vectors: 156 | PINT RXAINT; // SCI-A 157 | PINT TXAINT; // SCI-A 158 | PINT RXBINT; // SCI-B 159 | PINT TXBINT; // SCI-B 160 | PINT ECAN0INTA; // eCAN 161 | PINT ECAN1INTA; // eCAN 162 | PINT rsvd9_7; 163 | PINT rsvd9_8; 164 | 165 | // Group 10 PIE Peripheral Vectors: 166 | PINT rsvd10_1; 167 | PINT rsvd10_2; 168 | PINT rsvd10_3; 169 | PINT rsvd10_4; 170 | PINT rsvd10_5; 171 | PINT rsvd10_6; 172 | PINT rsvd10_7; 173 | PINT rsvd10_8; 174 | 175 | // Group 11 PIE Peripheral Vectors: 176 | PINT rsvd11_1; 177 | PINT rsvd11_2; 178 | PINT rsvd11_3; 179 | PINT rsvd11_4; 180 | PINT rsvd11_5; 181 | PINT rsvd11_6; 182 | PINT rsvd11_7; 183 | PINT rsvd11_8; 184 | 185 | // Group 12 PIE Peripheral Vectors: 186 | PINT rsvd12_1; 187 | PINT rsvd12_2; 188 | PINT rsvd12_3; 189 | PINT rsvd12_4; 190 | PINT rsvd12_5; 191 | PINT rsvd12_6; 192 | PINT rsvd12_7; 193 | PINT rsvd12_8; 194 | }; 195 | 196 | //--------------------------------------------------------------------------- 197 | // PIE Interrupt Vector Table External References & Function Declarations: 198 | // 199 | extern struct PIE_VECT_TABLE PieVectTable; 200 | 201 | 202 | #ifdef __cplusplus 203 | } 204 | #endif /* extern "C" */ 205 | 206 | #endif // end of DSP281x_PIE_VECT_H definition 207 | 208 | //=========================================================================== 209 | // No more. 210 | //=========================================================================== 211 | 212 | -------------------------------------------------------------------------------- /src/DSP281x_Sci.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Sci.c 4 | // 5 | // TITLE: DSP281x SCI Initialization & Support Functions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 15 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitSPI: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes the SPI(s) to a known state. 21 | // 22 | void InitSci(void) 23 | { 24 | // Initialize SCI-A: 25 | 26 | //tbd... 27 | 28 | 29 | // Initialize SCI-B: 30 | 31 | //tbd... 32 | } 33 | 34 | //=========================================================================== 35 | // No more. 36 | //=========================================================================== 37 | -------------------------------------------------------------------------------- /src/DSP281x_Sci.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Sci.h 4 | // 5 | // TITLE: DSP281x Device SCI Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Added SCIRST bit field to SCIFFTX register 13 | // | | | Renamed RXERR to RXERROR to match documentation 14 | // | | | Renamed RXOVF_CLR to RXFFOVRCLR to match user documentation 15 | //########################################################################### 16 | 17 | #ifndef DSP281x_SCI_H 18 | #define DSP281x_SCI_H 19 | 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | //--------------------------------------------------------------------------- 26 | // SCI Individual Register Bit Definitions 27 | 28 | //---------------------------------------------------------- 29 | // SCICCR communication control register bit definitions: 30 | // 31 | 32 | struct SCICCR_BITS { // bit description 33 | Uint16 SCICHAR:3; // 2:0 Character length control 34 | Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control 35 | Uint16 LOOPBKENA:1; // 4 Loop Back enable 36 | Uint16 PARITYENA:1; // 5 Parity enable 37 | Uint16 PARITY:1; // 6 Even or Odd Parity 38 | Uint16 STOPBITS:1; // 7 Number of Stop Bits 39 | Uint16 rsvd1:8; // 15:8 reserved 40 | }; 41 | 42 | 43 | union SCICCR_REG { 44 | Uint16 all; 45 | struct SCICCR_BITS bit; 46 | }; 47 | 48 | //------------------------------------------- 49 | // SCICTL1 control register 1 bit definitions: 50 | // 51 | 52 | struct SCICTL1_BITS { // bit description 53 | Uint16 RXENA:1; // 0 SCI receiver enable 54 | Uint16 TXENA:1; // 1 SCI transmitter enable 55 | Uint16 SLEEP:1; // 2 SCI sleep 56 | Uint16 TXWAKE:1; // 3 Transmitter wakeup method 57 | Uint16 rsvd:1; // 4 reserved 58 | Uint16 SWRESET:1; // 5 Software reset 59 | Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable 60 | Uint16 rsvd1:9; // 15:7 reserved 61 | 62 | }; 63 | 64 | union SCICTL1_REG { 65 | Uint16 all; 66 | struct SCICTL1_BITS bit; 67 | }; 68 | 69 | //--------------------------------------------- 70 | // SCICTL2 control register 2 bit definitions: 71 | // 72 | 73 | struct SCICTL2_BITS { // bit description 74 | Uint16 TXINTENA:1; // 0 Transmit interrupt enable 75 | Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable 76 | Uint16 rsvd:4; // 5:2 reserved 77 | Uint16 TXEMPTY:1; // 6 Transmitter empty flag 78 | Uint16 TXRDY:1; // 7 Transmitter ready flag 79 | Uint16 rsvd1:8; // 15:8 reserved 80 | 81 | }; 82 | 83 | union SCICTL2_REG { 84 | Uint16 all; 85 | struct SCICTL2_BITS bit; 86 | }; 87 | 88 | //--------------------------------------------------- 89 | // SCIRXST Receiver status register bit definitions: 90 | // 91 | 92 | struct SCIRXST_BITS { // bit description 93 | Uint16 rsvd:1; // 0 reserved 94 | Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag 95 | Uint16 PE:1; // 2 Parity error flag 96 | Uint16 OE:1; // 3 Overrun error flag 97 | Uint16 FE:1; // 4 Framing error flag 98 | Uint16 BRKDT:1; // 5 Break-detect flag 99 | Uint16 RXRDY:1; // 6 Receiver ready flag 100 | Uint16 RXERROR:1; // 7 Receiver error flag 101 | 102 | }; 103 | 104 | union SCIRXST_REG { 105 | Uint16 all; 106 | struct SCIRXST_BITS bit; 107 | }; 108 | 109 | //---------------------------------------------------- 110 | // SCIRXBUF Receiver Data Buffer with FIFO bit definitions: 111 | // 112 | 113 | struct SCIRXBUF_BITS { // bits description 114 | Uint16 RXDT:8; // 7:0 Receive word 115 | Uint16 rsvd:6; // 13:8 reserved 116 | Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode 117 | Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode 118 | }; 119 | 120 | union SCIRXBUF_REG { 121 | Uint16 all; 122 | struct SCIRXBUF_BITS bit; 123 | }; 124 | 125 | //-------------------------------------------------- 126 | // SCIPRI Priority control register bit definitions: 127 | // 128 | // 129 | 130 | struct SCIPRI_BITS { // bit description 131 | Uint16 rsvd:3; // 2:0 reserved 132 | Uint16 FREE:1; // 3 Free emulation suspend mode 133 | Uint16 SOFT:1; // 4 Soft emulation suspend mode 134 | Uint16 rsvd1:3; // 7:5 reserved 135 | }; 136 | 137 | union SCIPRI_REG { 138 | Uint16 all; 139 | struct SCIPRI_BITS bit; 140 | }; 141 | 142 | //------------------------------------------------- 143 | // SCI FIFO Transmit register bit definitions: 144 | // 145 | // 146 | 147 | struct SCIFFTX_BITS { // bit description 148 | Uint16 TXFFILIL:5; // 4:0 Interrupt level 149 | Uint16 TXFFIENA:1; // 5 Interrupt enable 150 | Uint16 TXINTCLR:1; // 6 Clear INT flag 151 | Uint16 TXFFINT:1; // 7 INT flag 152 | Uint16 TXFFST:5; // 12:8 FIFO status 153 | Uint16 TXFIFOXRESET:1; // 13 FIFO reset 154 | Uint16 SCIFFENA:1; // 14 Enhancement enable 155 | Uint16 SCIRST:1; // 15 SCI reset rx/tx channels 156 | 157 | }; 158 | 159 | union SCIFFTX_REG { 160 | Uint16 all; 161 | struct SCIFFTX_BITS bit; 162 | }; 163 | 164 | //------------------------------------------------ 165 | // SCI FIFO recieve register bit definitions: 166 | // 167 | // 168 | 169 | struct SCIFFRX_BITS { // bits description 170 | Uint16 RXFFIL:5; // 4:0 Interrupt level 171 | Uint16 RXFFIENA:1; // 5 Interrupt enable 172 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 173 | Uint16 RXFFINT:1; // 7 INT flag 174 | Uint16 RXFIFST:5; // 12:8 FIFO status 175 | Uint16 RXFIFORESET:1; // 13 FIFO reset 176 | Uint16 RXFFOVRCLR:1; // 14 Clear overflow 177 | Uint16 RXFFOVF:1; // 15 FIFO overflow 178 | 179 | }; 180 | 181 | union SCIFFRX_REG { 182 | Uint16 all; 183 | struct SCIFFRX_BITS bit; 184 | }; 185 | 186 | // SCI FIFO control register bit definitions: 187 | struct SCIFFCT_BITS { // bits description 188 | Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay 189 | Uint16 rsvd:5; // 12:8 reserved 190 | Uint16 CDC:1; // 13 Auto baud mode enable 191 | Uint16 ABDCLR:1; // 14 Auto baud clear 192 | Uint16 ABD:1; // 15 Auto baud detect 193 | }; 194 | 195 | union SCIFFCT_REG { 196 | Uint16 all; 197 | struct SCIFFCT_BITS bit; 198 | }; 199 | 200 | //--------------------------------------------------------------------------- 201 | // SCI Register File: 202 | // 203 | struct SCI_REGS { 204 | union SCICCR_REG SCICCR; // Communications control register 205 | union SCICTL1_REG SCICTL1; // Control register 1 206 | Uint16 SCIHBAUD; // Baud rate (high) register 207 | Uint16 SCILBAUD; // Baud rate (low) register 208 | union SCICTL2_REG SCICTL2; // Control register 2 209 | union SCIRXST_REG SCIRXST; // Recieve status register 210 | Uint16 SCIRXEMU; // Recieve emulation buffer register 211 | union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer 212 | Uint16 rsvd1; // reserved 213 | Uint16 SCITXBUF; // Transmit data buffer 214 | union SCIFFTX_REG SCIFFTX; // FIFO transmit register 215 | union SCIFFRX_REG SCIFFRX; // FIFO recieve register 216 | union SCIFFCT_REG SCIFFCT; // FIFO control register 217 | Uint16 rsvd2; // reserved 218 | Uint16 rsvd3; // reserved 219 | union SCIPRI_REG SCIPRI; // FIFO Priority control 220 | }; 221 | 222 | //--------------------------------------------------------------------------- 223 | // SCI External References & Function Declarations: 224 | // 225 | extern volatile struct SCI_REGS SciaRegs; 226 | extern volatile struct SCI_REGS ScibRegs; 227 | 228 | #ifdef __cplusplus 229 | } 230 | #endif /* extern "C" */ 231 | 232 | #endif // end of DSP281x_SCI_H definition 233 | 234 | //=========================================================================== 235 | // No more. 236 | //=========================================================================== 237 | -------------------------------------------------------------------------------- /src/DSP281x_Spi.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Spi.c 4 | // 5 | // TITLE: DSP281x SPI Initialization & Support Functions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 15 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitSPI: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes the SPI(s) to a known state. 21 | // 22 | void InitSpi(void) 23 | { 24 | // Initialize SPI-A: 25 | 26 | //tbd... 27 | 28 | } 29 | 30 | //=========================================================================== 31 | // No more. 32 | //=========================================================================== 33 | -------------------------------------------------------------------------------- /src/DSP281x_Spi.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Spi.h 4 | // 5 | // TITLE: DSP281x Device SPI Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Corrected SPIFFTX bit definitions. 13 | // | | | RESET renamed SPISWRESET to match documentation 14 | // | | | OVERRUN renamed OVERRUNINTENA to match documentation 15 | //########################################################################### 16 | 17 | #ifndef DSP281x_SPI_H 18 | #define DSP281x_SPI_H 19 | 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | 26 | //--------------------------------------------------------------------------- 27 | // SPI Individual Register Bit Definitions: 28 | // 29 | // SPI FIFO Transmit register bit definitions: 30 | struct SPIFFTX_BITS { // bit description 31 | Uint16 TXFFIL:5; // 4:0 Interrupt level 32 | Uint16 TXFFIENA:1; // 5 Interrupt enable 33 | Uint16 TXFFINTCLR:1; // 6 Clear INT flag 34 | Uint16 TXFFINT:1; // 7 INT flag 35 | Uint16 TXFFST:5; // 12:8 FIFO status 36 | Uint16 TXFIFO:1; // 13 FIFO reset 37 | Uint16 SPIFFENA:1; // 14 Enhancement enable 38 | Uint16 SPIRST:1; // 15 Reset SPI 39 | }; 40 | 41 | union SPIFFTX_REG { 42 | Uint16 all; 43 | struct SPIFFTX_BITS bit; 44 | }; 45 | 46 | //-------------------------------------------- 47 | // SPI FIFO recieve register bit definitions: 48 | // 49 | // 50 | struct SPIFFRX_BITS { // bits description 51 | Uint16 RXFFIL:5; // 4:0 Interrupt level 52 | Uint16 RXFFIENA:1; // 5 Interrupt enable 53 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 54 | Uint16 RXFFINT:1; // 7 INT flag 55 | Uint16 RXFFST:5; // 12:8 FIFO status 56 | Uint16 RXFIFORESET:1; // 13 FIFO reset 57 | Uint16 RXFFOVFCLR:1; // 14 Clear overflow 58 | Uint16 RXFFOVF:1; // 15 FIFO overflow 59 | 60 | }; 61 | 62 | union SPIFFRX_REG { 63 | Uint16 all; 64 | struct SPIFFRX_BITS bit; 65 | }; 66 | 67 | //-------------------------------------------- 68 | // SPI FIFO control register bit definitions: 69 | // 70 | // 71 | struct SPIFFCT_BITS { // bits description 72 | Uint16 TXDLY:8; // 7:0 FIFO transmit delay 73 | Uint16 rsvd:8; // 15:8 reserved 74 | }; 75 | 76 | union SPIFFCT_REG { 77 | Uint16 all; 78 | struct SPIFFCT_BITS bit; 79 | }; 80 | 81 | //--------------------------------------------- 82 | // SPI configuration register bit definitions: 83 | // 84 | // 85 | struct SPICCR_BITS { // bits description 86 | Uint16 SPICHAR:4; // 3:0 Character length control 87 | Uint16 SPILBK:1; // 4 Loop-back enable/disable 88 | Uint16 rsvd1:1; // 5 reserved 89 | Uint16 CLKPOLARITY:1; // 6 Clock polarity 90 | Uint16 SPISWRESET:1; // 7 SPI SW Reset 91 | Uint16 rsvd2:8; // 15:8 reserved 92 | }; 93 | 94 | union SPICCR_REG { 95 | Uint16 all; 96 | struct SPICCR_BITS bit; 97 | }; 98 | 99 | //------------------------------------------------- 100 | // SPI operation control register bit definitions: 101 | // 102 | // 103 | struct SPICTL_BITS { // bits description 104 | Uint16 SPIINTENA:1; // 0 Interrupt enable 105 | Uint16 TALK:1; // 1 Master/Slave transmit enable 106 | Uint16 MASTER_SLAVE:1; // 2 Network control mode 107 | Uint16 CLK_PHASE:1; // 3 Clock phase select 108 | Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable 109 | Uint16 rsvd:11; // 15:5 reserved 110 | }; 111 | 112 | union SPICTL_REG { 113 | Uint16 all; 114 | struct SPICTL_BITS bit; 115 | }; 116 | 117 | //-------------------------------------- 118 | // SPI status register bit definitions: 119 | // 120 | // 121 | struct SPISTS_BITS { // bits description 122 | Uint16 rsvd1:5; // 4:0 reserved 123 | Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag 124 | Uint16 INT_FLAG:1; // 6 SPI interrupt flag 125 | Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag 126 | Uint16 rsvd2:8; // 15:8 reserved 127 | }; 128 | 129 | union SPISTS_REG { 130 | Uint16 all; 131 | struct SPISTS_BITS bit; 132 | }; 133 | 134 | //------------------------------------------------ 135 | // SPI priority control register bit definitions: 136 | // 137 | // 138 | struct SPIPRI_BITS { // bits description 139 | Uint16 rsvd1:4; // 3:0 reserved 140 | Uint16 FREE:1; // 4 Free emulation mode control 141 | Uint16 SOFT:1; // 5 Soft emulation mode control 142 | Uint16 PRIORITY:1; // 6 Interrupt priority select 143 | Uint16 rsvd2:9; // 15:7 reserved 144 | }; 145 | 146 | union SPIPRI_REG { 147 | Uint16 all; 148 | struct SPIPRI_BITS bit; 149 | }; 150 | 151 | //--------------------------------------------------------------------------- 152 | // SPI Register File: 153 | // 154 | struct SPI_REGS { 155 | union SPICCR_REG SPICCR; // Configuration register 156 | union SPICTL_REG SPICTL; // Operation control register 157 | union SPISTS_REG SPISTS; // Status register 158 | Uint16 rsvd1; // reserved 159 | Uint16 SPIBRR; // Baud Rate 160 | Uint16 rsvd2; // reserved 161 | Uint16 SPIRXEMU; // Emulation buffer 162 | Uint16 SPIRXBUF; // Serial input buffer 163 | Uint16 SPITXBUF; // Serial output buffer 164 | Uint16 SPIDAT; // Serial data 165 | union SPIFFTX_REG SPIFFTX; // FIFO transmit register 166 | union SPIFFRX_REG SPIFFRX; // FIFO recieve register 167 | union SPIFFCT_REG SPIFFCT; // FIFO control register 168 | Uint16 rsvd3[2]; // reserved 169 | union SPIPRI_REG SPIPRI; // FIFO Priority control 170 | }; 171 | 172 | //--------------------------------------------------------------------------- 173 | // SPI External References & Function Declarations: 174 | // 175 | extern volatile struct SPI_REGS SpiaRegs; 176 | 177 | 178 | #ifdef __cplusplus 179 | } 180 | #endif /* extern "C" */ 181 | 182 | #endif // end of DSP281x_SPI_H definition 183 | 184 | //=========================================================================== 185 | // No more. 186 | //=========================================================================== 187 | -------------------------------------------------------------------------------- /src/DSP281x_SysCtrl.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_SysCtrl.c 4 | // 5 | // TITLE: DSP281x Device System Control Initialization & Support Functions. 6 | // 7 | // DESCRIPTION: 8 | // 9 | // Example initialization of system resources. 10 | // 11 | //########################################################################### 12 | // 13 | // Ver | dd mmm yyyy | Who | Description of changes 14 | // =====|=============|======|=============================================== 15 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 16 | // | | | Additional comments added to explain the PLL 17 | // | | | initialization. 18 | // | | | Changed the PLL initialization to take into 19 | // | | | account bit definitions for the PLLCR register 20 | // | | | Removed DFT initialization - no longer needed 21 | // | | | as of Rev C F2810/12 silicon 22 | // | | | Split some operations into their own function 23 | // | | | for better modularity 24 | // | | | Added pipeline flush after the Flash Init 25 | //########################################################################### 26 | 27 | 28 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 29 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 30 | 31 | // Functions that will be run from RAM need to be assigned to 32 | // a different section. This section will then be mapped to a load and 33 | // run address using the linker cmd file. 34 | 35 | #pragma CODE_SECTION(InitFlash, "ramfuncs"); 36 | 37 | //--------------------------------------------------------------------------- 38 | // InitSysCtrl: 39 | //--------------------------------------------------------------------------- 40 | // This function initializes the System Control registers to a known state. 41 | // - Disables the watchdog 42 | // - Set the PLLCR for proper SYSCLKOUT frequency 43 | // - Set the pre-scaler for the high and low frequency peripheral clocks 44 | // - Enable the clocks to the peripherals 45 | 46 | void InitSysCtrl(void) 47 | { 48 | 49 | // On F2812/F2810 TMX samples prior to rev C this initialization was 50 | // required. For Rev C and after this is no longer required 51 | /* 52 | EALLOW; 53 | DevEmuRegs.M0RAMDFT = 0x0300; 54 | DevEmuRegs.M1RAMDFT = 0x0300; 55 | DevEmuRegs.L0RAMDFT = 0x0300; 56 | DevEmuRegs.L1RAMDFT = 0x0300; 57 | DevEmuRegs.H0RAMDFT = 0x0300; 58 | EDIS; 59 | */ 60 | // Disable the watchdog 61 | DisableDog(); 62 | 63 | // Initialize the PLLCR to 0xA 64 | InitPll(0xA); 65 | 66 | // Initialize the peripheral clocks 67 | InitPeripheralClocks(); 68 | } 69 | 70 | 71 | //--------------------------------------------------------------------------- 72 | // Example: InitFlash: 73 | //--------------------------------------------------------------------------- 74 | // This function initializes the Flash Control registers 75 | 76 | // CAUTION 77 | // This function MUST be executed out of RAM. Executing it 78 | // out of OTP/Flash will yield unpredictable results 79 | 80 | void InitFlash(void) 81 | { 82 | EALLOW; 83 | //Enable Flash Pipeline mode to improve performance 84 | //of code executed from Flash. 85 | FlashRegs.FOPT.bit.ENPIPE = 1; 86 | 87 | // CAUTION 88 | //Minimum waitstates required for the flash operating 89 | //at a given CPU rate must be characterized by TI. 90 | //Refer to the datasheet for the latest information. 91 | 92 | //Set the Random Waitstate for the Flash 93 | FlashRegs.FBANKWAIT.bit.RANDWAIT = 5; 94 | 95 | //Set the Paged Waitstate for the Flash 96 | FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5; 97 | 98 | // CAUTION 99 | //Minimum cycles required to move between power states 100 | //at a given CPU rate must be characterized by TI. 101 | //Refer to the datasheet for the latest information. 102 | 103 | //For now use the default count 104 | //Set number of cycles to transition from sleep to standby 105 | FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; 106 | 107 | //Set number of cycles to transition from standby to active 108 | FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; 109 | EDIS; 110 | 111 | //Force a pipeline flush to ensure that the write to 112 | //the last register configured occurs before returning. 113 | 114 | asm(" RPT #7 || NOP"); 115 | } 116 | 117 | 118 | //--------------------------------------------------------------------------- 119 | // Example: KickDog: 120 | //--------------------------------------------------------------------------- 121 | // This function resets the watchdog timer. 122 | // Enable this function for using KickDog in the application 123 | 124 | void KickDog(void) 125 | { 126 | EALLOW; 127 | SysCtrlRegs.WDKEY = 0x0055; 128 | SysCtrlRegs.WDKEY = 0x00AA; 129 | EDIS; 130 | } 131 | 132 | //--------------------------------------------------------------------------- 133 | // Example: DisableDog: 134 | //--------------------------------------------------------------------------- 135 | // This function disables the watchdog timer. 136 | 137 | void DisableDog(void) 138 | { 139 | EALLOW; 140 | SysCtrlRegs.WDCR= 0x0068; 141 | EDIS; 142 | } 143 | 144 | //--------------------------------------------------------------------------- 145 | // Example: InitPll: 146 | //--------------------------------------------------------------------------- 147 | // This function initializes the PLLCR register. 148 | 149 | void InitPll(Uint16 val) 150 | { 151 | volatile Uint16 iVol; 152 | 153 | if (SysCtrlRegs.PLLCR.bit.DIV != val) 154 | { 155 | 156 | EALLOW; 157 | SysCtrlRegs.PLLCR.bit.DIV = val; 158 | EDIS; 159 | 160 | // Optional: Wait for PLL to lock. 161 | // During this time the CPU will switch to OSCCLK/2 until the PLL is 162 | // stable. Once the PLL is stable the CPU will switch to the new PLL value. 163 | // 164 | // This switch time is 131072 CLKIN cycles as of Rev C silicon. 165 | // 166 | // Code is not required to sit and wait for the PLL to lock. 167 | // However, if the code does anything that is timing critical, 168 | // and requires the correct clock be locked, then it is best to 169 | // wait until this switching has completed. 170 | 171 | // If this function is run from waitstated memory, then the loop count can 172 | // be reduced as long as the minimum switch time is still met. 173 | 174 | // iVol is volatile so the compiler will not optimize this loop out 175 | // 176 | // The watchdog should be disabled before this loop, or fed within 177 | // the loop. 178 | 179 | DisableDog(); 180 | 181 | // Wait lock cycles. 182 | // Note, This loop is tuned to 0-waitstate RAM memory. If this 183 | // function is run from wait-stated memory such as Flash or XINTF, 184 | // then the number of times through the loop can be reduced 185 | // accordingly. 186 | for(iVol= 0; iVol< ( (131072/2)/12 ); iVol++) 187 | { 188 | 189 | } 190 | } 191 | } 192 | 193 | //-------------------------------------------------------------------------- 194 | // Example: InitPeripheralClocks: 195 | //--------------------------------------------------------------------------- 196 | // This function initializes the clocks to the peripheral modules. 197 | // First the high and low clock prescalers are set 198 | // Second the clocks are enabled to each peripheral. 199 | // To reduce power, leave clocks to unused peripherals disabled 200 | // Note: If a peripherals clock is not enabled then you cannot 201 | // read or write to the registers for that peripheral 202 | 203 | void InitPeripheralClocks(void) 204 | { 205 | EALLOW; 206 | // HISPCP/LOSPCP prescale register settings, normally it will be set to default values 207 | SysCtrlRegs.HISPCP.all = 0x0001; 208 | SysCtrlRegs.LOSPCP.all = 0x0002; 209 | 210 | // Peripheral clock enables set for the selected peripherals. 211 | SysCtrlRegs.PCLKCR.bit.EVAENCLK=1; 212 | SysCtrlRegs.PCLKCR.bit.EVBENCLK=1; 213 | SysCtrlRegs.PCLKCR.bit.SCIAENCLK=1; 214 | SysCtrlRegs.PCLKCR.bit.SCIBENCLK=1; 215 | SysCtrlRegs.PCLKCR.bit.MCBSPENCLK=1; 216 | SysCtrlRegs.PCLKCR.bit.SPIENCLK=1; 217 | SysCtrlRegs.PCLKCR.bit.ECANENCLK=1; 218 | SysCtrlRegs.PCLKCR.bit.ADCENCLK=1; 219 | EDIS; 220 | } 221 | 222 | 223 | //=========================================================================== 224 | // No more. 225 | //=========================================================================== 226 | -------------------------------------------------------------------------------- /src/DSP281x_XIntrupt.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_XIntrupt.c 4 | // 5 | // TITLE: DSP28 External Interrupt Initialization & Support Functions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 15 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitXIntrupt: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes external interrupts to a known state. 21 | // 22 | void InitXIntrupt(void) 23 | { 24 | 25 | } 26 | 27 | //=========================================================================== 28 | // No more. 29 | //=========================================================================== 30 | -------------------------------------------------------------------------------- /src/DSP281x_XIntrupt.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_XIntrupt.h 4 | // 5 | // TITLE: DSP281x Device External Interrupt Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | #ifndef DSP281x_XINTRUPT_H 15 | #define DSP281x_XINTRUPT_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //--------------------------------------------------------------------------- 23 | 24 | struct XINTCR_BITS { 25 | Uint16 ENABLE:1; // 0 enable/disable 26 | Uint16 rsvd1:1; // 1 reserved 27 | Uint16 POLARITY:1; // 2 pos/neg triggered 28 | Uint16 rsvd2:12; // 15:3 reserved 29 | }; 30 | 31 | union XINTCR_REG { 32 | Uint16 all; 33 | struct XINTCR_BITS bit; 34 | }; 35 | 36 | struct XNMICR_BITS { 37 | Uint16 ENABLE:1; // 0 enable/disable 38 | Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to INT13 39 | Uint16 POLARITY:1; // 2 pos/neg triggered 40 | Uint16 rsvd2:12; // 15:3 reserved 41 | }; 42 | 43 | union XNMICR_REG { 44 | Uint16 all; 45 | struct XNMICR_BITS bit; 46 | }; 47 | 48 | 49 | 50 | 51 | //--------------------------------------------------------------------------- 52 | // External Interrupt Register File: 53 | // 54 | struct XINTRUPT_REGS { 55 | union XINTCR_REG XINT1CR; 56 | union XINTCR_REG XINT2CR; 57 | Uint16 rsvd1[5]; 58 | union XNMICR_REG XNMICR; 59 | Uint16 XINT1CTR; 60 | Uint16 XINT2CTR; 61 | Uint16 rsvd[5]; 62 | Uint16 XNMICTR; 63 | }; 64 | 65 | //--------------------------------------------------------------------------- 66 | // External Interrupt References & Function Declarations: 67 | // 68 | extern volatile struct XINTRUPT_REGS XIntruptRegs; 69 | 70 | #ifdef __cplusplus 71 | } 72 | #endif /* extern "C" */ 73 | 74 | #endif // end of DSP281x_XINTF_H definition 75 | 76 | //=========================================================================== 77 | // No more. 78 | //=========================================================================== 79 | -------------------------------------------------------------------------------- /src/DSP281x_Xintf.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Xintf.c 4 | // 5 | // TITLE: DSP281x Device External Interface Init & Support Functions. 6 | // 7 | // DESCRIPTION: 8 | // 9 | // Example initialization function for the external interface (XINTF). 10 | // This example configures the XINTF to its default state. For an 11 | // example of how this function can be modified to configure the XINTF 12 | // for use with the F2812 eZdsp, refer to the examples/run_from_xintf 13 | // project. 14 | // 15 | //########################################################################### 16 | // 17 | // Ver | dd mmm yyyy | Who | Description of changes 18 | // =====|=============|======|=============================================== 19 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 20 | // | | | Added pipeline flush after the XINTF Init 21 | //########################################################################### 22 | 23 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 24 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 25 | 26 | //--------------------------------------------------------------------------- 27 | // InitXINTF: 28 | //--------------------------------------------------------------------------- 29 | // This function initializes the External Interface the default reset state. 30 | // 31 | // Do not modify the timings of the XINTF while running from the XINTF. Doing 32 | // so can yield unpredictable results 33 | 34 | 35 | void InitXintf(void) 36 | { 37 | 38 | #if F2812 39 | 40 | // This shows how to write to the XINTF registers. The 41 | // values used here are the default state after reset. 42 | // Different hardware will require a different configuration. 43 | 44 | // For an example of an XINTF configuration used with the 45 | // F2812 eZdsp, refer to the examples/run_from_xintf project. 46 | 47 | // Any changes to XINTF timing should only be made by code 48 | // running outside of the XINTF. 49 | 50 | // All Zones--------------------------------- 51 | // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT 52 | XintfRegs.XINTCNF2.bit.XTIMCLK = 1; 53 | // No write buffering 54 | XintfRegs.XINTCNF2.bit.WRBUFF = 0; 55 | // XCLKOUT is enabled 56 | XintfRegs.XINTCNF2.bit.CLKOFF = 0; 57 | // XCLKOUT = XTIMCLK/2 58 | XintfRegs.XINTCNF2.bit.CLKMODE = 1; 59 | 60 | 61 | // Zone 0------------------------------------ 62 | // When using ready, ACTIVE must be 1 or greater 63 | // Lead must always be 1 or greater 64 | // Zone write timing 65 | XintfRegs.XTIMING0.bit.XWRLEAD = 3; 66 | XintfRegs.XTIMING0.bit.XWRACTIVE = 7; 67 | XintfRegs.XTIMING0.bit.XWRTRAIL = 3; 68 | // Zone read timing 69 | XintfRegs.XTIMING0.bit.XRDLEAD = 3; 70 | XintfRegs.XTIMING0.bit.XRDACTIVE = 7; 71 | XintfRegs.XTIMING0.bit.XRDTRAIL = 3; 72 | 73 | // double all Zone read/write lead/active/trail timing 74 | XintfRegs.XTIMING0.bit.X2TIMING = 1; 75 | 76 | // Zone will sample XREADY signal 77 | XintfRegs.XTIMING0.bit.USEREADY = 1; 78 | XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous 79 | 80 | // Size must be 1,1 - other values are reserved 81 | XintfRegs.XTIMING0.bit.XSIZE = 3; 82 | 83 | // Zone 1------------------------------------ 84 | // When using ready, ACTIVE must be 1 or greater 85 | // Lead must always be 1 or greater 86 | // Zone write timing 87 | XintfRegs.XTIMING1.bit.XWRLEAD = 3; 88 | XintfRegs.XTIMING1.bit.XWRACTIVE = 7; 89 | XintfRegs.XTIMING1.bit.XWRTRAIL = 3; 90 | // Zone read timing 91 | XintfRegs.XTIMING1.bit.XRDLEAD = 3; 92 | XintfRegs.XTIMING1.bit.XRDACTIVE = 7; 93 | XintfRegs.XTIMING1.bit.XRDTRAIL = 3; 94 | 95 | // double all Zone read/write lead/active/trail timing 96 | XintfRegs.XTIMING1.bit.X2TIMING = 1; 97 | 98 | // Zone will sample XREADY signal 99 | XintfRegs.XTIMING1.bit.USEREADY = 1; 100 | XintfRegs.XTIMING1.bit.READYMODE = 1; // sample asynchronous 101 | 102 | // Size must be 1,1 - other values are reserved 103 | XintfRegs.XTIMING1.bit.XSIZE = 3; 104 | 105 | // Zone 2------------------------------------ 106 | // When using ready, ACTIVE must be 1 or greater 107 | // Lead must always be 1 or greater 108 | // Zone write timing 109 | XintfRegs.XTIMING2.bit.XWRLEAD = 3; 110 | XintfRegs.XTIMING2.bit.XWRACTIVE = 7; 111 | XintfRegs.XTIMING2.bit.XWRTRAIL = 3; 112 | // Zone read timing 113 | XintfRegs.XTIMING2.bit.XRDLEAD = 3; 114 | XintfRegs.XTIMING2.bit.XRDACTIVE = 7; 115 | XintfRegs.XTIMING2.bit.XRDTRAIL = 3; 116 | 117 | // double all Zone read/write lead/active/trail timing 118 | XintfRegs.XTIMING2.bit.X2TIMING = 1; 119 | 120 | // Zone will sample XREADY signal 121 | XintfRegs.XTIMING2.bit.USEREADY = 1; 122 | XintfRegs.XTIMING2.bit.READYMODE = 1; // sample asynchronous 123 | 124 | // Size must be 1,1 - other values are reserved 125 | XintfRegs.XTIMING2.bit.XSIZE = 3; 126 | 127 | 128 | // Zone 6------------------------------------ 129 | // When using ready, ACTIVE must be 1 or greater 130 | // Lead must always be 1 or greater 131 | // Zone write timing 132 | XintfRegs.XTIMING6.bit.XWRLEAD = 3; 133 | XintfRegs.XTIMING6.bit.XWRACTIVE = 7; 134 | XintfRegs.XTIMING6.bit.XWRTRAIL = 3; 135 | // Zone read timing 136 | XintfRegs.XTIMING6.bit.XRDLEAD = 3; 137 | XintfRegs.XTIMING6.bit.XRDACTIVE = 7; 138 | XintfRegs.XTIMING6.bit.XRDTRAIL = 3; 139 | 140 | // double all Zone read/write lead/active/trail timing 141 | XintfRegs.XTIMING6.bit.X2TIMING = 1; 142 | 143 | // Zone will sample XREADY signal 144 | XintfRegs.XTIMING6.bit.USEREADY = 1; 145 | XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous 146 | 147 | // Size must be 1,1 - other values are reserved 148 | XintfRegs.XTIMING6.bit.XSIZE = 3; 149 | 150 | 151 | // Zone 7------------------------------------ 152 | // When using ready, ACTIVE must be 1 or greater 153 | // Lead must always be 1 or greater 154 | // Zone write timing 155 | XintfRegs.XTIMING7.bit.XWRLEAD = 3; 156 | XintfRegs.XTIMING7.bit.XWRACTIVE = 7; 157 | XintfRegs.XTIMING7.bit.XWRTRAIL = 3; 158 | // Zone read timing 159 | XintfRegs.XTIMING7.bit.XRDLEAD = 3; 160 | XintfRegs.XTIMING7.bit.XRDACTIVE = 7; 161 | XintfRegs.XTIMING7.bit.XRDTRAIL = 3; 162 | 163 | // double all Zone read/write lead/active/trail timing 164 | XintfRegs.XTIMING7.bit.X2TIMING = 1; 165 | 166 | // Zone will sample XREADY signal 167 | XintfRegs.XTIMING7.bit.USEREADY = 1; 168 | XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous 169 | 170 | // Size must be 1,1 - other values are reserved 171 | XintfRegs.XTIMING7.bit.XSIZE = 3; 172 | 173 | // Bank switching 174 | // Assume Zone 7 is slow, so add additional BCYC cycles 175 | // when ever switching from Zone 7 to another Zone. 176 | // This will help avoid bus contention. 177 | XintfRegs.XBANK.bit.BANK = 7; 178 | XintfRegs.XBANK.bit.BCYC = 7; 179 | 180 | //Force a pipeline flush to ensure that the write to 181 | //the last register configured occurs before returning. 182 | 183 | asm(" RPT #7 || NOP"); 184 | 185 | #endif 186 | } 187 | 188 | //=========================================================================== 189 | // No more. 190 | //=========================================================================== 191 | -------------------------------------------------------------------------------- /src/DSP281x_Xintf.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Xintf.h 4 | // 5 | // TITLE: DSP281x Device External Interface Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | #ifndef DSP281x_XINTF_H 15 | #define DSP281x_XINTF_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | // XINTF timing register bit definitions: 24 | struct XTIMING_BITS { // bits description 25 | Uint16 XWRTRAIL:2; // 1:0 Write access trail timing 26 | Uint16 XWRACTIVE:3; // 4:2 Write access active timing 27 | Uint16 XWRLEAD:2; // 6:5 Write access lead timing 28 | Uint16 XRDTRAIL:2; // 8:7 Read access trail timing 29 | Uint16 XRDACTIVE:3; // 11:9 Read access active timing 30 | Uint16 XRDLEAD:2; // 13:12 Read access lead timing 31 | Uint16 USEREADY:1; // 14 Extend access using HW waitstates 32 | Uint16 READYMODE:1; // 15 Ready mode 33 | Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b 34 | Uint16 rsvd1:4; // 21:18 reserved 35 | Uint16 X2TIMING:1; // 22 Double lead/active/trail timing 36 | Uint16 rsvd3:9; // 31:23 reserved 37 | }; 38 | 39 | union XTIMING_REG { 40 | Uint32 all; 41 | struct XTIMING_BITS bit; 42 | }; 43 | 44 | // XINTF control register bit definitions: 45 | struct XINTCNF2_BITS { // bits description 46 | Uint16 WRBUFF:2; // 1:0 Write buffer depth 47 | Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK 48 | Uint16 CLKOFF:1; // 3 Disable XCLKOUT 49 | Uint16 rsvd1:2; // 5:4 reserved 50 | Uint16 WLEVEL:2; // 7:6 Current level of the write buffer 51 | Uint16 MPNMC:1; // 8 Micro-processor/micro-computer mode 52 | Uint16 HOLD:1; // 9 Hold enable/disable 53 | Uint16 HOLDS:1; // 10 Current state of HOLDn input 54 | Uint16 HOLDAS:1; // 11 Current state of HOLDAn output 55 | Uint16 rsvd2:4; // 15:12 reserved 56 | Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK 57 | Uint16 rsvd3:13; // 31:19 reserved 58 | }; 59 | 60 | union XINTCNF2_REG { 61 | Uint32 all; 62 | struct XINTCNF2_BITS bit; 63 | }; 64 | 65 | // XINTF bank switching register bit definitions: 66 | struct XBANK_BITS { // bits description 67 | Uint16 BANK:2; // 2:0 Zone for which banking is enabled 68 | Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add 69 | Uint16 rsvd:10; // 15:6 reserved 70 | }; 71 | 72 | union XBANK_REG { 73 | Uint16 all; 74 | struct XBANK_BITS bit; 75 | }; 76 | 77 | 78 | //--------------------------------------------------------------------------- 79 | // XINTF Register File: 80 | // 81 | struct XINTF_REGS { 82 | union XTIMING_REG XTIMING0; 83 | union XTIMING_REG XTIMING1; 84 | union XTIMING_REG XTIMING2; 85 | Uint32 rsvd1[3]; 86 | union XTIMING_REG XTIMING6; 87 | union XTIMING_REG XTIMING7; 88 | Uint32 rsvd2[2]; 89 | union XINTCNF2_REG XINTCNF2; 90 | Uint32 rsvd3; 91 | union XBANK_REG XBANK; 92 | Uint16 rsvd4; 93 | Uint16 XREVISION; 94 | Uint16 rsvd5[5]; 95 | }; 96 | 97 | //--------------------------------------------------------------------------- 98 | // XINTF External References & Function Declarations: 99 | // 100 | extern volatile struct XINTF_REGS XintfRegs; 101 | 102 | 103 | #ifdef __cplusplus 104 | } 105 | #endif /* extern "C" */ 106 | 107 | #endif // end of DSP281x_XINTF_H definition 108 | 109 | //=========================================================================== 110 | // No more. 111 | //=========================================================================== 112 | -------------------------------------------------------------------------------- /src/DSP281x_XintfBootReset.asm: -------------------------------------------------------------------------------- 1 | ;//########################################################################### 2 | ;// 3 | ;// FILE: DSP281x_XintfBootReset.asm 4 | ;// 5 | ;// TITLE: Boot from XINTF Zone 7 6 | ;// 7 | ;// DESCRIPTION: 8 | ;// 9 | ;// This file includes the required setup for booting from XINTF Zone 7. 10 | ;// 11 | ;// The reset vector located at 0x3FFFC0 is set to either the watchdog 12 | ;// disable function or the entry point to the C routine. 13 | ;// 14 | ;// Use the linker file F2812_XintfBoot.cmd to properly map the reset vector. 15 | ;// 16 | ;// This file assumes the device is set to "boot from XINTF zone 7" and the 17 | ;// MP/MC pin is pulled high. 18 | ;// 19 | ;//########################################################################### 20 | ;// 21 | ;// Based on source from D.A. 22 | ;// 23 | ;// Ver | dd mmm yyyy | Who | Description of changes 24 | ;// =====|=============|======|=============================================== 25 | ;// 1.00| 11 Sep 03 | L.H. | First release 26 | ;//########################################################################### 27 | 28 | WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 29 | 30 | .ref _c_int00 31 | 32 | *********************************************************************** 33 | * Function: Reset vector for XINTF boot 34 | * 35 | *********************************************************************** 36 | 37 | .sect "reset_vec" 38 | 39 | reset_vec: 40 | .if WD_DISABLE == 1 41 | .long wd_disable ;Point reset to watchdog disable code 42 | .else 43 | .long _c_int00 ;Point reset to start of boot.asm in RTS library 44 | .endif 45 | 46 | ;end codestart section 47 | 48 | 49 | *********************************************************************** 50 | * Function: wd_disable 51 | * 52 | * Description: Disables the watchdog timer 53 | *********************************************************************** 54 | .if WD_DISABLE == 1 55 | 56 | .text 57 | wd_disable: 58 | SETC OBJMODE ;Set 28x OBJECTMODE 59 | EALLOW ;Enable EALLOW protected register access 60 | MOVZ DP, #7029h>>6 ;Set data page for WDCR register 61 | MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD 62 | EDIS ;Disable EALLOW protected register access 63 | LB _c_int00 ;Branch to start of boot.asm in RTS library 64 | 65 | .endif 66 | 67 | ;end wd_disable 68 | 69 | 70 | 71 | .end 72 | 73 | ; end of file XintfBootReset.asm -------------------------------------------------------------------------------- /src/DSP281x_usDelay.asm: -------------------------------------------------------------------------------- 1 | ;//########################################################################### 2 | ;// 3 | ;// FILE: DSP281x_usDelay.asm 4 | ;// 5 | ;// TITLE: Simple delay function 6 | ;// 7 | ;// DESCRIPTION: 8 | ;// 9 | ;// This is a simple delay function that can be used to insert a specified 10 | ;// delay into code. 11 | ;// 12 | ;// This function is only accurate if executed from internal zero-waitstate 13 | ;// SARAM. If it is executed from waitstate memory then the delay will be 14 | ;// longer then specified. 15 | ;// 16 | ;// To use this function: 17 | ;// 18 | ;// 1 - update the CPU clock speed in the DSP281x_Examples.h 19 | ;// file. For example: 20 | ;// #define CPU_CLOCK_SPEED 6.6667L // for a 150MHz CPU clock speed 21 | ;// 22 | ;// 2 - Call this function by using the DELAY_US(A) macro 23 | ;// that is defined in the DSP28_Device.h file. This macro 24 | ;// will convert the number of microseconds specified 25 | ;// into a loop count for use with this function. 26 | ;// This count will be based on the CPU frequency you specify. 27 | ;// 28 | ;// 3 - For the most accurate delay 29 | ;// - Execute this function in 0 waitstate RAM. 30 | ;// - Disable interrupts before calling the function 31 | ;// If you do not disable interrupts, then think of 32 | ;// this as an "at least" delay function as the actual 33 | ;// delay may be longer. 34 | ;// 35 | ;// The C assembly call from the DELAY_US(time) macro will 36 | ;// look as follows: 37 | ;// 38 | ;// extern void Delay(long LoopCount); 39 | ;// 40 | ;// MOV AL,#LowLoopCount 41 | ;// MOV AH,#HighLoopCount 42 | ;// LCR _Delay 43 | ;// 44 | ;// Or as follows (if count is less then 16-bits): 45 | ;// 46 | ;// MOV ACC,#LoopCount 47 | ;// LCR _Delay 48 | ;// 49 | ;// 50 | ;//########################################################################### 51 | ;// 52 | ;// Ver | dd mmm yyyy | Who | Description of changes 53 | ;// =====|=============|======|=============================================== 54 | ;// 1.00| 11 Sep 2003 | L.H. | No changes since v.58 55 | ;//########################################################################### 56 | 57 | .def _DSP28x_usDelay 58 | .sect "ramfuncs" 59 | 60 | .global __DSP28x_usDelay 61 | _DSP28x_usDelay: 62 | SUB ACC,#1 63 | BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 64 | LRETR 65 | 66 | ;There is a 9/10 cycle overhead and each loop 67 | ;takes five cycles. The LoopCount is given by 68 | ;the following formula: 69 | ; DELAY_CPU_CYCLES = 9 + 5*LoopCount 70 | ; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 71 | ; The macro DELAY_US(A) performs this calculation for you 72 | ;================================================== 73 | -------------------------------------------------------------------------------- /src/DSP28_Adc.h: -------------------------------------------------------------------------------- 1 | // 2 | // TMDX ALPHA RELEASE 3 | // Intended for product evaluation purposes 4 | // 5 | //########################################################################### 6 | // 7 | // FILE: DSP28_Adc.h 8 | // 9 | // TITLE: DSP28 Device ADC Register Definitions. 10 | // 11 | //########################################################################### 12 | // 13 | // Ver | dd mmm yyyy | Who | Description of changes 14 | // =====|=============|======|=============================================== 15 | // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release 16 | // 0.56| 20 May 2002 | L.H. | No change 17 | // 0.57| 27 May 2002 | L.H. | No change 18 | //########################################################################### 19 | 20 | #ifndef DSP28_ADC_H 21 | #define DSP28_ADC_H 22 | 23 | //--------------------------------------------------------------------------- 24 | // ADC Individual Register Bit Definitions: 25 | 26 | struct ADCTRL1_BITS { // bits description 27 | Uint16 rsvd1:4; // 3:0 reserved 28 | Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode 29 | Uint16 rsvd2:1; // 5 reserved 30 | Uint16 CONT_RUN:1; // 6 Continuous run 31 | Uint16 CPS:1; // 7 ADC core clock prescaler 32 | Uint16 ACQ_PS:4; // 11:8 Acquisition window size 33 | Uint16 SUSMOD:2; // 13:12 Emulation suspend mode 34 | Uint16 RESET:1; // 14 ADC reset 35 | Uint16 rsvd3:1; // 15 reserved 36 | }; 37 | 38 | 39 | union ADCTRL1_REG { 40 | Uint16 all; 41 | struct ADCTRL1_BITS bit; 42 | }; 43 | 44 | 45 | struct ADCTRL2_BITS { // bits description 46 | Uint16 EVB_SOC_SEQ2:1; // 0 Event manager B SOC mask for SEQ2 47 | Uint16 rsvd1:1; // 1 reserved 48 | Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode 49 | Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable 50 | Uint16 rsvd2:1; // 4 reserved 51 | Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 52 | Uint16 RST_SEQ2:1; // 6 Reset SEQ2 53 | Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 54 | Uint16 EVA_SOC_SEQ1:1; // 8 Event manager A SOC mask for SEQ1 55 | Uint16 rsvd3:1; // 9 reserved 56 | Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode 57 | Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable 58 | Uint16 rsvd4:1; // 12 reserved 59 | Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 60 | Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 61 | Uint16 EVB_SOC_SEQ:1; // 15 EVB SOC enable 62 | }; 63 | 64 | 65 | union ADCTRL2_REG { 66 | Uint16 all; 67 | struct ADCTRL2_BITS bit; 68 | }; 69 | 70 | 71 | struct AUTO_SEQ_SR_BITS { // bits description 72 | Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state 73 | Uint16 SEQ2_STATE:3; // 6:2 SEQ2 state 74 | Uint16 rsvd1:1; // 7 resverved 75 | Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status 76 | Uint16 rsvd2:4; // 15:12 reserved 77 | }; 78 | 79 | union AUTO_SEQ_SR_REG { 80 | Uint16 all; 81 | struct AUTO_SEQ_SR_BITS bit; 82 | }; 83 | 84 | 85 | struct MAX_CONV_BITS { 86 | Uint16 MAX_CONV:7; // 6:0 Max number of conversions 87 | Uint16 rsvd1:9; // 15:7 reserved 88 | }; 89 | 90 | union MAX_CONV_REG { 91 | Uint16 all; 92 | struct MAX_CONV_BITS bit; 93 | }; 94 | 95 | 96 | struct CHSELSEQ1_BITS { 97 | Uint16 CONV00:4; 98 | Uint16 CONV01:4; 99 | Uint16 CONV02:4; 100 | Uint16 CONV03:4; 101 | }; 102 | 103 | union CHSELSEQ1_REG{ 104 | Uint16 all; 105 | struct CHSELSEQ1_BITS bit; 106 | }; 107 | 108 | struct CHSELSEQ2_BITS { 109 | Uint16 CONV04:4; 110 | Uint16 CONV05:4; 111 | Uint16 CONV06:4; 112 | Uint16 CONV07:4; 113 | }; 114 | 115 | union CHSELSEQ2_REG{ 116 | Uint16 all; 117 | struct CHSELSEQ2_BITS bit; 118 | }; 119 | 120 | struct CHSELSEQ3_BITS { 121 | Uint16 CONV08:4; 122 | Uint16 CONV09:4; 123 | Uint16 CONV10:4; 124 | Uint16 CONV11:4; 125 | }; 126 | 127 | union CHSELSEQ3_REG{ 128 | Uint16 all; 129 | struct CHSELSEQ3_BITS bit; 130 | }; 131 | 132 | struct CHSELSEQ4_BITS { 133 | Uint16 CONV12:4; 134 | Uint16 CONV13:4; 135 | Uint16 CONV14:4; 136 | Uint16 CONV15:4; 137 | }; 138 | 139 | union CHSELSEQ4_REG { 140 | Uint16 all; 141 | struct CHSELSEQ4_BITS bit; 142 | }; 143 | 144 | struct ADCTRL3_BITS { 145 | Uint16 SMODE_SEL:1; // 0 Sampling mode select 146 | Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider 147 | Uint16 ADCPWDN:1; // 5 ADC powerdown 148 | Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down 149 | Uint16 rsvd1:8; // 15:8 reserved 150 | }; 151 | 152 | union ADCTRL3_REG { 153 | Uint16 all; 154 | struct ADCTRL3_BITS bit; 155 | }; 156 | 157 | 158 | struct ADC_ST_FLG_BITS { 159 | Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag 160 | Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag 161 | Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status 162 | Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status 163 | Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear 164 | Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear 165 | Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 166 | Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 167 | Uint16 rsvd1:8; // 15:8 168 | }; 169 | 170 | 171 | union ADC_ST_FLG_REG { 172 | Uint16 all; 173 | struct ADC_ST_FLG_BITS bit; 174 | }; 175 | 176 | 177 | struct ADC_REGS { 178 | union ADCTRL1_REG ADCTRL1; // ADC Control 1 179 | union ADCTRL2_REG ADCTRL2; // ADC Control 2 180 | union MAX_CONV_REG MAX_CONV; // Max conversions 181 | union CHSELSEQ1_REG CHSELSEQ1; // Channel select sequencing control 182 | union CHSELSEQ2_REG CHSELSEQ2; 183 | union CHSELSEQ3_REG CHSELSEQ3; 184 | union CHSELSEQ4_REG CHSELSEQ4; 185 | union AUTO_SEQ_SR_REG AUTO_SEQ_SR; // Autosequence status register 186 | Uint16 RESULT0; 187 | Uint16 RESULT1; 188 | Uint16 RESULT2; 189 | Uint16 RESULT3; 190 | Uint16 RESULT4; 191 | Uint16 RESULT5; 192 | Uint16 RESULT6; 193 | Uint16 RESULT7; 194 | Uint16 RESULT8; 195 | Uint16 RESULT9; 196 | Uint16 RESULT10; 197 | Uint16 RESULT11; 198 | Uint16 RESULT12; 199 | Uint16 RESULT13; 200 | Uint16 RESULT14; 201 | Uint16 RESULT15; 202 | union ADCTRL3_REG ADCTRL3; 203 | union ADC_ST_FLG_REG ADC_ST_FLAG; 204 | }; 205 | 206 | 207 | //--------------------------------------------------------------------------- 208 | // ADC External References & Function Declarations: 209 | // 210 | extern volatile struct ADC_REGS AdcRegs; 211 | 212 | #endif // end of DSP28_ADC_H definition 213 | 214 | //=========================================================================== 215 | // No more. 216 | //=========================================================================== 217 | -------------------------------------------------------------------------------- /src/DSP28_CpuTimers.h: -------------------------------------------------------------------------------- 1 | // 2 | // TMDX ALPHA RELEASE 3 | // Intended for product evaluation purposes 4 | // 5 | //########################################################################### 6 | // 7 | // FILE: DSP28_CpuTimers.h 8 | // 9 | // TITLE: DSP28 CPU 32-bit Timers Register Definitions. 10 | // 11 | //########################################################################### 12 | // 13 | // Ver | dd mmm yyyy | Who | Description of changes 14 | // =====|=============|======|=============================================== 15 | // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release 16 | // 0.56| 20 May 2002 | L.H. | No change 17 | // 0.57| 27 May 2002 | L.H. | No change 18 | //########################################################################### 19 | 20 | #ifndef DSP28_CPU_TIMERS_H 21 | #define DSP28_CPU_TIMERS_H 22 | 23 | //--------------------------------------------------------------------------- 24 | // CPU Timer Register Bit Definitions: 25 | // 26 | // 27 | // TCR: Control register bit definitions: 28 | struct TCR_BITS { // bits description 29 | Uint16 OUTSTS:1; // 0 Current state of TOUT 30 | Uint16 FORCE:1; // 1 Force TOUT 31 | Uint16 POL:1; // 2 Output polarity 32 | Uint16 TOG:1; // 3 Output toggle mode 33 | Uint16 TSS:1; // 4 Timer Start/Stop 34 | Uint16 TRB:1; // 5 Timer reload 35 | Uint16 FRCEN:1; // 6 Force enable 36 | Uint16 PWIDTH:3; // 9:7 BitTOUT output pulse width 37 | Uint16 SOFT:1; // 10 Emulation modes 38 | Uint16 FREE:1; // 11 39 | Uint16 rsvd:2; // 12:13 reserved 40 | Uint16 TIE:1; // 14 Output enable 41 | Uint16 TIF:1; // 15 Interrupt flag 42 | }; 43 | 44 | union TCR_REG { 45 | Uint16 all; 46 | struct TCR_BITS bit; 47 | }; 48 | 49 | // TPR: Pre-scale low bit definitions: 50 | struct TPR_BITS { // bits description 51 | Uint16 TDDR:8; // 7:0 Divide-down low 52 | Uint16 PSC:8; // 15:8 Prescale counter low 53 | }; 54 | 55 | union TPR_REG { 56 | Uint16 all; 57 | struct TPR_BITS bit; 58 | }; 59 | 60 | // TPRH: Pre-scale high bit definitions: 61 | struct TPRH_BITS { // bits description 62 | Uint16 TDDRH:8; // 7:0 Divide-down high 63 | Uint16 PSCH:8; // 15:8 Prescale counter high 64 | }; 65 | 66 | union TPRH_REG { 67 | Uint16 all; 68 | struct TPRH_BITS bit; 69 | }; 70 | 71 | // TIM, TIMH: Timer register definitions: 72 | struct TIM_REG { 73 | Uint16 LSW; 74 | Uint16 MSW; 75 | }; 76 | 77 | union TIM_GROUP { 78 | Uint32 all; 79 | struct TIM_REG half; 80 | }; 81 | 82 | // PRD, PRDH: Period register definitions: 83 | struct PRD_REG { 84 | Uint16 LSW; 85 | Uint16 MSW; 86 | }; 87 | 88 | union PRD_GROUP { 89 | Uint32 all; 90 | struct PRD_REG half; 91 | }; 92 | 93 | //--------------------------------------------------------------------------- 94 | // CPU Timer Register File: 95 | // 96 | struct CPUTIMER_REGS { 97 | union TIM_GROUP TIM; // Timer counter register 98 | union PRD_GROUP PRD; // Period register 99 | union TCR_REG TCR; // Timer control register 100 | Uint16 rsvd1; // reserved 101 | union TPR_REG TPR; // Timer pre-scale low 102 | union TPRH_REG TPRH; // Timer pre-scale high 103 | }; 104 | 105 | //--------------------------------------------------------------------------- 106 | // CPU Timer Support Variables: 107 | // 108 | struct CPUTIMER_VARS { 109 | volatile struct CPUTIMER_REGS *RegsAddr; 110 | Uint32 InterruptCount; 111 | float CPUFreqInMHz; 112 | float PeriodInUSec; 113 | }; 114 | 115 | //--------------------------------------------------------------------------- 116 | // Function prototypes and external definitions: 117 | // 118 | void InitCpuTimers(void); 119 | void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); 120 | 121 | extern volatile struct CPUTIMER_REGS CpuTimer0Regs; 122 | extern volatile struct CPUTIMER_REGS CpuTimer1Regs; 123 | extern volatile struct CPUTIMER_REGS CpuTimer2Regs; 124 | 125 | extern struct CPUTIMER_VARS CpuTimer0; 126 | extern struct CPUTIMER_VARS CpuTimer1; 127 | extern struct CPUTIMER_VARS CpuTimer2; 128 | 129 | //--------------------------------------------------------------------------- 130 | // Usefull Timer Operations: 131 | // 132 | // Start Timer: 133 | #define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 134 | #define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 135 | #define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 136 | 137 | // Stop Timer: 138 | #define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 139 | #define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 140 | #define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 141 | 142 | // Reload Timer With period Value: 143 | #define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 144 | #define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 145 | #define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 146 | 147 | // Read 32-Bit Timer Value: 148 | #define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all 149 | #define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all 150 | #define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all 151 | 152 | // Read 32-Bit Period Value: 153 | #define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all 154 | #define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all 155 | #define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all 156 | 157 | #endif // end of DSP28_CPU_TIMERS_H definition 158 | 159 | 160 | //=========================================================================== 161 | // No more. 162 | //=========================================================================== 163 | -------------------------------------------------------------------------------- /src/DSP28_DefaultIsr.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP28_DefaultIsr.h 4 | // 5 | // TITLE: DSP28 Devices Default Interrupt Service Routines Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release 12 | // 0.56| 20 May 2002 | L.H. | No change 13 | // 0.57| 27 May 2002 | L.H. | No change 14 | //########################################################################### 15 | 16 | #ifndef DSP28_DEFAULT_ISR_H 17 | #define DSP28_DEFAULT_ISR_H 18 | 19 | //--------------------------------------------------------------------------- 20 | // Default Interrupt Service Routine Declarations: 21 | // 22 | // The following function prototypes are for the 23 | // default ISR routines used with the default PIE vector table. 24 | // This default vector table is found in the DSP28_PieVect.h 25 | // file. 26 | // 27 | 28 | // Non-Peripheral Interrupts: 29 | interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 30 | interrupt void INT14_ISR(void); // CPU-Timer2 31 | interrupt void DATALOG_ISR(void); // Datalogging interrupt 32 | interrupt void RTOSINT_ISR(void); // RTOS interrupt 33 | interrupt void EMUINT_ISR(void); // Emulation interrupt 34 | interrupt void NMI_ISR(void); // Non-maskable interrupt 35 | interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP 36 | interrupt void USER0_ISR(void); // User Defined trap 0 37 | interrupt void USER1_ISR(void); // User Defined trap 1 38 | interrupt void USER2_ISR(void); // User Defined trap 2 39 | interrupt void USER3_ISR(void); // User Defined trap 3 40 | interrupt void USER4_ISR(void); // User Defined trap 4 41 | interrupt void USER5_ISR(void); // User Defined trap 5 42 | interrupt void USER6_ISR(void); // User Defined trap 6 43 | interrupt void USER7_ISR(void); // User Defined trap 7 44 | interrupt void USER8_ISR(void); // User Defined trap 8 45 | interrupt void USER9_ISR(void); // User Defined trap 9 46 | interrupt void USER10_ISR(void); // User Defined trap 10 47 | interrupt void USER11_ISR(void); // User Defined trap 11 48 | 49 | // Group 1 PIE Interrupt Service Routines: 50 | interrupt void PDPINTA_ISR(void); // EV-A 51 | interrupt void PDPINTB_ISR(void); // EV-B 52 | interrupt void XINT1_ISR(void); 53 | interrupt void XINT2_ISR(void); 54 | interrupt void ADCINT_ISR(void); // ADC 55 | interrupt void TINT0_ISR(void); // Timer 0 56 | interrupt void WAKEINT_ISR(void); // WD 57 | 58 | // Group 2 PIE Interrupt Service Routines: 59 | interrupt void CMP1INT_ISR(void); // EV-A 60 | interrupt void CMP2INT_ISR(void); // EV-A 61 | interrupt void CMP3INT_ISR(void); // EV-A 62 | interrupt void T1PINT_ISR(void); // EV-A 63 | interrupt void T1CINT_ISR(void); // EV-A 64 | interrupt void T1UFINT_ISR(void); // EV-A 65 | interrupt void T1OFINT_ISR(void); // EV-A 66 | 67 | // Group 3 PIE Interrupt Service Routines: 68 | interrupt void T2PINT_ISR(void); // EV-A 69 | interrupt void T2CINT_ISR(void); // EV-A 70 | interrupt void T2UFINT_ISR(void); // EV-A 71 | interrupt void T2OFINT_ISR(void); // EV-A 72 | interrupt void CAPINT1_ISR(void); // EV-A 73 | interrupt void CAPINT2_ISR(void); // EV-A 74 | interrupt void CAPINT3_ISR(void); // EV-A 75 | 76 | // Group 4 PIE Interrupt Service Routines: 77 | interrupt void CMP4INT_ISR(void); // EV-B 78 | interrupt void CMP5INT_ISR(void); // EV-B 79 | interrupt void CMP6INT_ISR(void); // EV-B 80 | interrupt void T3PINT_ISR(void); // EV-B 81 | interrupt void T3CINT_ISR(void); // EV-B 82 | interrupt void T3UFINT_ISR(void); // EV-B 83 | interrupt void T3OFINT_ISR(void); // EV-B 84 | 85 | // Group 5 PIE Interrupt Service Routines: 86 | interrupt void T4PINT_ISR(void); // EV-B 87 | interrupt void T4CINT_ISR(void); // EV-B 88 | interrupt void T4UFINT_ISR(void); // EV-B 89 | interrupt void T4OFINT_ISR(void); // EV-B 90 | interrupt void CAPINT4_ISR(void); // EV-B 91 | interrupt void CAPINT5_ISR(void); // EV-B 92 | interrupt void CAPINT6_ISR(void); // EV-B 93 | 94 | // Group 6 PIE Interrupt Service Routines: 95 | interrupt void SPIRXINTA_ISR(void); // SPI 96 | interrupt void SPITXINTA_ISR(void); // SPI 97 | interrupt void MRINTA_ISR(void); // McBSP 98 | interrupt void MXINTA_ISR(void); // McBSP 99 | 100 | 101 | // Group 9 PIE Interrupt Service Routines: 102 | interrupt void SCIRXINTA_ISR(void); // SCI-A 103 | interrupt void SCITXINTA_ISR(void); // SCI-A 104 | interrupt void SCIRXINTB_ISR(void); // SCI-B 105 | interrupt void SCITXINTB_ISR(void); // SCI-B 106 | interrupt void ECAN0INTA_ISR(void); // eCAN 107 | interrupt void ECAN1INTA_ISR(void); // eCAN 108 | 109 | 110 | // Catch-all for Reserved Locations For testing purposes: 111 | interrupt void PIE_RESERVED(void); // Reserved for test 112 | interrupt void rsvd_ISR(void); // for test 113 | 114 | #endif // end of DSP28_DEFAULT_ISR_H definition 115 | 116 | -------------------------------------------------------------------------------- /src/DSP28_DevEmu.h: -------------------------------------------------------------------------------- 1 | // 2 | // TMDX ALPHA RELEASE 3 | // Intended for product evaluation purposes 4 | // 5 | //########################################################################### 6 | // 7 | // FILE: DSP28_DevEmu.h 8 | // 9 | // TITLE: DSP28 Device Emulation Register Definitions. 10 | // 11 | //########################################################################### 12 | // 13 | // Ver | dd mmm yyyy | Who | Description of changes 14 | // =====|=============|======|=============================================== 15 | // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release 16 | // 0.56| 20 May 2002 | L.H. | No change 17 | // 0.57| 27 May 2002 | L.H. | No change 18 | //########################################################################### 19 | 20 | #ifndef DSP28_DEV_EMU_H 21 | #define DSP28_DEV_EMU_H 22 | 23 | //--------------------------------------------------------------------------- 24 | // Device Emulation Register Bit Definitions: 25 | // 26 | // Device Configuration Register Bit Definitions 27 | struct DEVICECNF_BITS { // bits description 28 | Uint16 rsvd1:3; // 2:0 reserved 29 | Uint16 VMAPS:1; // 3 VMAP Status 30 | Uint16 rsvd2:1; // 4 reserved 31 | Uint16 XRSn:1; // 5 XRSn Signal Status 32 | Uint16 rsvd3:10; // 15:6 33 | Uint16 rsvd4:3; // 18:6 34 | Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection 35 | Uint16 rsvd5:12; // 31:20 reserved 36 | }; 37 | 38 | union DEVICECNF_REG { 39 | Uint32 all; 40 | struct DEVICECNF_BITS bit; 41 | }; 42 | 43 | 44 | // Device ID Register Bit Definitions 45 | struct DEVICEID_BITS { // bits description 46 | Uint16 PARTID:16; // 15:0 Part ID 47 | Uint16 REVID:16; // 31:16 Revision 48 | }; 49 | 50 | union DEVICEID_REG { 51 | Uint32 all; 52 | struct DEVICEID_BITS bit; 53 | }; 54 | 55 | struct DEV_EMU_REGS { 56 | union DEVICECNF_REG DEVICECNF; 57 | union DEVICEID_REG DEVICEID; 58 | Uint16 PROTSTART; 59 | Uint16 PROTRANGE; 60 | Uint16 rsvd[202]; 61 | Uint16 M0RAMDFT; 62 | Uint16 M1RAMDFT; 63 | Uint16 L0RAMDFT; 64 | Uint16 L1RAMDFT; 65 | Uint16 H0RAMDFT; 66 | }; 67 | 68 | //--------------------------------------------------------------------------- 69 | // Device Emulation Register References & Function Declarations: 70 | // 71 | extern volatile struct DEV_EMU_REGS DevEmuRegs; 72 | 73 | #endif // end of DSP28_DEV_EMU_H definition 74 | 75 | //=========================================================================== 76 | // No more. 77 | //=========================================================================== 78 | -------------------------------------------------------------------------------- /src/DSP28_Device.h: -------------------------------------------------------------------------------- 1 | // 2 | // TMDX ALPHA RELEASE 3 | // Intended for product evaluation purposes 4 | // 5 | //########################################################################### 6 | // 7 | // FILE: DSP28_Device.h 8 | // 9 | // TITLE: DSP28 Device Definitions. 10 | // 11 | //########################################################################### 12 | // 13 | // Ver | dd mmm yyyy | Who | Description of changes 14 | // =====|=============|======|=============================================== 15 | // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release 16 | // 0.56| 20 May 2002 | L.H. | No change 17 | // 0.57| 24 May 2002 | L.H. | Added generic BIT# #define statements 18 | //########################################################################### 19 | 20 | #ifndef DSP28_DEVICE_H 21 | #define DSP28_DEVICE_H 22 | 23 | #define TARGET 1 24 | //--------------------------------------------------------------------------- 25 | // User To Select Target Device: 26 | 27 | #define F2812 TARGET 28 | #define F2810 0 29 | 30 | //--------------------------------------------------------------------------- 31 | // Common CPU Definitions: 32 | // 33 | 34 | extern cregister volatile unsigned int IFR; 35 | extern cregister volatile unsigned int IER; 36 | #define EINT asm(" clrc INTM") 37 | #define DINT asm(" setc INTM") 38 | #define ERTM asm(" clrc DBGM") 39 | #define DRTM asm(" setc DBGM") 40 | #define EALLOW asm(" EALLOW") 41 | #define EDIS asm(" EDIS") 42 | #define ESTOP0 asm(" ESTOP0") 43 | #define NOP asm(" NOP") 44 | 45 | #define M_INT1 0x0001 46 | #define M_INT2 0x0002 47 | #define M_INT3 0x0004 48 | #define M_INT4 0x0008 49 | #define M_INT5 0x0010 50 | #define M_INT6 0x0020 51 | #define M_INT7 0x0040 52 | #define M_INT8 0x0080 53 | #define M_INT9 0x0100 54 | #define M_INT10 0x0200 55 | #define M_INT11 0x0400 56 | #define M_INT12 0x0800 57 | #define M_INT13 0x1000 58 | #define M_INT14 0x2000 59 | #define M_DLOG 0x4000 60 | #define M_RTOS 0x8000 61 | 62 | #define BIT0 0x0001 63 | #define BIT1 0x0002 64 | #define BIT2 0x0004 65 | #define BIT3 0x0008 66 | #define BIT4 0x0010 67 | #define BIT5 0x0020 68 | #define BIT6 0x0040 69 | #define BIT7 0x0080 70 | #define BIT8 0x0100 71 | #define BIT9 0x0200 72 | #define BIT10 0x0400 73 | #define BIT11 0x0800 74 | #define BIT12 0x1000 75 | #define BIT13 0x2000 76 | #define BIT14 0x4000 77 | #define BIT15 0x8000 78 | 79 | 80 | 81 | //--------------------------------------------------------------------------- 82 | // For Portability, User Is Recommended To Use Following Data Type Size 83 | // Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: 84 | // 85 | 86 | typedef int int16; 87 | typedef long int32; 88 | typedef unsigned int Uint16; 89 | typedef unsigned long Uint32; 90 | 91 | //--------------------------------------------------------------------------- 92 | // Include All Peripheral Header Files: 93 | // 94 | 95 | #include "DSP28_GlobalPrototypes.h" // Prototypes for global functions within the 96 | // .c files. 97 | 98 | #include "DSP28_SysCtrl.h" // System Control/Power Modes 99 | #include "DSP28_DevEmu.h" // Device Emulation Registers 100 | #include "DSP28_Xintf.h" // External Interface Registers 101 | #include "DSP28_CpuTimers.h" // 32-bit CPU Timers 102 | #include "DSP28_PieCtrl.h" // PIE Control Registers 103 | #include "DSP28_PieVect.h" // PIE Vector Table 104 | #include "DSP28_DefaultIsr.h" // Software Prioritization for PIE Interrupts 105 | #include "DSP28_Spi.h" // SPI Registers 106 | #include "DSP28_Sci.h" // SCI Registers 107 | #include "DSP28_Mcbsp.h" // McBSP Registers 108 | #include "DSP28_ECan.h" // Enhanced eCAN Registers 109 | #include "DSP28_Gpio.h" // General Purpose I/O Registers 110 | #include "DSP28_Ev.h" // Event Manager Registers 111 | #include "DSP28_Adc.h" // ADC Registers 112 | #include "DSP28_XIntrupt.h" // External Interrupts 113 | 114 | //--------------------------------------------------------------------------- 115 | // Define Device Init Function Prototype: 116 | // 117 | 118 | 119 | #endif // end of DSP28_DEVICE_H definition 120 | 121 | 122 | //=========================================================================== 123 | // No more. 124 | //=========================================================================== 125 | -------------------------------------------------------------------------------- /src/DSP28_GlobalPrototypes.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: Example.h 4 | // 5 | // TITLE: Example program definition file 6 | //########################################################################### 7 | // 8 | // Ver | dd mmm yyyy | Who | Description of changes 9 | // =====|=============|======|=============================================== 10 | // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release 11 | // 0.56| 20 May 2002 | L.H. | No change 12 | // 0.57| 27 May 2002 | L.H. | No change 13 | //########################################################################### 14 | 15 | 16 | #ifndef EXAMPLE_H 17 | #define EXAMPLE_H 18 | 19 | /*---- shared global function prototypes -----------------------------------*/ 20 | extern void InitAdc(void); 21 | extern void InitDevEmu(void); 22 | extern void InitDevice(void); 23 | extern void InitECana(void); 24 | extern void InitEv(void); 25 | extern void InitGpio(void); 26 | extern void InitMcbsp(void); 27 | extern void InitPieCtrl(void); 28 | extern void InitPieVectTable(void); 29 | extern void InitSci(void); 30 | extern void InitSpi(void); 31 | extern void InitSysCtrl(void); 32 | extern void InitXintf(void); 33 | extern void InitXIntrupt(void); 34 | 35 | extern void KickDog(void); 36 | 37 | #endif // - end of EXAMPLE_H 38 | 39 | -------------------------------------------------------------------------------- /src/DSP28_PieCtrl.h: -------------------------------------------------------------------------------- 1 | // 2 | // TMDX ALPHA RELEASE 3 | // Intended for product evaluation purposes 4 | // 5 | //########################################################################### 6 | // 7 | // FILE: DSP28_PieCtrl.h 8 | // 9 | // TITLE: DSP28 Device PIE Control Register Definitions. 10 | // 11 | //########################################################################### 12 | // 13 | // Ver | dd mmm yyyy | Who | Description of changes 14 | // =====|=============|======|=============================================== 15 | // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release 16 | // 0.56| 20 May 2002 | L.H. | No change 17 | // 0.57| 27 May 2002 | L.H. | No change 18 | //########################################################################### 19 | 20 | 21 | #ifndef DSP28_PIE_CTRL_H 22 | #define DSP28_PIE_CTRL_H 23 | 24 | //--------------------------------------------------------------------------- 25 | // PIE Control Register Bit Definitions: 26 | // 27 | // PIECTRL: Register bit definitions: 28 | struct PIECTRL_BITS { // bits description 29 | Uint16 ENPIE:1; // 0 Enable PIE block 30 | Uint16 PIEVECT:15; // 15:1 Fetched vector address 31 | }; 32 | 33 | union PIECTRL_REG { 34 | Uint16 all; 35 | struct PIECTRL_BITS bit; 36 | }; 37 | 38 | // PIEIER: Register bit definitions: 39 | struct PIEIER_BITS { // bits description 40 | Uint16 INTx1:1; // 0 INTx.1 41 | Uint16 INTx2:1; // 1 INTx.2 42 | Uint16 INTx3:1; // 2 INTx.3 43 | Uint16 INTx4:1; // 3 INTx.4 44 | Uint16 INTx5:1; // 4 INTx.5 45 | Uint16 INTx6:1; // 5 INTx.6 46 | Uint16 INTx7:1; // 6 INTx.7 47 | Uint16 INTx8:1; // 7 INTx.8 48 | Uint16 rsvd:8; // 15:8 reserved 49 | }; 50 | 51 | union PIEIER_REG { 52 | Uint16 all; 53 | struct PIEIER_BITS bit; 54 | }; 55 | 56 | // PIEIFR: Register bit definitions: 57 | struct PIEIFR_BITS { // bits description 58 | Uint16 INTx1:1; // 0 INTx.1 59 | Uint16 INTx2:1; // 1 INTx.2 60 | Uint16 INTx3:1; // 2 INTx.3 61 | Uint16 INTx4:1; // 3 INTx.4 62 | Uint16 INTx5:1; // 4 INTx.5 63 | Uint16 INTx6:1; // 5 INTx.6 64 | Uint16 INTx7:1; // 6 INTx.7 65 | Uint16 INTx8:1; // 7 INTx.8 66 | Uint16 rsvd:8; // 15:8 reserved 67 | }; 68 | 69 | union PIEIFR_REG { 70 | Uint16 all; 71 | struct PIEIFR_BITS bit; 72 | }; 73 | 74 | // PIEACK: Register bit definitions: 75 | struct PIEACK_BITS { // bits description 76 | Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 77 | Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 78 | Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 79 | Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 80 | Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 81 | Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 82 | Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 83 | Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 84 | Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 85 | Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 86 | Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 87 | Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 88 | Uint16 rsvd:4; // 15:12 reserved 89 | }; 90 | 91 | union PIEACK_REG { 92 | Uint16 all; 93 | struct PIEACK_BITS bit; 94 | }; 95 | 96 | //--------------------------------------------------------------------------- 97 | // PIE Control Register File: 98 | // 99 | struct PIE_CTRL_REGS { 100 | union PIECTRL_REG PIECRTL; // PIE control register 101 | union PIEACK_REG PIEACK; // PIE acknowledge 102 | union PIEIER_REG PIEIER1; // PIE INT1 IER register 103 | union PIEIFR_REG PIEIFR1; // PIE INT1 IFR register 104 | union PIEIER_REG PIEIER2; // PIE INT2 IER register 105 | union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register 106 | union PIEIER_REG PIEIER3; // PIE INT3 IER register 107 | union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register 108 | union PIEIER_REG PIEIER4; // PIE INT4 IER register 109 | union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register 110 | union PIEIER_REG PIEIER5; // PIE INT5 IER register 111 | union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register 112 | union PIEIER_REG PIEIER6; // PIE INT6 IER register 113 | union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register 114 | union PIEIER_REG PIEIER7; // PIE INT7 IER register 115 | union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register 116 | union PIEIER_REG PIEIER8; // PIE INT8 IER register 117 | union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register 118 | union PIEIER_REG PIEIER9; // PIE INT9 IER register 119 | union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register 120 | union PIEIER_REG PIEIER10; // PIE INT10 IER register 121 | union PIEIFR_REG PIEIFR10; // PIE INT10 IFR register 122 | union PIEIER_REG PIEIER11; // PIE INT11 IER register 123 | union PIEIFR_REG PIEIFR11; // PIE INT11 IFR register 124 | union PIEIER_REG PIEIER12; // PIE INT12 IER register 125 | union PIEIFR_REG PIEIFR12; // PIE INT12 IFR register 126 | }; 127 | 128 | #define PIEACK_GROUP1 0x0001; 129 | #define PIEACK_GROUP2 0x0002; 130 | #define PIEACK_GROUP3 0x0004; 131 | #define PIEACK_GROUP4 0x0008; 132 | #define PIEACK_GROUP5 0x0010; 133 | #define PIEACK_GROUP6 0x0020; 134 | #define PIEACK_GROUP7 0x0040; 135 | #define PIEACK_GROUP8 0x0080; 136 | #define PIEACK_GROUP9 0x0100; 137 | #define PIEACK_GROUP10 0x0200; 138 | #define PIEACK_GROUP11 0x0400; 139 | #define PIEACK_GROUP12 0x0800; 140 | 141 | //--------------------------------------------------------------------------- 142 | // PIE Control Registers External References & Function Declarations: 143 | // 144 | extern volatile struct PIE_CTRL_REGS PieCtrl; 145 | 146 | #endif // end of DSP28_PIE_CTRL_H definition 147 | 148 | //=========================================================================== 149 | // No more. 150 | //=========================================================================== 151 | -------------------------------------------------------------------------------- /src/DSP28_PieVect.h: -------------------------------------------------------------------------------- 1 | // 2 | // TMDX ALPHA RELEASE 3 | // Intended for product evaluation purposes 4 | // 5 | //########################################################################### 6 | // 7 | // FILE: DSP28_PieVect.h 8 | // 9 | // TITLE: DSP28 Devices PIE Vector Table Definitions. 10 | // 11 | //########################################################################### 12 | // 13 | // Ver | dd mmm yyyy | Who | Description of changes 14 | // =====|=============|======|=============================================== 15 | // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release 16 | // 0.56| 20 May 2002 | L.H. | No change 17 | // 0.57| 27 May 2002 | L.H. | No change 18 | //########################################################################### 19 | 20 | #ifndef DSP28_PIE_VECT_H 21 | #define DSP28_PIE_VECT_H 22 | 23 | 24 | //--------------------------------------------------------------------------- 25 | // PIE Interrupt Vector Table Definition: 26 | // 27 | // Create a user type called PINT (pointer to interrupt): 28 | 29 | typedef interrupt void(*PINT)(void); 30 | 31 | // Define Vector Table: 32 | struct PIE_VECT_TABLE { 33 | 34 | // Reset is never fetched from this table. 35 | // It will always be fetched from 0x3FFFC0 in either 36 | // boot ROM or XINTF Zone 7 depending on the state of 37 | // the XMP/MC input signal. On the F2810 it is always 38 | // fetched from boot ROM. 39 | 40 | PINT PIE1_RESERVED; 41 | PINT PIE2_RESERVED; 42 | PINT PIE3_RESERVED; 43 | PINT PIE4_RESERVED; 44 | PINT PIE5_RESERVED; 45 | PINT PIE6_RESERVED; 46 | PINT PIE7_RESERVED; 47 | PINT PIE8_RESERVED; 48 | PINT PIE9_RESERVED; 49 | PINT PIE10_RESERVED; 50 | PINT PIE11_RESERVED; 51 | PINT PIE12_RESERVED; 52 | PINT PIE13_RESERVED; 53 | 54 | // Non-Peripheral Interrupts: 55 | PINT XINT13; // XINT13 56 | PINT TINT2; // CPU-Timer2 57 | PINT DATALOG; // Datalogging interrupt 58 | PINT RTOSINT; // RTOS interrupt 59 | PINT EMUINT; // Emulation interrupt 60 | PINT XNMI; // Non-maskable interrupt 61 | PINT ILLEGAL; // Illegal operation TRAP 62 | PINT USER0; // User Defined trap 0 63 | PINT USER1; // User Defined trap 1 64 | PINT USER2; // User Defined trap 2 65 | PINT USER3; // User Defined trap 3 66 | PINT USER4; // User Defined trap 4 67 | PINT USER5; // User Defined trap 5 68 | PINT USER6; // User Defined trap 6 69 | PINT USER7; // User Defined trap 7 70 | PINT USER8; // User Defined trap 8 71 | PINT USER9; // User Defined trap 9 72 | PINT USER10; // User Defined trap 10 73 | PINT USER11; // User Defined trap 11 74 | 75 | // Group 1 PIE Peripheral Vectors: 76 | PINT PDPINTA; // EV-A 77 | PINT PDPINTB; // EV-B 78 | PINT rsvd1_3; 79 | PINT XINT1; 80 | PINT XINT2; 81 | PINT ADCINT; // ADC 82 | PINT TINT0; // Timer 0 83 | PINT WAKEINT; // WD 84 | 85 | // Group 2 PIE Peripheral Vectors: 86 | PINT CMP1INT; // EV-A 87 | PINT CMP2INT; // EV-A 88 | PINT CMP3INT; // EV-A 89 | PINT T1PINT; // EV-A 90 | PINT T1CINT; // EV-A 91 | PINT T1UFINT; // EV-A 92 | PINT T1OFINT; // EV-A 93 | PINT rsvd2_8; 94 | 95 | // Group 3 PIE Peripheral Vectors: 96 | PINT T2PINT; // EV-A 97 | PINT T2CINT; // EV-A 98 | PINT T2UFINT; // EV-A 99 | PINT T2OFINT; // EV-A 100 | PINT CAPINT1; // EV-A 101 | PINT CAPINT2; // EV-A 102 | PINT CAPINT3; // EV-A 103 | PINT rsvd3_8; 104 | 105 | // Group 4 PIE Peripheral Vectors: 106 | PINT CMP4INT; // EV-B 107 | PINT CMP5INT; // EV-B 108 | PINT CMP6INT; // EV-B 109 | PINT T3PINT; // EV-B 110 | PINT T3CINT; // EV-B 111 | PINT T3UFINT; // EV-B 112 | PINT T3OFINT; // EV-B 113 | PINT rsvd4_8; 114 | 115 | // Group 5 PIE Peripheral Vectors: 116 | PINT T4PINT; // EV-B 117 | PINT T4CINT; // EV-B 118 | PINT T4UFINT; // EV-B 119 | PINT T4OFINT; // EV-B 120 | PINT CAPINT4; // EV-B 121 | PINT CAPINT5; // EV-B 122 | PINT CAPINT6; // EV-B 123 | PINT rsvd5_8; 124 | 125 | // Group 6 PIE Peripheral Vectors: 126 | PINT SPIRXINTA; // SPI-A 127 | PINT SPITXINTA; // SPI-A 128 | PINT rsvd6_3; 129 | PINT rsvd6_4; 130 | PINT MRINTA; // McBSP-A 131 | PINT MXINTA; // McBSP-A 132 | PINT rsvd6_7; 133 | PINT rsvd6_8; 134 | 135 | // Group 7 PIE Peripheral Vectors: 136 | PINT rsvd7_1; 137 | PINT rsvd7_2; 138 | PINT rsvd7_3; 139 | PINT rsvd7_4; 140 | PINT rsvd7_5; 141 | PINT rsvd7_6; 142 | PINT rsvd7_7; 143 | PINT rsvd7_8; 144 | 145 | // Group 8 PIE Peripheral Vectors: 146 | PINT rsvd8_1; 147 | PINT rsvd8_2; 148 | PINT rsvd8_3; 149 | PINT rsvd8_4; 150 | PINT rsvd8_5; 151 | PINT rsvd8_6; 152 | PINT rsvd8_7; 153 | PINT rsvd8_8; 154 | 155 | // Group 9 PIE Peripheral Vectors: 156 | PINT RXAINT; // SCI-A 157 | PINT TXAINT; // SCI-A 158 | PINT RXBINT; // SCI-B 159 | PINT TXBINT; // SCI-B 160 | PINT ECAN0INTA; // eCAN 161 | PINT ECAN1INTA; // eCAN 162 | PINT rsvd9_7; 163 | PINT rsvd9_8; 164 | 165 | // Group 10 PIE Peripheral Vectors: 166 | PINT rsvd10_1; 167 | PINT rsvd10_2; 168 | PINT rsvd10_3; 169 | PINT rsvd10_4; 170 | PINT rsvd10_5; 171 | PINT rsvd10_6; 172 | PINT rsvd10_7; 173 | PINT rsvd10_8; 174 | 175 | // Group 11 PIE Peripheral Vectors: 176 | PINT rsvd11_1; 177 | PINT rsvd11_2; 178 | PINT rsvd11_3; 179 | PINT rsvd11_4; 180 | PINT rsvd11_5; 181 | PINT rsvd11_6; 182 | PINT rsvd11_7; 183 | PINT rsvd11_8; 184 | 185 | // Group 12 PIE Peripheral Vectors: 186 | PINT rsvd12_1; 187 | PINT rsvd12_2; 188 | PINT rsvd12_3; 189 | PINT rsvd12_4; 190 | PINT rsvd12_5; 191 | PINT rsvd12_6; 192 | PINT rsvd12_7; 193 | PINT rsvd12_8; 194 | }; 195 | 196 | //--------------------------------------------------------------------------- 197 | // PIE Interrupt Vector Table External References & Function Declarations: 198 | // 199 | extern struct PIE_VECT_TABLE PieVectTable; 200 | 201 | 202 | #endif // end of DSP28_PIE_VECT_H definition 203 | 204 | //=========================================================================== 205 | // No more. 206 | //=========================================================================== 207 | 208 | -------------------------------------------------------------------------------- /src/DSP28_Sci.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/natsu1211/F2812_PMSM_SVPWM_PI/e61f8ed2da756a8a6a791fd4440c8b509083bb9c/src/DSP28_Sci.c -------------------------------------------------------------------------------- /src/DSP28_Sci.h: -------------------------------------------------------------------------------- 1 | // 2 | // TMDX ALPHA RELEASE 3 | // Intended for product evaluation purposes 4 | // 5 | //########################################################################### 6 | // 7 | // FILE: DSP28_Sci.h 8 | // 9 | // TITLE: DSP28 Device SCI Register Definitions. 10 | // 11 | //########################################################################### 12 | // 13 | // Ver | dd mmm yyyy | Who | Description of changes 14 | // =====|=============|======|=============================================== 15 | // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release 16 | // 0.56| 20 May 2002 | L.H. | No change 17 | // 0.57| 27 May 2002 | L.H. | No change 18 | //########################################################################### 19 | 20 | #ifndef DSP28_SCI_H 21 | #define DSP28_SCI_H 22 | 23 | //--------------------------------------------------------------------------- 24 | // SCI Individual Register Bit Definitions 25 | 26 | //---------------------------------------------------------- 27 | // SCICCR communication control register bit definitions: 28 | // 29 | 30 | struct SCICCR_BITS { // bit description 31 | Uint16 SCICHAR:3; // 2:0 Character length control 32 | Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control 33 | Uint16 LOOPBKENA:1; // 4 Loop Back enable 34 | Uint16 PARITYENA:1; // 5 Parity enable 35 | Uint16 PARITY:1; // 6 Even or Odd Parity 36 | Uint16 STOPBITS:1; // 7 Number of Stop Bits 37 | Uint16 rsvd1:8; // 15:8 reserved 38 | }; 39 | 40 | union SCICCR_REG { 41 | Uint16 all; 42 | struct SCICCR_BITS bit; 43 | }; 44 | 45 | //------------------------------------------- 46 | // SCICTL1 control register 1 bit definitions: 47 | // 48 | 49 | struct SCICTL1_BITS { // bit description 50 | Uint16 RXENA:1; // 0 SCI receiver enable 51 | Uint16 TXENA:1; // 1 SCI transmitter enable 52 | Uint16 SLEEP:1; // 2 SCI sleep 53 | Uint16 TXWAKE:1; // 3 Transmitter wakeup method 54 | Uint16 rsvd:1; // 4 reserved 55 | Uint16 SWRESET:1; // 5 Software reset 56 | Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable 57 | Uint16 rsvd1:9; // 15:7 reserved 58 | 59 | }; 60 | 61 | union SCICTL1_REG { 62 | Uint16 all; 63 | struct SCICTL1_BITS bit; 64 | }; 65 | 66 | //--------------------------------------------- 67 | // SCICTL2 control register 2 bit definitions: 68 | // 69 | 70 | struct SCICTL2_BITS { // bit description 71 | Uint16 TXINTENA:1; // 0 Transmit interrupt enable 72 | Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable 73 | Uint16 rsvd:4; // 5:2 reserved 74 | Uint16 TXEMPTY:1; // 6 Transmitter empty flag 75 | Uint16 TXRDY:1; // 7 Transmitter ready flag 76 | Uint16 rsvd1:8; // 15:8 reserved 77 | 78 | }; 79 | 80 | union SCICTL2_REG { 81 | Uint16 all; 82 | struct SCICTL2_BITS bit; 83 | }; 84 | 85 | //--------------------------------------------------- 86 | // SCIRXST Receiver status register bit definitions: 87 | // 88 | 89 | struct SCIRXST_BITS { // bit description 90 | Uint16 rsvd:1; // 0 reserved 91 | Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag 92 | Uint16 PE:1; // 2 Parity error flag 93 | Uint16 OE:1; // 3 Overrun error flag 94 | Uint16 FE:1; // 4 Framing error flag 95 | Uint16 BRKDT:1; // 5 Break-detect flag 96 | Uint16 RXRDY:1; // 6 Receiver ready flag 97 | Uint16 RXERR:1; // 7 Receiver error flag 98 | 99 | }; 100 | 101 | union SCIRXST_REG { 102 | Uint16 all; 103 | struct SCIRXST_BITS bit; 104 | }; 105 | 106 | //---------------------------------------------------- 107 | // SCIRXBUF Receiver Data Buffer with FIFO bit definitions: 108 | // 109 | 110 | struct SCIRXBUF_BITS { // bits description 111 | Uint16 RXDT:8; // 7:0 Receive word 112 | Uint16 rsvd:6; // 13:8 reserved 113 | Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode 114 | Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode 115 | }; 116 | 117 | union SCIRXBUF_REG { 118 | Uint16 all; 119 | struct SCIRXBUF_BITS bit; 120 | }; 121 | 122 | //-------------------------------------------------- 123 | // SCIPRI Priority control register bit definitions: 124 | // 125 | // 126 | 127 | struct SCIPRI_BITS { // bit description 128 | Uint16 rsvd:3; // 2:0 reserved 129 | Uint16 FREE:1; // 3 Free emulation suspend mode 130 | Uint16 SOFT:1; // 4 Soft emulation suspend mode 131 | Uint16 rsvd1:3; // 7:5 reserved 132 | }; 133 | 134 | union SCIPRI_REG { 135 | Uint16 all; 136 | struct SCIPRI_BITS bit; 137 | }; 138 | 139 | //------------------------------------------------- 140 | // SCI FIFO Transmit register bit definitions: 141 | // 142 | // 143 | 144 | struct SCIFFTX_BITS { // bit description 145 | Uint16 TXFFILIL:5; // 4:0 Interrupt level 146 | Uint16 TXFFIENA:1; // 5 Interrupt enable 147 | Uint16 TXINTCLR:1; // 6 Clear INT flag 148 | Uint16 TXFFINT:1; // 7 INT flag 149 | Uint16 TXFFST:5; // 12:8 FIFO status 150 | Uint16 TXFIFOXRESET:1; // 13 FIFO reset 151 | Uint16 SCIFFENA:1; // 14 Enhancement enable 152 | Uint16 resvd:1; // 15 reserved 153 | 154 | }; 155 | 156 | union SCIFFTX_REG { 157 | Uint16 all; 158 | struct SCIFFTX_BITS bit; 159 | }; 160 | 161 | //------------------------------------------------ 162 | // SCI FIFO recieve register bit definitions: 163 | // 164 | // 165 | 166 | struct SCIFFRX_BITS { // bits description 167 | Uint16 RXFFIL:5; // 4:0 Interrupt level 168 | Uint16 RXFFIENA:1; // 5 Interrupt enable 169 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 170 | Uint16 RXFFINT:1; // 7 INT flag 171 | Uint16 RXFIFST:5; // 12:8 FIFO status 172 | Uint16 RXFIFORESET:1; // 13 FIFO reset 173 | Uint16 RXOVF_CLR:1; // 14 Clear overflow 174 | Uint16 RXFFOVF:1; // 15 FIFO overflow 175 | 176 | }; 177 | 178 | union SCIFFRX_REG { 179 | Uint16 all; 180 | struct SCIFFRX_BITS bit; 181 | }; 182 | 183 | // SCI FIFO control register bit definitions: 184 | struct SCIFFCT_BITS { // bits description 185 | Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay 186 | Uint16 rsvd:5; // 12:8 reserved 187 | Uint16 CDC:1; // 13 Auto baud mode enable 188 | Uint16 ABDCLR:1; // 14 Auto baud clear 189 | Uint16 ABD:1; // 15 Auto baud detect 190 | }; 191 | 192 | union SCIFFCT_REG { 193 | Uint16 all; 194 | struct SCIFFCT_BITS bit; 195 | }; 196 | 197 | //--------------------------------------------------------------------------- 198 | // SCI Register File: 199 | // 200 | struct SCI_REGS { 201 | union SCICCR_REG SCICCR; // Communications control register 202 | union SCICTL1_REG SCICTL1; // Control register 1 203 | Uint16 SCIHBAUD; // Baud rate (high) register 204 | Uint16 SCILBAUD; // Baud rate (low) register 205 | union SCICTL2_REG SCICTL2; // Control register 2 206 | union SCIRXST_REG SCIRXST; // Recieve status register 207 | Uint16 SCIRXEMU; // Recieve emulation buffer register 208 | union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer 209 | Uint16 rsvd1; // reserved 210 | Uint16 SCITXBUF; // Transmit data buffer 211 | union SCIFFTX_REG SCIFFTX; // FIFO transmit register 212 | union SCIFFRX_REG SCIFFRX; // FIFO recieve register 213 | union SCIFFCT_REG SCIFFCT; // FIFO control register 214 | Uint16 rsvd2; // reserved 215 | Uint16 rsvd3; // reserved 216 | union SCIPRI_REG SCIPRI; // FIFO Priority control 217 | }; 218 | 219 | //--------------------------------------------------------------------------- 220 | // SCI External References & Function Declarations: 221 | // 222 | extern volatile struct SCI_REGS SciaRegs; 223 | extern volatile struct SCI_REGS ScibRegs; 224 | 225 | #endif // end of DSP28_SCI_H definition 226 | 227 | //=========================================================================== 228 | // No more. 229 | //=========================================================================== 230 | -------------------------------------------------------------------------------- /src/DSP28_Spi.h: -------------------------------------------------------------------------------- 1 | // 2 | // TMDX ALPHA RELEASE 3 | // Intended for product evaluation purposes 4 | // 5 | //########################################################################### 6 | // 7 | // FILE: DSP28_Spi.h 8 | // 9 | // TITLE: DSP28 Device SPI Register Definitions. 10 | // 11 | //########################################################################### 12 | // 13 | // Ver | dd mmm yyyy | Who | Description of changes 14 | // =====|=============|======|=============================================== 15 | // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release 16 | // 0.56| 20 May 2002 | L.H. | No change 17 | // 0.57| 27 May 2002 | L.H. | No change 18 | //########################################################################### 19 | 20 | #ifndef DSP28_SPI_H 21 | #define DSP28_SPI_H 22 | 23 | //--------------------------------------------------------------------------- 24 | // SPI Individual Register Bit Definitions: 25 | // 26 | // SPI FIFO Transmit register bit definitions: 27 | struct SPIFFTX_BITS { // bit description 28 | Uint16 TXFFIL:5; // 4:0 Interrupt level 29 | Uint16 TXFFIENA:1; // 5 Interrupt enable 30 | Uint16 TXFFINTINTCLR:1; // 6 Clear INT flag 31 | Uint16 TXFFINT:1; // 7 INT flag 32 | Uint16 TXFFST:5; // 12:8 FIFO status 33 | Uint16 TXFIFORESET:1; // 14 Enhancement enable 34 | Uint16 rsvd:1; // 15 reserved 35 | }; 36 | 37 | union SPIFFTX_REG { 38 | Uint16 all; 39 | struct SPIFFTX_BITS bit; 40 | }; 41 | 42 | //-------------------------------------------- 43 | // SPI FIFO recieve register bit definitions: 44 | // 45 | // 46 | struct SPIFFRX_BITS { // bits description 47 | Uint16 RXFFIL:5; // 4:0 Interrupt level 48 | Uint16 RXFFIENA:1; // 5 Interrupt enable 49 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 50 | Uint16 RXFFINT:1; // 7 INT flag 51 | Uint16 RXFFST:5; // 12:8 FIFO status 52 | Uint16 RXFIFORESET:1; // 13 FIFO reset 53 | Uint16 RXFFOVFCLR:1; // 14 Clear overflow 54 | Uint16 RXFFOVF:1; // 15 FIFO overflow 55 | 56 | }; 57 | 58 | union SPIFFRX_REG { 59 | Uint16 all; 60 | struct SPIFFRX_BITS bit; 61 | }; 62 | 63 | //-------------------------------------------- 64 | // SPI FIFO control register bit definitions: 65 | // 66 | // 67 | struct SPIFFCT_BITS { // bits description 68 | Uint16 TXDLY:8; // 7:0 FIFO transmit delay 69 | Uint16 rsvd:8; // 15:8 reserved 70 | }; 71 | 72 | union SPIFFCT_REG { 73 | Uint16 all; 74 | struct SPIFFCT_BITS bit; 75 | }; 76 | 77 | //--------------------------------------------- 78 | // SPI configuration register bit definitions: 79 | // 80 | // 81 | struct SPICCR_BITS { // bits description 82 | Uint16 SPICHAR:4; // 3:0 Character length control 83 | Uint16 SPILBK:1; // 4 Loop-back enable/disable 84 | Uint16 rsvd1:1; // 5 reserved 85 | Uint16 CLKPOLARITY:1; // 6 Clock polarity 86 | Uint16 RESET:1; // 7 SPI SW Reset 87 | Uint16 rsvd2:8; // 15:8 reserved 88 | }; 89 | 90 | union SPICCR_REG { 91 | Uint16 all; 92 | struct SPICCR_BITS bit; 93 | }; 94 | 95 | //------------------------------------------------- 96 | // SPI operation control register bit definitions: 97 | // 98 | // 99 | struct SPICTL_BITS { // bits description 100 | Uint16 SPIINTENA:1; // 0 Interrupt enable 101 | Uint16 TALK:1; // 1 Master/Slave transmit enable 102 | Uint16 MASTER_SLAVE:1; // 2 Network control mode 103 | Uint16 CLK_PHASE:1; // 3 Clock phase select 104 | Uint16 OVERRUN:1; // 4 Overrun interrupt enable 105 | Uint16 rsvd:11; // 15:5 reserved 106 | }; 107 | 108 | union SPICTL_REG { 109 | Uint16 all; 110 | struct SPICTL_BITS bit; 111 | }; 112 | 113 | //-------------------------------------- 114 | // SPI status register bit definitions: 115 | // 116 | // 117 | struct SPISTS_BITS { // bits description 118 | Uint16 rsvd1:5; // 4:0 reserved 119 | Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag 120 | Uint16 INT_FLAG:1; // 6 SPI interrupt flag 121 | Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag 122 | Uint16 rsvd2:8; // 15:8 reserved 123 | }; 124 | 125 | union SPISTS_REG { 126 | Uint16 all; 127 | struct SPISTS_BITS bit; 128 | }; 129 | 130 | //------------------------------------------------ 131 | // SPI priority control register bit definitions: 132 | // 133 | // 134 | struct SPIPRI_BITS { // bits description 135 | Uint16 rsvd1:4; // 3:0 reserved 136 | Uint16 FREE:1; // 4 Free emulation mode control 137 | Uint16 SOFT:1; // 5 Soft emulation mode control 138 | Uint16 PRIORITY:1; // 6 Interrupt priority select 139 | Uint16 rsvd2:9; // 15:7 reserved 140 | }; 141 | 142 | union SPIPRI_REG { 143 | Uint16 all; 144 | struct SPIPRI_BITS bit; 145 | }; 146 | 147 | //--------------------------------------------------------------------------- 148 | // SPI Register File: 149 | // 150 | struct SPI_REGS { 151 | union SPICCR_REG SPICCR; // Configuration register 152 | union SPICTL_REG SPICTL; // Operation control register 153 | union SPISTS_REG SPISTS; // Status register 154 | Uint16 rsvd1; // reserved 155 | Uint16 SPIBRR; // Baud Rate 156 | Uint16 rsvd2; // reserved 157 | Uint16 SPIRXEMU; // Emulation buffer 158 | Uint16 SPIRXBUF; // Serial input buffer 159 | Uint16 SPITXBUF; // Serial output buffer 160 | Uint16 SPIDAT; // Serial data 161 | union SPIFFTX_REG SPIFFTX; // FIFO transmit register 162 | union SPIFFRX_REG SPIFFRX; // FIFO recieve register 163 | union SPIFFCT_REG SPIFFCT; // FIFO control register 164 | Uint16 rsvd3[2]; // reserved 165 | union SPIPRI_REG SPIPRI; // FIFO Priority control 166 | }; 167 | 168 | //--------------------------------------------------------------------------- 169 | // SPI External References & Function Declarations: 170 | // 171 | extern volatile struct SPI_REGS SpiaRegs; 172 | extern volatile struct SPI_REGS SpibRegs; 173 | 174 | #endif // end of DSP28_SPI_H definition 175 | 176 | //=========================================================================== 177 | // No more. 178 | //=========================================================================== 179 | -------------------------------------------------------------------------------- /src/DSP28_XIntrupt.h: -------------------------------------------------------------------------------- 1 | // 2 | // TMDX ALPHA RELEASE 3 | // Intended for product evaluation purposes 4 | // 5 | //########################################################################### 6 | // 7 | // FILE: DSP28_XIntrupt.h 8 | // 9 | // TITLE: DSP28 Device External Interrupt Register Definitions. 10 | // 11 | //########################################################################### 12 | // 13 | // Ver | dd mmm yyyy | Who | Description of changes 14 | // =====|=============|======|=============================================== 15 | // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release 16 | // 0.56| 20 May 2002 | L.H. | No change 17 | // 0.57| 27 May 2002 | L.H. | No change 18 | //########################################################################### 19 | 20 | #ifndef DSP28_XINTRUPT_H 21 | #define DSP28_XINTRUPT_H 22 | 23 | //--------------------------------------------------------------------------- 24 | 25 | struct XINTCR_BITS { 26 | Uint16 ENABLE:1; // 0 enable/disable 27 | Uint16 rsvd1:1; // 1 reserved 28 | Uint16 POLARITY:1; // 2 pos/neg triggered 29 | Uint16 rsvd2:12; // 15:3 reserved 30 | }; 31 | 32 | union XINTCR_REG { 33 | Uint16 all; 34 | struct XINTCR_BITS bit; 35 | }; 36 | 37 | struct XNMICR_BITS { 38 | Uint16 ENABLE:1; // 0 enable/disable 39 | Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to INT13 40 | Uint16 POLARITY:1; // 2 pos/neg triggered 41 | Uint16 rsvd2:12; // 15:3 reserved 42 | }; 43 | 44 | union XNMICR_REG { 45 | Uint16 all; 46 | struct XNMICR_BITS bit; 47 | }; 48 | 49 | 50 | 51 | 52 | //--------------------------------------------------------------------------- 53 | // External Interrupt Register File: 54 | // 55 | struct XINTRUPT_REGS { 56 | union XINTCR_REG XINT1CR; 57 | union XINTCR_REG XINT2CR; 58 | Uint16 rsvd1[5]; 59 | union XNMICR_REG XNMICR; 60 | Uint16 XINT1CTR; 61 | Uint16 XINT2CTR; 62 | Uint16 rsvd[5]; 63 | Uint16 XNMICTR; 64 | }; 65 | 66 | //--------------------------------------------------------------------------- 67 | // External Interrupt References & Function Declarations: 68 | // 69 | extern volatile struct XINTRUPT_REGS XIntruptRegs; 70 | 71 | #endif // end of DSP28_XINTF_H definition 72 | 73 | //=========================================================================== 74 | // No more. 75 | //=========================================================================== 76 | -------------------------------------------------------------------------------- /src/DSP28_Xintf.h: -------------------------------------------------------------------------------- 1 | // 2 | // TMDX ALPHA RELEASE 3 | // Intended for product evaluation purposes 4 | // 5 | //########################################################################### 6 | // 7 | // FILE: DSP28_Xintf.h 8 | // 9 | // TITLE: DSP28 Device External Interface Register Definitions. 10 | // 11 | //########################################################################### 12 | // 13 | // Ver | dd mmm yyyy | Who | Description of changes 14 | // =====|=============|======|=============================================== 15 | // 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release 16 | // 0.56| 20 May 2002 | L.H. | No change 17 | // 0.57| 27 May 2002 | L.H. | No change 18 | //########################################################################### 19 | 20 | #ifndef DSP28_XINTF_H 21 | #define DSP28_XINTF_H 22 | 23 | 24 | // XINTF timing register bit definitions: 25 | struct XTIMING_BITS { // bits description 26 | Uint16 XWRTRAIL:2; // 1:0 Write access trail timing 27 | Uint16 XWRACTIVE:3; // 4:2 Write access active timing 28 | Uint16 XWRLEAD:2; // 6:5 Write access lead timing 29 | Uint16 XRDTRAIL:2; // 8:7 Read access trail timing 30 | Uint16 XRDACTIVE:3; // 11:9 Read access active timing 31 | Uint16 XRDLEAD:2; // 13:12 Read access lead timing 32 | Uint16 USEREADY:1; // 14 Extend access using HW waitstates 33 | Uint16 READYMODE:1; // 15 Ready mode 34 | Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b 35 | Uint16 rsvd1:4; // 21:18 reserved 36 | Uint16 X2TIMING:1; // 22 Double lead/active/trail timing 37 | Uint16 rsvd3:9; // 31:23 reserved 38 | }; 39 | 40 | union XTIMING_REG { 41 | Uint32 all; 42 | struct XTIMING_BITS bit; 43 | }; 44 | 45 | // XINTF control register bit definitions: 46 | struct XINTCNF2_BITS { // bits description 47 | Uint16 WRBUFF:2; // 1:0 Write buffer depth 48 | Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK 49 | Uint16 CLKOFF:1; // 3 Disable XCLKOUT 50 | Uint16 rsvd1:2; // 5:4 reserved 51 | Uint16 WLEVEL:2; // 7:6 Current level of the write buffer 52 | Uint16 MPNMC:1; // 8 Micro-processor/micro-computer mode 53 | Uint16 HOLD:1; // 9 Hold enable/disable 54 | Uint16 HOLDS:1; // 10 Current state of HOLDn input 55 | Uint16 HOLDAS:1; // 11 Current state of HOLDAn output 56 | Uint16 rsvd2:4; // 15:12 reserved 57 | Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK 58 | Uint16 rsvd3:13; // 31:19 reserved 59 | }; 60 | 61 | union XINTCNF2_REG { 62 | Uint32 all; 63 | struct XINTCNF2_BITS bit; 64 | }; 65 | 66 | // XINTF bank switching register bit definitions: 67 | struct XBANK_BITS { // bits description 68 | Uint16 BANK:2; // 2:0 Zone for which banking is enabled 69 | Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add 70 | Uint16 rsvd:10; // 15:6 reserved 71 | }; 72 | 73 | union XBANK_REG { 74 | Uint16 all; 75 | struct XBANK_BITS bit; 76 | }; 77 | 78 | 79 | //--------------------------------------------------------------------------- 80 | // XINTF Register File: 81 | // 82 | struct XINTF_REGS { 83 | union XTIMING_REG XTIMING0; 84 | union XTIMING_REG XTIMING1; 85 | union XTIMING_REG XTIMING2; 86 | Uint32 rsvd1[3]; 87 | union XTIMING_REG XTIMING6; 88 | union XTIMING_REG XTIMING7; 89 | Uint32 rsvd2[2]; 90 | union XINTCNF2_REG XINTCNF2; 91 | Uint32 rsvd3; 92 | union XBANK_REG XBANK; 93 | Uint16 rsvd4; 94 | Uint16 XREVISION; 95 | Uint16 rsvd5[5]; 96 | }; 97 | 98 | //--------------------------------------------------------------------------- 99 | // XINTF External References & Function Declarations: 100 | // 101 | extern volatile struct XINTF_REGS XintfRegs; 102 | 103 | #endif // end of DSP28_XINTF_H definition 104 | 105 | //=========================================================================== 106 | // No more. 107 | //=========================================================================== 108 | -------------------------------------------------------------------------------- /src/F2812.cmd: -------------------------------------------------------------------------------- 1 | /* 2 | //########################################################################### 3 | // 4 | // FILE: F2812.cmd 5 | // 6 | // TITLE: Linker Command File For F2812 Device 7 | // 8 | //########################################################################### 9 | // 10 | // Ver | dd mmm yyyy | Who | Description of changes 11 | // =====|=============|======|=============================================== 12 | // 1.00| 11 Sep 2003 | L.H | Changes since previous version (v.58 Alpha) 13 | // | | | Removed .bss, .const and .sysmem 14 | // | | | These are for a small memory model. All examples 15 | // | | | use the large model. 16 | // | | | Added ECANA_LAM ECANA_MOTO and ECANA_MOTS memory 17 | // | | | blocks. Also allocated the register files 18 | // | | | to these memory blocks. 19 | // | | | Added CSM Password locations to Page 0 20 | // | | | in order to program new passwords 21 | // | | | Moved peripheral register files to DSP28_Headers_BIOS.cmd 22 | // | | | and DSP28_Headers_nonBIOS.cmd 23 | // | | | Added CSM_RSVD memory section in FLASHA - this region 24 | // | | | should be programmed with all 0x0000 when using the CSM 25 | //########################################################################### 26 | */ 27 | 28 | /* ====================================================== 29 | // For Code Composer Studio V2.2 and later 30 | // --------------------------------------- 31 | // In addition to this memory linker command file, 32 | // add the header linker command file directly to the project. 33 | // The header linker command file is required to link the 34 | // peripheral structures to the proper locations within 35 | // the memory map. 36 | // 37 | // The header linker files are found in \DSP281x_Headers\cmd 38 | // 39 | // For BIOS applications add: DSP281x_Headers_nonBIOS.cmd 40 | // For nonBIOS applications add: DSP281x_Headers_nonBIOS.cmd 41 | ========================================================= */ 42 | 43 | /* ====================================================== 44 | // For Code Composer Studio prior to V2.2 45 | // -------------------------------------- 46 | // 1) Use one of the following -l statements to include the 47 | // header linker command file in the project. The header linker 48 | // file is required to link the peripheral structures to the proper 49 | // locations within the memory map */ 50 | 51 | /* Uncomment this line to include file only for non-BIOS applications */ 52 | /* -l DSP281x_Headers_nonBIOS.cmd */ 53 | 54 | /* Uncomment this line to include file only for BIOS applications */ 55 | /* -l DSP281x_Headers_BIOS.cmd */ 56 | 57 | /* 2) In your project add the path to \DSP281x_headers\cmd to the 58 | library search path under project->build options, linker tab, 59 | library search path (-i). 60 | /*========================================================= */ 61 | 62 | /* Define the memory block start/length for the F2812 63 | PAGE 0 will be used to organize program sections 64 | PAGE 1 will be used to organize data sections 65 | 66 | Notes: 67 | Memory blocks on F2812 are uniform (ie same 68 | physical memory) in both PAGE 0 and PAGE 1. 69 | That is the same memory region should not be 70 | defined for both PAGE 0 and PAGE 1. 71 | Doing so will result in corruption of program 72 | and/or data. 73 | */ 74 | 75 | MEMORY 76 | { 77 | PAGE 0: /* Program Memory */ 78 | /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ 79 | 80 | ZONE0 : origin = 0x002000, length = 0x002000 /* XINTF zone 0 */ 81 | ZONE1 : origin = 0x004000, length = 0x002000 /* XINTF zone 1 */ 82 | RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ 83 | ZONE2 : origin = 0x080000, length = 0x080000 /* XINTF zone 2 */ 84 | ZONE6 : origin = 0x100000, length = 0x080000 /* XINTF zone 6 */ 85 | OTP : origin = 0x3D7800, length = 0x000800 /* on-chip OTP */ 86 | FLASHJ : origin = 0x3D8000, length = 0x002000 /* on-chip FLASH */ 87 | FLASHI : origin = 0x3DA000, length = 0x002000 /* on-chip FLASH */ 88 | FLASHH : origin = 0x3DC000, length = 0x004000 /* on-chip FLASH */ 89 | FLASHG : origin = 0x3E0000, length = 0x004000 /* on-chip FLASH */ 90 | FLASHF : origin = 0x3E4000, length = 0x004000 /* on-chip FLASH */ 91 | FLASHE : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */ 92 | FLASHD : origin = 0x3EC000, length = 0x004000 /* on-chip FLASH */ 93 | FLASHC : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */ 94 | FLASHA : origin = 0x3F4001, length = 0x002F80 /* on-chip FLASH */ 95 | CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ 96 | BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ 97 | CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ 98 | 99 | /* ZONE7 : origin = 0x3FC000, length = 0x003FC0 /* XINTF zone 7 available if MP/MCn=1 */ 100 | ROM : origin = 0x3FF000, length = 0x000FC0 /* Boot ROM available if MP/MCn=0 */ 101 | RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM (MP/MCn=0) or XINTF zone 7 (MP/MCn=1) */ 102 | VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM (MP/MCn=0) or XINTF zone 7 (MP/MCn=1) */ 103 | 104 | PAGE 1 : /* Data Memory */ 105 | /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ 106 | /* Registers remain on PAGE1 */ 107 | 108 | RAMM0 : origin = 0x000000, length = 0x000400 /* on-chip RAM block M0 */ 109 | RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ 110 | RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ 111 | FLASHB : origin = 0x3F4000, length = 0x002000 /* on-chip FLASH */ 112 | RAMH0 : origin = 0x3F8000, length = 0x002000 /* on-chip RAM block H0 */ 113 | } 114 | 115 | /* Allocate sections to memory blocks. 116 | Note: 117 | codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 118 | execution when booting to flash 119 | ramfuncs user defined section to store functions that will be copied from Flash into RAM 120 | */ 121 | 122 | SECTIONS 123 | { 124 | 125 | /* Allocate program areas: */ 126 | .cinit : > FLASHA PAGE = 0 127 | .pinit : > FLASHA, PAGE = 0 128 | .text : > FLASHA PAGE = 0 129 | .codestart : > BEGIN PAGE = 0 130 | ramfuncs : LOAD = FLASHD, 131 | RUN = RAML0, 132 | LOAD_START(_RamfuncsLoadStart), 133 | LOAD_END(_RamfuncsLoadEnd), 134 | RUN_START(_RamfuncsRunStart), 135 | PAGE = 0 136 | 137 | csmpasswds : > CSM_PWL PAGE = 0 138 | csm_rsvd : > CSM_RSVD PAGE = 0 139 | 140 | /* Allocate uninitalized data sections: */ 141 | .stack : > RAMM0 PAGE = 1 142 | .ebss : > RAML1 PAGE = 1 143 | .esysmem : > RAMH0 PAGE = 1 144 | 145 | /* Initalized sections go in Flash */ 146 | /* For SDFlash to program these, they must be allocated to page 0 */ 147 | .econst : > FLASHA PAGE = 0 148 | .switch : > FLASHA PAGE = 0 149 | 150 | /* Allocate IQ math areas: */ 151 | IQmath : > FLASHC PAGE = 0 /* Math Code */ 152 | IQmathTables : > ROM PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */ 153 | 154 | /* .reset is a standard section used by the compiler. It contains the */ 155 | /* the address of the start of _c_int00 for C Code. /* 156 | /* When using the boot ROM this section and the CPU vector */ 157 | /* table is not needed. Thus the default type is set here to */ 158 | /* DSECT */ 159 | .reset : > RESET, PAGE = 0, TYPE = DSECT 160 | vectors : > VECTORS PAGE = 0, TYPE = DSECT 161 | 162 | } 163 | -------------------------------------------------------------------------------- /src/F2812_EzDSP_RAM_lnk.cmd: -------------------------------------------------------------------------------- 1 | /* 2 | //########################################################################### 3 | // 4 | // FILE: F2812_EzDSP_RAM_lnk.cmd 5 | // 6 | // TITLE: Linker Command File For F2812 eZdsp examples that run out of RAM 7 | // This linker file assumes the user is booting up in Jump to H0 mode 8 | // 9 | //########################################################################### 10 | // 11 | // Ver | dd mmm yyyy | Who | Description of changes 12 | // =====|=============|======|=============================================== 13 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 14 | // | | | Added BEGIN section to the start of H0 15 | // | | | Removed .bss, .const and .sysmem 16 | // | | | These are for a small memory model. All examples 17 | // | | | use the large model. 18 | // | | | Added .esysmem section 19 | // | | | Changed ramfuncs section to load and run from RAM 20 | // | | | (previously this was type DSECT) 21 | // | | | Moved peripheral register files to DSP28_Headers_BIOS.cmd 22 | // | | | and DSP28_Headers_nonBIOS.cmd 23 | // | | | Added CSM_RSVD memory section in FLASHA - this region 24 | // | | | should be programmed with all 0x0000 when using the CSM 25 | // -----|-------------|------|----------------------------------------------- 26 | //########################################################################### 27 | */ 28 | 29 | /* ====================================================== 30 | // For Code Composer Studio V2.2 and later 31 | // --------------------------------------- 32 | // In addition to this memory linker command file, 33 | // add the header linker command file directly to the project. 34 | // The header linker command file is required to link the 35 | // peripheral structures to the proper locations within 36 | // the memory map. 37 | // 38 | // The header linker files are found in \DSP281x_Headers\cmd 39 | // 40 | // For BIOS applications add: DSP281x_Headers_nonBIOS.cmd 41 | // For nonBIOS applications add: DSP281x_Headers_nonBIOS.cmd 42 | ========================================================= */ 43 | 44 | /* ====================================================== 45 | // For Code Composer Studio prior to V2.2 46 | // -------------------------------------- 47 | // 1) Use one of the following -l statements to include the 48 | // header linker command file in the project. The header linker 49 | // file is required to link the peripheral structures to the proper 50 | // locations within the memory map */ 51 | 52 | /* Uncomment this line to include file only for non-BIOS applications */ 53 | /* -l DSP281x_Headers_nonBIOS.cmd */ 54 | 55 | /* Uncomment this line to include file only for BIOS applications */ 56 | /* -l DSP281x_Headers_BIOS.cmd */ 57 | 58 | /* 2) In your project add the path to \DSP281x_headers\cmd to the 59 | library search path under project->build options, linker tab, 60 | library search path (-i). 61 | /*========================================================= */ 62 | 63 | 64 | 65 | MEMORY 66 | { 67 | PAGE 0 : 68 | /* For this example, H0 is split between PAGE 0 and PAGE 1 */ 69 | /* BEGIN is used for the "boot to HO" bootloader mode */ 70 | /* RESET is loaded with the reset vector only if */ 71 | /* the boot is from XINTF Zone 7. Otherwise reset vector */ 72 | /* is fetched from boot ROM. See .reset section below */ 73 | 74 | RAMM0 : origin = 0x000000, length = 0x000400 75 | BEGIN : origin = 0x3F8000, length = 0x000002 76 | PRAMH0 : origin = 0x3F8002, length = 0x001FFE 77 | RESET : origin = 0x3FFFC0, length = 0x000002 78 | 79 | 80 | 81 | PAGE 1 : 82 | 83 | /* For this example, H0 is split between PAGE 0 and PAGE 1 */ 84 | 85 | RAMM1 : origin = 0x000400, length = 0x000400 86 | DRAMH0 : origin = 0x008000, length = 0x002000 87 | } 88 | 89 | 90 | SECTIONS 91 | { 92 | /* Setup for "boot to H0" mode: 93 | The codestart section (found in DSP28_CodeStartBranch.asm) 94 | re-directs execution to the start of user code. 95 | Place this section at the start of H0 */ 96 | 97 | codestart : > BEGIN, PAGE = 0 98 | ramfuncs : > PRAMH0 PAGE = 0 99 | .text : > PRAMH0, PAGE = 0 100 | .cinit : > PRAMH0, PAGE = 0 101 | .pinit : > PRAMH0, PAGE = 0 102 | .switch : > RAMM0, PAGE = 0 103 | .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ 104 | 105 | .stack : > RAMM1, PAGE = 1 106 | .ebss : > DRAMH0, PAGE = 1 107 | .econst : > DRAMH0, PAGE = 1 108 | .esysmem : > DRAMH0, PAGE = 1 109 | 110 | 111 | } 112 | -------------------------------------------------------------------------------- /src/Table.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/natsu1211/F2812_PMSM_SVPWM_PI/e61f8ed2da756a8a6a791fd4440c8b509083bb9c/src/Table.c -------------------------------------------------------------------------------- /src/display.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/natsu1211/F2812_PMSM_SVPWM_PI/e61f8ed2da756a8a6a791fd4440c8b509083bb9c/src/display.c -------------------------------------------------------------------------------- /src/main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/natsu1211/F2812_PMSM_SVPWM_PI/e61f8ed2da756a8a6a791fd4440c8b509083bb9c/src/main.c -------------------------------------------------------------------------------- /src/pi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/natsu1211/F2812_PMSM_SVPWM_PI/e61f8ed2da756a8a6a791fd4440c8b509083bb9c/src/pi.h --------------------------------------------------------------------------------