├── Pipelined Datapath.pdf ├── LeftShift.v ├── SignExtend.v ├── JumpConcat.v ├── DFF.v ├── Gates.v ├── Reg32.v ├── ProgramCounter.v ├── HazardDetectionUnit.v ├── IF_ID.v ├── ALUController.v ├── Mux5bit2to1.v ├── MEM_WB.v ├── ID_EX.v ├── EX_MEM.v ├── ALU.v ├── Mux.v ├── README.md ├── RegFile.v ├── MainController.v ├── DataForwardingUnit.v ├── Mux32.v ├── RegFile32.v ├── Decoder.v ├── DataMemory32.v ├── InstructionMemory32.v ├── Adder.v └── LICENSE /Pipelined Datapath.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/neelkshah/MIPS-Processor/HEAD/Pipelined Datapath.pdf -------------------------------------------------------------------------------- /LeftShift.v: -------------------------------------------------------------------------------- 1 | module LeftShift(out, in); 2 | input [31:0] in; 3 | output [31:0] out; 4 | assign out = {in[29:0], 1'b0, 1'b0}; 5 | endmodule -------------------------------------------------------------------------------- /SignExtend.v: -------------------------------------------------------------------------------- 1 | module SignExtend(out, in); 2 | input [15:0] in; 3 | output [31:0] out; 4 | assign out = {{16{in[15]}}, in}; 5 | endmodule -------------------------------------------------------------------------------- /JumpConcat.v: -------------------------------------------------------------------------------- 1 | module JumpConcat(out, Jump, PC); 2 | input [31:0] Jump, PC; 3 | output [31:0] out; 4 | assign {out} = {{PC[31:28]}, {Jump[27:0]}}; 5 | endmodule -------------------------------------------------------------------------------- /DFF.v: -------------------------------------------------------------------------------- 1 | module dff_async_clear(q, d, clk, reset); 2 | input d, reset, clk; 3 | output q; 4 | reg q; 5 | 6 | always @ (posedge reset or negedge clk) 7 | begin 8 | if (!reset) q <= 1'b0; 9 | else q <= d; 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /Gates.v: -------------------------------------------------------------------------------- 1 | module bit32And (out, in1, in2); 2 | input [31:0] in1, in2; 3 | output [31:0] out; 4 | 5 | assign {out} = in1 & in2; 6 | 7 | endmodule 8 | 9 | module bit32Or (out, in1, in2); 10 | input [31:0] in1, in2; 11 | output [31:0] out; 12 | 13 | assign {out} = in1 | in2; 14 | 15 | endmodule -------------------------------------------------------------------------------- /Reg32.v: -------------------------------------------------------------------------------- 1 | `include "DFF.v" 2 | 3 | module reg_32bit(q, d, clk, reset); 4 | input [31:0] d; 5 | input reset, clk; 6 | output [31:0] q; 7 | genvar j; 8 | 9 | generate for (j = 0; j < 32; j = j + 1) begin: reg_loop 10 | dff_async_clear d(q[j], d[j], clk, reset); 11 | end 12 | endgenerate 13 | 14 | endmodule -------------------------------------------------------------------------------- /ProgramCounter.v: -------------------------------------------------------------------------------- 1 | `include "DFF.v" 2 | 3 | module ProgamCounter(out, in, clk, reset); 4 | input [31:0] in; 5 | input reset, clk; 6 | output [31:0] out; 7 | genvar j; 8 | 9 | generate for (j = 0; j < 32; j = j + 1) begin: reg_loop 10 | dff_async_clear d(out[j], in[j], clk, reset); 11 | end 12 | endgenerate 13 | 14 | endmodule -------------------------------------------------------------------------------- /HazardDetectionUnit.v: -------------------------------------------------------------------------------- 1 | module HazardDetectionUnit(stall, Rs1, Rt1, Rt2, MemRead2, clk); 2 | input clk, MemRead2; 3 | input [4:0] Rs1, Rt1, Rt2; 4 | output [2:0] stall; 5 | 6 | always (@ negedge clk) begin 7 | if(MemRead2 & ((Rt2 = Rs1) | (Rt2 = Rt1))) 8 | stall <= 3'b000; 9 | else 10 | stall <= 3'b111; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /IF_ID.v: -------------------------------------------------------------------------------- 1 | module IF_ID(new_content, instruction, newPC, clk, pwrite1); 2 | input pwrite1, clk; 3 | input [31:0] instruction, newPC; 4 | output [63:0] new_content; 5 | reg [63:0] next; 6 | always (@negedge clk) begin 7 | if(pwrite1) 8 | new_content <= {instruction, newPC}; 9 | else 10 | new_content <= 64'b0; 11 | 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /ALUController.v: -------------------------------------------------------------------------------- 1 | module ALUControlUnit (Operation, FuncField, ALUOp); 2 | input [5:0] FuncField; 3 | input [1:0] ALUOp; 4 | output [2:0] Operation; 5 | wire and_out, or_out; 6 | 7 | and a1(and_out, ALUOp[1], FuncField[1]); 8 | or o1(Operation[2], ALUOp[0], and_out); 9 | or o2(or_out, FuncField[0], FuncField[3]); 10 | and a2(Operation[0], ALUOp[1], or_out); 11 | nand(Operation[1], ALUOp[1], FuncField[2]); 12 | 13 | endmodule -------------------------------------------------------------------------------- /Mux5bit2to1.v: -------------------------------------------------------------------------------- 1 | module bit5_2to1mux(out, select, in1, in2); 2 | input [4:0] in1, in2; 3 | output [4:0] out; 4 | input select; 5 | genvar j; //this is the variable that is be used in the generate //block 6 | 7 | generate 8 | for (j = 0; j < 5; j = j + 1) begin: mux_loop //mux_loop is the name of the loop 9 | mux2to1 m1(out[j], select, in1[j], in2[j]); //mux2to1 is instantiated every time it is called 10 | end 11 | endgenerate 12 | 13 | endmodule -------------------------------------------------------------------------------- /MEM_WB.v: -------------------------------------------------------------------------------- 1 | module MEM_WB(new_content, control_signals, memory_data, ALU_Output, destination_reg, clk, pwrite4); 2 | input pwrite4, clk; 3 | input [31:0] ALU_Output, memory_data; 4 | input [4:0] destination_reg; 5 | input [1:0] control_signals; 6 | output [72:0] new_content; 7 | reg [72:0] new_content; 8 | 9 | always (@ negedge clk) begin 10 | if(pwrite4) 11 | new_content <= {destination_reg, ALU_Output, memory_data, control_signals}; 12 | else 13 | new_content <= 73'b0; 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /ID_EX.v: -------------------------------------------------------------------------------- 1 | module ID_EX(new_content, control_signals, newPC, lower26, read_Rs, read_Rt, sign_extended32, clk, pwrite2); 2 | input pwrite2, clk; 3 | input [31:0] sign_extended32, read_Rs, read_Rt, newPC; 4 | input [25:0] lower26; 5 | input [9:0] control_signals; 6 | output [163:0] new_content; 7 | reg [163:0] new_content; 8 | 9 | always (@ negedge clk) begin 10 | if(pwrite2) 11 | new_content <= {sign_extended32, read_Rs, read_Rt, lower26, newPC, control_signals}; 12 | else 13 | new_content <= 164'b0; 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /EX_MEM.v: -------------------------------------------------------------------------------- 1 | module EX_MEM(new_content, control_signals, branch_target, zero, ALU_Output, read_Rt, destination_reg, clk, pwrite3); 2 | input pwrite3, clk, zero; 3 | input [31:0] read_Rt, ALU_Output, branch_target; 4 | input [4:0] destination_reg; 5 | input [5:0] control_signals; 6 | output [106:0] new_content; 7 | reg [106:0] new_content; 8 | 9 | always (@negedge clk) begin 10 | if(pwrite3) 11 | new_content <= {destination_reg, read_Rt, ALU_Output, zero, branch_target, control_signals}; 12 | else 13 | new_content <= 107'b0; 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /ALU.v: -------------------------------------------------------------------------------- 1 | `include "Adder.v" 2 | `include "Mux.v" 3 | `include "Gates.v" 4 | 5 | module ALU(in1, in2, Binvert, Cin, Operation, Result, Carry); 6 | input [31:0] in1, in2; 7 | input [1:0] Operation; 8 | input Binvert, Cin; 9 | output [31:0] Result; 10 | output Carry; 11 | wire [31:0] not_in2, mux_out, and_out, or_out, sum; 12 | wire newc; 13 | 14 | mux2to1 m1(newc, Operation[1], Cin, 1'b1); 15 | bit32Not n1(not_in2, in2); 16 | bit32_2to1mux b0(mux_out, Binvert, in2, not_in2); 17 | thirtytwoBitFullAdder fa(sum, Carry, in1, mux_out, newc); 18 | bit32And a1(and_out, in1, mux_out); 19 | bit32Or o1(or_out, in1, mux_out); 20 | bit32_3to1mux b1(Result, Operation, and_out, or_out, sum); 21 | 22 | endmodule -------------------------------------------------------------------------------- /Mux.v: -------------------------------------------------------------------------------- 1 | module mux2to1(out, select, in1, in2); 2 | input in1, in2, select; 3 | output out; 4 | wire not_select, w1, w2; 5 | 6 | not (not_select, select); 7 | and (w1, select, in2); 8 | and (w2, not_select, in1); 9 | or(out, w1, w2); 10 | 11 | endmodule 12 | 13 | module mux3to1(out, select, in1, in2, in3); 14 | input in1, in2, in3; 15 | input [1:0] select; 16 | output out; 17 | wire w; 18 | 19 | mux2to1 m1(w, select[0], in1, in2); //in1 - 00; in2 - 01; in3 - 1x 20 | mux2to1 m2(out, select[1], w, in3); 21 | 22 | endmodule 23 | 24 | module bit32_3to1mux (out, select, in1, in2, in3); 25 | input [31:0] in1, in2, in3; 26 | input [1:0] select; 27 | output [31:0] out; 28 | genvar j; 29 | 30 | generate 31 | for(j = 0; j <32; j = j + 1) begin: mux_loop 32 | mux3to1 m1(out[j], select, in1[j], in2[j], in3[j]); 33 | end 34 | endgenerate 35 | 36 | endmodule -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Verilog code for a 32-bit pipelined MIPS processor. 2 | 3 | Datapath diagram with control signals is included in PDF format. 4 | 5 | Combination of gate-level, dataflow and behavioural modelling. 6 | 7 | Remarks: 8 | * Instruction Memory for 32 32-bit MIPS instructions. 9 | * 32 32-bit Data Memory locations. 10 | * Instruction Memory consisting of arithmetic, logical, branch, jump, and memory-access instructions. Immediate arguments and argument registers are hard-coded. 11 | * TRAP destination is generally OS-specific, and has been left to zero here. 12 | * 5-stage pipelining; stages are: 13 | - Instruction Fetch (IF) 14 | - Instruction Decode (ID) 15 | - Execute (EX) 16 | - Memory Access (MEM) 17 | - Writeback (WB) 18 | * *Data Forwarding Unit* to partially resolve hazards in R-type instructions. 19 | * *Hazard Detection Unit* to insert stalls (nop cycles) wherever required. 20 | -------------------------------------------------------------------------------- /RegFile.v: -------------------------------------------------------------------------------- 1 | module RegFile(clk, reset, ReadReg1, ReadReg2, WriteData, WriteReg, RegWrite, ReadData1, ReadData2); 2 | input clk, reset, RegWrite; 3 | input [31:0] WriteData; 4 | input [1:0] WriteReg, ReadReg1, ReadReg2; 5 | output [31:0] ReadData1, ReadData2; 6 | wire [3:0] decw; 7 | wire [3:0] andout; 8 | wire [31:0] q0, q1, q2, q3; 9 | genvar j; 10 | 11 | bit1_2to4decoder dec(decw, WriteReg[0], WriteReg[1]); 12 | generate 13 | for (j = 0; j < 4; j = j + 1) begin: reg_loop 14 | bit1_3to1and a1(andout[j], clk, RegWrite, decw[j]); 15 | end 16 | endgenerate 17 | 18 | reg_32bit reg1(q0, WriteData, andout[0], reset); 19 | reg_32bit reg2(q1, WriteData, andout[1], reset); 20 | reg_32bit reg3(q2, WriteData, andout[2], reset); 21 | reg_32bit reg4(q3, WriteData, andout[3], reset); 22 | 23 | bit32_4to1mux mux1(ReadData1, ReadReg1, q0, q1, q2, q3); 24 | bit32_4to1mux mux2(ReadData2, ReadReg2, q0, q1, q2, q3); 25 | 26 | endmodule -------------------------------------------------------------------------------- /MainController.v: -------------------------------------------------------------------------------- 1 | module MainControlUnit (RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, Jump, ALUOp, Op); 2 | input [5:0] Op; 3 | output RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, Jump; 4 | output [1:0] ALUOp; 5 | wire Rformat, lw, sw, beq; 6 | 7 | assign Rformat = (~Op[0]) & (~Op[1]) & (~Op[2]) & (~Op[3]) & (~Op[4]) & (~Op[5]); 8 | assign lw = (Op[0]) & (Op[1]) & (~Op[2]) & (~Op[3]) & (~Op[4]) & (Op[5]); 9 | assign sw = (Op[0]) & (Op[1]) & (Op[2]) & (Op[3]) & (~Op[4]) & (Op[5]); 10 | assign beq = (~Op[0]) & (~Op[1]) & (Op[2]) & (~Op[3]) & (~Op[4]) & (~Op[5]); 11 | assign Jump = (~Op[0]) & (Op[1]) & (~Op[2]) & (~Op[3]) & (~Op[4]) & (~Op[5]); 12 | assign RegDst = Rformat; 13 | assign ALUSrc = lw | sw; 14 | assign MemtoReg = lw; 15 | assign RegWrite = Rformat | lw; 16 | assign MemRead = lw; 17 | assign MemWrite = sw; 18 | assign Branch = beq; 19 | assign ALUOp[0] = Rformat; 20 | assign ALUOp[1] = beq; 21 | 22 | endmodule -------------------------------------------------------------------------------- /DataForwardingUnit.v: -------------------------------------------------------------------------------- 1 | module DataForwardingUnit(forwardA, forwardB, Rs2, Rt2, destreg3, destreg4, RegWrite3, RegWrite4, clk); // Rs2 = ID_EX.Rs; Rt2 = ID_EX.Rt; destreg3 = EX_MEM.destination_reg; destreg4 = MEM_WB.destination_reg; RegWrite3 = EX_MEM.control_signals.RegWrite; RegWrite4 = MEM_WB.control_signals.RegWrite 2 | input RegWrite3, RegWrite4, clk; 3 | input [4:0] Rs2, Rt2, destreg3, destreg4; 4 | output [1:0] forwardA, forwardB; 5 | 6 | always (@ negedge clk) begin 7 | if(RegWrite3 & (destreg3 != 0) & (destreg3 = Rs2)) 8 | forwardA <= 2'b10; 9 | else if(RegWrite4 & (destreg4 != 0) & (destreg3 != Rs2) & (destreg4 = Rs2)) 10 | forwardA <= 2'b01; 11 | else 12 | forwardA <= 2'b00; 13 | end 14 | 15 | always (@ negedge clk) begin 16 | if(RegWrite3 & (destreg3 != 0) & (destreg3 = Rt2)) 17 | forwardB <= 2'b10; 18 | else if(RegWrite4 & (destreg4 != 0) & (destreg3 != Rt2) & (destreg4 = Rt2)) 19 | forwardB <= 2'b01; 20 | else 21 | forwardB <= 2'b00; 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /Mux32.v: -------------------------------------------------------------------------------- 1 | module bit32_32to1mux(out, in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16, in17, in18, in19, in20, in21, in22, in23, in24, in25, in26, in27, in28, in29, in30, in31, select); 2 | input [31:0] in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16, in17, in18, in19, in20, in21, in22, in23, in24, in25, in26, in27, in28, in29, in30, in31; 3 | output [31:0] out; 4 | input [4:0] select; 5 | wire [31:0] w [9:0]; 6 | 7 | bit32_4to1mux m1(w[0], select[1:0], in0, in1, in2, in3); 8 | bit32_4to1mux m2(w[1], select[1:0], in4, in5, in6, in7); 9 | bit32_4to1mux m3(w[2], select[1:0], in8, in9, in10, in11); 10 | bit32_4to1mux m4(w[3], select[1:0], in12, in13, in14, in15); 11 | bit32_4to1mux m5(w[4], select[1:0], in16, in17, in18, in19); 12 | bit32_4to1mux m6(w[5], select[1:0], in20, in21, in22, in23); 13 | bit32_4to1mux m7(w[6], select[1:0], in24, in25, in26, in27); 14 | bit32_4to1mux m8(w[7], select[1:0], in28, in29, in30, in31); 15 | bit32_4to1mux m9(w[8], select[3:2], w[0], w[1], w[2], w[3]); 16 | bit32_4to1mux m10(w[9], select[3:2], w[4], w[5], w[6], w[7]); 17 | bit32_2to1mux m11(out, select[4], w[8], w[9]); 18 | 19 | endmodule -------------------------------------------------------------------------------- /RegFile32.v: -------------------------------------------------------------------------------- 1 | `include "Reg32.v" 2 | `include "Decoder.v" 3 | `include "Mux32.v" 4 | 5 | module RegFile32(clk, reset, ReadReg1, ReadReg2, WriteData, WriteReg, RegWrite, ReadData1, ReadData2); 6 | input clk, reset, RegWrite; 7 | input [31:0] WriteData; 8 | input [4:0] WriteReg, ReadReg1, ReadReg2; 9 | output [31:0] ReadData1, ReadData2; 10 | wire [31:0] decw; 11 | wire [31:0] andout; 12 | wire [31:0][31:0] q; 13 | genvar j, n; 14 | 15 | fiveToThirtyTwoDecoder dec(decw, WriteReg); 16 | generate 17 | for (j = 0; j < 32; j = j + 1) begin: reg_loop 18 | bit1_3to1and a1(andout[j], clk, RegWrite, decw[j]); 19 | end 20 | endgenerate 21 | 22 | generate 23 | for (n = 0; n < 32; n = n + 1) begin: and_loop 24 | reg_32bit reg1(q[n], WriteData, andout[n], reset); 25 | end 26 | endgenerate 27 | 28 | bit32_32to1mux(ReadData1, q[0], q[1], q[3], q[4], q[5], q[6], q[7], q[8], q[9], q[10], q[11], q[12], q[13], q[14], q[15], q[16], q[17], q[18], q[19], q[20], q[21], q[22], q[23], q[24], q[25], q[26], q[27], q[28], q[29], q[30], q[31], ReadReg1); 29 | bit32_32to1mux(ReadData2, q[0], q[1], q[3], q[4], q[5], q[6], q[7], q[8], q[9], q[10], q[11], q[12], q[13], q[14], q[15], q[16], q[17], q[18], q[19], q[20], q[21], q[22], q[23], q[24], q[25], q[26], q[27], q[28], q[29], q[30], q[31], ReadReg2); 30 | 31 | endmodule -------------------------------------------------------------------------------- /Decoder.v: -------------------------------------------------------------------------------- 1 | module fiveToThirtyTwoDecoder(out, in); 2 | input [4:0] in; 3 | output [31:0] out; 4 | wire [4:0] w; 5 | 6 | not n1(w[0], in[0]); 7 | not n2(w[1], in[1]); 8 | not n3(w[2], in[2]); 9 | not n4(w[3], in[3]); 10 | not n5(w[4], in[4]); 11 | and a0(out[0], w[0], w[1], w[2], w[3], w[4]); 12 | and a0(out[1], in[0], w[1], w[2], w[3], w[4]); 13 | and a0(out[2], w[0], in[1], w[2], w[3], w[4]); 14 | and a0(out[3], in[0], in[1], w[2], w[3], w[4]); 15 | and a0(out[4], w[0], w[1], in[2], w[3], w[4]); 16 | and a0(out[5], in[0], w[1], in[2], w[3], w[4]); 17 | and a0(out[6], w[0], in[1], in[2], w[3], w[4]); 18 | and a0(out[7], in[0], in[1], in[2], w[3], w[4]); 19 | and a0(out[8], w[0], w[1], w[2], in[3], w[4]); 20 | and a0(out[9], in[0], w[1], w[2], in[3], w[4]); 21 | and a0(out[10], w[0], in[1], w[2], in[3], w[4]); 22 | and a0(out[11], in[0], in[1], w[2], in[3], w[4]); 23 | and a0(out[12], w[0], w[1], in[2], in[3], w[4]); 24 | and a0(out[13], in[0], w[1], in[2], in[3], w[4]); 25 | and a0(out[14], w[0], in[1], in[2], in[3], w[4]); 26 | and a0(out[15], in[0], in[1], in[2], in[3], w[4]); 27 | and a0(out[16], w[0], w[1], w[2], w[3], in[4]); 28 | and a0(out[17], in[0], w[1], w[2], w[3], in[4]); 29 | and a0(out[18], w[0], in[1], w[2], w[3], in[4]); 30 | and a0(out[19], in[0], in[1], w[2], w[3], in[4]); 31 | and a0(out[20], w[0], w[1], in[2], w[3], in[4]); 32 | and a0(out[21], in[0], w[1], in[2], w[3], in[4]); 33 | and a0(out[22], w[0], in[1], in[2], w[3], in[4]); 34 | and a0(out[23], in[0], in[1], in[2], w[3], in[4]); 35 | and a0(out[24], w[0], w[1], w[2], in[3], in[4]); 36 | and a0(out[25], in[0], w[1], w[2], in[3], in[4]); 37 | and a0(out[26], w[0], in[1], w[2], in[3], in[4]); 38 | and a0(out[27], in[0], in[1], w[2], in[3], in[4]); 39 | and a0(out[28], w[0], w[1], in[2], in[3], in[4]); 40 | and a0(out[29], in[0], w[1], in[2], in[3], in[4]); 41 | and a0(out[30], w[0], in[1], in[2], in[3], in[4]); 42 | and a0(out[31], in[0], in[1], in[2], in[3], in[4]); 43 | 44 | endmodule -------------------------------------------------------------------------------- /DataMemory32.v: -------------------------------------------------------------------------------- 1 | module DataMemory32(clk, MemRead, ReadAddress, ReadData, MemWrite, WriteAddress, WriteData); 2 | input MemRead, MemWrite, clk; 3 | input [31:0] ReadAddress, WriteAddress; 4 | input [31:0] WriteData; 5 | output reg [31:0] ReadData; 6 | reg [31:0] data [0:31]; 7 | integer raddr, waddr; 8 | initial 9 | begin 10 | data[0] = 32'b00000000000000000000000000000000; 11 | data[1] = 32'b00000000000000000000000000000000; 12 | data[2] = 32'b00000000000000000000000000000000; 13 | data[3] = 32'b00000000000000000000000000000000; 14 | data[4] = 32'b00000000000000000000000000000000; 15 | data[5] = 32'b00000000000000000000000000000000; 16 | data[6] = 32'b00000000000000000000000000000000; 17 | data[7] = 32'b00000000000000000000000000000000; 18 | data[8] = 32'b00000000000000000000000000000000; 19 | data[9] = 32'b00000000000000000000000000000000; 20 | data[10] = 32'b00000000000000000000000000000000; 21 | data[11] = 32'b00000000000000000000000000000000; 22 | data[12] = 32'b00000000000000000000000000000000; 23 | data[13] = 32'b00000000000000000000000000000000; 24 | data[14] = 32'b00000000000000000000000000000000; 25 | data[15] = 32'b00000000000000000000000000000000; 26 | data[16] = 32'b00000000000000000000000000000000; 27 | data[17] = 32'b00000000000000000000000000000000; 28 | data[18] = 32'b00000000000000000000000000000000; 29 | data[19] = 32'b00000000000000000000000000000000; 30 | data[20] = 32'b00000000000000000000000000000000; 31 | data[21] = 32'b00000000000000000000000000000000; 32 | data[22] = 32'b00000000000000000000000000000000; 33 | data[23] = 32'b00000000000000000000000000000000; 34 | data[24] = 32'b00000000000000000000000000000000; 35 | data[25] = 32'b00000000000000000000000000000000; 36 | data[26] = 32'b00000000000000000000000000000000; 37 | data[27] = 32'b00000000000000000000000000000000; 38 | data[28] = 32'b00000000000000000000000000000000; 39 | data[29] = 32'b00000000000000000000000000000000; 40 | data[30] = 32'b00000000000000000000000000000000; 41 | data[31] = 32'b00000000000000000000000000000000; 42 | end 43 | 44 | always @(posedge clk) begin 45 | raddr = ReadAddress; 46 | waddr = WriteAddress; 47 | if(MemRead) 48 | ReadData = data[raddr/4]; 49 | else if(MemWrite) 50 | data[waddr/4] = WriteData; 51 | end 52 | 53 | endmodule -------------------------------------------------------------------------------- /InstructionMemory32.v: -------------------------------------------------------------------------------- 1 | module InstructionMemory32(instruction, ProgramCounter, clk); 2 | input[31:0] ProgramCounter; 3 | input clk; 4 | output[31:0] instruction; 5 | reg [31:0] memory [0:31]; 6 | reg [31:0] instruction; 7 | integer addr; 8 | 9 | initial 10 | begin 11 | memory[0] = 32'b00000001000010010101000000100000; // add add $s2, $s0, $s1 $s2 = $s0 + $s1 12 | memory[1] = 32'b00000001000010010101000000100001; // addu addu $s2, $s0, $s1 $s2 = $s0 + $s1 13 | memory[2] = 32'b00100001000010010001100100100110; // addi addi $s1, 6438($s0) $s1 = $s0 + 6438 14 | memory[3] = 32'b00100101000010010001100100100110; // addiu addiu $s1, 6438($s0) $s1 = $s0 + 6438 15 | memory[4] = 32'b00000001000010010101000000100100; // and and $s2, $s0, $s1 $s2 = $s0 & $s1 16 | memory[5] = 32'b00110001000010010001100100100110; // andi andi $s1, 6438($s0) $s1 = $s0 + 6438 17 | memory[6] = 32'b00000001000010010101000000011010; // div div $s2, $s0, $s1 $s2 = $s0 / $s1 18 | memory[7] = 32'b00000001000010010101000000011011; // divu divu $s2, $s0, $s1 $s2 = $s0 / $s1 19 | memory[8] = 32'b00000001000010010101000000011000; // mult mult $s2, $s0, $s1 $s2 = $s0 * $s1 20 | memory[9] = 32'b00000001000010010101000000011001; // multu multu $s2, $s0, $s1 $s2 = $s0 * $s1 21 | memory[10] = 32'b00000001000010010101000000100111; // nor nor $s2, $s0, $s1 $s2 = ~($s0 | $s1) 22 | memory[11] = 32'b00000001000010010101000000100101; // or or $s2, $s0, $s1 $s2 = $s0 | $s1 23 | memory[12] = 32'b00110101000010010001100100100110; // ori ori $s1, 6438($s0) $s1 = $s0 | 6438 24 | memory[13] = 32'b00000001000010010101000000100010; // sub sub $s2, $s0, $s1 $s2 = $s0 - $s1 25 | memory[14] = 32'b00000001000010010101000000100011; // subu subu $s2, $s0, $s1 $s2 = $s0 - $s1 26 | memory[15] = 32'b00000001000010010101000000100110; // xor xor $s2, $s0, $s1 $s2 = $s0 ^ $s1 27 | memory[16] = 32'b00111001000010010001100100100110; // xori xori $s1, 6438($s0) $s1 = $s0 ^ 6438 28 | memory[17] = 32'b00000001000010010101000000101010; // slt slt $s2, $s0, $s1 $s2 = $s0 < $s1 29 | memory[18] = 32'b00000001000010010101000000101011; // sltu slt $s2, $s0, $s1 $s2 = $s0 < $s1 30 | memory[19] = 32'b00101001000010010001100100100110; // slti slti $s1, 6438($s0) $s1 = $s0 < 6438 31 | memory[20] = 32'b00101101000010010001100100100110; // sltiu sltiu $s1, 6438($s0) $s1 = $s0 < 6438 32 | memory[21] = 32'b00010001000010010001100100100110; // beq beq $s0, $s1, 6438 if($s0 == $s1) goto loc 4*6438 33 | memory[22] = 32'b00000101000010010001100100100110; // bne bne $s0, $s1, 6438 if($s0 != $s1) goto loc 4*6438 34 | memory[23] = 32'b00001000000000000001100100100110; // j j 6438 PC = PC + <<2 6438 35 | memory[24] = 32'b00000100000000000001100100100110; // jal jal 6438 $31 = PC; PC = PC + <<2 6438 36 | memory[25] = 32'b00000000000000000000000000001001; // jalr jalr $s0 $31 = PC; PC = $s0 37 | memory[26] = 32'b00000001000000000000000000001000; // jr jr $s0 PC = $s0 38 | memory[27] = 32'b10001101000010010001100100100110; // lw lw $s1, 6438($s0) $s1 = mem($s0 + 6438):4 39 | memory[28] = 32'b10101101000010010001100100100110; // sw sw $s1, 6438($s0) mem($s0 + 6438):4 = $s1 40 | memory[29] = 32'b01101000000000000000000000000000; // trap trap 41 | memory[30] = 32'b00000000000000000000000000000000; // nop 42 | memory[31] = 32'b00000000000000000000000000000000; // nop 43 | end 44 | 45 | always @(posedge clk) begin 46 | addr = ProgramCounter[31:0]; 47 | instruction = memory[addr/4]; 48 | end 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /Adder.v: -------------------------------------------------------------------------------- 1 | module halfAdder(sum,carry,in1,in2); 2 | input in1, in2; 3 | output sum, carry; 4 | 5 | xor x1(sum, in1, in2); 6 | and a1(carry, in1, in2); 7 | 8 | endmodule 9 | 10 | /*module testbench1; 11 | reg i1, i2; 12 | wire s, c; 13 | halfAdder ha1(s, c, i1, i2); 14 | initial 15 | begin 16 | $monitor($time, " input1 = %b, input2 = %b, Sum = %b, Carry = %b", i1, i2, s, c); 17 | #2 i1 = 1'b 0; i2 = 1'b 0; 18 | #2 i1 = 1'b 0; i2 = 1'b 1; 19 | #2 i1 = 1'b 1; i2 = 1'b 0; 20 | #2 i1 = 1'b 1; i2 = 1'b 1; 21 | end 22 | 23 | endmodule */ 24 | 25 | module oneBitFullAdder(sum, carry, in1, in2, cin); 26 | input in1, in2, cin; 27 | output sum, carry; 28 | wire s1, c1, c2; 29 | 30 | halfAdder ha1(s1, c1, in1, in2); 31 | halfAdder ha2(sum, c2, s1, cin); 32 | or o1(carry, c1, c2); 33 | 34 | endmodule 35 | 36 | /*module testbench2; 37 | reg in1, in2, cin; 38 | wire sum, carry; 39 | oneBitFullAdder fa1(sum, carry, in1, in2, cin); 40 | initial 41 | begin 42 | $monitor($time, " input1 = %b, input2 = %b, carryIn = %b, sum = %b, carry = %b", in1, in2, cin, sum, carry); 43 | #2 in1 = 1'b 0; in2 = 1'b 0; cin = 1'b 0; 44 | #2 in1 = 1'b 0; in2 = 1'b 1; cin = 1'b 0; 45 | #2 in1 = 1'b 1; in2 = 1'b 0; cin = 1'b 0; 46 | #2 in1 = 1'b 1; in2 = 1'b 1; cin = 1'b 0; 47 | #2 in1 = 1'b 0; in2 = 1'b 0; cin = 1'b 1; 48 | #2 in1 = 1'b 0; in2 = 1'b 1; cin = 1'b 1; 49 | #2 in1 = 1'b 1; in2 = 1'b 0; cin = 1'b 1; 50 | #2 in1 = 1'b 1; in2 = 1'b 1; cin = 1'b 1; 51 | end 52 | endmodule */ 53 | 54 | module fourBitFullAdder(sum, carry, in1, in2, cin); 55 | input [3:0] in1, in2; 56 | input cin; 57 | output [3:0] sum; 58 | output carry; 59 | wire c0, c1, c2; 60 | 61 | oneBitFullAdder obfa1(sum[0], c0, in1[0], in2[0], cin); 62 | oneBitFullAdder obfa2(sum[1], c1, in1[1], in2[1], c0); 63 | oneBitFullAdder obfa3(sum[2], c2, in1[2], in2[2], c1); 64 | oneBitFullAdder obfa4(sum[3], carry, in1[3], in2[3], c2); 65 | 66 | endmodule 67 | 68 | /*module testbench3; 69 | reg [3:0] in1, in2; 70 | reg cin; 71 | wire [3:0] sum; 72 | wire carry; 73 | fourBitFullAdder fbfa1(sum, carry, in1, in2, cin); 74 | initial 75 | begin 76 | $monitor($time, " input1 = %b, input2 = %b, carryIn = %b, sum = %b, carry = %b", in1, in2, cin, sum, carry); 77 | #2 in1 = 4'b 0000; in2 = 4'b 0000; cin = 1'b 0; 78 | #2 in1 = 4'b 0010; in2 = 4'b 0100; cin = 1'b 1; 79 | #2 in1 = 4'b 0000; in2 = 4'b 1111; cin = 1'b 0; 80 | #2 in1 = 4'b 1111; in2 = 4'b 0001; cin = 1'b 1; 81 | end 82 | 83 | endmodule */ 84 | 85 | module eightBitFullAdder(sum, carry, in1, in2, cin); 86 | input [7:0] in1, in2; 87 | input cin; 88 | output [7:0] sum; 89 | output carry; 90 | wire caux; 91 | 92 | fourBitFullAdder fbfa1(sum[3:0], caux, in1[3:0], in2[3:0], cin); 93 | fourBitFullAdder fbfa2(sum[7:4], carry, in1[7:4], in2[7:4], caux); 94 | 95 | endmodule 96 | 97 | /*module testbench4; 98 | reg [7:0] in1, in2; 99 | reg cin; 100 | wire [7:0] sum; 101 | wire carry; 102 | eightBitFullAdder ebfa1(sum, carry, in1, in2, cin); 103 | initial 104 | begin 105 | $monitor($time, " input1 = %b, input2 = %b, carryIn = %b, sum = %b, carry = %b", in1, in2, cin, sum, carry); 106 | #2 in1 = 8'b 00000000; in2 = 8'b 00000000; cin = 1'b 0; 107 | #2 in1 = 8'b 10101010; in2 = 8'b 01010101; cin = 1'b 1; 108 | #2 in1 = 8'b 11111111; in2 = 8'b 00000000; cin = 1'b 1; 109 | #2 in1 = 8'b 11111111; in2 = 8'b 11111111; cin = 1'b 1; 110 | end 111 | 112 | endmodule */ 113 | 114 | module thirtytwoBitFullAdder(sum, carry, in1, in2, cin); 115 | input [31:0] in1, in2; 116 | input cin; 117 | output [31:0] sum; 118 | output carry; 119 | wire caux1, caux2, caux3; 120 | 121 | eightBitFullAdder ebfa1(sum[7:0], caux1, in1[7:0], in2[7:0], cin); 122 | eightBitFullAdder ebfa2(sum[15:8], caux2, in1[15:8], in2[15:8], caux1); 123 | eightBitFullAdder ebfa3(sum[23:16], caux3, in1[23:16], in2[23:16], caux2); 124 | eightBitFullAdder ebfa4(sum[31:24], carry, in1[31:24], in2[31:24], caux3); 125 | 126 | endmodule -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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Use with the GNU Affero General Public License. 553 | 554 | Notwithstanding any other provision of this License, you have 555 | permission to link or combine any covered work with a work licensed 556 | under version 3 of the GNU Affero General Public License into a single 557 | combined work, and to convey the resulting work. The terms of this 558 | License will continue to apply to the part which is the covered work, 559 | but the special requirements of the GNU Affero General Public License, 560 | section 13, concerning interaction through a network will apply to the 561 | combination as such. 562 | 563 | 14. Revised Versions of this License. 564 | 565 | The Free Software Foundation may publish revised and/or new versions of 566 | the GNU General Public License from time to time. Such new versions will 567 | be similar in spirit to the present version, but may differ in detail to 568 | address new problems or concerns. 569 | 570 | Each version is given a distinguishing version number. If the 571 | Program specifies that a certain numbered version of the GNU General 572 | Public License "or any later version" applies to it, you have the 573 | option of following the terms and conditions either of that numbered 574 | version or of any later version published by the Free Software 575 | Foundation. If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT 593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY 594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, 595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM 597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF 598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 599 | 600 | 16. Limitation of Liability. 601 | 602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS 604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY 605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE 606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF 607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD 608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), 609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF 610 | SUCH DAMAGES. 611 | 612 | 17. Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | --------------------------------------------------------------------------------