├── docs ├── videos.txt ├── implementacion_i2c.txt ├── ADV7513.pdf ├── ADV7513_Programming_Guide_R0.pdf ├── ADV7513_Hardware_User's_Guide_R0.pdf └── HDMI-Enabled Designs Using the ADV7513.pptx ├── quartus ├── src │ ├── pll │ │ ├── pll_25_sim.f │ │ ├── pll_25_sim │ │ │ ├── cadence │ │ │ │ ├── hdl.var │ │ │ │ └── ncsim_setup.sh │ │ │ ├── synopsys │ │ │ │ ├── vcsmx │ │ │ │ │ ├── synopsys_sim.setup │ │ │ │ │ └── vcsmx_setup.sh │ │ │ │ └── vcs │ │ │ │ │ └── vcs_setup.sh │ │ │ ├── aldec │ │ │ │ └── rivierapro_setup.tcl │ │ │ ├── mentor │ │ │ │ └── msim_setup.tcl │ │ │ └── pll_25.vo │ │ ├── pll_25.spd │ │ ├── pll_25.cmp │ │ ├── pll_25 │ │ │ ├── pll_25_0002.qip │ │ │ └── pll_25_0002.v │ │ ├── pll_25.ppf │ │ ├── pll_25.sip │ │ ├── pll_25.bsf │ │ └── pll_25.v │ ├── vgaHdmi_sim │ │ ├── vgaHdmi_sim │ │ │ ├── compile │ │ │ │ ├── vgaHdmi_sim.epr │ │ │ │ ├── contents.lib~vgaHdmi_sim │ │ │ │ ├── sources.sth │ │ │ │ ├── vgaHdmi_sim.opt │ │ │ │ ├── vgaHdmi_sim.opv │ │ │ │ ├── vgaHdmi_sim.erf │ │ │ │ └── wave.ver │ │ │ ├── projlib.cfg │ │ │ ├── compilation.order │ │ │ ├── synthesis.order │ │ │ ├── src │ │ │ │ ├── wave.asdb │ │ │ │ └── TestBench │ │ │ │ │ ├── vgaHdmi_TB_runtest.do │ │ │ │ │ ├── temp.do │ │ │ │ │ ├── vgaHdmi_TB_settings.txt │ │ │ │ │ ├── wave.ver │ │ │ │ │ └── vgaHdmi_TB.v │ │ │ ├── vgaHdmi_sim.rlb │ │ │ ├── 0vgaHdmi_sim.mgf │ │ │ ├── 1vgaHdmi_sim.mgf │ │ │ ├── 3vgaHdmi_sim.mgf │ │ │ ├── vgaHdmi_sim_0.rep │ │ │ ├── stimulators.set │ │ │ ├── compile.cfg │ │ │ ├── vgaHdmi_sim.wsp │ │ │ ├── vgaHdmi_sim.adf │ │ │ ├── bde.set │ │ │ └── Edfmap.ini │ │ ├── library.cfg │ │ ├── vgaHdmi_sim.wsw │ │ └── vgaHdmi_sim.aws │ ├── i2c │ │ ├── I2C_WRITE_WDATA.v │ │ ├── I2C_Controller.v │ │ └── I2C_HDMI_Config.v │ ├── TopModule.v │ └── vgaHdmi.v ├── vgaHdmi.qws ├── vgaHdmi.sdc ├── vgaHdmi.qpf ├── vgaHdmi_PinBackup.csv ├── c5_pin_model_dump.txt └── vgaHdmi.qsf ├── .gitignore ├── LICENSE └── Readme.md /docs/videos.txt: -------------------------------------------------------------------------------- 1 | https://youtu.be/6IAkYpmA1DQ -------------------------------------------------------------------------------- /quartus/src/pll/pll_25_sim.f: -------------------------------------------------------------------------------- 1 | pll_25_sim/pll_25.vo 2 | -------------------------------------------------------------------------------- /quartus/src/pll/pll_25_sim/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /quartus/vgaHdmi.qws: -------------------------------------------------------------------------------- 1 | @(last_workspace -------------------------------------------------------------------------------- /docs/implementacion_i2c.txt: -------------------------------------------------------------------------------- 1 | https://github.com/joelagnel/i2c-master/blob/master/i2c_master.v -------------------------------------------------------------------------------- /docs/ADV7513.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nhasbun/de10nano_vgaHdmi_chip/HEAD/docs/ADV7513.pdf -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/compile/vgaHdmi_sim.epr: -------------------------------------------------------------------------------- 1 | "./src/TestBench/vgaHdmi_TB.v" 1 2 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/projlib.cfg: -------------------------------------------------------------------------------- 1 | vgaHdmi_sim = "./vgaHdmi_sim.LIB" 1497554556741 2 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/compilation.order: -------------------------------------------------------------------------------- 1 | .\..\..\vgaHdmi.v 2 | .\src\TestBench\vgaHdmi_TB.v 3 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/synthesis.order: -------------------------------------------------------------------------------- 1 | i<>.\..\..\vgaHdmi.v 2 | i<>.\src\TestBench\vgaHdmi_TB.v 3 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | */db 2 | */incremental_db 3 | */output_files 4 | */simulation 5 | *.sublime-project 6 | *.sublime-workspace 7 | *.bak 8 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/library.cfg: -------------------------------------------------------------------------------- 1 | $include = "$VSIMSALIBRARYCFG" 2 | vgaHdmi_sim = "./vgaHdmi_sim/vgaHdmi_sim.LIB" 1497554556784 3 | -------------------------------------------------------------------------------- /docs/ADV7513_Programming_Guide_R0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nhasbun/de10nano_vgaHdmi_chip/HEAD/docs/ADV7513_Programming_Guide_R0.pdf -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim.wsw: -------------------------------------------------------------------------------- 1 | [OPENDOC|Aldec.WaveFormASDB.7|.\vgaHdmi_sim\src\wave.asdb|] 2 | TemplateId=0 3 | ActiveDocument=1 4 | -------------------------------------------------------------------------------- /docs/ADV7513_Hardware_User's_Guide_R0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nhasbun/de10nano_vgaHdmi_chip/HEAD/docs/ADV7513_Hardware_User's_Guide_R0.pdf -------------------------------------------------------------------------------- /docs/HDMI-Enabled Designs Using the ADV7513.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nhasbun/de10nano_vgaHdmi_chip/HEAD/docs/HDMI-Enabled Designs Using the ADV7513.pptx -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/wave.asdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nhasbun/de10nano_vgaHdmi_chip/HEAD/quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/wave.asdb -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/vgaHdmi_sim.rlb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nhasbun/de10nano_vgaHdmi_chip/HEAD/quartus/src/vgaHdmi_sim/vgaHdmi_sim/vgaHdmi_sim.rlb -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/0vgaHdmi_sim.mgf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nhasbun/de10nano_vgaHdmi_chip/HEAD/quartus/src/vgaHdmi_sim/vgaHdmi_sim/0vgaHdmi_sim.mgf -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/1vgaHdmi_sim.mgf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nhasbun/de10nano_vgaHdmi_chip/HEAD/quartus/src/vgaHdmi_sim/vgaHdmi_sim/1vgaHdmi_sim.mgf -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/3vgaHdmi_sim.mgf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nhasbun/de10nano_vgaHdmi_chip/HEAD/quartus/src/vgaHdmi_sim/vgaHdmi_sim/3vgaHdmi_sim.mgf -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/vgaHdmi_sim_0.rep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nhasbun/de10nano_vgaHdmi_chip/HEAD/quartus/src/vgaHdmi_sim/vgaHdmi_sim/vgaHdmi_sim_0.rep -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/stimulators.set: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /quartus/vgaHdmi.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name "clk50" -period 20.000ns [get_ports clock50] 2 | create_clock -name "i2c_20k_clock" -period 50000.000ns [get_keepers *mI2C_CTRL_CLK] 3 | 4 | derive_pll_clocks 5 | derive_clock_uncertainty -------------------------------------------------------------------------------- /quartus/src/pll/pll_25.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim.aws: -------------------------------------------------------------------------------- 1 | [Version] 2 | Version=9.1 3 | [Designs] 4 | vgahdmi_sim=.\vgaHdmi_sim\vgaHdmi_sim.adf 5 | [Browser] 6 | sort=order 7 | mode=none 8 | [Order] 9 | order=1 10 | macro= 11 | [Expand] 12 | vgahdmi_sim=1 13 | -------------------------------------------------------------------------------- /quartus/src/pll/pll_25.cmp: -------------------------------------------------------------------------------- 1 | component pll_25 is 2 | port ( 3 | refclk : in std_logic := 'X'; -- clk 4 | rst : in std_logic := 'X'; -- reset 5 | outclk_0 : out std_logic; -- clk 6 | locked : out std_logic -- export 7 | ); 8 | end component pll_25; 9 | 10 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/compile/contents.lib~vgaHdmi_sim: -------------------------------------------------------------------------------- 1 | 1469 2 | ~M 0 "" 0 $root 3 | ~A 1 "" 0 $root 4 | ~M 1 "./../../vgaHdmi.v" 21 vgaHdmi 5 | ~A 1 "./../../vgaHdmi.v" 21 vgaHdmi 6 | ~M 3 "./src/TestBench/vgaHdmi_TB.v" 15 vgaHdmi_tb 7 | ~A 1 "./src/TestBench/vgaHdmi_TB.v" 15 vgaHdmi_tb 8 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/compile/sources.sth: -------------------------------------------------------------------------------- 1 | [Files List] 2 | D:\Aldec\Active-HDL 9.1\Vlib\std/src/standard.vhd=S 3 | d:\ownCloud\Ecografo\FPGA\pruebas\de10nano\vgaHdmi_chip\quartus\src\vgaHdmi.v=S 4 | d:\ownCloud\Ecografo\FPGA\pruebas\de10nano\vgaHdmi_chip\quartus\src\vgaHdmi_sim\vgaHdmi_sim/src/TestBench/vgaHdmi_TB.v=S 5 | -------------------------------------------------------------------------------- /quartus/src/pll/pll_25/pll_25_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_25_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET OFF -to "*pll_25_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_25_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/compile.cfg: -------------------------------------------------------------------------------- 1 | [View] 2 | Entity=vgaHdmi_tb 3 | Architecture= 4 | TopLevelType=3 5 | [file:.\..\..\vgaHdmi.v] 6 | Enabled=1 7 | [file:.\src\wave.asdb] 8 | Enabled=1 9 | [file:.\src\TestBench\vgaHdmi_TB.v] 10 | Enabled=1 11 | LIB= 12 | [file:.\src\TestBench\vgaHdmi_TB_runtest.do] 13 | Enabled=1 14 | [file:.\src\TestBench\temp.do] 15 | Enabled=1 16 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/compile/vgaHdmi_sim.opt: -------------------------------------------------------------------------------- 1 | -u "D:\Aldec\Active-HDL 9.1\bin/systf.dll" -v20 "D:\ownCloud\Ecografo\FPGA\pruebas\de10nano\vgaHdmi_chip\quartus\src\vgaHdmi_sim\vgaHdmi_sim\src\TestBench\vgaHdmi_TB.v" -cs -g 5 -r -li "D:\ownCloud\Ecografo\FPGA\pruebas\de10nano\vgaHdmi_chip\quartus\src\vgaHdmi_sim\vgaHdmi_sim\compile\vgaHdmi_sim.epr" -p "D:\ownCloud\Ecografo\FPGA\pruebas\de10nano\vgaHdmi_chip\quartus\src\vgaHdmi_sim\vgaHdmi_sim" -------------------------------------------------------------------------------- /quartus/src/pll/pll_25.ppf: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/compile/vgaHdmi_sim.opv: -------------------------------------------------------------------------------- 1 | -erf "D:\ownCloud\Ecografo\FPGA\pruebas\de10nano\vgaHdmi_chip\quartus\src\vgaHdmi_sim\vgaHdmi_sim\compile\vgaHdmi_sim.erf" -work vgaHdmi_sim -lc D:/ownCloud/Ecografo/FPGA/pruebas/de10nano/vgaHdmi_chip/quartus/src/vgaHdmi_sim/library.cfg -fl D:/ownCloud/Ecografo/FPGA/pruebas/de10nano/vgaHdmi_chip/quartus/src/vgaHdmi_sim/vgaHdmi_sim/projlib.cfg -o D:/ownCloud/Ecografo/FPGA/pruebas/de10nano/vgaHdmi_chip/quartus/src/vgaHdmi_sim/vgaHdmi_sim/compile -l "vgaHdmi_sim" -sve -O2 -------------------------------------------------------------------------------- /quartus/src/pll/pll_25.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll_25" -library "lib_pll_25" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll_25" -library "lib_pll_25" -name IP_TOOL_VERSION "17.0" 3 | set_global_assignment -entity "pll_25" -library "lib_pll_25" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_pll_25" -name SPD_FILE [file join $::quartus(sip_path) "pll_25.spd"] 5 | 6 | set_global_assignment -library "lib_pll_25" -name MISC_FILE [file join $::quartus(sip_path) "pll_25_sim/pll_25.vo"] 7 | -------------------------------------------------------------------------------- /quartus/src/pll/pll_25_sim/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | 2 | WORK > DEFAULT 3 | DEFAULT: ./libraries/work/ 4 | work: ./libraries/work/ 5 | altera_ver: ./libraries/altera_ver/ 6 | lpm_ver: ./libraries/lpm_ver/ 7 | sgate_ver: ./libraries/sgate_ver/ 8 | altera_mf_ver: ./libraries/altera_mf_ver/ 9 | altera_lnsim_ver: ./libraries/altera_lnsim_ver/ 10 | cyclonev_ver: ./libraries/cyclonev_ver/ 11 | cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/ 12 | cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/ 13 | LIBRARY_SCAN = TRUE 14 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/compile/vgaHdmi_sim.erf: -------------------------------------------------------------------------------- 1 | MESSAGE "Pass 1. Scanning modules hierarchy." 2 | MESSAGE_SP VCP2113 "Module \$root found in current working library." 3 | BEGINPROGRESS Compiling... 4 | UPDATEPROGRESS 35 5 | MESSAGE_SP VCP2113 "Module vgaHdmi found in current working library." 6 | MESSAGE "Pass 2. Processing instantiations." 7 | UPDATEPROGRESS 45 8 | MESSAGE "Pass 3. Processing behavioral statements." 9 | UPDATEPROGRESS 80 10 | MESSAGE "Running Optimizer." 11 | MESSAGE "ELB/DAG code generating." 12 | MESSAGE_SP VCP2113 "Module \$root found in current working library." 13 | UPDATEPROGRESS 86 14 | UPDATEPROGRESS 93 15 | UPDATEPROGRESS 100 16 | MESSAGE "Unit top modules: vgaHdmi_tb." 17 | MESSAGE "$root top modules: vgaHdmi_tb." 18 | ENDPROGRESS Compiling... 19 | SUCCESS "Compile success 0 Errors 0 Warnings Analysis time: 0[s]." 20 | MESSAGE "done" 21 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/TestBench/vgaHdmi_TB_runtest.do: -------------------------------------------------------------------------------- 1 | SetActiveLib -work 2 | #Compiling UUT module design files 3 | comp -include "$dsn\..\..\vgaHdmi.v" 4 | comp -include "$dsn\src\TestBench\vgaHdmi_TB.v" 5 | asim +access +r vgaHdmi_tb 6 | 7 | add wave -noreg -logic {/vgaHdmi_tb/clock} 8 | add wave -noreg -logic {/vgaHdmi_tb/clock50} 9 | add wave -noreg -logic {/vgaHdmi_tb/reset} 10 | add wave -noreg -color 255,4,255 -logic {/vgaHdmi_tb/hsync} 11 | add wave -noreg -color 255,4,255 -logic {/vgaHdmi_tb/vsync} 12 | add wave -noreg -color 255,255,0 -decimal -literal {/vgaHdmi_tb/UUT/pixelH} 13 | add wave -noreg -color 255,255,0 -decimal -literal {/vgaHdmi_tb/UUT/pixelV} 14 | add wave -noreg -logic {/vgaHdmi_tb/dataEnable} 15 | add wave -noreg -logic {/vgaHdmi_tb/vgaClock} 16 | add wave -noreg -decimal -literal {/vgaHdmi_tb/RGBchannel} 17 | 18 | run 10000.00 us 19 | 20 | #End simulation macro 21 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/vgaHdmi_sim.wsp: -------------------------------------------------------------------------------- 1 | [General] 2 | CurrentVersion=103 3 | [COMPILESTATUS|.\src\vgaHdmi.v] 4 | FileTimeLow=30598668 5 | Status=Compiled 6 | [COMPILESTATUS|.\src\TestBench\VGAhandler_TB.v] 7 | FileTimeLow=30598670 8 | Status=Compiled 9 | [COMPILESTATUS|.\src\TestBench\VGAhandler_TB_runtest.do] 10 | FileTimeLow=30598671 11 | Status=Modified 12 | [COMPILESTATUS|.\src\TestBench\temp.do] 13 | FileTimeLow=30599289 14 | Status=Modified 15 | [COMPILESTATUS|.\..\..\vgaHdmi.v] 16 | FileTimeLow=30599300 17 | Status=Compiled 18 | [CACHEDOC|Aldec.Project.Generic.7|.\vgaHdmi_sim\vgaHdmi_sim.adf|] 19 | Path=/vgaHdmi_tb 20 | [COMPILESTATUS|.\src\wave.asdb] 21 | FileTimeLow=30599303 22 | Status=Modified 23 | [COMPILESTATUS|.\src\TestBench\vgaHdmi_TB.v] 24 | FileTimeLow=30599303 25 | Status=Compiled 26 | [COMPILESTATUS|.\src\TestBench\vgaHdmi_TB_runtest.do] 27 | FileTimeLow=30599336 28 | Status=Modified 29 | [Gui config] 30 | RunFor=100 ns 31 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/TestBench/temp.do: -------------------------------------------------------------------------------- 1 | onerror { resume } 2 | transcript off 3 | add wave -noreg -logic {/vgaHdmi_tb/clock} 4 | add wave -noreg -logic {/vgaHdmi_tb/clock50} 5 | add wave -noreg -logic {/vgaHdmi_tb/reset} 6 | add wave -noreg -color 255,4,255 -logic {/vgaHdmi_tb/hsync} 7 | add wave -noreg -color 255,4,255 -logic {/vgaHdmi_tb/vsync} 8 | add wave -noreg -color 255,4,255 -logic {/vgaHdmi_tb/UUT/vsync_old} 9 | add wave -noreg -color 255,158,0 -logic {/vgaHdmi_tb/UUT/newFrame} 10 | add wave -noreg -color 255,255,0 -decimal -literal {/vgaHdmi_tb/UUT/pixelH} 11 | add wave -noreg -color 255,255,0 -decimal -literal {/vgaHdmi_tb/UUT/pixelV} 12 | add wave -noreg -logic {/vgaHdmi_tb/dataEnable} 13 | add wave -noreg -logic {/vgaHdmi_tb/vgaClock} 14 | add wave -noreg -decimal -literal {/vgaHdmi_tb/RGBchannel} 15 | add wave -noreg -color 255,128,0 -decimal -literal -signed2 {/vgaHdmi_tb/UUT/contador} 16 | cursor "Cursor 1" 7840.05us 17 | transcript on 18 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2017 Nicolas Hasbun 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Readme.md: -------------------------------------------------------------------------------- 1 | # ADV7513 HDMI Transmitter # 2 | 3 | This is a test for the **ADV7513** chip from Analog Devices which is pretty useful to make an easy compatible **HDMI 1.4** output starting with a common **VGA module**. 4 | 5 | It is tested on a **de10 nano** board which has the chip included. **Quartus Prime 17** project is included for an easy deployment of a first working video signal. The project includes: 6 | 7 | - Verilog HDL files 8 | - SDC TimeQuest files por timing analysis 9 | - Quartus Project files (pin assignment done, etc.) 10 | 11 | There is a folder included under **./src/** with simulations done on **Active HDL 9.1** for functional verification of vga module and sync signals. 12 | 13 | ## I2C Controller ## 14 | 15 | The chip needs to be configured via i2c on **every start** to work correctly. I re-used Verilog code included in some Terasic examples for this board to accomplish this. 16 | 17 | I found this to be the only tricky part for an smooth vga to hdmi implementation. 18 | 19 | ## Test ## 20 | 21 | Switches of **de10 nano** are being used to control output screen color. 22 | 23 | - SW0, Red 24 | - SW1, Green 25 | - SW2, Blue 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/src/TestBench/vgaHdmi_TB_settings.txt: -------------------------------------------------------------------------------- 1 | [SETTINGS] 2 | UUT_module%vgaHdmi% 3 | TB_module%vgaHdmi_tb% 4 | DSN_PATH%$dsn\src\TestBench% 5 | OUTPUT_DIRECTORY%d:\ownCloud\Ecografo\FPGA\pruebas\de10nano\vgaHdmi_chip\src\vgaHdmi_sim\vgaHdmi_sim\src\TestBench% 6 | STIMULUS%YES% 7 | VECTORS_FILE%d:\ownCloud\Ecografo\FPGA\pruebas\de10nano\vgaHdmi_chip\src\vgaHdmi_sim\vgaHdmi_sim\compile\wave.ver% 8 | AWF_FILE%d:\ownCloud\Ecografo\FPGA\pruebas\de10nano\vgaHdmi_chip\src\vgaHdmi_sim\vgaHdmi_sim\compile\wave.ver% 9 | TB_FILE%vgaHdmi_TB.v% 10 | MACRO_FILE%vgaHdmi_TB_runtest.do% 11 | UUT_module_FILE%% 12 | LIBRARY_NAME%vgaHdmi_sim% 13 | LIBRARY_TYPE%work% 14 | END_SIMULATION_TIME%100.00 ns% 15 | SIMULATION_TIME%% 16 | TestBench_TYPE%simple% 17 | ENABLE_FILE%none% 18 | RESULT_FILE%none% 19 | 20 | [GENERICS] 21 | 22 | [PORTS] 23 | clock%in%wire%YES%NOCLK% 24 | reset%in%wire%YES%NOCLK% 25 | hsync%out%reg%NO%NOCLK% 26 | vsync%out%reg%NO%NOCLK% 27 | pixelH%out%[9:0]reg%NO%NOCLK% 28 | pixelV%out%[9:0]reg%NO%NOCLK% 29 | dataEnable%out%reg%NO%NOCLK% 30 | 31 | [SDF] 32 | 33 | [INCLUDE] 34 | [Verilog_FILES] 35 | d:\ownCloud\Ecografo\FPGA\pruebas\de10nano\vgaHdmi_chip\src\vgaHdmi.v 36 | 37 | -------------------------------------------------------------------------------- /quartus/src/vgaHdmi_sim/vgaHdmi_sim/compile/wave.ver: -------------------------------------------------------------------------------- 1 | //************************************************************* 2 | //* This file is automatically generated Test Bench * 3 | //* template and can be used in Test Bench generator. * 4 | //* ACTIVE-HDL Testbench Generator ver. 3.5. * 5 | //* Copyright (C) ALDEC Inc. * 6 | //* * 7 | //* This file was generated on: 19:43:40, 15-06-2017 * 8 | //************************************************************* 9 | //Bellow are listed ports used in STIMULUS process, 10 | //Begin Comment 11 | //clock : in wire 12 | //reset : in wire 13 | //100.00 ns : END_SIMULATION_TIME 14 | //End Comment 15 | 16 | initial 17 | begin : STIMUL // begin of stimulus process 18 | //#