├── Images ├── dimensions.JPG ├── final_LEF_write.JPG ├── final_routing.JPG ├── final_routing_1.JPG ├── initial_bbox.JPG ├── initial_metal2.jpg ├── layout_vs_LEF.JPG ├── lef_write.JPG ├── legalization_issue.JPG ├── legalization_issue_1.jpg ├── no_synth.JPG ├── no_synth_1.JPG ├── openlane.flow.1.png ├── portA.JPG ├── portVGND.JPG ├── portVPWR.JPG ├── portY.JPG ├── port_class_use.JPG ├── port_class_use_1.JPG ├── std_cell_power_corrected.png └── std_cell_power_issue.png ├── LICENSE ├── README.md ├── extras ├── README.md ├── guides.txt ├── my_base.sdc ├── picorv32a.synthesis.v └── sta.conf ├── libs ├── nshort.lib ├── pshort.lib ├── sky130A.tech ├── sky130_fd_sc_hd__fast.lib ├── sky130_fd_sc_hd__slow.lib └── sky130_fd_sc_hd__typical.lib └── sky130_inv.mag /Images/dimensions.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nickson-jose/vsdstdcelldesign/HEAD/Images/dimensions.JPG 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