├── Images ├── dimensions.JPG ├── final_LEF_write.JPG ├── final_routing.JPG ├── final_routing_1.JPG ├── initial_bbox.JPG ├── initial_metal2.jpg ├── layout_vs_LEF.JPG ├── lef_write.JPG ├── legalization_issue.JPG ├── legalization_issue_1.jpg ├── no_synth.JPG ├── no_synth_1.JPG ├── openlane.flow.1.png ├── portA.JPG ├── portVGND.JPG ├── portVPWR.JPG ├── portY.JPG ├── port_class_use.JPG ├── port_class_use_1.JPG ├── std_cell_power_corrected.png └── std_cell_power_issue.png ├── LICENSE ├── README.md ├── extras ├── README.md ├── guides.txt ├── my_base.sdc ├── picorv32a.synthesis.v └── sta.conf ├── libs ├── nshort.lib ├── pshort.lib ├── sky130A.tech ├── sky130_fd_sc_hd__fast.lib ├── sky130_fd_sc_hd__slow.lib └── sky130_fd_sc_hd__typical.lib └── sky130_inv.mag /Images/dimensions.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nickson-jose/vsdstdcelldesign/9001395f7faad7d2a823d8ca6d3b997e1afdb8f5/Images/dimensions.JPG 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In addition, it also contains procedures on how to create a custom LEF file and plugging it into an openlane flow. 3 | 4 | # Table of Contents 5 | - [Introduction to Openlane flow.](#introduction-to-openlane-flow) 6 | - [Overview of Physical Design flow.](#overview-of-physical-design-flow) 7 | - [Build and invoke openlane.](#build-and-invoke-openlane) 8 | - [Introduction to LEF.](#introduction-to-lef) 9 | - [Standard cell design and characterization in openlane.](#standard-cell-design-and-characterization-in-openlane ) 10 | - [Objective.](#objective) 11 | - [About PicoRV32.](#about-picorv32) 12 | - [Standard cell layout design in Magic.](#standard-cell-layout-design-in-magic) 13 | - [Create port definition.](#create-port-definition) 14 | - [Set `port class` and `port use` attributes for a layout.](#set-port-class-and-port-use-attributes-for-a-layout) 15 | - [Defining LEF properties and extracting LEF file.](#defining-lef-properties-and-extracting-lef-file) 16 | - [Plugging custom LEF to openlane flow.](#plugging-custom-lef-to-openlane-flow) 17 | - [Observations.](#observations) 18 | - [Challenges.](#challenges) 19 | - [Future work.](#future-work) 20 | - [Limitations.](#limitations) 21 | - [Acknowledgements.](#acknowledgements) 22 | 23 | # Introduction to Openlane flow 24 | OpenLANE is a completely automated RTL to GDSII flow which embeds in it different opensource tools, namely, OpenROAD, Yosys, ABC, Magic etc., apart from many custom methodology scripts for design exploration and optimization. Openlane is built around Skywater 130nm process node and is capable of performing full ASIC implementation steps from RTL all the way down to GDSII. 25 | The flow-chart below gives a better picture of openlane flow as a whole (**Image Courtesy:** [efabless/openlane](https://github.com/efabless/openlane/blob/master/doc/openlane.flow.1.png)) 26 | 27 | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/openlane.flow.1.png?raw=true) 28 | 29 | # Overview of Physical Design flow 30 | Place and Route (PnR) is the core of any ASIC implementation and Openlane flow integrates into it several key open source tools which perform each of the respective stages of PnR. 31 | Below are the stages and the respective tools (in ( )) that are called by openlane for the functionalities as described: 32 | - Synthesis 33 | - Generating gate-level netlist ([yosys](https://github.com/YosysHQ/yosys)). 34 | - Performing cell mapping ([abc](https://github.com/YosysHQ/yosys)). 35 | - Performing pre-layout STA ([OpenSTA](https://github.com/The-OpenROAD-Project/OpenSTA)). 36 | - Floorplanning 37 | - Defining the core area for the macro as well as the cell sites and the tracks ([init_fp](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/init_fp)). 38 | - Placing the macro input and output ports ([ioplacer](https://github.com/The-OpenROAD-Project/ioPlacer/)). 39 | - Generating the power distribution network ([pdn](https://github.com/The-OpenROAD-Project/pdn/)). 40 | - Placement 41 | - Performing global placement ([RePLace](https://github.com/The-OpenROAD-Project/RePlAce)). 42 | - Perfroming detailed placement to legalize the globally placed components ([OpenDP](https://github.com/The-OpenROAD-Project/OpenDP)). 43 | - Clock Tree Synthesis (CTS) 44 | - Synthesizing the clock tree ([TritonCTS](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/TritonCTS)). 45 | - Routing 46 | - Performing global routing to generate a guide file for the detailed router ([FastRoute](https://github.com/The-OpenROAD-Project/FastRoute/tree/openroad)). 47 | - Performing detailed routing ([TritonRoute](https://github.com/The-OpenROAD-Project/TritonRoute)) 48 | - GDSII Generation 49 | - Streaming out the final GDSII layout file from the routed def ([Magic](https://github.com/RTimothyEdwards/magic)). 50 | 51 | # Build and Invoke openlane 52 | 53 | Detailed description on how to build and invoke openlane is given in this [link](https://github.com/njose939/openlane_build_script). 54 | 55 | # Introduction to LEF 56 | For a PnR tool to correctly place and route a block (a macro or a std. cell), it doesn't need to know entire layout information of the block; just the pin positions, PR boundary is sufficient. These minimal and abstracted information is provided to the tool by the Library Exchange Format (LEF) file. LEF file also serves the purpose of protecting intellectual property and is basically of two types: 57 | - Cell LEF - It's an abstract view of the cell and only gives information about PR boundary, pin position and metal layer information of the cell. 58 | - Technology LEF - It contains information about available metal layer, via information, DRCs of particular technology used by placer and router etc.. 59 | The below diagram highlights the difference between a layout and a LEF (**Image Courtesy:** Google): 60 | 61 | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/layout_vs_LEF.JPG?raw=true) 62 | 63 | # Standard cell design and characterization in openlane 64 | 65 | ## Objective 66 | 67 | The goal of the project is to design a single height standard cell and plug this custom cell into a more complex design and perform it's PnR in the openlane flow. The standard cell chosen is a basic CMOS inverter and the design into which it's plugged into is a pre-built [picorv32a](https://github.com/efabless/openlane/tree/master/designs/picorv32a) core. 68 | 69 | ## About PicoRV32 70 | 71 | PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32I, RV32IC, RV32IM, or RV32IMC core; where the suffixes stand for: 72 | 73 | - M - Multiply extension 74 | - I - Base Integer Instructions 75 | - C - Compressed Instructions 76 | 77 | PicoRV32 is free and open hardware licensed under the ISC license. All features and data-sheet related to picoRV32 core can be obtained [here.](https://www.efabless.com/design_catalog/ip_block/92) 78 | 79 | ## Standard cell layout design in Magic 80 | 81 | - The proposed inverter for the design is a single height standard cell, so the dimensions needs to be a multiple of the single height place site; which for sky130 node has a nomenclature of `unithd` with dimensions(in microns): 0.46 x 2.72 (width x height) for **sky130_fd_sc_hd** PDK variant. The magic tool is invoked with sky130 tech file as `magic -T sky130A.tech &` (the magic tech file (sky130A.tech) has also been included in this repo under `/libs` as reference). 82 | 83 | - Thus, the first step in magic layout tool is to create a bounding box with a width of 1.38 (3 x width(unithd)) and height of 2.72. This can be done by using command `property FIXED_BBOX {0 0 138 272}` in magic tkcon window. 84 | 85 | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/initial_bbox.JPG?raw=true) 86 | 87 | - This is followed by defining the ground and power segments (in metal 1), the respective contacts and finally the layout of the logic part. Same procedure can be followed for any standard cell layout. 88 | 89 | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/initial_metal2.jpg?raw=true) 90 | 91 | ### Note: 92 | The layout (also included as the part of this repo, viz., `sky130_inv.mag`) can be viewed in magic layout window as `magic -T sky130A.tech sky130_inv.mag &` 93 | 94 | ## Create port definition 95 | 96 | Once the layout is ready, the next step is extracting LEF file for the cell. However, certain properties and definitions need to be set to the pins of the cell which aid the placer and router tool. For LEF files, a cell that contains ports is written as a macro cell, and the ports are the declared PINs of the macro. Our objective is to extract LEF from a given layout (here of a simple CMOS inverter) in standard format. Defining port and setting correct class and use attributes to each port is the first step. 97 | The easiest way to define a port is through Magic Layout window and following are the steps: 98 | - In Magic Layout window, first source the .mag file for the design (here inverter). Then **Edit >> Text** which opens up a dialogue box. 99 | 100 | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/portA.JPG?raw=true) 101 | 102 | - For each layer (to be turned into port), make a box on that particular layer and input a label name along with a sticky label of the layer name with which the port needs to be associated. Ensure the Port enable checkbox is checked and default checkbox is unchecked as shown in the figure: 103 | 104 | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/portY.JPG?raw=true) 105 | 106 | In the above two figures, port A (input port) and port Y (output port) are taken from locali (local interconnect) layer. Also, the number in the textarea near enable checkbox defines the order in which the ports will be written in LEF file (0 being the first). 107 | 108 | - For power and ground layers, the definition could be same or different than the signal layer. Here, ground and power connectivity are taken from metal1 (Notice the sticky label) 109 | 110 | | VPWR | VGND | 111 | | --------------------------------------------------------------------------------------------| ------------- | 112 | | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/portVPWR.JPG?raw=true) | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/portVGND.JPG?raw=true) | 113 | 114 | ## Set port class and port use attributes for a layout 115 | 116 | Post port definition, the next step is setting **port class** and **port use** attributes. The "class" and "use" properties of the port have no internal meaning to magic but are used by the LEF and DEF format read and write routines, and match the LEF/DEF CLASS and USE properties for macro cell pins. Valid classes are: default, input, output, tristate, bidirectional, inout, feedthrough, and feedthru. Valid uses are: default, analog, signal, digital, power, ground, and clock. These attributes are set in tkcon window (after selecting each port on layout window. A keyboard shortcut would be repeatedly pressing `s` till that port gets highlighed) as: 117 | 118 | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/port_class_use_1.JPG?raw=true) 119 | 120 | #### Additional: 121 | You can delete or remove any port by first selecting the port (key `s`) and then executing below two commands in order (in tkcon window): 122 | * `port remove` 123 | * `label erase` 124 | 125 | ## Defining LEF properties and extracting LEF file 126 | 127 | Certain properties needs to be set before writing the LEF. As mentioned before, these values are fetched by placer and router to determine, for instance, site where a cell needs to be placed. Macro cell properties common to the LEF/DEF definition but that have no corresponding database interpretation in magic are retained using the cell **property** method in magic. There are specific property names associated with the LEF format. Once the properties are set, `lef write` command writes the LEF file with the same nomenclature as that of the layout (.mag) file. 128 | 129 | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/final_LEF_write.JPG?raw=true) 130 | 131 | ## Plugging custom LEF to openlane flow 132 | 133 | If a new custom cell needs to be plugged into openlane flow, include the lefs (the one extracted in [Step-5](#defining-lef-properties-and-extracting-lef-file)) as below: 134 | 135 | - In the design's config.tcl file add the below line to point to the lef location which is required during spice extraction. 136 | 137 | set ::env(EXTRA_LEFS) [glob $::env(OPENLANE_ROOT)/designs/$::env(DESIGN_NAME)/src/*.lef] 138 | 139 | - Include the below command to include the additional lef into the flow: 140 | 141 | set lefs [glob $::env(DESIGN_DIR)/src/*.lef] 142 | 143 | add_lefs -src $lefs 144 | 145 | - Run the interactive flow as described [here.](https://github.com/efabless/openlane/blob/master/doc/advanced_readme.md) 146 | 147 | **Note:** 148 | A sample inverter magic file (_sky130_inv.mag_) has been included as a reference resource. 149 | 150 | ## Observations 151 | 152 | The custom inverter successfully included in the picorv32a design. Below is the final routed picorv32a design with the custom cell zoomed in and highlighted. 153 | 154 | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/final_routing_1.JPG?raw=true) 155 | 156 | ## Challenges 157 | 158 | - The biggest challenge was with the legalization of the cell. Initial iteration showed illegal positioning of the cell away from the standard cell rails. 159 | 160 | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/legalization_issue_1.jpg?raw=true) 161 | 162 | - Upon closer inspection, the issue seemed to be with the dimensions of the drawn power and ground rails and also with the positioning of local1 -> metal1 contacts which was then corrected for further iterations. 163 | 164 | ![alt text](https://github.com/njose939/OpenLane/blob/master/Images/dimensions.JPG?raw=true) 165 | 166 | # Future work 167 | 168 | The upcoming work of this project would be detailed IP characterization once all corner spice models is made availabe in Google-skywater [public forum.](https://github.com/google/skywater-pdk) 169 | 170 | # Limitations 171 | 172 | At present, Openlane has following limitations: 173 | - Limited Timing Constraints. 174 | - Timing Closure. 175 | - No post-routing optimizations. 176 | 177 | Nevertheless, Openlane has a huge community support and improvements are getting pushed every other day. For more details on openlane do visit [openlane1](https://github.com/efabless/openlane/) [openlane2](https://www.youtube.com/watch?v=Vhyv0eq_mLU). 178 | 179 | # Acknowledgements 180 | - [Kunal Ghosh](https://github.com/kunalg123), Co-founder (VSD Corp. Pvt. Ltd) 181 | - [Ahmed Ghazy](https://github.com/ax3ghazy), openlane team, efabless 182 | 183 | -------------------------------------------------------------------------------- /extras/README.md: -------------------------------------------------------------------------------- 1 | This directory contains all files and syntaxes required for VSD Openlane/sky130 workshop. Below are the description of each: 2 | - **guides.txt** - Contains the steps for including additional LEFs to the design. 3 | - **my_base.sdc** - SDC file for STA analysis in openSTA. 4 | - **picorv32a.synthesis.v** - modified netlist for anlysis (Day-4 of workshop) 5 | - **sta.conf** - template of .conf file to be used with openSTA 6 | -------------------------------------------------------------------------------- /extras/guides.txt: -------------------------------------------------------------------------------- 1 | **************************** 2 | STEPS TO ADD EXTRA LEFS 3 | **************************** 4 | 5 | 1) In the designs//config.tcl set below variable after copying the custom lef to /src folder: 6 | 7 | set ::env(EXTRA_LEFS) [glob $::env(OPENLANE_ROOT)/designs/$::env(DESIGN_NAME)/src/*.lef] 8 | 9 | 2) Include below lines in openlane flow (post 'prep -design' stage): 10 | 11 | set lefs [glob $::env(DESIGN_DIR)/src/*.lef] 12 | add_lefs -src $lefs 13 | -------------------------------------------------------------------------------- /extras/my_base.sdc: -------------------------------------------------------------------------------- 1 | set ::env(CLOCK_PORT) clk 2 | set ::env(CLOCK_PERIOD) 12.000 3 | set ::env(SYNTH_DRIVING_CELL) sky130_fd_sc_hd__inv_8 4 | set ::env(SYNTH_DRIVING_CELL_PIN) Y 5 | set ::env(SYNTH_CAP_LOAD) 17.65 6 | create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) 7 | set IO_PCT 0.2 8 | set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] 9 | set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] 10 | puts "\[INFO\]: Setting output delay to: $output_delay_value" 11 | puts "\[INFO\]: Setting input delay to: $input_delay_value" 12 | 13 | 14 | set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] 15 | #set rst_indx [lsearch [all_inputs] [get_port resetn]] 16 | set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] 17 | #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] 18 | set all_inputs_wo_clk_rst $all_inputs_wo_clk 19 | 20 | 21 | # correct resetn 22 | set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst 23 | #set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} 24 | set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] 25 | 26 | # TODO set this as parameter 27 | set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] 28 | set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] 29 | puts "\[INFO\]: Setting load to: $cap_load" 30 | set_load $cap_load [all_outputs] 31 | -------------------------------------------------------------------------------- /extras/sta.conf: -------------------------------------------------------------------------------- 1 | set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um 2 | read_liberty -min 3 | read_liberty -max 4 | read_verilog 5 | link_design 6 | read_sdc 7 | report_checks -path_delay min_max -fields {slew trans net cap input_pin} 8 | report_tns 9 | report_wns 10 | -------------------------------------------------------------------------------- /libs/sky130A.tech: -------------------------------------------------------------------------------- 1 | #---------------------------------------------------------- 2 | # Copyright (c) 2020 R. Timothy Edwards 3 | # Revisions: See below 4 | # 5 | # This file is an Open Source foundry process describing 6 | # the SkyWater S8 hybrid 0.18um / 0.13um fabrication 7 | # process. The file may be distributed under the terms 8 | # of the Apache 2.0 license agreement. 9 | # 10 | #---------------------------------------------------------- 11 | # This file is designed to be used with magic versions 12 | # 8.3.24 or newer. 13 | #---------------------------------------------------------- 14 | tech 15 | format 35 16 | sky130A 17 | end 18 | 19 | version 20 | version 20200508 21 | description "SkyWater SKY130: PRE ALPHA Vendor Open Source rules and DRC" 22 | end 23 | 24 | #---------------------------------------------------------- 25 | # Status 7/10/20: Rev 1 (alpha): 26 | # First public release 27 | #-------------------------------------------------------------- 28 | 29 | #-------------------------------------------------------------- 30 | # Supported device types 31 | #-------------------------------------------------------------- 32 | # device name magic ID layer description 33 | #------------------------------------------------------------- 34 | # nshort nfet standard nFET 35 | # nshort scnfet standard nFET in standard cell** 36 | # nlowvt nfetlvt low Vt nFET 37 | # sonos_p/e nsonos SONOS nFET 38 | # pshort pfet standard pFET 39 | # pshort scpfet standard pFET in standard cell** 40 | # plowvt pfetlvt low Vt pFET 41 | # phighvt pfethvt high Vt pFET 42 | # ntvnative --- native nFET 43 | # phv mvpfet thickox pFET 44 | # nhv mvnfet thickox nFET 45 | # nhvnative mvnnfet thickox native nFET 46 | # ndiode ndiode n+ diff diode 47 | # ndiode_h mvndiode thickox n+ diff diode 48 | # pdiode pdiode p+ diff diode 49 | # pdiode_h mvpdiode thickox p+ diff diode 50 | # ndiode_native nndiode diode with nndiff 51 | # ndiode_lvt ndiodelvt low Vt n+ diff diode 52 | # pdiode_lvt pdiodelvt low Vt p+ diff diode 53 | # pdiode_hvt pdiodehvt high Vt p+ diff diode 54 | # nwdiode --- nwell diode 55 | # dnwdiode_psub --- deep nwell diode to substrate 56 | # dnwdiode_pw --- deep nwell diode to pwell 57 | # xcmimc1 mimcap MiM cap 1st plate 58 | # xcmimc2 mimcap2 MiM cap 2nd plate 59 | # mrdn rdn n+ diff resistor 60 | # mrdn_hv mvrdn thickox n+ diff resistor 61 | # mrdp rdp p+ diff resistor 62 | # mrdp_hv mvrdp thickox p+ diff resistor 63 | # mrl1 rli local interconnect resistor 64 | # mrp1 npres n+ poly resistor 65 | # xhrpoly_* ppres (*) p+ poly resistor (300 Ohms/sq) 66 | # uhrpoly_* xres (*) p+ poly resistor (2k Ohms/sq) 67 | # xcnwvc varactor varactor (low Vt?) 68 | # xcnwvc2 varactorhvt high Vt varactor 69 | # xchvnwc mvvaractor thickox varactor 70 | # xpwres rpw pwell resistor (in deep nwell) 71 | # 72 | # (*) Note that ppres may extract into some generic type 73 | # called "xhrpoly", but only specific sizes of xhrpoly are 74 | # allowed, and these are created from fixed layouts like the 75 | # types below. 76 | # 77 | # (**) nFET and pFET in standard cells are the same as devices 78 | # outside of the standard cell except for the DRC rule for 79 | # FET to diffusion contact spacing (which is 0.05um, not 0.055um) 80 | # 81 | # To avoid creating a large number of types, a few ID layers are 82 | # used in conjunction with standard devices types: "lvt" for 83 | # low threshold voltage, and "hvt" for high threshold voltage. 84 | # "dnwell" is used as an identifier layer where appropriate. 85 | # Layer HVI (thick oxide) is treated differently, and types 86 | # "mv*" are defined where thick oxide is required. 87 | # 88 | #------------------------------------------------------------- 89 | # The following devices are not extracted but are represented 90 | # only by script-generated subcells in the PDK. 91 | #------------------------------------------------------------- 92 | # nshortesd ESD nFET 93 | # nhvesd ESD thickox nFET 94 | # nhvnativeesd ESD native nFET 95 | # phvesd ESD thickox pFET 96 | # fnpass flash nFET device 97 | # npnpar1x* parasitic NPN 98 | # npn_1x1_2p0_hv thickox gated parasitic NPN 99 | # pnppar parasitic PNP 100 | # pnppar5x parasitic PNP 101 | # xesd_ndiode_h_*** ESD n+ diode 102 | # xesd_pdiode_h_*** ESD p+ diode 103 | # reslocsub local substrate island indicator 104 | # xcmvpp Vpp cap 105 | # xcmvpp_2 Vpp cap 106 | # xcmvpp_* Vpp cap 107 | # xcmvpp* Vpp cap 108 | # balun balun inductor 109 | # ind4 inductor 110 | # fuse metal fuse device 111 | #-------------------------------------------------------------- 112 | 113 | #----------------------------------------------------- 114 | # Tile planes 115 | #----------------------------------------------------- 116 | 117 | planes 118 | dwell,dw 119 | well,w 120 | active,a 121 | locali,li1,li 122 | metal1,m1 123 | metal2,m2 124 | metal3,m3 125 | cap1,c1 126 | metal4,m4 127 | cap2,c2 128 | metal5,m5 129 | block,b 130 | comment,c 131 | end 132 | 133 | #----------------------------------------------------- 134 | # Tile types 135 | #----------------------------------------------------- 136 | 137 | types 138 | # Deep nwell 139 | dwell dnwell,dnw 140 | 141 | # Wells 142 | well nwell,nw 143 | -well pwell,pw 144 | -well rpw,rpwell 145 | -well obswell 146 | 147 | # Transistors 148 | active nmos,ntransistor,nfet 149 | -active scnmos,scntransistor,scnfet 150 | active pmos,ptransistor,pfet 151 | -active scpmos,scptransistor,scpfet 152 | -active nnmos,nntransistor 153 | active mvnmos,mvntransistor,mvnfet 154 | active mvpmos,mvptransistor,mvpfet 155 | -active mvnnmos,mvnntransistor,mvnnfet,nnfet 156 | -active varactor,varact,var 157 | -active mvvaractor,mvvaract,mvvar 158 | 159 | -active pmoslvt,pfetlvt 160 | -active pmoshvt,pfethvt 161 | -active nmoslvt,nfetlvt 162 | -active varactorhvt,varacthvt,varhvt 163 | -active nsonos,sonos 164 | 165 | # Diffusions 166 | active ndiff,ndiffusion,ndif 167 | active pdiff,pdiffusion,pdif 168 | -active mvndiff,mvndiffusion,mvndif 169 | -active mvpdiff,mvpdiffusion,mvpdif 170 | active ndiffc,ndcontact,ndc 171 | active pdiffc,pdcontact,pdc 172 | -active mvndiffc,mvndcontact,mvndc 173 | -active mvpdiffc,mvpdcontact,mvpdc 174 | active psubdiff,psubstratepdiff,ppdiff,ppd,psd 175 | active nsubdiff,nsubstratendiff,nndiff,nnd,nsd 176 | -active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd 177 | -active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd 178 | active psubdiffcont,psubstratepcontact,psc 179 | active nsubdiffcont,nsubstratencontact,nsc 180 | -active mvpsubdiffcont,mvpsubstratepcontact,mvpsc 181 | -active mvnsubdiffcont,mvnsubstratencontact,mvnsc 182 | -active obsactive 183 | -active mvobsactive 184 | 185 | # Poly 186 | active poly,p,polysilicon 187 | active polycont,pc,pcontact,polycut,polyc 188 | active xpolycontact,xpolyc,xpc 189 | 190 | # Resistors 191 | -active npolyres,npres,mrp1 192 | -active ppolyres,ppres,xhrpoly 193 | -active xpolyres,xpres,xres,uhrpoly 194 | -active ndiffres,rnd,rdn,rndiff 195 | -active pdiffres,rpd,rdp,rpdiff 196 | -active mvndiffres,mvrnd,mvrdn,mvrndiff 197 | -active mvpdiffres,mvrpd,mvrdp,mvrpdiff 198 | -active rmp 199 | 200 | # Diodes 201 | -active pdiode,pdi 202 | -active ndiode,ndi 203 | -active nndiode,nndi 204 | -active pdiodec,pdic 205 | -active ndiodec,ndic 206 | -active nndiodec,nndic 207 | -active mvpdiode,mvpdi 208 | -active mvndiode,mvndi 209 | -active mvpdiodec,mvpdic 210 | -active mvndiodec,mvndic 211 | -active pdiodelvt,pdilvt 212 | -active pdiodehvt,pdihvt 213 | -active ndiodelvt,ndilvt 214 | -active pdiodelvtc,pdilvtc 215 | -active pdiodehvtc,pdihvtc 216 | -active ndiodelvtc,ndilvtc 217 | 218 | # Local Interconnect 219 | locali locali,li1,li 220 | -locali corelocali,coreli1,coreli 221 | -locali rlocali,rli1,rli 222 | locali viali,vial,lic,licon,m1c,v0 223 | -locali obsli1,obsli 224 | -locali obsli1c,obslic,obslicon 225 | 226 | # Metal 1 227 | metal1 metal1,m1,met1 228 | -metal1 rmetal1,rm1,rmet1 229 | metal1 via1,m2contact,m2cut,m2c,via,v,v1 230 | -metal1 obsm1 231 | -metal1 padl 232 | 233 | # Metal 2 234 | metal2 metal2,m2,met2 235 | -metal2 rmetal2,rm2,rmet2 236 | metal2 via2,m3contact,m3cut,m3c,v2 237 | -metal2 obsm2 238 | 239 | # Metal 3 240 | metal3 metal3,m3,met3 241 | -metal3 rmetal3,rm3,rmet3 242 | -metal3 obsm3 243 | metal3 via3,v3 244 | 245 | -cap1 mimcap,mim,capm 246 | -cap1 mimcapcontact,mimcapc,mimcc,capmc 247 | 248 | # Metal 4 249 | metal4 metal4,m4,met4 250 | -metal4 rmetal4,rm4,rmet4 251 | -metal4 obsm4 252 | metal4 via4,v4 253 | 254 | -cap2 mimcap2,mim2,capm2 255 | -cap2 mimcap2contact,mimcap2c,mim2cc,capm2c 256 | 257 | # Metal 5 258 | metal5 metal5,m5,met5 259 | -metal5 rm5,rmetal5,rmet5 260 | -metal5 obsm5 261 | 262 | 263 | # Miscellaneous 264 | -block glass 265 | -block fillblock 266 | -comment comment 267 | -comment obscomment 268 | 269 | end 270 | 271 | #----------------------------------------------------- 272 | # Magic contact types 273 | #----------------------------------------------------- 274 | 275 | contact 276 | pc poly locali 277 | ndc ndiff locali 278 | pdc pdiff locali 279 | nsc nsd locali 280 | psc psd locali 281 | ndic ndiode locali 282 | ndilvtc ndiodelvt locali 283 | nndic nndiode locali 284 | pdic pdiode locali 285 | pdilvtc pdiodelvt locali 286 | pdihvtc pdiodehvt locali 287 | xpc xpc locali 288 | 289 | mvndc mvndiff locali 290 | mvpdc mvpdiff locali 291 | mvnsc mvnsd locali 292 | mvpsc mvpsd locali 293 | mvndic mvndiode locali 294 | mvpdic mvpdiode locali 295 | 296 | lic locali metal1 297 | obslic obsli obsm1 298 | 299 | via1 metal1 metal2 300 | via2 metal2 metal3 301 | via3 metal3 metal4 302 | via4 metal4 metal5 303 | stackable 304 | 305 | # MiM cap contacts are not stackable! 306 | mimcc mimcap metal4 307 | mim2cc mimcap2 metal5 308 | 309 | padl m1 m2 m3 m4 m5 glass 310 | 311 | end 312 | 313 | #----------------------------------------------------- 314 | # Layer aliases 315 | #----------------------------------------------------- 316 | 317 | aliases 318 | 319 | allwellplane nwell 320 | allnwell nwell,obswell 321 | 322 | allnfets nfet,scnfet,mvnfet,mvnnfet,nfetlvt,nsonos 323 | allpfets pfet,scpfet,mvpfet,pfethvt,pfetlvt 324 | allfets allnfets,allpfets,varactor,mvvaractor,varhvt 325 | 326 | allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt 327 | allnactive allnactivenonfet,allnfets 328 | allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets 329 | allnactivetap *nsd,*mvnsd,var,varhvt,mvvar 330 | 331 | allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt 332 | allpactive allpactivenonfet,allpfets 333 | allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets 334 | allpactivetap *psd,*mvpsd 335 | 336 | allactivenonfet allnactivenonfet,allpactivenonfet 337 | allactive allactivenonfet,allfets 338 | 339 | allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres 340 | 341 | allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,scnfet,nfetlvt,nsonos 342 | allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,scpfet,pfetlvt,pfethvt 343 | alldifflv allndifflv,allpdifflv 344 | allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt 345 | allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt 346 | alldifflvnonfet allndifflvnonfet,allpdifflvnonfet 347 | 348 | allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet 349 | allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet 350 | alldiffmv allndiffmv,allpdiffmv 351 | allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet 352 | allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet 353 | alldiffmvnontap allndiffmvnontap,allpdiffmvnontap 354 | allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres 355 | allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres 356 | alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet 357 | 358 | alldiffnonfet alldifflvnonfet,alldiffmvnonfet 359 | alldiff alldifflv,alldiffmv 360 | 361 | allpolyres mrp1,xhrpoly,uhrpoly,rmp 362 | allpolynonfet *poly,allpolyres,xpc 363 | allpolynonres *poly,allfets,xpc 364 | 365 | allpoly allpolynonfet,allfets 366 | allpolynoncap *poly,xpc,allfets,allpolyres 367 | 368 | allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc 369 | allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc 370 | allndiffcontmv mvndc,mvnsc,mvndic 371 | allpdiffcontmv mvpdc,mvpsc,mvpdic 372 | allndiffcont allndiffcontlv,allndiffcontmv 373 | allpdiffcont allpdiffcontlv,allpdiffcontmv 374 | alldiffcontlv allndiffcontlv,allpdiffcontlv 375 | alldiffcontmv allndiffcontmv,allpdiffcontmv 376 | alldiffcont alldiffcontlv,alldiffcontmv 377 | 378 | allcont alldiffcont,pc 379 | 380 | allres allpolyres,allactiveres 381 | 382 | allli *locali,coreli,rli 383 | allm1 *m1,rm1 384 | allm2 *m2,rm2 385 | allm3 *m3,rm3 386 | allm4 *m4,rm4 387 | allm5 *m5,rm5 388 | 389 | allpad padl 390 | 391 | psub pwell 392 | 393 | end 394 | 395 | #----------------------------------------------------- 396 | # Layer drawing styles 397 | #----------------------------------------------------- 398 | 399 | styles 400 | styletype mos 401 | dnwell cwell 402 | nwell nwell 403 | pwell pwell 404 | rpwell pwell ptransistor_stripes 405 | ndiff ndiffusion 406 | pdiff pdiffusion 407 | nsd ndiff_in_nwell 408 | psd pdiff_in_pwell 409 | nfet ntransistor ntransistor_stripes 410 | scnfet ntransistor ntransistor_stripes 411 | pfet ptransistor ptransistor_stripes 412 | scpfet ptransistor ptransistor_stripes 413 | var polysilicon ndiff_in_nwell 414 | ndc ndiffusion metal1 contact_X'es 415 | pdc pdiffusion metal1 contact_X'es 416 | nsc ndiff_in_nwell metal1 contact_X'es 417 | psc pdiff_in_pwell metal1 contact_X'es 418 | 419 | pfetlvt ptransistor ptransistor_stripes implant1 420 | pfethvt ptransistor ptransistor_stripes implant2 421 | nfetlvt ntransistor ntransistor_stripes implant1 422 | nsonos ntransistor implant3 423 | varhvt polysilicon ndiff_in_nwell implant2 424 | 425 | mvndiff ndiffusion hvndiff_mask 426 | mvpdiff pdiffusion hvpdiff_mask 427 | mvnsd ndiff_in_nwell hvndiff_mask 428 | mvpsd pdiff_in_pwell hvpdiff_mask 429 | mvnfet ntransistor ntransistor_stripes hvndiff_mask 430 | mvnnfet ntransistor ndiff_in_nwell hvndiff_mask 431 | mvpfet ptransistor ptransistor_stripes 432 | mvvar polysilicon ndiff_in_nwell hvndiff_mask 433 | mvndc ndiffusion metal1 contact_X'es hvndiff_mask 434 | mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask 435 | mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask 436 | mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask 437 | 438 | poly polysilicon 439 | pc polysilicon metal1 contact_X'es 440 | npolyres polysilicon silicide_block nselect2 441 | ppolyres polysilicon silicide_block pselect2 442 | xpc polysilicon pselect2 metal1 contact_X'es 443 | rmp polysilicon poly_resist_stripes 444 | 445 | pdiode pdiffusion pselect2 446 | ndiode ndiffusion nselect2 447 | pdiodec pdiffusion pselect2 metal1 contact_X'es 448 | ndiodec ndiffusion nselect2 metal1 contact_X'es 449 | 450 | nndiode ndiffusion nselect2 implant3 451 | ndiodelvt ndiffusion nselect2 implant1 452 | pdiodelvt pdiffusion pselect2 implant1 453 | pdiodehvt pdiffusion pselect2 implant2 454 | pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es 455 | pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es 456 | ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es 457 | 458 | mvpdiode pdiffusion pselect2 hvpdiff_mask 459 | mvndiode ndiffusion nselect2 hvndiff_mask 460 | mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask 461 | mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask 462 | nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask 463 | 464 | locali metal1 465 | coreli metal1 466 | rli metal1 poly_resist_stripes 467 | lic metal1 metal2 via1arrow 468 | obsli metal1 469 | obslic metal1 metal2 via1arrow 470 | 471 | metal1 metal2 472 | rm1 metal2 poly_resist_stripes 473 | obsm1 metal2 474 | m2c metal2 metal3 via2arrow 475 | metal2 metal3 476 | rm2 metal3 poly_resist_stripes 477 | obsm2 metal3 478 | m3c metal3 metal4 via3alt 479 | metal3 metal4 480 | rm3 metal4 poly_resist_stripes 481 | obsm3 metal4 482 | mimcap metal3 mems 483 | mimcc metal3 contact_X'es mems 484 | mimcap2 metal4 mems 485 | mim2cc metal4 contact_X'es mems 486 | via3 metal4 metal5 via4 487 | metal4 metal5 488 | rm4 metal5 poly_resist_stripes 489 | obsm4 metal5 490 | via4 metal5 metal6 via5 491 | metal5 metal6 492 | rm5 metal6 poly_resist_stripes 493 | obsm5 metal6 494 | 495 | glass overglass 496 | mrp1 poly_resist poly_resist_stripes 497 | xhrpoly poly_resist silicide_block 498 | uhrpoly poly_resist 499 | ndiffres ndiffusion ndop_stripes 500 | pdiffres pdiffusion pdop_stripes 501 | mvndiffres ndiffusion hvndiff_mask ndop_stripes 502 | mvpdiffres pdiffusion hvpdiff_mask pdop_stripes 503 | comment comment 504 | error_p error_waffle 505 | error_s error_waffle 506 | error_ps error_waffle 507 | fillblock cwell 508 | 509 | obswell cwell 510 | obsactive implant4 511 | 512 | padl metal6 via6 overglass 513 | 514 | magnet substrate_field_implant 515 | rotate via3alt 516 | fence via5 517 | end 518 | 519 | #----------------------------------------------------- 520 | # Special paint/erase rules 521 | #----------------------------------------------------- 522 | 523 | compose 524 | compose nfet poly ndiff 525 | compose pfet poly pdiff 526 | compose var poly nsd 527 | 528 | compose mvnfet poly mvndiff 529 | compose mvpfet poly mvpdiff 530 | compose mvvar poly mvnsd 531 | 532 | paint ndc nwell pdc 533 | paint nfet nwell pfet 534 | paint scnfet nwell scpfet 535 | paint ndiff nwell pdiff 536 | paint psd nwell nsd 537 | paint psc nwell nsc 538 | 539 | paint pdc pwell ndc 540 | paint pfet pwell nfet 541 | paint scpfet pwell scnfet 542 | paint pdiff pwell ndiff 543 | paint nsd pwell psd 544 | paint nsc pwell psc 545 | 546 | paint pdc coreli pdc 547 | paint ndc coreli ndc 548 | paint pc coreli pc 549 | paint nsc coreli pc 550 | paint psc coreli pc 551 | paint viali coreli viali 552 | 553 | paint coreli pdc pdc 554 | paint coreli ndc ndc 555 | paint coreli pc pc 556 | paint coreli nsc nsc 557 | paint coreli psc psc 558 | paint coreli viali viali 559 | 560 | paint m4 obsm4 m4 561 | paint m5 obsm5 m5 562 | end 563 | 564 | #----------------------------------------------------- 565 | # Electrical connectivity 566 | #----------------------------------------------------- 567 | 568 | connect 569 | *nwell,*nsd,*mvnsd,dnwell *nwell,*nsd,*mvnsd,dnwell 570 | pwell,*psd,*mvpsd pwell,*psd,*mvpsd 571 | *li,coreli *li,coreli 572 | *m1 *m1 573 | *m2 *m2 574 | *m3 *m3 575 | *m4 *m4 576 | *m5 *m5 577 | *mimcap *mimcap 578 | *mimcap2 *mimcap2 579 | allnactivenonfet allnactivenonfet 580 | allpactivenonfet allpactivenonfet 581 | *poly,xpc,allfets *poly,xpc,allfets 582 | end 583 | 584 | #----------------------------------------------------- 585 | # CIF/GDS output layer definitions 586 | #----------------------------------------------------- 587 | # NOTE: All values in this section MUST be multiples of 25 588 | # or else magic will scale below the allowed layout grid size 589 | 590 | cifoutput 591 | 592 | #---------------------------------------------------------------- 593 | style gdsii 594 | # NOTE: This section is used for actual GDS output 595 | #---------------------------------------------------------------- 596 | scalefactor 10 nanometers 597 | options calma-permissive-labels 598 | gridlimit 5 599 | 600 | #---------------------------------------------------------------- 601 | # Create a temp layer from the cell bounding box for use in 602 | # generating ID layers. Note that "boundary", unlike "bbox", 603 | # requires the FIXED_BBOX property (abutment box) in the cell. 604 | #---------------------------------------------------------------- 605 | templayer CELLBOUND 606 | boundary 607 | 608 | #---------------------------------------------------------------- 609 | # BOUND 610 | #---------------------------------------------------------------- 611 | layer BOUND CELLBOUND 612 | calma 235 4 613 | 614 | # Create a boundary outside of an abutment box, so that layers 615 | # can be made to stretch to the abutment box edges. First strink 616 | # so that any box that would be so small as to interact with 617 | # itself will be removed. 618 | 619 | templayer CELLRING CELLBOUND 620 | shrink 345 621 | grow 545 622 | and-not CELLBOUND 623 | 624 | #---------------------------------------------------------------- 625 | # DNWELL 626 | #---------------------------------------------------------------- 627 | 628 | layer DNWELL dnwell 629 | calma 64 18 630 | 631 | layer PWRES rpw 632 | and dnwell 633 | calma 64 13 634 | 635 | #---------------------------------------------------------------- 636 | # NWELL 637 | #---------------------------------------------------------------- 638 | 639 | layer NWELL allnwell 640 | bloat-all rpw dnwell 641 | and-not rpw,pwell 642 | calma 64 20 643 | 644 | layer WELLTXT 645 | labels allnwell noport 646 | calma 64 16 647 | 648 | layer WELLPIN 649 | labels allnwell port 650 | calma 64 5 651 | 652 | #---------------------------------------------------------------- 653 | # SUB (text/port only) 654 | #---------------------------------------------------------------- 655 | 656 | layer SUBTXT 657 | labels pwell noport 658 | calma 122 16 659 | 660 | layer SUBPIN 661 | labels pwell port 662 | calma 64 59 663 | 664 | #---------------------------------------------------------------- 665 | # DIFF 666 | #---------------------------------------------------------------- 667 | 668 | layer DIFF allnactivenontap,allpactivenontap,allactiveres 669 | labels allnactivenontap,allpactivenontap 670 | calma 65 20 671 | 672 | #---------------------------------------------------------------- 673 | # TAP 674 | #---------------------------------------------------------------- 675 | 676 | layer TAP allnactivetap,allpactivetap 677 | labels allnactivetap,allpactivetap 678 | calma 65 44 679 | 680 | #---------------------------------------------------------------- 681 | # PPLUS, NPLUS (PSDM, NSDM) 682 | #---------------------------------------------------------------- 683 | 684 | templayer basePPLUS pdiffres,mvpdiffres 685 | grow 15 686 | or xhrpoly,uhrpoly,xpc 687 | grow 110 688 | bloat-or allpactivetap * 125 allnactivenontap 0 689 | bloat-or allpactivenontap * 125 allnactivetap 0 690 | bridge 380 380 691 | 692 | templayer extendPPLUS basePPLUS,CELLRING 693 | grow 185 694 | shrink 185 695 | and-not CELLRING 696 | 697 | layer PPLUS basePPLUS,extendPPLUS 698 | close 265000 699 | calma 94 20 700 | 701 | templayer baseNPLUS ndiffres,mvndiffres 702 | grow 125 703 | bloat-or allnactivetap * 125 allpactivenontap 0 704 | bloat-or allnactivenontap * 125 allpactivetap 0 705 | bridge 380 380 706 | 707 | templayer extendNPLUS baseNPLUS,CELLRING 708 | grow 185 709 | shrink 185 710 | and-not CELLRING 711 | 712 | layer NPLUS baseNPLUS,extendNPLUS 713 | close 265000 714 | calma 93 44 715 | 716 | #---------------------------------------------------------------- 717 | # LVTN 718 | #---------------------------------------------------------------- 719 | 720 | layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode 721 | grow 180 722 | bridge 380 380 723 | grow 185 724 | shrink 185 725 | close 265000 726 | calma 125 44 727 | 728 | #---------------------------------------------------------------- 729 | # HVTP 730 | #---------------------------------------------------------------- 731 | 732 | layer HVTP pfethvt,varhvt,*pdiodehvt 733 | grow 180 734 | bridge 380 380 735 | grow 185 736 | shrink 185 737 | close 265000 738 | calma 78 44 739 | 740 | #---------------------------------------------------------------- 741 | # SONOS 742 | #---------------------------------------------------------------- 743 | 744 | layer SONOS nsonos 745 | grow 100 746 | grow-min 410 747 | bridge 500 410 748 | grow 250 749 | shrink 250 750 | calma 80 20 751 | 752 | #---------------------------------------------------------------- 753 | # SONOS requires COREID around area (areaid.ce). Also, the 754 | # coreli layer indicates a cell needing COREID. 755 | #---------------------------------------------------------------- 756 | 757 | layer COREID 758 | bloat-all nsonos,coreli CELLBOUND 759 | calma 81 2 760 | 761 | #---------------------------------------------------------------- 762 | # STDCELL applies to all cells containing scnfet or scpfet. 763 | #---------------------------------------------------------------- 764 | 765 | layer STDCELL scnfet 766 | bloat-all scpfet,scnfet CELLBOUND 767 | calma 81 4 768 | 769 | #---------------------------------------------------------------- 770 | # RPM 771 | #---------------------------------------------------------------- 772 | 773 | layer RPM 774 | bloat-all xhrpoly xpc 775 | grow 200 776 | grow-min 1270 777 | grow 420 778 | shrink 420 779 | calma 86 20 780 | 781 | #---------------------------------------------------------------- 782 | # URPM (2kOhms/sq. poly implant) 783 | #---------------------------------------------------------------- 784 | 785 | layer URPM 786 | bloat-all uhrpoly xpc 787 | grow 200 788 | grow-min 1270 789 | grow 420 790 | shrink 420 791 | calma 79 20 792 | 793 | #---------------------------------------------------------------- 794 | # LDNTM (Tip implant for SONOS FETs) 795 | #---------------------------------------------------------------- 796 | 797 | layer LDNTM 798 | bloat-all nsonos *ndiff 799 | grow 185 800 | grow 345 801 | shrink 345 802 | calma 11 44 803 | 804 | #---------------------------------------------------------------- 805 | # HVNTM (Tip implant for MV ndiff devices) 806 | #---------------------------------------------------------------- 807 | 808 | templayer hvntm_block *mvpsd 809 | grow 185 810 | 811 | layer HVNTM 812 | bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff 813 | bloat-all mvvaractor *mvnsd 814 | and-not hvntm_block 815 | grow 185 816 | grow 345 817 | shrink 345 818 | calma 125 20 819 | 820 | #---------------------------------------------------------------- 821 | # POLY 822 | #---------------------------------------------------------------- 823 | 824 | layer POLY allpoly 825 | calma 66 20 826 | 827 | layer POLYTXT 828 | labels allpoly noport 829 | calma 66 16 830 | 831 | layer POLYPIN 832 | labels allpoly port 833 | calma 66 5 834 | 835 | #---------------------------------------------------------------- 836 | # THKOX (HVI) (includes rules NWELL 8-11 and DIFFTAP 14-26) 837 | #---------------------------------------------------------------- 838 | 839 | templayer baseTHKOX *mvpsd 840 | grow-min 470 841 | or alldiffmv,mvvar 842 | grow 185 843 | bloat-all alldiffmv nwell 844 | grow-min 600 845 | bridge 700 600 846 | 847 | templayer extendTHKOX baseTHKOX,CELLRING 848 | grow 345 849 | shrink 345 850 | and-not CELLRING 851 | 852 | layer THKOX baseTHKOX,extendTHKOX 853 | calma 75 20 854 | 855 | #---------------------------------------------------------------- 856 | # CONT (LICON) 857 | #---------------------------------------------------------------- 858 | 859 | layer CONT allcont 860 | squares-grid 0 170 170 861 | calma 66 44 862 | 863 | # Contact for pres is different than other LICON contacts 864 | # See rules LICON 1b, 1c (width/length) and 2b (spacing) 865 | templayer xpc_horiz xpc 866 | shrink 1007 867 | grow 1007 868 | 869 | layer CONT xpc 870 | and-not xpc_horiz 871 | # Force long edge vertical for contacts narrower than 2um 872 | # Minimum space is 350 but 520 satisfies no. of contacts rule 873 | slots 80 190 520 80 2000 350 874 | calma 66 44 875 | 876 | layer CONT xpc 877 | and xpc_horiz 878 | # Force long edge vertical for contacts wider than 2um 879 | # Minimum space is 350 but 520 satisfies no. of contacts rule 880 | slots 80 2000 350 80 190 520 881 | calma 66 44 882 | 883 | #---------------------------------------------------------------- 884 | # NPC (Nitride poly cut) 885 | # surrounds CONT (LICON) on poly only (i.e., pc) 886 | #---------------------------------------------------------------- 887 | 888 | layer NPC pc 889 | squares-grid 0 170 170 890 | grow 100 891 | bridge 270 270 892 | grow 130 893 | shrink 130 894 | calma 95 20 895 | 896 | # NPC is also generated on xhrpoly and uhrpoly resistors 897 | 898 | layer NPC xpc,xhrpoly,uhrpoly 899 | # xpc surrounds precision_resistor by 0.095um 900 | grow 95 901 | grow 130 902 | shrink 130 903 | calma 95 20 904 | 905 | #---------------------------------------------------------------- 906 | # Device markers 907 | #---------------------------------------------------------------- 908 | 909 | layer DIFFRES rdn,mvrdn,rdp,mvrdp 910 | calma 65 13 911 | 912 | layer POLYRES mrp1 913 | calma 66 13 914 | 915 | # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers 916 | layer POLYSHORT rmp 917 | calma 66 15 918 | 919 | # POLYRES extends to edge of contact cut 920 | layer POLYRES xhrpoly,uhrpoly 921 | grow 60 922 | and xpc 923 | or xhrpoly,uhrpoly 924 | calma 66 13 925 | 926 | layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt 927 | # To be done: Expand to include anode, cathode, and guard ring 928 | calma 81 23 929 | 930 | #---------------------------------------------------------------- 931 | # LI 932 | #---------------------------------------------------------------- 933 | layer LI allli 934 | calma 67 20 935 | 936 | layer LITXT 937 | labels *locali,coreli noport 938 | calma 67 16 939 | 940 | layer LIPIN 941 | labels *locali,coreli port 942 | calma 67 5 943 | 944 | layer LIRES rli 945 | labels rli 946 | calma 67 13 947 | 948 | #---------------------------------------------------------------- 949 | # MCON 950 | #---------------------------------------------------------------- 951 | layer MCON lic 952 | squares-grid 0 170 190 953 | calma 67 44 954 | 955 | #---------------------------------------------------------------- 956 | # MET1 957 | #---------------------------------------------------------------- 958 | layer MET1 allm1 959 | calma 68 20 960 | 961 | layer MET1TXT 962 | labels allm1 noport 963 | calma 68 16 964 | 965 | layer MET1PIN 966 | labels allm1 port 967 | calma 68 5 968 | 969 | layer MET1RES rm1 970 | labels rm1 971 | calma 68 13 972 | 973 | #---------------------------------------------------------------- 974 | # VIA1 975 | #---------------------------------------------------------------- 976 | layer VIA1 via1 977 | squares-grid 55 150 170 978 | calma 68 44 979 | 980 | #---------------------------------------------------------------- 981 | # MET2 982 | #---------------------------------------------------------------- 983 | layer MET2 allm2 984 | calma 69 20 985 | 986 | layer MET2TXT 987 | labels allm2 noport 988 | calma 69 16 989 | 990 | layer MET2PIN 991 | labels allm2 port 992 | calma 69 5 993 | 994 | layer MET2RES rm2 995 | labels rm2 996 | calma 69 13 997 | 998 | #---------------------------------------------------------------- 999 | # VIA2 1000 | #---------------------------------------------------------------- 1001 | layer VIA2 via2 1002 | squares-grid 40 200 200 1003 | calma 69 44 1004 | 1005 | #---------------------------------------------------------------- 1006 | # MET3 1007 | #---------------------------------------------------------------- 1008 | layer MET3 allm3 1009 | calma 70 20 1010 | 1011 | layer MET3TXT 1012 | labels allm3 noport 1013 | calma 70 16 1014 | 1015 | layer MET3PIN 1016 | labels allm3 port 1017 | calma 70 5 1018 | 1019 | layer MET3RES rm3 1020 | labels rm3 1021 | calma 70 13 1022 | 1023 | #---------------------------------------------------------------- 1024 | # VIA3 1025 | #---------------------------------------------------------------- 1026 | layer VIA3 via3 1027 | or mimcc 1028 | squares-grid 60 200 200 1029 | calma 70 44 1030 | 1031 | #---------------------------------------------------------------- 1032 | # MET4 1033 | #---------------------------------------------------------------- 1034 | layer MET4 allm4 1035 | calma 71 20 1036 | 1037 | layer MET4TXT 1038 | labels allm4 noport 1039 | calma 71 16 1040 | 1041 | layer MET4PIN 1042 | labels allm4 port 1043 | calma 71 5 1044 | 1045 | layer MET4RES rm4 1046 | labels rm4 1047 | calma 71 13 1048 | 1049 | #---------------------------------------------------------------- 1050 | # VIA4 1051 | #---------------------------------------------------------------- 1052 | layer VIA4 via4 1053 | or mim2cc 1054 | squares-grid 190 800 800 1055 | calma 71 44 1056 | 1057 | #---------------------------------------------------------------- 1058 | # MET5 1059 | #---------------------------------------------------------------- 1060 | layer MET5 allm5 1061 | calma 72 20 1062 | 1063 | layer MET5TXT 1064 | labels allm5 noport 1065 | calma 72 16 1066 | 1067 | layer MET5PIN 1068 | labels allm5 port 1069 | calma 72 5 1070 | 1071 | layer MET5RES rm5 1072 | labels rm5 1073 | calma 72 13 1074 | 1075 | 1076 | 1077 | #---------------------------------------------------------------- 1078 | # GLASS 1079 | #---------------------------------------------------------------- 1080 | layer GLASS glass 1081 | calma 76 20 1082 | 1083 | #---------------------------------------------------------------- 1084 | # CAPM 1085 | #---------------------------------------------------------------- 1086 | layer CAPM *mimcap 1087 | labels mimcap 1088 | calma 89 44 1089 | 1090 | layer CAPM2 *mimcap2 1091 | labels mimcap2 1092 | calma 97 44 1093 | 1094 | #---------------------------------------------------------------- 1095 | # Chip top level marker for DRC latchup rules to check 15um 1096 | # distance to taps (otherwise 6um is used) 1097 | #---------------------------------------------------------------- 1098 | 1099 | layer LOWTAPDENSITY 1100 | bbox top 1101 | # Clear 200um for pads + 50um for required high tap density 1102 | # in critical area. 1103 | shrink 250000 1104 | calma 81 14 1105 | 1106 | #---------------------------------------------------------------- 1107 | # FILLBLOCK 1108 | #---------------------------------------------------------------- 1109 | layer FILLOBSM1 fillblock 1110 | calma 62 24 1111 | 1112 | layer FILLOBSM2 fillblock 1113 | calma 105 52 1114 | 1115 | layer FILLOBSM3 fillblock 1116 | calma 107 24 1117 | 1118 | layer FILLOBSM4 fillblock 1119 | calma 112 4 1120 | 1121 | render DNWELL cwell -0.1 0.1 1122 | render NWELL nwell 0.0 0.2062 1123 | render DIFF ndiffusion 0.2062 0.12 1124 | render TAP pdiffusion 0.2062 0.12 1125 | render POLY polysilicon 0.3262 0.18 1126 | render CONT via 0.5062 0.43 1127 | render LI metal1 0.9361 0.10 1128 | render MCON via 1.0361 0.34 1129 | render MET1 metal2 1.3761 0.36 1130 | render VIA1 via 1.7361 0.27 1131 | render MET2 metal3 2.0061 0.36 1132 | render VIA2 via 2.3661 0.42 1133 | render MET3 metal4 2.7861 0.845 1134 | render VIA3 via 3.6311 0.39 1135 | render MET4 metal5 4.0211 0.845 1136 | render VIA4 via 4.8661 0.505 1137 | render MET5 metal6 5.3711 1.26 1138 | render CAPM metal8 2.4661 0.2 1139 | render CAPM2 metal9 3.7311 0.2 1140 | 1141 | #---------------------------------------------------------------- 1142 | style drc 1143 | #---------------------------------------------------------------- 1144 | # NOTE: This style is used for DRC only, not for GDS output 1145 | #---------------------------------------------------------------- 1146 | scalefactor 10 nanometers 1147 | options calma-permissive-labels 1148 | 1149 | # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside 1150 | templayer dnwell_shrink dnwell 1151 | shrink 1030 1152 | 1153 | templayer nwell_missing dnwell 1154 | grow 400 1155 | and-not dnwell_shrink 1156 | and-not nwell 1157 | 1158 | # SONOS nFET devices must be in deep nwell 1159 | templayer dnwell_missing nsonos 1160 | and-not dnwell 1161 | 1162 | # Define MiM cap bottom plate for spacing rule 1163 | templayer mim_bottom 1164 | bloat-all *mimcap *metal3 1165 | 1166 | # Define MiM2 cap bottom plate for spacing rule 1167 | templayer mim2_bottom 1168 | bloat-all *mimcap2 *metal4 1169 | 1170 | # Note that metal fill is performed by the foundry and so is not 1171 | # an option for a cifoutput style. 1172 | 1173 | # Check latchup rule (15um minimum from tap LICON center to any 1174 | # non-tap diffusion. Note that to count as a tap, the diffusion 1175 | # must be contacted to LI 1176 | 1177 | templayer ptap_reach psc,mvpsc 1178 | and-not dnwell 1179 | # grow total is 15um. grow in 0.84um increments to ensure that 1180 | # no nwell ring is crossed 1181 | grow 840 1182 | and-not nwell,dnwell 1183 | grow 840 1184 | and-not nwell,dnwell 1185 | grow 840 1186 | and-not nwell,dnwell 1187 | grow 840 1188 | and-not nwell,dnwell 1189 | grow 840 1190 | and-not nwell,dnwell 1191 | grow 840 1192 | and-not nwell,dnwell 1193 | grow 840 1194 | and-not nwell,dnwell 1195 | grow 840 1196 | and-not nwell,dnwell 1197 | grow 840 1198 | and-not nwell,dnwell 1199 | grow 840 1200 | and-not nwell,dnwell 1201 | grow 840 1202 | and-not nwell,dnwell 1203 | grow 840 1204 | and-not nwell,dnwell 1205 | grow 840 1206 | and-not nwell,dnwell 1207 | grow 840 1208 | and-not nwell,dnwell 1209 | grow 840 1210 | and-not nwell,dnwell 1211 | grow 840 1212 | and-not nwell,dnwell 1213 | grow 840 1214 | and-not nwell,dnwell 1215 | grow 635 1216 | and-not nwell,dnwell 1217 | 1218 | templayer ptap_missing *ndiff,*mvndiff 1219 | and-not dnwell 1220 | and-not ptap_reach 1221 | 1222 | templayer ntap_reach nsc,mvnsc 1223 | # grow total is 15um. grow in 1.27um increments to ensure that 1224 | # no nwell ring is crossed. There is no difference between 1225 | # ntaps in and out of deep nwell. 1226 | grow 1270 1227 | and nwell 1228 | grow 1270 1229 | and nwell 1230 | grow 1270 1231 | and nwell 1232 | grow 1270 1233 | and nwell 1234 | grow 1270 1235 | and nwell 1236 | grow 1270 1237 | and nwell 1238 | grow 1270 1239 | and nwell 1240 | grow 1270 1241 | and nwell 1242 | grow 1270 1243 | and nwell 1244 | grow 1270 1245 | and nwell 1246 | grow 1270 1247 | and nwell 1248 | grow 945 1249 | and nwell 1250 | 1251 | templayer ntap_missing *pdiff,*mvpdiff 1252 | and-not dnwell 1253 | and-not ntap_reach 1254 | 1255 | templayer dptap_reach psc,mvpsc 1256 | and dnwell 1257 | grow 840 1258 | and-not nwell 1259 | and dnwell 1260 | grow 840 1261 | and-not nwell 1262 | and dnwell 1263 | grow 840 1264 | and-not nwell 1265 | and dnwell 1266 | grow 840 1267 | and-not nwell 1268 | and dnwell 1269 | grow 840 1270 | and-not nwell 1271 | and dnwell 1272 | grow 840 1273 | and-not nwell 1274 | and dnwell 1275 | grow 840 1276 | and-not nwell 1277 | and dnwell 1278 | grow 840 1279 | and-not nwell 1280 | and dnwell 1281 | grow 840 1282 | and-not nwell 1283 | and dnwell 1284 | grow 840 1285 | and-not nwell 1286 | and dnwell 1287 | grow 840 1288 | and-not nwell 1289 | and dnwell 1290 | grow 840 1291 | and-not nwell 1292 | and dnwell 1293 | grow 840 1294 | and-not nwell 1295 | and dnwell 1296 | grow 840 1297 | and-not nwell 1298 | and dnwell 1299 | grow 840 1300 | and-not nwell 1301 | and dnwell 1302 | grow 840 1303 | and-not nwell 1304 | and dnwell 1305 | grow 840 1306 | and-not nwell 1307 | and dnwell 1308 | grow 635 1309 | and-not nwell 1310 | and dnwell 1311 | 1312 | templayer dptap_missing *ndiff,*mvndiff 1313 | and dnwell 1314 | and-not dptap_reach 1315 | 1316 | templayer m1_small_hole *m1 1317 | close 140000 1318 | 1319 | templayer m1_hole_empty m1_small_hole 1320 | and-not *m1 1321 | 1322 | templayer m2_small_hole *m2 1323 | close 140000 1324 | 1325 | templayer m2_hole_empty m2_small_hole 1326 | and-not *m2 1327 | 1328 | 1329 | end 1330 | 1331 | #----------------------------------------------------------------------- 1332 | cifinput 1333 | #----------------------------------------------------------------------- 1334 | # NOTE: All values in this section MUST be multiples of 25 1335 | # or else magic will scale below the allowed layout grid size 1336 | #----------------------------------------------------------------------- 1337 | 1338 | style vendorimport 1339 | scalefactor 10 nanometers 1340 | gridlimit 5 1341 | 1342 | options ignore-unknown-layer-labels no-reconnect-labels 1343 | 1344 | ignore NPC 1345 | ignore SEALID 1346 | ignore NPNID 1347 | ignore PNPID 1348 | ignore CAPID 1349 | ignore LDNTM 1350 | ignore HVNTM 1351 | ignore POLYMOD 1352 | ignore LOWTAPDENSITY 1353 | 1354 | layer nwell NWELL,WELLTXT,WELLPIN 1355 | labels NWELL 1356 | labels WELLTXT text 1357 | labels WELLPIN port 1358 | 1359 | layer pwell SUBTXT,SUBPIN 1360 | labels SUBTXT text 1361 | labels SUBPIN port 1362 | 1363 | layer dnwell DNWELL 1364 | labels DNWELL 1365 | 1366 | layer rpw PWRES 1367 | and DNWELL 1368 | labels PWRES 1369 | 1370 | templayer ndiffarea DIFF,DIFFTXT,DIFFPIN 1371 | and-not POLY 1372 | and-not NWELL 1373 | and-not PPLUS 1374 | and-not DIODE 1375 | and-not DIFFRES 1376 | and-not THKOX 1377 | and NPLUS 1378 | copyup ndifcheck 1379 | labels DIFF 1380 | labels DIFFTXT text 1381 | labels DIFFPIN port 1382 | labels TAPPIN port 1383 | 1384 | layer ndiff ndiffarea 1385 | 1386 | # Copy ndiff areas up for contact checks 1387 | templayer xndifcheck ndifcheck 1388 | copyup ndifcheck 1389 | 1390 | templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN 1391 | and-not POLY 1392 | and-not NWELL 1393 | and-not PPLUS 1394 | and-not DIODE 1395 | and-not DIFFRES 1396 | and THKOX 1397 | and NPLUS 1398 | copyup ndifcheck 1399 | labels DIFF 1400 | labels DIFFTXT text 1401 | labels DIFFPIN port 1402 | 1403 | layer mvndiff mvndiffarea 1404 | 1405 | # Copy ndiff areas up for contact checks 1406 | templayer mvxndifcheck mvndifcheck 1407 | copyup mvndifcheck 1408 | 1409 | layer ndiode DIFF 1410 | and NPLUS 1411 | and DIODE 1412 | and-not NWELL 1413 | and-not POLY 1414 | and-not PPLUS 1415 | and-not THKOX 1416 | and-not LVTN 1417 | labels DIFF 1418 | 1419 | layer ndiodelvt DIFF 1420 | and NPLUS 1421 | and DIODE 1422 | and-not NWELL 1423 | and-not POLY 1424 | and-not PPLUS 1425 | and-not THKOX 1426 | and LVTN 1427 | labels DIFF 1428 | 1429 | templayer ndiodearea DIODE 1430 | and NPLUS 1431 | and-not THKOX 1432 | and-not NWELL 1433 | copyup DIODE,NPLUS 1434 | 1435 | layer ndiffres DIFFRES 1436 | and NPLUS 1437 | and-not THKOX 1438 | labels DIFF 1439 | 1440 | templayer pdiffarea DIFF,DIFFTXT,DIFFPIN 1441 | and-not POLY 1442 | and NWELL 1443 | and-not NPLUS 1444 | and-not DIODE 1445 | and-not THKOX 1446 | and PPLUS 1447 | copyup pdifcheck 1448 | labels DIFF 1449 | labels DIFFTXT text 1450 | labels DIFFPIN port 1451 | 1452 | layer pdiff pdiffarea 1453 | 1454 | layer mvndiode DIFF 1455 | and NPLUS 1456 | and DIODE 1457 | and THKOX 1458 | and-not POLY 1459 | and-not PPLUS 1460 | and-not LVTN 1461 | labels DIFF 1462 | 1463 | layer nndiode DIFF 1464 | and NPLUS 1465 | and DIODE 1466 | and THKOX 1467 | and-not POLY 1468 | and-not PPLUS 1469 | and LVTN 1470 | labels DIFF 1471 | 1472 | templayer mvndiodearea DIODE 1473 | and NPLUS 1474 | and THKOX 1475 | and-not NWELL 1476 | copyup DIODE,NPLUS 1477 | 1478 | layer mvndiffres DIFFRES 1479 | and NPLUS 1480 | and THKOX 1481 | labels DIFF 1482 | 1483 | templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN 1484 | and-not POLY 1485 | and NWELL 1486 | and-not NPLUS 1487 | and THKOX 1488 | and-not DIODE 1489 | and-not DIFFRES 1490 | and PPLUS 1491 | copyup mvpdifcheck 1492 | labels DIFF 1493 | labels DIFFTXT text 1494 | labels DIFFPIN port 1495 | 1496 | layer mvpdiff mvpdiffarea 1497 | 1498 | # Copy pdiff areas up for contact checks 1499 | templayer xpdifcheck pdifcheck 1500 | copyup pdifcheck 1501 | 1502 | layer pdiode DIFF 1503 | and PPLUS 1504 | and-not POLY 1505 | and-not NPLUS 1506 | and-not THKOX 1507 | and-not LVTN 1508 | and-not HVTP 1509 | and DIODE 1510 | labels DIFF 1511 | 1512 | layer pdiodelvt DIFF 1513 | and PPLUS 1514 | and-not POLY 1515 | and-not NPLUS 1516 | and-not THKOX 1517 | and LVTN 1518 | and-not HVTP 1519 | and DIODE 1520 | labels DIFF 1521 | 1522 | layer pdiodehvt DIFF 1523 | and PPLUS 1524 | and-not POLY 1525 | and-not NPLUS 1526 | and-not THKOX 1527 | and-not LVTN 1528 | and HVTP 1529 | and DIODE 1530 | labels DIFF 1531 | 1532 | templayer pdiodearea DIODE 1533 | and PPLUS 1534 | and-not THKOX 1535 | copyup DIODE,PPLUS 1536 | 1537 | # Define pfet areas as known pdiff, regardless of the presence of a well. 1538 | 1539 | templayer pfetarea DIFF 1540 | and-not NPLUS 1541 | and-not THKOX 1542 | and POLY 1543 | 1544 | layer pfet pfetarea 1545 | and-not LVTN 1546 | and-not HVTP 1547 | and-not STDCELL 1548 | labels DIFF 1549 | 1550 | layer scpfet pfetarea 1551 | and-not LVTN 1552 | and-not HVTP 1553 | and STDCELL 1554 | labels DIFF 1555 | 1556 | layer pfetlvt pfetarea 1557 | and LVTN 1558 | labels DIFF 1559 | 1560 | layer pfethvt pfetarea 1561 | and HVTP 1562 | labels DIFF 1563 | 1564 | # Always force nwell under pfet (nwell encloses pdiff by 0.18) 1565 | layer nwell pfetarea 1566 | grow 180 1567 | 1568 | # Copy mvpdiff areas up for contact checks 1569 | templayer mvxpdifcheck mvpdifcheck 1570 | copyup mvpdifcheck 1571 | 1572 | layer mvpdiode DIFF 1573 | and PPLUS 1574 | and-not POLY 1575 | and-not NPLUS 1576 | and THKOX 1577 | and DIODE 1578 | labels DIFF 1579 | 1580 | templayer mvpdiodearea DIODE 1581 | and PPLUS 1582 | and THKOX 1583 | copyup DIODE,PPLUS 1584 | 1585 | # Define pfet areas as known pdiff, 1586 | # regardless of the presence of a 1587 | # well. 1588 | 1589 | templayer mvpfetarea DIFF 1590 | and-not NPLUS 1591 | and THKOX 1592 | and POLY 1593 | 1594 | layer mvpfet mvpfetarea 1595 | labels DIFF 1596 | 1597 | layer pdiff DIFF,DIFFTXT,DIFFPIN 1598 | and-not NPLUS 1599 | and-not POLY 1600 | and-not THKOX 1601 | and-not DIODE 1602 | and-not DIFFRES 1603 | labels DIFF 1604 | labels DIFFTXT text 1605 | labels DIFFPIN port 1606 | 1607 | layer pdiffres DIFFRES 1608 | and PPLUS 1609 | and NWELL 1610 | and-not THKOX 1611 | labels DIFF 1612 | 1613 | layer nfet DIFF 1614 | and POLY 1615 | and-not PPLUS 1616 | and NPLUS 1617 | and-not THKOX 1618 | and-not LVTN 1619 | and-not SONOS 1620 | and-not STDCELL 1621 | labels DIFF 1622 | 1623 | layer scnfet DIFF 1624 | and POLY 1625 | and-not PPLUS 1626 | and NPLUS 1627 | and-not THKOX 1628 | and-not LVTN 1629 | and-not SONOS 1630 | and STDCELL 1631 | labels DIFF 1632 | 1633 | layer nfetlvt DIFF 1634 | and POLY 1635 | and-not PPLUS 1636 | and NPLUS 1637 | and-not THKOX 1638 | and LVTN 1639 | and-not SONOS 1640 | labels DIFF 1641 | 1642 | layer nsonos DIFF 1643 | and POLY 1644 | and-not PPLUS 1645 | and NPLUS 1646 | and-not THKOX 1647 | and LVTN 1648 | and SONOS 1649 | labels DIFF 1650 | 1651 | templayer nsdarea DIFF 1652 | and NPLUS 1653 | and NWELL 1654 | and-not POLY 1655 | and-not PPLUS 1656 | and-not THKOX 1657 | copyup nsubcheck 1658 | 1659 | layer nsd nsdarea 1660 | labels DIFF 1661 | 1662 | layer nsd TAP,TAPPIN 1663 | and NPLUS 1664 | labels TAP 1665 | labels TAPPIN port 1666 | 1667 | templayer nsdexpand nsdarea 1668 | grow 500 1669 | 1670 | # Copy nsub areas up for contact checks 1671 | templayer xnsubcheck nsubcheck 1672 | copyup nsubcheck 1673 | 1674 | templayer psdarea DIFF 1675 | and PPLUS 1676 | and-not NWELL 1677 | and-not POLY 1678 | and-not NPLUS 1679 | and-not THKOX 1680 | and-not pfetexpand 1681 | copyup psubcheck 1682 | 1683 | layer psd psdarea 1684 | labels DIFF 1685 | 1686 | layer psd TAP,TAPPIN 1687 | and PPLUS 1688 | and-not THKOX 1689 | labels TAP 1690 | labels TAPPIN port 1691 | 1692 | templayer psdexpand psdarea 1693 | grow 500 1694 | 1695 | layer mvpdiff DIFF,DIFFTXT,DIFFPIN 1696 | and-not NPLUS 1697 | and-not POLY 1698 | and THKOX 1699 | and mvpfetexpand 1700 | labels DIFF 1701 | labels DIFFTXT text 1702 | labels DIFFPIN port 1703 | 1704 | layer mvpdiffres DIFFRES 1705 | and PPLUS 1706 | and NWELL 1707 | and THKOX 1708 | and-not mvrdpioedge 1709 | labels DIFF 1710 | 1711 | layer mvnfet DIFF 1712 | and POLY 1713 | and-not PPLUS 1714 | and NPLUS 1715 | and-not LVTN 1716 | and THKOX 1717 | labels DIFF 1718 | 1719 | layer mvnnfet DIFF 1720 | and POLY 1721 | and-not PPLUS 1722 | and NPLUS 1723 | and LVTN 1724 | and THKOX 1725 | labels DIFF 1726 | 1727 | templayer mvnsdarea DIFF 1728 | and NPLUS 1729 | and NWELL 1730 | and-not POLY 1731 | and-not PPLUS 1732 | and THKOX 1733 | copyup mvnsubcheck 1734 | 1735 | layer mvnsd mvnsdarea 1736 | labels DIFF 1737 | 1738 | layer mvnsd TAP,TAPPIN 1739 | and NPLUS 1740 | and THKOX 1741 | labels TAP 1742 | labels TAPPIN port 1743 | 1744 | templayer mvnsdexpand mvnsdarea 1745 | grow 500 1746 | 1747 | # Copy nsub areas up for contact checks 1748 | templayer mvxnsubcheck mvnsubcheck 1749 | copyup mvnsubcheck 1750 | 1751 | templayer mvpsdarea DIFF 1752 | and PPLUS 1753 | and-not NWELL 1754 | and-not POLY 1755 | and-not NPLUS 1756 | and THKOX 1757 | and-not mvpfetexpand 1758 | copyup mvpsubcheck 1759 | 1760 | layer mvpsd mvpsdarea 1761 | labels DIFF 1762 | 1763 | layer mvpsd TAP,TAPPIN 1764 | and PPLUS 1765 | and THKOX 1766 | labels TAP 1767 | labels TAPPIN port 1768 | 1769 | templayer mvpsdexpand mvpsdarea 1770 | grow 500 1771 | 1772 | # Copy psub areas up for contact checks 1773 | templayer xpsubcheck psubcheck 1774 | copyup psubcheck 1775 | 1776 | templayer mvxpsubcheck mvpsubcheck 1777 | copyup mvpsubcheck 1778 | 1779 | layer psd DIFF 1780 | and-not PPLUS 1781 | and-not NPLUS 1782 | and-not POLY 1783 | and-not THKOX 1784 | and-not pfetexpand 1785 | and psdexpand 1786 | 1787 | layer nsd DIFF 1788 | and-not PPLUS 1789 | and-not NPLUS 1790 | and-not POLY 1791 | and-not THKOX 1792 | and nsdexpand 1793 | 1794 | layer mvpsd DIFF 1795 | and-not PPLUS 1796 | and-not NPLUS 1797 | and-not POLY 1798 | and THKOX 1799 | and-not mvpfetexpand 1800 | and mvpsdexpand 1801 | 1802 | layer mvnsd DIFF 1803 | and-not PPLUS 1804 | and-not NPLUS 1805 | and-not POLY 1806 | and THKOX 1807 | and mvnsdexpand 1808 | 1809 | templayer hresarea POLY 1810 | and RPM 1811 | grow 3000 1812 | 1813 | templayer uresarea POLY 1814 | and URPM 1815 | grow 3000 1816 | 1817 | templayer diffresarea DIFFRES 1818 | and-not THKOX 1819 | grow 3000 1820 | 1821 | templayer mvdiffresarea DIFFRES 1822 | and THKOX 1823 | grow 3000 1824 | 1825 | templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea 1826 | 1827 | layer pfet POLY 1828 | and DIFF 1829 | and diffresarea 1830 | and-not NPLUS 1831 | and-not STDCELL 1832 | 1833 | layer scpfet POLY 1834 | and DIFF 1835 | and diffresarea 1836 | and-not NPLUS 1837 | and STDCELL 1838 | 1839 | templayer xpolyterm RPM,URPM 1840 | and POLY 1841 | and-not POLYRES 1842 | # add back the 0.06um contact surround in the direction of the resistor 1843 | grow 60 1844 | and POLY 1845 | 1846 | layer xpc xpolyterm 1847 | 1848 | templayer polyarea POLY 1849 | and-not POLYRES 1850 | and-not POLYSHORT 1851 | and-not DIFF 1852 | and-not RPM 1853 | and-not URPM 1854 | copyup polycheck 1855 | 1856 | layer poly polyarea,POLYTXT,POLYPIN 1857 | labels POLY 1858 | labels POLYTXT text 1859 | labels POLYPIN port 1860 | 1861 | # Copy (non-resistor) poly areas up for contact checks 1862 | templayer xpolycheck polycheck 1863 | copyup polycheck 1864 | 1865 | layer mrp1 POLY 1866 | and POLYRES 1867 | and-not RPM 1868 | and-not URPM 1869 | labels POLY 1870 | 1871 | layer rmp POLY 1872 | and POLYSHORT 1873 | labels POLY 1874 | 1875 | layer xhrpoly POLY 1876 | and POLYRES 1877 | and RPM 1878 | and-not URPM 1879 | and PPLUS 1880 | and NPC 1881 | and-not xpolyterm 1882 | labels POLY 1883 | 1884 | layer uhrpoly POLY 1885 | and POLYRES 1886 | and URPM 1887 | and-not RPM 1888 | and NPC 1889 | and-not xpolyterm 1890 | labels POLY 1891 | 1892 | templayer ndcbase CONT 1893 | and DIFF 1894 | and NPLUS 1895 | and-not NWELL 1896 | and LI 1897 | and-not THKOX 1898 | 1899 | layer ndc ndcbase 1900 | grow 85 1901 | shrink 85 1902 | shrink 85 1903 | grow 85 1904 | or ndcbase 1905 | labels CONT 1906 | 1907 | templayer nscbase CONT 1908 | and DIFF,TAP 1909 | and NPLUS 1910 | and NWELL 1911 | and LI 1912 | and-not THKOX 1913 | 1914 | layer nsc nscbase 1915 | grow 85 1916 | shrink 85 1917 | shrink 85 1918 | grow 85 1919 | or nscbase 1920 | labels CONT 1921 | 1922 | templayer pdcbase CONT 1923 | and DIFF 1924 | and PPLUS 1925 | and NWELL 1926 | and LI 1927 | and-not THKOX 1928 | 1929 | layer pdc pdcbase 1930 | grow 85 1931 | shrink 85 1932 | shrink 85 1933 | grow 85 1934 | or pdcbase 1935 | labels CONT 1936 | 1937 | templayer pdcnowell CONT 1938 | and DIFF 1939 | and PPLUS 1940 | and pfetexpand 1941 | and LI 1942 | and-not THKOX 1943 | 1944 | layer pdc pdcnowell 1945 | grow 85 1946 | shrink 85 1947 | shrink 85 1948 | grow 85 1949 | or pdcnowell 1950 | labels CONT 1951 | 1952 | templayer pscbase CONT 1953 | and DIFF,TAP 1954 | and PPLUS 1955 | and-not NWELL 1956 | and-not pfetexpand 1957 | and LI 1958 | and-not THKOX 1959 | 1960 | layer psc pscbase 1961 | grow 85 1962 | shrink 85 1963 | shrink 85 1964 | grow 85 1965 | or pscbase 1966 | labels CONT 1967 | 1968 | templayer pcbase CONT 1969 | and POLY 1970 | and-not DIFF 1971 | and-not RPM,URPM 1972 | and LI 1973 | 1974 | layer pc pcbase 1975 | grow 85 1976 | shrink 85 1977 | shrink 85 1978 | grow 85 1979 | or pcbase 1980 | labels CONT 1981 | 1982 | templayer ndicbase CONT 1983 | and DIFF 1984 | and NPLUS 1985 | and DIODE 1986 | and-not POLY 1987 | and-not PPLUS 1988 | and-not THKOX 1989 | and-not LVTN 1990 | 1991 | layer ndic ndicbase 1992 | grow 85 1993 | shrink 85 1994 | shrink 85 1995 | grow 85 1996 | or ndicbase 1997 | labels CONT 1998 | 1999 | templayer ndilvtcbase CONT 2000 | and DIFF 2001 | and NPLUS 2002 | and DIODE 2003 | and-not POLY 2004 | and-not PPLUS 2005 | and-not THKOX 2006 | and LVTN 2007 | 2008 | layer ndilvtc ndilvtcbase 2009 | grow 85 2010 | shrink 85 2011 | shrink 85 2012 | grow 85 2013 | or ndilvtcbase 2014 | labels CONT 2015 | 2016 | templayer pdicbase CONT 2017 | and DIFF 2018 | and PPLUS 2019 | and DIODE 2020 | and-not POLY 2021 | and-not NPLUS 2022 | and-not THKOX 2023 | and-not LVTN 2024 | and-not HVTP 2025 | 2026 | layer pdic pdicbase 2027 | grow 85 2028 | shrink 85 2029 | shrink 85 2030 | grow 85 2031 | or pdicbase 2032 | labels CONT 2033 | 2034 | templayer pdilvtcbase CONT 2035 | and DIFF 2036 | and PPLUS 2037 | and DIODE 2038 | and-not POLY 2039 | and-not NPLUS 2040 | and-not THKOX 2041 | and LVTN 2042 | and-not HVTP 2043 | 2044 | layer pdilvtc pdilvtcbase 2045 | grow 85 2046 | shrink 85 2047 | shrink 85 2048 | grow 85 2049 | or pdilvtcbase 2050 | labels CONT 2051 | 2052 | templayer pdihvtcbase CONT 2053 | and DIFF 2054 | and PPLUS 2055 | and DIODE 2056 | and-not POLY 2057 | and-not NPLUS 2058 | and-not THKOX 2059 | and-not LVTN 2060 | and HVTP 2061 | 2062 | layer pdihvtc pdihvtcbase 2063 | grow 85 2064 | shrink 85 2065 | shrink 85 2066 | grow 85 2067 | or pdihvtcbase 2068 | labels CONT 2069 | 2070 | templayer mvndcbase CONT 2071 | and DIFF 2072 | and NPLUS 2073 | and-not NWELL 2074 | and LI 2075 | and THKOX 2076 | 2077 | layer mvndc mvndcbase 2078 | grow 85 2079 | shrink 85 2080 | shrink 85 2081 | grow 85 2082 | or mvndcbase 2083 | labels CONT 2084 | 2085 | templayer mvnscbase CONT 2086 | and DIFF,TAP 2087 | and NPLUS 2088 | and NWELL 2089 | and LI 2090 | and THKOX 2091 | 2092 | layer mvnsc mvnscbase 2093 | grow 85 2094 | shrink 85 2095 | shrink 85 2096 | grow 85 2097 | or mvnscbase 2098 | labels CONT 2099 | 2100 | templayer mvpdcbase CONT 2101 | and DIFF 2102 | and PPLUS 2103 | and NWELL 2104 | and LI 2105 | and THKOX 2106 | 2107 | layer mvpdc mvpdcbase 2108 | grow 85 2109 | shrink 85 2110 | shrink 85 2111 | grow 85 2112 | or mvpdcbase 2113 | labels CONT 2114 | 2115 | templayer mvpdcnowell CONT 2116 | and DIFF 2117 | and PPLUS 2118 | and mvpfetexpand 2119 | and MET1 2120 | and THKOX 2121 | 2122 | layer mvpdc mvpdcnowell 2123 | grow 85 2124 | shrink 85 2125 | shrink 85 2126 | grow 85 2127 | or mvpdcnowell 2128 | labels CONT 2129 | 2130 | templayer mvpscbase CONT 2131 | and DIFF,TAP 2132 | and PPLUS 2133 | and-not NWELL 2134 | and-not mvpfetexpand 2135 | and LI 2136 | and THKOX 2137 | 2138 | layer mvpsc mvpscbase 2139 | grow 85 2140 | shrink 85 2141 | shrink 85 2142 | grow 85 2143 | or mvpscbase 2144 | labels CONT 2145 | 2146 | templayer mvndicbase CONT 2147 | and DIFF 2148 | and NPLUS 2149 | and DIODE 2150 | and-not POLY 2151 | and-not PPLUS 2152 | and-not LVTN 2153 | and THKOX 2154 | 2155 | layer mvndic mvndicbase 2156 | grow 85 2157 | shrink 85 2158 | shrink 85 2159 | grow 85 2160 | or mvndicbase 2161 | labels CONT 2162 | 2163 | templayer nndicbase CONT 2164 | and DIFF 2165 | and NPLUS 2166 | and DIODE 2167 | and-not POLY 2168 | and-not PPLUS 2169 | and LVTN 2170 | and THKOX 2171 | 2172 | layer nndic nndicbase 2173 | grow 85 2174 | shrink 85 2175 | shrink 85 2176 | grow 85 2177 | or nndicbase 2178 | labels CONT 2179 | 2180 | templayer mvpdicbase CONT 2181 | and DIFF 2182 | and PPLUS 2183 | and DIODE 2184 | and-not POLY 2185 | and-not NPLUS 2186 | and THKOX 2187 | 2188 | layer mvpdic mvpdicbase 2189 | grow 85 2190 | shrink 85 2191 | shrink 85 2192 | grow 85 2193 | or mvpdicbase 2194 | labels CONT 2195 | 2196 | layer locali LI,LITXT,LIPIN 2197 | and-not LIRES,LISHORT 2198 | and-not COREID 2199 | labels LI 2200 | labels LITXT text 2201 | labels LIPIN port 2202 | 2203 | layer coreli LI,LITXT,LIPIN 2204 | and-not LIRES,LISHORT 2205 | and COREID 2206 | labels LI 2207 | labels LITXT text 2208 | labels LIPIN port 2209 | 2210 | layer rli LI 2211 | and LIRES,LISHORT 2212 | labels LIRES,LISHORT 2213 | 2214 | layer lic MCON 2215 | grow 95 2216 | shrink 95 2217 | shrink 85 2218 | grow 85 2219 | or MCON 2220 | labels MCON 2221 | 2222 | layer m1 MET1,MET1TXT,MET1PIN 2223 | and-not MET1RES,MET1SHORT 2224 | labels MET1 2225 | labels MET1TXT text 2226 | labels MET1PIN port 2227 | 2228 | layer rm1 MET1 2229 | and MET1RES,MET1SHORT 2230 | labels MET1RES,MET1SHORT 2231 | 2232 | layer mimcap MET3 2233 | and CAPM 2234 | labels CAPM 2235 | 2236 | layer mimcc VIA3 2237 | and CAPM 2238 | grow 60 2239 | grow 40 2240 | shrink 40 2241 | labels CAPM 2242 | 2243 | layer mimcap2 MET4 2244 | and CAPM2 2245 | labels CAPM2 2246 | 2247 | layer mim2cc VIA4 2248 | and CAPM2 2249 | grow 190 2250 | grow 210 2251 | shrink 210 2252 | labels CAPM2 2253 | 2254 | 2255 | templayer m2cbase VIA1 2256 | grow 55 2257 | 2258 | layer m2c m2cbase 2259 | grow 30 2260 | shrink 30 2261 | shrink 130 2262 | grow 130 2263 | or m2cbase 2264 | 2265 | layer m2 MET2,MET2TXT,MET2PIN 2266 | and-not MET2RES,MET2SHORT 2267 | labels MET2 2268 | labels MET2TXT text 2269 | labels MET2PIN port 2270 | 2271 | layer rm2 MET2 2272 | and MET2RES,MET2SHORT 2273 | labels MET2RES,MET2SHORT 2274 | 2275 | templayer m3cbase VIA2 2276 | grow 40 2277 | 2278 | layer m3c m3cbase 2279 | grow 60 2280 | shrink 60 2281 | shrink 140 2282 | grow 140 2283 | or m3cbase 2284 | 2285 | layer m3 MET3,MET3TXT,MET3PIN 2286 | and-not MET3RES,MET3SHORT 2287 | and-not CAPM 2288 | labels MET3 2289 | labels MET3TXT text 2290 | labels MET3PIN port 2291 | 2292 | layer rm3 MET3 2293 | and MET3RES,MET3SHORT 2294 | labels MET3RES,MET3SHORT 2295 | 2296 | 2297 | templayer via3base VIA3 2298 | and-not CAPM 2299 | grow 60 2300 | 2301 | layer via3 via3base 2302 | grow 40 2303 | shrink 40 2304 | shrink 160 2305 | grow 160 2306 | or via3base 2307 | 2308 | layer m4 MET4,MET4TXT,MET4PIN 2309 | and-not MET4RES,MET4SHORT 2310 | and-not CAPM2 2311 | labels MET4 2312 | labels MET4TXT text 2313 | labels MET4PIN port 2314 | 2315 | layer rm4 MET4 2316 | and MET4RES,MET4SHORT 2317 | labels MET4RES,MET4SHORT 2318 | 2319 | layer m5 MET5,MET5TXT,MET5PIN 2320 | and-not MET5RES,MET5SHORT 2321 | labels MET5 2322 | labels MET5TXT text 2323 | labels MET5PIN port 2324 | 2325 | layer rm5 MET5 2326 | and MET5RES,MET5SHORT 2327 | labels MET5RES,MET5SHORT 2328 | 2329 | templayer via4base VIA4 2330 | and-not CAPM2 2331 | grow 190 2332 | 2333 | layer via4 via4base 2334 | grow 210 2335 | shrink 210 2336 | shrink 590 2337 | grow 590 2338 | or via4base 2339 | 2340 | 2341 | # Find diffusion not covered in 2342 | # NPLUS or PPLUS and pull it into 2343 | # the next layer up 2344 | 2345 | templayer gentrans DIFF 2346 | and-not PPLUS 2347 | and-not NPLUS 2348 | and POLY 2349 | copyup DIFF,POLY 2350 | 2351 | templayer gendiff DIFF,TAP 2352 | and-not PPLUS 2353 | and-not NPLUS 2354 | and-not POLY 2355 | copyup DIFF 2356 | 2357 | # Handle contacts found by copyup 2358 | 2359 | templayer ndiccopy CONT 2360 | and LI 2361 | and DIODE 2362 | and NPLUS 2363 | and-not THKOX 2364 | 2365 | layer ndic ndiccopy 2366 | grow 85 2367 | shrink 85 2368 | shrink 85 2369 | grow 85 2370 | or ndiccopy 2371 | labels CONT 2372 | 2373 | templayer mvndiccopy CONT 2374 | and LI 2375 | and DIODE 2376 | and NPLUS 2377 | and THKOX 2378 | 2379 | layer mvndic mvndiccopy 2380 | grow 85 2381 | shrink 85 2382 | shrink 85 2383 | grow 85 2384 | or mvndiccopy 2385 | labels CONT 2386 | 2387 | templayer pdiccopy CONT 2388 | and LI 2389 | and DIODE 2390 | and PPLUS 2391 | and-not THKOX 2392 | 2393 | layer pdic pdiccopy 2394 | grow 85 2395 | shrink 85 2396 | shrink 85 2397 | grow 85 2398 | or pdiccopy 2399 | labels CONT 2400 | 2401 | templayer mvpdiccopy CONT 2402 | and LI 2403 | and DIODE 2404 | and PPLUS 2405 | and THKOX 2406 | 2407 | layer mvpdic mvpdiccopy 2408 | grow 85 2409 | shrink 85 2410 | shrink 85 2411 | grow 85 2412 | or mvpdiccopy 2413 | labels CONT 2414 | 2415 | templayer ndccopy CONT 2416 | and ndifcheck 2417 | 2418 | layer ndc ndccopy 2419 | grow 85 2420 | shrink 85 2421 | shrink 85 2422 | grow 85 2423 | or ndccopy 2424 | labels CONT 2425 | 2426 | templayer mvndccopy CONT 2427 | and mvndifcheck 2428 | 2429 | layer mvndc mvndccopy 2430 | grow 85 2431 | shrink 85 2432 | shrink 85 2433 | grow 85 2434 | or mvndccopy 2435 | labels CONT 2436 | 2437 | templayer pdccopy CONT 2438 | and pdifcheck 2439 | 2440 | layer pdc pdccopy 2441 | grow 85 2442 | shrink 85 2443 | shrink 85 2444 | grow 85 2445 | or pdccopy 2446 | labels CONT 2447 | 2448 | templayer mvpdccopy CONT 2449 | and mvpdifcheck 2450 | 2451 | layer mvpdc mvpdccopy 2452 | grow 85 2453 | shrink 85 2454 | shrink 85 2455 | grow 85 2456 | or mvpdccopy 2457 | labels CONT 2458 | 2459 | templayer pccopy CONT 2460 | and polycheck 2461 | 2462 | layer pc pccopy 2463 | grow 85 2464 | shrink 85 2465 | shrink 85 2466 | grow 85 2467 | or pccopy 2468 | labels CONT 2469 | 2470 | templayer nsccopy CONT 2471 | and nsubcheck 2472 | 2473 | layer nsc nsccopy 2474 | grow 85 2475 | shrink 85 2476 | shrink 85 2477 | grow 85 2478 | or nsccopy 2479 | labels CONT 2480 | 2481 | templayer mvnsccopy CONT 2482 | and mvnsubcheck 2483 | 2484 | layer mvnsc mvnsccopy 2485 | grow 85 2486 | shrink 85 2487 | shrink 85 2488 | grow 85 2489 | or mvnsccopy 2490 | labels CONT 2491 | 2492 | templayer psccopy CONT 2493 | and psubcheck 2494 | 2495 | layer psc psccopy 2496 | grow 85 2497 | shrink 85 2498 | shrink 85 2499 | grow 85 2500 | or psccopy 2501 | labels CONT 2502 | 2503 | templayer mvpsccopy CONT 2504 | and mvpsubcheck 2505 | 2506 | layer mvpsc mvpsccopy 2507 | grow 85 2508 | shrink 85 2509 | shrink 85 2510 | grow 85 2511 | or mvpsccopy 2512 | labels CONT 2513 | 2514 | # Find contacts not covered in 2515 | # metal and pull them into the 2516 | # next layer up 2517 | 2518 | templayer gencont CONT 2519 | and LI 2520 | and-not DIFF,TAP 2521 | and-not POLY 2522 | and-not DIODE 2523 | and-not nsubcheck 2524 | and-not psubcheck 2525 | and-not mvnsubcheck 2526 | and-not mvpsubcheck 2527 | copyup CONT,LI 2528 | 2529 | templayer barecont CONT 2530 | and-not LI 2531 | and-not nsubcheck 2532 | and-not psubcheck 2533 | and-not mvnsubcheck 2534 | and-not mvpsubcheck 2535 | copyup CONT 2536 | 2537 | layer glass GLASS,PADTXT,PADPIN 2538 | labels GLASS 2539 | labels PADTXT text 2540 | labels PADPIN port 2541 | 2542 | templayer boundary BOUND,STDCELL,PADCELL 2543 | boundary 2544 | 2545 | layer comment LVSTEXT 2546 | labels LVSTEXT text 2547 | 2548 | layer comment TTEXT 2549 | labels TTEXT text 2550 | 2551 | layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4 2552 | labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4 2553 | 2554 | # MOS Varactor 2555 | 2556 | layer var POLY 2557 | and DIFF 2558 | and NPLUS 2559 | and NWELL 2560 | and-not THKOX 2561 | and-not HVTP 2562 | grow 25 2563 | labels POLY 2564 | 2565 | layer varhvt POLY 2566 | and DIFF 2567 | and NPLUS 2568 | and NWELL 2569 | and-not THKOX 2570 | and HVTP 2571 | grow 25 2572 | labels POLY 2573 | 2574 | layer mvvar POLY 2575 | and DIFF 2576 | and NPLUS 2577 | and NWELL 2578 | and THKOX 2579 | grow 25 2580 | labels POLY 2581 | 2582 | calma NWELL 64 20 2583 | calma DIFF 65 20 2584 | calma DNWELL 64 18 2585 | calma PWRES 64 13 2586 | calma TAP 65 44 2587 | # LVTN 2588 | calma LVTN 125 44 2589 | # HVTP 2590 | calma HVTP 78 44 2591 | # SONOS (TUNM) 2592 | calma SONOS 80 20 2593 | # NPLUS = NSDM 2594 | calma NPLUS 93 44 2595 | # PPLUS = PSDM 2596 | calma PPLUS 94 20 2597 | # HVI 2598 | calma THKOX 75 20 2599 | # NPC 2600 | calma NPC 95 20 2601 | # P+ POLY MASK 2602 | calma RPM 86 20 2603 | calma URPM 79 20 2604 | calma LDNTM 11 44 2605 | calma HVNTM 125 20 2606 | # Poly resistor ID mark 2607 | calma POLYRES 66 13 2608 | # Diffusion resistor ID mark 2609 | calma DIFFRES 65 13 2610 | calma POLY 66 20 2611 | calma POLYMOD 66 83 2612 | # Diode ID mark 2613 | calma DIODE 81 23 2614 | # Bipolar NPN mark 2615 | calma NPNID 82 20 2616 | # Bipolar PNP mark 2617 | calma PNPID 82 20 2618 | # Capacitor ID 2619 | calma CAPID 82 64 2620 | # Core area ID mark 2621 | calma COREID 81 2 2622 | # Standard cell ID mark 2623 | calma STDCELL 81 4 2624 | # Padframe cell ID mark 2625 | calma PADCELL 81 3 2626 | # Seal ring ID mark 2627 | calma SEALID 81 1 2628 | # Low tap density ID mark 2629 | calma LOWTAPDENSITY 81 14 2630 | 2631 | # LICON 2632 | calma CONT 66 44 2633 | calma LI 67 20 2634 | calma MCON 67 44 2635 | 2636 | calma MET1 68 20 2637 | calma VIA1 68 44 2638 | calma MET2 69 20 2639 | calma VIA2 69 44 2640 | calma MET3 70 20 2641 | calma VIA3 70 44 2642 | calma MET4 71 20 2643 | calma VIA4 71 44 2644 | calma MET5 72 20 2645 | calma GLASS 76 20 2646 | 2647 | calma SUBPIN 64 59 2648 | calma PADPIN 76 5 2649 | calma DIFFPIN 65 6 2650 | calma TAPPIN 65 5 2651 | calma WELLPIN 64 5 2652 | calma LIPIN 67 5 2653 | calma POLYPIN 66 5 2654 | calma MET1PIN 68 5 2655 | calma MET2PIN 69 5 2656 | calma MET3PIN 70 5 2657 | calma MET4PIN 71 5 2658 | calma MET5PIN 72 5 2659 | 2660 | calma LIRES 67 13 2661 | calma MET1RES 68 13 2662 | calma MET2RES 69 13 2663 | calma MET3RES 70 13 2664 | calma MET4RES 71 13 2665 | calma MET5RES 72 13 2666 | 2667 | calma POLYSHORT 66 15 2668 | calma LISHORT 67 15 2669 | calma MET1SHORT 68 15 2670 | calma MET2SHORT 69 15 2671 | calma MET3SHORT 70 15 2672 | calma MET4SHORT 71 15 2673 | calma MET5SHORT 72 15 2674 | 2675 | calma SUBTXT 122 16 2676 | calma PADTXT 76 16 2677 | calma DIFFTXT 65 16 2678 | calma POLYTXT 66 16 2679 | calma WELLTXT 64 16 2680 | calma LITXT 67 16 2681 | calma MET1TXT 68 16 2682 | calma MET2TXT 69 16 2683 | calma MET3TXT 70 16 2684 | calma MET4TXT 71 16 2685 | calma MET5TXT 72 16 2686 | 2687 | calma BOUND 235 4 2688 | 2689 | calma LVSTEXT 83 44 2690 | 2691 | calma CAPM 89 44 2692 | calma CAPM2 97 44 2693 | 2694 | calma FILLOBSM1 62 24 2695 | calma FILLOBSM2 105 52 2696 | calma FILLOBSM3 107 24 2697 | calma FILLOBSM4 112 4 2698 | 2699 | end 2700 | 2701 | #----------------------------------------------------- 2702 | # Digital flow maze router cost parameters 2703 | #----------------------------------------------------- 2704 | 2705 | mzrouter 2706 | end 2707 | 2708 | #----------------------------------------------------- 2709 | # Vendor DRC rules 2710 | #----------------------------------------------------- 2711 | 2712 | drc 2713 | 2714 | style drc variants (fast),(full),(routing) 2715 | 2716 | scalefactor 10 2717 | 2718 | cifstyle drc 2719 | 2720 | variants (fast),(full) 2721 | 2722 | #----------------------------- 2723 | # DNWELL 2724 | #----------------------------- 2725 | 2726 | width dnwell 3000 "Deep N-well width < %d (Dnwell 2)" 2727 | spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (Dnwell 3)" 2728 | spacing dnwell allnwell 4500 surround_ok \ 2729 | "Deep N-well spacing to N-well < %d (Nwell 7)" 2730 | cifmaxwidth nwell_missing 0 bend_illegal \ 2731 | "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (Nwell 5a, 7)" 2732 | cifmaxwidth dnwell_missing 0 bend_illegal \ 2733 | "SONOS nFET must be in Deep N-well (Tunm 6a)" 2734 | 2735 | #----------------------------- 2736 | # NWELL 2737 | #----------------------------- 2738 | 2739 | width allnwell 840 "N-well width < %d (Nwell 1)" 2740 | spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (Nwell 2a)" 2741 | 2742 | #----------------------------- 2743 | # DIFF 2744 | #----------------------------- 2745 | 2746 | width *ndiff,nfet,scnfet,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,*psd,*pdiode,pdiffres \ 2747 | 150 "Diffusion width < %d (Diff/tap 1)" 2748 | width *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,*mvpdiode 290 \ 2749 | "MV Diffusion width < %d (Diff/tap 14)" 2750 | width *mvnsd,*mvpsd 150 "MV Tap width < %d (Diff/tap 1)" 2751 | extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (Diff/tap 16)" 2752 | extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (Diff/tap 16)" 2753 | extend *psd *ndiff 290 "Butting tap length < %d (Diff/tap 4)" 2754 | extend *nsd *pdiff 290 "Butting tap length < %d (Diff/tap 4)" 2755 | width mvpdiffres 150 "MV P-Diffusion resistor width < %d (Diff/tap 14a)" 2756 | spacing alldifflv,var,varhvt alldifflv,var,varhvt 270 touching_ok \ 2757 | "Diffusion spacing < %d (Diff/tap 3)" 2758 | spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \ 2759 | "MV Diffusion spacing < %d (Diff/tap 15a)" 2760 | spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \ 2761 | "MV Diffusion to MV tap spacing < %d (Diff/tap 3)" 2762 | spacing *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \ 2763 | touching_ok "MV P-Diffusion to MV N-tap spacing < %d (Diff/tap 15b)" 2764 | spacing *mvnsd,*mvpdiff,mvpfet,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \ 2765 | "MV Diffusion in N-well to P-tap spacing < %d (Diff/tap 20 + Diff/tap 17,19)" 2766 | spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \ 2767 | "N-Diffusion spacing to N-well < %d (Diff/tap 9)" 2768 | spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \ 2769 | "N-Diffusion spacing to N-well < %d (Diff/tap 9)" 2770 | spacing *psd allnwell 130 touching_illegal \ 2771 | "P-tap spacing to N-well < %d (Diff/tap 11)" 2772 | spacing *mvpsd allnwell 130 touching_illegal \ 2773 | "P-tap spacing to N-well < %d (Diff/tap 11)" 2774 | surround *nsd allnwell 180 absence_illegal \ 2775 | "N-well overlap of N-tap < %d (Diff/tap 10)" 2776 | surround *mvnsd allnwell 330 absence_illegal \ 2777 | "N-well overlap of MV N-tap < %d (Diff/tap 19)" 2778 | surround *pdiff,*pdiode,pfet,scpfet allnwell 180 absence_illegal \ 2779 | "N-well overlap of P-Diffusion < %d (Diff/tap 8)" 2780 | surround *mvpdiff,*mvpdiode,mvpfet allnwell 330 absence_illegal \ 2781 | "N-well overlap of P-Diffusion < %d (Diff/tap 17)" 2782 | surround mvvar allnwell 560 absence_illegal \ 2783 | "N-well overlap of MV varactor < %d (LVTN 10 + LVTN 4b)" 2784 | spacing *mvndiode *mvndiode 1070 touching_ok \ 2785 | "MV N-diode spacing < %d (HVNTM.2 + 2 * HVNTM.3)" 2786 | 2787 | # Butting junction rules 2788 | edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \ 2789 | "N-Diffusion to P-tap spacing < %d across butted junction" 2790 | edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \ 2791 | "N-Diffusion to P-tap spacing < %d across butted junction" 2792 | edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \ 2793 | "P-Diffusion to N-tap spacing < %d across butted junction" 2794 | edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \ 2795 | "P-Diffusion to N-tap spacing < %d across butted junction" 2796 | 2797 | edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \ 2798 | "MV N-Diffusion to MV P-tap spacing < %d across butted junction" 2799 | edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \ 2800 | "MV N-Diffusion to MV P-tap spacing < %d across butted junction" 2801 | edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \ 2802 | "MV P-Diffusion to MV N-tap spacing < %d across butted junction" 2803 | edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \ 2804 | "MV P-Diffusion to MV N-tap spacing < %d across butted junction" 2805 | 2806 | variants (full) 2807 | 2808 | # Latchup rules 2809 | cifmaxwidth ptap_missing 0 bend_illegal \ 2810 | "N-diff distance to P-tap must be < 15.0um (LU 2)" 2811 | cifmaxwidth dptap_missing 0 bend_illegal \ 2812 | "N-diff distance to P-tap in deep Nwell must be < 15.0um (LU 2.1)" 2813 | cifmaxwidth ntap_missing 0 bend_illegal \ 2814 | "P-diff distance to N-tap must be < 15.0um (LU 3)" 2815 | 2816 | variants * 2817 | 2818 | #----------------------------- 2819 | # POLY 2820 | #----------------------------- 2821 | 2822 | width allpoly 150 "Poly width < %d (Poly 1a)" 2823 | spacing allpoly allpoly 210 touching_ok "Poly spacing < %d (Poly 2)" 2824 | spacing allpolynonfet alldifflvnonfet 75 corner_ok allfets \ 2825 | "Poly spacing to Diffusion < %d (Poly 4a)" 2826 | spacing npres *nsd 480 touching_illegal \ 2827 | "Poly resistor spacing to N-tap < %d (Poly 9)" 2828 | overhang *ndiff,rndiff nfet,scnfet 250 "N-Diffusion overhang of nmos < %d (Poly 7)" 2829 | overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \ 2830 | "N-Diffusion overhang of nmos < %d (Poly 7)" 2831 | overhang *pdiff,rpdiff pfet,scpfet 250 "P-Diffusion overhang of pmos < %d (Poly 7)" 2832 | overhang *mvpdiff,mvrpdiff mvpfet 250 "P-Diffusion overhang of pmos < %d (Poly 7)" 2833 | overhang *poly allfets 130 "Poly overhang of transistor < %d (Poly 8)" 2834 | rect_only allfets "No bends in transistors (Poly 11)" 2835 | rect_only xhrpoly,uhrpoly "No bends in poly resistors (Poly 11)" 2836 | extend xpc/a xhrpoly,uhrpoly 2160 \ 2837 | "Poly contact extends poly resistor by < %d (LIcon 1c + LI 5)" 2838 | spacing xhrpoly,uhrpoly xhrpoly,uhrpoly 1240 touching_illegal \ 2839 | "Distance between precision resistors < %d (RPM 2 + 2 * RPM 3)" 2840 | 2841 | #-------------------------------------------------------------------- 2842 | # NPC (Nitride Poly Cut) 2843 | #-------------------------------------------------------------------- 2844 | 2845 | # Layer NPC is defined automatically around poly contacts (grow 0.1um) 2846 | 2847 | #-------------------------------------------------------------------- 2848 | # CONT (LICON, contact between poly/diff and LI) 2849 | #-------------------------------------------------------------------- 2850 | 2851 | width ndc/li 170 "N-diffusion contact width < %d (LIcon 1)" 2852 | width nsc/li 170 "N-tap contact width < %d (LIcon 1)" 2853 | width pdc/li 170 "P-diffusion contact width < %d (LIcon 1)" 2854 | width psc/li 170 "P-tap contact width < %d (LIcon 1)" 2855 | width ndic/li 170 "N-diode contact width < %d (LIcon 1)" 2856 | width pdic/li 170 "P-diode contact width < %d (LIcon 1)" 2857 | width pc/li 170 "Poly contact width < %d (LIcon 1)" 2858 | 2859 | width xpc/li 350 "Poly resistor contact width < %d (LIcon 1b + 2 * LI 5)" 2860 | 2861 | width mvndc/li 170 "N-diffusion contact width < %d (LIcon 1)" 2862 | width mvnsc/li 170 "N-tap contact width < %d (LIcon 1)" 2863 | width mvpdc/li 170 "P-diffusion contact width < %d (LIcon 1)" 2864 | width mvpsc/li 170 "P-tap contact width < %d (LIcon 1)" 2865 | width mvndic/li 170 "N-diode contact width < %d (LIcon 1)" 2866 | width mvpdic/li 170 "P-diode contact width < %d (LIcon 1)" 2867 | 2868 | spacing allpdiffcont allndiffcont 170 touching_illegal \ 2869 | "Diffusion contact spacing < %d (LIcon 2)" 2870 | spacing allndiffcont allndiffcont 170 touching_ok \ 2871 | "Diffusion contact spacing < %d (LIcon 2)" 2872 | spacing allpdiffcont allpdiffcont 170 touching_ok \ 2873 | "Diffusion contact spacing < %d (LIcon 2)" 2874 | spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (LIcon 2)" 2875 | 2876 | spacing pc alldiff 190 touching_illegal \ 2877 | "Poly contact spacing to diffusion < %d (LIcon 14)" 2878 | spacing pc allpfets 235 touching_illegal \ 2879 | "Poly contact spacing to pFET < %d (LIcon 9 + PSDM 5a)" 2880 | 2881 | spacing ndc,pdc nfet,pfet 55 touching_illegal \ 2882 | "Diffusion contact to gate < %d (LIcon 11)" 2883 | spacing ndc,pdc scnfet,scpfet 50 touching_illegal \ 2884 | "Diffusion contact to standard cell gate < %d (LIcon 11)" 2885 | spacing mvndc,mvpdc mvnfet,mvnnfet,mvpfet 55 touching_illegal \ 2886 | "Diffusion contact to gate < %d (LIcon 11)" 2887 | spacing ndc,mvndc rnd,mvrnd 60 touching_illegal "Diffusion contact to rndiff < %d ()" 2888 | spacing pdc,mvpdc rdp,mvrdp 60 touching_illegal "Diffusion contact to rndiff < %d ()" 2889 | spacing nsc varactor,varhvt 250 touching_illegal \ 2890 | "Diffusion contact to varactor gate < %d (LIcon 10)" 2891 | spacing mvnsc mvvar 250 touching_illegal \ 2892 | "Diffusion contact to varactor gate < %d (LIcon 10)" 2893 | 2894 | surround ndc/a *ndiff,nfet,scnfet,nfetlvt 40 absence_illegal \ 2895 | "N-diffusion overlap of N-diffusion contact < %d (LIcon 5a)" 2896 | surround pdc/a *pdiff,pfet,scpfet,pfethvt,pfetlvt 40 absence_illegal \ 2897 | "P-diffusion overlap of P-diffusion contact < %d (LIcon 5a)" 2898 | surround ndic/a *ndi 40 absence_illegal \ 2899 | "N-diode overlap of N-diode contact < %d (LIcon 5a)" 2900 | surround pdic/a *pdi 40 absence_illegal \ 2901 | "P-diode overlap of N-diode contact < %d (LIcon 5a)" 2902 | 2903 | surround ndc/a *ndiff,nfet,scnfet,nfetlvt 60 directional \ 2904 | "N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c)" 2905 | surround pdc/a *pdiff,pfet,scpfet,pfethvt,pfetlvt 60 directional \ 2906 | "P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c)" 2907 | surround ndic/a *ndi 60 directional \ 2908 | "N-diode overlap of N-diode contact < %d in one direction (LIcon 5c)" 2909 | surround pdic/a *pdi 60 directional \ 2910 | "P-diode overlap of N-diode contact < %d in one direction (LIcon 5c)" 2911 | 2912 | surround nsc/a *nsd 120 directional \ 2913 | "N-tap overlap of N-tap contact < %d in one direction (LIcon 7)" 2914 | surround psc/a *psd 120 directional \ 2915 | "P-tap overlap of P-tap contact < %d in one direction (LIcon 7)" 2916 | 2917 | surround mvndc/a *mvndiff,mvnfet 40 absence_illegal \ 2918 | "N-diffusion overlap of N-diffusion contact < %d (LIcon 5a)" 2919 | surround mvpdc/a *mvpdiff,mvpfet 40 absence_illegal \ 2920 | "P-diffusion overlap of P-diffusion contact < %d (LIcon 5a)" 2921 | surround mvndic/a *mvndi 40 absence_illegal \ 2922 | "N-diode overlap of N-diode contact < %d (LIcon 5a)" 2923 | surround mvpdic/a *mvpdi 40 absence_illegal \ 2924 | "P-diode overlap of N-diode contact < %d (LIcon 5a)" 2925 | 2926 | surround mvndc/a *mvndiff,mvnfet 60 directional \ 2927 | "N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c)" 2928 | surround mvpdc/a *mvpdiff,mvpfet 60 directional \ 2929 | "P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c)" 2930 | surround mvndic/a *mvndi 60 directional \ 2931 | "N-diode overlap of N-diode contact < %d in one direction (LIcon 5c)" 2932 | surround mvpdic/a *mvpdi 60 directional \ 2933 | "P-diode overlap of N-diode contact < %d in one direction (LIcon 5c)" 2934 | 2935 | surround mvnsc/a *mvnsd 120 directional \ 2936 | "N-tap overlap of N-tap contact < %d in one direction (LIcon 7)" 2937 | surround mvpsc/a *mvpsd 120 directional \ 2938 | "P-tap overlap of P-tap contact < %d in one direction (LIcon 7)" 2939 | 2940 | surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \ 2941 | "Poly overlap of poly contact < %d (LIcon 8)" 2942 | surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \ 2943 | "Poly overlap of poly contact < %d in one direction (LIcon 8a)" 2944 | 2945 | exact_overlap ndc/a,pdc/a,psc/a,nsc/a,pc/a,ndic/a,pdic/a 2946 | exact_overlap mvndc/a,mvpdc/a,mvpsc/a,mvnsc/a,mvndic/a,mvpdic/a 2947 | 2948 | #------------------------------------------------------------- 2949 | # LI - Local interconnect layer 2950 | #------------------------------------------------------------- 2951 | 2952 | width *li,rli 170 "Local interconnect width < %d (LI 1)" 2953 | width coreli 140 "Core local interconnect width < %d (LI c1)" 2954 | spacing allli allli,*obsli 170 touching_ok "Local interconnect spacing < %d (LI 3)" 2955 | spacing coreli allli,*obsli 140 touching_ok "Core local interconnect spacing < %d (LI c2)" 2956 | 2957 | surround pc/li *li 80 directional \ 2958 | "Local interconnect overlap of poly contact < %d in one direction (LI 5)" 2959 | 2960 | surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \ 2961 | *li,rli 80 directional \ 2962 | "Local interconnect overlap of diffusion contact < %d in one direction (LI 5)" 2963 | 2964 | area allli,*obsli 56100 170 "Local interconnect minimum area < %a (LI 6)" 2965 | 2966 | #------------------------------------------------------------- 2967 | # MCON - Contact between local interconnect and metal1 2968 | #------------------------------------------------------------- 2969 | 2970 | width lic/m1 170 "Mcon width < %d (Mcon 1)" 2971 | spacing lic/m1 lic/m1,obslic/m1 170 touching_ok "Mcon spacing < %d (Mcon 2)" 2972 | 2973 | exact_overlap lic/m1 2974 | 2975 | #------------------------------------------------------------- 2976 | # METAL1 - 2977 | #------------------------------------------------------------- 2978 | 2979 | width *m1,rm1 140 "Metal1 width < %d (Met1 1)" 2980 | spacing allm1 allm1,*obsm1 140 touching_ok "Metal1 spacing < %d (Met1 2)" 2981 | area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (Met1 6)" 2982 | 2983 | surround lic/m1 *met1 30 absence_illegal \ 2984 | "Metal1 overlap of local interconnect contact < %d (Met1 4)" 2985 | surround lic/m1 *met1 60 directional \ 2986 | "Metal1 overlap of local interconnect contact < %d in one direction (Met1 5)" 2987 | 2988 | variants (fast),(full) 2989 | widespacing allm1 3000 allm1,*obsm1 280 touching_ok \ 2990 | "Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)" 2991 | widespacing *obsm1 3000 allm1 280 touching_ok \ 2992 | "Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)" 2993 | 2994 | variants (full) 2995 | cifmaxwidth m1_hole_empty 0 bend_illegal \ 2996 | "Min area of metal1 holes > 0.14um^2 (Met1 7)" 2997 | variants * 2998 | 2999 | #-------------------------------------------------- 3000 | # VIA1 3001 | #-------------------------------------------------- 3002 | 3003 | width v1/m1 260 "Via1 width < %d (Via 1a + 2 * Via 4a)" 3004 | spacing v1 v1 60 touching_ok "Via1 spacing < %d (Via 2 - 2 * Via 4a)" 3005 | surround v1/m1 *m1 30 directional \ 3006 | "Metal1 overlap of Via1 < %d in one direction (Via 5a - Via 4a)" 3007 | surround v1/m2 *m2 30 directional \ 3008 | "Metal2 overlap of Via1 < %d in one direction (Met2 5 - Met2 4)" 3009 | 3010 | exact_overlap v1/m2 3011 | 3012 | #-------------------------------------------------- 3013 | # METAL2 - 3014 | #-------------------------------------------------- 3015 | 3016 | width allm2 140 "Metal2 width < %d (Met2 1)" 3017 | spacing allm2 allm2,obsm2 140 touching_ok "Metal2 spacing < %d (Met2 2)" 3018 | area allm2,obsm2 67600 140 "Metal2 minimum area < %a (Met2 6)" 3019 | 3020 | variants (fast),(full) 3021 | widespacing allm2 3000 allm2,obsm2 280 touching_ok \ 3022 | "Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)" 3023 | widespacing obsm2 3000 allm2 280 touching_ok \ 3024 | "Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)" 3025 | 3026 | variants (full) 3027 | cifmaxwidth m2_hole_empty 0 bend_illegal \ 3028 | "Min area of metal2 holes > 0.14um^2 (Met2 7)" 3029 | variants * 3030 | 3031 | #-------------------------------------------------- 3032 | # VIA2 3033 | #-------------------------------------------------- 3034 | 3035 | width v2/m2 280 "Via2 width < %d (Via2 1a + 2 * Via2 4)" 3036 | 3037 | spacing v2 v2 120 touching_ok "Via2 spacing < 0.24um (Via2 2 - 2 * Via2 4)" 3038 | 3039 | surround v2/m2 *m2 45 directional \ 3040 | "Metal2 overlap of Via2 < %d in one direction (Via2 4a - Via2 4)" 3041 | surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of Via2 < %d (Met3 4)" 3042 | 3043 | exact_overlap v2/m2 3044 | 3045 | #-------------------------------------------------- 3046 | # METAL3 - 3047 | #-------------------------------------------------- 3048 | 3049 | width allm3 300 "Metal3 width < %d (Met3 1)" 3050 | spacing allm3 allm3,obsm3 300 touching_ok "Metal3 spacing < %d (Met3 2)" 3051 | area allm3,obsm3 240000 300 "Metal3 minimum area < %a (Met3 6)" 3052 | 3053 | variants (fast),(full) 3054 | widespacing allm3 3000 allm3,obsm3 400 touching_ok \ 3055 | "Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)" 3056 | widespacing obsm3 3000 allm3 400 touching_ok \ 3057 | "Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)" 3058 | variants * 3059 | 3060 | 3061 | #-------------------------------------------------- 3062 | # VIA3 - Requires 1 Module 3063 | #-------------------------------------------------- 3064 | 3065 | width v3/m3 320 "Via3 width < %d (Via3 1 + 2 * Via3 4)" 3066 | spacing v3 v3 80 touching_ok "Via3 spacing < %d (Via3 2 - 2 * Via3 4)" 3067 | surround v3/m3 *m3 30 directional \ 3068 | "Metal3 overlap of Via3 in one direction < %d (Via3 5 - Via3 4)" 3069 | surround v3/m4 *m4 5 absence_illegal \ 3070 | "Metal4 overlap of Via3 < %d (Met4 3 - Via3 4)" 3071 | 3072 | exact_overlap v3/m3 3073 | 3074 | #----------------------------- 3075 | # METAL4 - METAL4 Module 3076 | #----------------------------- 3077 | 3078 | variants * 3079 | 3080 | width allm4 300 "Metal4 width < %d (Met4 1)" 3081 | spacing allm4 allm4,obsm4 300 touching_ok "Metal4 spacing < %d (Met4 2)" 3082 | area allm4,obsm4 240000 300 "Metal4 minimum area < %a (Met4 4a)" 3083 | 3084 | variants (fast),(full) 3085 | widespacing allm4 3000 allm4,obsm4 400 touching_ok \ 3086 | "Metal4 > 3um spacing to unrelated m4 < %d (S2M4)" 3087 | widespacing obsm4 3000 allm4 400 touching_ok \ 3088 | "Metal4 > 3um spacing to unrelated m4 < %d (S2M4)" 3089 | variants * 3090 | 3091 | #-------------------------------------------------- 3092 | # VIA4 - Requires 1 Module 3093 | #-------------------------------------------------- 3094 | 3095 | width v4/m4 1180 "Via4 width < %d (Via4 1 + 2 * Via4 4)" 3096 | spacing v4 v4 420 touching_ok "Via4 spacing < %d (Via4 2 - 2 * Via4 4)" 3097 | surround v4/m5 *m5 120 absence_illegal \ 3098 | "Metal5 overlap of Via4 < %d (Met5 3 - Via4 4)" 3099 | 3100 | exact_overlap v4/m4 3101 | 3102 | #----------------------------- 3103 | # 1 - 1 Module 3104 | #----------------------------- 3105 | 3106 | width allm5 1600 "Metal5 width < %d (Met5 1)" 3107 | spacing allm5 allm5,obsm5 1600 touching_ok "Metal5 spacing < %d (Met5 2)" 3108 | area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (Met5 4)" 3109 | 3110 | 3111 | 3112 | #-------------------------------------------------- 3113 | # NMOS, PMOS 3114 | #-------------------------------------------------- 3115 | 3116 | extend allfets *poly 420 "Transistor width < %d (Diff/tap 2)" 3117 | # Except: Note that standard cells allow transistor width minimum 0.36um 3118 | width pfetlvt 350 "LVT PMOS gate length < %d (Poly 1b)" 3119 | 3120 | spacing *nsd,*mvnsd allpolynonfet 55 touching_illegal \ 3121 | "N-tap spacing to field poly < %d (Poly 5)" 3122 | spacing *psd,*mvpsd allpolynonfet 55 touching_illegal \ 3123 | "P-tap spacing to field poly < %d (Poly 5)" 3124 | 3125 | # Full edge rule required to describe FET to butted tap distance 3126 | edge4way *psd *ndiff 300 *ndiff *psd 300 \ 3127 | "Butting P-tap spacing to NMOS gate < %d (Poly 6)" 3128 | edge4way *nsd *pdiff 300 *pdiff *nsd 300 \ 3129 | "Butting N-tap spacing to PMOS gate < %d (Poly 6)" 3130 | edge4way *mvpsd *mvndiff 300 *mvndiff *mvpsd 300 \ 3131 | "Butting MV P-tap spacing to MV NMOS gate < %d (Poly 6)" 3132 | edge4way *mvnsd *mvpdiff 300 *mvpdiff *mvnsd 300 \ 3133 | "Butting MV N-tap spacing to MV PMOS gate < %d (Poly 6)" 3134 | 3135 | # No LV FETs in HV diff 3136 | spacing pfet,scpfet,pfetlvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \ 3137 | "LV P-diffusion to MV P-diffusion < %d (Diff/tap 23 + Diff/tap 22)" 3138 | 3139 | spacing nfet,scnfet,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \ 3140 | "LV N-diffusion to MV N-diffusion < %d (Diff/tap 23 + Diff/tap 22)" 3141 | 3142 | # No HV FETs in LV diff 3143 | spacing mvpfet,*mvpdiff *pdiff 360 touching_illegal \ 3144 | "MV P-diffusion to LV P-diffusion < %d (Diff/tap 23 + Diff/tap 22)" 3145 | 3146 | spacing mvnfet,mvvaractor,*mvndiff *ndiff 360 touching_illegal \ 3147 | "MV N-diffusion to LV N-diffusion < %d (Diff/tap 23 + Diff/tap 22)" 3148 | 3149 | # Minimum length of MV FETs. Note that this is larger than the minimum 3150 | # width (0.29um), so an edge rule is required 3151 | 3152 | edge4way mvndiff mvnfet 500 mvnfet 0 0 \ 3153 | "MV NMOS minimum length < %d (Poly 13)" 3154 | 3155 | edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \ 3156 | "MV Varactor minimum length < %d (Poly 13)" 3157 | 3158 | edge4way mvpdiff mvpfet 500 mvpfet 0 0 \ 3159 | "MV PMOS minimum length < %d (Poly 13)" 3160 | 3161 | #-------------------------------------------------- 3162 | # mrp1 (N+ poly resistor) 3163 | #-------------------------------------------------- 3164 | 3165 | width mrp1 330 "mrp1 resistor width < %d (Poly 3)" 3166 | 3167 | #-------------------------------------------------- 3168 | # xhrpoly (P+ poly resistor) 3169 | #-------------------------------------------------- 3170 | 3171 | width xhrpoly 350 "xhrpoly resistor width < %d (P+ Poly 1a)" 3172 | # NOTE: xhrpoly resistor requires choice of discrete widths 0.35, 0.69, ... up to 1.27. 3173 | 3174 | #-------------------------------------------------- 3175 | # uhrpoly (P+ poly resistor, 2kOhm/sq) 3176 | #-------------------------------------------------- 3177 | 3178 | width uhrpoly 350 "uhrpoly resistor width < %d" 3179 | spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \ 3180 | "xhrpoly/uhrpoly resistor spacing to diffusion < %d (Poly 9)" 3181 | 3182 | #------------------------------------ 3183 | # MOS Varactor device rules 3184 | #------------------------------------ 3185 | 3186 | overhang *nsd var,varhvt 250 \ 3187 | "N-Tap overhang of Varactor < %d (Var 4)" 3188 | 3189 | overhang *mvnsd mvvar 250 \ 3190 | "N-Tap overhang of Varactor < %d (Var 4)" 3191 | 3192 | width var,varhvt,mvvar 180 "Varactor length < %d (Var 1)" 3193 | extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (Var 2)" 3194 | 3195 | #----------------------------------------------------------- 3196 | # MiM CAP (CAPM) - 3197 | #----------------------------------------------------------- 3198 | 3199 | width *mimcap 2000 "MiM cap width < %d (Capm 1)" 3200 | spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (Capm 2a)" 3201 | spacing *mimcap via2/m3 1270 touching_illegal \ 3202 | "MiM cap spacing to via2 < %d (Capm 5)" 3203 | surround *mimcc *mimcap 200 absence_illegal \ 3204 | "MiM cap must surround MiM cap contact by %d (Capm 4)" 3205 | rect_only *mimcap "MiM cap must be rectangular (Capm 7) 3206 | 3207 | surround *mimcap *metal3/m3 140 absence_illegal \ 3208 | "Metal3 must surround MiM cap by %d (Capm 3)" 3209 | spacing via2 *mimcap 50 touching_illegal "MiM cap cannot overlap via2 (Capm 8)" 3210 | spacing via3 *mimcap 50 touching_illegal "MiM cap cannot overlap via3 (Capm 8)" 3211 | # (resolve scaling issue!) 3212 | # cifspacing mim_bottom mim_bottom 1200 touching_ok \ 3213 | # "MiM cap bottom plate spacing < %d (Capm 2b)" 3214 | 3215 | # MiM cap contact rules (VIA3) 3216 | 3217 | width mimcc/m3 320 "MiM cap contact width < %d (Via3 1 + 2 * Via3 4)" 3218 | spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (Via3 2 - 2 * Via3 4)" 3219 | surround mimcc/m4 *m4 5 directional \ 3220 | "Metal4 overlap of MiM cap contact in one direction < %d (Met4 3 - Via3 4)" 3221 | exact_overlap mimcc/m3 3222 | 3223 | width *mimcap2 2000 "MiM cap width < %d (Cap2m 1)" 3224 | spacing *mimcap2 *mimcap2 840 touching_ok "MiM cap spacing < %d (Cap2m 2a)" 3225 | spacing *mimcap2 via3/m4 1270 touching_illegal \ 3226 | "MiM cap spacing to via3 < %d (Cap2m 5)" 3227 | surround *mim2cc *mimcap2 200 absence_illegal \ 3228 | "MiM cap must surround MiM cap contact by %d (Cap2m 4)" 3229 | rect_only *mimcap2 "MiM cap must be rectangular (Cap2m 7) 3230 | 3231 | surround *mimcap2 *metal4/m4 140 absence_illegal \ 3232 | "Metal4 must surround MiM cap by %d (Cap2m 3)" 3233 | spacing via3 *mimcap2 50 touching_illegal "MiM cap cannot overlap via3 (Cap2m 8)" 3234 | spacing via4 *mimcap2 50 touching_illegal "MiM cap cannot overlap via4 (Cap2m 8)" 3235 | # (resolve scaling issue!) 3236 | # cifspacing mim2_bottom mim2_bottom 1200 touching_ok \ 3237 | # "MiM2 cap bottom plate spacing < %d (Cap2m 2b)" 3238 | 3239 | # MiM cap contact rules (VIA4) 3240 | 3241 | width mim2cc/m4 1180 "MiM2 cap contact width < %d (Via4 1 + 2 * Via4 4)" 3242 | spacing mim2cc mim2cc 420 touching_ok \ 3243 | "MiM2 cap contact spacing < %d (Via4 2 - 2 * Via4 4)" 3244 | surround mim2cc/m5 *m5 120 absence_illegal \ 3245 | "Metal5 overlap of MiM2 cap contact < %d (Met5 3 - Via4 4)" 3246 | exact_overlap mim2cc/m4 3247 | 3248 | 3249 | #---------------------------- 3250 | # End DRC style 3251 | #---------------------------- 3252 | 3253 | end 3254 | 3255 | #---------------------------- 3256 | # LEF format definitions 3257 | #---------------------------- 3258 | 3259 | lef 3260 | 3261 | masterslice pwell pwell PWELL substrate 3262 | masterslice nwell nwell NWELL 3263 | 3264 | routing li li1 LI1 LI li 3265 | 3266 | routing m1 met1 MET1 m1 3267 | routing m2 met2 MET2 m2 3268 | routing m3 met3 MET3 m3 3269 | routing m4 met4 MET4 m4 3270 | routing m5 met5 MET5 m5 3271 | 3272 | cut lic mcon MCON Mcon 3273 | cut m2c via via1 VIA VIA1 cont2 via12 3274 | cut m3c via2 VIA2 cont3 via23 3275 | cut via3 via3 VIA3 cont4 via34 3276 | cut via4 via4 VIA4 cont5 via45 3277 | 3278 | obs obsli li1 3279 | obs obsm1 met1 3280 | obs obsm2 met2 3281 | obs obsm3 met3 3282 | 3283 | obs obsm4 met4 3284 | obs obsm5 met5 3285 | 3286 | obs obslic mcon 3287 | 3288 | end 3289 | 3290 | #----------------------------------------------------- 3291 | # Device and Parasitic extraction 3292 | #----------------------------------------------------- 3293 | 3294 | 3295 | extract 3296 | style ngspice variants (lvs),(sim),(si) 3297 | cscale 1 3298 | # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all 3299 | # dimensions must be in units of microns in the extract file. 3300 | # Use extract style "ngspice(si)" to override this and produce 3301 | # a file with SI units for length/area. 3302 | 3303 | variants (lvs),(sim) 3304 | lambda 1E6 3305 | variants (si) 3306 | lambda 1.0 3307 | variants * 3308 | 3309 | units microns 3310 | step 7 3311 | sidehalo 2 3312 | 3313 | # NOTE: MiM cap layers have been purposely put out of order, 3314 | # may want to reconsider. 3315 | 3316 | planeorder dwell 0 3317 | planeorder well 1 3318 | planeorder active 2 3319 | planeorder locali 3 3320 | planeorder metal1 4 3321 | planeorder metal2 5 3322 | planeorder metal3 6 3323 | planeorder metal4 7 3324 | planeorder metal5 8 3325 | planeorder block 9 3326 | planeorder comment 10 3327 | planeorder cap1 11 3328 | planeorder cap2 12 3329 | 3330 | height dnwell -0.1 0.1 3331 | height nwell,pwell 0.0 0.2062 3332 | height alldiff 0.2062 0.12 3333 | height allpoly 0.3262 0.18 3334 | height alldiffcont 0.3262 0.61 3335 | height pc 0.5062 0.43 3336 | height allli 0.9361 0.10 3337 | height lic 1.0361 0.34 3338 | height allm1 1.3761 0.36 3339 | height v1 1.7361 0.27 3340 | height allm2 2.0061 0.36 3341 | height v2 2.3661 0.42 3342 | height allm3 2.7861 0.845 3343 | height v3 3.6311 0.39 3344 | height allm4 4.0211 0.845 3345 | height v4 4.8661 0.505 3346 | height allm5 5.3711 1.26 3347 | height mimcap 2.4661 0.2 3348 | height mimcap2 3.7311 0.2 3349 | height mimcc 2.6661 0.12 3350 | height mim2cc 3.9311 0.09 3351 | 3352 | # Antenna check parameters 3353 | # Note that checks w/diode diffusion are not modeled 3354 | model partial 3355 | antenna poly sidewall 50 none 3356 | antenna allcont surface 3 none 3357 | antenna li sidewall 75 0 450 3358 | antenna lic surface 3 0 18 3359 | antenna m1,m2,m3 sidewall 400 2600 400 3360 | antenna v1 surface 3 0 18 3361 | antenna v2 surface 6 0 36 3362 | antenna m4,m5 sidewall 400 2600 400 3363 | antenna v3,v4 surface 6 0 36 3364 | 3365 | tiedown alldiffnonfet 3366 | 3367 | substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell 3368 | 3369 | # Layer resistance: Use document xp018-PDS-v4_2_1.pdf 3370 | 3371 | # Resistances are in milliohms per square 3372 | # Optional 3rd argument is the corner adjustment fraction 3373 | # Device values come from trtc.cor (typical corner) 3374 | resist (dnwell)/dwell 2200000 3375 | resist (pwell)/well 3050000 3376 | resist (nwell)/well 1700000 3377 | resist (rpw)/well 3050000 0.5 3378 | resist (*ndiff,nsd)/active 120000 3379 | resist (*pdiff,*psd)/active 197000 3380 | resist (*mvndiff,mvnsd)/active 114000 3381 | resist (*mvpdiff,*mvpsd)/active 191000 3382 | 3383 | resist ndiffres/active 120000 0.5 3384 | resist pdiffres/active 197000 0.5 3385 | resist mvndiffres/active 114000 0.5 3386 | resist mvpdiffres/active 191000 0.5 3387 | resist mrp1/active 48200 0.5 3388 | resist xhrpoly/active 319800 0.5 3389 | resist uhrpoly/active 2000000 0.5 3390 | 3391 | resist (allpolynonres)/active 48200 3392 | resist rmp/active 48200 3393 | 3394 | resist (allli)/locali 12200 3395 | resist (allm1)/metal1 125 3396 | resist (allm2)/metal2 125 3397 | resist (allm3)/metal3 47 3398 | resist (allm4)/metal4 47 3399 | resist (allm5)/metal5 29 3400 | 3401 | contact ndc,nsc 15000 3402 | contact pdc,psc 15000 3403 | contact mvndc,mvnsc 15000 3404 | contact mvpdc,mvpsc 15000 3405 | contact pc 15000 3406 | contact lic 152000 3407 | contact m2c 4500 3408 | contact m3c 3410 3409 | contact mimcc 4500 3410 | contact mim2cc 3410 3411 | contact via3 3410 3412 | contact via4 380 3413 | 3414 | #------------------------------------------------------------------------- 3415 | # Parasitic capacitance values: Use document (...) 3416 | #------------------------------------------------------------------------- 3417 | # This uses the new "default" definitions that determine the intervening 3418 | # planes from the planeorder stack, take care of the reflexive sideoverlap 3419 | # definitions, and generally clean up the section and make it more readable. 3420 | # 3421 | # Also uses "units microns" statement. All values are taken from the 3422 | # document PEX/xRC/cap_models. Fringe capacitance values are approximated. 3423 | # Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps. 3424 | #------------------------------------------------------------------------- 3425 | # Remember that device capacitances to substrate are taken care of by the 3426 | # models. Thus, active and poly definitions ignore all "fet" types. 3427 | # fet types are excluded when computing parasitic capacitance to 3428 | # active from layers above them because poly is a shield; fet types are 3429 | # included for parasitics from layers above to poly. Resistor types 3430 | # should be removed from all parasitic capacitance calculations, or else 3431 | # they just create floating caps. Technically, the capacitance probably 3432 | # should be split between the two terminals. Unsure of the correct model. 3433 | #------------------------------------------------------------------------- 3434 | 3435 | #n-well 3436 | # NOTE: This value not found in PEX files 3437 | defaultareacap nwell well 120 3438 | 3439 | #n-active 3440 | # Rely on device models to capture *ndiff area cap 3441 | # Do not extract parasitics from resistors 3442 | # defaultareacap allnactivenonfet active 790 3443 | # defaultperimeter allnactivenonfet active 280 3444 | 3445 | #p-active 3446 | # Rely on device models to capture *pdiff area cap 3447 | # Do not extract parasitics from resistors 3448 | # defaultareacap allpactivenonfet active 810 3449 | # defaultperimeter allpactivenonfet active 300 3450 | 3451 | #poly 3452 | # Do not extract parasitics from resistors 3453 | # defaultsidewall allpolynonfet active 22 3454 | # defaultareacap allpolynonfet active 106 3455 | # defaultperimeter allpolynonfet active 57 3456 | 3457 | defaultsidewall *poly active 23 3458 | defaultareacap *poly active nwell,obswell,pwell well 106 3459 | defaultperimeter *poly active nwell,obswell,pwell well 55 3460 | 3461 | #locali 3462 | defaultsidewall allli locali 33 3463 | defaultareacap allli locali nwell,obswell,pwell well 37 3464 | defaultperimeter allli locali nwell,obswell,pwell well 55 3465 | defaultoverlap allli locali nwell well 37 3466 | 3467 | #locali->diff 3468 | defaultoverlap allli locali allactivenonfet active 37 3469 | defaultsideoverlap allli locali allactivenonfet active 55 3470 | 3471 | #locali->poly 3472 | defaultoverlap allli locali allpolynonres active 94 3473 | defaultsideoverlap allli locali allpolynonres active 52 3474 | defaultsideoverlap *poly active allli locali 25 3475 | 3476 | #metal1 3477 | defaultsidewall allm1 metal1 45 3478 | defaultareacap allm1 metal1 nwell,obswell,pwell well 26 3479 | defaultperimeter allm1 metal1 nwell,obswell,pwell well 41 3480 | defaultoverlap allm1 metal1 nwell well 26 3481 | 3482 | #metal1->diff 3483 | defaultoverlap allm1 metal1 allactivenonfet active 26 3484 | defaultsideoverlap allm1 metal1 allactivenonfet active 41 3485 | 3486 | #metal1->poly 3487 | defaultoverlap allm1 metal1 allpolynonres active 45 3488 | defaultsideoverlap allm1 metal1 allpolynonres active 47 3489 | defaultsideoverlap *poly active allm1 metal1 17 3490 | 3491 | #metal1->locali 3492 | defaultoverlap allm1 metal1 allli locali 114 3493 | defaultsideoverlap allm1 metal1 allli locali 59 3494 | defaultsideoverlap allli locali allm1 metal1 35 3495 | 3496 | #metal2 3497 | defaultsidewall allm2 metal2 50 3498 | defaultareacap allm2 metal2 nwell,obswell,pwell well 17 3499 | defaultperimeter allm2 metal2 nwell,obswell,pwell well 41 3500 | defaultoverlap allm2 metal2 nwell well 38 3501 | 3502 | #metal2->diff 3503 | defaultoverlap allm2 metal2 allactivenonfet active 17 3504 | defaultsideoverlap allm2 metal2 allactivenonfet active 41 3505 | 3506 | #metal2->poly 3507 | defaultoverlap allm2 metal2 allpolynonres active 24 3508 | defaultsideoverlap allm2 metal2 allpolynonres active 41 3509 | defaultsideoverlap *poly active allm2 metal2 11 3510 | 3511 | #metal2->locali 3512 | defaultoverlap allm2 metal2 allli locali 38 3513 | defaultsideoverlap allm2 metal2 allli locali 46 3514 | defaultsideoverlap allli locali allm2 metal2 22 3515 | 3516 | #metal2->metal1 3517 | defaultoverlap allm2 metal2 allm1 metal1 134 3518 | defaultsideoverlap allm2 metal2 allm1 metal1 67 3519 | defaultsideoverlap allm1 metal1 allm2 metal2 48 3520 | 3521 | #metal3 3522 | defaultsidewall allm3 metal3 63 3523 | defaultoverlap allm3 metal3 nwell well 12 3524 | defaultareacap allm3 metal3 nwell,obswell,pwell well 12 3525 | defaultperimeter allm3 metal3 nwell,obswell,pwell well 41 3526 | 3527 | #metal3->diff 3528 | defaultoverlap allm3 metal3 allactive active 12 3529 | defaultsideoverlap allm3 metal3 allactive active 41 3530 | 3531 | #metal3->poly 3532 | defaultoverlap allm3 metal3 allpolynonres active 16 3533 | defaultsideoverlap allm3 metal3 allpolynonres active 44 3534 | defaultsideoverlap *poly active allm3 metal3 9 3535 | 3536 | #metal3->locali 3537 | defaultoverlap allm3 metal3 allli locali 21 3538 | defaultsideoverlap allm3 metal3 allli locali 47 3539 | defaultsideoverlap allli locali allm3 metal3 15 3540 | 3541 | #metal3->metal1 3542 | defaultoverlap allm3 metal3 allm1 metal1 35 3543 | defaultsideoverlap allm3 metal3 allm1 metal1 55 3544 | defaultsideoverlap allm1 metal1 allm3 metal3 27 3545 | 3546 | #metal3->metal2 3547 | defaultoverlap allm3 metal3 allm2 metal2 86 3548 | defaultsideoverlap allm3 metal3 allm2 metal2 70 3549 | defaultsideoverlap allm2 metal2 allm3 metal3 44 3550 | 3551 | #metal4 3552 | defaultsidewall allm4 metal4 67 3553 | # defaultareacap alltopm metal4 well 6 3554 | areacap allm4/m4 8 3555 | defaultoverlap allm4 metal4 nwell well 8 3556 | defaultperimeter allm4 metal4 well 37 3557 | 3558 | #metal4->diff 3559 | defaultoverlap allm4 metal4 allactivenonfet active 8 3560 | defaultsideoverlap allm4 metal4 allactivenonfet active 37 3561 | 3562 | #metal4->poly 3563 | defaultoverlap allm4 metal4 allpolynonres active 10 3564 | defaultsideoverlap allm4 metal4 allpolynonres active 38 3565 | defaultsideoverlap *poly active allm4 metal4 6 3566 | 3567 | #metal4->locali 3568 | defaultoverlap allm4 metal4 allli locali 12 3569 | defaultsideoverlap allm4 metal4 allli locali 40 3570 | defaultsideoverlap allli locali allm4 metal4 10 3571 | 3572 | #metal4->metal1 3573 | defaultoverlap allm4 metal4 allm1 metal1 15 3574 | defaultsideoverlap allm4 metal4 allm1 metal1 43 3575 | defaultsideoverlap allm1 metal1 allm4 metal4 16 3576 | 3577 | #metal4->metal2 3578 | defaultoverlap allm4 metal4 allm2 metal2 20 3579 | defaultsideoverlap allm4 metal4 allm2 metal2 46 3580 | defaultsideoverlap allm2 metal2 allm4 metal4 22 3581 | 3582 | #metal4->metal3 3583 | defaultoverlap allm4 metal4 allm3 metal3 84 3584 | defaultsideoverlap allm4 metal4 allm3 metal3 71 3585 | defaultsideoverlap allm3 metal3 allm4 metal4 43 3586 | 3587 | #metal5 3588 | defaultsidewall allm5 metal5 127 3589 | # defaultareacap allm5 metal5 well 6 3590 | areacap allm5/m5 6 3591 | defaultoverlap allm5 metal5 nwell well 6 3592 | defaultperimeter allm5 metal5 well 39 3593 | 3594 | #metal5->diff 3595 | defaultoverlap allm5 metal5 allactivenonfet active 6 3596 | defaultsideoverlap allm5 metal5 allactivenonfet active 39 3597 | 3598 | #metal5->poly 3599 | defaultoverlap allm5 metal5 allpolynonres active 7 3600 | defaultsideoverlap allm5 metal5 allpolynonres active 40 3601 | defaultsideoverlap *poly active allm5 metal5 6 3602 | 3603 | #metal5->locali 3604 | defaultoverlap allm5 metal5 allli locali 8 3605 | defaultsideoverlap allm5 metal5 allli locali 41 3606 | defaultsideoverlap allli locali allm5 metal5 8 3607 | 3608 | #metal5->metal1 3609 | defaultoverlap allm5 metal5 allm1 metal1 9 3610 | defaultsideoverlap allm5 metal5 allm1 metal1 43 3611 | defaultsideoverlap allm1 metal1 allm5 metal5 12 3612 | 3613 | #metal5->metal2 3614 | defaultoverlap allm5 metal5 allm2 metal2 11 3615 | defaultsideoverlap allm5 metal5 allm2 metal2 46 3616 | defaultsideoverlap allm2 metal2 allm5 metal5 16 3617 | 3618 | #metal5->metal3 3619 | defaultoverlap allm5 metal5 allm3 metal3 20 3620 | defaultsideoverlap allm5 metal5 allm3 metal3 54 3621 | defaultsideoverlap allm3 metal3 allm5 metal5 28 3622 | 3623 | #metal5->metal4 3624 | defaultoverlap allm5 metal5 allm4 metal4 68 3625 | defaultsideoverlap allm5 metal5 allm4 metal4 83 3626 | defaultsideoverlap allm4 metal4 allm5 metal5 47 3627 | 3628 | # Devices: Use document (...) 3629 | 3630 | variants (sim) 3631 | 3632 | device msubcircuit pshort pfet,scpfet *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w 3633 | device msubcircuit plowvt pfetlvt *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w 3634 | device msubcircuit phighvt pfethvt *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w 3635 | 3636 | device msubcircuit nshort nfet,scnfet *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w 3637 | device msubcircuit nlowvt nfetlvt *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w 3638 | device msubcircuit sonos_e nsonos *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w 3639 | device subcircuit xcnwvc varactor *nndiff nwell error l=l w=w 3640 | device subcircuit xcnwvc2 varhvt *nndiff nwell error l=l w=w 3641 | device subcircuit xchvnwc mvvaractor *mvnndiff nwell error l=l w=w 3642 | 3643 | device msubcircuit phv mvpfet *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w 3644 | device msubcircuit nhv mvnfet *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w 3645 | device msubcircuit nhvnative mvnnfet *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w 3646 | 3647 | device rsubcircuit short rmp *poly space/w,pwell,nwell error l=l w=w 3648 | device rsubcircuit short rli1 *li,coreli space/w,pwell,nwell error l=l w=w 3649 | device rsubcircuit short rmetal1 *metal1 space/w,pwell,nwell error l=l w=w 3650 | device rsubcircuit short rmetal2 *metal2 space/w,pwell,nwell error l=l w=w 3651 | device rsubcircuit short rmetal3 *metal3 space/w,pwell,nwell error l=l w=w 3652 | device rsubcircuit short rm4 *m4 space/w,pwell,nwell error l=l w=w 3653 | device rsubcircuit short rm5 *m5 space/w,pwell,nwell error l=l w=w 3654 | 3655 | device rsubcircuit xhrpoly xhrpoly xpc pwell,space/w error l=l w=w 3656 | device rsubcircuit uhrpoly uhrpoly xpc pwell,space/w error l=l w=w 3657 | device rsubcircuit mrp1 mrp1 *poly pwell,space/w error l=l w=w 3658 | 3659 | device rsubcircuit mrdn ndiffres *ndiff pwell,space/w error l=l w=w 3660 | device rsubcircuit mrdp pdiffres *pdiff nwell error l=l w=w 3661 | device rsubcircuit xpwres rpw pwell dnwell error l=l w=w 3662 | 3663 | device rsubcircuit mrdn_hv mvndiffres *mvndiff pwell,space/w error l=l w=w 3664 | device rsubcircuit mrdp_hv mvpdiffres *mvpdiff nwell error l=l w=w 3665 | 3666 | device subcircuit pdiode *pdiode nwell a=a p=p 3667 | device msubcircuit ndiode *ndiode pwell,space/w a=a p=p 3668 | device subcircuit pdiode_h *mvpdiode nwell a=a p=p 3669 | device msubcircuit ndiode_h *mvndiode pwell,space/w a=a p=p 3670 | 3671 | # These are parasitic devices 3672 | device msubcircuit ndiode_lvt *ndiodelvt pwell,space/w a=a p=p 3673 | device subcircuit pdiode_lvt *pdiodelvt nwell a=a p=p 3674 | device subcircuit pdiode_hvt *pdiodehvt nwell a=a p=p 3675 | device msubcircuit ndiode_native *nndiode pwell,space/w a=a p=p 3676 | 3677 | device subcircuit xcmimc1 *mimcap m3 nwell,pwell,space/w error a=a p=p s=subs 3678 | device subcircuit xcmimc2 *mimcap2 m4,mimcc/m4 nwell,pwell,space/w error a=a p=p s=subs 3679 | 3680 | variants (lvs),(si) 3681 | 3682 | device mosfet pshort scpfet,pfet pdiff,pdiffres,pdc nwell 3683 | device mosfet plowvt pfetlvt pdiff,pdiffres,pdc nwell 3684 | device mosfet phighvt pfethvt pdiff,pdiffres,pdc nwell 3685 | device mosfet nshort scnfet,nfet ndiff,ndiffres,ndc pwell,space/w 3686 | device mosfet nlowvt nfetlvt ndiff,ndiffres,ndc pwell,space/w 3687 | device mosfet sonos_e nsonos ndiff,ndiffres,ndc pwell,space/w 3688 | device mosfet phv mvpfet mvpdiff,mvpdiffres,mvpdc nwell 3689 | device mosfet nhv mvnfet mvndiff,mvndiffres,mvndc pwell,space/w 3690 | device mosfet nhvnative mvnnfet *mvndiff,mvndiffres pwell,space/w 3691 | 3692 | # These devices always extract as subcircuits 3693 | device subcircuit xcnwvc varactor *nndiff nwell error l=l w=w 3694 | device subcircuit xcnwvc2 varhvt *nndiff nwell error l=l w=w 3695 | device subcircuit xchvnwc mvvaractor *mvnndiff nwell error l=l w=w 3696 | 3697 | device resistor short rmp *poly 3698 | device resistor short rli1 *li,coreli 3699 | device resistor short rmetal1 *metal1 3700 | device resistor short rmetal2 *metal2 3701 | device resistor short rmetal3 *metal3 3702 | device resistor short rm4 *m4 3703 | device resistor short rm5 *m5 3704 | 3705 | device resistor xhrpoly xhrpoly xpc 3706 | device resistor uhrpoly uhrpoly xpc 3707 | device resistor mrp1 mrp1 *poly 3708 | device resistor mrdn ndiffres *ndiff 3709 | device resistor mrdp pdiffres *pdiff 3710 | device resistor mrdn_hv mvndiffres *mvndiff 3711 | device resistor mrdp_hv mvpdiffres *mvpdiff 3712 | device resistor xpwres rpw pwell 3713 | 3714 | device pdiode pdiode *pdiode nwell a=a p=p 3715 | device ndiode ndiode *ndiode pwell,space/w a=a p=p 3716 | device pdiode pdiode_h *mvpdiode nwell a=a p=p 3717 | device ndiode ndiode_h *mvndiode pwell,space/w a=a p=p 3718 | 3719 | # These are parasitic devices 3720 | device ndiode ndiode_lvt *ndiodelvt pwell,space/w a=a p=p 3721 | device pdiode pdiode_lvt *pdiodelvt nwell a=a p=p 3722 | device pdiode pdiode_hvt *pdiodehvt nwell a=a p=p 3723 | device ndiode ndiode_native *nndiode pwell,space/w a=a p=p 3724 | 3725 | device subcircuit pdiode_h *mvpdiode nwell a=a p=p 3726 | device msubcircuit ndiode_h *mvndiode pwell,space/w a=a p=p 3727 | 3728 | 3729 | device capacitor xcmimc1 *mimcap *m3 1 3730 | device capacitor xcmimc2 *mimcap2 *m4 1 3731 | 3732 | end 3733 | 3734 | #----------------------------------------------------- 3735 | # Wiring tool definitions 3736 | #----------------------------------------------------- 3737 | 3738 | wiring 3739 | # All wiring values are in nanometers 3740 | scalefactor 10 3741 | 3742 | contact lic 170 li 0 0 m1 30 60 3743 | contact v1 260 m1 0 30 m2 0 30 3744 | contact v2 280 m2 0 45 m3 25 0 3745 | contact v3 320 m3 0 30 m4 5 5 3746 | contact v4 1180 m4 0 m5 120 3747 | 3748 | contact pc 170 poly 50 80 li 0 80 3749 | contact pdc 170 pdiff 40 60 li 0 80 3750 | contact ndc 170 ndiff 40 60 li 0 80 3751 | contact psc 170 psd 40 60 li 0 80 3752 | contact nsc 170 nsd 40 60 li 0 80 3753 | 3754 | end 3755 | 3756 | #----------------------------------------------------- 3757 | # Plain old router. . . 3758 | #----------------------------------------------------- 3759 | 3760 | router 3761 | end 3762 | 3763 | #------------------------------------------------------------ 3764 | # Plowing (restored in magic 8.2, need to fill this section) 3765 | #------------------------------------------------------------ 3766 | 3767 | plowing 3768 | end 3769 | 3770 | #----------------------------------------------------------------- 3771 | # No special plot layers defined (use default PNM color choices) 3772 | #----------------------------------------------------------------- 3773 | 3774 | plot 3775 | style pnm 3776 | default 3777 | draw fillblock no_color_at_all 3778 | draw nwell cwell 3779 | end 3780 | 3781 | -------------------------------------------------------------------------------- /sky130_inv.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech sky130A 3 | timestamp 1600540370 4 | << nwell >> 5 | rect -20 114 157 304 6 | << nmos >> 7 | rect 49 41 72 76 8 | << pmos >> 9 | rect 49 196 72 233 10 | << ndiff >> 11 | rect 10 71 49 76 12 | rect 10 46 19 71 13 | rect 37 46 49 71 14 | rect 10 41 49 46 15 | rect 72 71 113 76 16 | rect 72 46 87 71 17 | rect 105 46 113 71 18 | rect 72 41 113 46 19 | << pdiff >> 20 | rect 8 228 49 233 21 | rect 8 203 18 228 22 | rect 36 203 49 228 23 | rect 8 196 49 203 24 | rect 72 227 111 233 25 | rect 72 202 84 227 26 | rect 102 202 111 227 27 | rect 72 196 111 202 28 | << ndiffc >> 29 | rect 19 46 37 71 30 | rect 87 46 105 71 31 | << pdiffc >> 32 | rect 18 203 36 228 33 | rect 84 202 102 227 34 | << psubdiff >> 35 | rect 12 13 129 14 36 | rect 12 -8 46 13 37 | rect 63 -8 80 13 38 | rect 97 -8 129 13 39 | << nsubdiff >> 40 | rect 12 285 130 286 41 | rect 12 261 45 285 42 | rect 63 261 80 285 43 | rect 98 261 130 285 44 | << psubdiffcont >> 45 | rect 46 -8 63 13 46 | rect 80 -8 97 13 47 | << nsubdiffcont >> 48 | rect 45 261 63 285 49 | rect 80 261 98 285 50 | << poly >> 51 | rect 49 233 72 250 52 | rect 49 169 72 196 53 | rect 6 161 72 169 54 | rect 6 126 14 161 55 | rect 42 126 72 161 56 | rect 6 118 72 126 57 | rect 49 76 72 118 58 | rect 49 27 72 41 59 | << polycont >> 60 | rect 14 126 42 161 61 | << locali >> 62 | rect -20 285 143 290 63 | rect -20 281 45 285 64 | rect -20 264 23 281 65 | rect 40 264 45 281 66 | rect -20 261 45 264 67 | rect 63 261 80 285 68 | rect 98 282 143 285 69 | rect 98 265 100 282 70 | rect 117 265 143 282 71 | rect 98 261 143 265 72 | rect -20 258 143 261 73 | rect 18 233 35 258 74 | rect 10 228 44 233 75 | rect 10 203 18 228 76 | rect 36 203 44 228 77 | rect 10 197 44 203 78 | rect 76 227 110 233 79 | rect 76 202 84 227 80 | rect 102 202 110 227 81 | rect 76 196 110 202 82 | rect 88 169 105 196 83 | rect 6 161 51 169 84 | rect 6 126 14 161 85 | rect 42 126 51 161 86 | rect 6 118 51 126 87 | rect 88 118 133 169 88 | rect 88 76 105 118 89 | rect 10 71 45 76 90 | rect 10 46 19 71 91 | rect 37 46 45 71 92 | rect 10 41 45 46 93 | rect 78 71 113 76 94 | rect 78 46 87 71 95 | rect 105 46 113 71 96 | rect 78 41 113 46 97 | rect 15 21 38 41 98 | rect 0 13 146 21 99 | rect 0 8 46 13 100 | rect 0 -9 21 8 101 | rect 38 -8 46 8 102 | rect 63 -8 80 13 103 | rect 97 8 146 13 104 | rect 97 -8 105 8 105 | rect 38 -9 105 -8 106 | rect 122 -9 146 8 107 | rect 0 -15 146 -9 108 | << viali >> 109 | rect 23 264 40 281 110 | rect 100 265 117 282 111 | rect 21 -9 38 8 112 | rect 105 -9 122 8 113 | << metal1 >> 114 | rect -20 282 157 296 115 | rect -20 281 100 282 116 | rect -20 264 23 281 117 | rect 40 265 100 281 118 | rect 117 265 157 282 119 | rect 40 264 157 265 120 | rect -20 248 157 264 121 | rect -11 8 157 24 122 | rect -11 -9 21 8 123 | rect 38 -9 105 8 124 | rect 122 -9 157 8 125 | rect -11 -24 157 -9 126 | << labels >> 127 | flabel metal1 s 44 258 90 289 0 FreeSans 120 0 0 0 VPWR 128 | port 3 nsew power bidirectional 129 | flabel locali s 10 121 45 164 0 FreeSans 120 0 0 0 A 130 | port 1 nsew signal input 131 | flabel locali s 96 121 131 164 0 FreeSans 120 0 0 0 Y 132 | port 2 nsew signal output 133 | flabel metal1 s 50 -3 105 26 0 FreeSans 120 0 0 0 VGND 134 | port 5 nsew ground bidirectional 135 | << properties >> 136 | string LEFsite unithd 137 | string LEFclass CORE 138 | string FIXED_BBOX 0 0 138 272 139 | string LEFsource USER 140 | string LEForigin 0 0 141 | << end >> 142 | --------------------------------------------------------------------------------