├── .cargo └── config.toml ├── .github └── workflows │ └── ci.yml ├── .gitignore ├── .vscode ├── .cortex-debug.peripherals.state.json ├── .cortex-debug.registers.state.json ├── extensions.json ├── launch.json └── settings.json ├── Cargo.toml ├── LICENSE ├── README.md ├── boards ├── .gitignore ├── Cargo.toml ├── bootloaders │ ├── imx8mn │ │ ├── .cargo │ │ │ └── config.toml │ │ ├── Cargo.toml │ │ ├── debug.md │ │ ├── imx8mn.bin │ │ ├── link.lds │ │ └── src │ │ │ ├── boot.rs │ │ │ ├── entry.S │ │ │ └── main.rs │ ├── nrf52840 │ │ ├── .cargo │ │ │ └── config.toml │ │ ├── Cargo.toml │ │ ├── README.md │ │ ├── build.rs │ │ ├── memory.x │ │ ├── nrf52840.svd │ │ └── src │ │ │ └── main.rs │ ├── rp2040 │ │ ├── .cargo │ │ │ └── config.toml │ │ ├── Cargo.toml │ │ ├── build.rs │ │ ├── memory.x │ │ └── src │ │ │ └── main.rs │ ├── rpi4 │ │ ├── .cargo │ │ │ └── config.toml │ │ ├── Cargo.toml │ │ ├── README.md │ │ ├── apertis │ │ │ ├── decompiled-bcm2711-rpi-4-b.dts │ │ │ ├── initramfs │ │ │ ├── rbconfig.txt │ │ │ ├── rpi4-apertis.its │ │ │ ├── signed-rpi4-apertis.itb │ │ │ ├── unpatched-bcm2711-rpi-4-b.dtb │ │ │ ├── update-rpi4-apertis.its │ │ │ ├── updt.txt │ │ │ └── vmlinuz │ │ ├── debug.md │ │ ├── layout.ld │ │ ├── rustBoot.bin │ │ ├── rustBoot1.bin │ │ └── src │ │ │ ├── boot.rs │ │ │ ├── boot.s │ │ │ ├── dtb.rs │ │ │ ├── fit.rs │ │ │ ├── log.rs │ │ │ └── main.rs │ ├── stm32f334 │ │ ├── .cargo │ │ │ └── config.toml │ │ ├── Cargo.toml │ │ ├── build.rs │ │ ├── memory.x │ │ └── src │ │ │ └── main.rs │ ├── stm32f411 │ │ ├── .cargo │ │ │ └── config.toml │ │ ├── Cargo.toml │ │ ├── build.rs │ │ ├── memory.x │ │ └── src │ │ │ └── main.rs │ ├── stm32f446 │ │ ├── .cargo │ │ │ └── config.toml │ │ ├── Cargo.toml │ │ ├── build.rs │ │ ├── debug.md │ │ ├── memory.x │ │ └── src │ │ │ └── main.rs │ ├── stm32f469 │ │ ├── .cargo │ │ │ └── config.toml │ │ ├── Cargo.toml │ │ ├── build.rs │ │ ├── memory.x │ │ └── src │ │ │ └── main.rs │ ├── stm32f746 │ │ ├── .cargo │ │ │ └── config.toml │ │ ├── .gitignore │ │ ├── Cargo.toml │ │ ├── build.rs │ │ ├── memory.x │ │ └── src │ │ │ └── main.rs │ └── stm32h723 │ │ ├── .cargo │ │ └── config.toml │ │ ├── Cargo.toml │ │ ├── README.md │ │ ├── STM32H723.svd │ │ ├── build.rs │ │ ├── debug.md │ │ ├── memory.x │ │ └── src │ │ └── main.rs ├── firmware │ ├── nrf52840 │ │ ├── boot_fw_blinky_green │ │ │ ├── .cargo │ │ │ │ └── config.toml │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ │ └── main.rs │ │ └── updt_fw_blinky_red │ │ │ ├── .cargo │ │ │ └── config.toml │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ └── main.rs │ ├── rp2040 │ │ ├── boot_fw_blinky_green │ │ │ ├── .cargo │ │ │ │ └── config.toml │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ │ └── main.rs │ │ └── updt_fw_blinky_red │ │ │ ├── .cargo │ │ │ └── config.toml │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ └── main.rs │ ├── stm32f334 │ │ ├── boot_fw_blinky_green │ │ │ ├── .cargo │ │ │ │ └── config.toml │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ │ └── main.rs │ │ └── updt_fw_blinky_red │ │ │ ├── .cargo │ │ │ └── config.toml │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ └── main.rs │ ├── stm32f411 │ │ ├── boot_fw_blinky_green │ │ │ ├── .cargo │ │ │ │ └── config.toml │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ │ └── main.rs │ │ └── updt_fw_blinky_red │ │ │ ├── .cargo │ │ │ └── config.toml │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ └── main.rs │ ├── stm32f446 │ │ ├── boot_fw_blinky_green │ │ │ ├── .cargo │ │ │ │ └── config.toml │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ │ └── main.rs │ │ └── updt_fw_blinky_red │ │ │ ├── .cargo │ │ │ └── config.toml │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ └── main.rs │ ├── stm32f469 │ │ ├── boot_fw_blinky_green │ │ │ ├── .cargo │ │ │ │ └── config.toml │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ │ └── main.rs │ │ └── updt_fw_blinky_red │ │ │ ├── .cargo │ │ │ └── config.toml │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ └── main.rs │ ├── stm32f746 │ │ ├── boot_fw_blinky_green │ │ │ ├── .cargo │ │ │ │ └── config.toml │ │ │ ├── .gitignore │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ │ └── main.rs │ │ └── updt_fw_blinky_red │ │ │ ├── .cargo │ │ │ └── config.toml │ │ │ ├── .gitignore │ │ │ ├── Cargo.toml │ │ │ ├── build.rs │ │ │ ├── memory.x │ │ │ └── src │ │ │ └── main.rs │ └── stm32h723 │ │ ├── boot_fw_blinky_green │ │ ├── .cargo │ │ │ └── config.toml │ │ ├── Cargo.toml │ │ ├── build.rs │ │ ├── memory.x │ │ └── src │ │ │ └── main.rs │ │ └── updt_fw_blinky_red │ │ ├── .cargo │ │ └── config.toml │ │ ├── Cargo.toml │ │ ├── build.rs │ │ ├── memory.x │ │ └── src │ │ └── main.rs ├── hal │ ├── Cargo.toml │ └── src │ │ ├── lib.rs │ │ ├── nrf │ │ ├── mod.rs │ │ └── nrf52840.rs │ │ ├── nxp │ │ ├── imx8mn │ │ │ ├── aarch64-cpu │ │ │ │ ├── Cargo.toml │ │ │ │ ├── LICENSE-APACHE │ │ │ │ ├── LICENSE-MIT │ │ │ │ ├── README.md │ │ │ │ └── src │ │ │ │ │ ├── asm.rs │ │ │ │ │ ├── asm │ │ │ │ │ ├── barrier.rs │ │ │ │ │ └── random.rs │ │ │ │ │ ├── lib.rs │ │ │ │ │ ├── registers.rs │ │ │ │ │ └── registers │ │ │ │ │ ├── actlr_el1.rs │ │ │ │ │ ├── actlr_el2.rs │ │ │ │ │ ├── actlr_el3.rs │ │ │ │ │ ├── ccsidr_el1.rs │ │ │ │ │ ├── clidr_el1.rs │ │ │ │ │ ├── cntfrq_el0.rs │ │ │ │ │ ├── cnthctl_el2.rs │ │ │ │ │ ├── cntp_ctl_el0.rs │ │ │ │ │ ├── cntp_cval_el0.rs │ │ │ │ │ ├── cntp_tval_el0.rs │ │ │ │ │ ├── cntpct_el0.rs │ │ │ │ │ ├── cntv_ctl_el0.rs │ │ │ │ │ ├── cntv_cval_el0.rs │ │ │ │ │ ├── cntv_tval_el0.rs │ │ │ │ │ ├── cntvct_el0.rs │ │ │ │ │ ├── cntvoff_el2.rs │ │ │ │ │ ├── cpacr_el1.rs │ │ │ │ │ ├── csselr_el1.rs │ │ │ │ │ ├── currentel.rs │ │ │ │ │ ├── dacr32_el2.rs │ │ │ │ │ ├── daif.rs │ │ │ │ │ ├── dbgdtr_el0.rs │ │ │ │ │ ├── dbgdtrrx_el0.rs │ │ │ │ │ ├── dbgdtrtx_el0.rs │ │ │ │ │ ├── elr_el1.rs │ │ │ │ │ ├── elr_el2.rs │ │ │ │ │ ├── elr_el3.rs │ │ │ │ │ ├── esr_el1.rs │ │ │ │ │ ├── esr_el2.rs │ │ │ │ │ ├── esr_el3.rs │ │ │ │ │ ├── far_el1.rs │ │ │ │ │ ├── far_el2.rs │ │ │ │ │ ├── far_el3.rs │ │ │ │ │ ├── fp.rs │ │ │ │ │ ├── hcr_el2.rs │ │ │ │ │ ├── id_aa64isar0_el1.rs │ │ │ │ │ ├── id_aa64mmfr0_el1.rs │ │ │ │ │ ├── id_aa64mmfr1_el1.rs │ │ │ │ │ ├── id_aa64mmfr2_el1.rs │ │ │ │ │ ├── lr.rs │ │ │ │ │ ├── macros.rs │ │ │ │ │ ├── mair_el1.rs │ │ │ │ │ ├── mair_el2.rs │ │ │ │ │ ├── mair_el3.rs │ │ │ │ │ ├── mdccsr_el0.rs │ │ │ │ │ ├── midr_el1.rs │ │ │ │ │ ├── mpidr_el1.rs │ │ │ │ │ ├── oslar_el1.rs │ │ │ │ │ ├── par_el1.rs │ │ │ │ │ ├── rvbar_el1.rs │ │ │ │ │ ├── rvbar_el2.rs │ │ │ │ │ ├── rvbar_el3.rs │ │ │ │ │ ├── scr_el3.rs │ │ │ │ │ ├── sctlr_el1.rs │ │ │ │ │ ├── sctlr_el2.rs │ │ │ │ │ ├── sctlr_el3.rs │ │ │ │ │ ├── sp.rs │ │ │ │ │ ├── sp_el0.rs │ │ │ │ │ ├── sp_el1.rs │ │ │ │ │ ├── spsel.rs │ │ │ │ │ ├── spsr_el1.rs │ │ │ │ │ ├── spsr_el2.rs │ │ │ │ │ ├── spsr_el3.rs │ │ │ │ │ ├── tcr_el1.rs │ │ │ │ │ ├── tcr_el2.rs │ │ │ │ │ ├── tpidr_el0.rs │ │ │ │ │ ├── tpidr_el1.rs │ │ │ │ │ ├── tpidr_el2.rs │ │ │ │ │ ├── tpidrro_el0.rs │ │ │ │ │ ├── ttbr0_el1.rs │ │ │ │ │ ├── ttbr0_el2.rs │ │ │ │ │ ├── ttbr1_el1.rs │ │ │ │ │ ├── vbar_el1.rs │ │ │ │ │ ├── vbar_el2.rs │ │ │ │ │ ├── vbar_el3.rs │ │ │ │ │ ├── vtcr_el2.rs │ │ │ │ │ └── vttbr_el2.rs │ │ │ ├── arch │ │ │ │ ├── cpu_core.rs │ │ │ │ ├── mod.rs │ │ │ │ └── timer.rs │ │ │ ├── bsp │ │ │ │ ├── clocks │ │ │ │ │ ├── analog.rs │ │ │ │ │ ├── ccm.rs │ │ │ │ │ ├── mod.rs │ │ │ │ │ ├── scntrclk.rs │ │ │ │ │ ├── uartclks.rs │ │ │ │ │ └── usdhcclks.rs │ │ │ │ ├── counter.rs │ │ │ │ ├── drivers │ │ │ │ │ ├── common.rs │ │ │ │ │ ├── driver_manager.rs │ │ │ │ │ ├── gpio.rs │ │ │ │ │ ├── mod.rs │ │ │ │ │ ├── uart0.rs │ │ │ │ │ └── usdhc.rs │ │ │ │ ├── global.rs │ │ │ │ ├── memory_map.rs │ │ │ │ ├── mod.rs │ │ │ │ └── mux │ │ │ │ │ ├── iomuxc.rs │ │ │ │ │ ├── mod.rs │ │ │ │ │ ├── uart2grp.rs │ │ │ │ │ └── usdhc2grp.rs │ │ │ ├── exception │ │ │ │ ├── asynchronous.rs │ │ │ │ ├── exception.rs │ │ │ │ ├── exception.s │ │ │ │ └── mod.rs │ │ │ ├── log │ │ │ │ ├── console.rs │ │ │ │ ├── mod.rs │ │ │ │ └── print.rs │ │ │ ├── memory │ │ │ │ ├── mmu.rs │ │ │ │ └── mod.rs │ │ │ ├── mod.rs │ │ │ ├── panic_wait.rs │ │ │ └── sync.rs │ │ └── mod.rs │ │ ├── pico │ │ ├── mod.rs │ │ └── rp2040.rs │ │ ├── rpi │ │ ├── mod.rs │ │ └── rpi4 │ │ │ ├── arch │ │ │ ├── cpu_core.rs │ │ │ ├── mod.rs │ │ │ └── time.rs │ │ │ ├── bsp │ │ │ ├── drivers │ │ │ │ ├── common.rs │ │ │ │ ├── driver_manager.rs │ │ │ │ ├── emmc.rs │ │ │ │ ├── gpio.rs │ │ │ │ ├── mod.rs │ │ │ │ └── uart0.rs │ │ │ ├── global.rs │ │ │ ├── memory_map.rs │ │ │ └── mod.rs │ │ │ ├── exception │ │ │ ├── asynchronous.rs │ │ │ ├── exception.rs │ │ │ ├── exception.s │ │ │ └── mod.rs │ │ │ ├── log │ │ │ ├── console.rs │ │ │ ├── mod.rs │ │ │ └── print.rs │ │ │ ├── memory │ │ │ ├── layout.rs │ │ │ ├── mmu.rs │ │ │ ├── mod.rs │ │ │ ├── tt.rs │ │ │ └── vmm.rs │ │ │ ├── mod.rs │ │ │ ├── panic_wait.rs │ │ │ └── sync.rs │ │ └── stm │ │ ├── mod.rs │ │ ├── stm32f334.rs │ │ ├── stm32f411.rs │ │ ├── stm32f446.rs │ │ ├── stm32f469.rs │ │ ├── stm32f746.rs │ │ └── stm32h723.rs ├── sign_images │ ├── keygen │ │ ├── ecc256.der │ │ └── pubkey.c │ └── signed_images │ │ └── trailer_magic.bin └── update │ ├── Cargo.toml │ └── src │ ├── hal │ ├── hal.rs │ └── mod.rs │ ├── lib.rs │ └── update │ ├── mod.rs │ └── update_flash.rs ├── rbsigner ├── Cargo.toml └── src │ ├── curve.rs │ ├── fitsigner.rs │ ├── main.rs │ └── mcusigner.rs ├── rustBoot ├── Cargo.toml ├── examples │ ├── dtb2rust.rs │ ├── fit.rs │ ├── fit_timestamp.rs │ ├── imx8mn-ddr4-evk.dtb │ ├── imx8mn-ddr4-evk.dts │ ├── patch.rs │ ├── patch_chosen_node.rs │ ├── updt_check.rs │ └── verify_fit.rs └── src │ ├── cfgparser.rs │ ├── constants.rs │ ├── crypto │ ├── mod.rs │ └── signatures.rs │ ├── dt │ ├── common.rs │ ├── fit.rs │ ├── internal.rs │ ├── mod.rs │ ├── patch.rs │ ├── reader.rs │ ├── struct_item.rs │ ├── test_dtb │ │ ├── bad_magic.dtb │ │ ├── bad_node_name.dtb │ │ ├── bad_property_name.dtb │ │ ├── bad_reserved_mem_offset.dtb │ │ ├── bad_str_encoding.dtb │ │ ├── bad_str_encoding2.dtb │ │ ├── bad_struct_token.dtb │ │ ├── bad_total_size.dtb │ │ ├── bad_version.dtb │ │ ├── no_zero_reserved_mem_entry.dtb │ │ ├── out_of_parent_node.dtb │ │ ├── overlapping_reserved_mem.dtb │ │ ├── overlapping_strings.dtb │ │ ├── overlapping_struct.dtb │ │ ├── sample.dtb │ │ ├── sample2.dtb │ │ ├── unaligned_reserved_mem.dtb │ │ ├── unaligned_struct.dtb │ │ ├── unaligned_struct2.dtb │ │ ├── unexpected_end_of_blob.dtb │ │ ├── unexpected_end_of_struct.dtb │ │ ├── unexpected_end_of_struct2.dtb │ │ ├── unexpected_end_of_struct3.dtb │ │ └── unsupported_comp_version.dtb │ └── writer.rs │ ├── flashapi.rs │ ├── fs │ ├── blockdevice.rs │ ├── controller.rs │ ├── fat.rs │ ├── filesystem.rs │ ├── mod.rs │ └── structure.rs │ ├── image │ ├── image.rs │ ├── mod.rs │ └── sealed.rs │ ├── lib.rs │ ├── parser.rs │ └── rbconstants.rs └── xtask ├── Cargo.toml └── src └── main.rs /.cargo/config.toml: -------------------------------------------------------------------------------- 1 | [alias] 2 | xtask = 'run -p xtask --' 3 | nrf52840 = 'run -p xtask --features nrf52840 -- nrf52840' 4 | stm32f411 = 'run -p xtask --features stm32f411 -- stm32f411' 5 | stm32f446 = 'run -p xtask --features stm32f446 -- stm32f446' 6 | stm32f469 = 'run -p xtask --features stm32f469 -- stm32f469' 7 | stm32h723 = 'run -p xtask --features stm32h723 -- stm32h723' 8 | stm32f746 = 'run -p xtask --features stm32f746 -- stm32f746' 9 | stm32f334 = 'run -p xtask --features stm32f334 -- stm32f334' 10 | rp2040 = 'run -p xtask --features rp2040 -- rp2040' 11 | rpi4 = 'run -p xtask -- rpi4' 12 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /rustBoot/src/dt/writer_test.rs 2 | /rustBoot/src/dt/reader_test.rs 3 | /rustBoot/examples/fit2.rs 4 | /rustBoot/examples/patch2.rs 5 | /rustBoot/examples/test.rs 6 | /rustBoot/src/disk.img 7 | /target 8 | Cargo.lock 9 | .gdb_history 10 | test.md 11 | **/*.DS_Store 12 | /boards/bootloaders/rpi4-test/ 13 | /boards/bootloaders/rpi4/layout_copy.ld 14 | /boards/bootloaders/rpi4/bl_objdump.s 15 | /boards/bootloaders/rpi4/failtestdump.s 16 | /boards/bootloaders/rpi4/testdump.s 17 | /boards/bootloaders/rpi4/output.txt 18 | /boards/bootloaders/rpi4/kernel8.img 19 | /boards/bootloaders/rpi4/apertis/signed-v* 20 | dts 21 | /boards/bootloaders/imx8mn/imx8mn.bin -------------------------------------------------------------------------------- /.vscode/.cortex-debug.peripherals.state.json: -------------------------------------------------------------------------------- 1 | [] -------------------------------------------------------------------------------- /.vscode/.cortex-debug.registers.state.json: -------------------------------------------------------------------------------- 1 | [] -------------------------------------------------------------------------------- /.vscode/extensions.json: -------------------------------------------------------------------------------- 1 | { 2 | "recommendations": [ 3 | "dan-c-underwood.arm", 4 | "eamodio.gitlens" 5 | ] 6 | } -------------------------------------------------------------------------------- /.vscode/settings.json: -------------------------------------------------------------------------------- 1 | { 2 | "rust-analyzer.linkedProjects": [ 3 | "Cargo.toml", 4 | "boards/Cargo.toml", 5 | ], 6 | "rust-analyzer.checkOnSave.allTargets": false, 7 | "rust-analyzer.updates.channel": "nightly", 8 | "files.associations": { 9 | "*.x": "linkerscript" 10 | }, 11 | "cortex-debug.registerUseNaturalFormat": false, 12 | "cortex-debug.variableUseNaturalFormat": false 13 | } -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- 1 | [workspace] 2 | 3 | resolver = "2" 4 | members = [ 5 | "rustBoot", 6 | "xtask", 7 | "rbsigner" 8 | ] -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 nihalpasham 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. -------------------------------------------------------------------------------- /boards/.gitignore: -------------------------------------------------------------------------------- 1 | /target 2 | Cargo.lock 3 | /sign_images/signed_images/*.bin 4 | /hal/src/nxp/imx8mn/aarch64-cpu/target 5 | 6 | -------------------------------------------------------------------------------- /boards/Cargo.toml: -------------------------------------------------------------------------------- 1 | [workspace] 2 | 3 | resolver = "2" 4 | members = ["update", 5 | "hal", 6 | "firmware/*/*", 7 | "bootloaders/*" 8 | ] 9 | 10 | [profile.dev] 11 | incremental = false 12 | codegen-units = 1 13 | debug = true 14 | lto = false 15 | 16 | [profile.release] 17 | debug = true 18 | lto = true 19 | opt-level = 2 20 | -------------------------------------------------------------------------------- /boards/bootloaders/imx8mn/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-A i.e. Aarch64 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "aarch64-unknown-none-softfloat" 7 | rustflags = [ 8 | "-C", "link-arg=-Tbootloaders/imx8mn/link.lds", 9 | "-C", "target-cpu=cortex-a53", 10 | ] -------------------------------------------------------------------------------- /boards/bootloaders/imx8mn/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | edition = "2021" 3 | name = "imx8mn-rs" 4 | version = "0.1.0" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [dependencies] 9 | log = {version = "0.4.16", default-features = false} 10 | # rustBoot = {path = "../../../rustBoot", default-features = true} 11 | rustBoot-hal = {path = "../../hal", default-features = false, features = ["nxp", "imx8mn"]} 12 | tock-registers = {version = "0.8.1", default-features = false, features = ["register_types"]} 13 | # zeroize = {version = "1.5.7", default-features = false, features = ["zeroize_derive"]} 14 | -------------------------------------------------------------------------------- /boards/bootloaders/imx8mn/imx8mn.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nihalpasham/rustBoot/d4394d383ba3758574159c6630e4c3261a6b47f1/boards/bootloaders/imx8mn/imx8mn.bin -------------------------------------------------------------------------------- /boards/bootloaders/imx8mn/src/boot.rs: -------------------------------------------------------------------------------- 1 | //! Architectural boot code. 2 | 3 | use core::arch::global_asm; 4 | 5 | use crate::kernel_init; 6 | use crate::{ 7 | clocks, exception, memory, 8 | mux::{uart2grp::uart2_mux_mmio_set, usdhc2grp::usdhc2_mux_mmio_set}, 9 | start_system_counter, 10 | }; 11 | 12 | // Assembly counterpart to this file. 13 | global_asm!(include_str!("entry.s")); 14 | 15 | /// The Rust entry of the `kernel` binary. 16 | /// 17 | /// The function is called from the assembly `_start` function. 18 | /// 19 | #[no_mangle] 20 | pub unsafe extern "C" fn _start_rust() -> ! { 21 | // disable i and d caching, mmu is already disabled. 22 | memory::mmu::mmu().disable_mmu_and_caching(); 23 | // set the vector base address for excpetion handlers 24 | exception::exception::handling_init(); 25 | // ungate sys_counter clock 26 | clocks::scntrclk::enable_sctr(); 27 | // start the system counter, this allows us to access ARM's architectural counter - CNTPCT_EL0 28 | start_system_counter(); 29 | // enable Uart and uSDHC clock 30 | clocks::uartclks::enable_uart_clk(1); 31 | clocks::usdhcclks::enable_usdhc_clk(2); 32 | // set mux state for UART2 and uSDHC2 peripherals. 33 | uart2_mux_mmio_set(); 34 | usdhc2_mux_mmio_set(); 35 | // jump to next init stage. 36 | kernel_init() 37 | } 38 | -------------------------------------------------------------------------------- /boards/bootloaders/nrf52840/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | runner = "probe-run --chip nRF52840_xxAA" # runner specific to nrf52840. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | "-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/bootloaders/nrf52840/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | build = "build.rs" 3 | edition = "2018" 4 | name = "nrf52840" 5 | version = "0.1.0" 6 | 7 | # makes `cargo check --all-targets` work 8 | [[bin]] 9 | bench = false 10 | doctest = false 11 | name = "nrf52840" 12 | test = false 13 | 14 | [dependencies] 15 | cortex-m = { version = "0.7.7", features = ["critical-section-single-core"] } 16 | cortex-m-rt = "0.7" 17 | defmt = {version = "0.3.2", optional = true} 18 | defmt-rtt = {version = "0.4.0", optional = true} 19 | rustBoot-hal = {path = "../../hal", features = ["nrf52840", "nrf"]} 20 | rustBoot-update = {path = "../../update", features = ["nrf52840"]} 21 | 22 | [features] 23 | default = ["defmt", "defmt-rtt"] 24 | 25 | # [workspace] -------------------------------------------------------------------------------- /boards/bootloaders/nrf52840/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/bootloaders/nrf52840/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* NOTE 1 K = 1 KiBi = 1024 bytes */ 4 | /* TODO Adjust these memory regions to match your device memory layout */ 5 | /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */ 6 | FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K 7 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K 8 | } 9 | 10 | /* This is where the call stack will be allocated. */ 11 | /* The stack is of the full descending type. */ 12 | /* You may want to use this variable to locate the call stack and static 13 | variables in different memory regions. Below is shown the default value */ 14 | /* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ 15 | 16 | /* You can use this symbol to customize the location of the .text section */ 17 | /* If omitted the .text section will be placed right after the .vector_table 18 | section */ 19 | /* This is required only on microcontrollers that store some configuration right 20 | after the vector table */ 21 | /* _stext = ORIGIN(FLASH) + 0x400; */ 22 | 23 | /* Example of putting non-initialized variables into custom RAM locations. */ 24 | /* This assumes you have defined a region RAM2 above, and in the Rust 25 | sources added the attribute `#[link_section = ".ram2bss"]` to the data 26 | you want to place there. */ 27 | /* Note that the section will not be zero-initialized by the runtime! */ 28 | /* SECTIONS { 29 | .ram2bss (NOLOAD) : ALIGN(4) { 30 | *(.ram2bss); 31 | . = ALIGN(4); 32 | } > RAM2 33 | } INSERT AFTER .bss; 34 | */ -------------------------------------------------------------------------------- /boards/bootloaders/nrf52840/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | #[cfg(feature = "defmt")] 5 | use defmt_rtt as _; // global logger 6 | use rustBoot_hal::nrf::nrf52840::FlashWriterEraser; 7 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 8 | 9 | use cortex_m_rt::entry; 10 | 11 | #[entry] 12 | fn main() -> ! { 13 | let updater = FlashUpdater::new(FlashWriterEraser::new()); 14 | updater.rustboot_start() 15 | } 16 | 17 | #[panic_handler] // panicking behavior 18 | fn panic(_: &core::panic::PanicInfo) -> ! { 19 | loop { 20 | cortex_m::asm::bkpt(); 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /boards/bootloaders/rp2040/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 2 | runner = "probe-run --chip RP2040" 3 | # runner = "elf2uf2-rs -d" 4 | # runner = "arm-none-eabi-gdb -q -x openocd.gdb" 5 | 6 | rustflags = [ 7 | "-C", "linker=flip-link", 8 | "-C", "link-arg=--nmagic", 9 | "-C", "link-arg=-Tlink.x", 10 | # "-C", "link-arg=-Tdefmt.x", 11 | "-C", "inline-threshold=5", 12 | "-C", "no-vectorize-loops", 13 | ] 14 | 15 | [build] 16 | target = "thumbv6m-none-eabi" 17 | 18 | # [env] 19 | # DEFMT_LOG = "debug" 20 | -------------------------------------------------------------------------------- /boards/bootloaders/rp2040/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | edition = "2021" 3 | name = "rp2040" 4 | version = "0.1.0" 5 | resolver = "2" 6 | 7 | [dependencies] 8 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 9 | cortex-m-rt = "0.7" 10 | rp2040-boot2 = "0.2.1" 11 | rustBoot-hal = { path = "../../hal", default-features = false, features = ["rp2040"] } 12 | rustBoot-update = { path = "../../update", features = ["rp2040"] } 13 | 14 | # defmt = { version = "0.3.0", optional = true } 15 | # defmt-rtt = { version = "0.3.0", optional = true } 16 | # panic-probe = { version = "0.3.0", features = ["print-defmt"] } 17 | 18 | # [features] 19 | # default = ["defmt", "defmt-rtt"] 20 | -------------------------------------------------------------------------------- /boards/bootloaders/rp2040/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 8 | File::create(out.join("memory.x")) 9 | .unwrap() 10 | .write_all(include_bytes!("memory.x")) 11 | .unwrap(); 12 | println!("cargo:rustc-link-search={}", out.display()); 13 | println!("cargo:rerun-if-changed=build.rs"); 14 | println!("cargo:rerun-if-changed=memory.x"); 15 | } 16 | -------------------------------------------------------------------------------- /boards/bootloaders/rp2040/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | BOOT2 : ORIGIN = 0x10000000, LENGTH = 0x100 3 | FLASH : ORIGIN = 0x10000100, LENGTH = 2048K - 0x100 4 | RAM : ORIGIN = 0x20000000, LENGTH = 264K 5 | } 6 | 7 | EXTERN(BOOT2_FIRMWARE) 8 | 9 | SECTIONS { 10 | .boot2 ORIGIN(BOOT2): 11 | { 12 | KEEP(*(.boot2)); 13 | } > BOOT2 14 | } INSERT BEFORE .text; -------------------------------------------------------------------------------- /boards/bootloaders/rp2040/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | // #[cfg(feature = "defmt")] 5 | // use defmt_rtt as _; // global logger 6 | 7 | use cortex_m_rt::entry; 8 | use rustBoot_hal::pico::rp2040::FlashWriterEraser; 9 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 10 | 11 | 12 | /// This is the second-Stage bootloader. RP2040 is a stateless device, 13 | /// with support for cached execute-in-place from external QSPI memory. 14 | /// This will put 256 byte header right at the start of the eventual program binary, 15 | /// required to configure external QSPI flash memory (W25Q080) for high speed, efficient, code access. 16 | #[link_section = ".boot2"] 17 | #[used] 18 | pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER_W25Q080; 19 | 20 | #[entry] 21 | fn main() -> ! { 22 | let updater = FlashUpdater::new(FlashWriterEraser::new()); 23 | updater.rustboot_start() 24 | } 25 | 26 | #[panic_handler] // panicking behavior 27 | fn panic(_: &core::panic::PanicInfo) -> ! { 28 | loop { 29 | cortex_m::asm::bkpt(); 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /boards/bootloaders/rpi4/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-A i.e. Aarch64 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "aarch64-unknown-none-softfloat" 7 | rustflags = [ 8 | "-C", "link-arg=-Tbootloaders/rpi4/layout.ld", 9 | "-C", "target-cpu=cortex-a72", 10 | ] -------------------------------------------------------------------------------- /boards/bootloaders/rpi4/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | edition = "2021" 3 | name = "rpi4" 4 | version = "0.1.0" 5 | 6 | [[bin]] 7 | name = "kernel" 8 | path = "src/main.rs" 9 | 10 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 11 | 12 | [dependencies] 13 | cortex-a = {version = "7.0.1"} 14 | log = {version = "0.4.16", default-features = false} 15 | rustBoot = {path = "../../../rustBoot", default-features = true} 16 | rustBoot-hal = {path = "../../hal", default-features = false, features = ["rpi", "rpi4"]} 17 | tock-registers = {version = "0.7.x", default-features = false, features = ["register_types"]} 18 | zeroize = {version = "1.5.7", default-features = false, features = ["zeroize_derive"]} 19 | -------------------------------------------------------------------------------- /boards/bootloaders/rpi4/README.md: -------------------------------------------------------------------------------- 1 | 2 | We have one example for the [rpi4](https://www.raspberrypi.org/products/raspberry-pi-4-model-b/). 3 | 4 | placeholder ..... -------------------------------------------------------------------------------- /boards/bootloaders/rpi4/apertis/initramfs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nihalpasham/rustBoot/d4394d383ba3758574159c6630e4c3261a6b47f1/boards/bootloaders/rpi4/apertis/initramfs -------------------------------------------------------------------------------- /boards/bootloaders/rpi4/apertis/rbconfig.txt: -------------------------------------------------------------------------------- 1 | bootargs="root=UUID=64bc182a-ca9d-4aa1-8936-d2919863c22a rootwait ro plymouth.ignore-serial-consoles fsck.mode=auto fsck.repair=yes cma=128M" -------------------------------------------------------------------------------- /boards/bootloaders/rpi4/apertis/signed-rpi4-apertis.itb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nihalpasham/rustBoot/d4394d383ba3758574159c6630e4c3261a6b47f1/boards/bootloaders/rpi4/apertis/signed-rpi4-apertis.itb -------------------------------------------------------------------------------- /boards/bootloaders/rpi4/apertis/unpatched-bcm2711-rpi-4-b.dtb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nihalpasham/rustBoot/d4394d383ba3758574159c6630e4c3261a6b47f1/boards/bootloaders/rpi4/apertis/unpatched-bcm2711-rpi-4-b.dtb -------------------------------------------------------------------------------- /boards/bootloaders/rpi4/apertis/updt.txt: -------------------------------------------------------------------------------- 1 | [active] 2 | image_name=signed-rpi4-apertis.itb 3 | image_version=ts_1654328925 4 | 5 | [passive] 6 | ready_for_update_flag=true 7 | image_name=signed-v1663342128.itb 8 | image_version=ts_1663342128 9 | update_status=updating -------------------------------------------------------------------------------- /boards/bootloaders/rpi4/apertis/vmlinuz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nihalpasham/rustBoot/d4394d383ba3758574159c6630e4c3261a6b47f1/boards/bootloaders/rpi4/apertis/vmlinuz -------------------------------------------------------------------------------- /boards/bootloaders/rpi4/rustBoot.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nihalpasham/rustBoot/d4394d383ba3758574159c6630e4c3261a6b47f1/boards/bootloaders/rpi4/rustBoot.bin -------------------------------------------------------------------------------- /boards/bootloaders/rpi4/rustBoot1.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nihalpasham/rustBoot/d4394d383ba3758574159c6630e4c3261a6b47f1/boards/bootloaders/rpi4/rustBoot1.bin -------------------------------------------------------------------------------- /boards/bootloaders/rpi4/src/log.rs: -------------------------------------------------------------------------------- 1 | use cortex_a::asm::barrier; 2 | use log::{Level, Metadata, Record}; 3 | use log::{LevelFilter, SetLoggerError}; 4 | 5 | use rustBoot_hal::info; 6 | 7 | struct Logger; 8 | 9 | impl log::Log for Logger { 10 | fn enabled(&self, metadata: &Metadata) -> bool { 11 | metadata.level() <= Level::Info 12 | } 13 | 14 | fn log(&self, record: &Record) { 15 | if self.enabled(record.metadata()) { 16 | info!("\x1b[93m[{}]\x1b[0m {}", record.level(), record.args()); 17 | match (record.module_path(), record.line()) { 18 | (Some(file), Some(line)) => { 19 | info!(" - {} @ line:{}", file, line); 20 | } 21 | (None, None) => { 22 | info!("... ") 23 | } 24 | (None, Some(line)) => info!("\t \u{2a3d} {} @ line:{}", record.target(), line), 25 | (Some(file), None) => info!("\t \u{2a3d} @ {}", file), 26 | } 27 | } 28 | } 29 | 30 | fn flush(&self) {} 31 | } 32 | 33 | static LOGGER: Logger = Logger; 34 | 35 | pub fn init() -> Result<(), SetLoggerError> { 36 | unsafe { log::set_logger_racy(&LOGGER).map(|()| log::set_max_level(LevelFilter::Info)) } 37 | } 38 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f334/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | runner = "probe-run --chip stm32f334r8tx" # runner specific to stm32f334r8tx. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | #"-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/bootloaders/stm32f334/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f334" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [[bin]] 9 | bench = false 10 | doctest = false 11 | name = "stm32f334" 12 | test = false 13 | 14 | [dependencies] 15 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 16 | cortex-m-rt = "0.7" 17 | defmt = {version = "0.3.2", optional = true} 18 | defmt-rtt = {version = "0.4.0", optional = true} 19 | rustBoot-hal = {path = "../../hal", default-features = false, features = ["stm32f334"]} 20 | rustBoot-update = {path = "../../update", features = ["stm32f334"]} 21 | 22 | [features] 23 | default = ["defmt","defmt-rtt"] -------------------------------------------------------------------------------- /boards/bootloaders/stm32f334/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f334/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K 3 | CCMRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 4K 4 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 12K 5 | } 6 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f334/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | #[cfg(feature = "defmt")] 5 | use defmt_rtt as _; // global logger 6 | 7 | use rustBoot_hal::stm::stm32f334::FlashWriterEraser; 8 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 9 | 10 | use cortex_m_rt::entry; 11 | 12 | #[entry] 13 | fn main() -> ! { 14 | let updater = FlashUpdater::new(FlashWriterEraser::new()); 15 | updater.rustboot_start() 16 | } 17 | 18 | #[panic_handler] // panicking behavior 19 | fn panic(_: &core::panic::PanicInfo) -> ! { 20 | loop { 21 | cortex_m::asm::bkpt(); 22 | } 23 | } -------------------------------------------------------------------------------- /boards/bootloaders/stm32f411/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | runner = "probe-run --chip stm32f411vetx" # runner specific to stm32f411vetx. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | # "-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/bootloaders/stm32f411/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f411" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [[bin]] 9 | bench = false 10 | doctest = false 11 | name = "stm32f411" 12 | test = false 13 | 14 | [dependencies] 15 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 16 | cortex-m-rt = "0.7" 17 | # defmt = {version = "0.3.1", optional = true} 18 | # defmt-rtt = {version = "0.3.2", optional = true} 19 | rustBoot-hal = {path = "../../hal", default-features = false, features = ["stm32f411"]} 20 | rustBoot-update = {path = "../../update", features = ["stm32f411"]} 21 | 22 | [features] 23 | default = [] 24 | 25 | # [workspace] 26 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f411/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f411/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* NOTE 1 K = 1 KiBi = 1024 bytes */ 4 | /* TODO Adjust these memory regions to match your device memory layout */ 5 | /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */ 6 | /* We'll need prepend a 256-byte rustBoot header. So add an offset - 0x100 */ 7 | FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K 8 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K 9 | } 10 | 11 | /* This is where the call stack will be allocated. */ 12 | /* The stack is of the full descending type. */ 13 | /* You may want to use this variable to locate the call stack and static 14 | variables in different memory regions. Below is shown the default value */ 15 | /* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ 16 | 17 | /* You can use this symbol to customize the location of the .text section */ 18 | /* If omitted the .text section will be placed right after the .vector_table 19 | section */ 20 | /* This is required only on microcontrollers that store some configuration right 21 | after the vector table */ 22 | /* _stext = ORIGIN(FLASH) + 0x400; */ 23 | 24 | /* Example of putting non-initialized variables into custom RAM locations. */ 25 | /* This assumes you have defined a region RAM2 above, and in the Rust 26 | sources added the attribute `#[link_section = ".ram2bss"]` to the data 27 | you want to place there. */ 28 | /* Note that the section will not be zero-initialized by the runtime! */ 29 | /* SECTIONS { 30 | .ram2bss (NOLOAD) : ALIGN(4) { 31 | *(.ram2bss); 32 | . = ALIGN(4); 33 | } > RAM2 34 | } INSERT AFTER .bss; 35 | */ -------------------------------------------------------------------------------- /boards/bootloaders/stm32f411/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | // #[cfg(feature = "defmt")] 5 | // use defmt_rtt as _; // global logger 6 | // use panic_probe as _; 7 | 8 | use rustBoot_hal::stm::stm32f411::FlashWriterEraser; 9 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 10 | 11 | use cortex_m_rt::entry; 12 | 13 | #[entry] 14 | fn main() -> ! { 15 | let updater = FlashUpdater::new(FlashWriterEraser::new()); 16 | updater.rustboot_start() 17 | } 18 | 19 | #[panic_handler] // panicking behavior 20 | fn panic(_: &core::panic::PanicInfo) -> ! { 21 | loop { 22 | cortex_m::asm::bkpt(); 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f446/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | runner = "probe-run --chip stm32f446retx" # runner specific to stm32f446retx. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | # "-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/bootloaders/stm32f446/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f446" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [[bin]] 9 | bench = false 10 | doctest = false 11 | name = "stm32f446" 12 | test = false 13 | 14 | [dependencies] 15 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 16 | cortex-m-rt = "0.7" 17 | # defmt = {version = "0.3.1", optional = true} 18 | # defmt-rtt = {version = "0.3.2", optional = true} 19 | rustBoot-hal = {path = "../../hal", default-features =false, features= ["stm32f446" ]} 20 | rustBoot-update = {path = "../../update", features = ["stm32f446"]} 21 | 22 | [features] 23 | default = [] 24 | 25 | # [workspace] 26 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f446/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f446/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* NOTE 1 K = 1 KiBi = 1024 bytes */ 4 | /* TODO Adjust these memory regions to match your device memory layout */ 5 | /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */ 6 | /* We'll need prepend a 256-byte rustBoot header. So add an offset - 0x100 */ 7 | FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K 8 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K 9 | } 10 | 11 | /* This is where the call stack will be allocated. */ 12 | /* The stack is of the full descending type. */ 13 | /* You may want to use this variable to locate the call stack and static 14 | variables in different memory regions. Below is shown the default value */ 15 | /* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ 16 | 17 | /* You can use this symbol to customize the location of the .text section */ 18 | /* If omitted the .text section will be placed right after the .vector_table 19 | section */ 20 | /* This is required only on microcontrollers that store some configuration right 21 | after the vector table */ 22 | /* _stext = ORIGIN(FLASH) + 0x400; */ 23 | 24 | /* Example of putting non-initialized variables into custom RAM locations. */ 25 | /* This assumes you have defined a region RAM2 above, and in the Rust 26 | sources added the attribute `#[link_section = ".ram2bss"]` to the data 27 | you want to place there. */ 28 | /* Note that the section will not be zero-initialized by the runtime! */ 29 | /* SECTIONS { 30 | .ram2bss (NOLOAD) : ALIGN(4) { 31 | *(.ram2bss); 32 | . = ALIGN(4); 33 | } > RAM2 34 | } INSERT AFTER .bss; 35 | */ -------------------------------------------------------------------------------- /boards/bootloaders/stm32f446/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | #[cfg(feature = "defmt")] 5 | use defmt_rtt as _; // global logger 6 | use rustBoot_hal::stm::stm32f446::FlashWriterEraser; 7 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 8 | 9 | use cortex_m_rt::entry; 10 | 11 | #[entry] 12 | fn main() -> ! { 13 | let updater = FlashUpdater::new(FlashWriterEraser::new()); 14 | updater.rustboot_start() 15 | } 16 | 17 | #[panic_handler] // panicking behavior 18 | fn panic(_: &core::panic::PanicInfo) -> ! { 19 | loop { 20 | cortex_m::asm::bkpt(); 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f469/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | runner = "probe-run --chip STM32F469NIHx" # runner specific to STM32F469NIHx. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | # "-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] 18 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f469/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f469" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [[bin]] 9 | bench = false 10 | doctest = false 11 | name = "stm32f469" 12 | test = false 13 | 14 | [dependencies] 15 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 16 | cortex-m-rt = "0.7" 17 | # defmt = {version = "0.3.1", optional = true} 18 | # defmt-rtt = {version = "0.3.2", optional = true} 19 | rustBoot-hal = {path = "../../hal", default-features = false, features = ["stm32f469"]} 20 | rustBoot-update = {path = "../../update", features = ["stm32f469"]} 21 | 22 | [features] 23 | default = [] 24 | 25 | # [workspace] 26 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f469/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f469/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* NOTE 1 K = 1 KiBi = 1024 bytes */ 4 | /* TODO Adjust these memory regions to match your device memory layout */ 5 | /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */ 6 | /* We'll need prepend a 256-byte rustBoot header. So add an offset - 0x100 */ 7 | FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K 8 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K 9 | } 10 | 11 | /* This is where the call stack will be allocated. */ 12 | /* The stack is of the full descending type. */ 13 | /* You may want to use this variable to locate the call stack and static 14 | variables in different memory regions. Below is shown the default value */ 15 | /* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ 16 | 17 | /* You can use this symbol to customize the location of the .text section */ 18 | /* If omitted the .text section will be placed right after the .vector_table 19 | section */ 20 | /* This is required only on microcontrollers that store some configuration right 21 | after the vector table */ 22 | /* _stext = ORIGIN(FLASH) + 0x400; */ 23 | 24 | /* Example of putting non-initialized variables into custom RAM locations. */ 25 | /* This assumes you have defined a region RAM2 above, and in the Rust 26 | sources added the attribute `#[link_section = ".ram2bss"]` to the data 27 | you want to place there. */ 28 | /* Note that the section will not be zero-initialized by the runtime! */ 29 | /* SECTIONS { 30 | .ram2bss (NOLOAD) : ALIGN(4) { 31 | *(.ram2bss); 32 | . = ALIGN(4); 33 | } > RAM2 34 | } INSERT AFTER .bss; 35 | */ -------------------------------------------------------------------------------- /boards/bootloaders/stm32f469/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | // #[cfg(feature = "defmt")] 5 | // use defmt_rtt as _; // global logger 6 | // use panic_probe as _; 7 | 8 | use rustBoot_hal::stm::stm32f469::FlashWriterEraser; 9 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 10 | 11 | use cortex_m_rt::entry; 12 | 13 | #[entry] 14 | fn main() -> ! { 15 | let updater = FlashUpdater::new(FlashWriterEraser::new()); 16 | updater.rustboot_start() 17 | } 18 | 19 | #[panic_handler] // panicking behavior 20 | fn panic(_: &core::panic::PanicInfo) -> ! { 21 | loop { 22 | cortex_m::asm::bkpt(); 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f746/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | [build] 2 | target = "thumbv7em-none-eabihf" 3 | 4 | 5 | [target.thumbv7em-none-eabihf] 6 | runner = "arm-none-eabi-gdb -q -tui -x openocd.gdb" 7 | 8 | 9 | rustflags = [ 10 | "-C", "linker=flip-link", 11 | "-C", "link-arg=-Tlink.x", 12 | "-C", "link-arg=-Tdefmt.x", 13 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 14 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 15 | "-C", "link-arg=--nmagic", 16 | ] 17 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f746/.gitignore: -------------------------------------------------------------------------------- 1 | /target 2 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f746/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f746" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [[bin]] 9 | bench = false 10 | doctest = false 11 | name = "stm32f746" 12 | test = false 13 | 14 | 15 | [dependencies] 16 | cortex-m-rt = "0.7" 17 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 18 | # panic-halt = "0.2.0" 19 | stm32f7xx-hal = {version = "0.7.0", features = ["stm32f746", "rt"]} 20 | rustBoot-hal = {path = "../../hal", default-features = false, features = ["stm32f746"]} 21 | rustBoot-update = {path = "../../update", features = ["stm32f746"]} 22 | defmt = {version = "0.3.1", optional = true} 23 | defmt-rtt = {version = "0.3.2", optional = true} 24 | 25 | 26 | [features] 27 | default = ["defmt","defmt-rtt"] 28 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f746/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32f746/memory.x: -------------------------------------------------------------------------------- 1 | /* For STM32F7{45,46,56} devices */ 2 | MEMORY 3 | { 4 | /* NOTE K = KiBi = 1024 bytes */ 5 | FLASH : ORIGIN = 0x08000000, LENGTH = 1M 6 | RAM : ORIGIN = 0x20000000, LENGTH = 128K 7 | } 8 | 9 | /* This is where the call stack will be allocated. */ 10 | /* The stack is of the full descending type. */ 11 | /* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ 12 | /*_stack_start = ORIGIN(RAM) + LENGTH(RAM); */ -------------------------------------------------------------------------------- /boards/bootloaders/stm32f746/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | #[cfg(feature = "defmt")] 5 | use defmt_rtt as _; // global logger 6 | 7 | use cortex_m_rt::entry; 8 | 9 | use rustBoot_hal::stm::stm32f746::FlashWriterEraser; 10 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 11 | 12 | #[entry] 13 | fn main() -> ! { 14 | let updater = FlashUpdater::new(FlashWriterEraser::new()); 15 | updater.rustboot_start() 16 | } 17 | 18 | #[panic_handler] // panicking behavior 19 | fn panic(_: &core::panic::PanicInfo) -> ! { 20 | loop { 21 | cortex_m::asm::bkpt(); 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32h723/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 2 | runner = "probe-run --chip STM32H723ZGIx" 3 | 4 | rustflags = [ 5 | "-C", "linker=flip-link", 6 | "-C", "link-arg=-Tlink.x", 7 | "-C", "link-arg=-Tdefmt.x", 8 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 9 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 10 | "-C", "link-arg=--nmagic", 11 | ] 12 | 13 | [build] 14 | # (`thumbv6m-*` is compatible with all ARM Cortex-M chips but using the right 15 | # target improves performance) 16 | # target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ 17 | # target = "thumbv7m-none-eabi" # Cortex-M3 18 | # target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) 19 | target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) -------------------------------------------------------------------------------- /boards/bootloaders/stm32h723/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32h723" 3 | version = "0.1.0" 4 | edition = "2021" 5 | build = "build.rs" 6 | 7 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 8 | 9 | [[bin]] 10 | bench = false 11 | doctest = false 12 | name = "stm32h723" 13 | test = false 14 | 15 | [dependencies] 16 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 17 | cortex-m-rt = "0.7" 18 | defmt = {version = "0.3.1", optional = true} 19 | defmt-rtt = {version = "0.3.2", optional = true} 20 | rustBoot-hal = {path = "../../hal", default-features = false, features = ["stm32h723"]} 21 | rustBoot-update = {path = "../../update", features = ["stm32h723"]} 22 | 23 | [features] 24 | default = ["defmt", "defmt-rtt"] 25 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32h723/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32h723/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* FLASH and RAM are mandatory memory regions */ 4 | 5 | /* STM32H742xI/743xI/753xI */ 6 | /* STM32H745xI/747xI/755xI/757xI */ 7 | /* STM32H7A3xI/7B3xI */ 8 | FLASH : ORIGIN = 0x08000000, LENGTH = 128K 9 | 10 | /* STM32H742xG/743xG */ 11 | /* STM32H745xG/STM32H747xG */ 12 | /* STM32H7A3xG */ 13 | /* FLASH : ORIGIN = 0x08000000, LENGTH = 512K */ 14 | /* FLASH1 : ORIGIN = 0x08100000, LENGTH = 512K */ 15 | 16 | /* STM32H750xB */ 17 | /* STM32H7B0 */ 18 | /* FLASH : ORIGIN = 0x08000000, LENGTH = 1M */ 19 | 20 | /* DTCM */ 21 | RAM : ORIGIN = 0x20000000, LENGTH = 128K 22 | } 23 | -------------------------------------------------------------------------------- /boards/bootloaders/stm32h723/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | #[cfg(feature = "defmt")] 5 | use defmt_rtt as _; // global logger 6 | 7 | use rustBoot_hal::stm::stm32h723::FlashWriterEraser; 8 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 9 | 10 | use cortex_m_rt::entry; 11 | 12 | #[entry] 13 | fn main() -> ! { 14 | let updater = FlashUpdater::new(FlashWriterEraser::new()); 15 | updater.rustboot_start() 16 | } 17 | 18 | #[panic_handler] // panicking behavior 19 | fn panic(_: &core::panic::PanicInfo) -> ! { 20 | loop { 21 | cortex_m::asm::bkpt(); 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /boards/firmware/nrf52840/boot_fw_blinky_green/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | # [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | # runner = "probe-run --chip nRF52840_xxAA" # runner specific to nrf52840. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | # "-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/firmware/nrf52840/boot_fw_blinky_green/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "nrf52840_bootfw" 3 | version = "0.1.0" 4 | edition = "2018" 5 | build = "build.rs" 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | # makes `cargo check --all-targets` work 9 | [[bin]] 10 | name = "nrf52840_bootfw" 11 | bench = false 12 | doctest = false 13 | test = false 14 | 15 | [dependencies] 16 | # defmt = "0.2.3" 17 | # defmt-rtt = "0.2.0" 18 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 19 | cortex-m-rt = "0.7" 20 | nrf52840-hal = "0.16.0" 21 | panic-probe = { version = "0.3.0" } 22 | rustBoot-hal = {path = "../../../hal", default-features = false, features = ["nrf52840", "nrf"]} 23 | rustBoot-update = {path = "../../../update", features = ["nrf52840"]} 24 | 25 | [features] 26 | 27 | 28 | # [workspace] -------------------------------------------------------------------------------- /boards/firmware/nrf52840/boot_fw_blinky_green/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/nrf52840/boot_fw_blinky_green/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* NOTE 1 K = 1 KiBi = 1024 bytes */ 4 | /* TODO Adjust these memory regions to match your device memory layout */ 5 | /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */ 6 | /* We'll need prepend a 256-byte rustBoot header. So add an offset - 0x100 */ 7 | FLASH (rx) : ORIGIN = 0x2f100, LENGTH = 159K 8 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K 9 | } 10 | 11 | /* This is where the call stack will be allocated. */ 12 | /* The stack is of the full descending type. */ 13 | /* You may want to use this variable to locate the call stack and static 14 | variables in different memory regions. Below is shown the default value */ 15 | /* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ 16 | 17 | /* You can use this symbol to customize the location of the .text section */ 18 | /* If omitted the .text section will be placed right after the .vector_table 19 | section */ 20 | /* This is required only on microcontrollers that store some configuration right 21 | after the vector table */ 22 | /* _stext = ORIGIN(FLASH) + 0x400; */ 23 | 24 | /* Example of putting non-initialized variables into custom RAM locations. */ 25 | /* This assumes you have defined a region RAM2 above, and in the Rust 26 | sources added the attribute `#[link_section = ".ram2bss"]` to the data 27 | you want to place there. */ 28 | /* Note that the section will not be zero-initialized by the runtime! */ 29 | /* SECTIONS { 30 | .ram2bss (NOLOAD) : ALIGN(4) { 31 | *(.ram2bss); 32 | . = ALIGN(4); 33 | } > RAM2 34 | } INSERT AFTER .bss; 35 | */ -------------------------------------------------------------------------------- /boards/firmware/nrf52840/updt_fw_blinky_red/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | # [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | # runner = "probe-run --chip nRF52840_xxAA" # runner specific to nrf52840. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | # "-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/firmware/nrf52840/updt_fw_blinky_red/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "nrf52840_updtfw" 3 | version = "0.1.0" 4 | edition = "2018" 5 | build = "build.rs" 6 | 7 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 8 | 9 | # makes `cargo check --all-targets` work 10 | [[bin]] 11 | name = "nrf52840_updtfw" 12 | bench = false 13 | doctest = false 14 | test = false 15 | 16 | [dependencies] 17 | # defmt = "0.2.3" 18 | # defmt-rtt = "0.2.0" 19 | cortex-m-rt = "0.7" 20 | nrf52840-hal = "0.16.0" 21 | panic-probe = { version = "0.2.0" } 22 | rustBoot-hal = {path = "../../../hal", default-features = false, features = ["nrf52840", "nrf"]} 23 | rustBoot-update = {path = "../../../update", features = ["nrf52840"]} 24 | 25 | [features] 26 | 27 | 28 | # [workspace] -------------------------------------------------------------------------------- /boards/firmware/nrf52840/updt_fw_blinky_red/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/nrf52840/updt_fw_blinky_red/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* NOTE 1 K = 1 KiBi = 1024 bytes */ 4 | /* TODO Adjust these memory regions to match your device memory layout */ 5 | /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */ 6 | /* We'll need prepend a 256-byte rustBoot header. So add an offset - 0x100 */ 7 | FLASH (rx) : ORIGIN = 0x2f100, LENGTH = 159K 8 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K 9 | } 10 | 11 | /* This is where the call stack will be allocated. */ 12 | /* The stack is of the full descending type. */ 13 | /* You may want to use this variable to locate the call stack and static 14 | variables in different memory regions. Below is shown the default value */ 15 | /* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ 16 | 17 | /* You can use this symbol to customize the location of the .text section */ 18 | /* If omitted the .text section will be placed right after the .vector_table 19 | section */ 20 | /* This is required only on microcontrollers that store some configuration right 21 | after the vector table */ 22 | /* _stext = ORIGIN(FLASH) + 0x400; */ 23 | 24 | /* Example of putting non-initialized variables into custom RAM locations. */ 25 | /* This assumes you have defined a region RAM2 above, and in the Rust 26 | sources added the attribute `#[link_section = ".ram2bss"]` to the data 27 | you want to place there. */ 28 | /* Note that the section will not be zero-initialized by the runtime! */ 29 | /* SECTIONS { 30 | .ram2bss (NOLOAD) : ALIGN(4) { 31 | *(.ram2bss); 32 | . = ALIGN(4); 33 | } > RAM2 34 | } INSERT AFTER .bss; 35 | */ -------------------------------------------------------------------------------- /boards/firmware/rp2040/boot_fw_blinky_green/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | 2 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 3 | runner = "probe-run --chip RP2040" 4 | # runner = "elf2uf2-rs -d" 5 | # runner = "arm-none-eabi-gdb -q -x openocd.gdb" 6 | 7 | rustflags = [ 8 | "-C", "linker=flip-link", 9 | "-C", "link-arg=--nmagic", 10 | "-C", "link-arg=-Tlink.x", 11 | # "-C", "link-arg=-Tdefmt.x", 12 | "-C", "inline-threshold=5", 13 | "-C", "no-vectorize-loops", 14 | ] 15 | 16 | [build] 17 | target = "thumbv6m-none-eabi" 18 | 19 | # [env] 20 | # DEFMT_LOG = "debug" 21 | -------------------------------------------------------------------------------- /boards/firmware/rp2040/boot_fw_blinky_green/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | edition = "2021" 3 | name = "rp2040_bootfw" 4 | version = "0.1.0" 5 | resolver = "2" 6 | 7 | [[bin]] 8 | name = "rp2040_bootfw" 9 | bench = false 10 | doctest = false 11 | test = false 12 | 13 | [dependencies] 14 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 15 | cortex-m-rt = "0.7" 16 | embedded-hal = { version = "0.2.7", features = ["unproven"] } 17 | rp2040-hal = "0.7.0" 18 | rustBoot-hal = { path = "../../../hal", default-features = false, features = ["rp2040"]} 19 | rustBoot-update = { path = "../../../update", features = ["rp2040"] } 20 | 21 | # defmt = { version = "0.3.0", optional = true } 22 | # defmt-rtt = { version = "0.3.0", optional = true } 23 | # panic-probe = { version = "0.3.0", features = ["print-defmt"] } 24 | 25 | # [features] 26 | # default = ["defmt", "defmt-rtt"] 27 | -------------------------------------------------------------------------------- /boards/firmware/rp2040/boot_fw_blinky_green/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 8 | File::create(out.join("memory.x")) 9 | .unwrap() 10 | .write_all(include_bytes!("memory.x")) 11 | .unwrap(); 12 | println!("cargo:rustc-link-search={}", out.display()); 13 | println!("cargo:rerun-if-changed=build.rs"); 14 | println!("cargo:rerun-if-changed=memory.x"); 15 | } 16 | -------------------------------------------------------------------------------- /boards/firmware/rp2040/boot_fw_blinky_green/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH : ORIGIN = 0x10020100, LENGTH = 2048K 3 | RAM : ORIGIN = 0x20000000, LENGTH = 264K 4 | } -------------------------------------------------------------------------------- /boards/firmware/rp2040/boot_fw_blinky_green/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | // #[cfg(feature = "defmt")] 5 | // use defmt_rtt as _; // global logger 6 | // use panic_probe as _; // global logger 7 | // use defmt::*; 8 | 9 | use cortex_m_rt::entry; 10 | use cortex_m::asm; 11 | 12 | use embedded_hal::digital::v2::OutputPin; 13 | use rp2040_hal as hal; 14 | 15 | use rustBoot_hal::pico::rp2040::FlashWriterEraser; 16 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 17 | 18 | #[entry] 19 | fn main() -> ! { 20 | 21 | let mut pac = hal::pac::Peripherals::take().unwrap(); 22 | let sio = hal::Sio::new(pac.SIO); 23 | let pins = hal::gpio::Pins::new( 24 | pac.IO_BANK0, 25 | pac.PADS_BANK0, 26 | sio.gpio_bank0, 27 | &mut pac.RESETS, 28 | ); 29 | let mut led_pin = pins.gpio25.into_push_pull_output(); 30 | 31 | let mut count = 0u8; 32 | while count < 5 { 33 | led_pin.set_high().unwrap(); 34 | asm::delay(32_00_000); // 1 Sec 35 | led_pin.set_low().unwrap(); 36 | asm::delay(32_00_000); // 1 Sec 37 | count += 1; 38 | } 39 | 40 | let flash_writer = FlashWriterEraser {}; 41 | let updater = FlashUpdater::new(flash_writer); 42 | 43 | match updater.update_trigger() { 44 | Ok(_v) => {} 45 | Err(e) => panic!("couldnt trigger update: {}", e), 46 | } 47 | 48 | hal::pac::SCB::sys_reset() 49 | } 50 | 51 | #[panic_handler] // panicking behavior 52 | fn panic(_: &core::panic::PanicInfo) -> ! { 53 | loop { 54 | cortex_m::asm::bkpt(); 55 | } 56 | } 57 | // End of file 58 | -------------------------------------------------------------------------------- /boards/firmware/rp2040/updt_fw_blinky_red/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | 2 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 3 | runner = "probe-run --chip RP2040" 4 | # runner = "elf2uf2-rs -d" 5 | # runner = "arm-none-eabi-gdb -q -x openocd.gdb" 6 | 7 | rustflags = [ 8 | "-C", "linker=flip-link", 9 | "-C", "link-arg=--nmagic", 10 | "-C", "link-arg=-Tlink.x", 11 | # "-C", "link-arg=-Tdefmt.x", 12 | "-C", "inline-threshold=5", 13 | "-C", "no-vectorize-loops", 14 | ] 15 | 16 | [build] 17 | target = "thumbv6m-none-eabi" 18 | 19 | # [env] 20 | # DEFMT_LOG = "debug" 21 | -------------------------------------------------------------------------------- /boards/firmware/rp2040/updt_fw_blinky_red/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | edition = "2021" 3 | name = "rp2040_updtfw" 4 | version = "0.1.0" 5 | resolver = "2" 6 | 7 | [[bin]] 8 | name = "rp2040_updtfw" 9 | bench = false 10 | doctest = false 11 | test = false 12 | 13 | [dependencies] 14 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 15 | cortex-m-rt = "0.7" 16 | embedded-hal = { version = "0.2.7", features = ["unproven"] } 17 | rp2040-hal = "0.7.0" 18 | rustBoot-hal = { path = "../../../hal", default-features = false, features = ["rp2040"]} 19 | rustBoot-update = { path = "../../../update", features = ["rp2040"] } 20 | 21 | # defmt = { version = "0.3.0", optional = true } 22 | # defmt-rtt = { version = "0.3.0", optional = true } 23 | # panic-probe = { version = "0.3.0", features = ["print-defmt"] } 24 | 25 | # [features] 26 | # default = ["defmt", "defmt-rtt"] 27 | -------------------------------------------------------------------------------- /boards/firmware/rp2040/updt_fw_blinky_red/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 8 | File::create(out.join("memory.x")) 9 | .unwrap() 10 | .write_all(include_bytes!("memory.x")) 11 | .unwrap(); 12 | println!("cargo:rustc-link-search={}", out.display()); 13 | println!("cargo:rerun-if-changed=build.rs"); 14 | println!("cargo:rerun-if-changed=memory.x"); 15 | } 16 | -------------------------------------------------------------------------------- /boards/firmware/rp2040/updt_fw_blinky_red/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH : ORIGIN = 0x10020100, LENGTH = 2048K 3 | RAM : ORIGIN = 0x20000000, LENGTH = 264K 4 | } -------------------------------------------------------------------------------- /boards/firmware/rp2040/updt_fw_blinky_red/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | // #[cfg(feature = "defmt")] 5 | // use defmt_rtt as _; // global logger 6 | // use panic_probe as _; // global logger 7 | // use defmt::*; 8 | 9 | use cortex_m_rt::entry; 10 | use cortex_m::asm; 11 | 12 | use embedded_hal::digital::v2::OutputPin; 13 | use rp2040_hal as hal; 14 | 15 | use rustBoot_hal::pico::rp2040::FlashWriterEraser; 16 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 17 | 18 | #[entry] 19 | fn main() -> ! { 20 | 21 | let mut pac = hal::pac::Peripherals::take().unwrap(); 22 | let sio = hal::Sio::new(pac.SIO); 23 | let pins = hal::gpio::Pins::new ( 24 | pac.IO_BANK0, 25 | pac.PADS_BANK0, 26 | sio.gpio_bank0, 27 | &mut pac.RESETS, 28 | ); 29 | let mut led_pin = pins.gpio25.into_push_pull_output(); 30 | 31 | let flash_writer = FlashWriterEraser {}; 32 | let updater = FlashUpdater::new(flash_writer); 33 | 34 | match updater.update_success() { 35 | Ok(_v) => {} 36 | Err(e) => panic!("couldnt trigger update: {}", e), 37 | } 38 | 39 | loop { 40 | led_pin.set_high().unwrap(); 41 | asm::delay(4_00_000); // 125 mSec 42 | led_pin.set_low().unwrap(); 43 | asm::delay(4_00_000); // 125 mSec 44 | } 45 | } 46 | 47 | #[panic_handler] // panicking behavior 48 | fn panic(_: &core::panic::PanicInfo) -> ! { 49 | loop { 50 | cortex_m::asm::bkpt(); 51 | } 52 | } 53 | // End of file 54 | -------------------------------------------------------------------------------- /boards/firmware/stm32f334/boot_fw_blinky_green/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | # [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | #runner = "probe-run --chip stm32f334r8tx" # runner specific to nrf52840. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | #"-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/firmware/stm32f334/boot_fw_blinky_green/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f334_bootfw" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | [[bin]] 7 | name = "stm32f334_bootfw" 8 | bench = false 9 | doctest = false 10 | test = false 11 | 12 | [dependencies] 13 | #defmt = {version = "0.3.1", optional = true} 14 | #defmt-rtt = {version = "0.3.2", optional = true} 15 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 16 | cortex-m-rt = "0.7" 17 | rustBoot-hal ={path = "../../../hal",default-features = false,features = ["stm32f334"]} 18 | panic-probe = { version = "0.3.0" } 19 | rustBoot-update = {path = "../../../update", features = ["stm32f334"]} 20 | 21 | # board-specific features 22 | [dependencies.stm32f3xx-hal] 23 | version = "0.9.1" 24 | features = ["stm32f334x8"] 25 | 26 | [features] 27 | default = [] -------------------------------------------------------------------------------- /boards/firmware/stm32f334/boot_fw_blinky_green/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32f334/boot_fw_blinky_green/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH (rx) : ORIGIN = 0x800B900, LENGTH = 64K 3 | CCMRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 4K 4 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 12K 5 | } 6 | -------------------------------------------------------------------------------- /boards/firmware/stm32f334/boot_fw_blinky_green/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | extern crate cortex_m; 5 | extern crate cortex_m_rt; 6 | 7 | //#[cfg(feature = "defmt")] 8 | //use defmt_rtt as _; // global logger 9 | 10 | extern crate stm32f3xx_hal as mcu; 11 | use cortex_m::peripheral::Peripherals; 12 | use cortex_m::asm; 13 | use cortex_m_rt::entry; 14 | use mcu::{pac, prelude::*}; 15 | 16 | use rustBoot_hal::stm::stm32f334::FlashWriterEraser; 17 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 18 | 19 | #[entry] 20 | fn main() -> ! { 21 | if let (Some(peri), Some(_cortex_peri)) = (pac::Peripherals::take(), Peripherals::take()){ 22 | 23 | let mut rcc = peri.RCC.constrain(); 24 | let mut gpioa = peri.GPIOA.split(&mut rcc.ahb); 25 | let mut led = gpioa.pa5.into_push_pull_output(&mut gpioa.moder, &mut gpioa.otyper); 26 | 27 | let flash1 = peri.FLASH; 28 | let mut count = 0; 29 | 30 | while count < 6 { 31 | led.toggle().unwrap(); 32 | asm::delay(8000_000); 33 | count += 1; 34 | } 35 | 36 | let flash_writer = FlashWriterEraser { nvm: flash1 }; 37 | let updater = FlashUpdater::new(flash_writer); 38 | 39 | match updater.update_trigger() { 40 | Ok(_v) => {} 41 | Err(e) => panic!("couldnt trigger update: {}", e) 42 | } 43 | 44 | } 45 | mcu::pac::SCB::sys_reset() 46 | } 47 | 48 | #[panic_handler] // panicking behavior 49 | fn panic(_: &core::panic::PanicInfo) -> ! { 50 | loop { 51 | cortex_m::asm::bkpt(); 52 | } 53 | } -------------------------------------------------------------------------------- /boards/firmware/stm32f334/updt_fw_blinky_red/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | # [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | #runner = "probe-run --chip stm32f334r8tx" # runner specific to nrf52840. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | #"-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/firmware/stm32f334/updt_fw_blinky_red/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f334_updtfw" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | [[bin]] 7 | name = "stm32f334_updtfw" 8 | bench = false 9 | doctest = false 10 | test = false 11 | 12 | [dependencies] 13 | #defmt = {version = "0.3.1", optional = true} 14 | #defmt-rtt = {version = "0.3.2", optional = true} 15 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 16 | cortex-m-rt = "0.7" 17 | rustBoot-hal ={path = "../../../hal",default-features = false,features = ["stm32f334"]} 18 | panic-probe = { version = "0.3.0" } 19 | rustBoot-update = {path = "../../../update", features = ["stm32f334"]} 20 | 21 | # board-specific features 22 | [dependencies.stm32f3xx-hal] 23 | version = "0.9.1" 24 | features = ["stm32f334x8"] 25 | 26 | [features] 27 | default = [] -------------------------------------------------------------------------------- /boards/firmware/stm32f334/updt_fw_blinky_red/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32f334/updt_fw_blinky_red/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | FLASH (rx) : ORIGIN = 0x800B900, LENGTH = 64K 3 | CCMRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 4K 4 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 12K 5 | } 6 | -------------------------------------------------------------------------------- /boards/firmware/stm32f334/updt_fw_blinky_red/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | 5 | extern crate cortex_m; 6 | extern crate cortex_m_rt; 7 | 8 | extern crate stm32f3xx_hal as mcu; 9 | use cortex_m::asm; 10 | use cortex_m_rt::entry; 11 | use crate::mcu::{ 12 | pac, 13 | prelude::*, 14 | }; 15 | use panic_probe as _; 16 | 17 | use rustBoot_hal::stm::stm32f334::FlashWriterEraser; 18 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 19 | 20 | 21 | #[entry] 22 | fn main() -> ! { 23 | let dp = pac::Peripherals::take().unwrap(); 24 | let mut rcc = dp.RCC.constrain(); 25 | let mut gpio = dp.GPIOA.split(&mut rcc.ahb); 26 | let mut led = gpio.pa5.into_push_pull_output(&mut gpio.moder, &mut gpio.otyper); 27 | 28 | let flash1 = dp.FLASH; 29 | let flash_writer = FlashWriterEraser { nvm: flash1 }; 30 | let updater = FlashUpdater::new(flash_writer); 31 | 32 | match updater.update_success() { 33 | Ok(_v) => {} 34 | Err(e) => panic!("couldnt trigger update: {}", e), 35 | } 36 | 37 | loop { 38 | led.toggle().unwrap(); 39 | asm::delay(4000_00); 40 | } 41 | 42 | } 43 | -------------------------------------------------------------------------------- /boards/firmware/stm32f411/boot_fw_blinky_green/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | runner = "probe-run --chip stm32f411vetx" # runner specific to nrf52840. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | # "-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/firmware/stm32f411/boot_fw_blinky_green/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f411_bootfw" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | [[bin]] 7 | name = "stm32f411_bootfw" 8 | bench = false 9 | doctest = false 10 | test = false 11 | 12 | [dependencies] 13 | # defmt = {version = "0.3.1", optional = true} 14 | # defmt-rtt = {version = "0.3.2", optional = true} 15 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 16 | cortex-m-rt = "0.7" 17 | rustBoot-hal ={path = "../../../hal",default-features = false,features = ["stm32f411"]} 18 | panic-probe = { version = "0.2.0" } 19 | rustBoot-update = {path = "../../../update", features = ["stm32f411"]} 20 | 21 | # board-specific features 22 | [dependencies.stm32f4xx-hal] 23 | version = "0.14.0" 24 | features = ["stm32f411"] 25 | 26 | [features] 27 | default = [] -------------------------------------------------------------------------------- /boards/firmware/stm32f411/boot_fw_blinky_green/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32f411/boot_fw_blinky_green/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* NOTE 1 K = 1 KiBi = 1024 bytes */ 4 | /* TODO Adjust these memory regions to match your device memory layout */ 5 | /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */ 6 | /* We'll need prepend a 256-byte rustBoot header. So add an offset - 0x100 */ 7 | FLASH (rx) : ORIGIN = 0x08020100, LENGTH = 128K 8 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K 9 | } 10 | 11 | /* This is where the call stack will be allocated. */ 12 | /* The stack is of the full descending type. */ 13 | /* You may want to use this variable to locate the call stack and static 14 | variables in different memory regions. Below is shown the default value */ 15 | /* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ 16 | 17 | /* You can use this symbol to customize the location of the .text section */ 18 | /* If omitted the .text section will be placed right after the .vector_table 19 | section */ 20 | /* This is required only on microcontrollers that store some configuration right 21 | after the vector table */ 22 | /* _stext = ORIGIN(FLASH) + 0x400; */ 23 | 24 | /* Example of putting non-initialized variables into custom RAM locations. */ 25 | /* This assumes you have defined a region RAM2 above, and in the Rust 26 | sources added the attribute `#[link_section = ".ram2bss"]` to the data 27 | you want to place there. */ 28 | /* Note that the section will not be zero-initialized by the runtime! */ 29 | /* SECTIONS { 30 | .ram2bss (NOLOAD) : ALIGN(4) { 31 | *(.ram2bss); 32 | . = ALIGN(4); 33 | } > RAM2 34 | } INSERT AFTER .bss; 35 | */ -------------------------------------------------------------------------------- /boards/firmware/stm32f411/boot_fw_blinky_green/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | use stm32f4xx_hal as mcu; 5 | 6 | // #[cfg(feature = "defmt")] 7 | // use defmt_rtt as _; // global logger 8 | 9 | use cortex_m_rt::entry; 10 | use mcu::pac; 11 | use mcu::prelude::*; 12 | 13 | use rustBoot_hal::stm::stm32f411::FlashWriterEraser; 14 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 15 | 16 | #[entry] 17 | fn main() -> ! { 18 | if let (Some(peri), Some(cortex_peri)) = ( 19 | pac::Peripherals::take(), 20 | cortex_m::peripheral::Peripherals::take(), 21 | ) { 22 | // GPIO Initialization 23 | let gpiod = peri.GPIOD.split(); 24 | let mut green_led = gpiod.pd12.into_push_pull_output(); 25 | 26 | // Set up the system clock. We want to run at 48MHz for this one. 27 | let rcc = peri.RCC.constrain(); 28 | let clocks = rcc.cfgr.sysclk(48.MHz()).freeze(); 29 | 30 | // Create a delay abstraction based on SysTick 31 | let mut delay = cortex_peri.SYST.delay(&clocks); 32 | 33 | let flash1 = peri.FLASH; 34 | 35 | let mut count = 0; 36 | while count < 3 { 37 | // On for 1s, off for 1s. 38 | green_led.set_high(); 39 | delay.delay_ms(1000_u32); 40 | green_led.set_low(); 41 | delay.delay_ms(1000_u32); 42 | count = count + 1; 43 | } 44 | 45 | let flash_writer = FlashWriterEraser { nvm: flash1 }; 46 | let updater = FlashUpdater::new(flash_writer); 47 | 48 | match updater.update_trigger() { 49 | Ok(_v) => {} 50 | Err(e) => panic!("couldnt trigger update: {}", e), 51 | } 52 | } 53 | //nvic_systemreset(); 54 | mcu::pac::SCB::sys_reset() 55 | } 56 | 57 | #[panic_handler] // panicking behavior 58 | fn panic(_: &core::panic::PanicInfo) -> ! { 59 | loop { 60 | cortex_m::asm::bkpt(); 61 | } 62 | } 63 | -------------------------------------------------------------------------------- /boards/firmware/stm32f411/updt_fw_blinky_red/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | runner = "probe-run --chip stm32f411vetx" # runner specific to nrf52840. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | # "-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/firmware/stm32f411/updt_fw_blinky_red/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f411_updtfw" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | [[bin]] 7 | name = "stm32f411_updtfw" 8 | bench = false 9 | doctest = false 10 | test = false 11 | 12 | [dependencies] 13 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 14 | cortex-m-rt = "0.7" 15 | rustBoot-hal ={path = "../../../hal",default-features = false,features = ["stm32f411"]} 16 | rustBoot-update = {path = "../../../update", features = ["stm32f411"]} 17 | 18 | # board-specific features 19 | [dependencies.stm32f4xx-hal] 20 | version = "0.14.0" 21 | features = ["rt", "stm32f411"] 22 | -------------------------------------------------------------------------------- /boards/firmware/stm32f411/updt_fw_blinky_red/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32f411/updt_fw_blinky_red/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* NOTE 1 K = 1 KiBi = 1024 bytes */ 4 | /* TODO Adjust these memory regions to match your device memory layout */ 5 | /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */ 6 | /* We'll need prepend a 256-byte rustBoot header. So add an offset - 0x100 */ 7 | FLASH (rx) : ORIGIN = 0x08020100, LENGTH = 128K 8 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K 9 | } 10 | 11 | /* This is where the call stack will be allocated. */ 12 | /* The stack is of the full descending type. */ 13 | /* You may want to use this variable to locate the call stack and static 14 | variables in different memory regions. Below is shown the default value */ 15 | /* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ 16 | 17 | /* You can use this symbol to customize the location of the .text section */ 18 | /* If omitted the .text section will be placed right after the .vector_table 19 | section */ 20 | /* This is required only on microcontrollers that store some configuration right 21 | after the vector table */ 22 | /* _stext = ORIGIN(FLASH) + 0x400; */ 23 | 24 | /* Example of putting non-initialized variables into custom RAM locations. */ 25 | /* This assumes you have defined a region RAM2 above, and in the Rust 26 | sources added the attribute `#[link_section = ".ram2bss"]` to the data 27 | you want to place there. */ 28 | /* Note that the section will not be zero-initialized by the runtime! */ 29 | /* SECTIONS { 30 | .ram2bss (NOLOAD) : ALIGN(4) { 31 | *(.ram2bss); 32 | . = ALIGN(4); 33 | } > RAM2 34 | } INSERT AFTER .bss; 35 | */ -------------------------------------------------------------------------------- /boards/firmware/stm32f446/boot_fw_blinky_green/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | runner = "probe-run --chip stm32f446retx" # runner specific to nrf52840. Replace this with probe-run option for your board. 10 | 11 | rustflags = [ 12 | "-C", "linker=flip-link", 13 | "-C", "link-arg=-Tlink.x", 14 | # "-C", "link-arg=-Tdefmt.x", 15 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 16 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 17 | "-C", "link-arg=--nmagic", 18 | ] -------------------------------------------------------------------------------- /boards/firmware/stm32f446/boot_fw_blinky_green/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f446_bootfw" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | [[bin]] 7 | name = "stm32f446_bootfw" 8 | bench = false 9 | doctest = false 10 | test = false 11 | 12 | [dependencies] 13 | # defmt = {version = "0.3.1", optional = true} 14 | # defmt-rtt = {version = "0.3.2", optional = true} 15 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 16 | cortex-m-rt = "0.7" 17 | rustBoot-hal ={path = "../../../hal",default-features = false,features = ["stm32f446"]} 18 | panic-probe = { version = "0.3.0" } 19 | rustBoot-update = {path = "../../../update", features = ["stm32f446"]} 20 | 21 | # board-specific features 22 | [dependencies.stm32f4xx-hal] 23 | version = "0.14.0" 24 | features = ["stm32f446"] 25 | 26 | [features] 27 | default = [] -------------------------------------------------------------------------------- /boards/firmware/stm32f446/boot_fw_blinky_green/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32f446/boot_fw_blinky_green/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* NOTE 1 K = 1 KiBi = 1024 bytes */ 4 | /* TODO Adjust these memory regions to match your device memory layout */ 5 | /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */ 6 | /* We'll need prepend a 256-byte rustBoot header. So add an offset - 0x100 */ 7 | FLASH (rx) : ORIGIN = 0x08020100, LENGTH = 128K 8 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K 9 | } 10 | 11 | /* This is where the call stack will be allocated. */ 12 | /* The stack is of the full descending type. */ 13 | /* You may want to use this variable to locate the call stack and static 14 | variables in different memory regions. Below is shown the default value */ 15 | /* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ 16 | 17 | /* You can use this symbol to customize the location of the .text section */ 18 | /* If omitted the .text section will be placed right after the .vector_table 19 | section */ 20 | /* This is required only on microcontrollers that store some configuration right 21 | after the vector table */ 22 | /* _stext = ORIGIN(FLASH) + 0x400; */ 23 | 24 | /* Example of putting non-initialized variables into custom RAM locations. */ 25 | /* This assumes you have defined a region RAM2 above, and in the Rust 26 | sources added the attribute `#[link_section = ".ram2bss"]` to the data 27 | you want to place there. */ 28 | /* Note that the section will not be zero-initialized by the runtime! */ 29 | /* SECTIONS { 30 | .ram2bss (NOLOAD) : ALIGN(4) { 31 | *(.ram2bss); 32 | . = ALIGN(4); 33 | } > RAM2 34 | } INSERT AFTER .bss; 35 | */ -------------------------------------------------------------------------------- /boards/firmware/stm32f446/boot_fw_blinky_green/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | use stm32f4xx_hal as mcu; 5 | 6 | // #[cfg(feature = "defmt")] 7 | // use defmt_rtt as _; // global logger 8 | 9 | use cortex_m_rt::entry; 10 | use mcu::pac; 11 | use mcu::prelude::*; 12 | 13 | use rustBoot_hal::stm::stm32f446::FlashWriterEraser; 14 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 15 | 16 | #[entry] 17 | fn main() -> ! { 18 | if let (Some(peri), Some(cortex_peri)) = ( 19 | pac::Peripherals::take(), 20 | cortex_m::peripheral::Peripherals::take(), 21 | ) { 22 | // GPIO Initialization 23 | let gpioa = peri.GPIOA.split(); 24 | let mut led = gpioa.pa5.into_push_pull_output(); 25 | 26 | // Set up the system clock. We want to run at 48MHz for this one. 27 | let rcc = peri.RCC.constrain(); 28 | let clocks = rcc.cfgr.sysclk(48.MHz()).freeze(); 29 | 30 | // Create a delay abstraction based on SysTick 31 | let mut delay = cortex_peri.SYST.delay(&clocks); 32 | 33 | let flash1 = peri.FLASH; 34 | 35 | let mut count = 0; 36 | while count < 3 { 37 | // On for 1s, off for 1s. 38 | led.set_high(); 39 | delay.delay_ms(1000_u32); 40 | led.set_low(); 41 | delay.delay_ms(1000_u32); 42 | count = count + 1; 43 | } 44 | 45 | let flash_writer = FlashWriterEraser { nvm: flash1 }; 46 | let updater = FlashUpdater::new(flash_writer); 47 | 48 | match updater.update_trigger() { 49 | Ok(_v) => {} 50 | Err(e) => panic!("couldnt trigger update: {}", e), 51 | } 52 | } 53 | //nvic_systemreset(); 54 | mcu::pac::SCB::sys_reset() 55 | } 56 | 57 | #[panic_handler] // panicking behavior 58 | fn panic(_: &core::panic::PanicInfo) -> ! { 59 | loop { 60 | cortex_m::asm::bkpt(); 61 | } 62 | } 63 | -------------------------------------------------------------------------------- /boards/firmware/stm32f446/updt_fw_blinky_red/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | runner = "probe-run --chip stm32f446retx" # runner specific to nrf52840. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | # "-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/firmware/stm32f446/updt_fw_blinky_red/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f446_updtfw" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | [[bin]] 7 | name = "stm32f446_updtfw" 8 | bench = false 9 | doctest = false 10 | test = false 11 | 12 | [dependencies] 13 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 14 | cortex-m-rt = "0.7" 15 | rustBoot-hal ={path = "../../../hal",default-features = false,features = ["stm32f446"]} 16 | panic-probe = { version = "0.3.0" } 17 | rustBoot-update = {path = "../../../update", features = ["stm32f446"]} 18 | 19 | # board-specific features 20 | [dependencies.stm32f4xx-hal] 21 | version = "0.14.0" 22 | features = ["rt", "stm32f446"] 23 | -------------------------------------------------------------------------------- /boards/firmware/stm32f446/updt_fw_blinky_red/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32f446/updt_fw_blinky_red/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* NOTE 1 K = 1 KiBi = 1024 bytes */ 4 | /* TODO Adjust these memory regions to match your device memory layout */ 5 | /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */ 6 | /* We'll need prepend a 256-byte rustBoot header. So add an offset - 0x100 */ 7 | FLASH (rx) : ORIGIN = 0x08020100, LENGTH = 128K 8 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K 9 | } 10 | 11 | /* This is where the call stack will be allocated. */ 12 | /* The stack is of the full descending type. */ 13 | /* You may want to use this variable to locate the call stack and static 14 | variables in different memory regions. Below is shown the default value */ 15 | /* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ 16 | 17 | /* You can use this symbol to customize the location of the .text section */ 18 | /* If omitted the .text section will be placed right after the .vector_table 19 | section */ 20 | /* This is required only on microcontrollers that store some configuration right 21 | after the vector table */ 22 | /* _stext = ORIGIN(FLASH) + 0x400; */ 23 | 24 | /* Example of putting non-initialized variables into custom RAM locations. */ 25 | /* This assumes you have defined a region RAM2 above, and in the Rust 26 | sources added the attribute `#[link_section = ".ram2bss"]` to the data 27 | you want to place there. */ 28 | /* Note that the section will not be zero-initialized by the runtime! */ 29 | /* SECTIONS { 30 | .ram2bss (NOLOAD) : ALIGN(4) { 31 | *(.ram2bss); 32 | . = ALIGN(4); 33 | } > RAM2 34 | } INSERT AFTER .bss; 35 | */ -------------------------------------------------------------------------------- /boards/firmware/stm32f446/updt_fw_blinky_red/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | use stm32f4xx_hal as mcu; 5 | 6 | #[cfg(feature = "defmt")] 7 | use defmt_rtt as _; // global logger 8 | 9 | use cortex_m_rt::entry; 10 | use mcu::{pac, prelude::*}; 11 | use panic_probe as _; 12 | 13 | use rustBoot_hal::stm::stm32f446::FlashWriterEraser; 14 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 15 | 16 | #[entry] 17 | fn main() -> ! { 18 | if let (Some(peri), Some(cortex_peri)) = ( 19 | pac::Peripherals::take(), 20 | cortex_m::peripheral::Peripherals::take(), 21 | ) { 22 | // GPIO Initialization 23 | let gpioa = peri.GPIOA.split(); 24 | let mut led = gpioa.pa5.into_push_pull_output(); 25 | 26 | // Set up the system clock. We want to run at 48MHz for this one. 27 | let rcc = peri.RCC.constrain(); 28 | let clocks = rcc.cfgr.sysclk(48.MHz()).freeze(); 29 | 30 | // Create a delay abstraction based on SysTick 31 | let mut delay = cortex_peri.SYST.delay(&clocks); 32 | 33 | let mut count = 0; 34 | while count < 3 { 35 | // On for 1s, off for 1s. 36 | led.set_high(); 37 | delay.delay_ms(1000_u32); 38 | led.set_low(); 39 | delay.delay_ms(1000_u32); 40 | count = count + 1; 41 | } 42 | 43 | let flash1 = peri.FLASH; 44 | let flash_writer = FlashWriterEraser { nvm: flash1 }; 45 | let updater = FlashUpdater::new(flash_writer); 46 | 47 | match updater.update_success() { 48 | Ok(_v) => {} 49 | Err(e) => panic!("couldnt trigger update: {}", e), 50 | } 51 | 52 | loop { 53 | led.set_high(); 54 | delay.delay_ms(1000_u32); 55 | led.set_low(); 56 | delay.delay_ms(1000_u32); 57 | } 58 | } 59 | 60 | loop {} 61 | } 62 | -------------------------------------------------------------------------------- /boards/firmware/stm32f469/boot_fw_blinky_green/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | runner = "probe-run --chip STM32F469NIHx" # runner specific to STM32F469NIHx. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | # "-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/firmware/stm32f469/boot_fw_blinky_green/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f469_bootfw" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | [[bin]] 7 | name = "stm32f469_bootfw" 8 | bench = false 9 | doctest = false 10 | test = false 11 | 12 | [dependencies] 13 | # defmt = {version = "0.3.1", optional = true} 14 | # defmt-rtt = {version = "0.3.2", optional = true} 15 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 16 | cortex-m-rt = "0.7" 17 | rustBoot-hal ={path = "../../../hal",default-features = false,features = ["stm32f469"]} 18 | panic-probe = { version = "0.2.0" } 19 | rustBoot-update = {path = "../../../update", features = ["stm32f469"]} 20 | 21 | # board-specific features 22 | [dependencies.stm32f4xx-hal] 23 | version = "0.14.0" 24 | features = ["stm32f469"] 25 | 26 | [features] 27 | default = [] 28 | -------------------------------------------------------------------------------- /boards/firmware/stm32f469/boot_fw_blinky_green/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32f469/boot_fw_blinky_green/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* NOTE 1 K = 1 KiBi = 1024 bytes */ 4 | /* TODO Adjust these memory regions to match your device memory layout */ 5 | /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */ 6 | /* We'll need prepend a 256-byte rustBoot header. So add an offset - 0x100 */ 7 | FLASH (rx) : ORIGIN = 0x08020100, LENGTH = 917248 8 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K 9 | } 10 | 11 | /* This is where the call stack will be allocated. */ 12 | /* The stack is of the full descending type. */ 13 | /* You may want to use this variable to locate the call stack and static 14 | variables in different memory regions. Below is shown the default value */ 15 | /* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ 16 | 17 | /* You can use this symbol to customize the location of the .text section */ 18 | /* If omitted the .text section will be placed right after the .vector_table 19 | section */ 20 | /* This is required only on microcontrollers that store some configuration right 21 | after the vector table */ 22 | /* _stext = ORIGIN(FLASH) + 0x400; */ 23 | 24 | /* Example of putting non-initialized variables into custom RAM locations. */ 25 | /* This assumes you have defined a region RAM2 above, and in the Rust 26 | sources added the attribute `#[link_section = ".ram2bss"]` to the data 27 | you want to place there. */ 28 | /* Note that the section will not be zero-initialized by the runtime! */ 29 | /* SECTIONS { 30 | .ram2bss (NOLOAD) : ALIGN(4) { 31 | *(.ram2bss); 32 | . = ALIGN(4); 33 | } > RAM2 34 | } INSERT AFTER .bss; 35 | */ 36 | -------------------------------------------------------------------------------- /boards/firmware/stm32f469/boot_fw_blinky_green/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | use stm32f4xx_hal as mcu; 5 | 6 | // #[cfg(feature = "defmt")] 7 | // use defmt_rtt as _; // global logger 8 | 9 | use cortex_m_rt::entry; 10 | use mcu::pac; 11 | use mcu::prelude::*; 12 | 13 | use rustBoot_hal::stm::stm32f469::FlashWriterEraser; 14 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 15 | 16 | #[entry] 17 | fn main() -> ! { 18 | if let (Some(peri), Some(cortex_peri)) = ( 19 | pac::Peripherals::take(), 20 | cortex_m::peripheral::Peripherals::take(), 21 | ) { 22 | // GPIO Initialization 23 | let gpiog = peri.GPIOG.split(); 24 | let mut green_led = gpiog.pg6.into_push_pull_output(); 25 | 26 | // Set up the system clock. We want to run at 48MHz for this one. 27 | let rcc = peri.RCC.constrain(); 28 | let clocks = rcc.cfgr.sysclk(48.MHz()).freeze(); 29 | 30 | // Create a delay abstraction based on SysTick 31 | let mut delay = cortex_peri.SYST.delay(&clocks); 32 | 33 | let flash1 = peri.FLASH; 34 | 35 | let mut count = 0; 36 | while count < 3 { 37 | // On for 1s, off for 1s. 38 | green_led.set_high(); 39 | delay.delay_ms(1000_u32); 40 | green_led.set_low(); 41 | delay.delay_ms(1000_u32); 42 | count = count + 1; 43 | } 44 | 45 | let flash_writer = FlashWriterEraser { nvm: flash1 }; 46 | let updater = FlashUpdater::new(flash_writer); 47 | 48 | match updater.update_trigger() { 49 | Ok(_v) => {} 50 | Err(e) => panic!("couldnt trigger update: {}", e), 51 | } 52 | } 53 | //nvic_systemreset(); 54 | mcu::pac::SCB::sys_reset() 55 | } 56 | 57 | #[panic_handler] // panicking behavior 58 | fn panic(_: &core::panic::PanicInfo) -> ! { 59 | loop { 60 | cortex_m::asm::bkpt(); 61 | } 62 | } 63 | -------------------------------------------------------------------------------- /boards/firmware/stm32f469/updt_fw_blinky_red/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | # ============================================================================= 2 | # Build configuration options for Cortex-M 3 | # ============================================================================= 4 | 5 | [build] 6 | target = "thumbv7em-none-eabihf" 7 | 8 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 9 | runner = "probe-run --chip STM32F469NIHx" # runner specific to STM32F469NIHx. Replace this with probe-run option for your board. 10 | rustflags = [ 11 | "-C", "linker=flip-link", 12 | "-C", "link-arg=-Tlink.x", 13 | # "-C", "link-arg=-Tdefmt.x", 14 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 15 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 16 | "-C", "link-arg=--nmagic", 17 | ] -------------------------------------------------------------------------------- /boards/firmware/stm32f469/updt_fw_blinky_red/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f469_updtfw" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | [[bin]] 7 | name = "stm32f469_updtfw" 8 | bench = false 9 | doctest = false 10 | test = false 11 | 12 | [dependencies] 13 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 14 | cortex-m-rt = "0.7" 15 | rustBoot-hal ={path = "../../../hal",default-features = false,features = ["stm32f469"]} 16 | rustBoot-update = {path = "../../../update", features = ["stm32f469"]} 17 | 18 | # board-specific features 19 | [dependencies.stm32f4xx-hal] 20 | version = "0.14.0" 21 | features = ["rt", "stm32f469"] 22 | -------------------------------------------------------------------------------- /boards/firmware/stm32f469/updt_fw_blinky_red/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32f469/updt_fw_blinky_red/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* NOTE 1 K = 1 KiBi = 1024 bytes */ 4 | /* TODO Adjust these memory regions to match your device memory layout */ 5 | /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */ 6 | /* We'll need prepend a 256-byte rustBoot header. So add an offset - 0x100 */ 7 | FLASH (rx) : ORIGIN = 0x08020100, LENGTH = 917248 8 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K 9 | } 10 | 11 | /* This is where the call stack will be allocated. */ 12 | /* The stack is of the full descending type. */ 13 | /* You may want to use this variable to locate the call stack and static 14 | variables in different memory regions. Below is shown the default value */ 15 | /* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */ 16 | 17 | /* You can use this symbol to customize the location of the .text section */ 18 | /* If omitted the .text section will be placed right after the .vector_table 19 | section */ 20 | /* This is required only on microcontrollers that store some configuration right 21 | after the vector table */ 22 | /* _stext = ORIGIN(FLASH) + 0x400; */ 23 | 24 | /* Example of putting non-initialized variables into custom RAM locations. */ 25 | /* This assumes you have defined a region RAM2 above, and in the Rust 26 | sources added the attribute `#[link_section = ".ram2bss"]` to the data 27 | you want to place there. */ 28 | /* Note that the section will not be zero-initialized by the runtime! */ 29 | /* SECTIONS { 30 | .ram2bss (NOLOAD) : ALIGN(4) { 31 | *(.ram2bss); 32 | . = ALIGN(4); 33 | } > RAM2 34 | } INSERT AFTER .bss; 35 | */ 36 | -------------------------------------------------------------------------------- /boards/firmware/stm32f746/boot_fw_blinky_green/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | [build] 2 | target = "thumbv7em-none-eabihf" 3 | 4 | 5 | [target.thumbv7em-none-eabihf] 6 | runner = "arm-none-eabi-gdb -q -tui -x openocd.gdb" 7 | 8 | 9 | rustflags = [ 10 | "-C", "linker=flip-link", 11 | "-C", "link-arg=-Tlink.x", 12 | "-C", "link-arg=-Tdefmt.x", 13 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 14 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 15 | "-C", "link-arg=--nmagic", 16 | ] 17 | 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32f746/boot_fw_blinky_green/.gitignore: -------------------------------------------------------------------------------- 1 | /target 2 | -------------------------------------------------------------------------------- /boards/firmware/stm32f746/boot_fw_blinky_green/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f746_bootfw" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [[bin]] 9 | name = "stm32f746_bootfw" 10 | bench = false 11 | doctest = false 12 | test = false 13 | 14 | [dependencies] 15 | cortex-m-rt = "0.7" 16 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 17 | # panic-halt = "0.2.0" 18 | rustBoot-hal ={path = "../../../hal",default-features = false,features = ["stm32f746"]} 19 | rustBoot-update = {path = "../../../update", features = ["stm32f746"]} 20 | defmt = {version = "0.3.1", optional = true} 21 | defmt-rtt = {version = "0.3.2", optional = true} 22 | 23 | # board-specific features 24 | [dependencies.stm32f7xx-hal] 25 | version = "0.7.0" 26 | features = ["stm32f746"] 27 | 28 | [features] 29 | default = ["defmt", "defmt-rtt"] 30 | -------------------------------------------------------------------------------- /boards/firmware/stm32f746/boot_fw_blinky_green/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32f746/boot_fw_blinky_green/memory.x: -------------------------------------------------------------------------------- 1 | /* For STM32F7{45,46,56} devices */ 2 | MEMORY 3 | { 4 | /* NOTE K = KiBi = 1024 bytes */ 5 | FLASH : ORIGIN = 0x08040100, LENGTH = 1M 6 | RAM : ORIGIN = 0x20000000, LENGTH = 128K 7 | } 8 | 9 | /* This is where the call stack will be allocated. */ 10 | /* The stack is of the full descending type. */ 11 | /* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ 12 | /*_stack_start = ORIGIN(RAM) + LENGTH(RAM); */ -------------------------------------------------------------------------------- /boards/firmware/stm32f746/boot_fw_blinky_green/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | #[cfg(feature = "defmt")] 5 | use defmt_rtt as _; // global logger 6 | 7 | use crate::mcu::{pac, prelude::*}; 8 | use cortex_m_rt::entry; 9 | use stm32f7xx_hal as mcu; 10 | 11 | use rustBoot_hal::stm::stm32f746::FlashWriterEraser; 12 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 13 | #[entry] 14 | fn main() -> ! { 15 | let _p = pac::Peripherals::take().unwrap(); 16 | 17 | let gipo = _p.GPIOB.split(); 18 | let mut led1 = gipo.pb0.into_push_pull_output(); 19 | let mut count = 0; 20 | while count < 6 { 21 | led1.toggle(); 22 | cortex_m::asm::delay(8000000); 23 | count = count + 1; 24 | } 25 | 26 | let flash1 = _p.FLASH; 27 | let flash_writer = FlashWriterEraser { nvm: flash1 }; 28 | let updater = FlashUpdater::new(flash_writer); 29 | 30 | match updater.update_trigger() { 31 | Ok(_v) => {} 32 | Err(e) => panic!("couldnt trigger update: {}", e), 33 | } 34 | 35 | stm32f7xx_hal::pac::SCB::sys_reset() 36 | } 37 | 38 | #[panic_handler] // panicking behavior 39 | fn panic(_: &core::panic::PanicInfo) -> ! { 40 | loop { 41 | cortex_m::asm::bkpt(); 42 | } 43 | } 44 | -------------------------------------------------------------------------------- /boards/firmware/stm32f746/updt_fw_blinky_red/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | [build] 2 | target = "thumbv7em-none-eabihf" 3 | 4 | 5 | [target.thumbv7em-none-eabihf] 6 | runner = "arm-none-eabi-gdb -q -tui -x openocd.gdb" 7 | 8 | 9 | rustflags = [ 10 | "-C", "linker=flip-link", 11 | "-C", "link-arg=-Tlink.x", 12 | "-C", "link-arg=-Tdefmt.x", 13 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 14 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 15 | "-C", "link-arg=--nmagic", 16 | ] 17 | 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32f746/updt_fw_blinky_red/.gitignore: -------------------------------------------------------------------------------- 1 | /target 2 | -------------------------------------------------------------------------------- /boards/firmware/stm32f746/updt_fw_blinky_red/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32f746_updtfw" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | 9 | [[bin]] 10 | name = "stm32f746_updtfw" 11 | bench = false 12 | doctest = false 13 | test = false 14 | 15 | [dependencies] 16 | cortex-m-rt = "0.7" 17 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 18 | rustBoot-hal ={path = "../../../hal",default-features = false,features = ["stm32f746"]} 19 | rustBoot-update = {path = "../../../update", features = ["stm32f746"]} 20 | defmt = {version = "0.3.2", optional = true} 21 | defmt-rtt = {version = "0.4.0", optional = true} 22 | 23 | # board-specific features 24 | [dependencies.stm32f7xx-hal] 25 | version = "0.7.0" 26 | features = ["stm32f746"] 27 | 28 | [features] 29 | default = ["defmt", "defmt-rtt"] 30 | -------------------------------------------------------------------------------- /boards/firmware/stm32f746/updt_fw_blinky_red/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32f746/updt_fw_blinky_red/memory.x: -------------------------------------------------------------------------------- 1 | /* For STM32F7{45,46,56} devices */ 2 | MEMORY 3 | { 4 | /* NOTE K = KiBi = 1024 bytes */ 5 | FLASH : ORIGIN = 0x08040100, LENGTH = 1M 6 | RAM : ORIGIN = 0x20000000, LENGTH = 128K 7 | } 8 | 9 | /* This is where the call stack will be allocated. */ 10 | /* The stack is of the full descending type. */ 11 | /* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ 12 | /*_stack_start = ORIGIN(RAM) + LENGTH(RAM); */ -------------------------------------------------------------------------------- /boards/firmware/stm32f746/updt_fw_blinky_red/src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | #[cfg(feature = "defmt")] 5 | use defmt_rtt as _; // global logger 6 | 7 | use crate::mcu::{pac, prelude::*}; 8 | use cortex_m_rt::entry; 9 | use stm32f7xx_hal as mcu; 10 | 11 | use rustBoot_hal::stm::stm32f746::FlashWriterEraser; 12 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 13 | 14 | #[entry] 15 | fn main() -> ! { 16 | let _p = pac::Peripherals::take().unwrap(); 17 | 18 | let gipo = _p.GPIOB.split(); 19 | let mut led1 = gipo.pb14.into_push_pull_output(); 20 | 21 | let flash1 = _p.FLASH; 22 | let flash_writer = FlashWriterEraser { nvm: flash1 }; 23 | let updater = FlashUpdater::new(flash_writer); 24 | 25 | match updater.update_success() { 26 | Ok(_v) => {} 27 | Err(e) => panic!("couldnt trigger update: {}", e), 28 | } 29 | 30 | loop { 31 | led1.toggle(); 32 | cortex_m::asm::delay(8000000); 33 | } 34 | } 35 | 36 | #[panic_handler] // panicking behavior 37 | fn panic(_: &core::panic::PanicInfo) -> ! { 38 | loop { 39 | cortex_m::asm::bkpt(); 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /boards/firmware/stm32h723/boot_fw_blinky_green/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 2 | runner = "probe-run --chip STM32H723ZGIx" 3 | 4 | rustflags = [ 5 | "-C", "linker=flip-link", 6 | "-C", "link-arg=-Tlink.x", 7 | "-C", "link-arg=-Tdefmt.x", 8 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 9 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 10 | "-C", "link-arg=--nmagic", 11 | ] 12 | 13 | [build] 14 | # (`thumbv6m-*` is compatible with all ARM Cortex-M chips but using the right 15 | # target improves performance) 16 | # target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ 17 | # target = "thumbv7m-none-eabi" # Cortex-M3 18 | # target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) 19 | target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) -------------------------------------------------------------------------------- /boards/firmware/stm32h723/boot_fw_blinky_green/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32h723_bootfw" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [[bin]] 9 | name = "stm32h723_bootfw" 10 | bench = false 11 | doctest = false 12 | test = false 13 | 14 | [dependencies] 15 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 16 | cortex-m-rt = "0.7" 17 | panic-probe = "0.3.0" 18 | defmt = {version = "0.3.2", optional = true} 19 | defmt-rtt = {version = "0.4.0", optional = true} 20 | rustBoot-hal ={path = "../../../hal",default-features = false,features = ["stm32h723"]} 21 | rustBoot-update = {path = "../../../update", features = ["stm32h723"]} 22 | # board-specific features 23 | stm32h7xx-hal = {version = "0.12.2", features = ["stm32h735","rt"]} 24 | 25 | [features] 26 | default = ["defmt", "defmt-rtt"] 27 | -------------------------------------------------------------------------------- /boards/firmware/stm32h723/boot_fw_blinky_green/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32h723/boot_fw_blinky_green/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* FLASH and RAM are mandatory memory regions */ 4 | 5 | /* STM32H742xI/743xI/753xI */ 6 | /* STM32H745xI/747xI/755xI/757xI */ 7 | /* STM32H7A3xI/7B3xI */ 8 | FLASH : ORIGIN = 0x08020100, LENGTH = 128K 9 | 10 | /* STM32H742xG/743xG */ 11 | /* STM32H745xG/STM32H747xG */ 12 | /* STM32H7A3xG */ 13 | /* FLASH : ORIGIN = 0x08000000, LENGTH = 512K */ 14 | /* FLASH1 : ORIGIN = 0x08100000, LENGTH = 512K */ 15 | 16 | /* STM32H750xB */ 17 | /* STM32H7B0 */ 18 | /* FLASH : ORIGIN = 0x08000000, LENGTH = 1M */ 19 | 20 | /* DTCM */ 21 | RAM : ORIGIN = 0x20000000, LENGTH = 128K 22 | } 23 | -------------------------------------------------------------------------------- /boards/firmware/stm32h723/boot_fw_blinky_green/src/main.rs: -------------------------------------------------------------------------------- 1 | // #![deny(warnings)] 2 | #![no_main] 3 | #![no_std] 4 | 5 | #[cfg(feature = "defmt")] 6 | use defmt_rtt as _; // global logger 7 | use panic_probe as _; // global logger 8 | 9 | use stm32h7xx_hal::{pac, prelude::*}; 10 | 11 | use rustBoot_hal::stm::stm32h723::FlashWriterEraser; 12 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 13 | 14 | use cortex_m_rt::entry; 15 | 16 | #[entry] 17 | fn main() -> ! { 18 | let cp = cortex_m::Peripherals::take().unwrap(); 19 | let dp = pac::Peripherals::take().unwrap(); 20 | 21 | // Constrain and Freeze power 22 | let pwr = dp.PWR.constrain(); 23 | let pwrcfg = pwr.freeze(); 24 | 25 | // Constrain and Freeze clock 26 | let rcc = dp.RCC.constrain(); 27 | let ccdr = rcc.sys_ck(100.MHz()).freeze(pwrcfg, &dp.SYSCFG); 28 | 29 | //GPIO init 30 | let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB); 31 | 32 | // Configure PE1 as output. 33 | let mut led1 = gpiob.pb0.into_push_pull_output(); 34 | 35 | // Get the delay provider. 36 | let mut delay = cp.SYST.delay(ccdr.clocks); 37 | 38 | let flsh = dp.FLASH; 39 | 40 | let mut count = 0; 41 | 42 | while count < 4 { 43 | led1.set_high(); 44 | delay.delay_ms(500_u16); 45 | led1.set_low(); 46 | delay.delay_ms(500_u16); 47 | count = count + 1; 48 | } 49 | 50 | let flash_writer = FlashWriterEraser { nvm: flsh }; 51 | let updater = FlashUpdater::new(flash_writer); 52 | 53 | match updater.update_trigger() { 54 | Ok(_v) => {} 55 | Err(e) => panic!("couldnt trigger update: {}", e), 56 | } 57 | 58 | stm32h7xx_hal::pac::SCB::sys_reset(); 59 | } 60 | -------------------------------------------------------------------------------- /boards/firmware/stm32h723/updt_fw_blinky_red/.cargo/config.toml: -------------------------------------------------------------------------------- 1 | [target.'cfg(all(target_arch = "arm", target_os = "none"))'] 2 | runner = "probe-run --chip STM32H723ZGIx" 3 | 4 | rustflags = [ 5 | "-C", "linker=flip-link", 6 | "-C", "link-arg=-Tlink.x", 7 | "-C", "link-arg=-Tdefmt.x", 8 | # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x 9 | # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 10 | "-C", "link-arg=--nmagic", 11 | ] 12 | 13 | [build] 14 | # (`thumbv6m-*` is compatible with all ARM Cortex-M chips but using the right 15 | # target improves performance) 16 | # target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ 17 | # target = "thumbv7m-none-eabi" # Cortex-M3 18 | # target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) 19 | target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) -------------------------------------------------------------------------------- /boards/firmware/stm32h723/updt_fw_blinky_red/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32h723_updtfw" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [[bin]] 9 | name = "stm32h723_updtfw" 10 | bench = false 11 | doctest = false 12 | test = false 13 | 14 | [dependencies] 15 | cortex-m = { version = "0.7", features = ["critical-section-single-core"] } 16 | cortex-m-rt = "0.7" 17 | panic-probe = "0.3.0" 18 | defmt = {version = "0.3.2", optional = true} 19 | defmt-rtt = {version = "0.4.0", optional = true} 20 | rustBoot-hal ={path = "../../../hal", default-features = false, features = ["stm32h723"]} 21 | rustBoot-update = {path = "../../../update", features = ["stm32h723"]} 22 | # board-specific features 23 | stm32h7xx-hal = {version = "0.12.2", features = ["stm32h735", "rt"]} 24 | 25 | [features] 26 | default = ["defmt", "defmt-rtt"] 27 | -------------------------------------------------------------------------------- /boards/firmware/stm32h723/updt_fw_blinky_red/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs::File; 3 | use std::io::Write; 4 | use std::path::PathBuf; 5 | 6 | fn main() { 7 | // Put the linker script somewhere the linker can find it 8 | let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); 9 | File::create(out.join("memory.x")) 10 | .unwrap() 11 | .write_all(include_bytes!("memory.x")) 12 | .unwrap(); 13 | println!("cargo:rustc-link-search={}", out.display()); 14 | 15 | println!("cargo:rerun-if-changed=build.rs"); 16 | println!("cargo:rerun-if-changed=memory.x"); 17 | } 18 | -------------------------------------------------------------------------------- /boards/firmware/stm32h723/updt_fw_blinky_red/memory.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | /* FLASH and RAM are mandatory memory regions */ 4 | 5 | /* STM32H742xI/743xI/753xI */ 6 | /* STM32H745xI/747xI/755xI/757xI */ 7 | /* STM32H7A3xI/7B3xI */ 8 | FLASH : ORIGIN = 0x08020100, LENGTH = 128K 9 | 10 | /* STM32H742xG/743xG */ 11 | /* STM32H745xG/STM32H747xG */ 12 | /* STM32H7A3xG */ 13 | /* FLASH : ORIGIN = 0x08000000, LENGTH = 512K */ 14 | /* FLASH1 : ORIGIN = 0x08100000, LENGTH = 512K */ 15 | 16 | /* STM32H750xB */ 17 | /* STM32H7B0 */ 18 | /* FLASH : ORIGIN = 0x08000000, LENGTH = 1M */ 19 | 20 | /* DTCM */ 21 | RAM : ORIGIN = 0x20000000, LENGTH = 128K 22 | } 23 | -------------------------------------------------------------------------------- /boards/firmware/stm32h723/updt_fw_blinky_red/src/main.rs: -------------------------------------------------------------------------------- 1 | // #![deny(warnings)] 2 | #![no_main] 3 | #![no_std] 4 | 5 | #[cfg(feature = "defmt")] 6 | use defmt_rtt as _; // global logger 7 | use panic_probe as _; 8 | 9 | use stm32h7xx_hal::{pac, prelude::*}; 10 | 11 | use rustBoot_hal::stm::stm32h723::FlashWriterEraser; 12 | use rustBoot_update::update::{update_flash::FlashUpdater, UpdateInterface}; 13 | 14 | use cortex_m_rt::entry; 15 | 16 | #[entry] 17 | fn main() -> ! { 18 | let cp = cortex_m::Peripherals::take().unwrap(); 19 | let dp = pac::Peripherals::take().unwrap(); 20 | 21 | // Constrain and Freeze power 22 | let pwr = dp.PWR.constrain(); 23 | let pwrcfg = pwr.freeze(); 24 | 25 | // Constrain and Freeze clock 26 | let rcc = dp.RCC.constrain(); 27 | let ccdr = rcc.sys_ck(100.MHz()).freeze(pwrcfg, &dp.SYSCFG); 28 | 29 | //GPIO init 30 | let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB); 31 | 32 | // Configure PE1 as output. 33 | let mut led2 = gpiob.pb14.into_push_pull_output(); 34 | 35 | // Get the delay provider. 36 | let mut delay = cp.SYST.delay(ccdr.clocks); 37 | 38 | let flsh = dp.FLASH; 39 | 40 | let mut count = 0; 41 | 42 | while count < 4 { 43 | led2.set_high(); 44 | delay.delay_ms(500_u16); 45 | led2.set_low(); 46 | delay.delay_ms(500_u16); 47 | count = count + 1; 48 | } 49 | 50 | let flash_writer = FlashWriterEraser { nvm: flsh }; 51 | let updater = FlashUpdater::new(flash_writer); 52 | 53 | match updater.update_success() { 54 | Ok(_v) => {} 55 | Err(e) => panic!("couldnt trigger update: {}", e), 56 | } 57 | 58 | loop { 59 | led2.toggle(); 60 | delay.delay_ms(500_u16); 61 | } 62 | } 63 | -------------------------------------------------------------------------------- /boards/hal/src/nrf/mod.rs: -------------------------------------------------------------------------------- 1 | #[cfg(feature = "nrf52840")] 2 | pub mod nrf52840; 3 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "aarch64-cpu" 3 | version = "9.3.1" 4 | authors = ["Andre Richter "] 5 | description = "Low level access to processors using the AArch64 execution state" 6 | homepage = "https://github.com/rust-embedded/aarch64-cpu" 7 | repository = "https://github.com/rust-embedded/aarch64-cpu" 8 | readme = "README.md" 9 | keywords = ["arm", "aarch64", "cpu", "register"] 10 | categories = ["embedded", "hardware-support", "no-std"] 11 | license = "MIT/Apache-2.0" 12 | edition = "2018" 13 | exclude = [ 14 | ".github", 15 | ".gitignore", 16 | ".rustfmt.toml", 17 | ".vscode", 18 | ".editorconfig", 19 | "Makefile" 20 | ] 21 | 22 | [dependencies] 23 | tock-registers = { version = "0.8.x", default-features = false } # Use it as interface-only library. 24 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/LICENSE-MIT: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (C) 2018-2023 by the respective authors 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/actlr_el1.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Valentin B. 7 | 8 | //! Auxiliary Control Register - EL1 9 | //! 10 | //! Provides implementation-defined configuration and control options for execution 11 | //! at EL1 and EL0. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "ACTLR_EL1", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "ACTLR_EL1", "x"); 29 | } 30 | 31 | pub const ACTLR_EL1: Reg = Reg; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/actlr_el2.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Valentin B. 7 | 8 | //! Auxiliary Control Register - EL2 9 | //! 10 | //! Provides implementation-defined configuration and control options for execution 11 | //! at EL2. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "ACTLR_EL2", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "ACTLR_EL2", "x"); 29 | } 30 | 31 | pub const ACTLR_EL2: Reg = Reg; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/actlr_el3.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Valentin B. 7 | 8 | //! Auxiliary Control Register - EL3 9 | //! 10 | //! Provides implementation-defined configuration and control options for execution 11 | //! at EL3. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "ACTLR_EL3", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "ACTLR_EL3", "x"); 29 | } 30 | 31 | pub const ACTLR_EL3: Reg = Reg; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/cntfrq_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Counter-timer Frequency register - EL0 9 | //! 10 | //! This register is provided so that software can discover the frequency of the system counter. It 11 | //! must be programmed with this value as part of system initialization. The value of the register 12 | //! is not interpreted by hardware. 13 | 14 | use tock_registers::interfaces::{Readable, Writeable}; 15 | 16 | pub struct Reg; 17 | 18 | impl Readable for Reg { 19 | type T = u64; 20 | type R = (); 21 | 22 | sys_coproc_read_raw!(u64, "CNTFRQ_EL0", "x"); 23 | } 24 | 25 | impl Writeable for Reg { 26 | type T = u64; 27 | type R = (); 28 | 29 | sys_coproc_write_raw!(u64, "CNTFRQ_EL0", "x"); 30 | } 31 | pub const CNTFRQ_EL0: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/cntp_cval_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Counter-timer Physical Timer CompareValue register - EL0 9 | //! 10 | //! Holds the compare value for the EL1 physical timer. 11 | //! 12 | //! When CNTP_CTL_EL0.ENABLE is 1, the timer condition is met when (CNTPCT_EL0 - CompareValue) is 13 | //! greater than or equal to zero. This means that CompareValue acts like a 64-bit upcounter timer. 14 | //! 15 | //! When the timer condition is met: 16 | //! - CNTP_CTL_EL0.ISTATUS is set to 1. 17 | //! - If CNTP_CTL_EL0.IMASK is 0, an interrupt is generated. 18 | //! 19 | //! When CNTP_CTL_EL0.ENABLE is 0, the timer condition is not met, but CNTPCT_EL0 continues to 20 | //! count. 21 | //! 22 | //! If the Generic counter is implemented at a size less than 64 bits, then this field is permitted 23 | //! to be implemented at the same width as the counter, and the upper bits are RES0. 24 | //! 25 | //! The value of this field is treated as zero-extended in all counter calculations. 26 | //! 27 | //! The reset behaviour of this field is: 28 | //! - On a Warm reset, this field resets to an architecturally UNKNOWN value. 29 | 30 | use tock_registers::interfaces::{Readable, Writeable}; 31 | 32 | pub struct Reg; 33 | 34 | impl Readable for Reg { 35 | type T = u64; 36 | type R = (); 37 | 38 | sys_coproc_read_raw!(u64, "CNTP_CVAL_EL0", "x"); 39 | } 40 | 41 | impl Writeable for Reg { 42 | type T = u64; 43 | type R = (); 44 | 45 | sys_coproc_write_raw!(u64, "CNTP_CVAL_EL0", "x"); 46 | } 47 | 48 | pub const CNTP_CVAL_EL0: Reg = Reg {}; 49 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/cntp_tval_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Counter-timer Physical Timer TimerValue register - EL0 9 | //! 10 | //! Holds the timer value for the EL1 physical timer. 11 | 12 | use tock_registers::interfaces::{Readable, Writeable}; 13 | 14 | pub struct Reg; 15 | 16 | impl Readable for Reg { 17 | type T = u64; 18 | type R = (); 19 | 20 | sys_coproc_read_raw!(u64, "CNTP_TVAL_EL0", "x"); 21 | } 22 | 23 | impl Writeable for Reg { 24 | type T = u64; 25 | type R = (); 26 | 27 | sys_coproc_write_raw!(u64, "CNTP_TVAL_EL0", "x"); 28 | } 29 | 30 | pub const CNTP_TVAL_EL0: Reg = Reg {}; 31 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/cntpct_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Counter-timer Physical Count register - EL0 9 | //! 10 | //! Holds the 64-bit physical count value. 11 | 12 | use tock_registers::interfaces::Readable; 13 | 14 | pub struct Reg; 15 | 16 | impl Readable for Reg { 17 | type T = u64; 18 | type R = (); 19 | 20 | sys_coproc_read_raw!(u64, "CNTPCT_EL0", "x"); 21 | } 22 | 23 | pub const CNTPCT_EL0: Reg = Reg {}; 24 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/cntv_cval_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | // - Javier Alvarez 8 | 9 | //! Counter-timer Virtual Timer CompareValue register - EL0 10 | //! 11 | //! Holds the compare value for the virtual timer. 12 | //! 13 | //! When CNTV_CTL_EL0.ENABLE is 1, the timer condition is met when (CNTVCT_EL0 - CompareValue) is 14 | //! greater than or equal to zero. This means that CompareValue acts like a 64-bit upcounter timer. 15 | //! 16 | //! When the timer condition is met: 17 | //! - CNTV_CTL_EL0.ISTATUS is set to 1. 18 | //! - If CNTV_CTL_EL0.IMASK is 0, an interrupt is generated. 19 | //! 20 | //! When CNTV_CTL_EL0.ENABLE is 0, the timer condition is not met, but CNTVCT_EL0 continues to 21 | //! count. 22 | //! 23 | //! If the Generic counter is implemented at a size less than 64 bits, then this field is permitted 24 | //! to be implemented at the same width as the counter, and the upper bits are RES0. 25 | //! 26 | //! The value of this field is treated as zero-extended in all counter calculations. 27 | //! 28 | //! The reset behaviour of this field is: 29 | //! - On a Warm reset, this field resets to an architecturally UNKNOWN value. 30 | 31 | use tock_registers::interfaces::{Readable, Writeable}; 32 | 33 | pub struct Reg; 34 | 35 | impl Readable for Reg { 36 | type T = u64; 37 | type R = (); 38 | 39 | sys_coproc_read_raw!(u64, "CNTV_CVAL_EL0", "x"); 40 | } 41 | 42 | impl Writeable for Reg { 43 | type T = u64; 44 | type R = (); 45 | 46 | sys_coproc_write_raw!(u64, "CNTV_CVAL_EL0", "x"); 47 | } 48 | 49 | pub const CNTV_CVAL_EL0: Reg = Reg {}; 50 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/cntv_tval_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | // - Gregor Reitzenstein 8 | 9 | //! Counter-timer Virtual Timer TimerValue register - EL0 10 | //! 11 | //! Holds the timer value for the EL1 virtual timer. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "CNTV_TVAL_EL0", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "CNTV_TVAL_EL0", "x"); 29 | } 30 | 31 | pub const CNTV_TVAL_EL0: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/cntvct_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | // - Gregor Reitzenstein 8 | 9 | //! Counter-timer Virtual Count register - EL0 10 | //! 11 | //! Holds the 64-bit virtual count value. The virtual count value is equal to the physical count 12 | //! value in `CNTPCT_EL0` minus the virtual offset visible in `CNTVOFF_EL2` 13 | 14 | use tock_registers::interfaces::Readable; 15 | 16 | pub struct Reg; 17 | 18 | impl Readable for Reg { 19 | type T = u64; 20 | type R = (); 21 | 22 | sys_coproc_read_raw!(u64, "CNTVCT_EL0", "x"); 23 | } 24 | 25 | pub const CNTVCT_EL0: Reg = Reg {}; 26 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/cntvoff_el2.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Counter-timer Virtual Offset register - EL2 9 | //! 10 | //! Holds the 64-bit virtual offset. This is the offset between the physical count value visible in 11 | //! CNTPCT_EL0 and the virtual count value visible in CNTVCT_EL0. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "CNTVOFF_EL2", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "CNTVOFF_EL2", "x"); 29 | } 30 | 31 | pub const CNTVOFF_EL2: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/currentel.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Current Exception Level 9 | //! 10 | //! Holds the current Exception level. 11 | 12 | use tock_registers::{interfaces::Readable, register_bitfields}; 13 | 14 | register_bitfields! {u64, 15 | pub CurrentEL [ 16 | /// Current Exception level. Possible values of this field are: 17 | /// 18 | /// 00 EL0 19 | /// 01 EL1 20 | /// 10 EL2 21 | /// 11 EL3 22 | /// 23 | /// When the HCR_EL2.NV bit is 1, Non-secure EL1 read accesses to the CurrentEL register 24 | /// return the value of 0x2 in this field. 25 | /// 26 | /// This field resets to a value that is architecturally UNKNOWN. 27 | EL OFFSET(2) NUMBITS(2) [ 28 | EL0 = 0, 29 | EL1 = 1, 30 | EL2 = 2, 31 | EL3 = 3 32 | ] 33 | ] 34 | } 35 | 36 | pub struct Reg; 37 | 38 | impl Readable for Reg { 39 | type T = u64; 40 | type R = CurrentEL::Register; 41 | 42 | sys_coproc_read_raw!(u64, "CurrentEL", "x"); 43 | } 44 | 45 | #[allow(non_upper_case_globals)] 46 | pub const CurrentEL: Reg = Reg {}; 47 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/dbgdtr_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2020-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Chris Brown 7 | 8 | //! Debug Data Transfer Register, half-duplex 9 | //! 10 | //! Transfers 64 bits of data between the PE and an external debugger. Can transfer both ways using 11 | //! only a single register. 12 | 13 | use tock_registers::{ 14 | interfaces::{Readable, Writeable}, 15 | register_bitfields, 16 | }; 17 | 18 | register_bitfields! {u64, 19 | pub DBGDTR_EL0 [ 20 | /// Writes to this register set DTRRX to the value in this field and do not change RXfull. 21 | /// 22 | /// Reads of this register: 23 | /// 24 | /// - If RXfull is set to 1, return the last value written to DTRTX. 25 | /// - If RXfull is set to 0, return an UNKNOWN value. 26 | /// 27 | /// After the read, RXfull is cleared to 0. 28 | HighWord OFFSET(32) NUMBITS(32) [], 29 | 30 | /// Writes to this register set DTRTX to the value in this field and set TXfull to 1. 31 | /// 32 | /// Reads of this register: 33 | /// 34 | /// - If RXfull is set to 1, return the last value written to DTRRX. 35 | /// - If RXfull is set to 0, return an UNKNOWN value. 36 | /// 37 | /// After the read, RXfull is cleared to 0. 38 | LowWord OFFSET(0) NUMBITS(32) [] 39 | ] 40 | } 41 | 42 | pub struct Reg; 43 | 44 | impl Readable for Reg { 45 | type T = u64; 46 | type R = DBGDTR_EL0::Register; 47 | 48 | sys_coproc_read_raw!(u64, "DBGDTR_EL0", "x"); 49 | } 50 | 51 | impl Writeable for Reg { 52 | type T = u64; 53 | type R = DBGDTR_EL0::Register; 54 | 55 | sys_coproc_write_raw!(u64, "DBGDTR_EL0", "x"); 56 | } 57 | 58 | pub const DBGDTR_EL0: Reg = Reg {}; 59 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/dbgdtrrx_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2020-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Chris Brown 7 | 8 | //! Debug Data Transfer Register, Receive 9 | //! 10 | //! Transfers data from an external debugger to the PE. For example, it is used by a debugger 11 | //! transferring commands and data to a debug target. See DBGDTR_EL0 for additional architectural 12 | //! mappings. It is a component of the Debug Communications Channel. 13 | 14 | use tock_registers::interfaces::Readable; 15 | 16 | pub struct Reg; 17 | 18 | impl Readable for Reg { 19 | type T = u64; 20 | type R = (); 21 | 22 | sys_coproc_read_raw!(u64, "DBGDTRRX_EL0", "x"); 23 | } 24 | 25 | pub const DBGDTRRX_EL0: Reg = Reg {}; 26 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/dbgdtrtx_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2020-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Chris Brown 7 | 8 | //! Debug Data Transfer Register, Transmit 9 | //! 10 | //! Transfers data from the PE to an external debugger. For example, it is used by a debug target 11 | //! to transfer data to the debugger. See DBGDTR_EL0 for additional architectural mappings. It is a 12 | //! component of the Debug Communication Channel. 13 | 14 | use tock_registers::interfaces::Writeable; 15 | 16 | pub struct Reg; 17 | 18 | impl Writeable for Reg { 19 | type T = u64; 20 | type R = (); 21 | 22 | sys_coproc_write_raw!(u64, "DBGDTRTX_EL0", "x"); 23 | } 24 | 25 | pub const DBGDTRTX_EL0: Reg = Reg {}; 26 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/elr_el1.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Exception Link Register - EL1 9 | //! 10 | //! When taking an exception to EL1, holds the address to return to. 11 | 12 | use tock_registers::interfaces::{Readable, Writeable}; 13 | 14 | pub struct Reg; 15 | 16 | impl Readable for Reg { 17 | type T = u64; 18 | type R = (); 19 | 20 | sys_coproc_read_raw!(u64, "ELR_EL1", "x"); 21 | } 22 | 23 | impl Writeable for Reg { 24 | type T = u64; 25 | type R = (); 26 | 27 | sys_coproc_write_raw!(u64, "ELR_EL1", "x"); 28 | } 29 | 30 | pub const ELR_EL1: Reg = Reg {}; 31 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/elr_el2.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Exception Link Register - EL2 9 | //! 10 | //! When taking an exception to EL2, holds the address to return to. 11 | 12 | use tock_registers::interfaces::{Readable, Writeable}; 13 | 14 | pub struct Reg; 15 | 16 | impl Readable for Reg { 17 | type T = u64; 18 | type R = (); 19 | 20 | sys_coproc_read_raw!(u64, "ELR_EL2", "x"); 21 | } 22 | 23 | impl Writeable for Reg { 24 | type T = u64; 25 | type R = (); 26 | 27 | sys_coproc_write_raw!(u64, "ELR_EL2", "x"); 28 | } 29 | 30 | pub const ELR_EL2: Reg = Reg {}; 31 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/elr_el3.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | // - Berkus Decker 8 | 9 | //! Exception Link Register - EL3 10 | //! 11 | //! When taking an exception to EL3, holds the address to return to. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "ELR_EL3", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "ELR_EL3", "x"); 29 | } 30 | 31 | pub const ELR_EL3: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/far_el1.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Fault Address Register - EL1 9 | //! 10 | //! Holds the faulting Virtual Address for all synchronous Instruction or Data Abort, PC alignment 11 | //! fault and Watchpoint exceptions that are taken to EL1. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "FAR_EL1", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "FAR_EL1", "x"); 29 | } 30 | 31 | pub const FAR_EL1: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/far_el2.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Fault Address Register - EL2 9 | //! 10 | //! Holds the faulting Virtual Address for all synchronous Instruction or Data Abort, PC alignment 11 | //! fault and Watchpoint exceptions that are taken to EL2. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "FAR_EL2", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "FAR_EL2", "x"); 29 | } 30 | 31 | pub const FAR_EL2: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/far_el3.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Fault Address Register - EL3 9 | //! 10 | //! Holds the faulting Virtual Address for all synchronous Instruction or Data Abort, PC alignment 11 | //! fault and Watchpoint exceptions that are taken to EL3. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "FAR_EL3", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "FAR_EL3", "x"); 29 | } 30 | 31 | pub const FAR_EL3: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/fp.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2022-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! The frame pointer register 9 | 10 | use tock_registers::interfaces::{Readable, Writeable}; 11 | 12 | pub struct Reg; 13 | 14 | impl Readable for Reg { 15 | type T = u64; 16 | type R = (); 17 | 18 | read_raw!(u64, "x29", "x"); 19 | } 20 | 21 | impl Writeable for Reg { 22 | type T = u64; 23 | type R = (); 24 | 25 | write_raw!(u64, "x29", "x"); 26 | } 27 | 28 | pub const FP: Reg = Reg {}; 29 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/id_aa64isar0_el1.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2022-2023 Amazon.com, Inc. or its affiliates. 4 | // 5 | // Author(s): 6 | // - Ali Saidi 7 | 8 | //! AArch64 Instruction Set Architecture Feature Register 0 - EL1 9 | //! 10 | //! Provides information about the implemented instruction set. 11 | 12 | use tock_registers::{interfaces::Readable, register_bitfields}; 13 | 14 | register_bitfields! {u64, 15 | pub ID_AA64ISAR0_EL1 [ 16 | /// Support for Random Number instructions in AArch64. 17 | /// 18 | /// 0000 No random number instructions are implemented 19 | /// 0001 RNDR and RNDRSS are implemented 20 | /// 21 | /// All other values are reserved. 22 | RNDR OFFSET(60) NUMBITS(4) [ 23 | Supported = 0b0001, 24 | NotSupported = 0b0000 25 | ], 26 | ] 27 | } 28 | 29 | pub struct Reg; 30 | 31 | impl Readable for Reg { 32 | type T = u64; 33 | type R = ID_AA64ISAR0_EL1::Register; 34 | 35 | sys_coproc_read_raw!(u64, "ID_AA64ISAR0_EL1", "x"); 36 | } 37 | 38 | pub const ID_AA64ISAR0_EL1: Reg = Reg {}; 39 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/lr.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | // - Alban Seurat 8 | 9 | //! The link register 10 | 11 | use tock_registers::interfaces::{Readable, Writeable}; 12 | 13 | pub struct Reg; 14 | 15 | impl Readable for Reg { 16 | type T = u64; 17 | type R = (); 18 | 19 | read_raw!(u64, "lr", "x"); 20 | } 21 | 22 | impl Writeable for Reg { 23 | type T = u64; 24 | type R = (); 25 | 26 | write_raw!(u64, "lr", "x"); 27 | } 28 | 29 | pub const LR: Reg = Reg {}; 30 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/mdccsr_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2020-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Chris Brown 7 | 8 | //! Monitor DCC Status Register 9 | //! 10 | //! Transfers data from an external debugger to the PE. For example, it is used by a debugger 11 | //! transferring commands and data to a debug target. See DBGDTR_EL0 for additional architectural 12 | //! mappings. It is a component of the Debug Communications Channel. 13 | 14 | use tock_registers::{interfaces::Readable, register_bitfields}; 15 | 16 | register_bitfields! {u64, 17 | pub MDCCSR_EL0 [ 18 | /// DTRRX full. Read-only view of the equivalent bit in the EDSCR. 19 | RXfull OFFSET(30) NUMBITS(1) [ 20 | NotFull = 0, 21 | Full = 1 22 | ], 23 | 24 | /// DTRTX full. Read-only view of the equivalent bit in the EDSCR. 25 | TXfull OFFSET(29) NUMBITS(1) [ 26 | NotFull = 0, 27 | Full = 1 28 | ] 29 | ] 30 | } 31 | 32 | pub struct Reg; 33 | 34 | impl Readable for Reg { 35 | type T = u64; 36 | type R = MDCCSR_EL0::Register; 37 | 38 | sys_coproc_read_raw!(u64, "MDCCSR_EL0", "x"); 39 | } 40 | 41 | pub const MDCCSR_EL0: Reg = Reg {}; 42 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/mpidr_el1.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Multiprocessor Affinity Register - EL1 9 | //! 10 | //! In a multiprocessor system, provides an additional PE identification mechanism for scheduling 11 | //! purposes. 12 | 13 | use tock_registers::{interfaces::Readable, register_bitfields}; 14 | 15 | register_bitfields! {u64, 16 | pub MPIDR_EL1 [ 17 | /// Affinity level 3. See the description of Aff0 for more information. 18 | Aff3 OFFSET(32) NUMBITS(8) [], 19 | 20 | /// Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. 21 | U OFFSET(30) NUMBITS(1) [ 22 | MultiprocessorSystem = 0b0, 23 | UniprocessorSystem = 0b1, 24 | ], 25 | 26 | /// Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a 27 | /// multithreading type approach. See the description of Aff0 for more information about affinity levels 28 | MT OFFSET(24) NUMBITS(1) [], 29 | 30 | /// Affinity level 2. See the description of Aff0 for more information. 31 | Aff2 OFFSET(16) NUMBITS(8) [], 32 | 33 | /// Affinity level 1. See the description of Aff0 for more information. 34 | Aff1 OFFSET(8) NUMBITS(8) [], 35 | 36 | /// Affinity level 0. This is the affinity level that is most significant for determining PE behavior. Higher 37 | /// affinity levels are increasingly less significant in determining PE behavior. 38 | Aff0 OFFSET(0) NUMBITS(8) [] 39 | ] 40 | } 41 | 42 | pub struct Reg; 43 | 44 | impl Readable for Reg { 45 | type T = u64; 46 | type R = MPIDR_EL1::Register; 47 | 48 | sys_coproc_read_raw!(u64, "MPIDR_EL1", "x"); 49 | } 50 | 51 | pub const MPIDR_EL1: Reg = Reg {}; 52 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/oslar_el1.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | // - Javier Alvarez 8 | 9 | //! OS Lock Access Register - EL1 10 | //! 11 | //! Used to lock or unlock the OS Lock. 12 | //! 13 | //! AArch64 System register `OSLAR_EL1` bits \[31:0\] are architecturally mapped to External 14 | //! register `OSLAR_EL1[31:0]`. The OS Lock can also be locked or unlocked using `DBGOSLAR`. 15 | 16 | use tock_registers::{ 17 | interfaces::{Readable, Writeable}, 18 | register_bitfields, 19 | }; 20 | 21 | register_bitfields! {u64, 22 | pub OSLAR_EL1 [ 23 | /// On writes to `OSLAR_EL1`, bit[0] is copied to the OS Lock. 24 | /// Use `OSLSR_EL1.OSLK` to check the current status of the lock. 25 | OSLK OFFSET(0) NUMBITS(1) [ 26 | Unlocked = 0, 27 | Locked = 1 28 | ] 29 | ] 30 | } 31 | 32 | pub struct Reg; 33 | 34 | impl Readable for Reg { 35 | type T = u64; 36 | type R = OSLAR_EL1::Register; 37 | 38 | sys_coproc_read_raw!(u64, "OSLAR_EL1", "x"); 39 | } 40 | 41 | impl Writeable for Reg { 42 | type T = u64; 43 | type R = OSLAR_EL1::Register; 44 | 45 | sys_coproc_write_raw!(u64, "OSLAR_EL1", "x"); 46 | } 47 | 48 | pub const OSLAR_EL1: Reg = Reg {}; 49 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/rvbar_el1.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Matt Schulte 7 | 8 | //! Reset Vector Base Address Register - EL1 9 | //! 10 | //! If EL1 is the highest Exception level implemented, contains the 11 | //! IMPLEMENTATION DEFINED address that execution starts from after reset when 12 | //! executing in AArch64 state. 13 | 14 | use tock_registers::interfaces::Readable; 15 | 16 | pub struct Reg; 17 | 18 | impl Readable for Reg { 19 | type T = u64; 20 | type R = (); 21 | 22 | sys_coproc_read_raw!(u64, "RVBAR_EL1", "x"); 23 | } 24 | 25 | pub const RVBAR_EL1: Reg = Reg; 26 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/rvbar_el2.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Matt Schulte 7 | 8 | //! Reset Vector Base Address Register - EL2 9 | //! 10 | //! If EL2 is the highest Exception level implemented, contains the 11 | //! IMPLEMENTATION DEFINED address that execution starts from after reset when 12 | //! executing in AArch64 state. 13 | 14 | use tock_registers::interfaces::Readable; 15 | 16 | pub struct Reg; 17 | 18 | impl Readable for Reg { 19 | type T = u64; 20 | type R = (); 21 | 22 | sys_coproc_read_raw!(u64, "RVBAR_EL2", "x"); 23 | } 24 | 25 | pub const RVBAR_EL2: Reg = Reg; 26 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/rvbar_el3.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Matt Schulte 7 | 8 | //! Reset Vector Base Address Register - EL3 9 | //! 10 | //! If EL3 is the highest Exception level implemented, contains the 11 | //! IMPLEMENTATION DEFINED address that execution starts from after reset when 12 | //! executing in AArch64 state. 13 | 14 | use tock_registers::interfaces::Readable; 15 | 16 | pub struct Reg; 17 | 18 | impl Readable for Reg { 19 | type T = u64; 20 | type R = (); 21 | 22 | sys_coproc_read_raw!(u64, "RVBAR_EL3", "x"); 23 | } 24 | 25 | pub const RVBAR_EL3: Reg = Reg; 26 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/sp.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! The stack pointer 9 | 10 | use tock_registers::interfaces::{Readable, Writeable}; 11 | 12 | pub struct Reg; 13 | 14 | impl Readable for Reg { 15 | type T = u64; 16 | type R = (); 17 | 18 | read_raw!(u64, "sp", "x"); 19 | } 20 | 21 | impl Writeable for Reg { 22 | type T = u64; 23 | type R = (); 24 | 25 | write_raw!(u64, "sp", "x"); 26 | } 27 | 28 | pub const SP: Reg = Reg {}; 29 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/sp_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! The stack pointer - EL0 9 | //! 10 | //! Holds the stack pointer associated with EL0. At higher Exception levels, this is used as the 11 | //! current stack pointer when the value of SPSel.SP is 0. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "SP_EL0", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "SP_EL0", "x"); 29 | } 30 | 31 | pub const SP_EL0: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/sp_el1.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! The stack pointer - EL1 9 | //! 10 | //! Holds the stack pointer associated with EL1. When executing at EL1, the value of SPSel.SP 11 | //! determines the current stack pointer: 12 | //! 13 | //! SPSel.SP | current stack pointer 14 | //! -------------------------------- 15 | //! 0 | SP_EL0 16 | //! 1 | SP_EL1 17 | 18 | use tock_registers::interfaces::{Readable, Writeable}; 19 | 20 | pub struct Reg; 21 | 22 | impl Readable for Reg { 23 | type T = u64; 24 | type R = (); 25 | 26 | sys_coproc_read_raw!(u64, "SP_EL1", "x"); 27 | } 28 | 29 | impl Writeable for Reg { 30 | type T = u64; 31 | type R = (); 32 | 33 | sys_coproc_write_raw!(u64, "SP_EL1", "x"); 34 | } 35 | 36 | pub const SP_EL1: Reg = Reg {}; 37 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/spsel.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Stack Pointer Select 9 | //! 10 | //! Allows the Stack Pointer to be selected between SP_EL0 and SP_ELx. 11 | 12 | use tock_registers::{ 13 | interfaces::{Readable, Writeable}, 14 | register_bitfields, 15 | }; 16 | 17 | register_bitfields! {u64, 18 | pub SPSel [ 19 | /// Stack pointer to use. Possible values of this bit are: 20 | /// 21 | /// 0 Use SP_EL0 at all Exception levels. 22 | /// 1 Use SP_ELx for Exception level ELx. 23 | /// 24 | /// When this register has an architecturally-defined reset value, this field resets to 1. 25 | SP OFFSET(0) NUMBITS(1) [ 26 | EL0 = 0, 27 | ELx = 1 28 | ] 29 | ] 30 | } 31 | 32 | pub struct Reg; 33 | 34 | impl Readable for Reg { 35 | type T = u64; 36 | type R = SPSel::Register; 37 | 38 | sys_coproc_read_raw!(u64, "SPSEL", "x"); 39 | } 40 | 41 | impl Writeable for Reg { 42 | type T = u64; 43 | type R = SPSel::Register; 44 | 45 | sys_coproc_write_raw!(u64, "SPSEL", "x"); 46 | } 47 | 48 | #[allow(non_upper_case_globals)] 49 | pub const SPSel: Reg = Reg {}; 50 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/tpidr_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2020-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Erik Verbruggen 7 | 8 | //! Read/Write Software Thread ID Register - EL0. 9 | //! 10 | //! Provides a location where software executing at EL0 can store thread identifying information, 11 | //! for OS management purposes. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "TPIDR_EL0", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "TPIDR_EL0", "x"); 29 | } 30 | 31 | pub const TPIDR_EL0: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/tpidr_el1.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2020-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Erik Verbruggen 7 | 8 | //! Software Thread ID Register - EL1. 9 | //! 10 | //! Provides a location where software executing at EL1 can store thread identifying information, 11 | //! for OS management purposes. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "TPIDR_EL1", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "TPIDR_EL1", "x"); 29 | } 30 | 31 | pub const TPIDR_EL1: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/tpidr_el2.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2022 Amazon.com, Inc. or its affiliates. 4 | // Author(s): 5 | // - Javi Merino 6 | 7 | //! Software Thread ID Register - EL2. 8 | //! 9 | //! Provides a location where software executing at EL2 can store thread identifying information, 10 | //! for OS management purposes. 11 | 12 | use tock_registers::interfaces::{Readable, Writeable}; 13 | 14 | pub struct Reg; 15 | 16 | impl Readable for Reg { 17 | type T = u64; 18 | type R = (); 19 | 20 | sys_coproc_read_raw!(u64, "TPIDR_EL2", "x"); 21 | } 22 | 23 | impl Writeable for Reg { 24 | type T = u64; 25 | type R = (); 26 | 27 | sys_coproc_write_raw!(u64, "TPIDR_EL2", "x"); 28 | } 29 | 30 | pub const TPIDR_EL2: Reg = Reg {}; 31 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/tpidrro_el0.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2020-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Erik Verbruggen 7 | 8 | //! Read-Only Software Thread ID Register - EL0. 9 | //! 10 | //! Provides a location where software executing at EL1 or higher can store thread identifying 11 | //! information that is visible to software executing at EL0, for OS management purposes. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "TPIDRRO_EL0", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "TPIDRRO_EL0", "x"); 29 | } 30 | 31 | pub const TPIDRRO_EL0: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/ttbr0_el1.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Translation Table Base Register 0 - EL1 9 | //! 10 | //! Holds the base address of the translation table for the initial lookup for stage 1 of the 11 | //! translation of an address from the lower VA range in the EL1&0 translation regime, and other 12 | //! information for this translation regime. 13 | 14 | use tock_registers::{ 15 | interfaces::{Readable, Writeable}, 16 | register_bitfields, 17 | }; 18 | 19 | register_bitfields! {u64, 20 | pub TTBR0_EL1 [ 21 | /// An ASID for the translation table base address. The TCR_EL1.A1 field selects either 22 | /// TTBR0_EL1.ASID or TTBR1_EL1.ASID. 23 | /// 24 | /// If the implementation has only 8 bits of ASID, then the upper 8 bits of this field are 25 | /// RES 0. 26 | ASID OFFSET(48) NUMBITS(16) [], 27 | 28 | /// Translation table base address 29 | BADDR OFFSET(1) NUMBITS(47) [], 30 | 31 | /// Common not Private 32 | CnP OFFSET(0) NUMBITS(1) [] 33 | ] 34 | } 35 | 36 | pub struct Reg; 37 | 38 | impl Readable for Reg { 39 | type T = u64; 40 | type R = TTBR0_EL1::Register; 41 | 42 | sys_coproc_read_raw!(u64, "TTBR0_EL1", "x"); 43 | } 44 | 45 | impl Writeable for Reg { 46 | type T = u64; 47 | type R = TTBR0_EL1::Register; 48 | 49 | sys_coproc_write_raw!(u64, "TTBR0_EL1", "x"); 50 | } 51 | 52 | impl Reg { 53 | #[inline(always)] 54 | pub fn get_baddr(&self) -> u64 { 55 | self.read(TTBR0_EL1::BADDR) << 1 56 | } 57 | 58 | #[inline(always)] 59 | pub fn set_baddr(&self, addr: u64) { 60 | self.write(TTBR0_EL1::BADDR.val(addr >> 1)); 61 | } 62 | } 63 | 64 | pub const TTBR0_EL1: Reg = Reg {}; 65 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/ttbr0_el2.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | // - Bradley Landherr 8 | 9 | //! Translation Table Base Register 0 - EL2 10 | //! 11 | //! Holds the base address of the translation table for the initial lookup for stage 1 of the 12 | //! translation of an address from the lower VA range for accesses from EL2. 13 | 14 | use tock_registers::{ 15 | interfaces::{Readable, Writeable}, 16 | register_bitfields, 17 | }; 18 | 19 | register_bitfields! {u64, 20 | pub TTBR0_EL2 [ 21 | /// Reserved 22 | RES0 OFFSET(48) NUMBITS(16) [], 23 | 24 | /// Translation table base address 25 | BADDR OFFSET(1) NUMBITS(48) [], 26 | 27 | /// Common not Private 28 | CnP OFFSET(0) NUMBITS(1) [] 29 | ] 30 | } 31 | 32 | pub struct Reg; 33 | 34 | impl Readable for Reg { 35 | type T = u64; 36 | type R = TTBR0_EL2::Register; 37 | 38 | sys_coproc_read_raw!(u64, "TTBR0_EL2", "x"); 39 | } 40 | 41 | impl Writeable for Reg { 42 | type T = u64; 43 | type R = TTBR0_EL2::Register; 44 | 45 | sys_coproc_write_raw!(u64, "TTBR0_EL2", "x"); 46 | } 47 | 48 | impl Reg { 49 | #[inline(always)] 50 | pub fn get_baddr(&self) -> u64 { 51 | self.read(TTBR0_EL2::BADDR) << 1 52 | } 53 | 54 | #[inline(always)] 55 | pub fn set_baddr(&self, addr: u64) { 56 | self.write(TTBR0_EL2::BADDR.val(addr >> 1)); 57 | } 58 | } 59 | 60 | pub const TTBR0_EL2: Reg = Reg {}; 61 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/ttbr1_el1.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Translation Table Base Register 1 - EL1 9 | //! 10 | //! Holds the base address of the translation table for the initial lookup for stage 1 of the 11 | //! translation of an address from the higher VA range in the EL1&0 translation regime, and other 12 | //! information for this translation regime. 13 | 14 | use tock_registers::{ 15 | interfaces::{Readable, Writeable}, 16 | register_bitfields, 17 | }; 18 | 19 | register_bitfields! {u64, 20 | pub TTBR1_EL1 [ 21 | /// An ASID for the translation table base address. The TCR_EL1.A1 field selects either 22 | /// TTBR0_EL1.ASID or TTBR1_EL1.ASID. 23 | /// 24 | /// If the implementation has only 8 bits of ASID, then the upper 8 bits of this field are 25 | /// RES 0. 26 | ASID OFFSET(48) NUMBITS(16) [], 27 | 28 | /// Translation table base address 29 | BADDR OFFSET(1) NUMBITS(47) [], 30 | 31 | /// Common not Private 32 | CnP OFFSET(0) NUMBITS(1) [] 33 | ] 34 | } 35 | 36 | pub struct Reg; 37 | 38 | impl Readable for Reg { 39 | type T = u64; 40 | type R = TTBR1_EL1::Register; 41 | 42 | sys_coproc_read_raw!(u64, "TTBR1_EL1", "x"); 43 | } 44 | 45 | impl Writeable for Reg { 46 | type T = u64; 47 | type R = TTBR1_EL1::Register; 48 | 49 | sys_coproc_write_raw!(u64, "TTBR1_EL1", "x"); 50 | } 51 | 52 | impl Reg { 53 | #[inline(always)] 54 | pub fn get_baddr(&self) -> u64 { 55 | self.read(TTBR1_EL1::BADDR) << 1 56 | } 57 | 58 | #[inline(always)] 59 | pub fn set_baddr(&self, addr: u64) { 60 | self.write(TTBR1_EL1::BADDR.val(addr >> 1)); 61 | } 62 | } 63 | 64 | pub const TTBR1_EL1: Reg = Reg {}; 65 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/vbar_el1.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | 8 | //! Vector Base Address Register - EL1 9 | //! 10 | //! Holds the vector base address for any exception that is taken to EL1. 11 | 12 | use tock_registers::interfaces::{Readable, Writeable}; 13 | 14 | pub struct Reg; 15 | 16 | impl Readable for Reg { 17 | type T = u64; 18 | type R = (); 19 | 20 | sys_coproc_read_raw!(u64, "VBAR_EL1", "x"); 21 | } 22 | 23 | impl Writeable for Reg { 24 | type T = u64; 25 | type R = (); 26 | 27 | sys_coproc_write_raw!(u64, "VBAR_EL1", "x"); 28 | } 29 | 30 | pub const VBAR_EL1: Reg = Reg {}; 31 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/vbar_el2.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | // - Javier Alvarez 8 | 9 | //! Vector Base Address Register - EL2 10 | //! 11 | //! Holds the vector base address for any exception that is taken to EL2. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "VBAR_EL2", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "VBAR_EL2", "x"); 29 | } 30 | 31 | pub const VBAR_EL2: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/vbar_el3.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - Andre Richter 7 | // - Javier Alvarez 8 | 9 | //! Vector Base Address Register - EL3 10 | //! 11 | //! Holds the vector base address for any exception that is taken to EL3. 12 | 13 | use tock_registers::interfaces::{Readable, Writeable}; 14 | 15 | pub struct Reg; 16 | 17 | impl Readable for Reg { 18 | type T = u64; 19 | type R = (); 20 | 21 | sys_coproc_read_raw!(u64, "VBAR_EL3", "x"); 22 | } 23 | 24 | impl Writeable for Reg { 25 | type T = u64; 26 | type R = (); 27 | 28 | sys_coproc_write_raw!(u64, "VBAR_EL3", "x"); 29 | } 30 | 31 | pub const VBAR_EL3: Reg = Reg {}; 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/aarch64-cpu/src/registers/vttbr_el2.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 OR MIT 2 | // 3 | // Copyright (c) 2018-2023 by the author(s) 4 | // 5 | // Author(s): 6 | // - KarimAllah Ahmed 7 | // - Andre Richter 8 | 9 | use tock_registers::{ 10 | interfaces::{Readable, Writeable}, 11 | register_bitfields, 12 | }; 13 | 14 | register_bitfields! {u64, 15 | pub VTTBR_EL2 [ 16 | /// An VMID for the translation table 17 | /// 18 | /// If the implementation only supports 8-bit VM IDs the top 8 bits are RES0 19 | VMID OFFSET(48) NUMBITS(16) [], 20 | 21 | /// Translation table base address 22 | BADDR OFFSET(1) NUMBITS(48) [], 23 | 24 | /// Common not Private 25 | CnP OFFSET(0) NUMBITS(1) [] 26 | ] 27 | } 28 | 29 | pub struct Reg; 30 | 31 | impl Readable for Reg { 32 | type T = u64; 33 | type R = VTTBR_EL2::Register; 34 | 35 | sys_coproc_read_raw!(u64, "VTTBR_EL2", "x"); 36 | } 37 | 38 | impl Writeable for Reg { 39 | type T = u64; 40 | type R = VTTBR_EL2::Register; 41 | 42 | sys_coproc_write_raw!(u64, "VTTBR_EL2", "x"); 43 | } 44 | 45 | impl Reg { 46 | #[inline(always)] 47 | pub fn get_baddr(&self) -> u64 { 48 | self.read(VTTBR_EL2::BADDR) << 1 49 | } 50 | 51 | #[inline(always)] 52 | pub fn set_baddr(&self, addr: u64) { 53 | self.write(VTTBR_EL2::BADDR.val(addr >> 1)); 54 | } 55 | } 56 | 57 | pub const VTTBR_EL2: Reg = Reg {}; 58 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/arch/cpu_core.rs: -------------------------------------------------------------------------------- 1 | //! Architectural processor code. 2 | //! 3 | 4 | pub use asm::nop; 5 | use aarch64_cpu::asm; 6 | 7 | use crate::info; 8 | //-------------------------------------------------------------------------------------------------- 9 | // Public Code 10 | //-------------------------------------------------------------------------------------------------- 11 | 12 | /// Pause execution on the core. 13 | #[no_mangle] 14 | pub fn wait_forever() -> ! { 15 | info!("\n"); 16 | info!(" ... wait forever"); 17 | loop { 18 | asm::wfe() 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/arch/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod cpu_core; 2 | pub mod timer; 3 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/bsp/clocks/mod.rs: -------------------------------------------------------------------------------- 1 | mod ccm; 2 | pub mod uartclks; 3 | pub mod usdhcclks; 4 | pub mod scntrclk; 5 | pub mod analog; -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/bsp/clocks/scntrclk.rs: -------------------------------------------------------------------------------- 1 | //! Enable or Disable system counter 2 | 3 | use super::ccm::*; 4 | 5 | /// Allow system counter i.e. ungate clock gate for SCTR. 6 | pub fn enable_sctr() { 7 | clock_enable(CCGRIdx::CcgrSctr, true) 8 | } -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/bsp/clocks/uartclks.rs: -------------------------------------------------------------------------------- 1 | //! The `i.MX8MN` has 4 UARTs in total. Although, a UART interface does not use a clock signal i.e. 2 | //! it is an asynchronous protocol, the i.MX8MN requires the corresponding clock for a UART to be enabled 3 | //! before you can start using the peripheral. 4 | 5 | use super::ccm::*; 6 | use crate::info; 7 | 8 | /// Enable UART clocks. 9 | pub fn enable_uart_clk(index: u32) { 10 | /* 11 | * set uart clock root 12 | * 24M OSC 13 | */ 14 | match index { 15 | 0 => { 16 | clock_enable(CCGRIdx::CcgrUart1, false); 17 | clock_set_target_val( 18 | ClkRootIdx::Uart1ClkRoot, 19 | CLK_ROOT_ON | clk_root_source_sel(0), 20 | ); 21 | clock_enable(CCGRIdx::CcgrUart1, true); 22 | } 23 | 1 => { 24 | clock_enable(CCGRIdx::CcgrUart2, false); 25 | clock_set_target_val( 26 | ClkRootIdx::Uart2ClkRoot, 27 | CLK_ROOT_ON | clk_root_source_sel(0), 28 | ); 29 | clock_enable(CCGRIdx::CcgrUart2, true); 30 | } 31 | 2 => { 32 | clock_enable(CCGRIdx::CcgrUart3, false); 33 | clock_set_target_val( 34 | ClkRootIdx::Uart3ClkRoot, 35 | CLK_ROOT_ON | clk_root_source_sel(0), 36 | ); 37 | clock_enable(CCGRIdx::CcgrUart3, true); 38 | } 39 | 3 => { 40 | clock_enable(CCGRIdx::CcgrUart4, false); 41 | clock_set_target_val( 42 | ClkRootIdx::Uart4ClkRoot, 43 | CLK_ROOT_ON | clk_root_source_sel(0), 44 | ); 45 | clock_enable(CCGRIdx::CcgrUart4, true); 46 | } 47 | _ => { 48 | info!("invalid uart selection \n"); 49 | } 50 | } 51 | } -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/bsp/clocks/usdhcclks.rs: -------------------------------------------------------------------------------- 1 | //! The i.MX8 has 3 uSDHC(s). Select root clock SYSTEM_PLL1_DIV2_CLK i.e. 800Mhz/2 for uSDHC2 2 | 3 | use super::ccm::*; 4 | use crate::info; 5 | 6 | /// Enable uSDHC clocks. 7 | pub fn enable_usdhc_clk(index: u32) { 8 | match index { 9 | 1 => { 10 | clock_enable(CCGRIdx::CcgrUsdhc1, false); 11 | clock_set_target_val( 12 | ClkRootIdx::Usdhc1ClkRoot, 13 | CLK_ROOT_ON | clk_root_source_sel(1), 14 | ); 15 | clock_enable(CCGRIdx::CcgrUsdhc1, true); 16 | } 17 | 2 => { 18 | clock_enable(CCGRIdx::CcgrUsdhc2, false); 19 | clock_set_target_val( 20 | ClkRootIdx::Usdhc2ClkRoot, 21 | CLK_ROOT_ON | clk_root_source_sel(1), 22 | ); 23 | clock_enable(CCGRIdx::CcgrUsdhc2, true); 24 | } 25 | 3 => { 26 | clock_enable(CCGRIdx::CcgrUsdhc3, false); 27 | clock_set_target_val( 28 | ClkRootIdx::Usdhc3ClkRoot, 29 | CLK_ROOT_ON | clk_root_source_sel(1), 30 | ); 31 | clock_enable(CCGRIdx::CcgrUsdhc3, true); 32 | } 33 | _ => { 34 | info!("invalid uSDHC selection \n"); 35 | } 36 | } 37 | } 38 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/bsp/drivers/common.rs: -------------------------------------------------------------------------------- 1 | //! Common device driver code. 2 | 3 | use core::{marker::PhantomData, ops}; 4 | 5 | pub struct MMIODerefWrapper { 6 | start_addr: usize, 7 | phantom: PhantomData T>, 8 | } 9 | 10 | impl MMIODerefWrapper { 11 | /// Create an instance. 12 | pub const unsafe fn new(start_addr: usize) -> Self { 13 | Self { 14 | start_addr, 15 | phantom: PhantomData, 16 | } 17 | } 18 | } 19 | 20 | impl ops::Deref for MMIODerefWrapper { 21 | type Target = T; 22 | 23 | fn deref(&self) -> &Self::Target { 24 | unsafe { &*(self.start_addr as *const T) } 25 | } 26 | } 27 | 28 | /// Driver interfaces. 29 | pub mod interface { 30 | /// Device Driver functions. 31 | #[no_mangle] 32 | pub trait DeviceDriver { 33 | /// Return a compatibility string for identifying the driver. 34 | fn compatible(&self) -> &'static str; 35 | 36 | /// Called by the kernel to bring up the device. 37 | /// 38 | /// # Safety 39 | /// 40 | /// - During init, drivers might do stuff with system-wide impact. 41 | unsafe fn init(&self) -> Result<(), &'static str> { 42 | Ok(()) 43 | } 44 | } 45 | 46 | /// Device driver management functions. 47 | /// 48 | /// The `BSP` is supposed to supply one global instance. 49 | pub trait DriverManager { 50 | /// Return a slice of references to all `BSP`-instantiated drivers. 51 | /// 52 | /// # Safety 53 | /// 54 | /// - The order of devices is the order in which `DeviceDriver::init()` is called. 55 | fn all_device_drivers(&self) -> &[&'static (dyn DeviceDriver + Sync)]; 56 | } 57 | } 58 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/bsp/drivers/driver_manager.rs: -------------------------------------------------------------------------------- 1 | //! BSP driver support. 2 | 3 | use super::common::interface::{DeviceDriver, DriverManager}; 4 | use crate::info; 5 | use crate::nxp::imx8mn::bsp::global::{UART, CNTR, ANALOG}; 6 | 7 | /// Device Driver Manager type. 8 | struct BSPDriverManager { 9 | device_drivers: [&'static (dyn DeviceDriver + Sync); 1], 10 | } 11 | 12 | // Global instances 13 | 14 | static BSP_DRIVER_MANAGER: BSPDriverManager = BSPDriverManager { 15 | device_drivers: [&UART], 16 | }; 17 | 18 | /// Return a reference to the driver manager. 19 | pub fn driver_manager() -> &'static impl DriverManager { 20 | &BSP_DRIVER_MANAGER 21 | } 22 | 23 | /// Turn on system counter. 24 | pub fn start_system_counter() { 25 | &CNTR.start_counter(); 26 | } 27 | 28 | /// Configure system Plls and set clock-gates, root-clocks for GIC, DRAM, NAND, WDG etc. 29 | pub fn sys_clocks_init() { 30 | &ANALOG.clock_init(); 31 | } 32 | 33 | impl DriverManager for BSPDriverManager { 34 | fn all_device_drivers(&self) -> &[&'static (dyn DeviceDriver + Sync)] { 35 | &self.device_drivers[..] 36 | } 37 | } 38 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/bsp/drivers/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod common; 2 | pub mod driver_manager; 3 | // pub mod emmc; 4 | pub mod gpio; 5 | pub mod uart0; 6 | pub mod usdhc; 7 | // pub mod gicv2; 8 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/bsp/global.rs: -------------------------------------------------------------------------------- 1 | //! BSP Processor code. Global peripherals file for the i.MX8MN. 2 | 3 | use super::clocks::analog::CCMAnalog; 4 | use super::counter::SystemCounter; 5 | use super::drivers::{gpio::Gpio, uart0::Uart, usdhc::UsdhController}; 6 | use super::memory_map; 7 | use super::mux::uart2grp::*; 8 | 9 | pub static UART: Uart = unsafe { Uart::new(memory_map::map::mmio::UART_START) }; 10 | pub static GPIO2: Gpio = unsafe { Gpio::new(memory_map::map::mmio::GPIO2_START) }; 11 | pub static GPIO1: Gpio = unsafe { Gpio::new(memory_map::map::mmio::GPIO1_START) }; 12 | pub static CNTR: SystemCounter = unsafe { SystemCounter::new(memory_map::map::mmio::SYSCNT_START) }; 13 | pub static SDHC2: UsdhController = 14 | unsafe { UsdhController::new(memory_map::map::mmio::USDHC2_START) }; 15 | pub static ANALOG: CCMAnalog = unsafe { CCMAnalog::new(memory_map::map::mmio::CCM_ANALOG) }; 16 | 17 | /// Board identification. 18 | pub fn board_name() -> &'static str { 19 | { 20 | "i.MX 8M Nano EVK" 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/bsp/memory_map.rs: -------------------------------------------------------------------------------- 1 | //! BSP Memory Map. 2 | 3 | /// The board's physical memory map. 4 | #[rustfmt::skip] 5 | pub mod map { 6 | 7 | pub const GPIO1_OFFSET : usize = 0x0020_0000; 8 | pub const GPIO2_OFFSET : usize = 0x0021_0000; 9 | pub const CCM_OFFSET : usize = 0x0038_0000; 10 | pub const UART_OFFSET : usize = 0x0089_0000; 11 | pub const USDHC2_OFFSET : usize = 0x00B5_0000; 12 | pub const SYSCNT_OFFSET : usize = 0x006C_0000; 13 | pub const IOMUXC_OFFSET : usize = 0x0033_0000; 14 | pub const ANALOG_OFFSET : usize = 0x0036_0000; 15 | 16 | pub mod mmio { 17 | use super::*; 18 | 19 | pub const START: usize = 0x3000_0000; 20 | pub const GPIO2_START: usize = START + GPIO2_OFFSET; 21 | pub const GPIO1_START: usize = START + GPIO1_OFFSET; 22 | pub const CCM_START: usize = START + CCM_OFFSET; 23 | pub const UART_START: usize = START + UART_OFFSET; 24 | pub const USDHC2_START: usize = START + USDHC2_OFFSET; 25 | pub const SYSCNT_START: usize = START + SYSCNT_OFFSET; 26 | pub const IOMUXC_START: usize = START + IOMUXC_OFFSET; 27 | pub const CCM_ANALOG: usize = START + ANALOG_OFFSET; 28 | pub const END_INCLUSIVE: usize = 0x30FF_FFFF; 29 | 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/bsp/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod clocks; 2 | pub mod counter; 3 | pub mod drivers; 4 | pub mod global; 5 | pub mod memory_map; 6 | pub mod mux; 7 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/bsp/mux/iomuxc.rs: -------------------------------------------------------------------------------- 1 | //! Pin Mux and Pin Control types 2 | 3 | /// MUX Mode Select Field 4 | pub enum MuxMode { 5 | Alt0, 6 | Alt1, 7 | Alt2, 8 | Alt3, 9 | Alt4, 10 | Alt5, 11 | Alt6, 12 | Alt7, 13 | } 14 | 15 | /// Software Input On Field. 16 | pub enum Sion { 17 | Enabled, 18 | Disabled, 19 | } 20 | 21 | /// Drive Strength Field 22 | pub enum Dse { 23 | DseX1, 24 | DseX2, 25 | DseX6, 26 | Unimplemented, 27 | } 28 | /// Slew Rate Field 29 | pub enum Fsel { 30 | Slow, 31 | Fast, 32 | } 33 | /// Open Drain Enable Field 34 | pub enum Ode { 35 | Enabled, 36 | Disabled, 37 | } 38 | /// Control IO ports PS 39 | pub enum Pue { 40 | PullUp, 41 | PullDown, 42 | } 43 | /// Hysteresis Enable Field 44 | pub enum Hys { 45 | Enabled, 46 | Disabled, 47 | } 48 | /// Pull Resistors Enable Field 49 | pub enum Pe { 50 | Enabled, 51 | Disabled, 52 | } 53 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/bsp/mux/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod uart2grp; 2 | pub mod usdhc2grp; 3 | mod iomuxc; -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/exception/asynchronous.rs: -------------------------------------------------------------------------------- 1 | //! Architectural asynchronous exception handling. 2 | 3 | use aarch64_cpu::registers::*; 4 | use tock_registers::interfaces::Readable; 5 | 6 | trait DaifField { 7 | fn daif_field() -> tock_registers::fields::Field; 8 | } 9 | 10 | struct Debug; 11 | struct SError; 12 | struct IRQ; 13 | struct FIQ; 14 | 15 | impl DaifField for Debug { 16 | fn daif_field() -> tock_registers::fields::Field { 17 | DAIF::D 18 | } 19 | } 20 | 21 | impl DaifField for SError { 22 | fn daif_field() -> tock_registers::fields::Field { 23 | DAIF::A 24 | } 25 | } 26 | 27 | impl DaifField for IRQ { 28 | fn daif_field() -> tock_registers::fields::Field { 29 | DAIF::I 30 | } 31 | } 32 | 33 | impl DaifField for FIQ { 34 | fn daif_field() -> tock_registers::fields::Field { 35 | DAIF::F 36 | } 37 | } 38 | 39 | fn is_masked() -> bool 40 | where 41 | T: DaifField, 42 | { 43 | DAIF.is_set(T::daif_field()) 44 | } 45 | 46 | /// Print the AArch64 exceptions status. 47 | #[rustfmt::skip] 48 | pub fn print_state() { 49 | use crate::info; 50 | 51 | let to_mask_str = |x| -> _ { 52 | if x { "Masked" } else { "Unmasked" } 53 | }; 54 | 55 | info!(" Debug: {}", to_mask_str(is_masked::())); 56 | info!(" SError: {}", to_mask_str(is_masked::())); 57 | info!(" IRQ: {}", to_mask_str(is_masked::())); 58 | info!(" FIQ: {}", to_mask_str(is_masked::())); 59 | } 60 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/exception/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod asynchronous; 2 | pub mod exception; 3 | 4 | /// Kernel privilege levels. 5 | #[allow(missing_docs)] 6 | #[derive(PartialEq)] 7 | pub enum PrivilegeLevel { 8 | User, 9 | Kernel, 10 | Hypervisor, 11 | EL3Mode, 12 | Unknown, 13 | } 14 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/log/console.rs: -------------------------------------------------------------------------------- 1 | //! System console. 2 | 3 | use crate::nxp::imx8mn::bsp::{clocks, drivers::uart0::PanicUart, global, memory_map, mux}; 4 | 5 | use core::fmt; 6 | 7 | /// Console write functions. 8 | pub trait Write { 9 | /// Write a single character. 10 | fn write_char(&self, c: char); 11 | 12 | /// Write a Rust format string. 13 | fn write_fmt(&self, args: fmt::Arguments) -> fmt::Result; 14 | 15 | // /// Block until the last buffered character has been physically put on the TX wire. 16 | // fn flush(&self); 17 | } 18 | 19 | /// Console read functions. 20 | pub trait Read { 21 | /// Read a single character. 22 | fn read_char(&self) -> char { 23 | ' ' 24 | } 25 | 26 | /// Clear RX buffers, if any. 27 | fn clear_rx(&self); 28 | } 29 | 30 | /// Console statistics. 31 | pub trait Statistics { 32 | /// Return the number of characters written. 33 | fn chars_written(&self) -> usize { 34 | 0 35 | } 36 | 37 | /// Return the number of characters read. 38 | fn chars_read(&self) -> usize { 39 | 0 40 | } 41 | } 42 | 43 | /// In case of a panic, the panic handler uses this function to take a last shot at printing 44 | /// something before the system is halted. 45 | /// 46 | /// We try to init panic-versions of the GPIO and the UART. The panic versions are not protected 47 | /// with synchronization primitives, which increases chances that we get to print something, even 48 | /// when the kernel's default GPIO or UART instances happen to be locked at the time of the panic. 49 | /// 50 | /// # Safety 51 | /// 52 | /// - Use only for printing during a panic. 53 | pub unsafe fn panic_console_out() -> impl fmt::Write { 54 | let mut panic_uart = PanicUart::new(memory_map::map::mmio::UART_START); 55 | 56 | clocks::uartclks::enable_uart_clk(1); 57 | mux::uart2grp::uart2_mux_mmio_set(); 58 | panic_uart.init_uart(); 59 | panic_uart 60 | } 61 | 62 | /// Return a reference to the console. 63 | pub fn console() -> &'static (impl Write + Read + Statistics) { 64 | &global::UART 65 | } 66 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/log/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod console; 2 | pub mod print; 3 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/memory/mmu.rs: -------------------------------------------------------------------------------- 1 | //! Memory Management Unit Driver. 2 | 3 | use aarch64_cpu::{asm::barrier, registers::*}; 4 | use core::intrinsics::unlikely; 5 | use tock_registers::interfaces::{ReadWriteable, Readable, Writeable}; 6 | 7 | /// Memory Management Unit type. 8 | pub struct MemoryManagementUnit; 9 | 10 | /// Constants for indexing the MAIR_EL3. 11 | #[allow(dead_code)] 12 | pub mod mair { 13 | pub const DEVICE: u64 = 0; 14 | pub const NORMAL: u64 = 1; 15 | } 16 | 17 | pub static MMU: MemoryManagementUnit = MemoryManagementUnit; 18 | 19 | impl MemoryManagementUnit { 20 | /// Setup function for the MAIR_EL3 register. 21 | fn set_up_mair(&self) { 22 | // Define the memory types being mapped. 23 | MAIR_EL3.write( 24 | // Attribute 1 - Cacheable normal DRAM. 25 | MAIR_EL3::Attr1_Normal_Outer::WriteBack_NonTransient_ReadWriteAlloc + 26 | MAIR_EL3::Attr1_Normal_Inner::WriteBack_NonTransient_ReadWriteAlloc + 27 | 28 | // Attribute 0 - Device. 29 | MAIR_EL3::Attr0_Device::nonGathering_nonReordering_EarlyWriteAck, 30 | ); 31 | } 32 | 33 | #[inline(always)] 34 | fn is_enabled(&self) -> bool { 35 | SCTLR_EL3.matches_all(SCTLR_EL3::M::Enable) 36 | } 37 | 38 | pub unsafe fn disable_mmu_and_caching(&self) { 39 | // Disable the MMU . 40 | // 41 | // First, force all previous changes to be seen before the MMU is disabled. 42 | barrier::isb(barrier::SY); 43 | 44 | // We have already disabled the MMU using GDB. So, we only turn off data and instruction caching. 45 | SCTLR_EL3.modify( 46 | SCTLR_EL3::C::NonCacheable + SCTLR_EL3::I::NonCacheable, 47 | ); 48 | 49 | // Force MMU disabling to complete before next instruction. 50 | barrier::isb(barrier::SY); 51 | } 52 | } 53 | 54 | /// Return a reference to the MMU instance. 55 | pub fn mmu() -> &'static MemoryManagementUnit { 56 | &MMU 57 | } 58 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/memory/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod mmu; 2 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/imx8mn/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod arch; 2 | pub mod bsp; 3 | pub mod exception; 4 | pub mod log; 5 | pub mod memory; 6 | 7 | mod panic_wait; 8 | mod sync; 9 | -------------------------------------------------------------------------------- /boards/hal/src/nxp/mod.rs: -------------------------------------------------------------------------------- 1 | #[cfg(feature = "imx8mn")] 2 | pub mod imx8mn; -------------------------------------------------------------------------------- /boards/hal/src/pico/mod.rs: -------------------------------------------------------------------------------- 1 | #[cfg(feature = "rp2040")] 2 | pub mod rp2040; -------------------------------------------------------------------------------- /boards/hal/src/rpi/mod.rs: -------------------------------------------------------------------------------- 1 | #[cfg(feature = "rpi4")] 2 | pub mod rpi4; 3 | -------------------------------------------------------------------------------- /boards/hal/src/rpi/rpi4/arch/cpu_core.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: MIT OR Apache-2.0 2 | // 3 | // Copyright (c) 2018-2021 Andre Richter 4 | 5 | //! Architectural processor code. 6 | //! 7 | 8 | pub use asm::nop; 9 | use cortex_a::asm; 10 | //-------------------------------------------------------------------------------------------------- 11 | // Public Code 12 | //-------------------------------------------------------------------------------------------------- 13 | 14 | /// Pause execution on the core. 15 | #[inline(always)] 16 | pub fn wait_forever() -> ! { 17 | loop { 18 | asm::wfe() 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /boards/hal/src/rpi/rpi4/arch/mod.rs: -------------------------------------------------------------------------------- 1 | // mod boot; 2 | pub mod cpu_core; 3 | pub mod time; 4 | -------------------------------------------------------------------------------- /boards/hal/src/rpi/rpi4/bsp/drivers/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod common; 2 | pub mod driver_manager; 3 | pub mod emmc; 4 | pub mod gpio; 5 | pub mod uart0; 6 | // pub mod gicv2; 7 | -------------------------------------------------------------------------------- /boards/hal/src/rpi/rpi4/bsp/global.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: MIT OR Apache-2.0 2 | // 3 | // Copyright (c) 2018-2021 Andre Richter 4 | 5 | //! BSP Processor code. Top-level BSP file for the Raspberry Pi 4. 6 | 7 | use super::drivers::{emmc::EMMCController, gpio::GPIO, uart0::PL011Uart}; 8 | use super::memory_map; 9 | 10 | //-------------------------------------------------------------------------------------------------- 11 | // Global instances 12 | //-------------------------------------------------------------------------------------------------- 13 | pub static GPIO: GPIO = unsafe { GPIO::new(memory_map::map::mmio::GPIO_START) }; 14 | 15 | pub static PL011_UART: PL011Uart = 16 | unsafe { PL011Uart::new(memory_map::map::mmio::PL011_UART_START) }; 17 | 18 | pub static EMMC_CONT: EMMCController = 19 | unsafe { EMMCController::new(memory_map::map::mmio::EMMC_START) }; 20 | 21 | //-------------------------------------------------------------------------------------------------- 22 | // Public Code 23 | //-------------------------------------------------------------------------------------------------- 24 | 25 | /// Board identification. 26 | pub fn board_name() -> &'static str { 27 | { 28 | "Raspberry Pi 4" 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /boards/hal/src/rpi/rpi4/bsp/memory_map.rs: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: MIT OR Apache-2.0 2 | // 3 | // Copyright (c) 2018-2021 Andre Richter 4 | 5 | //! BSP Memory Map. 6 | 7 | //-------------------------------------------------------------------------------------------------- 8 | // Public Definitions 9 | //-------------------------------------------------------------------------------------------------- 10 | 11 | /// The board's physical memory map. 12 | #[rustfmt::skip] 13 | pub mod map { 14 | pub const END_INCLUSIVE: usize = 0xFFFF_FFFF; 15 | 16 | pub const GPIO_OFFSET: usize = 0x0020_0000; 17 | pub const UART_OFFSET: usize = 0x0020_1000; 18 | pub const EMMC_OFFSET: usize = 0x0034_0000; 19 | 20 | pub mod mmio { 21 | use super::*; 22 | 23 | pub const START: usize = 0xFE00_0000; 24 | pub const GPIO_START: usize = START + GPIO_OFFSET; 25 | pub const PL011_UART_START: usize = START + UART_OFFSET; 26 | pub const EMMC_START: usize = START + EMMC_OFFSET; 27 | pub const END_INCLUSIVE: usize = 0xFF84_FFFF; 28 | 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /boards/hal/src/rpi/rpi4/bsp/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod drivers; 2 | pub mod global; 3 | pub mod memory_map; 4 | -------------------------------------------------------------------------------- /boards/hal/src/rpi/rpi4/exception/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod asynchronous; 2 | pub mod exception; 3 | 4 | /// Kernel privilege levels. 5 | #[allow(missing_docs)] 6 | #[derive(PartialEq)] 7 | pub enum PrivilegeLevel { 8 | User, 9 | Kernel, 10 | Hypervisor, 11 | Unknown, 12 | } 13 | -------------------------------------------------------------------------------- /boards/hal/src/rpi/rpi4/log/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod console; 2 | pub mod print; 3 | -------------------------------------------------------------------------------- /boards/hal/src/rpi/rpi4/memory/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod layout; 2 | pub mod mmu; 3 | mod tt; 4 | pub mod vmm; 5 | -------------------------------------------------------------------------------- /boards/hal/src/rpi/rpi4/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod arch; 2 | pub mod bsp; 3 | pub mod exception; 4 | pub mod log; 5 | pub mod memory; 6 | 7 | mod panic_wait; 8 | mod sync; 9 | -------------------------------------------------------------------------------- /boards/hal/src/stm/mod.rs: -------------------------------------------------------------------------------- 1 | #[cfg(feature = "stm32f411")] 2 | pub mod stm32f411; 3 | 4 | #[cfg(feature = "stm32f446")] 5 | pub mod stm32f446; 6 | 7 | #[cfg(feature = "stm32f469")] 8 | pub mod stm32f469; 9 | 10 | #[cfg(feature = "stm32h723")] 11 | pub mod stm32h723; 12 | 13 | #[cfg(feature = "stm32f746")] 14 | pub mod stm32f746; 15 | 16 | #[cfg(feature = "stm32f334")] 17 | pub mod stm32f334; 18 | -------------------------------------------------------------------------------- /boards/sign_images/keygen/ecc256.der: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nihalpasham/rustBoot/d4394d383ba3758574159c6630e4c3261a6b47f1/boards/sign_images/keygen/ecc256.der -------------------------------------------------------------------------------- /boards/sign_images/keygen/pubkey.c: -------------------------------------------------------------------------------- 1 | /* Public-key file for wolfBoot, automatically generated. Do not edit. */ 2 | /* 3 | * This file has been generated and contains the public key which is 4 | * used by wolfBoot to verify the updates. 5 | */ 6 | #include 7 | 8 | const uint8_t ecc256_pub_key[64] = { 9 | 0x74, 0xBF, 0x5D, 0xE9, 0xF8, 0x69, 0x69, 0x44, 10 | 0x35, 0xAE, 0xB7, 0x39, 0x6F, 0xA1, 0x40, 0x11, 11 | 0xB6, 0xA1, 0x7F, 0x2D, 0x8A, 0x86, 0xB9, 0x58, 12 | 0xBC, 0x4A, 0x51, 0xF7, 0xF3, 0x0F, 0x23, 0x77, 13 | 0x78, 0x0E, 0x11, 0x46, 0x95, 0x3A, 0x1D, 0xDF, 14 | 0x69, 0xCD, 0x34, 0x23, 0xFE, 0x63, 0x05, 0x15, 15 | 0x30, 0x43, 0xBB, 0x9E, 0x75, 0x63, 0xE0, 0x41, 16 | 0x6A, 0x70, 0xCE, 0x16, 0x0A, 0x60, 0x2A, 0x38 17 | }; 18 | const uint32_t ecc256_pub_key_len = 64; 19 | -------------------------------------------------------------------------------- /boards/sign_images/signed_images/trailer_magic.bin: -------------------------------------------------------------------------------- 1 | BOOT -------------------------------------------------------------------------------- /boards/update/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | authors = ["Twitter: @npashi "] 3 | categories = ["embedded", "no_std", "authentication"] 4 | description = """ 5 | This is a rustBoot dependency. It allows for multi-slot partitioning of a flash device 6 | and can be used to perform power-interruptible A/B updates. 7 | """ 8 | documentation = "" 9 | edition = "2018" 10 | homepage = "" 11 | keywords = ["security", "bootloader", "firmware", "authentication", "update"] 12 | license = "MIT" 13 | name = "rustBoot-update" 14 | readme = "README.md" 15 | repository = "https://github.com/nihalpasham/rustBoot" 16 | version = "0.1.0" 17 | 18 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 19 | 20 | # makes `cargo check --all-targets` (used by Rust-Analyzer) work 21 | [lib] 22 | bench = false 23 | doctest = false 24 | test = false 25 | 26 | [dependencies] 27 | defmt = {version = "0.3.2", optional = true} 28 | rustBoot = {path = "../../rustBoot", default-features = true, features = ["mcu"]} 29 | rustBoot-hal = {path = "../hal"} 30 | 31 | [features] 32 | default = [] 33 | nrf52840 = ["rustBoot/nrf52840"] 34 | stm32f411 = ["rustBoot/stm32f411"] 35 | stm32f446 = ["rustBoot/stm32f446"] 36 | stm32f469 = ["rustBoot/stm32f469"] 37 | stm32h723 = ["rustBoot/stm32h723"] 38 | stm32f746 = ["rustBoot/stm32f746"] 39 | stm32f334 = ["rustBoot/stm32f334"] 40 | rp2040 = ["rustBoot/rp2040"] 41 | -------------------------------------------------------------------------------- /boards/update/src/hal/hal.rs: -------------------------------------------------------------------------------- 1 | use rustBoot_hal::{boot_from, preboot}; 2 | 3 | // Arch-specific code 4 | pub fn hal_preboot() { 5 | preboot() 6 | } 7 | pub fn hal_boot_from(addr: usize) -> ! { 8 | boot_from(addr) 9 | } 10 | -------------------------------------------------------------------------------- /boards/update/src/hal/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod hal; 2 | -------------------------------------------------------------------------------- /boards/update/src/lib.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![allow(warnings)] 3 | #![feature(once_cell)] 4 | 5 | pub mod hal; 6 | pub mod update; 7 | -------------------------------------------------------------------------------- /boards/update/src/update/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod update_flash; 2 | 3 | use rustBoot::flashapi::FlashApi; 4 | use rustBoot::Result; 5 | 6 | pub trait UpdateInterface: FlashApi { 7 | fn rustboot_start(self) -> !; 8 | fn update_trigger(self) -> Result<()>; 9 | fn update_success(self) -> Result<()>; 10 | } 11 | -------------------------------------------------------------------------------- /rbsigner/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | edition = "2021" 3 | name = "rbsigner" 4 | version = "0.1.0" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [dependencies] 9 | as-slice = "0.2.1" 10 | filetime = "0.2.16" 11 | log = {version = "0.4", default-features = false, features = ["std"]} 12 | p256 = {version = "0.10.1", default-features = false, features = ["ecdsa"], optional = true} 13 | rustBoot = {path = "../rustBoot"} 14 | sha2 = {version = "0.9.9", default-features = false} 15 | signature = {version = "1.3.1", default-features = false, features = ["digest-preview"]} 16 | 17 | [features] 18 | default = ["sha256", "nistp256"] 19 | nistp256 = ["p256/ecdsa", "sha256"] 20 | secp256k1 = [] 21 | sha256 = [] 22 | # secp256k1 = ["k256/ecdsa", "sha256"] 23 | # ed25519 = ["sha256"] 24 | # sha384 = [] 25 | -------------------------------------------------------------------------------- /rustBoot/examples/fit_timestamp.rs: -------------------------------------------------------------------------------- 1 | use rustBoot::dt::Reader; 2 | 3 | use std::convert::TryInto; 4 | use std::{fs, io::Read}; 5 | 6 | fn main() { 7 | let mut buf = Vec::new(); 8 | let mut file = fs::File::open( 9 | std::env::args() 10 | .nth(1) 11 | .expect("Need path to FIT Blob file as argument"), 12 | ) 13 | .unwrap(); 14 | file.read_to_end(&mut buf).unwrap(); 15 | 16 | let reader = Reader::read(buf.as_slice()).unwrap(); 17 | let root = &reader.struct_items(); 18 | let (_, node_iter) = root.path_struct_items("/").next().unwrap(); 19 | 20 | let timestamp = node_iter.get_node_property("timestamp"); 21 | println!( 22 | "\nfitImage timestamp: {:?}", 23 | u32::from_be_bytes(timestamp.unwrap().try_into().unwrap()) 24 | ); 25 | } 26 | -------------------------------------------------------------------------------- /rustBoot/examples/imx8mn-ddr4-evk.dtb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nihalpasham/rustBoot/d4394d383ba3758574159c6630e4c3261a6b47f1/rustBoot/examples/imx8mn-ddr4-evk.dtb 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pub trait FlashApi: Copy { 3 | fn flash_trailer_write( 4 | self, 5 | part: &PartDescriptor, 6 | offset: usize, 7 | data: *const u8, 8 | len: usize, 9 | ); 10 | fn flash_write( 11 | self, 12 | part: &PartDescriptor, 13 | offset: usize, 14 | data: *const u8, 15 | len: usize, 16 | ); 17 | fn flash_erase(self, part: &PartDescriptor, offset: usize, len: usize); 18 | fn flash_init(); 19 | fn flash_lock(); 20 | fn flash_unlock(); 21 | } 22 | -------------------------------------------------------------------------------- /rustBoot/src/fs/mod.rs: -------------------------------------------------------------------------------- 1 | #![allow(dead_code)] 2 | 3 | pub mod blockdevice; 4 | pub mod controller; 5 | mod fat; 6 | pub mod filesystem; 7 | mod structure; 8 | -------------------------------------------------------------------------------- /rustBoot/src/image/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod image; 2 | mod sealed; 3 | -------------------------------------------------------------------------------- /rustBoot/src/image/sealed.rs: -------------------------------------------------------------------------------- 1 | /* */ 2 | 3 | use super::image::*; 4 | /// Using the sealed-trait pattern to seal or limit possible `states` and `valid partitions` 5 | /// to the types included in this module. 6 | pub trait Sealed {} 7 | 8 | impl<'a, Part: ValidPart + Swappable, State: TypeState> Sealed for RustbootImage<'a, Part, State> {} 9 | impl Sealed for NoState {} 10 | impl Sealed for StateNew {} 11 | impl Sealed for StateSuccess {} 12 | impl Sealed for StateTesting {} 13 | impl Sealed for StateUpdating {} 14 | impl Sealed for Boot {} 15 | impl Sealed for Swap {} 16 | impl Sealed for Update {} 17 | -------------------------------------------------------------------------------- /xtask/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | authors = ["Nihal Pasham "] 3 | edition = "2018" 4 | name = "xtask" 5 | publish = false 6 | version = "0.1.0" 7 | 8 | [dependencies] 9 | anyhow = "1.0.38" 10 | rustBoot = {path = "../rustBoot"} 11 | xshell = "0.1.9" 12 | 13 | [features] 14 | nrf52840 = ["mcu", "rustBoot/nrf52840"] 15 | stm32f411 = ["mcu", "rustBoot/stm32f411"] 16 | stm32f446 = ["mcu", "rustBoot/stm32f446"] 17 | stm32f469 = ["mcu", "rustBoot/stm32f469"] 18 | stm32h723 = ["mcu", "rustBoot/stm32h723"] 19 | stm32f746 = ["mcu", "rustBoot/stm32f746"] 20 | stm32f334 = ["mcu", "rustBoot/stm32f334"] 21 | rp2040 = ["mcu", "rustBoot/rp2040"] 22 | 23 | mcu = [] --------------------------------------------------------------------------------