├── ppcaltivec.p64
├── ppcaltivec.plw
├── src
    ├── ppcaltivec.vcxproj.filters
    ├── ppcaltivec.sln
    ├── .gitignore
    ├── ppcaltivec.vcxproj
    └── main.cpp
└── readme.txt


/ppcaltivec.p64:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/nihilus/PPCAltivec/HEAD/ppcaltivec.p64


--------------------------------------------------------------------------------
/ppcaltivec.plw:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/nihilus/PPCAltivec/HEAD/ppcaltivec.plw


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/src/ppcaltivec.vcxproj.filters:
--------------------------------------------------------------------------------
 1 | <?xml version="1.0" encoding="utf-8"?>
 2 | <Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
 3 |   <ItemGroup>
 4 |     <Filter Include="Source Files">
 5 |       <UniqueIdentifier>{4FC737F1-C7A5-4376-A066-2A32D752A2FF}</UniqueIdentifier>
 6 |       <Extensions>cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx</Extensions>
 7 |     </Filter>
 8 |     <Filter Include="Header Files">
 9 |       <UniqueIdentifier>{93995380-89BD-4b04-88EB-625FBE52EBFB}</UniqueIdentifier>
10 |       <Extensions>h;hpp;hxx;hm;inl;inc;xsd</Extensions>
11 |     </Filter>
12 |     <Filter Include="Resource Files">
13 |       <UniqueIdentifier>{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}</UniqueIdentifier>
14 |       <Extensions>rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav</Extensions>
15 |     </Filter>
16 |   </ItemGroup>
17 |   <ItemGroup>
18 |     <ClCompile Include="main.cpp">
19 |       <Filter>Source Files</Filter>
20 |     </ClCompile>
21 |   </ItemGroup>
22 | </Project>


--------------------------------------------------------------------------------
/readme.txt:
--------------------------------------------------------------------------------
 1 | 
 2 | 
 3 | PPC Altivec v1.8 for IDA
 4 | 
 5 | (aka Xbox360, PS3, Gamecube, Wii support for IDA)
 6 | 
 7 | 
 8 | 
 9 | :: Overview
10 | 
11 | This plugin for IDA originally written by Dean Ashton to add support
12 | for Altivec/VMX instructions to IDAs normal PPC processor module.
13 | 
14 | Dean did the hard work in creating and setting up this plugin,
15 | and since then many other people including myself have taken advantage
16 | of the existing sourcecode to add more instructions and tweaks to
17 | support a variety of other special instructions. It now supports
18 | the extra instructions used by Xbox360, PS3, Gamecube and Wii,
19 | as well as the original Altivec and VMX instructions.
20 | 
21 | 
22 | 
23 | 
24 | :: Install
25 | 
26 | To install this, copy all files into the "IDA\plugins" directory.
27 | 
28 | If you have the Gamecube "Gekko CPU Extension" plugin by HyperIris
29 | installed you will need to remove it before using this plugin as
30 | otherwise they will clash with each other. This plugin now implements
31 | all features of the Gekko plugin anyway.
32 | 
33 | 
34 | 
35 | 


--------------------------------------------------------------------------------
/src/ppcaltivec.sln:
--------------------------------------------------------------------------------
 1 | 
 2 | Microsoft Visual Studio Solution File, Format Version 11.00
 3 | # Visual Studio 2010
 4 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "ppcaltivec", "ppcaltivec.vcxproj", "{74F130DA-94CF-4F36-AB4D-2A228C6020EC}"
 5 | EndProject
 6 | Global
 7 | 	GlobalSection(SolutionConfigurationPlatforms) = preSolution
 8 | 		Debug|Win32 = Debug|Win32
 9 | 		Debug64|Win32 = Debug64|Win32
10 | 		Release|Win32 = Release|Win32
11 | 		Release64|Win32 = Release64|Win32
12 | 	EndGlobalSection
13 | 	GlobalSection(ProjectConfigurationPlatforms) = postSolution
14 | 		{74F130DA-94CF-4F36-AB4D-2A228C6020EC}.Debug|Win32.ActiveCfg = Debug|Win32
15 | 		{74F130DA-94CF-4F36-AB4D-2A228C6020EC}.Debug|Win32.Build.0 = Debug|Win32
16 | 		{74F130DA-94CF-4F36-AB4D-2A228C6020EC}.Debug64|Win32.ActiveCfg = Debug64|Win32
17 | 		{74F130DA-94CF-4F36-AB4D-2A228C6020EC}.Debug64|Win32.Build.0 = Debug64|Win32
18 | 		{74F130DA-94CF-4F36-AB4D-2A228C6020EC}.Release|Win32.ActiveCfg = Release|Win32
19 | 		{74F130DA-94CF-4F36-AB4D-2A228C6020EC}.Release|Win32.Build.0 = Release|Win32
20 | 		{74F130DA-94CF-4F36-AB4D-2A228C6020EC}.Release64|Win32.ActiveCfg = Release64|Win32
21 | 		{74F130DA-94CF-4F36-AB4D-2A228C6020EC}.Release64|Win32.Build.0 = Release64|Win32
22 | 	EndGlobalSection
23 | 	GlobalSection(SolutionProperties) = preSolution
24 | 		HideSolutionNode = FALSE
25 | 	EndGlobalSection
26 | EndGlobal
27 | 


--------------------------------------------------------------------------------
/src/.gitignore:
--------------------------------------------------------------------------------
  1 | ## Ignore Visual Studio temporary files, build results, and
  2 | ## files generated by popular Visual Studio add-ons.
  3 | 
  4 | # User-specific files
  5 | *.suo
  6 | *.user
  7 | *.sln.docstates
  8 | 
  9 | # Build results
 10 | [Dd]ebug/
 11 | [Dd]ebugPublic/
 12 | [Rr]elease/
 13 | [Rr]eleases/
 14 | x64/
 15 | x86/
 16 | build/
 17 | bld/
 18 | [Bb]in/
 19 | [Oo]bj/
 20 | 
 21 | # Roslyn cache directories
 22 | *.ide/
 23 | 
 24 | # MSTest test Results
 25 | [Tt]est[Rr]esult*/
 26 | [Bb]uild[Ll]og.*
 27 | 
 28 | #NUNIT
 29 | *.VisualState.xml
 30 | TestResult.xml
 31 | 
 32 | # Build Results of an ATL Project
 33 | [Dd]ebugPS/
 34 | [Rr]eleasePS/
 35 | dlldata.c
 36 | 
 37 | *_i.c
 38 | *_p.c
 39 | *_i.h
 40 | *.ilk
 41 | *.meta
 42 | *.obj
 43 | *.pch
 44 | *.pdb
 45 | *.pgc
 46 | *.pgd
 47 | *.rsp
 48 | *.sbr
 49 | *.tlb
 50 | *.tli
 51 | *.tlh
 52 | *.tmp
 53 | *.tmp_proj
 54 | *.log
 55 | *.vspscc
 56 | *.vssscc
 57 | .builds
 58 | *.pidb
 59 | *.svclog
 60 | *.scc
 61 | 
 62 | # Chutzpah Test files
 63 | _Chutzpah*
 64 | 
 65 | # Visual C++ cache files
 66 | ipch/
 67 | *.aps
 68 | *.ncb
 69 | *.opensdf
 70 | *.sdf
 71 | *.cachefile
 72 | 
 73 | # Visual Studio profiler
 74 | *.psess
 75 | *.vsp
 76 | *.vspx
 77 | 
 78 | # TFS 2012 Local Workspace
 79 | $tf/
 80 | 
 81 | # Guidance Automation Toolkit
 82 | *.gpState
 83 | 
 84 | # ReSharper is a .NET coding add-in
 85 | _ReSharper*/
 86 | *.[Rr]e[Ss]harper
 87 | *.DotSettings.user
 88 | 
 89 | # JustCode is a .NET coding addin-in
 90 | .JustCode
 91 | 
 92 | # TeamCity is a build add-in
 93 | _TeamCity*
 94 | 
 95 | # DotCover is a Code Coverage Tool
 96 | *.dotCover
 97 | 
 98 | # NCrunch
 99 | _NCrunch_*
100 | .*crunch*.local.xml
101 | 
102 | # MightyMoose
103 | *.mm.*
104 | AutoTest.Net/
105 | 
106 | # Web workbench (sass)
107 | .sass-cache/
108 | 
109 | # Installshield output folder
110 | [Ee]xpress/
111 | 
112 | # DocProject is a documentation generator add-in
113 | DocProject/buildhelp/
114 | DocProject/Help/*.HxT
115 | DocProject/Help/*.HxC
116 | DocProject/Help/*.hhc
117 | DocProject/Help/*.hhk
118 | DocProject/Help/*.hhp
119 | DocProject/Help/Html2
120 | DocProject/Help/html
121 | 
122 | # Click-Once directory
123 | publish/
124 | 
125 | # Publish Web Output
126 | *.[Pp]ublish.xml
127 | *.azurePubxml
128 | # TODO: Comment the next line if you want to checkin your web deploy settings 
129 | # but database connection strings (with potential passwords) will be unencrypted
130 | *.pubxml
131 | *.publishproj
132 | 
133 | # NuGet Packages
134 | *.nupkg
135 | # The packages folder can be ignored because of Package Restore
136 | **/packages/*
137 | # except build/, which is used as an MSBuild target.
138 | !**/packages/build/
139 | # If using the old MSBuild-Integrated Package Restore, uncomment this:
140 | #!**/packages/repositories.config
141 | 
142 | # Windows Azure Build Output
143 | csx/
144 | *.build.csdef
145 | 
146 | # Windows Store app package directory
147 | AppPackages/
148 | 
149 | # Others
150 | sql/
151 | *.Cache
152 | ClientBin/
153 | [Ss]tyle[Cc]op.*
154 | ~$*
155 | *~
156 | *.dbmdl
157 | *.dbproj.schemaview
158 | *.pfx
159 | *.publishsettings
160 | node_modules/
161 | 
162 | # RIA/Silverlight projects
163 | Generated_Code/
164 | 
165 | # Backup & report files from converting an old project file
166 | # to a newer Visual Studio version. Backup files are not needed,
167 | # because we have git ;-)
168 | _UpgradeReport_Files/
169 | Backup*/
170 | UpgradeLog*.XML
171 | UpgradeLog*.htm
172 | 
173 | # SQL Server files
174 | *.mdf
175 | *.ldf
176 | 
177 | # Business Intelligence projects
178 | *.rdl.data
179 | *.bim.layout
180 | *.bim_*.settings
181 | 
182 | # Microsoft Fakes
183 | FakesAssemblies/
184 | 


--------------------------------------------------------------------------------
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104 |       <PreprocessorDefinitions>WIN32;_DEBUG;_WINDOWS;_USRDLL;_CRT_SECURE_NO_WARNINGS;__NT__;__IDP__;%(PreprocessorDefinitions)</PreprocessorDefinitions>
105 |       <MinimalRebuild>true</MinimalRebuild>
106 |       <BasicRuntimeChecks>EnableFastChecks</BasicRuntimeChecks>
107 |       <RuntimeLibrary>MultiThreadedDebug</RuntimeLibrary>
108 |       <PrecompiledHeader>
109 |       </PrecompiledHeader>
110 |       <WarningLevel>Level3</WarningLevel>
111 |       <DebugInformationFormat>EditAndContinue</DebugInformationFormat>
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120 |       <AdditionalOptions>/EXPORT:PLUGIN %(AdditionalOptions)</AdditionalOptions>
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193 |       <AdditionalLibraryDirectories>%(AdditionalLibraryDirectories)</AdditionalLibraryDirectories>
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205 |   </ItemDefinitionGroup>
206 |   <ItemGroup>
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209 |   <Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
210 |   <ImportGroup Label="ExtensionTargets">
211 |   </ImportGroup>
212 | </Project>


--------------------------------------------------------------------------------
/src/main.cpp:
--------------------------------------------------------------------------------
   1 | /**************************************************************************************************
   2 | *
   3 | *	$Header::                                                                                     $
   4 | *
   5 | *	PowerPC Altivec/VMX Extension Module
   6 | *
   7 | *	The PowerPC processor module in IDA Pro 4.8 does not handle Altivec/VMX instructions. Many 
   8 | *	well-known PowerPC implementations include support for Altivec (such as the Apple G4/G5 range, 
   9 | *	or the majority of next generation game consoles). Fortunately IDA Pro supports the concept of
  10 | *	extension modules that can add support for non-standard instructions, so this extension adds 
  11 | *	support for the Altivec instruction set.
  12 | *
  13 | *
  14 | *	INSTALLATION
  15 | *	------------
  16 | *
  17 | *	Place the two processor extension modules (ppcAltivec.plw and ppcAltivec.p64) within your
  18 | *	IDA Pro 'plugins' directory. By default the plugin is active when dealing with PPC code, but
  19 | *	you can disable/re-enable the plugin by using the entry in the Edit/Plugins menu. If you want 
  20 | *	the plugin to be disabled on load, you will have to edit this source code. Change the value of
  21 | *	g_HookState to 'kDisabled' and rebuild.  
  22 | *
  23 | *
  24 | *	NOTES
  25 | *	-----
  26 | *	
  27 | *	The versions of ppc.w32 and ppc64.w64 that were in initial distributions of IDA Pro 4.8 contain
  28 | *	a flaw that will trigger an illegal read of memory when used with this extension. If you happen
  29 | *	to encounter crashes in these modules, I would recommend that you contact Data Rescue, 
  30 | *	specifically Ilfak Guilfanov - ig@datarescue.com - to obtaining corrected versions of these
  31 | *	modules, as I did.
  32 | *
  33 | *
  34 | *	CHANGES
  35 | *	-------
  36 | *
  37 | *	27.03.05	Dean		V1.0	Created
  38 | *
  39 | *	14.05.05	Dean		V1.1	Correction to operand register number extraction.
  40 | *									Correction to operand order for vmaddfp.
  41 | *									Now handles initial analysis without any additional hassle. 
  42 | *									Added support for Altivec opcodes with 4 parameters.
  43 | *
  44 | *	22.05.05	Dean		V1.2	Added support for auto comments.
  45 | *
  46 | *	26.09.05	Dean		V1.3	Support for IDA Pro 4.9
  47 | *
  48 | *	07.12.10	xorloser	V1.8	Support for Gekko instructions merged from the Gekko
  49 | *									extension module created by HyperIris. Also incldued
  50 | *									support for SPRG names for PS3 as added by Tridentsx.
  51 | *
  52 | ***************************************************************************************************/
  53 | 
  54 | #define	PPCALTIVEC_VERSION	"V1.8"
  55 | 
  56 | /***************************************************************************************************
  57 | *
  58 | *	Strings required for IDA Pro's PLUGIN descriptor block
  59 | *
  60 | ***************************************************************************************************/
  61 | 
  62 | char	g_pluginName[]	=	"PowerPC Altivec Extension " PPCALTIVEC_VERSION " with support for VMX128, Xbox360(Xenon), PS3(CellBE) and GC/WII(Gekko).";
  63 | char	g_pluginHelp[]	=	"This plugin enables recognition of many extra processor specific instructions\n"
  64 | 							"when using IDA Pro's PowerPC processor module.\n"
  65 | 							"The added instructions support Altivec, VMX128, Xbox360(Xenon), PS3(CellBE) and GC/WII(Gekko).\n";
  66 | 
  67 | 
  68 | // SDK 4.8's "pro.h" (line 718) has a signed/unsigned mismatch, so we disable this warning..
  69 | #pragma warning( disable:4018 )		
  70 | 
  71 | #include <ida.hpp>
  72 | #include <idp.hpp>
  73 | #include <name.hpp>
  74 | #include <bytes.hpp>
  75 | #include <loader.hpp>
  76 | #include <kernwin.hpp>
  77 | 
  78 | /***************************************************************************************************
  79 | *
  80 | *	Data needed to maintain plugin state
  81 | *
  82 | ***************************************************************************************************/
  83 | 
  84 | enum	HookState
  85 | {
  86 | 	kDefault,
  87 | 	kEnabled,
  88 | 	kDisabled,
  89 | };
  90 | 
  91 | static HookState	g_HookState = kEnabled;
  92 | static netnode		g_AltivecNode;
  93 | static const char	g_AltivecNodeName[] = "$ PowerPC Altivec Extension Parameters";
  94 | 
  95 | 
  96 | 
  97 | // -------------------------------------------------------------------------------------------------
  98 | // Operand identifiers (they map into g_altivecOperands array)
  99 | 
 100 | enum	altivec_operand_id
 101 | {	
 102 | 	NO_OPERAND,
 103 | 	VA,
 104 | 	VB,
 105 | 	VC,
 106 | 	VD,		VS = VD,
 107 | 	SIMM,
 108 | 	UIMM,
 109 | 	SHB,
 110 | 	RA,
 111 | 	RB,
 112 | 	STRM,
 113 | 
 114 | 	// Takires: Added operand identifiers
 115 | 	RS,		RT = RS,
 116 | 	L15,
 117 | 	L9_10,	LS = L9_10,
 118 | 	L10,	L = L10,
 119 | 	VD128,	VS128 = VD128,
 120 | 	CRM,
 121 | 	VA128,
 122 | 	VB128,
 123 | 	VC128,
 124 | 	VPERM128,
 125 | 	VD3D0,
 126 | 	VD3D1,
 127 | 	VD3D2,
 128 | 	RA0,
 129 | 
 130 | //	LEV,
 131 | //	FL1,
 132 | //	FL2,
 133 | //	SV,
 134 | //	SVC_LEV,
 135 | 	SPR,
 136 | 	
 137 | 	// gekko specific
 138 | 	FA,
 139 | 	FB,
 140 | 	FC,
 141 | 	FD,
 142 | 	FS = FD,
 143 | 	
 144 | 	crfD,
 145 | 
 146 | 	WB,
 147 | 	IB,
 148 | 	WC,
 149 | 	IC,
 150 | //	D,
 151 | 
 152 | //	RA,
 153 | //	RB,
 154 | 	DRA,
 155 | 	DRB,
 156 | };
 157 | 
 158 | // -------------------------------------------------------------------------------------------------
 159 | // Structure used to define an operand 
 160 | 
 161 | struct	cbea_sprg
 162 | {
 163 | 	int					sprg;
 164 | 	char*				shortName;
 165 | 	char*				comment;
 166 | };
 167 | 
 168 | cbea_sprg g_cbeaSprgs[] =
 169 | {
 170 | 	{	1023, "PIR",				"Processor Identification Register" },
 171 | 	{	1022, "BP_VR",				"CBEA-Compliant Processor Version Register" },
 172 | 	{	1017, "HID6",				"Hardware Implementation Register 6" },
 173 | 	{	1015, "DABRX",				"Data Address Breakpoint Register Extension" },
 174 | 	{	1013, "DABR",				"Data Address Breakpoint Register" },
 175 | 	{	1012, "HID4",				"Hardware Implementation Register 4" },
 176 | 	{	1009, "HID1",				"Hardware Implementation Register 1" },
 177 | 	{	1008, "HID0",				"Hardware Implementation Register 0"},
 178 | 	{	981, "ICIDR",				"Instruction Class ID Register 1" },
 179 | 	{	980, "IRMR1",				"Instruction Range Mask Register 1" },
 180 | 	{	979, "IRSR1",				"Instruction Range Start Register 1" },
 181 | 	{	978, "ICIDR0",				"Instruction Class ID Register 0" },
 182 | 	{	977, "IRMR0",				"Instruction Range Mask Register 0" },
 183 | 	{	976, "IRSR0",				"Instruction Range Start Register 0" },
 184 | 	{	957, "DCIDR1",				"Data Class ID Register 1" },
 185 | 	{	956, "DRMR1",				"Data Range Mask Register 1" },
 186 | 	{	955, "DRSR1",				"Data Range Start Register 1" },
 187 | 	{	954, "DCIDR0",				"Data Class ID Register 0" },
 188 | 	{	953, "DRMR0",				"Data Range Mask Register 0" },
 189 | 	{	952, "DRSR0",				"Data Range Start Register 0" },
 190 | 	{	951, "PPE_TLB_RMT",			"PPE Translation Lookaside Buffer RMT Register" },
 191 | 	{	949, "PPE_TLB_RPN",			"PPE Translation Lookaside Buffer Real-Page Number" },
 192 | 	{	948, "PPE_TLB_VPN",			"PPE Translation Lookaside Buffer Virtual-Page Number" },
 193 | 	{	947, "PPE_TLB_Index",		"PPE Translation Lookaside Buffer Index Register" },
 194 | 	{	946, "PPE_TLB_Index_Hint",	"PPE Translation Lookaside Buffer Index Hint Register" },
 195 | 	{	922, "TTR",					"Thread Switch Timeout Register" },
 196 | 	{	921, "TSCR",				"Thread Switch Control Register" },
 197 | 	{	897, "TSRR",				"Thread Status Register Remote" },
 198 | 	{	896, "TSRL",				"Thread Status Register Local" },
 199 | 	{	319, "LPIDR",				"Logical Partition Identity Register" },
 200 | 	{	318, "LPCR",				"Logical Partition Control Register" },
 201 | 	{	315, "HSRR1",				"Hypervisor Machine Status Save/Restore Register 1" },
 202 | 	{	314, "HSRR0",				"Hypervisor Machine Status Save/Restore Register 0" },
 203 | 	{	313, "HRMOR",				"Hypervisor Real Mode Offset Register" },
 204 | 	{	312, "RMOR",				"Real Mode Offset Register" },
 205 | 	{	310, "HDEC",				"Hypervisor Decrementer Register" },
 206 | 	{	305, "HSPRG1",				"Hypervisor Software Use Special Purpose Register 1" },
 207 | 	{	304, "HSPRG0",				"Hypervisor Software Use Special Purpose Register 0" },
 208 | 	{	287, "PVR",					"PPE Processor Version Register" },
 209 | 	{	285, "TBU",					"Time Base Upper Register - Write Only" },
 210 | 	{	284, "TBL",					"Time Base Lower Register - Write Only" },
 211 | 	{	275, "SPRG3",				"Software Use Special Purpose Register 3" },
 212 | 	{	274, "SPRG2",				"Software Use Special Purpose Register 2" },
 213 | 	{	273, "SPRG1",				"Software Use Special Purpose Register 1" },
 214 | 	{	272, "SPRG0",				"Software Use Special Purpose Register 0" },
 215 | 	{	269, "TBU",					"Time Base Upper Register - Read Only" },
 216 | 	{	268, "TB",					"Time Base Register - Read Only" },
 217 | 	{	259, "SPRG3",				"Software Use Special Purpose Register 3" },
 218 | 	{	256, "VRSAVE",				"VXU Register Save" },
 219 | 	{	152, "CTRL",				"Control Register Write" },
 220 | 	{	136, "CTRL",				"Control Register Read" },
 221 | 	{	29, "ACCR",					"Address Compare Control Register" },
 222 | 	{	27, "SRR1",					"Machine Status Save/Restore Register 1" },
 223 | 	{	26, "SRR0",					"Machine Status Save/Restore Register 0" },
 224 | 	{	25, "SDR1",					"Storage Description Register 1" },
 225 | 	{	22, "DEC",					"Decrementer Register" },
 226 | 	{	19, "DAR",					"Data Address Register" },
 227 | 	{	18, "DSISR",				"Data Storage Interrupt Status Register" },
 228 | 	{	9, "CTR",					"Count Register" },
 229 | 	{	8, "LR",					"Link Register" },
 230 | 	{	1, "XER",					"Fixed-Point exception Register" },
 231 | };
 232 | 
 233 | struct	altivec_operand
 234 | {
 235 | 	int					bits;
 236 | 	int					shift;
 237 | };
 238 | 
 239 | altivec_operand	g_altivecOperands[] =  // {Length, Start bit}
 240 | {
 241 | 	{ 0, 0		},	// No Operand
 242 | 	{ 5, 16		},	// VA
 243 | 	{ 5, 11		},	// VB
 244 | 	{ 5, 6		},	// VC
 245 | 	{ 5, 21		},	// VD / VS
 246 | 	{ 5, 16		},	// SIMM
 247 | 	{ 5, 16		},	// UIMM
 248 | 	{ 4, 6		},	// SHB
 249 | 	{ 5, 16		},	// RA
 250 | 	{ 5, 11		},	// RB
 251 | 	{ 2, 21		},	// STRM
 252 | 
 253 | 	// Takires: Added operands
 254 | 	{ 5, 21		},	// RS / RT
 255 | 	{ 1, 16		},	// L15
 256 | 	{ 2, 21		},	// L9_10
 257 | 	{ 1, 21		},	// L10
 258 | 	{ 0, 0		},	// VD128 / VS128
 259 | 	{ 8, 12		},	// CRM
 260 | 	{ 0, 0		},	// VA128
 261 | 	{ 0, 0		},	// VB128
 262 | 	{ 3, 8		},	// VC128
 263 | 	{ 0, 0		},	// VPERM128
 264 | 	{ 3, 18		},	// VD3D0
 265 | 	{ 2, 16		},	// VD3D1
 266 | 	{ 2, 6		},	// VD3D2
 267 | 	{ 5, 16		},	// RA0
 268 | //	{ 7, 5      },	// LEV
 269 | //	{ 4, 12     },	// FL1
 270 | //	{ 3, 2      },	// FL2
 271 | //	{ 14, 2     },	// SV
 272 | //	{ 7, 5      },	// SVC_LEV
 273 | 	{ 10,11     },	// SPR
 274 | 
 275 | 
 276 | 	// gekko specific
 277 | 	{ 5, 16	},	// FA
 278 | 	{ 5, 11	},	// FB
 279 | 	{ 5, 6	},	// FC
 280 | 	{ 5, 21	},	// FD/FS
 281 | 
 282 | 	{ 3, 23	},	//crfD,
 283 | 
 284 | 
 285 | 	{ 1, 16	},	//WB,
 286 | 	{ 3, 12	},	//IB,
 287 | 	{ 1, 10	},	//WC,
 288 | 	{ 3, 7	},	//IC,
 289 | //	{ 12, 0	},	//D,
 290 | 
 291 | //	{ 5, 16	},	// RA
 292 | //	{ 5, 11	},	// RB
 293 | 	{ 5, 16 },//DRA,
 294 | 	{ 5, 11 },//DRB,
 295 | };
 296 | 
 297 | 
 298 | 
 299 | 
 300 | // -------------------------------------------------------------------------------------------------
 301 | // Macros used to define opcode table
 302 | 
 303 | #define OP(x)				((((unsigned long)(x)) & 0x3f) << 26)
 304 | #define OP_MASK				OP(0x3f)
 305 | #define SC(op, sa, lk)		(OP(op)  | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
 306 | #define SC_MASK				(OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
 307 | #define VX(op, xop)			(OP(op)  | (((unsigned long)(xop)) & 0x7ff))
 308 | #define VX_MASK				VX(0x3f, 0x7ff)
 309 | #define VXR(op, xop, rc)	(OP(op)  | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
 310 | #define VXR_MASK			VXR(0x3f, 0x3ff, 1)
 311 | #define X(op, xop)			(OP(op)  | ((((unsigned long)(xop)) & 0x3ff) << 1))
 312 | #define X_MASK				XRC (0x3f, 0x3ff, 1)
 313 | #define RA_MASK				(0x1f << 16)
 314 | #define RB_MASK				(0x1f << 11)
 315 | #define RT_MASK				(0x1f << 21)
 316 | #define VXA(op, xop)		(OP(op)  | (((unsigned long)(xop)) & 0x03f))
 317 | #define VXA_MASK			VXA(0x3f, 0x3f)
 318 | #define XDSS(op, xop, a)	(X((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
 319 | #define XDSS_MASK			XDSS(0x3f, 0x3ff, 1)
 320 | 
 321 | #define VX128(op, xop)		(OP(op) | (((unsigned long)(xop)) & 0x3d0))
 322 | #define VX128_MASK			VX(0x3f, 0x3d0)
 323 | #define VX128_1(op, xop)	(OP(op) | (((unsigned long)(xop)) & 0x7f3))
 324 | #define VX128_1_MASK		VX(0x3f, 0x7f3)
 325 | #define VX128_2(op, xop)	(OP(op) | (((unsigned long)(xop)) & 0x210))
 326 | #define VX128_2_MASK		VX(0x3f, 0x210)
 327 | #define VX128_3(op, xop)	(OP(op) | (((unsigned long)(xop)) & 0x7f0))
 328 | #define VX128_3_MASK		VX(0x3f, 0x7f0)
 329 | #define VX128_P(op, xop)	(OP(op) | (((unsigned long)(xop)) & 0x630))
 330 | #define VX128_P_MASK		VX(0x3f, 0x630)
 331 | #define VX128_4(op, xop)	(OP(op) | (((unsigned long)(xop)) & 0x730))
 332 | #define VX128_4_MASK		VX(0x3f, 0x730)
 333 | #define VX128_5(op, xop)	(OP(op) | (((unsigned long)(xop)) & 0x10))
 334 | #define VX128_5_MASK		VX(0x3f, 0x10)
 335 | 
 336 | #define XFX(op, xop, a)		(X(op, xop) | ((((unsigned long)(a)) & 1) << 20))
 337 | #define XFX_MASK			XFX(0x3f, 0x3ff, 1)
 338 | #define XRT(op, xop, rt)	(X(op, xop) | ((((unsigned long)(rt)) & 0x1F) << 21))
 339 | #define XRT_MASK			XRT(0x3f, 0x3ff, 0x1f)
 340 | #define XRA(op, xop, ra)	(X(op, xop) | ((((unsigned long)(ra)) & 0x1F) << 16))
 341 | #define XRA_MASK			(X_MASK | RA_MASK)
 342 | #define XRC(op, xop, rc)	(X((op), (xop)) | ((rc) & 1))
 343 | #define XRARB_MASK			(X_MASK | RA_MASK | RB_MASK)
 344 | #define XRLARB_MASK			(XRARB_MASK & ~((unsigned long) 1 << 16))
 345 | #define XSYNC(op, xop, l)	(X(op, xop) | ((((unsigned long)(l)) & 3) << 21))
 346 | #define XRTRA_MASK			(X_MASK | RT_MASK | RA_MASK)
 347 | #define XRTLRA_MASK			(XRTRA_MASK & ~((unsigned long) 1 << 21))
 348 | 
 349 | 
 350 | // gekko specific
 351 | 
 352 | #define OPS(op, xop)		(OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
 353 | #define OPSC(op, xop, rc)	(OPS ((op), (xop)) | ((rc) & 1))
 354 | //#define OPSC(op, xop, rc)	(OPS ((op), (xop)) | rc)
 355 | #define OPS_MASK			OPSC (0x3f, 0x1f, 1)
 356 | #define OPS_MASK_DOT		OPSC (0x3f, 0x1f, 1)
 357 | 
 358 | #define OPM(op, xop)		(OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1))
 359 | #define OPMC(op, xop, rc)	(OPM ((op), (xop)) | ((rc) & 1))
 360 | #define OPM_MASK			OPMC (0x3f, 0x3f, 0)
 361 | 
 362 | #define OPL(op, xop)		(OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
 363 | #define OPLC(op, xop, rc)	(OPL ((op), (xop)) | ((rc) & 1))
 364 | //#define OPLC(op, xop, rc)	(OPL ((op), (xop)) | rc)
 365 | #define OPL_MASK			OPLC (0x3f, 0x3ff, 1)
 366 | #define OPL_MASK_DOT		OPLC (0x3f, 0x3ff, 1)
 367 | 
 368 | 
 369 | 
 370 | // -------------------------------------------------------------------------------------------------
 371 | // Opcode identifiers (they map into g_altivecOpcodes array)
 372 | 
 373 | enum altivec_insn_type_t
 374 | {
 375 | 	altivec_insn_start = CUSTOM_CMD_ITYPE,
 376 | 
 377 | 	altivec_lvebx = altivec_insn_start,
 378 | 	altivec_lvehx,
 379 | 	altivec_lvewx,
 380 | 	altivec_lvsl,
 381 | 	altivec_lvsr,
 382 | 	altivec_lvx,
 383 | 	altivec_lvxl,
 384 | 	altivec_stvebx,
 385 | 	altivec_stvehx,
 386 | 	altivec_stvewx,
 387 | 	altivec_stvx,
 388 | 	altivec_stvxl,
 389 | 	altivec_dst,	
 390 | 	altivec_dstt,	
 391 | 	altivec_dstst,	
 392 | 	altivec_dststt,	
 393 | 	altivec_dss,	
 394 | 	altivec_dssall,	
 395 | 	altivec_mfvscr,
 396 | 	altivec_mtvscr,
 397 | 	altivec_vaddcuw,	
 398 | 	altivec_vaddfp,
 399 | 	altivec_vaddsbs,
 400 | 	altivec_vaddshs,
 401 | 	altivec_vaddsws,
 402 | 	altivec_vaddubm,
 403 | 	altivec_vaddubs,
 404 | 	altivec_vadduhm,
 405 | 	altivec_vadduhs,
 406 | 	altivec_vadduwm,
 407 | 	altivec_vadduws,
 408 | 	altivec_vand,
 409 | 	altivec_vandc,
 410 | 	altivec_vavgsb,
 411 | 	altivec_vavgsh,
 412 | 	altivec_vavgsw,
 413 | 	altivec_vavgub,
 414 | 	altivec_vavguh,
 415 | 	altivec_vavguw,
 416 | 	altivec_vcfsx,
 417 | 	altivec_vcfux,
 418 | 	altivec_vcmpbfp,
 419 | 	altivec_vcmpbfp_c,
 420 | 	altivec_vcmpeqfp,
 421 | 	altivec_vcmpeqfp_c,
 422 | 	altivec_vcmpequb,
 423 | 	altivec_vcmpequb_c,
 424 | 	altivec_vcmpequh,
 425 | 	altivec_vcmpequh_c,
 426 | 	altivec_vcmpequw,
 427 | 	altivec_vcmpequw_c,
 428 | 	altivec_vcmpgefp,
 429 | 	altivec_vcmpgefp_c,
 430 | 	altivec_vcmpgtfp,
 431 | 	altivec_vcmpgtfp_c,
 432 | 	altivec_vcmpgtsb,
 433 | 	altivec_vcmpgtsb_c,
 434 | 	altivec_vcmpgtsh,
 435 | 	altivec_vcmpgtsh_c,
 436 | 	altivec_vcmpgtsw,
 437 | 	altivec_vcmpgtsw_c,
 438 | 	altivec_vcmpgtub,
 439 | 	altivec_vcmpgtub_c,
 440 | 	altivec_vcmpgtuh,
 441 | 	altivec_vcmpgtuh_c,
 442 | 	altivec_vcmpgtuw,
 443 | 	altivec_vcmpgtuw_c,
 444 | 	altivec_vctsxs,
 445 | 	altivec_vctuxs,
 446 | 	altivec_vexptefp,
 447 | 	altivec_vlogefp,
 448 | 	altivec_vmaddfp,
 449 | 	altivec_vmaxfp,
 450 | 	altivec_vmaxsb,
 451 | 	altivec_vmaxsh,
 452 | 	altivec_vmaxsw,
 453 | 	altivec_vmaxub,
 454 | 	altivec_vmaxuh,
 455 | 	altivec_vmaxuw,
 456 | 	altivec_vmhaddshs,
 457 | 	altivec_vmhraddshs,
 458 | 	altivec_vminfp,
 459 | 	altivec_vminsb,
 460 | 	altivec_vminsh,
 461 | 	altivec_vminsw,
 462 | 	altivec_vminub,
 463 | 	altivec_vminuh,
 464 | 	altivec_vminuw,
 465 | 	altivec_vmladduhm,
 466 | 	altivec_vmrghb,
 467 | 	altivec_vmrghh,
 468 | 	altivec_vmrghw,
 469 | 	altivec_vmrglb,
 470 | 	altivec_vmrglh,
 471 | 	altivec_vmrglw,
 472 | 	altivec_vmsummbm,
 473 | 	altivec_vmsumshm,
 474 | 	altivec_vmsumshs,
 475 | 	altivec_vmsumubm,
 476 | 	altivec_vmsumuhm,
 477 | 	altivec_vmsumuhs,
 478 | 	altivec_vmulesb,
 479 | 	altivec_vmulesh,
 480 | 	altivec_vmuleub,
 481 | 	altivec_vmuleuh,
 482 | 	altivec_vmulosb,
 483 | 	altivec_vmulosh,
 484 | 	altivec_vmuloub,
 485 | 	altivec_vmulouh,
 486 | 	altivec_vnmsubfp,
 487 | 	altivec_vnor, 
 488 | 	altivec_vor,
 489 | 	altivec_vperm,
 490 | 	altivec_vpkpx,
 491 | 	altivec_vpkshss,
 492 | 	altivec_vpkshus,
 493 | 	altivec_vpkswss,
 494 | 	altivec_vpkswus,
 495 | 	altivec_vpkuhum,
 496 | 	altivec_vpkuhus,
 497 | 	altivec_vpkuwum,
 498 | 	altivec_vpkuwus,
 499 | 	altivec_vrefp,
 500 | 	altivec_vrfim,
 501 | 	altivec_vrfin,
 502 | 	altivec_vrfip,
 503 | 	altivec_vrfiz,
 504 | 	altivec_vrlb, 
 505 | 	altivec_vrlh,
 506 | 	altivec_vrlw, 
 507 | 	altivec_vrsqrtefp,
 508 | 	altivec_vsel,
 509 | 	altivec_vsl,
 510 | 	altivec_vslb, 
 511 | 	altivec_vsldoi,
 512 | 	altivec_vslh, 
 513 | 	altivec_vslo, 
 514 | 	altivec_vslw, 
 515 | 	altivec_vspltb,
 516 | 	altivec_vsplth,
 517 | 	altivec_vspltisb,
 518 | 	altivec_vspltish,
 519 | 	altivec_vspltisw,
 520 | 	altivec_vspltw,
 521 | 	altivec_vsr,
 522 | 	altivec_vsrab,
 523 | 	altivec_vsrah,
 524 | 	altivec_vsraw,
 525 | 	altivec_vsrb,
 526 | 	altivec_vsrh, 
 527 | 	altivec_vsro, 
 528 | 	altivec_vsrw,
 529 | 	altivec_vsubcuw,
 530 | 	altivec_vsubfp,
 531 | 	altivec_vsubsbs,
 532 | 	altivec_vsubshs,
 533 | 	altivec_vsubsws,
 534 | 	altivec_vsububm,
 535 | 	altivec_vsububs,
 536 | 	altivec_vsubuhm,
 537 | 	altivec_vsubuhs,
 538 | 	altivec_vsubuwm,
 539 | 	altivec_vsubuws,
 540 | 	altivec_vsumsws,
 541 | 	altivec_vsum2sws,
 542 | 	altivec_vsum4sbs,
 543 | 	altivec_vsum4shs,
 544 | 	altivec_vsum4ubs,
 545 | 	altivec_vupkhpx,
 546 | 	altivec_vupkhsb,
 547 | 	altivec_vupkhsh,
 548 | 	altivec_vupklpx,
 549 | 	altivec_vupklsb,
 550 | 	altivec_vupklsh,
 551 | 	altivec_vxor,
 552 | 
 553 | 	// Takires: Added opcode identifiers
 554 | 	vmx128_vsldoi128,
 555 | 	vmx128_lvsl128,
 556 | 	vmx128_lvsr128,
 557 | 	vmx128_lvewx128,
 558 | 	vmx128_lvx128,
 559 | 	vmx128_stvewx128,
 560 | 	vmx128_stvx128,
 561 | 	vmx128_lvxl128,
 562 | 	vmx128_stvxl128,
 563 | 	vmx128_lvlx128,
 564 | 	vmx128_lvrx128,
 565 | 	vmx128_stvlx128,
 566 | 	vmx128_stvrx128,
 567 | 	vmx128_lvlxl128,
 568 | 	vmx128_lvrxl128,
 569 | 	vmx128_stvlxl128,
 570 | 	vmx128_stvrxl128,
 571 | 	vmx128_vperm128,
 572 | 	vmx128_vaddfp128,
 573 | 	vmx128_vsubfp128,
 574 | 	vmx128_vmulfp128,
 575 | 	vmx128_vmaddfp128,
 576 | 	vmx128_vmaddcfp128,
 577 | 	vmx128_vnmsubfp128,
 578 | 	vmx128_vmsum3fp128,
 579 | 	vmx128_vmsum4fp128,
 580 | 	vmx128_vpkshss128,
 581 | 	vmx128_vand128,
 582 | 	vmx128_vpkshus128,
 583 | 	vmx128_vandc128,
 584 | 	vmx128_vpkswss128,
 585 | 	vmx128_vnor128,
 586 | 	vmx128_vpkswus128,
 587 | 	vmx128_vor128,
 588 | 	vmx128_vpkuhum128,
 589 | 	vmx128_vxor128,
 590 | 	vmx128_vpkuhus128,
 591 | 	vmx128_vsel128,
 592 | 	vmx128_vpkuwum128,
 593 | 	vmx128_vslo128,
 594 | 	vmx128_vpkuwus128,
 595 | 	vmx128_vsro128,
 596 | 
 597 | 	vmx128_vpermwi128,
 598 | 	vmx128_vcfpsxws128,
 599 | 	vmx128_vcfpuxws128,
 600 | 	vmx128_vcsxwfp128,
 601 | 	vmx128_vcuxwfp128,
 602 | 	vmx128_vrfim128,
 603 | 	vmx128_vrfin128,
 604 | 	vmx128_vrfip128,
 605 | 	vmx128_vrfiz128,
 606 | 	vmx128_vpkd3d128,
 607 | 	vmx128_vrefp128,
 608 | 	vmx128_vrsqrtefp128,
 609 | 	vmx128_vexptefp128,
 610 | 	vmx128_vlogefp128,
 611 | 	vmx128_vrlimi128,
 612 | 	vmx128_vspltw128,
 613 | 	vmx128_vspltisw128,
 614 | 	vmx128_vupkd3d128,
 615 | 	vmx128_vcmpeqfp128,
 616 | 	vmx128_vcmpeqfp128c,
 617 | 	vmx128_vrlw128,
 618 | 	vmx128_vcmpgefp128,
 619 | 	vmx128_vcmpgefp128c,
 620 | 	vmx128_vslw128,
 621 | 	vmx128_vcmpgtfp128,
 622 | 	vmx128_vcmpgtfp128c,
 623 | 	vmx128_vsraw128,
 624 | 	vmx128_vcmpbfp128,
 625 | 	vmx128_vcmpbfp128c,
 626 | 	vmx128_vsrw128,
 627 | 	vmx128_vcmpequw128,
 628 | 	vmx128_vcmpequw128c,
 629 | 	vmx128_vmaxfp128,
 630 | 	vmx128_vminfp128,
 631 | 	vmx128_vmrghw128,
 632 | 	vmx128_vmrglw128,
 633 | 	vmx128_vupkhsb128,
 634 | 	vmx128_vupklsb128,
 635 | 
 636 | 	vmx128_lvlx,
 637 | 	vmx128_lvlxl,
 638 | 	vmx128_lvrx,
 639 | 	vmx128_lvrxl,
 640 | 	vmx128_stvlx,
 641 | 	vmx128_stvlxl,
 642 | 	vmx128_stvrx,
 643 | 	vmx128_stvrxl,
 644 | 
 645 | 	std_attn,
 646 | 	std_dbcz128,
 647 | 	std_hvsc,
 648 | 	std_mtspr, // To decode the SPR name
 649 | 	std_mfspr, // To decode the SPR name
 650 | 	std_ldbrx,
 651 | 	std_mfocrf,
 652 | 	std_mtmsr,
 653 | 	std_mtmsrd,
 654 | 	std_mtocrf,
 655 | 	std_slbmte,
 656 | 	std_stdbrx,
 657 | //	std_svc,
 658 | //	std_svcl,
 659 | //	std_svca,
 660 | //	std_svcla,
 661 | 	std_lwsync,
 662 | 	std_ptesync,
 663 | 	std_sync,
 664 | 	std_tlbiel,
 665 | 	std_tlbie,
 666 | 	std_tlbi,
 667 | 	std_slbie,
 668 | 	
 669 | 	spec_callthru,
 670 | 	spec_cctpl,
 671 | 	spec_cctpm,
 672 | 	spec_cctph,
 673 | 	spec_db8cyc,
 674 | 	spec_db10cyc,
 675 | 	spec_db12cyc,
 676 | 	spec_db16cyc,
 677 | 	spec_02002000,
 678 | 	
 679 | 	
 680 | 	// gekko specific
 681 | 	gekko_psq_lx,
 682 | 	gekko_psq_stx,
 683 | 	gekko_psq_lux,
 684 | 	gekko_psq_stux,
 685 | 	gekko_psq_l,
 686 | 	gekko_psq_lu,
 687 | 	gekko_psq_st,
 688 | 	gekko_psq_stu,
 689 | 
 690 | 	gekko_ps_div,
 691 | 	gekko_ps_div_dot,
 692 | 	gekko_ps_sub,
 693 | 	gekko_ps_sub_dot,
 694 | 	gekko_ps_add,
 695 | 	gekko_ps_add_dot,
 696 | 	gekko_ps_sel,
 697 | 	gekko_ps_sel_dot,
 698 | 	gekko_ps_res,
 699 | 	gekko_ps_res_dot,
 700 | 	gekko_ps_mul,
 701 | 	gekko_ps_mul_dot,
 702 | 	gekko_ps_rsqrte,
 703 | 	gekko_ps_rsqrte_dot,
 704 | 	gekko_ps_msub,
 705 | 	gekko_ps_msub_dot,
 706 | 	gekko_ps_madd,
 707 | 	gekko_ps_madd_dot,
 708 | 	gekko_ps_nmsub,
 709 | 	gekko_ps_nmsub_dot,
 710 | 	gekko_ps_nmadd,
 711 | 	gekko_ps_nmadd_dot,
 712 | 	gekko_ps_neg,
 713 | 	gekko_ps_neg_dot,
 714 | 	gekko_ps_mr,
 715 | 	gekko_ps_mr_dot,
 716 | 	gekko_ps_nabs,
 717 | 	gekko_ps_nabs_dot,
 718 | 	gekko_ps_abs,
 719 | 	gekko_ps_abs_dot,
 720 | 
 721 | 	gekko_ps_sum0,
 722 | 	gekko_ps_sum0_dot,
 723 | 	gekko_ps_sum1,
 724 | 	gekko_ps_sum1_dot,
 725 | 	gekko_ps_muls0,
 726 | 	gekko_ps_muls0_dot,
 727 | 	gekko_ps_muls1,
 728 | 	gekko_ps_muls1_dot,
 729 | 	gekko_ps_madds0,
 730 | 	gekko_ps_madds0_dot,
 731 | 	gekko_ps_madds1,
 732 | 	gekko_ps_madds1_dot,
 733 | 	gekko_ps_cmpu0,
 734 | 	gekko_ps_cmpo0,
 735 | 	gekko_ps_cmpu1,
 736 | 	gekko_ps_cmpo1,
 737 | 	gekko_ps_merge00,
 738 | 	gekko_ps_merge00_dot,
 739 | 	gekko_ps_merge01,
 740 | 	gekko_ps_merge01_dot,
 741 | 	gekko_ps_merge10,
 742 | 	gekko_ps_merge10_dot,
 743 | 	gekko_ps_merge11,
 744 | 	gekko_ps_merge11_dot,
 745 | 	gekko_ps_dcbz_l,
 746 | };
 747 | 
 748 | // -------------------------------------------------------------------------------------------------
 749 | // Structure used to define an opcode
 750 | 
 751 | #define MAX_OPERANDS		6
 752 | 
 753 | struct	altivec_opcode
 754 | {
 755 | 	altivec_insn_type_t	insn;
 756 | 	const char*			name;
 757 | 	unsigned int		opcode;
 758 | 	unsigned int		mask;	
 759 | 	unsigned char		operands[MAX_OPERANDS];
 760 | 	const char*			description;			
 761 | };
 762 | 
 763 | altivec_opcode	g_altivecOpcodes[] = 
 764 | {
 765 | 	{	altivec_lvebx,		"lvebx",		X(31, 7),		X_MASK,		{ VD, RA, RB },			"Load Vector Element Byte Indexed"	},
 766 | 	{	altivec_lvehx,		"lvehx",		X(31, 39),		X_MASK,		{ VD, RA, RB },			"Load Vector Element Half Word Indexed"	},
 767 | 	{	altivec_lvewx,		"lvewx",		X(31, 71),		X_MASK,		{ VD, RA, RB },			"Load Vector Element Word Indexed"	},
 768 | 	{	altivec_lvsl,		"lvsl",			X(31, 6),		X_MASK,		{ VD, RA, RB },			"Load Vector for Shift Left"	},
 769 | 	{	altivec_lvsr, 		"lvsr",			X(31, 38),		X_MASK,		{ VD, RA, RB },			"Load Vector for Shift Right"	},
 770 | 	{	altivec_lvx,		"lvx",			X(31, 103), 	X_MASK,		{ VD, RA, RB },			"Load Vector Indexed"	},
 771 | 	{	altivec_lvxl,		"lvxl",			X(31, 359), 	X_MASK,		{ VD, RA, RB },			"Load Vector Indexed LRU"	},
 772 | 	{	altivec_stvebx,		"stvebx",		X(31, 135), 	X_MASK,		{ VS, RA, RB },			"Store Vector Element Byte Indexed"	},
 773 | 	{	altivec_stvehx,		"stvehx",		X(31, 167), 	X_MASK,		{ VS, RA, RB },			"Store Vector Element Half Word Indexed"	},
 774 | 	{	altivec_stvewx,		"stvewx",		X(31, 199), 	X_MASK,		{ VS, RA, RB },			"Store Vector Element Word Indexed"	},
 775 | 	{	altivec_stvx,		"stvx",			X(31, 231), 	X_MASK,		{ VS, RA, RB },			"Store Vector Indexed"	},
 776 | 	{	altivec_stvxl,		"stvxl",		X(31, 487), 	X_MASK,		{ VS, RA, RB },			"Store Vector Indexed LRU"	},
 777 | 	{	altivec_dst,		"dst",			XDSS(31,342,0),	XDSS_MASK,	{ RA, RB, STRM },		"Data Stream Touch"	},
 778 | 	{	altivec_dstt,		"dstt",			XDSS(31,342,1),	XDSS_MASK,	{ RA, RB, STRM },		"Data Stream Touch Transient"	},
 779 | 	{	altivec_dstst,		"dstst",		XDSS(31,374,0),	XDSS_MASK,	{ RA, RB, STRM },		"Data Stream Touch for Store"	},
 780 | 	{	altivec_dststt,		"dststt",		XDSS(31,374,1),	XDSS_MASK,	{ RA, RB, STRM },		"Data Stream Touch for Store Transient"	},
 781 | 	{	altivec_dss,		"dss",			XDSS(31,822,0),	XDSS_MASK,	{ STRM },				"Data Stream Stop"	},
 782 | 	{	altivec_dssall,		"dssall",		XDSS(31,822,1),	XDSS_MASK,	{ 0 },					"Data Stream Stop All"	},
 783 | 	{	altivec_mfvscr,		"mfvscr",		VX(4, 1540),	VX_MASK,	{ VD },					"Move from Vector Status and Control Register"	},
 784 | 	{	altivec_mtvscr,		"mtvscr",		VX(4, 1604),	VX_MASK,	{ VD },					"Move to Vector Status and Control Register"	},
 785 | 	{	altivec_vaddcuw,	"vaddcuw",		VX(4, 384),		VX_MASK,	{ VD, VA, VB },			"Vector Add Carryout Unsigned Word"	},
 786 | 	{	altivec_vaddfp,		"vaddfp",		VX(4, 10),		VX_MASK,	{ VD, VA, VB },			"Vector Add Floating Point"	},
 787 | 	{	altivec_vaddsbs,	"vaddsbs",		VX(4, 768),		VX_MASK,	{ VD, VA, VB },			"Vector Add Signed Byte Saturate"	},
 788 | 	{	altivec_vaddshs,	"vaddshs",		VX(4, 832),		VX_MASK,	{ VD, VA, VB },			"Vector Add Signed Half Word Saturate"	},
 789 | 	{	altivec_vaddsws,	"vaddsws",		VX(4, 896),		VX_MASK,	{ VD, VA, VB },			"Vector Add Signed Word Saturate"	},
 790 | 	{	altivec_vaddubm,	"vaddubm",		VX(4, 0),		VX_MASK,	{ VD, VA, VB },			"Vector Add Unsigned Byte Modulo"	},
 791 | 	{	altivec_vaddubs,	"vaddubs",		VX(4, 512),		VX_MASK,	{ VD, VA, VB },			"Vector Add Unsigned Byte Saturate"	},
 792 | 	{	altivec_vadduhm,	"vadduhm",		VX(4, 64),		VX_MASK,	{ VD, VA, VB },			"Vector Add Unsigned Half Word Modulo"	},
 793 | 	{	altivec_vadduhs,	"vadduhs",		VX(4, 576),		VX_MASK,	{ VD, VA, VB },			"Vector Add Unsigned Half Word Saturate"	},
 794 | 	{	altivec_vadduwm,	"vadduwm",		VX(4, 128),		VX_MASK,	{ VD, VA, VB },			"Vector Add Unsigned Word Modulo"	},
 795 | 	{	altivec_vadduws,	"vadduws",		VX(4, 640),		VX_MASK,	{ VD, VA, VB },			"Vector Add Unsigned Word Saturate"	},
 796 | 	{	altivec_vand,		"vand",			VX(4, 1028),	VX_MASK,	{ VD, VA, VB },			"Vector Logical AND"	},
 797 | 	{	altivec_vandc,		"vandc",		VX(4, 1092),	VX_MASK,	{ VD, VA, VB },			"Vector Logical AND with Complement"	},
 798 | 	{	altivec_vavgsb,		"vavgsb",		VX(4, 1282),	VX_MASK,	{ VD, VA, VB },			"Vector Average Signed Byte"	},
 799 | 	{	altivec_vavgsh,		"vavgsh",		VX(4, 1346),	VX_MASK,	{ VD, VA, VB },			"Vector Average Signed Half Word"	},
 800 | 	{	altivec_vavgsw,		"vavgsw",		VX(4, 1410),	VX_MASK,	{ VD, VA, VB },			"Vector Average Signed Word"	},
 801 | 	{	altivec_vavgub,		"vavgub",		VX(4, 1026),	VX_MASK,	{ VD, VA, VB },			"Vector Average Unsigned Byte"	},
 802 | 	{	altivec_vavguh,		"vavguh",		VX(4, 1090),	VX_MASK,	{ VD, VA, VB },			"Vector Average Unsigned Half Word"	},
 803 | 	{	altivec_vavguw,		"vavguw",		VX(4, 1154),	VX_MASK,	{ VD, VA, VB },			"Vector Average Unsigned Word"	},
 804 | 	{	altivec_vcfsx,		"vcfsx",		VX(4, 842),		VX_MASK,	{ VD, VB, UIMM },		"Vector Convert from Signed Fixed-Point Word"	},
 805 | 	{	altivec_vcfux,		"vcfux",		VX(4, 778),		VX_MASK,	{ VD, VB, UIMM },		"Vector Convert from Unsigned Fixed-Point Word"	},
 806 | 	{	altivec_vcmpbfp,	"vcmpbfp",		VXR(4, 966, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Bounds Floating Point"	},
 807 | 	{	altivec_vcmpbfp_c,	"vcmpbfp.",		VXR(4, 966, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Bounds Floating Point (set CR6)"	},
 808 | 	{	altivec_vcmpeqfp,	"vcmpeqfp",		VXR(4, 198, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Equal-to Floating Point"	},
 809 | 	{	altivec_vcmpeqfp_c,	"vcmpeqfp.",	VXR(4, 198, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Equal-to Floating Point (set CR6)"	},
 810 | 	{	altivec_vcmpequb,	"vcmpequb",		VXR(4, 6, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Equal-to Unsigned Byte"	},
 811 | 	{	altivec_vcmpequb_c,	"vcmpequb.",	VXR(4, 6, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Equal-to Unsigned Byte (set CR6)"	},
 812 | 	{	altivec_vcmpequh,	"vcmpequh",		VXR(4, 70, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Equal-to Unsigned Half Word"	},
 813 | 	{	altivec_vcmpequh_c,	"vcmpequh.",	VXR(4, 70, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Equal-to Unsigned Half Word (set CR6)"	},
 814 | 	{	altivec_vcmpequw,	"vcmpequw",		VXR(4, 134, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Equal-to Unsigned Word"	},
 815 | 	{	altivec_vcmpequw_c,	"vcmpequw.",	VXR(4, 134, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Equal-to Unsigned Word (set CR6)"	},
 816 | 	{	altivec_vcmpgefp,	"vcmpgefp",		VXR(4, 454, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than-or-Equal-to Floating Point"	},
 817 | 	{	altivec_vcmpgefp_c,	"vcmpgefp.",	VXR(4, 454, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than-or-Equal-to Floating Point (set CR6)"	},
 818 | 	{	altivec_vcmpgtfp,	"vcmpgtfp",		VXR(4, 710, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Floating Point"	},
 819 | 	{	altivec_vcmpgtfp_c,	"vcmpgtfp.",	VXR(4, 710, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Floating Point (set CR6)"	},
 820 | 	{	altivec_vcmpgtsb,	"vcmpgtsb",		VXR(4, 774, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Signed Byte"	},
 821 | 	{	altivec_vcmpgtsb_c,	"vcmpgtsb.",	VXR(4, 774, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Signed Byte (set CR6)"	},
 822 | 	{	altivec_vcmpgtsh,	"vcmpgtsh",		VXR(4, 838, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Signed Half Word"	},
 823 | 	{	altivec_vcmpgtsh_c,	"vcmpgtsh.",	VXR(4, 838, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Signed Half Word (set CR6)"	},
 824 | 	{	altivec_vcmpgtsw,	"vcmpgtsw",		VXR(4, 902, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Signed Word"	},
 825 | 	{	altivec_vcmpgtsw_c,	"vcmpgtsw.",	VXR(4, 902, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Signed Word (set CR6)"	},
 826 | 	{	altivec_vcmpgtub,	"vcmpgtub",		VXR(4, 518, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Unsigned Byte"	},
 827 | 	{	altivec_vcmpgtub_c,	"vcmpgtub.",	VXR(4, 518, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Unsigned Byte (set CR6)"	},
 828 | 	{	altivec_vcmpgtuh,	"vcmpgtuh",		VXR(4, 582, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Unsigned Half Word"	},
 829 | 	{	altivec_vcmpgtuh_c,	"vcmpgtuh.",	VXR(4, 582, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Unsigned Half Word (set CR6)"	},
 830 | 	{	altivec_vcmpgtuw,	"vcmpgtuw",		VXR(4, 646, 0),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Unsigned Word"	},
 831 | 	{	altivec_vcmpgtuw_c,	"vcmpgtuw.",	VXR(4, 646, 1),	VXR_MASK,	{ VD, VA, VB },			"Vector Compare Greater-Than Unsigned Word (set CR6)"	},
 832 | 	{	altivec_vctsxs,		"vctsxs",		VX(4, 970),		VX_MASK,	{ VD, VB, UIMM },		"Vector Convert to Signed Fixed-Point Word Saturate"	},
 833 | 	{	altivec_vctuxs,		"vctuxs",		VX(4, 906),		VX_MASK,	{ VD, VB, UIMM },		"Vector Convert to Unsigned Fixed-Point Word Saturate"	},
 834 | 	{	altivec_vexptefp,	"vexptefp",		VX(4, 394),		VX_MASK,	{ VD, VB },				"Vector 2 Raised to the Exponent Estimate Floating Point"	},
 835 | 	{	altivec_vlogefp,	"vlogefp",		VX(4, 458),		VX_MASK,	{ VD, VB },				"Vector Log2 Estimate Floating Point"	},
 836 | 	{	altivec_vmaddfp,	"vmaddfp",		VXA(4, 46),		VXA_MASK,	{ VD, VA, VC, VB },		"Vector Multiply-Add Floating Point"	},
 837 | 	{	altivec_vmaxfp,		"vmaxfp",		VX(4, 1034),	VX_MASK,	{ VD, VA, VB },			"Vector Maximum Floating Point"	},
 838 | 	{	altivec_vmaxsb,		"vmaxsb",		VX(4, 258),		VX_MASK,	{ VD, VA, VB },			"Vector Maximum Signed Byte"	},
 839 | 	{	altivec_vmaxsh,		"vmaxsh",		VX(4, 322),		VX_MASK,	{ VD, VA, VB },			"Vector Maximum Signed Half Word"	},
 840 | 	{	altivec_vmaxsw,		"vmaxsw",		VX(4, 386),		VX_MASK,	{ VD, VA, VB },			"Vector Maximum Signed Word"	},
 841 | 	{	altivec_vmaxub,		"vmaxub",		VX(4, 2),		VX_MASK,	{ VD, VA, VB },			"Vector Maximum Unsigned Byte"	},
 842 | 	{	altivec_vmaxuh,		"vmaxuh",		VX(4, 66),		VX_MASK,	{ VD, VA, VB },			"Vector Maximum Unsigned Half Word"	},
 843 | 	{	altivec_vmaxuw,		"vmaxuw",		VX(4, 130),		VX_MASK,	{ VD, VA, VB },			"Vector Maximum Unsigned Word"	},
 844 | 	{	altivec_vmhaddshs,	"vmhaddshs",	VXA(4, 32),		VXA_MASK,	{ VD, VA, VB, VC },		"Vector Multiply-High and Add Signed Signed Half Word Saturate"	},
 845 | 	{	altivec_vmhraddshs,	"vmhraddshs",	VXA(4, 33),		VXA_MASK,	{ VD, VA, VB, VC },		"Vector Multiply-High Round and Add Signed Signed Half Word Saturate"	},
 846 | 	{	altivec_vminfp,		"vminfp",		VX(4, 1098),	VX_MASK,	{ VD, VA, VB },			"Vector Minimum Floating Point"	},
 847 | 	{	altivec_vminsb,		"vminsb",		VX(4, 770),		VX_MASK,	{ VD, VA, VB },			"Vector Minimum Signed Byte"	},
 848 | 	{	altivec_vminsh,		"vminsh",		VX(4, 834),		VX_MASK,	{ VD, VA, VB },			"Vector Minimum Signed Half Word"	},
 849 | 	{	altivec_vminsw,		"vminsw",		VX(4, 898),		VX_MASK,	{ VD, VA, VB },			"Vector Minimum Signed Word"	},
 850 | 	{	altivec_vminub,		"vminub",		VX(4, 514),		VX_MASK,	{ VD, VA, VB },			"Vector Minimum Unsigned Byte"	},
 851 | 	{	altivec_vminuh,		"vminuh",		VX(4, 578),		VX_MASK,	{ VD, VA, VB },			"Vector Minimum Unsigned Half Word"	},
 852 | 	{	altivec_vminuw,		"vminuw",		VX(4, 642),		VX_MASK,	{ VD, VA, VB },			"Vector Minimum Unsigned Word"	},
 853 | 	{	altivec_vmladduhm,	"vmladduhm",	VXA(4, 34),		VXA_MASK,	{ VD, VA, VB, VC },		"Vector Multiply-Low and Add Unsigned Half Word Modulo"	},
 854 | 	{	altivec_vmrghb,		"vmrghb",		VX(4, 12),		VX_MASK,	{ VD, VA, VB },			"Vector Merge High Byte"	},
 855 | 	{	altivec_vmrghh,		"vmrghh",		VX(4, 76),		VX_MASK,	{ VD, VA, VB },			"Vector Merge High Half Word"	},
 856 | 	{	altivec_vmrghw,		"vmrghw",		VX(4, 140),		VX_MASK,	{ VD, VA, VB },			"Vector Merge High Word"	},
 857 | 	{	altivec_vmrglb,		"vmrglb",		VX(4, 268),		VX_MASK,	{ VD, VA, VB },			"Vector Merge Low Byte"	},
 858 | 	{	altivec_vmrglh,		"vmrglh",		VX(4, 332),		VX_MASK,	{ VD, VA, VB },			"Vector Merge Low Half Word"	},
 859 | 	{	altivec_vmrglw,		"vmrglw",		VX(4, 396),		VX_MASK,	{ VD, VA, VB },			"Vector Merge Low Word"	},
 860 | 	{	altivec_vmsummbm,	"vmsummbm",		VXA(4, 37),		VXA_MASK,	{ VD, VA, VB, VC },		"Vector Multiply-Sum Mixed-Sign Byte Modulo"	},
 861 | 	{	altivec_vmsumshm,	"vmsumshm",		VXA(4, 40),		VXA_MASK,	{ VD, VA, VB, VC },		"Vector Multiply-Sum Signed Half Word Modulo"	},
 862 | 	{	altivec_vmsumshs,	"vmsumshs",		VXA(4, 41),		VXA_MASK,	{ VD, VA, VB, VC },		"Vector Multiply-Sum Signed Half Word Saturate"	},
 863 | 	{	altivec_vmsumubm,	"vmsumubm",		VXA(4, 36),		VXA_MASK,	{ VD, VA, VB, VC },		"Vector Multiply-Sum Unsigned Byte Modulo"	},
 864 | 	{	altivec_vmsumuhm,	"vmsumuhm",		VXA(4, 38),		VXA_MASK,	{ VD, VA, VB, VC },		"Vector Multiply-Sum Unsigned Half Word Modulo"	},
 865 | 	{	altivec_vmsumuhs,	"vmsumuhs",		VXA(4, 39),		VXA_MASK,	{ VD, VA, VB, VC },		"Vector Multiply-Sum Unsigned Half Word Saturate"	},
 866 | 	{	altivec_vmulesb,	"vmulesb",		VX(4, 776),		VX_MASK,	{ VD, VA, VB },			"Vector Multiply Even Signed Byte"	},
 867 | 	{	altivec_vmulesh,	"vmulesh",		VX(4, 840),		VX_MASK,	{ VD, VA, VB },			"Vector Multiply Even Signed Half Word"	},
 868 | 	{	altivec_vmuleub,	"vmuleub",		VX(4, 520),		VX_MASK,	{ VD, VA, VB },			"Vector Multiply Even Unsigned Byte"	},
 869 | 	{	altivec_vmuleuh,	"vmuleuh",		VX(4, 584),		VX_MASK,	{ VD, VA, VB },			"Vector Multiply Even Unsigned Half Word"	},
 870 | 	{	altivec_vmulosb,	"vmulosb",		VX(4, 264),		VX_MASK,	{ VD, VA, VB },			"Vector Multiply Odd Signed Byte"	},
 871 | 	{	altivec_vmulosh,	"vmulosh",		VX(4, 328),		VX_MASK,	{ VD, VA, VB },			"Vector Multiply Odd Signed Half Word"	},
 872 | 	{	altivec_vmuloub,	"vmuloub",		VX(4, 8),		VX_MASK,	{ VD, VA, VB },			"Vector Multiply Odd Unsigned Byte"	},
 873 | 	{	altivec_vmulouh,	"vmulouh",		VX(4, 72),		VX_MASK,	{ VD, VA, VB },			"Vector Multiply Odd Unsigned Half Word"	},
 874 | 	{	altivec_vnmsubfp,	"vnmsubfp",		VXA(4, 47),		VXA_MASK,	{ VD, VA, VC, VB },		"Vector Negative Multiply-Subtract Floating Point"	},
 875 | 	{	altivec_vnor, 		"vnor",			VX(4, 1284),	VX_MASK,	{ VD, VA, VB },			"Vector Logical NOR"	},
 876 | 	{	altivec_vor,		"vor",			VX(4, 1156),	VX_MASK,	{ VD, VA, VB },			"Vector Logical OR"	},
 877 | 	{	altivec_vperm,		"vperm",		VXA(4, 43),		VXA_MASK,	{ VD, VA, VB, VC },		"Vector Permute"	},
 878 | 	{	altivec_vpkpx,		"vpkpx",		VX(4, 782),		VX_MASK,	{ VD, VA, VB },			"Vector Pack Pixel"	},
 879 | 	{	altivec_vpkshss,	"vpkshss",		VX(4, 398),		VX_MASK,	{ VD, VA, VB },			"Vector Pack Signed Half Word Signed Saturate"	},
 880 | 	{	altivec_vpkshus,	"vpkshus",		VX(4, 270),		VX_MASK,	{ VD, VA, VB },			"Vector Pack Signed Half Word Unsigned Saturate"	},
 881 | 	{	altivec_vpkswss,	"vpkswss",		VX(4, 462),		VX_MASK,	{ VD, VA, VB },			"Vector Pack Signed Word Signed Saturate"	},
 882 | 	{	altivec_vpkswus,	"vpkswus",		VX(4, 334),		VX_MASK,	{ VD, VA, VB },			"Vector Pack Signed Word Unsigned Saturate"	},
 883 | 	{	altivec_vpkuhum,	"vpkuhum",		VX(4, 14),		VX_MASK,	{ VD, VA, VB },			"Vector Pack Unsigned Half Word Unsigned Modulo"	},
 884 | 	{	altivec_vpkuhus,	"vpkuhus",		VX(4, 142),		VX_MASK,	{ VD, VA, VB },			"Vector Pack Unsigned Half Word Unsigned Saturate"	},
 885 | 	{	altivec_vpkuwum,	"vpkuwum",		VX(4, 78),		VX_MASK,	{ VD, VA, VB },			"Vector Pack Unsigned Word Unsigned Modulo"	},
 886 | 	{	altivec_vpkuwus,	"vpkuwus",		VX(4, 206),		VX_MASK,	{ VD, VA, VB },			"Vector Pack Unsigned Word Unsigned Saturate"	},
 887 | 	{	altivec_vrefp,		"vrefp",		VX(4, 266),		VX_MASK,	{ VD, VB },				"Vector Reciprocal Estimate Floating Point"	},
 888 | 	{	altivec_vrfim,		"vrfim",		VX(4, 714),		VX_MASK,	{ VD, VB },				"Vector Round to Floating-Point Integer toward Minus Infinity"	},
 889 | 	{	altivec_vrfin,		"vrfin",		VX(4, 522),		VX_MASK,	{ VD, VB },				"Vector Round to Floating-Point Integer Nearest"	},
 890 | 	{	altivec_vrfip,		"vrfip",		VX(4, 650),		VX_MASK,	{ VD, VB },				"Vector Round to Floating-Point Integer toward Plus Infinity"	},
 891 | 	{	altivec_vrfiz,		"vrfiz",		VX(4, 586),		VX_MASK,	{ VD, VB },				"Vector Round to Floating-Point Integer toward Zero"	},
 892 | 	{	altivec_vrlb, 		"vrlb",			VX(4, 4),		VX_MASK,	{ VD, VA, VB },			"Vector Rotate Left Integer Byte"	},
 893 | 	{	altivec_vrlh,		"vrlh",			VX(4, 68),		VX_MASK,	{ VD, VA, VB },			"Vector Rotate Left Integer Half Word"	},
 894 | 	{	altivec_vrlw, 		"vrlw",			VX(4, 132),		VX_MASK,	{ VD, VA, VB },			"Vector Rotate Left Integer Word"	},
 895 | 	{	altivec_vrsqrtefp,	"vrsqrtefp",	VX(4, 330),		VX_MASK,	{ VD, VB },				"Vector Reciprocal Square Root Estimate Floating Point"	},
 896 | 	{	altivec_vsel,		"vsel",			VXA(4, 42),		VXA_MASK,	{ VD, VA, VB, VC },		"Vector Conditional Select"	},
 897 | 	{	altivec_vsl,		"vsl",			VX(4, 452),		VX_MASK,	{ VD, VA, VB },			"Vector Shift Left"	},
 898 | 	{	altivec_vslb, 		"vslb",			VX(4, 260),		VX_MASK,	{ VD, VA, VB },			"Vector Shift Left Integer Byte"	},
 899 | 	{	altivec_vsldoi,		"vsldoi",		VXA(4, 44),		VXA_MASK,	{ VD, VA, VB, SHB },	"Vector Shift Left Double by Octet Immediate"	},
 900 | 	{	altivec_vslh, 		"vslh",			VX(4, 324),		VX_MASK,	{ VD, VA, VB },			"Vector Shift Left Integer Half Word"	},
 901 | 	{	altivec_vslo, 		"vslo",			VX(4, 1036),	VX_MASK,	{ VD, VA, VB },			"Vector Shift Left by Octet"	},
 902 | 	{	altivec_vslw, 		"vslw",			VX(4, 388),		VX_MASK,	{ VD, VA, VB },			"Vector Shift Left Integer Word"	},
 903 | 	{	altivec_vspltb,		"vspltb",		VX(4, 524),		VX_MASK,	{ VD, VB, UIMM },		"Vector Splat Byte"	},
 904 | 	{	altivec_vsplth,		"vsplth",		VX(4, 588),		VX_MASK,	{ VD, VB, UIMM },		"Vector Splat Half Word"	},
 905 | 	{	altivec_vspltisb,	"vspltisb",		VX(4, 780),		VX_MASK,	{ VD, SIMM },			"Vector Splat Immediate Signed Byte"	},
 906 | 	{	altivec_vspltish,	"vspltish",		VX(4, 844),		VX_MASK,	{ VD, SIMM },			"Vector Splat Immediate Signed Half Word"	},
 907 | 	{	altivec_vspltisw,	"vspltisw",		VX(4, 908),		VX_MASK,	{ VD, SIMM },			"Vector Splat Immediate Signed Word"	},
 908 | 	{	altivec_vspltw,		"vspltw",		VX(4, 652),		VX_MASK,	{ VD, VB, UIMM },		"Vector Splat Word"	},
 909 | 	{	altivec_vsr,		"vsr",			VX(4, 708),		VX_MASK,	{ VD, VA, VB },			"Vector Shift Right"	},
 910 | 	{	altivec_vsrab,		"vsrab",		VX(4, 772),		VX_MASK,	{ VD, VA, VB },			"Vector Shift Right Algebraic Byte"	},
 911 | 	{	altivec_vsrah,		"vsrah",		VX(4, 836),		VX_MASK,	{ VD, VA, VB },			"Vector Shift Right Algebraic Half Word"	},
 912 | 	{	altivec_vsraw,		"vsraw",		VX(4, 900),		VX_MASK,	{ VD, VA, VB },			"Vector Shift Right Algebraic Word"	},
 913 | 	{	altivec_vsrb,		"vsrb",			VX(4, 516),		VX_MASK,	{ VD, VA, VB },			"Vector Shift Right Byte"	},
 914 | 	{	altivec_vsrh, 		"vsrh",			VX(4, 580),		VX_MASK,	{ VD, VA, VB },			"Vector Shift Right Half Word"	},
 915 | 	{	altivec_vsro, 		"vsro",			VX(4, 1100),	VX_MASK,	{ VD, VA, VB },			"Vector Shift Right Octet"	},
 916 | 	{	altivec_vsrw,		"vsrw",			VX(4, 644),		VX_MASK,	{ VD, VA, VB },			"Vector Shift Right Word"	},
 917 | 	{	altivec_vsubcuw,	"vsubcuw",		VX(4, 1408),	VX_MASK,	{ VD, VA, VB },			"Vector Subtract Carryout Unsigned Word"	},
 918 | 	{	altivec_vsubfp,		"vsubfp",		VX(4, 74),		VX_MASK,	{ VD, VA, VB },			"Vector Subtract Floating Point"	},
 919 | 	{	altivec_vsubsbs,	"vsubsbs",		VX(4, 1792),	VX_MASK,	{ VD, VA, VB },			"Vector Subtract Signed Byte Saturate"	},
 920 | 	{	altivec_vsubshs,	"vsubshs",		VX(4, 1856),	VX_MASK,	{ VD, VA, VB },			"Vector Subtract Signed Half Word Saturate"	},
 921 | 	{	altivec_vsubsws,	"vsubsws",		VX(4, 1920),	VX_MASK,	{ VD, VA, VB },			"Vector Subtract Signed Word Saturate"	},
 922 | 	{	altivec_vsububm,	"vsububm",		VX(4, 1024),	VX_MASK,	{ VD, VA, VB },			"Vector Subtract Unsigned Byte Modulo"	},
 923 | 	{	altivec_vsububs,	"vsububs",		VX(4, 1536),	VX_MASK,	{ VD, VA, VB },			"Vector Subtract Unsigned Byte Saturate"	},
 924 | 	{	altivec_vsubuhm,	"vsubuhm",		VX(4, 1088),	VX_MASK,	{ VD, VA, VB },			"Vector Subtract Unsigned Half Word Modulo"	},
 925 | 	{	altivec_vsubuhs,	"vsubuhs",		VX(4, 1600),	VX_MASK,	{ VD, VA, VB },			"Vector Subtract Unsigned Half Word Saturate"	},
 926 | 	{	altivec_vsubuwm,	"vsubuwm",		VX(4, 1152),	VX_MASK,	{ VD, VA, VB },			"Vector Subtract Unsigned Word Modulo"	},
 927 | 	{	altivec_vsubuws,	"vsubuws",		VX(4, 1664),	VX_MASK,	{ VD, VA, VB },			"Vector Subtract Unsigned Word Saturate"	},
 928 | 	{	altivec_vsumsws,	"vsumsws",		VX(4, 1928),	VX_MASK,	{ VD, VA, VB },			"Vector Sum Across Signed Word Saturate"	},
 929 | 	{	altivec_vsum2sws,	"vsum2sws",		VX(4, 1672),	VX_MASK,	{ VD, VA, VB },			"Vector Sum Across Partial (1/2) Signed Word Saturate"	},
 930 | 	{	altivec_vsum4sbs,	"vsum4sbs",		VX(4, 1800),	VX_MASK,	{ VD, VA, VB },			"Vector Sum Across Partial (1/4) Signed Byte Saturate"	},
 931 | 	{	altivec_vsum4shs,	"vsum4shs",		VX(4, 1608),	VX_MASK,	{ VD, VA, VB },			"Vector Sum Across Partial (1/4) Signed Half Word Saturate"	},
 932 | 	{	altivec_vsum4ubs,	"vsum4ubs",		VX(4, 1544),	VX_MASK,	{ VD, VA, VB },			"Vector Sum Across Partial (1/4) Unsigned Byte Saturate"	},
 933 | 	{	altivec_vupkhpx,	"vupkhpx",		VX(4, 846),		VX_MASK,	{ VD, VB },				"Vector Unpack High Pixel"	},
 934 | 	{	altivec_vupkhsb,	"vupkhsb",		VX(4, 526),		VX_MASK,	{ VD, VB },				"Vector Unpack High Signed Byte"	},
 935 | 	{	altivec_vupkhsh,	"vupkhsh",		VX(4, 590),		VX_MASK,	{ VD, VB },				"Vector Unpack High Signed Half Word"	},
 936 | 	{	altivec_vupklpx,	"vupklpx",		VX(4, 974),		VX_MASK,	{ VD, VB },				"Vector Unpack Low Pixel"	},
 937 | 	{	altivec_vupklsb,	"vupklsb",		VX(4, 654),		VX_MASK,	{ VD, VB },				"Vector Unpack Low Signed Byte"	},
 938 | 	{	altivec_vupklsh,	"vupklsh",		VX(4, 718),		VX_MASK,	{ VD, VB },				"Vector Unpack Low Signed Half Word"	},
 939 | 	{	altivec_vxor,		"vxor",			VX(4, 1220),	VX_MASK,	{ VD, VA, VB },			"Vector Logical XOR"	},
 940 | 
 941 | 	// Takires: Added opcodes
 942 | 	{	vmx128_vsldoi128,	"vsldoi128",	VX128_5(4, 16),		VX128_5_MASK,	{ VD128, VA128, VB128, SHB },			""	},
 943 | 	{	vmx128_lvsl128,		"lvsl128",		VX128_1(4, 3),		VX128_1_MASK,	{ VD128, RA, RB },						""	},
 944 | 	{	vmx128_lvsr128,		"lvsr128",		VX128_1(4, 67),		VX128_1_MASK,	{ VD128, RA, RB },						""	},
 945 | 	{	vmx128_lvewx128,	"lvewx128",		VX128_1(4, 131),	VX128_1_MASK,	{ VD128, RA, RB },						""	},
 946 | 	{	vmx128_lvx128,		"lvx128",		VX128_1(4, 195),	VX128_1_MASK,	{ VD128, RA, RB },						""	},
 947 | 	{	vmx128_stvewx128,	"stvewx128",	VX128_1(4, 387),	VX128_1_MASK,	{ VS128, RA, RB },						""	},
 948 | 	{	vmx128_stvx128,		"stvx128",		VX128_1(4, 451),	VX128_1_MASK,	{ VS128, RA, RB },						""	},
 949 | 	{	vmx128_lvxl128,		"lvxl128",		VX128_1(4, 707),	VX128_1_MASK,	{ VD128, RA, RB },						""	},
 950 | 	{	vmx128_stvxl128,	"stvxl128",		VX128_1(4, 963),	VX128_1_MASK,	{ VS128, RA, RB },						""	},
 951 | 	{	vmx128_lvlx128,		"lvlx128",		VX128_1(4, 1027),	VX128_1_MASK,	{ VD128, RA, RB },						""	},
 952 | 	{	vmx128_lvrx128,		"lvrx128",		VX128_1(4, 1091),	VX128_1_MASK,	{ VD128, RA, RB },						""	},
 953 | 	{	vmx128_stvlx128,	"stvlx128",		VX128_1(4, 1283),	VX128_1_MASK,	{ VS128, RA, RB },						""	},
 954 | 	{	vmx128_stvrx128,	"stvrx128",		VX128_1(4, 1347),	VX128_1_MASK,	{ VS128, RA, RB },						""	},
 955 | 	{	vmx128_lvlxl128,	"lvlxl128",		VX128_1(4, 1539),	VX128_1_MASK,	{ VD128, RA, RB },						""	},
 956 | 	{	vmx128_lvrxl128,	"lvrxl128",		VX128_1(4, 1603),	VX128_1_MASK,	{ VD128, RA, RB },						""	},
 957 | 	{	vmx128_stvlxl128,	"stvlxl128",	VX128_1(4, 1795),	VX128_1_MASK,	{ VS128, RA, RB },						""	},
 958 | 	{	vmx128_stvrxl128,	"stvrxl128",	VX128_1(4, 1859),	VX128_1_MASK,	{ VS128, RA, RB },						""	},
 959 | 	{	vmx128_vperm128,	"vperm128",		VX128_2(5, 0),		VX128_2_MASK,	{ VD128, VA128, VB128, VC128 },			""	},
 960 | 	{	vmx128_vaddfp128,	"vaddfp128",	VX128(5, 16),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 961 | 	{	vmx128_vsubfp128,	"vsubfp128",	VX128(5,  80),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 962 | 	{	vmx128_vmulfp128,	"vmulfp128",	VX128(5, 144),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 963 | 	{	vmx128_vmaddfp128,	"vmaddfp128",	VX128(5, 208),		VX128_MASK,		{ VD128, VA128, VB128, VS128 },			""	},
 964 | 	{	vmx128_vmaddcfp128,	"vmaddcfp128",	VX128(5, 272),		VX128_MASK,		{ VD128, VA128, VS128, VB128 },			""	},
 965 | 	{	vmx128_vnmsubfp128,	"vnmsubfp128",	VX128(5, 336),		VX128_MASK,		{ VD128, VA128, VB128, VS128 },			""	},
 966 | 	{	vmx128_vmsum3fp128,	"vmsum3fp128",	VX128(5, 400),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 967 | 	{	vmx128_vmsum4fp128,	"vmsum4fp128",	VX128(5, 464),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 968 | 	{	vmx128_vpkshss128,	"vpkshss128",	VX128(5, 512),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 969 | 	{	vmx128_vand128,		"vand128",		VX128(5, 528),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 970 | 	{	vmx128_vpkshus128,	"vpkshus128",	VX128(5, 576),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 971 | 	{	vmx128_vandc128,	"vandc128",		VX128(5, 592),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 972 | 	{	vmx128_vpkswss128,	"vpkswss128",	VX128(5, 640),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 973 | 	{	vmx128_vnor128,		"vnor128",		VX128(5, 656),		VX128_MASK,		{ VD128, VA128, VB128 },				""  },
 974 | 	{	vmx128_vpkswus128,	"vpkswus128",	VX128(5, 704),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 975 | 	{	vmx128_vor128,		"vor128",		VX128(5, 720),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 976 | 	{	vmx128_vpkuhum128,	"vpkuhum128",	VX128(5, 768),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 977 | 	{	vmx128_vxor128,		"vxor128",		VX128(5, 784),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 978 | 	{	vmx128_vpkuhus128,	"vpkuhus128",	VX128(5, 832),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 979 | 	{	vmx128_vsel128,		"vsel128",		VX128(5, 848),		VX128_MASK,		{ VD128, VA128, VB128, VS128 },			""	},
 980 | 	{	vmx128_vpkuwum128,	"vpkuwum128",	VX128(5, 896),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 981 | 	{	vmx128_vslo128,		"vslo128",		VX128(5, 912),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 982 | 	{	vmx128_vpkuwus128,	"vpkuwus128",	VX128(5, 960),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 983 | 	{	vmx128_vsro128,		"vsro128",		VX128(5, 976),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
 984 | 
 985 | 	{	vmx128_vpermwi128,	"vpermwi128",	VX128_P(6, 528),	VX128_P_MASK,	{ VD128, VB128, VPERM128 },				""	},
 986 | 	{	vmx128_vcfpsxws128,	"vcfpsxws128",	VX128_3(6, 560),	VX128_3_MASK,	{ VD128, VB128, SIMM },					""	},
 987 | 	{	vmx128_vcfpuxws128,	"vcfpuxws128",	VX128_3(6, 624),	VX128_3_MASK,	{ VD128, VB128, UIMM },					""	},
 988 | 	{	vmx128_vcsxwfp128,	"vcsxwfp128",	VX128_3(6, 688),	VX128_3_MASK,	{ VD128, VB128, SIMM },					""	},
 989 | 	{	vmx128_vcuxwfp128,	"vcuxwfp128",	VX128_3(6, 752),	VX128_3_MASK,	{ VD128, VB128, UIMM },					""	},
 990 | 	{	vmx128_vrfim128,	"vrfim128",		VX128_3(6, 816),	VX128_3_MASK,	{ VD128, VB128 },						""	},
 991 | 	{	vmx128_vrfin128,	"vrfin128",		VX128_3(6, 880),	VX128_3_MASK,	{ VD128, VB128 },						""	},
 992 | 	{	vmx128_vrfip128,	"vrfip128",		VX128_3(6, 944),	VX128_3_MASK,	{ VD128, VB128 },						""	},
 993 | 	{	vmx128_vrfiz128,	"vrfiz128",		VX128_3(6, 1008),	VX128_3_MASK,	{ VD128, VB128 },						""	},
 994 | 	{	vmx128_vpkd3d128,	"vpkd3d128",	VX128_4(6, 1552),	VX128_4_MASK,	{ VD128, VB128, VD3D0, VD3D1, VD3D2},	""	},
 995 | 	{	vmx128_vrefp128,	"vrefp128",		VX128_3(6, 1584),	VX128_3_MASK,	{ VD128, VB128 },						""	},
 996 | 	{	vmx128_vrsqrtefp128,"vrsqrtefp128",	VX128_3(6, 1648),	VX128_3_MASK,	{ VD128, VB128 },						""	},
 997 | 	{	vmx128_vexptefp128,	"vexptefp128",	VX128_3(6, 1712),	VX128_3_MASK,	{ VD128, VB128 },						""	},
 998 | 	{	vmx128_vlogefp128,	"vlogefp128",	VX128_3(6, 1776),	VX128_3_MASK,	{ VD128, VB128 },						""	},
 999 | 	{	vmx128_vrlimi128,	"vrlimi128",	VX128_4(6, 1808),	VX128_4_MASK,	{ VD128, VB128, UIMM, VD3D2},			""	},
1000 | 	{	vmx128_vspltw128,	"vspltw128",	VX128_3(6, 1840),	VX128_3_MASK,	{ VD128, VB128, UIMM },					""	},
1001 | 	{	vmx128_vspltisw128,	"vspltisw128",	VX128_3(6, 1904),	VX128_3_MASK,	{ VD128, VB128, SIMM },					""	},
1002 | 	{	vmx128_vupkd3d128,	"vupkd3d128",	VX128_3(6, 2032),	VX128_3_MASK,	{ VD128, VB128, UIMM },					""	},
1003 | 	{	vmx128_vcmpeqfp128,	"vcmpeqfp128",	VX128(6, 0),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1004 | 	{	vmx128_vcmpeqfp128c,"vcmpeqfp128.",	VX128(6, 64),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1005 | 	{	vmx128_vrlw128,		"vrlw128",		VX128(6, 80),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1006 | 	{	vmx128_vcmpgefp128,	"vcmpgefp128",	VX128(6, 128),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1007 | 	{	vmx128_vcmpgefp128c,"vcmpgefp128.",	VX128(6, 192),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1008 | 	{	vmx128_vslw128,		"vslw128",		VX128(6, 208),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1009 | 	{	vmx128_vcmpgtfp128,	"vcmpgtfp128",	VX128(6, 256),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1010 | 	{	vmx128_vcmpgtfp128c,"vcmpgtfp128.",	VX128(6, 320),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1011 | 	{	vmx128_vsraw128,	"vsraw128",		VX128(6, 336),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1012 | 	{	vmx128_vcmpbfp128,	"vcmpbfp128",	VX128(6, 384),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1013 | 	{	vmx128_vcmpbfp128c,	"vcmpbfp128.",	VX128(6, 448),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1014 | 	{	vmx128_vsrw128,		"vsrw128",		VX128(6, 464),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1015 | 	{	vmx128_vcmpequw128,	"vcmpequw128",	VX128(6, 512),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1016 | 	{	vmx128_vcmpequw128c,"vcmpequw128.",	VX128(6, 576),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1017 | 	{	vmx128_vmaxfp128,	"vmaxfp128",	VX128(6, 640),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1018 | 	{	vmx128_vminfp128,	"vminfp128",	VX128(6, 704),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1019 | 	{	vmx128_vmrghw128,	"vmrghw128",	VX128(6, 768),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1020 | 	{	vmx128_vmrglw128,	"vmrglw128",	VX128(6, 832),		VX128_MASK,		{ VD128, VA128, VB128 },				""	},
1021 | 	{	vmx128_vupkhsb128,	"vupkhsb128",	VX128(6, 896),		VX128_MASK,		{ VD128, VB128 },						""	},
1022 | 	{	vmx128_vupklsb128,	"vupklsb128",	VX128(6, 960),		VX128_MASK,		{ VD128, VB128 },						""  },
1023 | 
1024 | 	{	vmx128_lvlx,		"lvlx",			X(31, 519),			X_MASK,			{ VD, RA0, RB },						""	},
1025 | 	{	vmx128_lvlxl,		"lvlxl",		X(31, 775),			X_MASK,			{ VD, RA0, RB },						""	},
1026 | 	{	vmx128_lvrx,		"lvrx",			X(31, 551),			X_MASK,			{ VD, RA0, RB },						""	},
1027 | 	{	vmx128_lvrxl,		"lvrxl",		X(31, 807),			X_MASK,			{ VD, RA0, RB },						""	},
1028 | 	{	vmx128_stvlx,		"stvlx",		X(31, 647),			X_MASK,			{ VS, RA0, RB },						""	},
1029 | 	{	vmx128_stvlxl,		"stvlxl",		X(31, 903),			X_MASK,			{ VS, RA0, RB },						""	},
1030 | 	{	vmx128_stvrx,		"stvrx",		X(31, 679),			X_MASK,			{ VS, RA0, RB },						""	},
1031 | 	{	vmx128_stvrxl,		"stvrxl",		X(31, 935),			X_MASK,			{ VS, RA0, RB },						""	},
1032 | 
1033 | 	{	std_attn,			"attn",			X(0, 256),			X_MASK,			{ 0 },									""	},
1034 | 	{	std_dbcz128,		"dbcz128",		XRT(31, 1014, 1),	XRT_MASK,		{ RA, RB },								"Data Cache Block set to Zero (1)"	},
1035 | 	
1036 | 	// the normal PPC processor module handles normal syscalls,
1037 | 	// so this just need to handle level 1 syscalls (hypercalls)
1038 | 	{	std_hvsc,			"hvsc",			0x44000022,			0xFFFFFFFF,		{ 0 },									"Level1 Syscall (Hypercall)"	},
1039 | 	
1040 | 	// added entries for mfspr and mtspr to cover all spr's described in CEBA documentation
1041 | 	{	std_mtspr,			"mtspr",		0x7C0003A6,			0xFC0007FE,		{ SPR, RS },							"Move to sprg, "	},/// XFX macro didnt work just put opcode + mask manually
1042 | 	{	std_mfspr,			"mfspr",		0x7C0002A6,			0xFC0007FE,		{ RS, SPR },							"Move from sprg, "	},
1043 | 	
1044 | 	{	std_ldbrx,			"ldbrx",		X(31, 532),			X_MASK,			{ RT, RA0, RB },						"Load Doubleword Byte Reverse Indexed" },
1045 | 	{	std_mfocrf,			"mfocrf",		XFX(31, 19, 1),		XFX_MASK,		{ RT, CRM },							"Move from One Condition Register Field"	},
1046 | 	{	std_mtmsr,			"mtmsr",		X(31, 146),			XRLARB_MASK,	{ RS },									"Move to Machine State Register"	},
1047 | 	{	std_mtmsrd,			"mtmsrd",		X(31, 178),			XRLARB_MASK,	{ RS, L15 },							"Move to Machine State Register Doubleword"	},
1048 | 	{	std_mtocrf,			"mtocrf",		XFX(31, 144, 1),	XFX_MASK,		{ CRM, RS },							"Move to One Condition Register Field"	},
1049 | 	{	std_slbmte,			"slbmte",		X(31, 402),			XRA_MASK,		{ RS, RB, 0 },							"SLB Move to Entry"	},
1050 | 	{	std_stdbrx,			"stdbrx",		X(31, 660),			X_MASK,			{ RS, RA0, RB },						"Store Doubleword Byte Reverse Indexed" },
1051 | //	{	std_svc,			"svc",			SC(17, 0, 0),		SC_MASK,		{ SVC_LEV, FL1, FL2 },					"Synchronize"	},
1052 | //	{	std_svcl,			"svcl",			SC(17, 0, 1),		SC_MASK,		{ SVC_LEV, FL1, FL2 },					"Synchronize"	},
1053 | //	{	std_svca,			"svca",			SC(17, 1, 0),		SC_MASK,		{ SV },									"Synchronize"	},
1054 | //	{	std_svcla,			"svcla",		SC(17, 1, 1),		SC_MASK,		{ SV },									"Synchronize"	},
1055 | 	{	std_lwsync,			"lwsync",		XSYNC(31, 598, 1),	0xffffffff,		{ 0 },									"Lightweight Synchronize"	},
1056 | 	{	std_ptesync,		"ptesync",		XSYNC(31, 598, 2),	0xffffffff,		{ 0 },									"Synchronize"	},
1057 | 	{	std_sync,			"sync",			X(31, 598),			X_MASK,			{ 0 },									"Synchronize"	},
1058 | 	{	std_tlbiel,			"tlbiel",		X(31, 274),			X_MASK,			{ RB, L10 },							"TLB Invalidate Entry Local"	},
1059 | 	{	std_tlbie,			"tlbie",		X(31, 306),			XRTLRA_MASK,	{ RB, L },								"TLB Invalidate Entry"	},
1060 | 	{	std_tlbi,			"tlbi",			X(31, 306),			XRT_MASK,		{ RA, RB },								"TLB Invalidate"	},
1061 | 	{	std_slbie,			"slbie",		X(31, 434),			XRTRA_MASK,		{ RB },									"SLB Invalidate Entry"	},
1062 | 	
1063 | 	// special instructions that don't seem to have full setup info
1064 | 	{ spec_callthru,		"callthru",		0x000eaeb0,			0xffffffff,		{ 0 },									"SystemSim Callthru" },
1065 | 	{ spec_cctpl,			"cctpl",		0x7c210b78,			0xffffffff,		{ 0 },									"" },
1066 | 	{ spec_cctpm,			"cctpm",		0x7c421378,			0xffffffff,		{ 0 },									"" },
1067 | 	{ spec_cctph,			"cctph",		0x7c631b78,			0xffffffff,		{ 0 },									"" },
1068 | 	{ spec_db8cyc,			"db8cyc",		0x7f9ce378,			0xffffffff,		{ 0 },									"" },
1069 | 	{ spec_db10cyc,			"db10cyc",		0x7fbdeb78,			0xffffffff,		{ 0 },									"" },
1070 | 	{ spec_db12cyc,			"db12cyc",		0x7fdef378,			0xffffffff,		{ 0 },									"" },
1071 | 	{ spec_db16cyc,			"db16cyc",		0x7ffffb78,			0xffffffff,		{ 0 },									"" },
1072 | 	{ spec_02002000,		"opcode_02002000",0x02002000,		0xffffffff,		{ 0 },									"Unknown instruction - included to allow conversion to code" },
1073 | 	
1074 | 	// gekko specific
1075 | 	{	gekko_psq_lx,			"psq_lx",		OPM(4, 6),			OPM_MASK,	{ FD, RA, RB, WC, IC },	"Paired Single Quantized Load Indexed"	},
1076 | 	{	gekko_psq_stx,			"psq_stx",		OPM(4, 7),			OPM_MASK,	{ FS, RA, RB, WC, IC },	"Paired Single Quantized Store Indexed"	},
1077 | 	{	gekko_psq_lux,			"psq_lux",		OPM(4, 38),			OPM_MASK,	{ FD, RA, RB, WC, IC },	"Paired Single Quantized Load with update Indexed"	},
1078 | 	{	gekko_psq_stux,			"psq_stux",		OPM(4, 39),			OPM_MASK,	{ FS, RA, RB, WC, IC },	"Paired Single Quantized Store with update Indexed"	},
1079 | 	
1080 | 	{	gekko_psq_l, 			"psq_l",		OP(56),				OP_MASK,	{ FD, DRA, WB, IB },	"Paired Single Quantized Load"	},
1081 | 	{	gekko_psq_lu,			"psq_lu",		OP(57), 			OP_MASK,	{ FD, DRA, WB, IB },	"Paired Single Quantized Load with Update"	},
1082 | 	{	gekko_psq_st,			"psq_st",		OP(60), 			OP_MASK,	{ FS, DRA, WB, IB },	"Paired Single Quantized Store"	},
1083 | 	{	gekko_psq_stu,			"psq_stu",		OP(61), 			OP_MASK,	{ FS, DRA, WB, IB },	"Paired Single Quantized Store with update"	},
1084 | 	
1085 | 	{	gekko_ps_div,			"ps_div",		OPSC(4, 18, 0),		OPS_MASK,		{ FD, FA, FB},		"Paired Single Divide"	},
1086 | 	{	gekko_ps_div_dot,		"ps_div.",		OPSC(4, 18, 1),		OPS_MASK_DOT,	{ FD, FA, FB},		"Paired Single Divide"	},
1087 | 	{	gekko_ps_sub,			"ps_sub",		OPSC(4, 20, 0),		OPS_MASK,		{ FD, FA, FB},		"Paired Single Subtract"	},
1088 | 	{	gekko_ps_sub_dot,		"ps_sub.",		OPSC(4, 20, 1),		OPS_MASK_DOT,	{ FD, FA, FB},		"Paired Single Subtract"	},
1089 | 	{	gekko_ps_add,			"ps_add",		OPSC(4, 21, 0),		OPS_MASK,		{ FD, FA, FB},		"Paired Single Add"	},
1090 | 	{	gekko_ps_add_dot,		"ps_add.",		OPSC(4, 21, 1),		OPS_MASK_DOT,	{ FD, FA, FB},		"Paired Single Add"	},
1091 | 	{	gekko_ps_sel,			"ps_sel",		OPSC(4, 23, 0),		OPS_MASK,		{ FD, FA, FC, FB},	"Paired Single Select"	},
1092 | 	{	gekko_ps_sel_dot,		"ps_sel.",		OPSC(4, 23, 1),		OPS_MASK_DOT,	{ FD, FA, FC, FB},	"Paired Single Select"	},
1093 | 	{	gekko_ps_res,			"ps_res",		OPSC(4, 24, 0),		OPS_MASK,		{ FD, FB},			"Paired Single Reciprocal Estimate"	},
1094 | 	{	gekko_ps_res_dot,		"ps_res.",		OPSC(4, 24, 1),		OPS_MASK_DOT,	{ FD, FB},			"Paired Single Reciprocal Estimate"	},
1095 | 	{	gekko_ps_mul,			"ps_mul",		OPSC(4, 25, 0),		OPS_MASK,		{ FD, FA, FC},		"Paired Single Multiply"	},
1096 | 	{	gekko_ps_mul_dot,		"ps_mul.",		OPSC(4, 25, 1),		OPS_MASK_DOT,	{ FD, FA, FC},		"Paired Single Multiply"	},
1097 | 	{	gekko_ps_rsqrte,		"ps_rsqrte",	OPSC(4, 26, 0),		OPS_MASK,		{ FD, FB},			"Paired Single Reciprocal Square Root Estimate"	},
1098 | 	{	gekko_ps_rsqrte_dot,	"ps_rsqrte.",	OPSC(4, 26, 1),		OPS_MASK_DOT,	{ FD, FB},			"Paired Single Reciprocal Square Root Estimate"	},
1099 | 	{	gekko_ps_msub,			"ps_msub",		OPSC(4, 28, 0),		OPS_MASK,		{ FD, FA, FC, FB},	"Paired Single Multiply-Subtract"	},
1100 | 	{	gekko_ps_msub_dot,		"ps_msub.",		OPSC(4, 28, 1),		OPS_MASK_DOT,	{ FD, FA, FC, FB},	"Paired Single Multiply-Subtract"	},
1101 | 	{	gekko_ps_madd,			"ps_madd",		OPSC(4, 29, 0),		OPS_MASK,		{ FD, FA, FC, FB},	"Paired Single Multiply-Add"	},
1102 | 	{	gekko_ps_madd_dot,		"ps_madd.",		OPSC(4, 29, 1),		OPS_MASK_DOT,	{ FD, FA, FC, FB},	"Paired Single Multiply-Add"	},
1103 | 	{	gekko_ps_nmsub,			"ps_nmsub",		OPSC(4, 30, 0),		OPS_MASK,		{ FD, FA, FC, FB},	"Paired Single Negative Multiply-Subtract"	},
1104 | 	{	gekko_ps_nmsub_dot,		"ps_nmsub.",	OPSC(4, 30, 1),		OPS_MASK_DOT,	{ FD, FA, FC, FB},	"Paired Single Negative Multiply-Subtract"	},
1105 | 	{	gekko_ps_nmadd,			"ps_nmadd",		OPSC(4, 31, 0),		OPS_MASK,		{ FD, FA, FC, FB},	"Paired Single Negative Multiply-Add"	},
1106 | 	{	gekko_ps_nmadd_dot,		"ps_nmadd.",	OPSC(4, 31, 1),		OPS_MASK_DOT,	{ FD, FA, FC, FB},	"Paired Single Negative Multiply-Add"	},
1107 | 
1108 | 	{	gekko_ps_neg,			"ps_neg",		OPLC(4, 40, 0),		OPL_MASK,		{ FD, FB },			"Paired Single Negate"	},
1109 | 	{	gekko_ps_neg_dot,		"ps_neg.",		OPLC(4, 40, 1),		OPL_MASK_DOT,	{ FD, FB },			"Paired Single Negate"	},
1110 | 	{	gekko_ps_mr,			"ps_mr",		OPLC(4, 72, 0),		OPL_MASK,		{ FD, FB },			"Paired Single Move Register"	},
1111 | 	{	gekko_ps_mr_dot,		"ps_mr.",		OPLC(4, 72, 1),		OPL_MASK_DOT,	{ FD, FB },			"Paired Single Move Register"	},
1112 | 	{	gekko_ps_nabs,			"ps_nabs",		OPLC(4, 136, 0),	OPL_MASK,		{ FD, FB },			"Paired Single Negative Absolute Value"	},
1113 | 	{	gekko_ps_nabs_dot,		"ps_nabs.",		OPLC(4, 136, 1),	OPL_MASK_DOT,	{ FD, FB },			"Paired Single Negative Absolute Value"	},
1114 | 	{	gekko_ps_abs,			"ps_abs",		OPLC(4, 264, 0),	OPL_MASK,		{ FD, FB },			"Paired Single Absolute Value"	},
1115 | 	{	gekko_ps_abs_dot,		"ps_abs.",		OPLC(4, 264, 1),	OPL_MASK_DOT,	{ FD, FB },			"Paired Single Absolute Value"	},
1116 | 	
1117 | 	{	gekko_ps_sum0,			"ps_sum0",		OPSC(4, 10, 0),		OPS_MASK,		{ FD, FA, FC, FB },	"Paired Single vector SUM high"	},
1118 | 	{	gekko_ps_sum0_dot,		"ps_sum0.",		OPSC(4, 10, 1),		OPS_MASK_DOT,	{ FD, FA, FC, FB },	"Paired Single vector SUM high"	},
1119 | 	{	gekko_ps_sum1,			"ps_sum1",		OPSC(4, 11, 0),		OPS_MASK,		{ FD, FA, FC, FB },	"Paired Single vector SUM low"	},
1120 | 	{	gekko_ps_sum1_dot,		"ps_sum1.",		OPSC(4, 11, 1),		OPS_MASK_DOT,	{ FD, FA, FC, FB },	"Paired Single vector SUM low"	},
1121 | 	{	gekko_ps_muls0,			"ps_muls0",		OPSC(4, 12, 0),		OPS_MASK,		{ FD, FA, FC },		"Paired Single Multiply Scalar high"	},
1122 | 	{	gekko_ps_muls0_dot,		"ps_muls0.",	OPSC(4, 12, 1),		OPS_MASK_DOT,	{ FD, FA, FC },		"Paired Single Multiply Scalar high"	},
1123 | 	{	gekko_ps_muls1,			"ps_muls1",		OPSC(4, 13, 0),		OPS_MASK,		{ FD, FA, FC },		"Paired Single Multiply Scalar low"		},
1124 | 	{	gekko_ps_muls1_dot,		"ps_muls1.",	OPSC(4, 13, 1),		OPS_MASK_DOT,	{ FD, FA, FC },		"Paired Single Multiply Scalar low"		},
1125 | 	{	gekko_ps_madds0,		"ps_madds0",	OPSC(4, 14, 0),		OPS_MASK,		{ FD, FA, FC, FB },	"Paired Single Multiply-Add Scalar high"},
1126 | 	{	gekko_ps_madds0_dot,	"ps_madds0.",	OPSC(4, 14, 1),		OPS_MASK_DOT,	{ FD, FA, FC, FB },	"Paired Single Multiply-Add Scalar high"},
1127 | 	{	gekko_ps_madds1,		"ps_madds1",	OPSC(4, 15, 0),		OPS_MASK,		{ FD, FA, FC, FB },	"Paired Single Multiply-Add Scalar low"	},
1128 | 	{	gekko_ps_madds1_dot,	"ps_madds1.",	OPSC(4, 15, 1),		OPS_MASK_DOT,	{ FD, FA, FC, FB },	"Paired Single Multiply-Add Scalar low"	},
1129 | 	
1130 | 	{	gekko_ps_cmpu0,			"ps_cmpu0",		OPL(4, 0),			OPL_MASK,		{ crfD, FA, FB },	"Paired Singles Compare Unordered High"	},
1131 | 	{	gekko_ps_cmpo0,			"ps_cmpo0",		OPL(4, 32),			OPL_MASK,		{ crfD, FA, FB },	"Paired Singles Compare Ordered High"	},
1132 | 	{	gekko_ps_cmpu1,			"ps_cmpu1",		OPL(4, 64),			OPL_MASK,		{ crfD, FA, FB },	"Paired Singles Compare Unordered Low"	},
1133 | 	{	gekko_ps_cmpo1,			"ps_cmpo1",		OPL(4, 96),			OPL_MASK,		{ crfD, FA, FB },	"Paired Singles Compare Ordered Low"	},
1134 | 
1135 | 	{	gekko_ps_merge00,		"ps_merge00",	OPLC(4, 528, 0),	OPL_MASK,		{ FD, FA, FB },		"Paired Single MERGE high"		},
1136 | 	{	gekko_ps_merge00_dot,	"ps_merge00.",	OPLC(4, 528, 1),	OPL_MASK_DOT,	{ FD, FA, FB },		"Paired Single MERGE high"		},
1137 | 	{	gekko_ps_merge01,		"ps_merge01",	OPLC(4, 560, 0),	OPL_MASK,		{ FD, FA, FB },		"Paired Single MERGE direct"	},
1138 | 	{	gekko_ps_merge01_dot,	"ps_merge01.",	OPLC(4, 560, 1),	OPL_MASK_DOT,	{ FD, FA, FB },		"Paired Single MERGE direct"	},
1139 | 	{	gekko_ps_merge10,		"ps_merge10",	OPLC(4, 592, 0),	OPL_MASK,		{ FD, FA, FB },		"Paired Single MERGE swapped"	},
1140 | 	{	gekko_ps_merge10_dot,	"ps_merge10.",	OPLC(4, 592, 1),	OPL_MASK_DOT,	{ FD, FA, FB },		"Paired Single MERGE swapped"	},
1141 | 	{	gekko_ps_merge11,		"ps_merge11",	OPLC(4, 624, 0),	OPL_MASK,		{ FD, FA, FB },		"Paired Single MERGE low"		},
1142 | 	{	gekko_ps_merge11_dot,	"ps_merge11.",	OPLC(4, 624, 1),	OPL_MASK_DOT,	{ FD, FA, FB },		"Paired Single MERGE low"		},
1143 | 
1144 | 	{	gekko_ps_dcbz_l,		"dcbz_l",		OPL(4, 1014),		OPL_MASK,		{ RA, RB },			"Data Cache Block Set to Zero Locked"	},
1145 | };
1146 | 
1147 | 
1148 | 
1149 | 
1150 | /***************************************************************************************************
1151 | *
1152 | *	FUNCTION		PluginAnalyse
1153 | *
1154 | *	DESCRIPTION		This is the main analysis function..
1155 | *
1156 | ***************************************************************************************************/
1157 | 
1158 | int	PluginAnalyse( void )
1159 | {
1160 | 	// Get the 
1161 | 	int	codeBytes = get_long( cmd.ea );
1162 | 
1163 | 	// When we check
1164 | 	int opBytes = ( codeBytes & OP_MASK );
1165 | 
1166 | 	// These signify the additional opcodes that this module supports
1167 | 	if( ( opBytes == OP(  0 ) ) || 
1168 | 		( opBytes == OP(  4 ) ) || 
1169 | 		( opBytes == OP(  5 ) ) || 
1170 | 		( opBytes == OP(  6 ) ) || 
1171 |  		( opBytes == OP( 17 ) ) || 
1172 | 		( opBytes == OP( 31 ) ) ||
1173 | 		 // gekko specific
1174 | 		( opBytes == OP( 56 ) ) ||
1175 | 		( opBytes == OP( 57 ) ) || 
1176 | 		( opBytes == OP( 60 ) ) || 
1177 | 		( opBytes == OP( 61 ) ) )
1178 | 	{
1179 | 		int	opcodeArraySize				= sizeof( g_altivecOpcodes ) / sizeof( altivec_opcode );
1180 | 		altivec_opcode*	pCurrentOpcode	= g_altivecOpcodes;
1181 | 		
1182 | 		// Go through the entire opcode array looking for a match
1183 | 		for ( int opcodeLoop = 0; opcodeLoop < opcodeArraySize; opcodeLoop++ )
1184 | 		{
1185 | 			// Is this a match?
1186 | 			if ( ( codeBytes & pCurrentOpcode->mask ) == pCurrentOpcode->opcode ) 
1187 | 			{
1188 | 				// Ok, so we've got a match.. let's sort out the operands..
1189 | 				int operandLoop = 0;
1190 | 				while ( ( pCurrentOpcode->operands[ operandLoop ] != 0 ) && ( operandLoop < MAX_OPERANDS ) )
1191 | 				{
1192 | 					op_t*				operandData = &cmd.Operands[ operandLoop ];
1193 | 					altivec_operand*	pCurrentOperand = &g_altivecOperands[ pCurrentOpcode->operands[ operandLoop ] ];
1194 | 
1195 | 					int	rawBits			=	( codeBytes >> pCurrentOperand->shift ) & ( ( 1 <<  pCurrentOperand->bits ) - 1 );
1196 | 					int	extendedBits	=	( rawBits << ( 32 - pCurrentOperand->bits ) ) >> ( 32 - pCurrentOperand->bits );
1197 | 
1198 | 					switch ( pCurrentOpcode->operands[ operandLoop ] )
1199 | 					{
1200 | 						// These are the main Altivec registers
1201 | 						case	VA:
1202 | 						case	VB:
1203 | 						case	VC:
1204 | 						case	VD:	// VS
1205 | 						{
1206 | 							operandData->type		=	o_reg;
1207 | 							operandData->reg		=	rawBits;
1208 | 							operandData->specflag1	=	0x01;		// Mark the register as being an Altivec one.
1209 | 							break;
1210 | 						}
1211 | 	
1212 | 						// Signed immediate (extendedBits is sign extended into 32 bits)
1213 | 						case	SIMM:
1214 | 						{
1215 | 							operandData->type	=	o_imm;
1216 | 							operandData->dtyp	=	dt_byte;
1217 | 							operandData->value	=	extendedBits;
1218 | 							break;
1219 | 						}
1220 | 
1221 | 						// Unsigned immediate
1222 | 						case	UIMM:
1223 | 						{
1224 | 							operandData->type	=	o_imm;
1225 | 							operandData->dtyp	=	dt_byte;
1226 | 							operandData->value	=	rawBits;
1227 | 							break;
1228 | 						}
1229 | 
1230 | 						// Shift values are the same as unsigned immediates, but we separate for clarity
1231 | 						case	SHB:
1232 | 						{
1233 | 							operandData->type	=	o_imm;
1234 | 							operandData->dtyp	=	dt_byte;
1235 | 							operandData->value	=	rawBits;
1236 | 							break;
1237 | 						}
1238 | 
1239 | 						// Altivec memory loads are always via a CPU register
1240 | 						case	RA:
1241 | 						case	RB:
1242 | 						{
1243 | 							operandData->type		=	o_reg;
1244 | 							operandData->reg		=	rawBits;
1245 | 							operandData->specflag1	=	0x00;
1246 | 							break;
1247 | 						}
1248 | 
1249 | 						// Altivec data stream ID
1250 | 						case	STRM:
1251 | 						{
1252 | 							operandData->type	=	o_imm;
1253 | 							operandData->dtyp	=	dt_byte;
1254 | 							operandData->value	=	rawBits;
1255 | 							break;
1256 | 						}
1257 | 						
1258 | 						// Takires: Added operands
1259 | 						case	L9_10:
1260 | 						case	L10:
1261 | 						case	L15:
1262 | 						{
1263 | 							operandData->type	=	o_imm;
1264 | 							operandData->dtyp	=	dt_byte;
1265 | 							operandData->value	=	rawBits;
1266 | 							break;
1267 | 						}
1268 | 
1269 | 						case	RS:		// also RT
1270 | 						{
1271 | 							operandData->type		=	o_reg;
1272 | 							operandData->reg		=	rawBits;
1273 | 							operandData->specflag1	=	0x00;
1274 | 							break;
1275 | 						}
1276 | 						
1277 | 						case	VD128:	// also VS128
1278 | 						{
1279 | 							operandData->type		=	o_reg;
1280 | 							operandData->reg		=	((codeBytes >> 21) & 0x1F) | ((codeBytes & 0x0C) << 3);
1281 | 							operandData->specflag1	=	0x01;		// Mark the register as being an Altivec one.
1282 | 							break;
1283 | 						}
1284 | 
1285 | 						case	VA128:
1286 | 						{
1287 | 							operandData->type		=	o_reg;
1288 | 							operandData->reg		=	((codeBytes >> 16) & 0x1F) | (codeBytes & 0x20) | ((codeBytes >> 4) & 0x40);
1289 | 							operandData->specflag1	=	0x01;		// Mark the register as being an Altivec one.
1290 | 							break;
1291 | 						}
1292 | 
1293 | 						case	VB128:
1294 | 						{
1295 | 							operandData->type		=	o_reg;
1296 | 							operandData->reg		=	((codeBytes << 5) & 0x60) | ((codeBytes >> 11) & 0x1F);
1297 | 							operandData->specflag1	=	0x01;		// Mark the register as being an Altivec one.
1298 | 							break;
1299 | 						}
1300 | 
1301 | 						case	VC128:
1302 | 						{
1303 | 							operandData->type		=	o_reg;
1304 | 							operandData->reg		=	rawBits;
1305 | 							operandData->specflag1	=	0x01;
1306 | 							break;
1307 | 						}
1308 | 
1309 | 						case	CRM:
1310 | 						{
1311 | 							operandData->type		=	o_reg;
1312 | 							operandData->reg		=	rawBits;
1313 | 							operandData->specflag1	=	0x02;		// Mark the register as being a CRF.
1314 | 							break;
1315 | 						}
1316 | 
1317 | 						case	VPERM128:
1318 | 						{
1319 | 							operandData->type		=	o_imm;
1320 | 							operandData->dtyp		=	dt_byte;
1321 | 							operandData->value		=	((codeBytes >> 1) & 0xE0) | ((codeBytes >> 16) & 0x1F);
1322 | 							break;
1323 | 						}
1324 | 		
1325 | 						case	VD3D0:
1326 | 						case	VD3D1:
1327 | 						case	VD3D2:
1328 | 						{
1329 | 							operandData->type		=	o_imm;
1330 | 							operandData->dtyp		=	dt_byte;
1331 | 							operandData->value		=	rawBits;
1332 | 							break;
1333 | 						}
1334 | 	
1335 | 						case	RA0:
1336 | 						{
1337 | 							if(rawBits == 0)
1338 | 							{
1339 | 							operandData->type		=	o_imm;
1340 | 							operandData->dtyp		=	dt_byte;
1341 | 							operandData->value		=	rawBits;
1342 | 							}
1343 | 							else
1344 | 							{
1345 | 							operandData->type		=	o_reg;
1346 | 							operandData->reg		=	rawBits;
1347 | 							operandData->specflag1	=	0;
1348 | 							}
1349 | 							break;
1350 | 						}
1351 | 						
1352 | 						case	SPR:
1353 | 						{
1354 | 							operandData->type		=	o_reg;
1355 | 							operandData->reg		=	(((rawBits & 0x3e0)>>5) + ((rawBits&0x1f)<<5));
1356 | 							operandData->specflag1	=	0x04;		// Mark the register as being a SPR.
1357 | 							break;
1358 | 						}
1359 | 
1360 | 
1361 | 						// gekko specific
1362 | 						
1363 | 						// These are the main Gekko registers
1364 | 						case	FA:
1365 | 						case	FB:
1366 | 						case	FC:
1367 | 						case	FD://FS
1368 | 						//case	FS:
1369 | 						{
1370 | 							operandData->type		=	o_reg;
1371 | 							operandData->reg		=	rawBits;
1372 | 							operandData->specflag1	=	0x08;		// Mark the register as being a Gekko one.
1373 | 							break;
1374 | 						}
1375 | 	
1376 | 						case	crfD:
1377 | 						case	WB:
1378 | 						case	IB:
1379 | 						case	WC:
1380 | 						case	IC:
1381 | 						{
1382 | 							operandData->type	=	o_imm;
1383 | 							operandData->dtyp	=	dt_byte;
1384 | 							operandData->value	=	rawBits;
1385 | 							break;
1386 | 						}
1387 | 
1388 | 						case	DRA:
1389 | 						{
1390 | 							unsigned short imm	= (unsigned short)(codeBytes & 0x7FF);
1391 | 							unsigned short sign = (unsigned short)(codeBytes & 0x800);
1392 | 							short displacement = 0;
1393 | 
1394 | 							if (sign == 0)
1395 | 								displacement = imm;
1396 | 							else
1397 | 								displacement = -1 * imm;
1398 | 
1399 | 
1400 | 							operandData->type	=	o_displ;
1401 | 							operandData->phrase	=	rawBits;
1402 | 							operandData->addr	=	displacement;
1403 | 
1404 | 							break;
1405 | 						}
1406 | 
1407 | 
1408 | 						default:
1409 | 							break;
1410 | 					}	
1411 | 
1412 | 					// Next operand please..
1413 | 					operandLoop++;
1414 | 				}
1415 | 
1416 | 				// Make a note of which opcode we are.. we need it to print our stuff out.
1417 | 				cmd.itype	= pCurrentOpcode->insn;
1418 | 
1419 | 				// The command is 4 bytes long.. 
1420 | 				return 4;
1421 | 			}	
1422 | 	
1423 | 			// We obviously didn't find our opcode this time round.. go test the next one.
1424 | 			pCurrentOpcode++;
1425 | 		}
1426 | 	}
1427 | 
1428 | 	// We didn't do anything.. honest.	
1429 | 	return 0;
1430 | }
1431 | 
1432 | 
1433 | /***************************************************************************************************
1434 | *
1435 | *	FUNCTION		PluginExtensionCallback
1436 | *
1437 | *	DESCRIPTION		This callback is responsible for distributing work associated with each
1438 | *					intercepted event that we deal with. In our case we deal with the following
1439 | *					event identifiers.
1440 | *
1441 | *					custom_ana		:	Analyses a command (in 'cmd') to see if it is an Altivec 
1442 | *										instruction. If so, then it extracts information from the 
1443 | *										opcode in order to determine which opcode it is, along with
1444 | *										data relating to any used operands.
1445 | *
1446 | *					custom_mnem		:	Generates the mnemonic for our Altivec instructions, by looking
1447 | *										into our array of opcode information structures.
1448 | *
1449 | *					custom_outop	:	Outputs operands for Altivec instructions. In our case, we
1450 | *										have an alternate register set (vr0 to vr31), so our operands
1451 | *										may be marked as being Altivec registers.
1452 | *
1453 | *					may_be_func		:	It's perfectly OK for an Altivec instruction to be the start
1454 | *										of a function, so I figured I should return 100 here. The
1455 | *										return value is a percentage probability.. 
1456 | *
1457 | *					is_sane_insn	:	All our Altivec instructions (well, the ones we've identified
1458 | *										inside custom_ana processing), are ok.	
1459 | *
1460 | ***************************************************************************************************/
1461 | 
1462 | static int idaapi PluginExtensionCallback( void * /*user_data*/, int event_id, va_list va )
1463 | {
1464 | 	switch ( event_id )
1465 | 	{
1466 | 		// Analyse a command to see if it's an Altivec instruction.
1467 | 		case ph.custom_ana:
1468 | 		{
1469 | 			int length = PluginAnalyse();
1470 | 			if ( length )
1471 | 			{
1472 | 				cmd.size = length;
1473 | 				//return ( length + 1 );       // event processed
1474 | 				return ( length );       // event processed
1475 | 			}
1476 | 			break;
1477 | 		}
1478 | 	
1479 | 		// Obtain mnemonic for our Altivec instructions.
1480 | 		case ph.custom_mnem:
1481 | 		{
1482 | 			if ( cmd.itype >= CUSTOM_CMD_ITYPE )
1483 | 			{
1484 | 				char *buf   = va_arg(va, char *);
1485 | 				size_t size = va_arg(va, size_t);
1486 | 				qstrncpy(buf, g_altivecOpcodes[ cmd.itype - altivec_lvebx ].name, size);
1487 | 				return 2;
1488 | 			}
1489 | 			break;
1490 | 		}
1491 | 
1492 | 		// Display operands that differ from PPC ones.. like our Altivec registers.
1493 | 		case ph.custom_outop:
1494 | 		{
1495 | 			if ( cmd.itype >= CUSTOM_CMD_ITYPE )
1496 | 			{
1497 | 				op_t* operand = va_arg( va, op_t* );
1498 | 				if ( ( operand->type == o_reg ) && ( operand->specflag1 & 0x01 ) )
1499 | 				{
1500 | 					char buf[ MAXSTR ];
1501 | 					_snprintf_s( buf, MAXSTR, "%%vr%d", operand->reg );					
1502 | 					out_register( buf );
1503 | 					return 2;
1504 | 				} 
1505 | 				else if ( ( operand->type == o_reg ) && ( operand->specflag1 & 0x02 ) )
1506 | 				{
1507 | 					char buf[ MAXSTR ];
1508 | 					for (int i = 0; i < 8; i++)
1509 | 					{
1510 | 						if (operand->reg & (1 << i))
1511 | 						{
1512 | 							_snprintf_s( buf, MAXSTR, "cr%d", 7 - i );
1513 | 							out_register( buf );
1514 | 							break;
1515 | 						}
1516 | 					}
1517 | 					return 2;
1518 | 				}
1519 | 				// decode SPR Values
1520 | 				else if ( ( operand->type == o_reg ) && ( operand->specflag1 & 0x04 ) )
1521 | 				{
1522 | 					int	sprgArraySize = sizeof( g_cbeaSprgs ) / sizeof( cbea_sprg );
1523 | 					cbea_sprg*	pCurrentSprg	= g_cbeaSprgs;
1524 | 
1525 | 					// Go through the entire special register array looking for a match
1526 | 					for ( int sprgLoop = 0; sprgLoop < sprgArraySize; sprgLoop++ )
1527 | 					{
1528 | 						if(operand->reg == g_cbeaSprgs[sprgLoop].sprg)
1529 | 						{
1530 | 							out_register( g_cbeaSprgs[sprgLoop].shortName);
1531 | 							return 2;
1532 | 						}
1533 | 
1534 | 					}
1535 | 					char buf[ MAXSTR ];
1536 | 					_snprintf_s( buf, MAXSTR, "%x", operand->reg );					
1537 | 					out_register( buf );
1538 | 					return 2;
1539 | 				}
1540 | 				// decode fr values (gekko)
1541 | 				else if ( ( operand->type == o_reg ) && ( operand->specflag1 & 0x08 ) )
1542 | 				{
1543 | 					char buf[ MAXSTR ];
1544 | 					_snprintf_s( buf, MAXSTR, "%%fr%d", operand->reg );					
1545 | 					out_register( buf );
1546 | 					return 2;
1547 | 				}
1548 | 			}
1549 | 			break;
1550 | 		}
1551 | 
1552 | 		// Custom output
1553 | 		case ph.custom_out:
1554 | 		{
1555 | 			if ( cmd.itype >= CUSTOM_CMD_ITYPE )
1556 | 			{
1557 | 				char buf[ MAXSTR ];	
1558 | 				init_output_buffer( buf, sizeof( buf ) );
1559 | 		
1560 | 				// Output mnemonic
1561 | 				OutMnem();
1562 | 
1563 | 				// Output operands
1564 | 				if ( cmd.Op1.showed() && cmd.Op1.type != o_void )
1565 | 				{
1566 | 					 out_one_operand( 0 );
1567 | 				}
1568 | 
1569 | 				if ( cmd.Op2.showed() && cmd.Op2.type != o_void )
1570 | 				{
1571 | 					if ( cmd.Op1.showed() )
1572 | 					{
1573 | 						out_symbol(',');
1574 | 						OutChar(' ');
1575 | 					}
1576 | 					out_one_operand( 1 );
1577 | 				}
1578 | 				
1579 | 				if ( cmd.Op3.showed() && cmd.Op3.type != o_void )
1580 | 				{
1581 | 					if ( cmd.Op1.showed() || cmd.Op2.showed() )
1582 | 					{
1583 | 						out_symbol(',');
1584 | 						OutChar(' ');
1585 | 					}
1586 | 					out_one_operand( 2 );
1587 | 				}
1588 | 
1589 | 				if ( cmd.Op4.showed() && cmd.Op4.type != o_void )
1590 | 				{
1591 | 					if ( cmd.Op1.showed() || cmd.Op2.showed() || cmd.Op3.showed() )
1592 | 					{
1593 | 						out_symbol(',');
1594 | 						OutChar(' ');
1595 | 					}
1596 | 					out_one_operand( 3 );
1597 | 				}
1598 | 
1599 | 				if ( cmd.Op5.showed() && cmd.Op5.type != o_void )
1600 | 				{
1601 | 					if ( cmd.Op1.showed() || cmd.Op2.showed() || cmd.Op3.showed() || cmd.Op4.showed() )
1602 | 					{
1603 | 						out_symbol(',');
1604 | 						OutChar(' ');
1605 | 					}
1606 | 					out_one_operand( 4 );
1607 | 				}
1608 | 
1609 | 				// Output auto comments
1610 | 				if ( showAllComments() && ( get_cmt( cmd.ea, true, NULL, 0 ) == -1 ) )
1611 | 				{
1612 | 					for ( int indentLoop = (int)tag_strlen( buf ); indentLoop < ( inf.comment - inf.indent ); indentLoop++ )
1613 | 						OutChar(' ');
1614 | 					out_line( "# ", COLOR_AUTOCMT );
1615 | 					out_line( g_altivecOpcodes[ cmd.itype - altivec_lvebx ].description, COLOR_AUTOCMT );// add a check for sprg
1616 | 				}
1617 | 				//else
1618 | 					gl_comm = 1;
1619 | 
1620 | 				term_output_buffer();
1621 | 
1622 | 				MakeLine(buf);
1623 | 				return 2;
1624 | 			}
1625 | 			break;
1626 | 		}
1627 | 
1628 | 		// Can this be the start of a function? 
1629 | 		case ph.may_be_func:
1630 | 		{
1631 | 			if ( cmd.itype >= CUSTOM_CMD_ITYPE )
1632 | 			{
1633 | 				return 100;
1634 | 			}
1635 | 			break;
1636 | 		}
1637 | 
1638 | 		// If we've identified the command as an Altivec instruction, it's good to go.
1639 | 		case ph.is_sane_insn:
1640 | 		{
1641 | 			if ( cmd.itype >= CUSTOM_CMD_ITYPE )
1642 | 			{
1643 | 				return 1;
1644 | 			}
1645 | 		}
1646 | 	}
1647 | 
1648 | 	// We didn't process the event.. just let IDA handle it.
1649 | 	return 0;
1650 | }
1651 | 
1652 | 
1653 | /***************************************************************************************************
1654 | *
1655 | *	FUNCTION		PluginStartup
1656 | *
1657 | *	DESCRIPTION		IDA will call this function only once. If this function returns PLUGIN_SKIP,
1658 | *					IDA will never load it again. If it returns PLUGIN_OK, IDA will unload the plugin
1659 | *					but remember that the plugin agreed to work with the database. The plugin will
1660 | *					be loaded again if the user invokes it by pressing the hotkey or selecting it
1661 | *					from the menu. After the second load, the plugin will stay in memory.
1662 | *
1663 | *	NOTES			In our Altivec case, we just hook into IDA'S callbacks if we need to be active
1664 | *					on plugin load. 
1665 | *
1666 | ***************************************************************************************************/
1667 | 
1668 | int idaapi PluginStartup(void)
1669 | {
1670 | 	if ( ph.id != PLFM_PPC )
1671 | 		return PLUGIN_SKIP;
1672 | 
1673 | 	// Debug stuff to identify auto-comment status
1674 | //	if ( showAllComments() )
1675 | //		msg( "All comments enabled\n" );
1676 | //	else
1677 | //		msg( "All comments disabled\n" );
1678 | 	
1679 | 	// Create our node...
1680 | 	g_AltivecNode.create( g_AltivecNodeName );
1681 | 
1682 | 	// Retrieve any existing hook state that may be in the database.
1683 | 	HookState	databaseHookState = ( HookState )g_AltivecNode.altval( 0 );
1684 | 
1685 | 	// altval() returns 0 (which maps to kDefault) when the value isn't there.. so handle it.
1686 | 	if ( databaseHookState != kDefault )
1687 | 		g_HookState = databaseHookState;	
1688 | 
1689 | 	if ( g_HookState == kEnabled )
1690 | 	{
1691 | 		hook_to_notification_point( HT_IDP, PluginExtensionCallback, NULL );
1692 | 		msg( "%s is enabled\n", g_pluginName);
1693 | 		return PLUGIN_KEEP;
1694 | 	}
1695 | 	
1696 | 	return PLUGIN_OK;
1697 | }
1698 | 
1699 | /***************************************************************************************************
1700 | *
1701 | *	FUNCTION		PluginShutdown
1702 | *
1703 | *	DESCRIPTION		IDA will call this function when the user asks to exit. This function is *not*
1704 | *					called in the case of emergency exits.
1705 | *
1706 | *   NOTES			All we can do here is to release from our callbacks..
1707 | *
1708 | ***************************************************************************************************/
1709 | 
1710 | void idaapi PluginShutdown(void)
1711 | {
1712 | 	unhook_from_notification_point( HT_IDP, PluginExtensionCallback );
1713 | }
1714 | 
1715 | 
1716 | /***************************************************************************************************
1717 | *
1718 | *	FUNCTION		PluginMain
1719 | *
1720 | *	DESCRIPTION		Our plugin is all about hooking callbacks.. 
1721 | *
1722 | ***************************************************************************************************/
1723 | 
1724 | void idaapi PluginMain(int param)
1725 | {
1726 | 	if ( g_HookState == kEnabled )
1727 | 	{
1728 | 		unhook_from_notification_point( HT_IDP, PluginExtensionCallback );
1729 | 		g_HookState = kDisabled;
1730 | 	}
1731 | 	else
1732 | 	if ( g_HookState == kDisabled )
1733 | 	{
1734 | 		hook_to_notification_point( HT_IDP, PluginExtensionCallback, NULL );
1735 | 		g_HookState = kEnabled;
1736 | 	}
1737 | 
1738 | 	g_AltivecNode.create( g_AltivecNodeName );
1739 | 	g_AltivecNode.altset( 0, g_HookState );
1740 | 
1741 | 	static const char* pHookStateDescription[] = 
1742 | 	{
1743 | 		"default",
1744 | 		"enabled",
1745 | 		"disabled",
1746 | 	};
1747 | 
1748 | 	info(	"AUTOHIDE NONE\n"
1749 | 			"%s is now %s", g_pluginName, pHookStateDescription[ g_HookState ] );
1750 | }
1751 | 
1752 | 
1753 | /***************************************************************************************************
1754 | *
1755 | *	This 'PLUGIN' data block is how IDA Pro interfaces with this plugin.
1756 | *
1757 | ***************************************************************************************************/
1758 | plugin_t PLUGIN =
1759 | {
1760 | 	IDP_INTERFACE_VERSION,
1761 | 	0,						// plugin flags	
1762 | 	
1763 | 	PluginStartup,			// initialize
1764 | 	PluginShutdown,			// terminate. this pointer may be NULL.
1765 | 	PluginMain,				// invoke plugin
1766 | 	
1767 | 	g_pluginName,			// long comment about the plugin. It could appear in the status line or as a hint
1768 | 	g_pluginHelp,			// multiline help about the plugin
1769 | 	g_pluginName,			// the preferred short name of the plugin
1770 | 	""						// the preferred hotkey to run the plugin
1771 | };
1772 | 


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