├── Block_LMS_Simulation └── BLMS.srcs │ ├── sources_1 │ ├── ip │ │ └── clk_wiz_0 │ │ │ ├── clk_wiz_0_board.xdc │ │ │ ├── clk_wiz_0_ooc.xdc │ │ │ ├── clk_wiz_0.xdc │ │ │ ├── clk_wiz_0.veo │ │ │ └── clk_wiz_0.v │ └── new │ │ ├── lfsr.v │ │ ├── Data_Mult4.v │ │ ├── Data_Div4.v │ │ ├── BLMS_ECU.v │ │ ├── FIR_Filter.v │ │ └── ToneGen.v │ └── sim_1 │ └── new │ └── BLMS_TB.v ├── Block_FIR_Simulation └── Block_FIR.srcs │ ├── sources_1 │ ├── ip │ │ └── clk_wiz_0 │ │ │ ├── clk_wiz_0_board.xdc │ │ │ ├── clk_wiz_0_ooc.xdc │ │ │ ├── clk_wiz_0.xdc │ │ │ ├── clk_wiz_0.veo │ │ │ └── clk_wiz_0.v │ └── new │ │ ├── Data_Mult4.v │ │ ├── Data_Div4.v │ │ ├── FIR_Filter.v │ │ ├── ToneGen.v │ │ └── Block_FIR_Top.v │ └── sim_1 │ └── new │ └── Block_FIR_TB.v ├── Block_LMS_Implementation └── BLMS.srcs │ ├── sources_1 │ ├── ip │ │ └── clk_wiz_0 │ │ │ ├── clk_wiz_0_board.xdc │ │ │ ├── clk_wiz_0_ooc.xdc │ │ │ ├── clk_wiz_0.xdc │ │ │ ├── clk_wiz_0.veo │ │ │ └── clk_wiz_0.v │ └── new │ │ ├── lfsr.v │ │ ├── Data_Mult4.v │ │ ├── Data_Div4.v │ │ ├── BLMS_ECU.v │ │ ├── FIR_Filter.v │ │ └── ToneGen.v │ └── sim_1 │ └── new │ └── BLMS_TB.v ├── Block_FIR_Implementation └── Block_FIR.srcs │ ├── sources_1 │ ├── ip │ │ └── clk_wiz_0 │ │ │ ├── clk_wiz_0_board.xdc │ │ │ ├── clk_wiz_0_ooc.xdc │ │ │ ├── clk_wiz_0.xdc │ │ │ ├── clk_wiz_0.veo │ │ │ └── clk_wiz_0.v │ └── new │ │ ├── Data_Mult4.v │ │ ├── Data_Div4.v │ │ ├── FIR_Filter.v │ │ └── ToneGen.v │ └── sim_1 │ └── new │ └── Block_FIR_TB.v ├── FIR_Simulation ├── project_1 │ └── project_1.srcs │ │ ├── sources_1 │ │ ├── ip │ │ │ └── clk_wiz_0 │ │ │ │ ├── clk_wiz_0_board.xdc │ │ │ │ ├── clk_wiz_0.dcp │ │ │ │ ├── clk_wiz_0_stub.v │ │ │ │ ├── clk_wiz_0_stub.vhdl │ │ │ │ ├── clk_wiz_0_ooc.xdc │ │ │ │ ├── clk_wiz_0.xdc │ │ │ │ ├── clk_wiz_0.veo │ │ │ │ └── clk_wiz_0.v │ │ └── new │ │ │ ├── clk_en.v │ │ │ ├── filter_top.v │ │ │ └── FIR_Filter.v │ │ └── sim_1 │ │ └── new │ │ └── TB_ToneGen.v └── ToneGen.v ├── LMS_Simulation ├── LMS_Adaptive_Filter.srcs │ └── sources_1 │ │ └── ip │ │ └── clk_wiz_0 │ │ ├── clk_wiz_0_board.xdc │ │ ├── clk_wiz_0.dcp │ │ ├── clk_wiz_0_stub.v │ │ ├── clk_wiz_0_stub.vhdl │ │ ├── clk_wiz_0_ooc.xdc │ │ ├── clk_wiz_0.xdc │ │ ├── clk_wiz_0.veo │ │ └── clk_wiz_0.v ├── clk_en.v ├── TB_LMS_Adapt.v ├── lfsr.v ├── delay_line.v ├── filter_top.v ├── FIR_Filter.v ├── LMS_Adapt.v └── ToneGen.v ├── FIR_Implementation ├── project_1 │ └── project_1.srcs │ │ ├── sources_1 │ │ ├── ip │ │ │ └── clk_wiz_0 │ │ │ │ ├── clk_wiz_0_board.xdc │ │ │ │ ├── clk_wiz_0_ooc.xdc │ │ │ │ ├── clk_wiz_0.xdc │ │ │ │ ├── clk_wiz_0.veo │ │ │ │ └── clk_wiz_0.v │ │ └── new │ │ │ ├── clk_en.v │ │ │ ├── filter_top.v │ │ │ └── FIR_Filter.v │ │ └── sim_1 │ │ └── new │ │ └── TB_ToneGen.v └── ToneGen.v ├── LMS_Implementation ├── LMS_Adaptive_Filter.srcs │ └── sources_1 │ │ └── ip │ │ └── clk_wiz_0 │ │ ├── clk_wiz_0_board.xdc │ │ ├── clk_wiz_0.dcp │ │ ├── clk_wiz_0_stub.v │ │ ├── clk_wiz_0_stub.vhdl │ │ ├── clk_wiz_0_ooc.xdc │ │ ├── clk_wiz_0.xdc │ │ ├── clk_wiz_0.veo │ │ └── clk_wiz_0.v ├── clk_en.v ├── TB_LMS_Adapt.v ├── lfsr.v ├── delay_line.v ├── filter_top.v ├── FIR_Filter.v ├── LMS_Adapt.v └── ToneGen.v ├── README.md ├── Presentation └── Filter+Implementation+on+a+FPGA+Board_Xueyan+Lu_06152017.pdf └── .gitignore /Block_LMS_Simulation/BLMS.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /Block_FIR_Simulation/Block_FIR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /Block_LMS_Implementation/BLMS.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /Block_FIR_Implementation/Block_FIR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /FIR_Simulation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /LMS_Simulation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /FIR_Implementation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /LMS_Implementation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # fpga-filter-implementation 2 | FIR and LMS filter implementations in FPGAs 3 | 4 | # NOTE 5 | This project is part of my project portfolio: https://nmikstas.github.io/portfolio/ 6 | -------------------------------------------------------------------------------- /Presentation/Filter+Implementation+on+a+FPGA+Board_Xueyan+Lu_06152017.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nmikstas/fpga-filter-implementation/HEAD/Presentation/Filter+Implementation+on+a+FPGA+Board_Xueyan+Lu_06152017.pdf -------------------------------------------------------------------------------- /FIR_Simulation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nmikstas/fpga-filter-implementation/HEAD/FIR_Simulation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp -------------------------------------------------------------------------------- /LMS_Simulation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nmikstas/fpga-filter-implementation/HEAD/LMS_Simulation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp -------------------------------------------------------------------------------- /LMS_Implementation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nmikstas/fpga-filter-implementation/HEAD/LMS_Implementation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp -------------------------------------------------------------------------------- /FIR_Simulation/project_1/project_1.srcs/sim_1/new/TB_ToneGen.v: -------------------------------------------------------------------------------- 1 | module TB_ToneGen; 2 | 3 | reg clk = 1'b0; 4 | reg sw0 = 1'b0; 5 | wire [7:0]JA; 6 | 7 | filter_top uut(.clk(clk), .sw({15'h00,sw0}), .JA(JA)); 8 | 9 | initial begin 10 | #50000 sw0 = 1'b1; 11 | end 12 | 13 | //100MHz clock 14 | always #5 clk = ~clk; 15 | endmodule 16 | -------------------------------------------------------------------------------- /Block_FIR_Simulation/Block_FIR.srcs/sim_1/new/Block_FIR_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Block_FIR_TB; 4 | reg clk = 1'b0; 5 | reg [7:0]sw = 8'd0; 6 | wire [7:0]JA; 7 | 8 | Block_FIR_Top uut(.clk(clk), .sw(sw), .JA(JA)); 9 | 10 | initial begin 11 | #50000 sw = 8'd1; 12 | end 13 | 14 | always #5 clk = ~clk; 15 | endmodule 16 | -------------------------------------------------------------------------------- /Block_FIR_Implementation/Block_FIR.srcs/sim_1/new/Block_FIR_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Block_FIR_TB; 4 | reg clk = 1'b0; 5 | reg [7:0]sw = 8'd0; 6 | wire [7:0]JA; 7 | 8 | Block_FIR_Top uut(.clk(clk), .sw(sw), .JA(JA)); 9 | 10 | initial begin 11 | #50000 sw = 8'd1; 12 | end 13 | 14 | always #5 clk = ~clk; 15 | endmodule 16 | -------------------------------------------------------------------------------- /LMS_Simulation/clk_en.v: -------------------------------------------------------------------------------- 1 | module clk_en( 2 | input clk, 3 | output reg en = 1'b0 4 | ); 5 | 6 | reg [15:0]en_counter = 16'h0; 7 | 8 | always @(posedge clk) begin 9 | if(en_counter == 16'd449) begin 10 | en_counter <= 16'h0; 11 | en <= 1'b1; 12 | end 13 | else begin 14 | en_counter <= en_counter + 1'b1; 15 | en <= 1'b0; 16 | end 17 | end 18 | 19 | endmodule -------------------------------------------------------------------------------- /LMS_Implementation/clk_en.v: -------------------------------------------------------------------------------- 1 | module clk_en( 2 | input clk, 3 | output reg en = 1'b0 4 | ); 5 | 6 | reg [15:0]en_counter = 16'h0; 7 | 8 | always @(posedge clk) begin 9 | if(en_counter == 16'd449) begin 10 | en_counter <= 16'h0; 11 | en <= 1'b1; 12 | end 13 | else begin 14 | en_counter <= en_counter + 1'b1; 15 | en <= 1'b0; 16 | end 17 | end 18 | 19 | endmodule -------------------------------------------------------------------------------- /FIR_Simulation/project_1/project_1.srcs/sources_1/new/clk_en.v: -------------------------------------------------------------------------------- 1 | module clk_en( 2 | input clk, 3 | output reg en = 1'b0 4 | ); 5 | 6 | reg [15:0]en_counter = 16'h0; 7 | 8 | always @(posedge clk) begin 9 | if(en_counter == 16'd5999) begin 10 | en_counter <= 16'h0; 11 | en <= 1'b1; 12 | end 13 | else begin 14 | en_counter <= en_counter + 1'b1; 15 | en <= 1'b0; 16 | end 17 | end 18 | 19 | endmodule -------------------------------------------------------------------------------- /FIR_Implementation/project_1/project_1.srcs/sources_1/new/clk_en.v: -------------------------------------------------------------------------------- 1 | module clk_en( 2 | input clk, 3 | output reg en = 1'b0 4 | ); 5 | 6 | reg [15:0]en_counter = 16'h0; 7 | 8 | always @(posedge clk) begin 9 | if(en_counter == 16'd5999) begin 10 | en_counter <= 16'h0; 11 | en <= 1'b1; 12 | end 13 | else begin 14 | en_counter <= en_counter + 1'b1; 15 | en <= 1'b0; 16 | end 17 | end 18 | 19 | endmodule -------------------------------------------------------------------------------- /FIR_Implementation/project_1/project_1.srcs/sim_1/new/TB_ToneGen.v: -------------------------------------------------------------------------------- 1 | module TB_ToneGen; 2 | 3 | reg clk = 1'b0; 4 | reg sw0 = 1'b1; 5 | wire [7:0]JA; 6 | 7 | wire en; 8 | //wire [15:0]cout; 9 | 10 | filter_top uut(.clk(clk), .sw({15'h00,sw0}), .JA({JA[3:0], JA[7:4]})); 11 | 12 | assign en = uut.en; 13 | //assign cout = uut.ce.en_counter; 14 | 15 | //initial begin 16 | // #600000 sw0 = 1'b1; 17 | //end 18 | 19 | //100MHz clock 20 | always #5 clk = ~clk; 21 | endmodule 22 | -------------------------------------------------------------------------------- /LMS_Simulation/TB_LMS_Adapt.v: -------------------------------------------------------------------------------- 1 | module TB_LMS_Adapt; 2 | 3 | reg clk = 1'b0; 4 | reg [7:0]sw = 1'b0; 5 | wire [7:0]JA; 6 | 7 | wire [15:0]d; 8 | wire [15:0]y; 9 | wire [15:0]e; 10 | wire [15:0]n1; 11 | 12 | filter_top uut(.clk(clk), .sw(sw), .JA(JA)); 13 | 14 | assign d = uut.fout; 15 | assign y = uut.aout; 16 | assign e = uut.err; 17 | assign n1 = uut.af.n1[0]; 18 | 19 | always #5 clk = ~clk; 20 | 21 | initial begin 22 | #40000 sw[0] = 1'b1; 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /Block_LMS_Simulation/BLMS.srcs/sim_1/new/BLMS_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module BLMS_TB; 4 | reg clk = 1'b0; 5 | reg [7:0]sw = 8'd0; 6 | wire [7:0]JA; 7 | 8 | wire clk_50MHz; 9 | wire clk_25MHz; 10 | wire en; 11 | 12 | BLMS_Top uut(.clk(clk), .sw(sw), .JA(JA)); 13 | 14 | assign clk_50MHz = uut.clk_50MHz; 15 | assign clk_25MHz = uut.clk_25MHz; 16 | assign en = uut.en; 17 | 18 | //Generate 100MHz clock. 19 | always #5 clk = ~clk; 20 | 21 | initial begin 22 | #50000 sw = 8'd1; 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /LMS_Implementation/TB_LMS_Adapt.v: -------------------------------------------------------------------------------- 1 | module TB_LMS_Adapt; 2 | 3 | reg clk = 1'b0; 4 | reg [7:0]sw = 1'b1; 5 | wire [7:0]JA; 6 | 7 | wire [15:0]d; 8 | wire [15:0]y; 9 | wire [15:0]e; 10 | wire [15:0]n1; 11 | 12 | filter_top uut(.clk(clk), .sw(sw), .JA(JA)); 13 | 14 | assign d = uut.fout; 15 | assign y = uut.aout; 16 | assign e = uut.err; 17 | assign n1 = uut.af.n1[0]; 18 | 19 | always #5 clk = ~clk; 20 | 21 | initial begin 22 | //#20000000 sw[0] = 1'b1; 23 | //#40000 sw[0] = 1'b1; 24 | end 25 | endmodule 26 | -------------------------------------------------------------------------------- /LMS_Simulation/lfsr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lfsr( 4 | input clk, 5 | input en, 6 | input rst, 7 | output [15:0]lfsr_out 8 | ); 9 | 10 | //Create a 16-bit linear feedback shift register with 11 | //maximal polynomial x^16 + x^14 + x^13 + x^11 + 1. 12 | reg [15:0]lfsr = 16'd1; 13 | wire feedback; 14 | 15 | assign feedback = ((lfsr[15] ^ lfsr[13]) ^ lfsr[12]) ^ lfsr[10]; 16 | assign lfsr_out = lfsr; 17 | 18 | //Update the linear shift feedback register. 19 | always @(posedge clk) begin 20 | if(rst) lfsr <= 16'd1; 21 | else if(en) lfsr <= {lfsr[14:0], feedback}; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /LMS_Implementation/lfsr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lfsr( 4 | input clk, 5 | input en, 6 | input rst, 7 | output [15:0]lfsr_out 8 | ); 9 | 10 | //Create a 16-bit linear feedback shift register with 11 | //maximal polynomial x^16 + x^14 + x^13 + x^11 + 1. 12 | reg [15:0]lfsr = 16'd1; 13 | wire feedback; 14 | 15 | assign feedback = ((lfsr[15] ^ lfsr[13]) ^ lfsr[12]) ^ lfsr[10]; 16 | assign lfsr_out = lfsr; 17 | 18 | //Update the linear feedback shift register. 19 | always @(posedge clk) begin 20 | if(rst) lfsr <= 16'd1; 21 | else if(en) lfsr <= {lfsr[14:0], feedback}; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /Block_LMS_Simulation/BLMS.srcs/sources_1/new/lfsr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lfsr( 4 | input clk, 5 | input en, 6 | input rst, 7 | output [15:0]lfsr_out 8 | ); 9 | 10 | //Create a 16-bit linear feedback shift register with 11 | //maximal polynomial x^16 + x^14 + x^13 + x^11 + 1. 12 | reg [15:0]lfsr = 16'd1; 13 | wire feedback; 14 | 15 | assign feedback = ((lfsr[15] ^ lfsr[13]) ^ lfsr[12]) ^ lfsr[10]; 16 | assign lfsr_out = lfsr; 17 | 18 | //Update the linear shift feedback register. 19 | always @(posedge clk) begin 20 | if(rst) lfsr <= 16'd1; 21 | else if(en) lfsr <= {lfsr[14:0], feedback}; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /Block_LMS_Implementation/BLMS.srcs/sources_1/new/lfsr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lfsr( 4 | input clk, 5 | input en, 6 | input rst, 7 | output [15:0]lfsr_out 8 | ); 9 | 10 | //Create a 16-bit linear feedback shift register with 11 | //maximal polynomial x^16 + x^14 + x^13 + x^11 + 1. 12 | reg [15:0]lfsr = 16'd1; 13 | wire feedback; 14 | 15 | assign feedback = ((lfsr[15] ^ lfsr[13]) ^ lfsr[12]) ^ lfsr[10]; 16 | assign lfsr_out = lfsr; 17 | 18 | //Update the linear shift feedback register. 19 | always @(posedge clk) begin 20 | if(rst) lfsr <= 16'd1; 21 | else if(en) lfsr <= {lfsr[14:0], feedback}; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /FIR_Simulation/project_1/project_1.srcs/sources_1/new/filter_top.v: -------------------------------------------------------------------------------- 1 | module filter_top( 2 | input clk, 3 | input [7:0]sw, 4 | output [7:0]JA 5 | ); 6 | 7 | wire [15:0]tout; //The output of the tone lookup table. 8 | wire [15:0]fout; //The output of the FIR filter. 9 | wire [15:0]mout; //Selected output. 10 | wire en; //Clock enble. 11 | wire clk_out; //264MHz System clock. 12 | 13 | assign en = 1'b1; 14 | clk_wiz_0 cw (.clk_in1(clk), .clk_out1(clk_out), .reset(1'b0)); 15 | ToneGen tg(.clk(clk_out), .en(en), .dout(tout)); 16 | FIR_Filter ff(.clk(clk_out), .en(en), .din(tout), .dout(fout)); 17 | 18 | //Choose filtered or unfiltered output based on sw0. 19 | assign mout = sw[0] ? fout : tout; 20 | 21 | //Take only the upper 8 bits and make it unsigned. 22 | assign JA = mout[15:8] + 8'd128; 23 | endmodule 24 | -------------------------------------------------------------------------------- /FIR_Implementation/project_1/project_1.srcs/sources_1/new/filter_top.v: -------------------------------------------------------------------------------- 1 | module filter_top( 2 | input clk, 3 | input [7:0]sw, 4 | output [7:0]JA 5 | ); 6 | 7 | wire [15:0]tout; //The output of the tone lookup table. 8 | wire [15:0]fout; //The output of the FIR filter. 9 | wire [15:0]mout; //Selected output. 10 | wire en; //Clock enble. 11 | wire clk_out; //264MHz System clock. 12 | 13 | assign en = 1'b1; 14 | 15 | clk_wiz_0 cw (.clk_in1(clk), .clk_out1(clk_out)); 16 | //clk_en ce(.clk(clk_out), .en(en)); 17 | ToneGen tg(.clk(clk_out), .en(en), .dout(tout)); 18 | FIR_Filter ff(.clk(clk_out), .en(en), .din(tout), .dout(fout)); 19 | 20 | //Choose filtered or unfiltered output based on sw0. 21 | assign mout = sw[0] ? fout : tout; 22 | 23 | //Take only the upper 8 bits and make it unsigned. 24 | //assign JA = mout[15:8] + 8'd128; 25 | assign {JA[3:0], JA[7:4]} = mout[15:8] + 8'd128; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /LMS_Simulation/delay_line.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module delay_line#(LENGTH = 101)( 4 | input clk, 5 | input en, 6 | input [15:0]din, 7 | output [15:0]dout 8 | ); 9 | 10 | reg [15:0]delay[LENGTH-1:0]; 11 | integer i; //Initialization integer. 12 | genvar c; //Delay line generation variable. 13 | 14 | //Initialize delay line. 15 | initial begin 16 | for(i = 0; i < LENGTH; i = i+1) begin 17 | delay[i] = 16'd0; 18 | end 19 | end 20 | 21 | assign dout = delay[LENGTH-1]; 22 | 23 | //Advance the data through the delay line every clock cycle. 24 | generate 25 | for (c = LENGTH-1; c > 0; c = c - 1) begin: inc_delay 26 | always @(posedge clk) begin 27 | if(en) delay[c] <= delay[c-1]; 28 | end 29 | end 30 | endgenerate 31 | 32 | //Update with input data. 33 | always @(posedge clk) begin 34 | if(en) delay[0] <= din; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /LMS_Implementation/delay_line.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module delay_line#(LENGTH = 101)( 4 | input clk, 5 | input en, 6 | input [15:0]din, 7 | output [15:0]dout 8 | ); 9 | 10 | reg [15:0]delay[LENGTH-1:0]; 11 | integer i; //Initialization integer. 12 | genvar c; //Delay line generation variable. 13 | 14 | //Initialize delay line. 15 | initial begin 16 | for(i = 0; i < LENGTH; i = i+1) begin 17 | delay[i] = 16'd0; 18 | end 19 | end 20 | 21 | assign dout = delay[LENGTH-1]; 22 | 23 | //Advance the data through the delay line every clock cycle. 24 | generate 25 | for (c = LENGTH-1; c > 0; c = c - 1) begin: inc_delay 26 | always @(posedge clk) begin 27 | if(en) delay[c] <= delay[c-1]; 28 | end 29 | end 30 | endgenerate 31 | 32 | //Update with input data. 33 | always @(posedge clk) begin 34 | if(en) delay[0] <= din; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /Block_FIR_Simulation/Block_FIR.srcs/sources_1/new/Data_Mult4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Data_Mult4( 4 | input clk, 5 | input en, 6 | input [15:0]d0_in, 7 | input [15:0]d1_in, 8 | input [15:0]d2_in, 9 | input [15:0]d3_in, 10 | output reg [15:0]dout = 16'd0 11 | ); 12 | 13 | reg [1:0]count = 2'd0; 14 | 15 | //Internal registers for holding data. 16 | reg [15:0]d0 = 16'd0; 17 | reg [15:0]d1 = 16'd0; 18 | reg [15:0]d2 = 16'd0; 19 | reg [15:0]d3 = 16'd0; 20 | 21 | always @(posedge clk) begin 22 | if(en) begin 23 | count <= count + 1'b1; 24 | 25 | if(count == 2'b00) begin 26 | dout <= d0; 27 | end 28 | else if(count == 2'b01) begin 29 | dout <= d1; 30 | end 31 | else if(count == 2'b10) begin 32 | dout <= d2; 33 | end 34 | else begin 35 | d0 <= d0_in; 36 | d1 <= d1_in; 37 | d2 <= d2_in; 38 | d3 <= d3_in; 39 | dout <= d3; 40 | end 41 | end 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /Block_FIR_Implementation/Block_FIR.srcs/sources_1/new/Data_Mult4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Data_Mult4( 4 | input clk, 5 | input en, 6 | input [15:0]d0_in, 7 | input [15:0]d1_in, 8 | input [15:0]d2_in, 9 | input [15:0]d3_in, 10 | output reg [15:0]dout = 16'd0 11 | ); 12 | 13 | reg [1:0]count = 2'd0; 14 | 15 | //Internal registers for holding data. 16 | reg [15:0]d0 = 16'd0; 17 | reg [15:0]d1 = 16'd0; 18 | reg [15:0]d2 = 16'd0; 19 | reg [15:0]d3 = 16'd0; 20 | 21 | always @(posedge clk) begin 22 | if(en) begin 23 | count <= count + 1'b1; 24 | 25 | if(count == 2'b00) begin 26 | dout <= d0; 27 | end 28 | else if(count == 2'b01) begin 29 | dout <= d1; 30 | end 31 | else if(count == 2'b10) begin 32 | dout <= d2; 33 | end 34 | else begin 35 | d0 <= d0_in; 36 | d1 <= d1_in; 37 | d2 <= d2_in; 38 | d3 <= d3_in; 39 | dout <= d3; 40 | end 41 | end 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /Block_LMS_Implementation/BLMS.srcs/sources_1/new/Data_Mult4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Data_Mult4( 4 | input clk, 5 | input en, 6 | input [15:0]d0_in, 7 | input [15:0]d1_in, 8 | input [15:0]d2_in, 9 | input [15:0]d3_in, 10 | output reg [15:0]dout = 16'd0 11 | ); 12 | 13 | reg [1:0]count = 2'd0; 14 | 15 | //Internal registers for holding data. 16 | reg [15:0]d0 = 16'd0; 17 | reg [15:0]d1 = 16'd0; 18 | reg [15:0]d2 = 16'd0; 19 | reg [15:0]d3 = 16'd0; 20 | 21 | always @(posedge clk) begin 22 | if(en) begin 23 | count <= count + 1'b1; 24 | 25 | if(count == 2'b00) begin 26 | d0 <= d0_in; 27 | d1 <= d1_in; 28 | d2 <= d2_in; 29 | d3 <= d3_in; 30 | dout <= d3; 31 | end 32 | else if(count == 2'b01) begin 33 | dout <= d0; 34 | end 35 | else if(count == 2'b10) begin 36 | dout <= d1; 37 | end 38 | else begin 39 | 40 | dout <= d2; 41 | end 42 | end 43 | end 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /Block_LMS_Simulation/BLMS.srcs/sources_1/new/Data_Mult4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Data_Mult4( 4 | input clk, 5 | input en, 6 | input [15:0]d0_in, 7 | input [15:0]d1_in, 8 | input [15:0]d2_in, 9 | input [15:0]d3_in, 10 | output reg [15:0]dout = 16'd0 11 | ); 12 | 13 | reg [1:0]count = 2'd0; 14 | 15 | //Internal registers for holding data. 16 | reg [15:0]d0 = 16'd0; 17 | reg [15:0]d1 = 16'd0; 18 | reg [15:0]d2 = 16'd0; 19 | reg [15:0]d3 = 16'd0; 20 | 21 | always @(posedge clk) begin 22 | if(en) begin 23 | count <= count + 1'b1; 24 | 25 | if(count == 2'b00) begin 26 | d0 <= d0_in; 27 | d1 <= d1_in; 28 | d2 <= d2_in; 29 | d3 <= d3_in; 30 | dout <= d3; 31 | end 32 | else if(count == 2'b01) begin 33 | dout <= d0; 34 | end 35 | else if(count == 2'b10) begin 36 | dout <= d1; 37 | end 38 | else begin 39 | 40 | dout <= d2; 41 | end 42 | end 43 | end 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /Block_LMS_Implementation/BLMS.srcs/sources_1/new/Data_Div4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Data_Div4( 4 | input clk, 5 | input en, 6 | input [15:0]din, 7 | output reg en_out = 1'b0, 8 | output reg [15:0]d0_out = 16'd0, 9 | output reg [15:0]d1_out = 16'd0, 10 | output reg [15:0]d2_out = 16'd0, 11 | output reg [15:0]d3_out = 16'd0 12 | ); 13 | 14 | reg [1:0]count = 2'd0; 15 | 16 | //Internal registers for holding data. 17 | reg [15:0]d0 = 16'd0; 18 | reg [15:0]d1 = 16'd0; 19 | reg [15:0]d2 = 16'd0; 20 | 21 | always @(posedge clk) begin 22 | if(en) begin 23 | count <= count + 1'b1; 24 | 25 | if(count == 2'b00) begin 26 | d0 <= din; 27 | en_out <= 1'b0; 28 | end 29 | else if(count == 2'b01) begin 30 | d1 <= din; 31 | en_out <= 1'b0; 32 | end 33 | else if(count == 2'b10) begin 34 | d2 <= din; 35 | en_out <= 1'b0; 36 | end 37 | else begin 38 | d0_out <= d0; 39 | d1_out <= d1; 40 | d2_out <= d2; 41 | d3_out <= din; 42 | en_out <= 1'b1; 43 | end 44 | end 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /Block_LMS_Simulation/BLMS.srcs/sources_1/new/Data_Div4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Data_Div4( 4 | input clk, 5 | input en, 6 | input [15:0]din, 7 | output reg en_out = 1'b0, 8 | output reg [15:0]d0_out = 16'd0, 9 | output reg [15:0]d1_out = 16'd0, 10 | output reg [15:0]d2_out = 16'd0, 11 | output reg [15:0]d3_out = 16'd0 12 | ); 13 | 14 | reg [1:0]count = 2'd0; 15 | 16 | //Internal registers for holding data. 17 | reg [15:0]d0 = 16'd0; 18 | reg [15:0]d1 = 16'd0; 19 | reg [15:0]d2 = 16'd0; 20 | 21 | always @(posedge clk) begin 22 | if(en) begin 23 | count <= count + 1'b1; 24 | 25 | if(count == 2'b00) begin 26 | d0 <= din; 27 | en_out <= 1'b0; 28 | end 29 | else if(count == 2'b01) begin 30 | d1 <= din; 31 | en_out <= 1'b0; 32 | end 33 | else if(count == 2'b10) begin 34 | d2 <= din; 35 | en_out <= 1'b0; 36 | end 37 | else begin 38 | d0_out <= d0; 39 | d1_out <= d1; 40 | d2_out <= d2; 41 | d3_out <= din; 42 | en_out <= 1'b1; 43 | end 44 | end 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /Block_FIR_Implementation/Block_FIR.srcs/sources_1/new/Data_Div4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Data_Div4( 4 | input clk, 5 | input en, 6 | input [15:0]din, 7 | output reg en_out = 1'b0, 8 | output reg [15:0]d0_out = 16'd0, 9 | output reg [15:0]d1_out = 16'd0, 10 | output reg [15:0]d2_out = 16'd0, 11 | output reg [15:0]d3_out = 16'd0 12 | ); 13 | 14 | reg [1:0]count = 2'd0; 15 | 16 | //Internal registers for holding data. 17 | reg [15:0]d0 = 16'd0; 18 | reg [15:0]d1 = 16'd0; 19 | reg [15:0]d2 = 16'd0; 20 | 21 | always @(posedge clk) begin 22 | if(en) begin 23 | count <= count + 1'b1; 24 | 25 | if(count == 2'b00) begin 26 | d0 <= din; 27 | en_out <= 1'b0; 28 | end 29 | else if(count == 2'b01) begin 30 | d1 <= din; 31 | en_out <= 1'b0; 32 | end 33 | else if(count == 2'b10) begin 34 | d2 <= din; 35 | en_out <= 1'b0; 36 | end 37 | else begin 38 | d0_out <= d0; 39 | d1_out <= d1; 40 | d2_out <= d2; 41 | d3_out <= din; 42 | en_out <= 1'b1; 43 | end 44 | end 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /Block_FIR_Simulation/Block_FIR.srcs/sources_1/new/Data_Div4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Data_Div4( 4 | input clk, 5 | input en, 6 | input [15:0]din, 7 | output reg en_out = 1'b0, 8 | output reg [15:0]d0_out = 16'd0, 9 | output reg [15:0]d1_out = 16'd0, 10 | output reg [15:0]d2_out = 16'd0, 11 | output reg [15:0]d3_out = 16'd0 12 | ); 13 | 14 | reg [1:0]count = 2'd0; 15 | 16 | //Internal registers for holding data. 17 | reg [15:0]d0 = 16'd0; 18 | reg [15:0]d1 = 16'd0; 19 | reg [15:0]d2 = 16'd0; 20 | 21 | always @(posedge clk) begin 22 | if(en) begin 23 | count <= count + 1'b1; 24 | 25 | if(count == 2'b00) begin 26 | d0 <= din; 27 | en_out <= 1'b0; 28 | end 29 | else if(count == 2'b01) begin 30 | d1 <= din; 31 | en_out <= 1'b0; 32 | end 33 | else if(count == 2'b10) begin 34 | d2 <= din; 35 | en_out <= 1'b0; 36 | end 37 | else begin 38 | d0_out <= d0; 39 | d1_out <= d1; 40 | d2_out <= d2; 41 | d3_out <= din; 42 | en_out <= 1'b1; 43 | end 44 | end 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /Block_LMS_Implementation/BLMS.srcs/sim_1/new/BLMS_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module BLMS_TB; 4 | reg clk = 1'b0; 5 | reg [7:0]sw = 8'd0; 6 | wire [7:0]JA; 7 | 8 | wire clk_50MHz; 9 | wire clk_25MHz; 10 | 11 | wire signed [15:0]tone_and_noise; 12 | wire signed [15:0]fout; 13 | wire signed [15:0]dout0; 14 | wire signed [15:0]dout1; 15 | wire signed [15:0]dout2; 16 | wire signed [15:0]dout3; 17 | wire signed [15:0]blms_din0; 18 | wire signed [15:0]blms_din1; 19 | wire signed [15:0]blms_din2; 20 | wire signed [15:0]blms_din3; 21 | wire en; 22 | 23 | BLMS_Top uut(.clk(clk), .sw(sw), .JA(JA)); 24 | 25 | assign clk_50MHz = uut.clk_50MHz; 26 | assign clk_25MHz = uut.clk_25MHz; 27 | 28 | assign tone_and_noise = uut.tone_and_noise; 29 | assign fout = uut.fout; 30 | assign dout0 = uut.dout0; 31 | assign dout1 = uut.dout1; 32 | assign dout2 = uut.dout2; 33 | assign dout3 = uut.dout3; 34 | assign blms_din0 = uut.blms_din0; 35 | assign blms_din1 = uut.blms_din1; 36 | assign blms_din2 = uut.blms_din2; 37 | assign blms_din3 = uut.blms_din3; 38 | assign en = uut.en; 39 | 40 | //Generate 100MHz clock. 41 | always #5 clk = ~clk; 42 | 43 | initial begin 44 | #500000 sw = 8'd1; 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /FIR_Simulation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016 4 | // Date : Mon May 22 23:20:30 2017 5 | // Host : Test running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // c:/Users/Nick/Desktop/TA_Stuff/Lucys_Project/Lucys_Project_Vivado/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v 8 | // Design : clk_wiz_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a35tcpg236-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module clk_wiz_0(clk_in1, clk_out1, reset, locked) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset,locked" */; 18 | input clk_in1; 19 | output clk_out1; 20 | input reset; 21 | output locked; 22 | endmodule 23 | -------------------------------------------------------------------------------- /LMS_Simulation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016 4 | // Date : Mon May 22 22:52:31 2017 5 | // Host : Test running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // c:/Users/Nick/Desktop/TA_Stuff/Adaptive_Filter_Stuff/LMS_Adaptive_Filter/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v 8 | // Design : clk_wiz_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a35tcpg236-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module clk_wiz_0(clk_in1, clk_out1, reset, locked) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset,locked" */; 18 | input clk_in1; 19 | output clk_out1; 20 | input reset; 21 | output locked; 22 | endmodule 23 | -------------------------------------------------------------------------------- /FIR_Simulation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016 4 | -- Date : Mon May 22 23:20:30 2017 5 | -- Host : Test running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- c:/Users/Nick/Desktop/TA_Stuff/Lucys_Project/Lucys_Project_Vivado/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl 8 | -- Design : clk_wiz_0 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a35tcpg236-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity clk_wiz_0 is 16 | Port ( 17 | clk_in1 : in STD_LOGIC; 18 | clk_out1 : out STD_LOGIC; 19 | reset : in STD_LOGIC; 20 | locked : out STD_LOGIC 21 | ); 22 | 23 | end clk_wiz_0; 24 | 25 | architecture stub of clk_wiz_0 is 26 | attribute syn_black_box : boolean; 27 | attribute black_box_pad_pin : string; 28 | attribute syn_black_box of stub : architecture is true; 29 | attribute black_box_pad_pin of stub : architecture is "clk_in1,clk_out1,reset,locked"; 30 | begin 31 | end; 32 | -------------------------------------------------------------------------------- /LMS_Implementation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016 4 | // Date : Mon May 22 22:52:31 2017 5 | // Host : Test running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // c:/Users/Nick/Desktop/TA_Stuff/Adaptive_Filter_Stuff/LMS_Adaptive_Filter/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v 8 | // Design : clk_wiz_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a35tcpg236-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module clk_wiz_0(clk_in1, clk_out1, reset, locked) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset,locked" */; 18 | input clk_in1; 19 | output clk_out1; 20 | input reset; 21 | output locked; 22 | endmodule 23 | -------------------------------------------------------------------------------- /LMS_Simulation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016 4 | -- Date : Mon May 22 22:52:31 2017 5 | -- Host : Test running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- c:/Users/Nick/Desktop/TA_Stuff/Adaptive_Filter_Stuff/LMS_Adaptive_Filter/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl 8 | -- Design : clk_wiz_0 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a35tcpg236-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity clk_wiz_0 is 16 | Port ( 17 | clk_in1 : in STD_LOGIC; 18 | clk_out1 : out STD_LOGIC; 19 | reset : in STD_LOGIC; 20 | locked : out STD_LOGIC 21 | ); 22 | 23 | end clk_wiz_0; 24 | 25 | architecture stub of clk_wiz_0 is 26 | attribute syn_black_box : boolean; 27 | attribute black_box_pad_pin : string; 28 | attribute syn_black_box of stub : architecture is true; 29 | attribute black_box_pad_pin of stub : architecture is "clk_in1,clk_out1,reset,locked"; 30 | begin 31 | end; 32 | -------------------------------------------------------------------------------- /LMS_Implementation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016 4 | -- Date : Mon May 22 22:52:31 2017 5 | -- Host : Test running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- c:/Users/Nick/Desktop/TA_Stuff/Adaptive_Filter_Stuff/LMS_Adaptive_Filter/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl 8 | -- Design : clk_wiz_0 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a35tcpg236-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity clk_wiz_0 is 16 | Port ( 17 | clk_in1 : in STD_LOGIC; 18 | clk_out1 : out STD_LOGIC; 19 | reset : in STD_LOGIC; 20 | locked : out STD_LOGIC 21 | ); 22 | 23 | end clk_wiz_0; 24 | 25 | architecture stub of clk_wiz_0 is 26 | attribute syn_black_box : boolean; 27 | attribute black_box_pad_pin : string; 28 | attribute syn_black_box of stub : architecture is true; 29 | attribute black_box_pad_pin of stub : architecture is "clk_in1,clk_out1,reset,locked"; 30 | begin 31 | end; 32 | -------------------------------------------------------------------------------- /Block_LMS_Simulation/BLMS.srcs/sources_1/new/BLMS_ECU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module BLMS_ECU( 4 | input clk, //Filter clock. 5 | input r_en, //Weight adjust registers enable. 6 | 7 | input signed [15:0]din0, // 8 | input signed [15:0]din1, //Desired inputs. 9 | input signed [15:0]din2, // 10 | input signed [15:0]din3, // 11 | 12 | input signed [15:0]yin0, // 13 | input signed [15:0]yin1, //From filter output. 14 | input signed [15:0]yin2, // 15 | input signed [15:0]yin3, // 16 | 17 | output reg signed [15:0]r0 = 16'd0, // 18 | output reg signed [15:0]r1 = 16'd0, //Stepped error output. 19 | output reg signed [15:0]r2 = 16'd0, // 20 | output reg signed [15:0]r3 = 16'd0 // 21 | ); 22 | 23 | //Adder outputs. 24 | wire signed [15:0]add_out0; 25 | wire signed [15:0]add_out1; 26 | wire signed [15:0]add_out2; 27 | wire signed [15:0]add_out3; 28 | 29 | //Mu outputs. 30 | wire signed [31:0]mu0; 31 | wire signed [31:0]mu1; 32 | wire signed [31:0]mu2; 33 | wire signed [31:0]mu3; 34 | 35 | //Assign outputs. 36 | assign add_out0 = din0 - yin0; 37 | assign add_out1 = din1 - yin1; 38 | assign add_out2 = din2 - yin2; 39 | assign add_out3 = din3 - yin3; 40 | 41 | //Multiply error by mu (hard coded). 42 | assign mu0 = add_out0 << 15; 43 | assign mu1 = add_out1 << 15; 44 | assign mu2 = add_out2 << 15; 45 | assign mu3 = add_out3 << 15; 46 | 47 | //Update delay registers. 48 | always @(posedge clk) begin 49 | if(r_en) begin 50 | r0 <= mu0[31:16]; 51 | r1 <= mu1[31:16]; 52 | r2 <= mu2[31:16]; 53 | r3 <= mu3[31:16]; 54 | end 55 | end 56 | endmodule 57 | -------------------------------------------------------------------------------- /Block_LMS_Implementation/BLMS.srcs/sources_1/new/BLMS_ECU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module BLMS_ECU( 4 | input clk, //Filter clock. 5 | input r_en, //Weight adjust registers enable. 6 | 7 | input signed [15:0]din0, // 8 | input signed [15:0]din1, //Desired inputs. 9 | input signed [15:0]din2, // 10 | input signed [15:0]din3, // 11 | 12 | input signed [15:0]yin0, // 13 | input signed [15:0]yin1, //From filter output. 14 | input signed [15:0]yin2, // 15 | input signed [15:0]yin3, // 16 | 17 | output reg signed [15:0]r0 = 16'd0, // 18 | output reg signed [15:0]r1 = 16'd0, //Stepped error output. 19 | output reg signed [15:0]r2 = 16'd0, // 20 | output reg signed [15:0]r3 = 16'd0 // 21 | ); 22 | 23 | //Adder outputs. 24 | wire signed [15:0]add_out0; 25 | wire signed [15:0]add_out1; 26 | wire signed [15:0]add_out2; 27 | wire signed [15:0]add_out3; 28 | 29 | //Mu outputs. 30 | wire signed [31:0]mu0; 31 | wire signed [31:0]mu1; 32 | wire signed [31:0]mu2; 33 | wire signed [31:0]mu3; 34 | 35 | //Assign outputs. 36 | assign add_out0 = din0 - yin0; 37 | assign add_out1 = din1 - yin1; 38 | assign add_out2 = din2 - yin2; 39 | assign add_out3 = din3 - yin3; 40 | 41 | //Multiply error by mu (hard coded). 42 | assign mu0 = add_out0 << 15; 43 | assign mu1 = add_out1 << 15; 44 | assign mu2 = add_out2 << 15; 45 | assign mu3 = add_out3 << 15; 46 | 47 | //Update delay registers. 48 | always @(posedge clk) begin 49 | if(r_en) begin 50 | r0 <= mu0[31:16]; 51 | r1 <= mu1[31:16]; 52 | r2 <= mu2[31:16]; 53 | r3 <= mu3[31:16]; 54 | end 55 | end 56 | endmodule 57 | -------------------------------------------------------------------------------- /LMS_Implementation/filter_top.v: -------------------------------------------------------------------------------- 1 | module filter_top( 2 | input clk, 3 | input [7:0]sw, 4 | output [7:0]JA 5 | ); 6 | 7 | wire signed [15:0]tout; //Output of the tone lookup table. 8 | wire [15:0]fout; //Output of the FIR filter. 9 | wire [15:0]aout; //Output of the adaptive filter. 10 | wire [15:0]err; //Adaptive filter error. 11 | wire [15:0]lfsr_out; //16-bit Random noise variable. 12 | wire en; //Clock enble. 13 | wire [9:0]rnd; //10-bit noise. 14 | wire signed [15:0]tone_and_noise; //Combination of tone and noise. 15 | wire signed [15:0]delay_out; //Output of the delay line. 16 | wire [15:0]mout; //Selected desired output. 17 | wire clk19_8MHz; //19.8MHz system clock. 18 | 19 | assign rnd = lfsr_out[15:6]; 20 | assign tone_and_noise = tout + rnd; 21 | //assign en = 1'b1; 22 | 23 | clk_wiz_0 cw(.clk_in1(clk), .clk_out1(clk19_8MHz), .reset(1'b0)); 24 | ToneGen tg(.clk(clk19_8MHz), .en(en), .dout(tout)); 25 | FIR_Filter ff(.clk(clk19_8MHz), .en(en), .din(tone_and_noise), .dout(fout)); 26 | LMS_Adapt af(.clk(clk19_8MHz), .en(en), .din(tone_and_noise), .desired(mout), .dout(aout), .err(err)); 27 | lfsr sr(.clk(clk19_8MHz), .en(en), .lfsr_out(lfsr_out)); 28 | clk_en ce(.clk(clk19_8MHz), .en(en)); 29 | 30 | //Choose filtered or unfiltered output based on sw0. 31 | assign mout = sw[0] ? fout : tone_and_noise;//delay_out; 32 | 33 | //Take only the upper 8 bits and make it unsigned. 34 | assign {JA[3:0], JA[7:4]} = aout[15:8] + 8'd128; 35 | //assign JA[7:0] = aout[15:8] + 8'd128; 36 | 37 | //assign {JA[3:0], JA[7:4]} = sw[7:0]; 38 | endmodule 39 | -------------------------------------------------------------------------------- /LMS_Simulation/filter_top.v: -------------------------------------------------------------------------------- 1 | module filter_top( 2 | input clk, 3 | input [7:0]sw, 4 | output [7:0]JA 5 | ); 6 | 7 | wire signed [15:0]tout; //Output of the tone lookup table. 8 | wire [15:0]fout; //Output of the FIR filter. 9 | wire [15:0]aout; //Output of the adaptive filter. 10 | wire [15:0]err; //Adaptive filter error. 11 | wire [15:0]lfsr_out; //16-bit Random noise variable. 12 | wire en; //Clock enble. 13 | wire [9:0]rnd; //10-bit noise. 14 | wire signed [15:0]tone_and_noise; //Combination of tone and noise. 15 | wire signed [15:0]delay_out; //Output of the delay line. 16 | wire [15:0]mout; //Selected desired output. 17 | wire clk19_8MHz; //19.8MHz system clock. 18 | 19 | assign rnd = lfsr_out[15:6]; 20 | assign tone_and_noise = tout + rnd; 21 | assign en = 1'b1; 22 | 23 | clk_wiz_0 cw(.clk_in1(clk), .clk_out1(clk19_8MHz), .reset(1'b0)); 24 | ToneGen tg(.clk(clk19_8MHz), .en(en), .dout(tout)); 25 | FIR_Filter ff(.clk(clk19_8MHz), .en(en), .din(tone_and_noise), .dout(fout)); 26 | LMS_Adapt af(.clk(clk19_8MHz), .en(en), .din(tone_and_noise), .desired(mout), .dout(aout), .err(err)); 27 | lfsr sr(.clk(clk19_8MHz), .en(en), .lfsr_out(lfsr_out)); 28 | //clk_en ce(.clk(clk19_8MHz), .en(en)); 29 | 30 | //Choose filtered or unfiltered output based on sw0. 31 | assign mout = sw[0] ? fout : tone_and_noise;//delay_out; 32 | 33 | //Take only the upper 8 bits and make it unsigned. 34 | //assign {JA[3:0], JA[7:4]} = aout[15:8] + 8'd128; 35 | assign JA[7:0] = aout[15:8] + 8'd128; 36 | 37 | //assign {JA[3:0], JA[7:4]} = sw[7:0]; 38 | endmodule 39 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | ./Block_FIR_Implementation/Block_FIR.cache 2 | ./Block_FIR_Implementation/Block_FIR.hw 3 | ./Block_FIR_Implementation/Block_FIR.ip_user_files 4 | ./Block_FIR_Implementation/Block_FIR.runs 5 | ./Block_FIR_Implementation/Block_FIR.sim 6 | ./Block_FIR_Implementation/*.log 7 | 8 | ./Block_FIR_Simulation/Block_FIR.cache 9 | ./Block_FIR_Simulation/Block_FIR.hw 10 | ./Block_FIR_Simulation/Block_FIR.ip_user_files 11 | ./Block_FIR_Simulation/Block_FIR.runs 12 | ./Block_FIR_Simulation/Block_FIR.sim 13 | ./Block_FIR_Simulation/*.log 14 | 15 | ./Block_LMS_Implementation/BLMS.cache 16 | ./Block_LMS_Implementation/BLMS.hw 17 | ./Block_LMS_Implementation/BLMS.ip_user_files 18 | ./Block_LMS_Implementation/BLMS.runs 19 | ./Block_LMS_Implementation/BLMS.sim 20 | ./Block_LMS_Implementation/*.log 21 | 22 | ./Block_LMS_Simulation/BLMS.cache 23 | ./Block_LMS_Simulation/BLMS.hw 24 | ./Block_LMS_Simulation/BLMS.ip_user_files 25 | ./Block_LMS_Simulation/BLMS.runs 26 | ./Block_LMS_Simulation/BLMS.sim 27 | ./Block_LMS_Simulation/*.log 28 | 29 | ./FIR_Implementation/project_1/project_1.cache 30 | ./FIR_Implementation/project_1/project_1.hw 31 | ./FIR_Implementation/project_1/project_1.ip_user_files 32 | ./FIR_Implementation/project_1/project_1.runs 33 | ./FIR_Implementation/project_1/project_1.sim 34 | ./FIR_Implementation/project_1/*.log 35 | 36 | ./FIR_Simulation/project_1/project_1.cache 37 | ./FIR_Simulation/project_1/project_1.hw 38 | ./FIR_Simulation/project_1/project_1.ip_user_files 39 | ./FIR_Simulation/project_1/project_1.runs 40 | ./FIR_Simulation/project_1/project_1.sim 41 | ./FIR_Simulation/project_1/*.log 42 | 43 | ./LMS_Implementation/BLMS.cache 44 | ./LMS_Implementation/BLMS.hw 45 | ./LMS_Implementation/BLMS.ip_user_files 46 | ./LMS_Implementation/BLMS.runs 47 | ./LMS_Implementation/BLMS.sim 48 | ./LMS_Implementation/*.log 49 | 50 | ./LMS_Simulation/BLMS.cache 51 | ./LMS_Simulation/BLMS.hw 52 | ./LMS_Simulation/BLMS.ip_user_files 53 | ./LMS_Simulation/BLMS.runs 54 | ./LMS_Simulation/BLMS.sim 55 | ./LMS_Simulation/*.log 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | -------------------------------------------------------------------------------- /LMS_Simulation/FIR_Filter.v: -------------------------------------------------------------------------------- 1 | `define FILT_LENGTH 16 2 | 3 | module FIR_Filter( 4 | input clk, 5 | input en, 6 | input [15:0]din, 7 | output [15:0]dout 8 | ); 9 | 10 | reg signed [15:0]coeff[`FILT_LENGTH/2-1:0]; //Filter coefficients. 11 | reg signed [15:0]delay_line[`FILT_LENGTH-1:0]; //Input delay line. 12 | wire [31:0]accum; //Accumulator for output filter calculation. 13 | integer i; //Initialization integer. 14 | genvar c; //Delay line generation variable. 15 | 16 | //Calculate value in the accumulator. 17 | assign accum = (delay_line[0] + delay_line[15]) * coeff[0] + 18 | (delay_line[1] + delay_line[14]) * coeff[1] + 19 | (delay_line[2] + delay_line[13]) * coeff[2] + 20 | (delay_line[3] + delay_line[12]) * coeff[3] + 21 | (delay_line[4] + delay_line[11]) * coeff[4] + 22 | (delay_line[5] + delay_line[10]) * coeff[5] + 23 | (delay_line[6] + delay_line[9]) * coeff[6] + 24 | (delay_line[7] + delay_line[8]) * coeff[7]; 25 | 26 | //Assign upper 16-bits to output. 27 | assign dout = accum[31:16]; 28 | 29 | initial begin 30 | //Load the filter coefficients. 31 | coeff[0] = 16'd2552; 32 | coeff[1] = 16'd4557; 33 | coeff[2] = 16'd5051; 34 | coeff[3] = 16'd8006; 35 | coeff[4] = 16'd9265; 36 | coeff[5] = 16'd11427; 37 | coeff[6] = 16'd12396; 38 | coeff[7] = 16'd13200; 39 | 40 | //Initialize delay line. 41 | for(i = 0; i < `FILT_LENGTH; i = i+1'b1) begin 42 | delay_line[i] = 16'd0; 43 | end 44 | end 45 | 46 | //Advance the data through the delay line every clock cycle. 47 | generate 48 | for (c = `FILT_LENGTH-1; c > 0; c = c - 1) begin: inc_delay 49 | always @(posedge clk) begin 50 | if(en) delay_line[c] <= delay_line[c-1]; 51 | end 52 | end 53 | endgenerate 54 | 55 | //Update with input data. 56 | always @(posedge clk) begin 57 | if(en) delay_line[0] <= din; 58 | end 59 | endmodule 60 | -------------------------------------------------------------------------------- /LMS_Implementation/FIR_Filter.v: -------------------------------------------------------------------------------- 1 | `define FILT_LENGTH 16 2 | 3 | module FIR_Filter( 4 | input clk, 5 | input en, 6 | input [15:0]din, 7 | output [15:0]dout 8 | ); 9 | 10 | reg signed [15:0]coeff[`FILT_LENGTH/2-1:0]; //Filter coefficients. 11 | reg signed [15:0]delay_line[`FILT_LENGTH-1:0]; //Input delay line. 12 | wire [31:0]accum; //Accumulator for output filter calculation. 13 | integer i; //Initialization integer. 14 | genvar c; //Delay line generation variable. 15 | 16 | //Calculate value in the accumulator. 17 | assign accum = (delay_line[0] + delay_line[15]) * coeff[0] + 18 | (delay_line[1] + delay_line[14]) * coeff[1] + 19 | (delay_line[2] + delay_line[13]) * coeff[2] + 20 | (delay_line[3] + delay_line[12]) * coeff[3] + 21 | (delay_line[4] + delay_line[11]) * coeff[4] + 22 | (delay_line[5] + delay_line[10]) * coeff[5] + 23 | (delay_line[6] + delay_line[9]) * coeff[6] + 24 | (delay_line[7] + delay_line[8]) * coeff[7]; 25 | 26 | //Assign upper 16-bits to output. 27 | assign dout = accum[31:16]; 28 | 29 | initial begin 30 | //Load the filter coefficients. 31 | coeff[0] = 16'd2552; 32 | coeff[1] = 16'd4557; 33 | coeff[2] = 16'd5051; 34 | coeff[3] = 16'd8006; 35 | coeff[4] = 16'd9265; 36 | coeff[5] = 16'd11427; 37 | coeff[6] = 16'd12396; 38 | coeff[7] = 16'd13200; 39 | 40 | //Initialize delay line. 41 | for(i = 0; i < `FILT_LENGTH; i = i+1'b1) begin 42 | delay_line[i] = 16'd0; 43 | end 44 | end 45 | 46 | //Advance the data through the delay line every clock cycle. 47 | generate 48 | for (c = `FILT_LENGTH-1; c > 0; c = c - 1) begin: inc_delay 49 | always @(posedge clk) begin 50 | if(en) delay_line[c] <= delay_line[c-1]; 51 | end 52 | end 53 | endgenerate 54 | 55 | //Update with input data. 56 | always @(posedge clk) begin 57 | if(en) delay_line[0] <= din; 58 | end 59 | endmodule 60 | -------------------------------------------------------------------------------- /Block_FIR_Simulation/Block_FIR.srcs/sources_1/new/FIR_Filter.v: -------------------------------------------------------------------------------- 1 | `define FILT_LENGTH 16 2 | 3 | module FIR_Filter( 4 | input clk, 5 | input en, 6 | input [15:0]din, 7 | output [15:0]dout 8 | ); 9 | 10 | reg signed [15:0]coeff[`FILT_LENGTH/2-1:0]; //Filter coefficients. 11 | reg signed [15:0]delay_line[`FILT_LENGTH-1:0]; //Input delay line. 12 | wire [31:0]accum; //Accumulator for output filter calculation. 13 | integer i; //Initialization integer. 14 | genvar c; //Delay line generation variable. 15 | 16 | //Calculate value in the accumulator. 17 | assign accum = (delay_line[0] + delay_line[15]) * coeff[0] + 18 | (delay_line[1] + delay_line[14]) * coeff[1] + 19 | (delay_line[2] + delay_line[13]) * coeff[2] + 20 | (delay_line[3] + delay_line[12]) * coeff[3] + 21 | (delay_line[4] + delay_line[11]) * coeff[4] + 22 | (delay_line[5] + delay_line[10]) * coeff[5] + 23 | (delay_line[6] + delay_line[9]) * coeff[6] + 24 | (delay_line[7] + delay_line[8]) * coeff[7]; 25 | 26 | //Assign upper 16-bits to output. 27 | assign dout = accum[31:16]; 28 | 29 | initial begin 30 | //Load the filter coefficients. 31 | coeff[0] = 16'd2320; 32 | coeff[1] = 16'd4143; 33 | coeff[2] = 16'd4592; 34 | coeff[3] = 16'd7278; 35 | coeff[4] = 16'd8423; 36 | coeff[5] = 16'd10389; 37 | coeff[6] = 16'd11269; 38 | coeff[7] = 16'd12000; 39 | 40 | //Initialize delay line. 41 | for(i = 0; i < `FILT_LENGTH; i = i+1'b1) begin 42 | delay_line[i] = 16'd0; 43 | end 44 | end 45 | 46 | //Advance the data through the delay line every clock cycle. 47 | generate 48 | for (c = `FILT_LENGTH-1; c > 0; c = c - 1) begin: inc_delay 49 | always @(posedge clk) begin 50 | if(en) delay_line[c] <= delay_line[c-1]; 51 | end 52 | end 53 | endgenerate 54 | 55 | //Update with input data. 56 | always @(posedge clk) begin 57 | if(en) delay_line[0] <= din; 58 | end 59 | endmodule 60 | -------------------------------------------------------------------------------- /Block_FIR_Implementation/Block_FIR.srcs/sources_1/new/FIR_Filter.v: -------------------------------------------------------------------------------- 1 | `define FILT_LENGTH 16 2 | 3 | module FIR_Filter( 4 | input clk, 5 | input en, 6 | input [15:0]din, 7 | output [15:0]dout 8 | ); 9 | 10 | reg signed [15:0]coeff[`FILT_LENGTH/2-1:0]; //Filter coefficients. 11 | reg signed [15:0]delay_line[`FILT_LENGTH-1:0]; //Input delay line. 12 | wire [31:0]accum; //Accumulator for output filter calculation. 13 | integer i; //Initialization integer. 14 | genvar c; //Delay line generation variable. 15 | 16 | //Calculate value in the accumulator. 17 | assign accum = (delay_line[0] + delay_line[15]) * coeff[0] + 18 | (delay_line[1] + delay_line[14]) * coeff[1] + 19 | (delay_line[2] + delay_line[13]) * coeff[2] + 20 | (delay_line[3] + delay_line[12]) * coeff[3] + 21 | (delay_line[4] + delay_line[11]) * coeff[4] + 22 | (delay_line[5] + delay_line[10]) * coeff[5] + 23 | (delay_line[6] + delay_line[9]) * coeff[6] + 24 | (delay_line[7] + delay_line[8]) * coeff[7]; 25 | 26 | //Assign upper 16-bits to output. 27 | assign dout = accum[31:16]; 28 | 29 | initial begin 30 | //Load the filter coefficients. 31 | coeff[0] = 16'd2320; 32 | coeff[1] = 16'd4143; 33 | coeff[2] = 16'd4592; 34 | coeff[3] = 16'd7278; 35 | coeff[4] = 16'd8423; 36 | coeff[5] = 16'd10389; 37 | coeff[6] = 16'd11269; 38 | coeff[7] = 16'd12000; 39 | 40 | //Initialize delay line. 41 | for(i = 0; i < `FILT_LENGTH; i = i+1'b1) begin 42 | delay_line[i] = 16'd0; 43 | end 44 | end 45 | 46 | //Advance the data through the delay line every clock cycle. 47 | generate 48 | for (c = `FILT_LENGTH-1; c > 0; c = c - 1) begin: inc_delay 49 | always @(posedge clk) begin 50 | if(en) delay_line[c] <= delay_line[c-1]; 51 | end 52 | end 53 | endgenerate 54 | 55 | //Update with input data. 56 | always @(posedge clk) begin 57 | if(en) delay_line[0] <= din; 58 | end 59 | endmodule 60 | -------------------------------------------------------------------------------- /FIR_Simulation/project_1/project_1.srcs/sources_1/new/FIR_Filter.v: -------------------------------------------------------------------------------- 1 | `define FILT_LENGTH 16 2 | 3 | module FIR_Filter( 4 | input clk, 5 | input en, 6 | input [15:0]din, 7 | output [15:0]dout 8 | ); 9 | 10 | reg signed [15:0]coeff[`FILT_LENGTH/2-1:0]; //Filter coefficients. 11 | reg signed [15:0]delay_line[`FILT_LENGTH-1:0]; //Input delay line. 12 | wire [31:0]accum; //Accumulator for output filter calculation. 13 | integer i; //Initialization integer. 14 | genvar c; //Delay line generation variable. 15 | 16 | //Calculate value in the accumulator. 17 | assign accum = (delay_line[0] + delay_line[15]) * coeff[0] + 18 | (delay_line[1] + delay_line[14]) * coeff[1] + 19 | (delay_line[2] + delay_line[13]) * coeff[2] + 20 | (delay_line[3] + delay_line[12]) * coeff[3] + 21 | (delay_line[4] + delay_line[11]) * coeff[4] + 22 | (delay_line[5] + delay_line[10]) * coeff[5] + 23 | (delay_line[6] + delay_line[9]) * coeff[6] + 24 | (delay_line[7] + delay_line[8]) * coeff[7]; 25 | 26 | //Assign upper 16-bits to output. 27 | assign dout = accum[31:16]; 28 | 29 | initial begin 30 | //Load the filter coefficients. 31 | coeff[0] = 16'd2320; 32 | coeff[1] = 16'd4143; 33 | coeff[2] = 16'd4592; 34 | coeff[3] = 16'd7278; 35 | coeff[4] = 16'd8423; 36 | coeff[5] = 16'd10389; 37 | coeff[6] = 16'd11269; 38 | coeff[7] = 16'd12000; 39 | 40 | //Initialize delay line. 41 | for(i = 0; i < `FILT_LENGTH; i = i+1'b1) begin 42 | delay_line[i] = 16'd0; 43 | end 44 | end 45 | 46 | //Advance the data through the delay line every clock cycle. 47 | generate 48 | for (c = `FILT_LENGTH-1; c > 0; c = c - 1) begin: inc_delay 49 | always @(posedge clk) begin 50 | if(en) delay_line[c] <= delay_line[c-1]; 51 | end 52 | end 53 | endgenerate 54 | 55 | //Update with input data. 56 | always @(posedge clk) begin 57 | if(en) delay_line[0] <= din; 58 | end 59 | endmodule 60 | -------------------------------------------------------------------------------- /Block_LMS_Simulation/BLMS.srcs/sources_1/new/FIR_Filter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | `define FILT_LENGTH 16 4 | 5 | module FIR_Filter( 6 | input clk, 7 | input en, 8 | input [15:0]din, 9 | output [15:0]dout 10 | ); 11 | 12 | reg signed [15:0]coeff[`FILT_LENGTH/2-1:0]; //Filter coefficients. 13 | reg signed [15:0]delay_line[`FILT_LENGTH-1:0]; //Input delay line. 14 | wire [31:0]accum; //Accumulator for output filter calculation. 15 | integer i; //Initialization integer. 16 | genvar c; //Delay line generation variable. 17 | 18 | //Calculate value in the accumulator. 19 | assign accum = (delay_line[0] + delay_line[15]) * coeff[0] + 20 | (delay_line[1] + delay_line[14]) * coeff[1] + 21 | (delay_line[2] + delay_line[13]) * coeff[2] + 22 | (delay_line[3] + delay_line[12]) * coeff[3] + 23 | (delay_line[4] + delay_line[11]) * coeff[4] + 24 | (delay_line[5] + delay_line[10]) * coeff[5] + 25 | (delay_line[6] + delay_line[9]) * coeff[6] + 26 | (delay_line[7] + delay_line[8]) * coeff[7]; 27 | 28 | //Assign upper 16-bits to output. 29 | assign dout = accum[31:16]; 30 | 31 | initial begin 32 | //Load the filter coefficients. 33 | coeff[0] = 16'd2552; 34 | coeff[1] = 16'd4557; 35 | coeff[2] = 16'd5051; 36 | coeff[3] = 16'd8006; 37 | coeff[4] = 16'd9265; 38 | coeff[5] = 16'd11427; 39 | coeff[6] = 16'd12396; 40 | coeff[7] = 16'd13200; 41 | 42 | //Initialize delay line. 43 | for(i = 0; i < `FILT_LENGTH; i = i+1'b1) begin 44 | delay_line[i] = 16'd0; 45 | end 46 | end 47 | 48 | //Advance the data through the delay line every clock cycle. 49 | generate 50 | for (c = `FILT_LENGTH-1; c > 0; c = c - 1) begin: inc_delay 51 | always @(posedge clk) begin 52 | if(en) delay_line[c] <= delay_line[c-1]; 53 | end 54 | end 55 | endgenerate 56 | 57 | //Update with input data. 58 | always @(posedge clk) begin 59 | if(en) delay_line[0] <= din; 60 | end 61 | endmodule 62 | -------------------------------------------------------------------------------- /Block_LMS_Implementation/BLMS.srcs/sources_1/new/FIR_Filter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | `define FILT_LENGTH 16 4 | 5 | module FIR_Filter( 6 | input clk, 7 | input en, 8 | input [15:0]din, 9 | output [15:0]dout 10 | ); 11 | 12 | reg signed [15:0]coeff[`FILT_LENGTH/2-1:0]; //Filter coefficients. 13 | reg signed [15:0]delay_line[`FILT_LENGTH-1:0]; //Input delay line. 14 | wire [31:0]accum; //Accumulator for output filter calculation. 15 | integer i; //Initialization integer. 16 | genvar c; //Delay line generation variable. 17 | 18 | //Calculate value in the accumulator. 19 | assign accum = (delay_line[0] + delay_line[15]) * coeff[0] + 20 | (delay_line[1] + delay_line[14]) * coeff[1] + 21 | (delay_line[2] + delay_line[13]) * coeff[2] + 22 | (delay_line[3] + delay_line[12]) * coeff[3] + 23 | (delay_line[4] + delay_line[11]) * coeff[4] + 24 | (delay_line[5] + delay_line[10]) * coeff[5] + 25 | (delay_line[6] + delay_line[9]) * coeff[6] + 26 | (delay_line[7] + delay_line[8]) * coeff[7]; 27 | 28 | //Assign upper 16-bits to output. 29 | assign dout = accum[31:16]; 30 | 31 | initial begin 32 | //Load the filter coefficients. 33 | coeff[0] = 16'd2552; 34 | coeff[1] = 16'd4557; 35 | coeff[2] = 16'd5051; 36 | coeff[3] = 16'd8006; 37 | coeff[4] = 16'd9265; 38 | coeff[5] = 16'd11427; 39 | coeff[6] = 16'd12396; 40 | coeff[7] = 16'd13200; 41 | 42 | //Initialize delay line. 43 | for(i = 0; i < `FILT_LENGTH; i = i+1'b1) begin 44 | delay_line[i] = 16'd0; 45 | end 46 | end 47 | 48 | //Advance the data through the delay line every clock cycle. 49 | generate 50 | for (c = `FILT_LENGTH-1; c > 0; c = c - 1) begin: inc_delay 51 | always @(posedge clk) begin 52 | if(en) delay_line[c] <= delay_line[c-1]; 53 | end 54 | end 55 | endgenerate 56 | 57 | //Update with input data. 58 | always @(posedge clk) begin 59 | if(en) delay_line[0] <= din; 60 | end 61 | endmodule 62 | -------------------------------------------------------------------------------- /Block_LMS_Simulation/BLMS.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0_ooc.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | ################# 52 | #DEFAULT CLOCK CONSTRAINTS 53 | 54 | ############################################################ 55 | # Clock Period Constraints # 56 | ############################################################ 57 | #create_clock -period 10.0 [get_ports clk_in1] 58 | 59 | -------------------------------------------------------------------------------- /Block_FIR_Simulation/Block_FIR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0_ooc.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | ################# 52 | #DEFAULT CLOCK CONSTRAINTS 53 | 54 | ############################################################ 55 | # Clock Period Constraints # 56 | ############################################################ 57 | #create_clock -period 10.0 [get_ports clk_in1] 58 | 59 | -------------------------------------------------------------------------------- /Block_LMS_Implementation/BLMS.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0_ooc.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | ################# 52 | #DEFAULT CLOCK CONSTRAINTS 53 | 54 | ############################################################ 55 | # Clock Period Constraints # 56 | ############################################################ 57 | #create_clock -period 10.0 [get_ports clk_in1] 58 | 59 | -------------------------------------------------------------------------------- /Block_FIR_Implementation/Block_FIR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0_ooc.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | ################# 52 | #DEFAULT CLOCK CONSTRAINTS 53 | 54 | ############################################################ 55 | # Clock Period Constraints # 56 | ############################################################ 57 | #create_clock -period 10.0 [get_ports clk_in1] 58 | 59 | -------------------------------------------------------------------------------- /FIR_Simulation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0_ooc.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | ################# 52 | #DEFAULT CLOCK CONSTRAINTS 53 | 54 | ############################################################ 55 | # Clock Period Constraints # 56 | ############################################################ 57 | #create_clock -period 10.0 [get_ports clk_in1] 58 | 59 | -------------------------------------------------------------------------------- /LMS_Simulation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0_ooc.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | ################# 52 | #DEFAULT CLOCK CONSTRAINTS 53 | 54 | ############################################################ 55 | # Clock Period Constraints # 56 | ############################################################ 57 | #create_clock -period 10.0 [get_ports clk_in1] 58 | 59 | -------------------------------------------------------------------------------- /FIR_Implementation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0_ooc.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | ################# 52 | #DEFAULT CLOCK CONSTRAINTS 53 | 54 | ############################################################ 55 | # Clock Period Constraints # 56 | ############################################################ 57 | #create_clock -period 10.0 [get_ports clk_in1] 58 | 59 | -------------------------------------------------------------------------------- /LMS_Implementation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0_ooc.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | ################# 52 | #DEFAULT CLOCK CONSTRAINTS 53 | 54 | ############################################################ 55 | # Clock Period Constraints # 56 | ############################################################ 57 | #create_clock -period 10.0 [get_ports clk_in1] 58 | 59 | -------------------------------------------------------------------------------- /Block_LMS_Simulation/BLMS.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # Input clock periods. These duplicate the values entered for the 52 | # input clocks. You can use these to time your system. If required 53 | # commented constraints can be used in the top level xdc 54 | #---------------------------------------------------------------- 55 | # Connect to input port when clock capable pin is selected for input 56 | create_clock -period 10.0 [get_ports clk_in1] 57 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 58 | 59 | 60 | -------------------------------------------------------------------------------- /Block_FIR_Simulation/Block_FIR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # Input clock periods. These duplicate the values entered for the 52 | # input clocks. You can use these to time your system. If required 53 | # commented constraints can be used in the top level xdc 54 | #---------------------------------------------------------------- 55 | # Connect to input port when clock capable pin is selected for input 56 | create_clock -period 10.0 [get_ports clk_in1] 57 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 58 | 59 | 60 | -------------------------------------------------------------------------------- /Block_LMS_Implementation/BLMS.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # Input clock periods. These duplicate the values entered for the 52 | # input clocks. You can use these to time your system. If required 53 | # commented constraints can be used in the top level xdc 54 | #---------------------------------------------------------------- 55 | # Connect to input port when clock capable pin is selected for input 56 | create_clock -period 10.0 [get_ports clk_in1] 57 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 58 | 59 | 60 | -------------------------------------------------------------------------------- /Block_FIR_Implementation/Block_FIR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # Input clock periods. These duplicate the values entered for the 52 | # input clocks. You can use these to time your system. If required 53 | # commented constraints can be used in the top level xdc 54 | #---------------------------------------------------------------- 55 | # Connect to input port when clock capable pin is selected for input 56 | create_clock -period 10.0 [get_ports clk_in1] 57 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 58 | 59 | 60 | -------------------------------------------------------------------------------- /FIR_Simulation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # Input clock periods. These duplicate the values entered for the 52 | # input clocks. You can use these to time your system. If required 53 | # commented constraints can be used in the top level xdc 54 | #---------------------------------------------------------------- 55 | # Connect to input port when clock capable pin is selected for input 56 | create_clock -period 10.0 [get_ports clk_in1] 57 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 58 | 59 | 60 | -------------------------------------------------------------------------------- /LMS_Simulation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # Input clock periods. These duplicate the values entered for the 52 | # input clocks. You can use these to time your system. If required 53 | # commented constraints can be used in the top level xdc 54 | #---------------------------------------------------------------- 55 | # Connect to input port when clock capable pin is selected for input 56 | create_clock -period 10.0 [get_ports clk_in1] 57 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 58 | 59 | 60 | -------------------------------------------------------------------------------- /FIR_Implementation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # Input clock periods. These duplicate the values entered for the 52 | # input clocks. You can use these to time your system. If required 53 | # commented constraints can be used in the top level xdc 54 | #---------------------------------------------------------------- 55 | # Connect to input port when clock capable pin is selected for input 56 | create_clock -period 10.0 [get_ports clk_in1] 57 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 58 | 59 | 60 | -------------------------------------------------------------------------------- /LMS_Implementation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clk_wiz_0.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # Input clock periods. These duplicate the values entered for the 52 | # input clocks. You can use these to time your system. If required 53 | # commented constraints can be used in the top level xdc 54 | #---------------------------------------------------------------- 55 | # Connect to input port when clock capable pin is selected for input 56 | create_clock -period 10.0 [get_ports clk_in1] 57 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 58 | 59 | 60 | -------------------------------------------------------------------------------- /FIR_Implementation/project_1/project_1.srcs/sources_1/new/FIR_Filter.v: -------------------------------------------------------------------------------- 1 | `define FILT_LENGTH 16 2 | 3 | module FIR_Filter( 4 | input clk, 5 | input en, 6 | input [15:0]din, 7 | output [15:0]dout 8 | ); 9 | 10 | reg signed [15:0]coeff[`FILT_LENGTH/2-1:0]; //Filter coefficients. 11 | reg signed [15:0]delay_line[`FILT_LENGTH-1:0]; //Input delay line. 12 | wire [31:0]accum; //Accumulator for output filter calculation. 13 | integer i; //Initialization integer. 14 | genvar c; //Delay line generation variable. 15 | 16 | reg signed [16:0]preadd_regs[7:0]; //Save calc after preadd. 17 | reg signed [31:0]mult_regs[7:0]; //Save calc after multiplication. 18 | reg signed [31:0]tree1_regs[3:0]; //Save calc after first layer of adder tree. 19 | reg signed [31:0]tree2_regs[1:0]; //Save calc after first layer of adder tree. 20 | reg signed [31:0]treeout_reg; //Save calc after complete. 21 | 22 | //assign dout = treeout_reg[31:16]; 23 | 24 | //Calculate value in the accumulator. 25 | assign accum = (delay_line[0] + delay_line[15]) * coeff[0] + 26 | (delay_line[1] + delay_line[14]) * coeff[1] + 27 | (delay_line[2] + delay_line[13]) * coeff[2] + 28 | (delay_line[3] + delay_line[12]) * coeff[3] + 29 | (delay_line[4] + delay_line[11]) * coeff[4] + 30 | (delay_line[5] + delay_line[10]) * coeff[5] + 31 | (delay_line[6] + delay_line[9]) * coeff[6] + 32 | (delay_line[7] + delay_line[8]) * coeff[7]; 33 | 34 | //Assign upper 16-bits to output. 35 | assign dout = accum[31:16]; 36 | 37 | initial begin 38 | //Load the filter coefficients. 39 | coeff[0] = 16'd2320; 40 | coeff[1] = 16'd4143; 41 | coeff[2] = 16'd4592; 42 | coeff[3] = 16'd7278; 43 | coeff[4] = 16'd8423; 44 | coeff[5] = 16'd10389; 45 | coeff[6] = 16'd11269; 46 | coeff[7] = 16'd12000; 47 | 48 | //Initialize delay line. 49 | for(i = 0; i < `FILT_LENGTH; i = i+1'b1) begin 50 | delay_line[i] = 16'd0; 51 | end 52 | 53 | //Initialize the preadder regs. 54 | for(i = 0; i < 8; i = i+1'b1) begin 55 | preadd_regs[i] = 17'd0; 56 | end 57 | 58 | //Initialize the multiplier regs. 59 | for(i = 0; i < 8; i = i+1'b1) begin 60 | mult_regs[i] = 32'd0; 61 | end 62 | 63 | //Initialize the first layer of the adder tree regs. 64 | for(i = 0; i < 4; i = i+1'b1) begin 65 | tree1_regs[i] = 32'd0; 66 | end 67 | 68 | //Initialize the second layer of the adder tree regs. 69 | for(i = 0; i < 2; i = i+1'b1) begin 70 | tree2_regs[i] = 32'd0; 71 | end 72 | 73 | //Initialize the adder tree output reg. 74 | treeout_reg = 32'd0; 75 | end 76 | 77 | //Advance the data through the delay line every clock cycle. 78 | generate 79 | for (c = `FILT_LENGTH-1; c > 0; c = c - 1) begin: inc_delay 80 | always @(posedge clk) begin 81 | if(en) delay_line[c] <= delay_line[c-1]; 82 | end 83 | end 84 | endgenerate 85 | 86 | //Update with input data. 87 | always @(posedge clk) begin 88 | if(en) delay_line[0] <= din; 89 | end 90 | endmodule 91 | -------------------------------------------------------------------------------- /FIR_Implementation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo: -------------------------------------------------------------------------------- 1 | 2 | // 3 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // clk_out1___450.000______0.000______50.0_______98.066_____97.646 59 | // 60 | //---------------------------------------------------------------------------- 61 | // Input Clock Freq (MHz) Input Jitter (UI) 62 | //---------------------------------------------------------------------------- 63 | // __primary_________100.000____________0.010 64 | 65 | // The following must be inserted into your Verilog file for this 66 | // core to be instantiated. Change the instance name and port connections 67 | // (in parentheses) to your own signal names. 68 | 69 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 70 | 71 | clk_wiz_0 instance_name 72 | ( 73 | // Clock in ports 74 | .clk_in1(clk_in1), // input clk_in1 75 | // Clock out ports 76 | .clk_out1(clk_out1)); // output clk_out1 77 | // INST_TAG_END ------ End INSTANTIATION Template --------- 78 | -------------------------------------------------------------------------------- /LMS_Simulation/LMS_Adapt.v: -------------------------------------------------------------------------------- 1 | `define ADAPT_FILT_LENGTH 16 2 | module LMS_Adapt( 3 | input clk, 4 | input en, 5 | input [15:0]din, 6 | input signed [15:0]desired, 7 | output signed [15:0]dout, 8 | output signed [15:0]err 9 | ); 10 | 11 | parameter MU = 16'd32767; 12 | 13 | reg signed [15:0]mu = MU; 14 | reg signed [15:0]coeff[`ADAPT_FILT_LENGTH-1:0]; //Filter coefficients. 15 | reg signed [15:0]delay_line[`ADAPT_FILT_LENGTH-1:0]; //Input delay line. 16 | wire signed [31:0]accum; //Accumulator for output filter calculation. 17 | wire signed [31:0]stepped; //Error after step sized applied. 18 | integer i; //Initialization integer. 19 | genvar c; //Delay line generation variable. 20 | 21 | //Calculate the error and multiply it by the step size. 22 | assign err = desired - dout; 23 | //assign stepped = err * mu; 24 | assign stepped = err << 15; 25 | 26 | //Calculate value in the accumulator. 27 | assign accum = delay_line[0]*coeff[0] + 28 | delay_line[1]*coeff[1] + 29 | delay_line[2]*coeff[2] + 30 | delay_line[3]*coeff[3] + 31 | delay_line[4]*coeff[4] + 32 | delay_line[5]*coeff[5] + 33 | delay_line[6]*coeff[6] + 34 | delay_line[7]*coeff[7] + 35 | delay_line[8]*coeff[8] + 36 | delay_line[9]*coeff[9] + 37 | delay_line[10]*coeff[10] + 38 | delay_line[11]*coeff[11] + 39 | delay_line[12]*coeff[12] + 40 | delay_line[13]*coeff[13] + 41 | delay_line[14]*coeff[14] + 42 | delay_line[15]*coeff[15]; 43 | 44 | //Assign upper 16-bits to output. 45 | assign dout = accum[31:16]; 46 | 47 | initial begin 48 | //Load the filter coefficients. 49 | coeff[0] = 20'd0; 50 | coeff[1] = 20'd0; 51 | coeff[2] = 20'd0; 52 | coeff[3] = 20'd0; 53 | coeff[4] = 20'd0; 54 | coeff[5] = 20'd0; 55 | coeff[6] = 20'd0; 56 | coeff[7] = 20'd0; 57 | coeff[8] = 20'd0; 58 | coeff[9] = 20'd0; 59 | coeff[10] = 20'd0; 60 | coeff[11] = 20'd0; 61 | coeff[12] = 20'd0; 62 | coeff[13] = 20'd0; 63 | coeff[14] = 20'd0; 64 | coeff[15] = 20'd0; 65 | 66 | //Initialize delay line. 67 | for(i = 0; i < `ADAPT_FILT_LENGTH; i = i+1'b1) begin 68 | delay_line[i] = 16'd0; 69 | end 70 | end 71 | 72 | //Advance the data through the delay line every clock cycle. 73 | generate 74 | for (c = `ADAPT_FILT_LENGTH-1; c > 0; c = c - 1) begin: inc_delay 75 | always @(posedge clk) begin 76 | if(en) delay_line[c] <= delay_line[c-1]; 77 | end 78 | end 79 | endgenerate 80 | 81 | //Update with input data. 82 | always @(posedge clk) begin 83 | if(en) delay_line[0] <= din; 84 | end 85 | 86 | wire signed [31:0]num2[`ADAPT_FILT_LENGTH-1:0]; 87 | wire signed [15:0]n1[`ADAPT_FILT_LENGTH-1:0]; 88 | wire signed [15:0]n2[`ADAPT_FILT_LENGTH-1:0]; 89 | 90 | //Update the coefficients with the LMS algorithm. 91 | generate 92 | for (c = `ADAPT_FILT_LENGTH; c > 0; c = c - 1) begin: adapt_update 93 | assign n1[c-1] = stepped[31:16]; 94 | 95 | assign num2[c-1] = n1[c-1]*delay_line[c-1]; 96 | assign n2[c-1] = num2[c-1][31:16]; 97 | 98 | always @(posedge clk) begin 99 | if(en) coeff[c-1] <= coeff[c-1] + n2[c-1]; 100 | end 101 | end 102 | endgenerate 103 | endmodule 104 | -------------------------------------------------------------------------------- /LMS_Implementation/LMS_Adapt.v: -------------------------------------------------------------------------------- 1 | `define ADAPT_FILT_LENGTH 16 2 | module LMS_Adapt( 3 | input clk, 4 | input en, 5 | input [15:0]din, 6 | input signed [15:0]desired, 7 | output signed [15:0]dout, 8 | output signed [15:0]err 9 | ); 10 | 11 | parameter MU = 16'd32767; 12 | 13 | reg signed [15:0]mu = MU; 14 | reg signed [15:0]coeff[`ADAPT_FILT_LENGTH-1:0]; //Filter coefficients. 15 | reg signed [15:0]delay_line[`ADAPT_FILT_LENGTH-1:0]; //Input delay line. 16 | wire signed [31:0]accum; //Accumulator for output filter calculation. 17 | wire signed [31:0]stepped; //Error after step sized applied. 18 | integer i; //Initialization integer. 19 | genvar c; //Delay line generation variable. 20 | 21 | //Calculate the error and multiply it by the step size. 22 | assign err = desired - dout; 23 | //assign stepped = err * mu; 24 | assign stepped = err << 15; 25 | 26 | //Calculate value in the accumulator. 27 | assign accum = delay_line[0]*coeff[0] + 28 | delay_line[1]*coeff[1] + 29 | delay_line[2]*coeff[2] + 30 | delay_line[3]*coeff[3] + 31 | delay_line[4]*coeff[4] + 32 | delay_line[5]*coeff[5] + 33 | delay_line[6]*coeff[6] + 34 | delay_line[7]*coeff[7] + 35 | delay_line[8]*coeff[8] + 36 | delay_line[9]*coeff[9] + 37 | delay_line[10]*coeff[10] + 38 | delay_line[11]*coeff[11] + 39 | delay_line[12]*coeff[12] + 40 | delay_line[13]*coeff[13] + 41 | delay_line[14]*coeff[14] + 42 | delay_line[15]*coeff[15]; 43 | 44 | //Assign upper 16-bits to output. 45 | assign dout = accum[31:16]; 46 | 47 | initial begin 48 | //Load the filter coefficients. 49 | coeff[0] = 20'd0; 50 | coeff[1] = 20'd0; 51 | coeff[2] = 20'd0; 52 | coeff[3] = 20'd0; 53 | coeff[4] = 20'd0; 54 | coeff[5] = 20'd0; 55 | coeff[6] = 20'd0; 56 | coeff[7] = 20'd0; 57 | coeff[8] = 20'd0; 58 | coeff[9] = 20'd0; 59 | coeff[10] = 20'd0; 60 | coeff[11] = 20'd0; 61 | coeff[12] = 20'd0; 62 | coeff[13] = 20'd0; 63 | coeff[14] = 20'd0; 64 | coeff[15] = 20'd0; 65 | 66 | //Initialize delay line. 67 | for(i = 0; i < `ADAPT_FILT_LENGTH; i = i+1'b1) begin 68 | delay_line[i] = 16'd0; 69 | end 70 | end 71 | 72 | //Advance the data through the delay line every clock cycle. 73 | generate 74 | for (c = `ADAPT_FILT_LENGTH-1; c > 0; c = c - 1) begin: inc_delay 75 | always @(posedge clk) begin 76 | if(en) delay_line[c] <= delay_line[c-1]; 77 | end 78 | end 79 | endgenerate 80 | 81 | //Update with input data. 82 | always @(posedge clk) begin 83 | if(en) delay_line[0] <= din; 84 | end 85 | 86 | wire signed [31:0]num2[`ADAPT_FILT_LENGTH-1:0]; 87 | wire signed [15:0]n1[`ADAPT_FILT_LENGTH-1:0]; 88 | wire signed [15:0]n2[`ADAPT_FILT_LENGTH-1:0]; 89 | 90 | //Update the coefficients with the LMS algorithm. 91 | generate 92 | for (c = `ADAPT_FILT_LENGTH; c > 0; c = c - 1) begin: adapt_update 93 | assign n1[c-1] = stepped[31:16]; 94 | 95 | assign num2[c-1] = n1[c-1]*delay_line[c-1]; 96 | assign n2[c-1] = num2[c-1][31:16]; 97 | 98 | always @(posedge clk) begin 99 | if(en) coeff[c-1] <= coeff[c-1] + n2[c-1]; 100 | end 101 | end 102 | endgenerate 103 | endmodule 104 | -------------------------------------------------------------------------------- /Block_LMS_Simulation/BLMS.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo: -------------------------------------------------------------------------------- 1 | 2 | // 3 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // clk_out1____50.000______0.000______50.0______151.636_____98.575 59 | // clk_out2____25.000______0.000______50.0______175.402_____98.575 60 | // 61 | //---------------------------------------------------------------------------- 62 | // Input Clock Freq (MHz) Input Jitter (UI) 63 | //---------------------------------------------------------------------------- 64 | // __primary_________100.000____________0.010 65 | 66 | // The following must be inserted into your Verilog file for this 67 | // core to be instantiated. Change the instance name and port connections 68 | // (in parentheses) to your own signal names. 69 | 70 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 71 | 72 | clk_wiz_0 instance_name 73 | ( 74 | // Clock in ports 75 | .clk_in1(clk_in1), // input clk_in1 76 | // Clock out ports 77 | .clk_out1(clk_out1), // output clk_out1 78 | .clk_out2(clk_out2)); // output clk_out2 79 | // INST_TAG_END ------ End INSTANTIATION Template --------- 80 | -------------------------------------------------------------------------------- /Block_FIR_Simulation/Block_FIR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo: -------------------------------------------------------------------------------- 1 | 2 | // 3 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // clk_out1____60.000______0.000______50.0______254.384____300.046 59 | // clk_out2____15.000____180.000______50.0______325.072____300.046 60 | // 61 | //---------------------------------------------------------------------------- 62 | // Input Clock Freq (MHz) Input Jitter (UI) 63 | //---------------------------------------------------------------------------- 64 | // __primary_________100.000____________0.010 65 | 66 | // The following must be inserted into your Verilog file for this 67 | // core to be instantiated. Change the instance name and port connections 68 | // (in parentheses) to your own signal names. 69 | 70 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 71 | 72 | clk_wiz_0 instance_name 73 | ( 74 | // Clock in ports 75 | .clk_in1(clk_in1), // input clk_in1 76 | // Clock out ports 77 | .clk_out1(clk_out1), // output clk_out1 78 | .clk_out2(clk_out2)); // output clk_out2 79 | // INST_TAG_END ------ End INSTANTIATION Template --------- 80 | -------------------------------------------------------------------------------- /Block_LMS_Implementation/BLMS.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo: -------------------------------------------------------------------------------- 1 | 2 | // 3 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // clk_out1____10.000______0.000______50.0______559.472____346.848 59 | // clk_out2_____5.000______0.000______50.0______631.442____346.848 60 | // 61 | //---------------------------------------------------------------------------- 62 | // Input Clock Freq (MHz) Input Jitter (UI) 63 | //---------------------------------------------------------------------------- 64 | // __primary_________100.000____________0.010 65 | 66 | // The following must be inserted into your Verilog file for this 67 | // core to be instantiated. Change the instance name and port connections 68 | // (in parentheses) to your own signal names. 69 | 70 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 71 | 72 | clk_wiz_0 instance_name 73 | ( 74 | // Clock in ports 75 | .clk_in1(clk_in1), // input clk_in1 76 | // Clock out ports 77 | .clk_out1(clk_out1), // output clk_out1 78 | .clk_out2(clk_out2)); // output clk_out2 79 | // INST_TAG_END ------ End INSTANTIATION Template --------- 80 | -------------------------------------------------------------------------------- /Block_FIR_Implementation/Block_FIR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo: -------------------------------------------------------------------------------- 1 | 2 | // 3 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // clk_out1____60.000______0.000______50.0______254.384____300.046 59 | // clk_out2____15.000____180.000______50.0______325.072____300.046 60 | // 61 | //---------------------------------------------------------------------------- 62 | // Input Clock Freq (MHz) Input Jitter (UI) 63 | //---------------------------------------------------------------------------- 64 | // __primary_________100.000____________0.010 65 | 66 | // The following must be inserted into your Verilog file for this 67 | // core to be instantiated. Change the instance name and port connections 68 | // (in parentheses) to your own signal names. 69 | 70 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 71 | 72 | clk_wiz_0 instance_name 73 | ( 74 | // Clock in ports 75 | .clk_in1(clk_in1), // input clk_in1 76 | // Clock out ports 77 | .clk_out1(clk_out1), // output clk_out1 78 | .clk_out2(clk_out2)); // output clk_out2 79 | // INST_TAG_END ------ End INSTANTIATION Template --------- 80 | -------------------------------------------------------------------------------- /FIR_Simulation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo: -------------------------------------------------------------------------------- 1 | 2 | // 3 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // clk_out1___264.000______0.000______50.0______212.484____296.868 59 | // 60 | //---------------------------------------------------------------------------- 61 | // Input Clock Freq (MHz) Input Jitter (UI) 62 | //---------------------------------------------------------------------------- 63 | // __primary_________100.000____________0.010 64 | 65 | // The following must be inserted into your Verilog file for this 66 | // core to be instantiated. Change the instance name and port connections 67 | // (in parentheses) to your own signal names. 68 | 69 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 70 | 71 | clk_wiz_0 instance_name 72 | ( 73 | // Clock in ports 74 | .clk_in1(clk_in1), // input clk_in1 75 | // Clock out ports 76 | .clk_out1(clk_out1), // output clk_out1 77 | // Status and control signals 78 | .reset(reset), // input reset 79 | .locked(locked)); // output locked 80 | // INST_TAG_END ------ End INSTANTIATION Template --------- 81 | -------------------------------------------------------------------------------- /LMS_Implementation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo: -------------------------------------------------------------------------------- 1 | 2 | // 3 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // clk_out1____19.800______0.000______50.0______322.864____296.868 59 | // 60 | //---------------------------------------------------------------------------- 61 | // Input Clock Freq (MHz) Input Jitter (UI) 62 | //---------------------------------------------------------------------------- 63 | // __primary_________100.000____________0.010 64 | 65 | // The following must be inserted into your Verilog file for this 66 | // core to be instantiated. Change the instance name and port connections 67 | // (in parentheses) to your own signal names. 68 | 69 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 70 | 71 | clk_wiz_0 instance_name 72 | ( 73 | // Clock in ports 74 | .clk_in1(clk_in1), // input clk_in1 75 | // Clock out ports 76 | .clk_out1(clk_out1), // output clk_out1 77 | // Status and control signals 78 | .reset(reset), // input reset 79 | .locked(locked)); // output locked 80 | // INST_TAG_END ------ End INSTANTIATION Template --------- 81 | -------------------------------------------------------------------------------- /LMS_Simulation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo: -------------------------------------------------------------------------------- 1 | 2 | // 3 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // clk_out1____19.800______0.000______50.0______322.864____296.868 59 | // 60 | //---------------------------------------------------------------------------- 61 | // Input Clock Freq (MHz) Input Jitter (UI) 62 | //---------------------------------------------------------------------------- 63 | // __primary_________100.000____________0.010 64 | 65 | // The following must be inserted into your Verilog file for this 66 | // core to be instantiated. Change the instance name and port connections 67 | // (in parentheses) to your own signal names. 68 | 69 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 70 | 71 | clk_wiz_0 instance_name 72 | ( 73 | // Clock in ports 74 | .clk_in1(clk_in1), // input clk_in1 75 | // Clock out ports 76 | .clk_out1(clk_out1), // output clk_out1 77 | // Status and control signals 78 | .reset(reset), // input reset 79 | .locked(locked)); // output locked 80 | // INST_TAG_END ------ End INSTANTIATION Template --------- 81 | -------------------------------------------------------------------------------- /FIR_Implementation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v: -------------------------------------------------------------------------------- 1 | 2 | // file: clk_wiz_0.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1___450.000______0.000______50.0_______98.066_____97.646 60 | // 61 | //---------------------------------------------------------------------------- 62 | // Input Clock Freq (MHz) Input Jitter (UI) 63 | //---------------------------------------------------------------------------- 64 | // __primary_________100.000____________0.010 65 | 66 | `timescale 1ps/1ps 67 | 68 | (* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_3_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 69 | 70 | module clk_wiz_0 71 | ( 72 | // Clock in ports 73 | input clk_in1, 74 | // Clock out ports 75 | output clk_out1 76 | ); 77 | 78 | clk_wiz_0_clk_wiz inst 79 | ( 80 | // Clock in ports 81 | .clk_in1(clk_in1), 82 | // Clock out ports 83 | .clk_out1(clk_out1) 84 | ); 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /Block_LMS_Simulation/BLMS.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v: -------------------------------------------------------------------------------- 1 | 2 | // file: clk_wiz_0.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1____50.000______0.000______50.0______151.636_____98.575 60 | // clk_out2____25.000______0.000______50.0______175.402_____98.575 61 | // 62 | //---------------------------------------------------------------------------- 63 | // Input Clock Freq (MHz) Input Jitter (UI) 64 | //---------------------------------------------------------------------------- 65 | // __primary_________100.000____________0.010 66 | 67 | `timescale 1ps/1ps 68 | 69 | (* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_3_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 70 | 71 | module clk_wiz_0 72 | ( 73 | // Clock in ports 74 | input clk_in1, 75 | // Clock out ports 76 | output clk_out1, 77 | output clk_out2 78 | ); 79 | 80 | clk_wiz_0_clk_wiz inst 81 | ( 82 | // Clock in ports 83 | .clk_in1(clk_in1), 84 | // Clock out ports 85 | .clk_out1(clk_out1), 86 | .clk_out2(clk_out2) 87 | ); 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /Block_FIR_Simulation/Block_FIR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v: -------------------------------------------------------------------------------- 1 | 2 | // file: clk_wiz_0.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1____60.000______0.000______50.0______254.384____300.046 60 | // clk_out2____15.000____180.000______50.0______325.072____300.046 61 | // 62 | //---------------------------------------------------------------------------- 63 | // Input Clock Freq (MHz) Input Jitter (UI) 64 | //---------------------------------------------------------------------------- 65 | // __primary_________100.000____________0.010 66 | 67 | `timescale 1ps/1ps 68 | 69 | (* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_3_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 70 | 71 | module clk_wiz_0 72 | ( 73 | // Clock in ports 74 | input clk_in1, 75 | // Clock out ports 76 | output clk_out1, 77 | output clk_out2 78 | ); 79 | 80 | clk_wiz_0_clk_wiz inst 81 | ( 82 | // Clock in ports 83 | .clk_in1(clk_in1), 84 | // Clock out ports 85 | .clk_out1(clk_out1), 86 | .clk_out2(clk_out2) 87 | ); 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /Block_LMS_Implementation/BLMS.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v: -------------------------------------------------------------------------------- 1 | 2 | // file: clk_wiz_0.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1____10.000______0.000______50.0______559.472____346.848 60 | // clk_out2_____5.000______0.000______50.0______631.442____346.848 61 | // 62 | //---------------------------------------------------------------------------- 63 | // Input Clock Freq (MHz) Input Jitter (UI) 64 | //---------------------------------------------------------------------------- 65 | // __primary_________100.000____________0.010 66 | 67 | `timescale 1ps/1ps 68 | 69 | (* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_3_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 70 | 71 | module clk_wiz_0 72 | ( 73 | // Clock in ports 74 | input clk_in1, 75 | // Clock out ports 76 | output clk_out1, 77 | output clk_out2 78 | ); 79 | 80 | clk_wiz_0_clk_wiz inst 81 | ( 82 | // Clock in ports 83 | .clk_in1(clk_in1), 84 | // Clock out ports 85 | .clk_out1(clk_out1), 86 | .clk_out2(clk_out2) 87 | ); 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /Block_FIR_Implementation/Block_FIR.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v: -------------------------------------------------------------------------------- 1 | 2 | // file: clk_wiz_0.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1____60.000______0.000______50.0______254.384____300.046 60 | // clk_out2____15.000____180.000______50.0______325.072____300.046 61 | // 62 | //---------------------------------------------------------------------------- 63 | // Input Clock Freq (MHz) Input Jitter (UI) 64 | //---------------------------------------------------------------------------- 65 | // __primary_________100.000____________0.010 66 | 67 | `timescale 1ps/1ps 68 | 69 | (* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_3_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 70 | 71 | module clk_wiz_0 72 | ( 73 | // Clock in ports 74 | input clk_in1, 75 | // Clock out ports 76 | output clk_out1, 77 | output clk_out2 78 | ); 79 | 80 | clk_wiz_0_clk_wiz inst 81 | ( 82 | // Clock in ports 83 | .clk_in1(clk_in1), 84 | // Clock out ports 85 | .clk_out1(clk_out1), 86 | .clk_out2(clk_out2) 87 | ); 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /LMS_Simulation/ToneGen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module ToneGen( 4 | input clk, 5 | input en, 6 | output [15:0]dout 7 | ); 8 | 9 | //Tone generation data. At a 44KHz sampling rate, the lookup table 10 | //generates a 440Hz and 4.4KHz tone mixed together. 11 | reg [15:0]tonetbl[99:0]; 12 | 13 | //Pointer into the tone table. 14 | reg [6:0]toneptr = 7'h00; 15 | 16 | initial begin 17 | tonetbl[0] = 2743; 18 | tonetbl[1] = 4538; 19 | tonetbl[2] = 4799; 20 | tonetbl[3] = 3526; 21 | tonetbl[4] = 1303; 22 | tonetbl[5] = -926; 23 | tonetbl[6] = -2214; 24 | tonetbl[7] = -1978; 25 | tonetbl[8] = -219; 26 | tonetbl[9] = 2478; 27 | tonetbl[10] = 5165; 28 | tonetbl[11] = 6895; 29 | tonetbl[12] = 7083; 30 | tonetbl[13] = 5726; 31 | tonetbl[14] = 3411; 32 | tonetbl[15] = 1082; 33 | tonetbl[16] = -315; 34 | tonetbl[17] = -195; 35 | tonetbl[18] = 1442; 36 | tonetbl[19] = 4009; 37 | tonetbl[20] = 6561; 38 | tonetbl[21] = 8151; 39 | tonetbl[22] = 8192; 40 | tonetbl[23] = 6685; 41 | tonetbl[24] = 4216; 42 | tonetbl[25] = 1729; 43 | tonetbl[26] = 173; 44 | tonetbl[27] = 132; 45 | tonetbl[28] = 1605; 46 | tonetbl[29] = 4009; 47 | tonetbl[30] = 6398; 48 | tonetbl[31] = 7824; 49 | tonetbl[32] = 7704; 50 | tonetbl[33] = 6037; 51 | tonetbl[34] = 3411; 52 | tonetbl[35] = 770; 53 | tonetbl[36] = -936; 54 | tonetbl[37] = -1124; 55 | tonetbl[38] = 209; 56 | tonetbl[39] = 2478; 57 | tonetbl[40] = 4737; 58 | tonetbl[41] = 6040; 59 | tonetbl[42] = 5804; 60 | tonetbl[43] = 4030; 61 | tonetbl[44] = 1303; 62 | tonetbl[45] = -1430; 63 | tonetbl[46] = -3219; 64 | tonetbl[47] = -3481; 65 | tonetbl[48] = -2213; 66 | tonetbl[49] = 0; 67 | tonetbl[50] = 2213; 68 | tonetbl[51] = 3481; 69 | tonetbl[52] = 3219; 70 | tonetbl[53] = 1430; 71 | tonetbl[54] = -1303; 72 | tonetbl[55] = -4030; 73 | tonetbl[56] = -5804; 74 | tonetbl[57] = -6040; 75 | tonetbl[58] = -4737; 76 | tonetbl[59] = -2478; 77 | tonetbl[60] = -209; 78 | tonetbl[61] = 1124; 79 | tonetbl[62] = 936; 80 | tonetbl[63] = -770; 81 | tonetbl[64] = -3411; 82 | tonetbl[65] = -6037; 83 | tonetbl[66] = -7704; 84 | tonetbl[67] = -7824; 85 | tonetbl[68] = -6398; 86 | tonetbl[69] = -4009; 87 | tonetbl[70] = -1605; 88 | tonetbl[71] = -132; 89 | tonetbl[72] = -173; 90 | tonetbl[73] = -1729; 91 | tonetbl[74] = -4216; 92 | tonetbl[75] = -6685; 93 | tonetbl[76] = -8192; 94 | tonetbl[77] = -8151; 95 | tonetbl[78] = -6561; 96 | tonetbl[79] = -4009; 97 | tonetbl[80] = -1442; 98 | tonetbl[81] = 195; 99 | tonetbl[82] = 315; 100 | tonetbl[83] = -1082; 101 | tonetbl[84] = -3411; 102 | tonetbl[85] = -5726; 103 | tonetbl[86] = -7083; 104 | tonetbl[87] = -6895; 105 | tonetbl[88] = -5165; 106 | tonetbl[89] = -2478; 107 | tonetbl[90] = 219; 108 | tonetbl[91] = 1978; 109 | tonetbl[92] = 2214; 110 | tonetbl[93] = 926; 111 | tonetbl[94] = -1303; 112 | tonetbl[95] = -3526; 113 | tonetbl[96] = -4799; 114 | tonetbl[97] = -4538; 115 | tonetbl[98] = -2743; 116 | tonetbl[99] = 0; 117 | end 118 | 119 | //Assign the output to the value in the lookup table 120 | //pointed to by toneptr. 121 | assign dout = tonetbl[toneptr]; 122 | 123 | //Increment through the tone lookup table and wrap back 124 | //to zero when at the end. 125 | always @(posedge clk) begin 126 | if(en) begin 127 | if(toneptr == 7'd99) begin 128 | toneptr <= 7'd0; 129 | end 130 | else begin 131 | toneptr <= toneptr + 1'b1; 132 | end 133 | end 134 | end 135 | endmodule 136 | -------------------------------------------------------------------------------- /LMS_Implementation/ToneGen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module ToneGen( 4 | input clk, 5 | input en, 6 | output [15:0]dout 7 | ); 8 | 9 | //Tone generation data. At a 44KHz sampling rate, the lookup table 10 | //generates a 440Hz and 4.4KHz tone mixed together. 11 | reg [15:0]tonetbl[99:0]; 12 | 13 | //Pointer into the tone table. 14 | reg [6:0]toneptr = 7'h00; 15 | 16 | initial begin 17 | tonetbl[0] = 2743; 18 | tonetbl[1] = 4538; 19 | tonetbl[2] = 4799; 20 | tonetbl[3] = 3526; 21 | tonetbl[4] = 1303; 22 | tonetbl[5] = -926; 23 | tonetbl[6] = -2214; 24 | tonetbl[7] = -1978; 25 | tonetbl[8] = -219; 26 | tonetbl[9] = 2478; 27 | tonetbl[10] = 5165; 28 | tonetbl[11] = 6895; 29 | tonetbl[12] = 7083; 30 | tonetbl[13] = 5726; 31 | tonetbl[14] = 3411; 32 | tonetbl[15] = 1082; 33 | tonetbl[16] = -315; 34 | tonetbl[17] = -195; 35 | tonetbl[18] = 1442; 36 | tonetbl[19] = 4009; 37 | tonetbl[20] = 6561; 38 | tonetbl[21] = 8151; 39 | tonetbl[22] = 8192; 40 | tonetbl[23] = 6685; 41 | tonetbl[24] = 4216; 42 | tonetbl[25] = 1729; 43 | tonetbl[26] = 173; 44 | tonetbl[27] = 132; 45 | tonetbl[28] = 1605; 46 | tonetbl[29] = 4009; 47 | tonetbl[30] = 6398; 48 | tonetbl[31] = 7824; 49 | tonetbl[32] = 7704; 50 | tonetbl[33] = 6037; 51 | tonetbl[34] = 3411; 52 | tonetbl[35] = 770; 53 | tonetbl[36] = -936; 54 | tonetbl[37] = -1124; 55 | tonetbl[38] = 209; 56 | tonetbl[39] = 2478; 57 | tonetbl[40] = 4737; 58 | tonetbl[41] = 6040; 59 | tonetbl[42] = 5804; 60 | tonetbl[43] = 4030; 61 | tonetbl[44] = 1303; 62 | tonetbl[45] = -1430; 63 | tonetbl[46] = -3219; 64 | tonetbl[47] = -3481; 65 | tonetbl[48] = -2213; 66 | tonetbl[49] = 0; 67 | tonetbl[50] = 2213; 68 | tonetbl[51] = 3481; 69 | tonetbl[52] = 3219; 70 | tonetbl[53] = 1430; 71 | tonetbl[54] = -1303; 72 | tonetbl[55] = -4030; 73 | tonetbl[56] = -5804; 74 | tonetbl[57] = -6040; 75 | tonetbl[58] = -4737; 76 | tonetbl[59] = -2478; 77 | tonetbl[60] = -209; 78 | tonetbl[61] = 1124; 79 | tonetbl[62] = 936; 80 | tonetbl[63] = -770; 81 | tonetbl[64] = -3411; 82 | tonetbl[65] = -6037; 83 | tonetbl[66] = -7704; 84 | tonetbl[67] = -7824; 85 | tonetbl[68] = -6398; 86 | tonetbl[69] = -4009; 87 | tonetbl[70] = -1605; 88 | tonetbl[71] = -132; 89 | tonetbl[72] = -173; 90 | tonetbl[73] = -1729; 91 | tonetbl[74] = -4216; 92 | tonetbl[75] = -6685; 93 | tonetbl[76] = -8192; 94 | tonetbl[77] = -8151; 95 | tonetbl[78] = -6561; 96 | tonetbl[79] = -4009; 97 | tonetbl[80] = -1442; 98 | tonetbl[81] = 195; 99 | tonetbl[82] = 315; 100 | tonetbl[83] = -1082; 101 | tonetbl[84] = -3411; 102 | tonetbl[85] = -5726; 103 | tonetbl[86] = -7083; 104 | tonetbl[87] = -6895; 105 | tonetbl[88] = -5165; 106 | tonetbl[89] = -2478; 107 | tonetbl[90] = 219; 108 | tonetbl[91] = 1978; 109 | tonetbl[92] = 2214; 110 | tonetbl[93] = 926; 111 | tonetbl[94] = -1303; 112 | tonetbl[95] = -3526; 113 | tonetbl[96] = -4799; 114 | tonetbl[97] = -4538; 115 | tonetbl[98] = -2743; 116 | tonetbl[99] = 0; 117 | end 118 | 119 | //Assign the output to the value in the lookup table 120 | //pointed to by toneptr. 121 | assign dout = tonetbl[toneptr]; 122 | 123 | //Increment through the tone lookup table and wrap back 124 | //to zero when at the end. 125 | always @(posedge clk) begin 126 | if(en) begin 127 | if(toneptr == 7'd99) begin 128 | toneptr <= 7'd0; 129 | end 130 | else begin 131 | toneptr <= toneptr + 1'b1; 132 | end 133 | end 134 | end 135 | endmodule 136 | -------------------------------------------------------------------------------- /Block_LMS_Simulation/BLMS.srcs/sources_1/new/ToneGen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module ToneGen( 4 | input clk, 5 | input en, 6 | output [15:0]dout 7 | ); 8 | 9 | //Tone generation data. At a 44KHz sampling rate, the lookup table 10 | //generates a 440Hz and 4.4KHz tone mixed together. 11 | reg [15:0]tonetbl[99:0]; 12 | 13 | //Pointer into the tone table. 14 | reg [6:0]toneptr = 7'h00; 15 | 16 | initial begin 17 | tonetbl[0] = 2743; 18 | tonetbl[1] = 4538; 19 | tonetbl[2] = 4799; 20 | tonetbl[3] = 3526; 21 | tonetbl[4] = 1303; 22 | tonetbl[5] = -926; 23 | tonetbl[6] = -2214; 24 | tonetbl[7] = -1978; 25 | tonetbl[8] = -219; 26 | tonetbl[9] = 2478; 27 | tonetbl[10] = 5165; 28 | tonetbl[11] = 6895; 29 | tonetbl[12] = 7083; 30 | tonetbl[13] = 5726; 31 | tonetbl[14] = 3411; 32 | tonetbl[15] = 1082; 33 | tonetbl[16] = -315; 34 | tonetbl[17] = -195; 35 | tonetbl[18] = 1442; 36 | tonetbl[19] = 4009; 37 | tonetbl[20] = 6561; 38 | tonetbl[21] = 8151; 39 | tonetbl[22] = 8192; 40 | tonetbl[23] = 6685; 41 | tonetbl[24] = 4216; 42 | tonetbl[25] = 1729; 43 | tonetbl[26] = 173; 44 | tonetbl[27] = 132; 45 | tonetbl[28] = 1605; 46 | tonetbl[29] = 4009; 47 | tonetbl[30] = 6398; 48 | tonetbl[31] = 7824; 49 | tonetbl[32] = 7704; 50 | tonetbl[33] = 6037; 51 | tonetbl[34] = 3411; 52 | tonetbl[35] = 770; 53 | tonetbl[36] = -936; 54 | tonetbl[37] = -1124; 55 | tonetbl[38] = 209; 56 | tonetbl[39] = 2478; 57 | tonetbl[40] = 4737; 58 | tonetbl[41] = 6040; 59 | tonetbl[42] = 5804; 60 | tonetbl[43] = 4030; 61 | tonetbl[44] = 1303; 62 | tonetbl[45] = -1430; 63 | tonetbl[46] = -3219; 64 | tonetbl[47] = -3481; 65 | tonetbl[48] = -2213; 66 | tonetbl[49] = 0; 67 | tonetbl[50] = 2213; 68 | tonetbl[51] = 3481; 69 | tonetbl[52] = 3219; 70 | tonetbl[53] = 1430; 71 | tonetbl[54] = -1303; 72 | tonetbl[55] = -4030; 73 | tonetbl[56] = -5804; 74 | tonetbl[57] = -6040; 75 | tonetbl[58] = -4737; 76 | tonetbl[59] = -2478; 77 | tonetbl[60] = -209; 78 | tonetbl[61] = 1124; 79 | tonetbl[62] = 936; 80 | tonetbl[63] = -770; 81 | tonetbl[64] = -3411; 82 | tonetbl[65] = -6037; 83 | tonetbl[66] = -7704; 84 | tonetbl[67] = -7824; 85 | tonetbl[68] = -6398; 86 | tonetbl[69] = -4009; 87 | tonetbl[70] = -1605; 88 | tonetbl[71] = -132; 89 | tonetbl[72] = -173; 90 | tonetbl[73] = -1729; 91 | tonetbl[74] = -4216; 92 | tonetbl[75] = -6685; 93 | tonetbl[76] = -8192; 94 | tonetbl[77] = -8151; 95 | tonetbl[78] = -6561; 96 | tonetbl[79] = -4009; 97 | tonetbl[80] = -1442; 98 | tonetbl[81] = 195; 99 | tonetbl[82] = 315; 100 | tonetbl[83] = -1082; 101 | tonetbl[84] = -3411; 102 | tonetbl[85] = -5726; 103 | tonetbl[86] = -7083; 104 | tonetbl[87] = -6895; 105 | tonetbl[88] = -5165; 106 | tonetbl[89] = -2478; 107 | tonetbl[90] = 219; 108 | tonetbl[91] = 1978; 109 | tonetbl[92] = 2214; 110 | tonetbl[93] = 926; 111 | tonetbl[94] = -1303; 112 | tonetbl[95] = -3526; 113 | tonetbl[96] = -4799; 114 | tonetbl[97] = -4538; 115 | tonetbl[98] = -2743; 116 | tonetbl[99] = 0; 117 | end 118 | 119 | //Assign the output to the value in the lookup table 120 | //pointed to by toneptr. 121 | assign dout = tonetbl[toneptr]; 122 | 123 | //Increment through the tone lookup table and wrap back 124 | //to zero when at the end. 125 | always @(posedge clk) begin 126 | if(en) begin 127 | if(toneptr == 7'd99) begin 128 | toneptr <= 7'd0; 129 | end 130 | else begin 131 | toneptr <= toneptr + 1'b1; 132 | end 133 | end 134 | end 135 | endmodule 136 | -------------------------------------------------------------------------------- /Block_LMS_Implementation/BLMS.srcs/sources_1/new/ToneGen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module ToneGen( 4 | input clk, 5 | input en, 6 | output [15:0]dout 7 | ); 8 | 9 | //Tone generation data. At a 44KHz sampling rate, the lookup table 10 | //generates a 440Hz and 4.4KHz tone mixed together. 11 | reg [15:0]tonetbl[99:0]; 12 | 13 | //Pointer into the tone table. 14 | reg [6:0]toneptr = 7'h00; 15 | 16 | initial begin 17 | tonetbl[0] = 2743; 18 | tonetbl[1] = 4538; 19 | tonetbl[2] = 4799; 20 | tonetbl[3] = 3526; 21 | tonetbl[4] = 1303; 22 | tonetbl[5] = -926; 23 | tonetbl[6] = -2214; 24 | tonetbl[7] = -1978; 25 | tonetbl[8] = -219; 26 | tonetbl[9] = 2478; 27 | tonetbl[10] = 5165; 28 | tonetbl[11] = 6895; 29 | tonetbl[12] = 7083; 30 | tonetbl[13] = 5726; 31 | tonetbl[14] = 3411; 32 | tonetbl[15] = 1082; 33 | tonetbl[16] = -315; 34 | tonetbl[17] = -195; 35 | tonetbl[18] = 1442; 36 | tonetbl[19] = 4009; 37 | tonetbl[20] = 6561; 38 | tonetbl[21] = 8151; 39 | tonetbl[22] = 8192; 40 | tonetbl[23] = 6685; 41 | tonetbl[24] = 4216; 42 | tonetbl[25] = 1729; 43 | tonetbl[26] = 173; 44 | tonetbl[27] = 132; 45 | tonetbl[28] = 1605; 46 | tonetbl[29] = 4009; 47 | tonetbl[30] = 6398; 48 | tonetbl[31] = 7824; 49 | tonetbl[32] = 7704; 50 | tonetbl[33] = 6037; 51 | tonetbl[34] = 3411; 52 | tonetbl[35] = 770; 53 | tonetbl[36] = -936; 54 | tonetbl[37] = -1124; 55 | tonetbl[38] = 209; 56 | tonetbl[39] = 2478; 57 | tonetbl[40] = 4737; 58 | tonetbl[41] = 6040; 59 | tonetbl[42] = 5804; 60 | tonetbl[43] = 4030; 61 | tonetbl[44] = 1303; 62 | tonetbl[45] = -1430; 63 | tonetbl[46] = -3219; 64 | tonetbl[47] = -3481; 65 | tonetbl[48] = -2213; 66 | tonetbl[49] = 0; 67 | tonetbl[50] = 2213; 68 | tonetbl[51] = 3481; 69 | tonetbl[52] = 3219; 70 | tonetbl[53] = 1430; 71 | tonetbl[54] = -1303; 72 | tonetbl[55] = -4030; 73 | tonetbl[56] = -5804; 74 | tonetbl[57] = -6040; 75 | tonetbl[58] = -4737; 76 | tonetbl[59] = -2478; 77 | tonetbl[60] = -209; 78 | tonetbl[61] = 1124; 79 | tonetbl[62] = 936; 80 | tonetbl[63] = -770; 81 | tonetbl[64] = -3411; 82 | tonetbl[65] = -6037; 83 | tonetbl[66] = -7704; 84 | tonetbl[67] = -7824; 85 | tonetbl[68] = -6398; 86 | tonetbl[69] = -4009; 87 | tonetbl[70] = -1605; 88 | tonetbl[71] = -132; 89 | tonetbl[72] = -173; 90 | tonetbl[73] = -1729; 91 | tonetbl[74] = -4216; 92 | tonetbl[75] = -6685; 93 | tonetbl[76] = -8192; 94 | tonetbl[77] = -8151; 95 | tonetbl[78] = -6561; 96 | tonetbl[79] = -4009; 97 | tonetbl[80] = -1442; 98 | tonetbl[81] = 195; 99 | tonetbl[82] = 315; 100 | tonetbl[83] = -1082; 101 | tonetbl[84] = -3411; 102 | tonetbl[85] = -5726; 103 | tonetbl[86] = -7083; 104 | tonetbl[87] = -6895; 105 | tonetbl[88] = -5165; 106 | tonetbl[89] = -2478; 107 | tonetbl[90] = 219; 108 | tonetbl[91] = 1978; 109 | tonetbl[92] = 2214; 110 | tonetbl[93] = 926; 111 | tonetbl[94] = -1303; 112 | tonetbl[95] = -3526; 113 | tonetbl[96] = -4799; 114 | tonetbl[97] = -4538; 115 | tonetbl[98] = -2743; 116 | tonetbl[99] = 0; 117 | end 118 | 119 | //Assign the output to the value in the lookup table 120 | //pointed to by toneptr. 121 | assign dout = tonetbl[toneptr]; 122 | 123 | //Increment through the tone lookup table and wrap back 124 | //to zero when at the end. 125 | always @(posedge clk) begin 126 | if(en) begin 127 | if(toneptr == 7'd99) begin 128 | toneptr <= 7'd0; 129 | end 130 | else begin 131 | toneptr <= toneptr + 1'b1; 132 | end 133 | end 134 | end 135 | endmodule 136 | -------------------------------------------------------------------------------- /FIR_Simulation/project_1/project_1.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v: -------------------------------------------------------------------------------- 1 | 2 | // file: clk_wiz_0.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1___264.000______0.000______50.0______212.484____296.868 60 | // 61 | //---------------------------------------------------------------------------- 62 | // Input Clock Freq (MHz) Input Jitter (UI) 63 | //---------------------------------------------------------------------------- 64 | // __primary_________100.000____________0.010 65 | 66 | `timescale 1ps/1ps 67 | 68 | (* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_3_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 69 | 70 | module clk_wiz_0 71 | ( 72 | // Clock in ports 73 | input clk_in1, 74 | // Clock out ports 75 | output clk_out1, 76 | // Status and control signals 77 | input reset, 78 | output locked 79 | ); 80 | 81 | clk_wiz_0_clk_wiz inst 82 | ( 83 | // Clock in ports 84 | .clk_in1(clk_in1), 85 | // Clock out ports 86 | .clk_out1(clk_out1), 87 | // Status and control signals 88 | .reset(reset), 89 | .locked(locked) 90 | ); 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /LMS_Implementation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v: -------------------------------------------------------------------------------- 1 | 2 | // file: clk_wiz_0.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1____19.800______0.000______50.0______322.864____296.868 60 | // 61 | //---------------------------------------------------------------------------- 62 | // Input Clock Freq (MHz) Input Jitter (UI) 63 | //---------------------------------------------------------------------------- 64 | // __primary_________100.000____________0.010 65 | 66 | `timescale 1ps/1ps 67 | 68 | (* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_3_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 69 | 70 | module clk_wiz_0 71 | ( 72 | // Clock in ports 73 | input clk_in1, 74 | // Clock out ports 75 | output clk_out1, 76 | // Status and control signals 77 | input reset, 78 | output locked 79 | ); 80 | 81 | clk_wiz_0_clk_wiz inst 82 | ( 83 | // Clock in ports 84 | .clk_in1(clk_in1), 85 | // Clock out ports 86 | .clk_out1(clk_out1), 87 | // Status and control signals 88 | .reset(reset), 89 | .locked(locked) 90 | ); 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /LMS_Simulation/LMS_Adaptive_Filter.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v: -------------------------------------------------------------------------------- 1 | 2 | // file: clk_wiz_0.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1____19.800______0.000______50.0______322.864____296.868 60 | // 61 | //---------------------------------------------------------------------------- 62 | // Input Clock Freq (MHz) Input Jitter (UI) 63 | //---------------------------------------------------------------------------- 64 | // __primary_________100.000____________0.010 65 | 66 | `timescale 1ps/1ps 67 | 68 | (* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_3_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 69 | 70 | module clk_wiz_0 71 | ( 72 | // Clock in ports 73 | input clk_in1, 74 | // Clock out ports 75 | output clk_out1, 76 | // Status and control signals 77 | input reset, 78 | output locked 79 | ); 80 | 81 | clk_wiz_0_clk_wiz inst 82 | ( 83 | // Clock in ports 84 | .clk_in1(clk_in1), 85 | // Clock out ports 86 | .clk_out1(clk_out1), 87 | // Status and control signals 88 | .reset(reset), 89 | .locked(locked) 90 | ); 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /FIR_Simulation/ToneGen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module ToneGen( 4 | input clk, 5 | input en, 6 | output [15:0]dout 7 | ); 8 | 9 | //Tone generation data. At a 44KHz sampling rate, the lookup table 10 | //generates a 440Hz and 4.4KHz tone mixed together. 11 | reg [15:0]tonetbl[99:0]; 12 | 13 | //Pointer into the tone table. 14 | reg [6:0]toneptr = 7'h00; 15 | 16 | initial begin 17 | tonetbl[0] = 10970; 18 | tonetbl[1] = 18151; 19 | tonetbl[2] = 19197; 20 | tonetbl[3] = 14105; 21 | tonetbl[4] = 5211; 22 | tonetbl[5] = -3704; 23 | tonetbl[6] = -8858; 24 | tonetbl[7] = -7914; 25 | tonetbl[8] = -876; 26 | tonetbl[9] = 9912; 27 | tonetbl[10] = 20660; 28 | tonetbl[11] = 27581; 29 | tonetbl[12] = 28330; 30 | tonetbl[13] = 22905; 31 | tonetbl[14] = 13642; 32 | tonetbl[15] = 4326; 33 | tonetbl[16] = -1260; 34 | tonetbl[17] = -780; 35 | tonetbl[18] = 5767; 36 | tonetbl[19] = 16037; 37 | tonetbl[20] = 26244; 38 | tonetbl[21] = 32601; 39 | tonetbl[22] = 32767; 40 | tonetbl[23] = 26741; 41 | tonetbl[24] = 16863; 42 | tonetbl[25] = 6918; 43 | tonetbl[26] = 692; 44 | tonetbl[27] = 527; 45 | tonetbl[28] = 6421; 46 | tonetbl[29] = 16037; 47 | tonetbl[30] = 25590; 48 | tonetbl[31] = 31295; 49 | tonetbl[32] = 30814; 50 | tonetbl[33] = 24149; 51 | tonetbl[34] = 13642; 52 | tonetbl[35] = 3081; 53 | tonetbl[36] = -3745; 54 | tonetbl[37] = -4494; 55 | tonetbl[38] = 837; 56 | tonetbl[39] = 9912; 57 | tonetbl[40] = 18947; 58 | tonetbl[41] = 24161; 59 | tonetbl[42] = 23217; 60 | tonetbl[43] = 16119; 61 | tonetbl[44] = 5211; 62 | tonetbl[45] = -5718; 63 | tonetbl[46] = -12878; 64 | tonetbl[47] = -13924; 65 | tonetbl[48] = -8853; 66 | tonetbl[49] = 0; 67 | tonetbl[50] = 8853; 68 | tonetbl[51] = 13924; 69 | tonetbl[52] = 12878; 70 | tonetbl[53] = 5718; 71 | tonetbl[54] = -5211; 72 | tonetbl[55] = -16119; 73 | tonetbl[56] = -23217; 74 | tonetbl[57] = -24161; 75 | tonetbl[58] = -18947; 76 | tonetbl[59] = -9912; 77 | tonetbl[60] = -837; 78 | tonetbl[61] = 4494; 79 | tonetbl[62] = 3745; 80 | tonetbl[63] = -3081; 81 | tonetbl[64] = -13642; 82 | tonetbl[65] = -24149; 83 | tonetbl[66] = -30814; 84 | tonetbl[67] = -31295; 85 | tonetbl[68] = -25590; 86 | tonetbl[69] = -16037; 87 | tonetbl[70] = -6421; 88 | tonetbl[71] = -527; 89 | tonetbl[72] = -692; 90 | tonetbl[73] = -6918; 91 | tonetbl[74] = -16863; 92 | tonetbl[75] = -26741; 93 | tonetbl[76] = -32767; 94 | tonetbl[77] = -32601; 95 | tonetbl[78] = -26244; 96 | tonetbl[79] = -16037; 97 | tonetbl[80] = -5767; 98 | tonetbl[81] = 780; 99 | tonetbl[82] = 1260; 100 | tonetbl[83] = -4326; 101 | tonetbl[84] = -13642; 102 | tonetbl[85] = -22905; 103 | tonetbl[86] = -28330; 104 | tonetbl[87] = -27581; 105 | tonetbl[88] = -20660; 106 | tonetbl[89] = -9912; 107 | tonetbl[90] = 876; 108 | tonetbl[91] = 7914; 109 | tonetbl[92] = 8858; 110 | tonetbl[93] = 3704; 111 | tonetbl[94] = -5211; 112 | tonetbl[95] = -14105; 113 | tonetbl[96] = -19197; 114 | tonetbl[97] = -18151; 115 | tonetbl[98] = -10970; 116 | tonetbl[99] = 0; 117 | end 118 | 119 | //Assign the output to the value in the lookup table 120 | //pointed to by toneptr. 121 | assign dout = tonetbl[toneptr]; 122 | 123 | //Increment through the tone lookup table and wrap back 124 | //to zero when at the end. 125 | always @(posedge clk) begin 126 | if(en) begin 127 | if(toneptr == 7'd99) begin 128 | toneptr <= 7'd0; 129 | end 130 | else begin 131 | toneptr <= toneptr + 1'b1; 132 | end 133 | end 134 | end 135 | endmodule 136 | -------------------------------------------------------------------------------- /FIR_Implementation/ToneGen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module ToneGen( 4 | input clk, 5 | input en, 6 | output [15:0]dout 7 | ); 8 | 9 | //Tone generation data. At a 44KHz sampling rate, the lookup table 10 | //generates a 440Hz and 4.4KHz tone mixed together. 11 | reg [15:0]tonetbl[99:0]; 12 | 13 | //Pointer into the tone table. 14 | reg [6:0]toneptr = 7'h00; 15 | 16 | initial begin 17 | tonetbl[0] = 10970; 18 | tonetbl[1] = 18151; 19 | tonetbl[2] = 19197; 20 | tonetbl[3] = 14105; 21 | tonetbl[4] = 5211; 22 | tonetbl[5] = -3704; 23 | tonetbl[6] = -8858; 24 | tonetbl[7] = -7914; 25 | tonetbl[8] = -876; 26 | tonetbl[9] = 9912; 27 | tonetbl[10] = 20660; 28 | tonetbl[11] = 27581; 29 | tonetbl[12] = 28330; 30 | tonetbl[13] = 22905; 31 | tonetbl[14] = 13642; 32 | tonetbl[15] = 4326; 33 | tonetbl[16] = -1260; 34 | tonetbl[17] = -780; 35 | tonetbl[18] = 5767; 36 | tonetbl[19] = 16037; 37 | tonetbl[20] = 26244; 38 | tonetbl[21] = 32601; 39 | tonetbl[22] = 32767; 40 | tonetbl[23] = 26741; 41 | tonetbl[24] = 16863; 42 | tonetbl[25] = 6918; 43 | tonetbl[26] = 692; 44 | tonetbl[27] = 527; 45 | tonetbl[28] = 6421; 46 | tonetbl[29] = 16037; 47 | tonetbl[30] = 25590; 48 | tonetbl[31] = 31295; 49 | tonetbl[32] = 30814; 50 | tonetbl[33] = 24149; 51 | tonetbl[34] = 13642; 52 | tonetbl[35] = 3081; 53 | tonetbl[36] = -3745; 54 | tonetbl[37] = -4494; 55 | tonetbl[38] = 837; 56 | tonetbl[39] = 9912; 57 | tonetbl[40] = 18947; 58 | tonetbl[41] = 24161; 59 | tonetbl[42] = 23217; 60 | tonetbl[43] = 16119; 61 | tonetbl[44] = 5211; 62 | tonetbl[45] = -5718; 63 | tonetbl[46] = -12878; 64 | tonetbl[47] = -13924; 65 | tonetbl[48] = -8853; 66 | tonetbl[49] = 0; 67 | tonetbl[50] = 8853; 68 | tonetbl[51] = 13924; 69 | tonetbl[52] = 12878; 70 | tonetbl[53] = 5718; 71 | tonetbl[54] = -5211; 72 | tonetbl[55] = -16119; 73 | tonetbl[56] = -23217; 74 | tonetbl[57] = -24161; 75 | tonetbl[58] = -18947; 76 | tonetbl[59] = -9912; 77 | tonetbl[60] = -837; 78 | tonetbl[61] = 4494; 79 | tonetbl[62] = 3745; 80 | tonetbl[63] = -3081; 81 | tonetbl[64] = -13642; 82 | tonetbl[65] = -24149; 83 | tonetbl[66] = -30814; 84 | tonetbl[67] = -31295; 85 | tonetbl[68] = -25590; 86 | tonetbl[69] = -16037; 87 | tonetbl[70] = -6421; 88 | tonetbl[71] = -527; 89 | tonetbl[72] = -692; 90 | tonetbl[73] = -6918; 91 | tonetbl[74] = -16863; 92 | tonetbl[75] = -26741; 93 | tonetbl[76] = -32767; 94 | tonetbl[77] = -32601; 95 | tonetbl[78] = -26244; 96 | tonetbl[79] = -16037; 97 | tonetbl[80] = -5767; 98 | tonetbl[81] = 780; 99 | tonetbl[82] = 1260; 100 | tonetbl[83] = -4326; 101 | tonetbl[84] = -13642; 102 | tonetbl[85] = -22905; 103 | tonetbl[86] = -28330; 104 | tonetbl[87] = -27581; 105 | tonetbl[88] = -20660; 106 | tonetbl[89] = -9912; 107 | tonetbl[90] = 876; 108 | tonetbl[91] = 7914; 109 | tonetbl[92] = 8858; 110 | tonetbl[93] = 3704; 111 | tonetbl[94] = -5211; 112 | tonetbl[95] = -14105; 113 | tonetbl[96] = -19197; 114 | tonetbl[97] = -18151; 115 | tonetbl[98] = -10970; 116 | tonetbl[99] = 0; 117 | end 118 | 119 | //Assign the output to the value in the lookup table 120 | //pointed to by toneptr. 121 | assign dout = tonetbl[toneptr]; 122 | 123 | //Increment through the tone lookup table and wrap back 124 | //to zero when at the end. 125 | always @(posedge clk) begin 126 | if(en) begin 127 | if(toneptr == 7'd99) begin 128 | toneptr <= 7'd0; 129 | end 130 | else begin 131 | toneptr <= toneptr + 1'b1; 132 | end 133 | end 134 | end 135 | endmodule 136 | -------------------------------------------------------------------------------- /Block_FIR_Simulation/Block_FIR.srcs/sources_1/new/ToneGen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module ToneGen( 4 | input clk, 5 | input en, 6 | output [15:0]dout 7 | ); 8 | 9 | //Tone generation data. At a 44KHz sampling rate, the lookup table 10 | //generates a 440Hz and 4.4KHz tone mixed together. 11 | reg [15:0]tonetbl[99:0]; 12 | 13 | //Pointer into the tone table. 14 | reg [6:0]toneptr = 7'h00; 15 | 16 | initial begin 17 | tonetbl[0] = 10970; 18 | tonetbl[1] = 18151; 19 | tonetbl[2] = 19197; 20 | tonetbl[3] = 14105; 21 | tonetbl[4] = 5211; 22 | tonetbl[5] = -3704; 23 | tonetbl[6] = -8858; 24 | tonetbl[7] = -7914; 25 | tonetbl[8] = -876; 26 | tonetbl[9] = 9912; 27 | tonetbl[10] = 20660; 28 | tonetbl[11] = 27581; 29 | tonetbl[12] = 28330; 30 | tonetbl[13] = 22905; 31 | tonetbl[14] = 13642; 32 | tonetbl[15] = 4326; 33 | tonetbl[16] = -1260; 34 | tonetbl[17] = -780; 35 | tonetbl[18] = 5767; 36 | tonetbl[19] = 16037; 37 | tonetbl[20] = 26244; 38 | tonetbl[21] = 32601; 39 | tonetbl[22] = 32767; 40 | tonetbl[23] = 26741; 41 | tonetbl[24] = 16863; 42 | tonetbl[25] = 6918; 43 | tonetbl[26] = 692; 44 | tonetbl[27] = 527; 45 | tonetbl[28] = 6421; 46 | tonetbl[29] = 16037; 47 | tonetbl[30] = 25590; 48 | tonetbl[31] = 31295; 49 | tonetbl[32] = 30814; 50 | tonetbl[33] = 24149; 51 | tonetbl[34] = 13642; 52 | tonetbl[35] = 3081; 53 | tonetbl[36] = -3745; 54 | tonetbl[37] = -4494; 55 | tonetbl[38] = 837; 56 | tonetbl[39] = 9912; 57 | tonetbl[40] = 18947; 58 | tonetbl[41] = 24161; 59 | tonetbl[42] = 23217; 60 | tonetbl[43] = 16119; 61 | tonetbl[44] = 5211; 62 | tonetbl[45] = -5718; 63 | tonetbl[46] = -12878; 64 | tonetbl[47] = -13924; 65 | tonetbl[48] = -8853; 66 | tonetbl[49] = 0; 67 | tonetbl[50] = 8853; 68 | tonetbl[51] = 13924; 69 | tonetbl[52] = 12878; 70 | tonetbl[53] = 5718; 71 | tonetbl[54] = -5211; 72 | tonetbl[55] = -16119; 73 | tonetbl[56] = -23217; 74 | tonetbl[57] = -24161; 75 | tonetbl[58] = -18947; 76 | tonetbl[59] = -9912; 77 | tonetbl[60] = -837; 78 | tonetbl[61] = 4494; 79 | tonetbl[62] = 3745; 80 | tonetbl[63] = -3081; 81 | tonetbl[64] = -13642; 82 | tonetbl[65] = -24149; 83 | tonetbl[66] = -30814; 84 | tonetbl[67] = -31295; 85 | tonetbl[68] = -25590; 86 | tonetbl[69] = -16037; 87 | tonetbl[70] = -6421; 88 | tonetbl[71] = -527; 89 | tonetbl[72] = -692; 90 | tonetbl[73] = -6918; 91 | tonetbl[74] = -16863; 92 | tonetbl[75] = -26741; 93 | tonetbl[76] = -32767; 94 | tonetbl[77] = -32601; 95 | tonetbl[78] = -26244; 96 | tonetbl[79] = -16037; 97 | tonetbl[80] = -5767; 98 | tonetbl[81] = 780; 99 | tonetbl[82] = 1260; 100 | tonetbl[83] = -4326; 101 | tonetbl[84] = -13642; 102 | tonetbl[85] = -22905; 103 | tonetbl[86] = -28330; 104 | tonetbl[87] = -27581; 105 | tonetbl[88] = -20660; 106 | tonetbl[89] = -9912; 107 | tonetbl[90] = 876; 108 | tonetbl[91] = 7914; 109 | tonetbl[92] = 8858; 110 | tonetbl[93] = 3704; 111 | tonetbl[94] = -5211; 112 | tonetbl[95] = -14105; 113 | tonetbl[96] = -19197; 114 | tonetbl[97] = -18151; 115 | tonetbl[98] = -10970; 116 | tonetbl[99] = 0; 117 | end 118 | 119 | //Assign the output to the value in the lookup table 120 | //pointed to by toneptr. 121 | assign dout = tonetbl[toneptr]; 122 | 123 | //Increment through the tone lookup table and wrap back 124 | //to zero when at the end. 125 | always @(posedge clk) begin 126 | if(en) begin 127 | if(toneptr == 7'd99) begin 128 | toneptr <= 7'd0; 129 | end 130 | else begin 131 | toneptr <= toneptr + 1'b1; 132 | end 133 | end 134 | end 135 | endmodule 136 | -------------------------------------------------------------------------------- /Block_FIR_Implementation/Block_FIR.srcs/sources_1/new/ToneGen.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module ToneGen( 4 | input clk, 5 | input en, 6 | output [15:0]dout 7 | ); 8 | 9 | //Tone generation data. At a 44KHz sampling rate, the lookup table 10 | //generates a 440Hz and 4.4KHz tone mixed together. 11 | reg [15:0]tonetbl[99:0]; 12 | 13 | //Pointer into the tone table. 14 | reg [6:0]toneptr = 7'h00; 15 | 16 | initial begin 17 | tonetbl[0] = 10970; 18 | tonetbl[1] = 18151; 19 | tonetbl[2] = 19197; 20 | tonetbl[3] = 14105; 21 | tonetbl[4] = 5211; 22 | tonetbl[5] = -3704; 23 | tonetbl[6] = -8858; 24 | tonetbl[7] = -7914; 25 | tonetbl[8] = -876; 26 | tonetbl[9] = 9912; 27 | tonetbl[10] = 20660; 28 | tonetbl[11] = 27581; 29 | tonetbl[12] = 28330; 30 | tonetbl[13] = 22905; 31 | tonetbl[14] = 13642; 32 | tonetbl[15] = 4326; 33 | tonetbl[16] = -1260; 34 | tonetbl[17] = -780; 35 | tonetbl[18] = 5767; 36 | tonetbl[19] = 16037; 37 | tonetbl[20] = 26244; 38 | tonetbl[21] = 32601; 39 | tonetbl[22] = 32767; 40 | tonetbl[23] = 26741; 41 | tonetbl[24] = 16863; 42 | tonetbl[25] = 6918; 43 | tonetbl[26] = 692; 44 | tonetbl[27] = 527; 45 | tonetbl[28] = 6421; 46 | tonetbl[29] = 16037; 47 | tonetbl[30] = 25590; 48 | tonetbl[31] = 31295; 49 | tonetbl[32] = 30814; 50 | tonetbl[33] = 24149; 51 | tonetbl[34] = 13642; 52 | tonetbl[35] = 3081; 53 | tonetbl[36] = -3745; 54 | tonetbl[37] = -4494; 55 | tonetbl[38] = 837; 56 | tonetbl[39] = 9912; 57 | tonetbl[40] = 18947; 58 | tonetbl[41] = 24161; 59 | tonetbl[42] = 23217; 60 | tonetbl[43] = 16119; 61 | tonetbl[44] = 5211; 62 | tonetbl[45] = -5718; 63 | tonetbl[46] = -12878; 64 | tonetbl[47] = -13924; 65 | tonetbl[48] = -8853; 66 | tonetbl[49] = 0; 67 | tonetbl[50] = 8853; 68 | tonetbl[51] = 13924; 69 | tonetbl[52] = 12878; 70 | tonetbl[53] = 5718; 71 | tonetbl[54] = -5211; 72 | tonetbl[55] = -16119; 73 | tonetbl[56] = -23217; 74 | tonetbl[57] = -24161; 75 | tonetbl[58] = -18947; 76 | tonetbl[59] = -9912; 77 | tonetbl[60] = -837; 78 | tonetbl[61] = 4494; 79 | tonetbl[62] = 3745; 80 | tonetbl[63] = -3081; 81 | tonetbl[64] = -13642; 82 | tonetbl[65] = -24149; 83 | tonetbl[66] = -30814; 84 | tonetbl[67] = -31295; 85 | tonetbl[68] = -25590; 86 | tonetbl[69] = -16037; 87 | tonetbl[70] = -6421; 88 | tonetbl[71] = -527; 89 | tonetbl[72] = -692; 90 | tonetbl[73] = -6918; 91 | tonetbl[74] = -16863; 92 | tonetbl[75] = -26741; 93 | tonetbl[76] = -32767; 94 | tonetbl[77] = -32601; 95 | tonetbl[78] = -26244; 96 | tonetbl[79] = -16037; 97 | tonetbl[80] = -5767; 98 | tonetbl[81] = 780; 99 | tonetbl[82] = 1260; 100 | tonetbl[83] = -4326; 101 | tonetbl[84] = -13642; 102 | tonetbl[85] = -22905; 103 | tonetbl[86] = -28330; 104 | tonetbl[87] = -27581; 105 | tonetbl[88] = -20660; 106 | tonetbl[89] = -9912; 107 | tonetbl[90] = 876; 108 | tonetbl[91] = 7914; 109 | tonetbl[92] = 8858; 110 | tonetbl[93] = 3704; 111 | tonetbl[94] = -5211; 112 | tonetbl[95] = -14105; 113 | tonetbl[96] = -19197; 114 | tonetbl[97] = -18151; 115 | tonetbl[98] = -10970; 116 | tonetbl[99] = 0; 117 | end 118 | 119 | //Assign the output to the value in the lookup table 120 | //pointed to by toneptr. 121 | assign dout = tonetbl[toneptr]; 122 | 123 | //Increment through the tone lookup table and wrap back 124 | //to zero when at the end. 125 | always @(posedge clk) begin 126 | if(en) begin 127 | if(toneptr == 7'd99) begin 128 | toneptr <= 7'd0; 129 | end 130 | else begin 131 | toneptr <= toneptr + 1'b1; 132 | end 133 | end 134 | end 135 | endmodule 136 | -------------------------------------------------------------------------------- /Block_FIR_Simulation/Block_FIR.srcs/sources_1/new/Block_FIR_Top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Block_FIR_Top( 4 | input clk, 5 | input [7:0]sw, 6 | output [7:0]JA 7 | ); 8 | 9 | wire clk_100MHz; 10 | wire clk_25MHz; 11 | wire en; 12 | 13 | wire signed [15:0]tonegen_out; 14 | 15 | //Data divider outputs. 16 | wire en_out; 17 | wire signed [15:0]d0_out; 18 | wire signed [15:0]d1_out; 19 | wire signed [15:0]d2_out; 20 | wire signed [15:0]d3_out; 21 | 22 | //FIR f1 outputs 23 | wire signed [15:0]f1_x0_out; 24 | wire signed [15:0]f1_x1_out; 25 | wire signed [15:0]f1_x2_out; 26 | wire signed [15:0]f1_x3_out; 27 | wire signed [15:0]f1_u0; 28 | wire signed [15:0]f1_u1; 29 | wire signed [15:0]f1_u2; 30 | wire signed [15:0]f1_u3; 31 | 32 | //FIR f2 outputs 33 | wire signed [15:0]f2_x0_out; 34 | wire signed [15:0]f2_x1_out; 35 | wire signed [15:0]f2_x2_out; 36 | wire signed [15:0]f2_x3_out; 37 | wire signed [15:0]f2_u0; 38 | wire signed [15:0]f2_u1; 39 | wire signed [15:0]f2_u2; 40 | wire signed [15:0]f2_u3; 41 | 42 | //FIR f3 outputs 43 | wire signed [15:0]f3_x0_out; 44 | wire signed [15:0]f3_x1_out; 45 | wire signed [15:0]f3_x2_out; 46 | wire signed [15:0]f3_x3_out; 47 | wire signed [15:0]f3_u0; 48 | wire signed [15:0]f3_u1; 49 | wire signed [15:0]f3_u2; 50 | wire signed [15:0]f3_u3; 51 | 52 | //FIR f4 outputs 53 | wire signed [15:0]f4_x0_out; 54 | wire signed [15:0]f4_x1_out; 55 | wire signed [15:0]f4_x2_out; 56 | wire signed [15:0]f4_x3_out; 57 | wire signed [15:0]f4_u0; 58 | wire signed [15:0]f4_u1; 59 | wire signed [15:0]f4_u2; 60 | wire signed [15:0]f4_u3; 61 | 62 | //Block filter outputs. 63 | wire signed [15:0]y0; 64 | wire signed [15:0]y1; 65 | wire signed [15:0]y2; 66 | wire signed [15:0]y3; 67 | 68 | wire [15:0]serial_dout; //Serialized output. 69 | wire [15:0]mout; //Selected output. 70 | 71 | assign en = 1'b1; 72 | 73 | clk_wiz_0 cw(.clk_in1(clk), .clk_out1(clk_100MHz), .clk_out2(clk_25MHz)); 74 | ToneGen tg(.clk(clk_100MHz), .en(en), .dout(tonegen_out)); 75 | Data_Div4 dd(.clk(clk_100MHz), .en(en), .din(tonegen_out), .en_out(en_out), 76 | .d0_out(d0_out), .d1_out(d1_out), .d2_out(d2_out), .d3_out(d3_out)); 77 | 78 | //Build 16-tap block FIR filter. 79 | Block_FIR #(.b0(16'd2320), .b1(16'd4143), .b2(16'd4592), .b3(16'd7278))f1(.clk(clk_25MHz), .en(en), 80 | .x0_in(d0_out), .x1_in(d1_out), .x2_in(d2_out), .x3_in(d3_out), 81 | .x0_out(f1_x0_out), .x1_out(f1_x1_out), .x2_out(f1_x2_out), .x3_out(f1_x3_out), 82 | .u0(f1_u0), .u1(f1_u1), .u2(f1_u2), .u3(f1_u3)); 83 | 84 | Block_FIR #(.b0(16'd8423), .b1(16'd10389), .b2(16'd11269), .b3(16'd12000))f2(.clk(clk_25MHz), .en(en), 85 | .x0_in(f1_x0_out), .x1_in(f1_x1_out), .x2_in(f1_x2_out), .x3_in(f1_x3_out), 86 | .x0_out(f2_x0_out), .x1_out(f2_x1_out), .x2_out(f2_x2_out), .x3_out(f2_x3_out), 87 | .u0(f2_u0), .u1(f2_u1), .u2(f2_u2), .u3(f2_u3)); 88 | 89 | Block_FIR #(.b0(16'd12000), .b1(16'd11269), .b2(16'd10389), .b3(16'd8423))f3(.clk(clk_25MHz), .en(en), 90 | .x0_in(f2_x0_out), .x1_in(f2_x1_out), .x2_in(f2_x2_out), .x3_in(f2_x3_out), 91 | .x0_out(f3_x0_out), .x1_out(f3_x1_out), .x2_out(f3_x2_out), .x3_out(f3_x3_out), 92 | .u0(f3_u0), .u1(f3_u1), .u2(f3_u2), .u3(f3_u3)); 93 | 94 | Block_FIR #(.b0(16'd7278), .b1(16'd4592), .b2(16'd4143), .b3(16'd2320))f4(.clk(clk_25MHz), .en(en), 95 | .x0_in(f3_x0_out), .x1_in(f3_x1_out), .x2_in(f3_x2_out), .x3_in(f3_x3_out), 96 | .x0_out(f4_x0_out), .x1_out(f4_x1_out), .x2_out(f4_x2_out), .x3_out(f4_x3_out), 97 | .u0(f4_u0), .u1(f4_u1), .u2(f4_u2), .u3(f4_u3)); 98 | 99 | //Add outputs together. 100 | assign y0 = f1_u0 + f2_u0 + f3_u0 + f4_u0; 101 | assign y1 = f1_u1 + f2_u1 + f3_u1 + f4_u1; 102 | assign y2 = f1_u2 + f2_u2 + f3_u2 + f4_u2; 103 | assign y3 = f1_u3 + f2_u3 + f3_u3 + f4_u3; 104 | 105 | //Serialize the output data. 106 | Data_Mult4 dm(.clk(clk_100MHz), .en(en), .d0_in(y0), .d1_in(y1), .d2_in(y2), .d3_in(y3), .dout(serial_dout)); 107 | 108 | //Choose filtered or unfiltered output based on sw0. 109 | assign mout = sw[0] ? serial_dout : tonegen_out; 110 | 111 | //Take only the upper 8 bits and make it unsigned. 112 | assign JA = mout[15:8] + 8'd128; 113 | endmodule 114 | --------------------------------------------------------------------------------