├── Modelsim ├── loadfname.dat ├── readme.txt ├── run.bat ├── tb.tcl └── wave.do ├── Opencores ├── LICENSE ├── README ├── fileList.txt ├── readme.txt ├── slib_clock_div.vhd ├── slib_counter.vhd ├── slib_edge_detect.vhd ├── slib_fifo.vhd ├── slib_fifo_cyclone2.vhd ├── slib_input_filter.vhd ├── slib_input_sync.vhd ├── slib_mv_filter.vhd ├── uart_16750.vhd ├── uart_baudgen.vhd ├── uart_interrupt.vhd ├── uart_receiver.vhd └── uart_transmitter.vhd ├── README.md ├── Software ├── Mon88 │ ├── MON88.ASM │ ├── MON88.COE │ ├── MON88.COM │ ├── MON88.SYM │ ├── loadfname.dat │ └── mon88.bat ├── Mon88_rom │ ├── MON88.ASM │ ├── MON88.COE │ ├── MON88.COM │ ├── MON88.SYM │ ├── loadfname.dat │ └── mon88.bat ├── asm │ ├── HELLO.LST │ ├── Makefile │ ├── asm.bat │ ├── hello.asm │ ├── hello.hex │ ├── hello2.asm │ └── hello2.hex └── bootloader │ ├── Bootstrap_rtl.vhd │ ├── jump0400.asm │ ├── jump0400.bat │ ├── ldintel.asm │ └── ldintel.bat ├── bin ├── bin2case.exe ├── bin2coe.exe ├── bin2hex.exe └── bin2mem.exe ├── copying.txt ├── cpu86_rtl ├── a_table.vhd ├── alu_rtl.vhd ├── biu_struct.vhd ├── biufsm_fsm.vhd ├── cpu86_struct.vhd ├── cpu86instr.vhd ├── cpu86pack.vhd ├── d_table.vhd ├── datapath_struct.vhd ├── dataregfile_rtl.vhd ├── divider_rtl_ser.vhd ├── formatter_struct.vhd ├── ipregister_rtl.vhd ├── m_table.vhd ├── multiplier_rtl.vhd ├── n_table.vhd ├── proc_rtl.vhd ├── r_table.vhd ├── readme.txt ├── regshiftmux_regshift.vhd └── segregfile_rtl.vhd ├── drigmorn1 ├── DRIGMORN1.ucf ├── Drigmorn1.gise ├── Drigmorn1.xise ├── Drigmorn1_tb_beh.prj ├── Drigmorn1_tb_isim_beh.exe ├── _xmsgs │ └── pn_parser.xmsgs ├── blk_mem_40K.mif ├── blk_mem_40K.ngc ├── coregen │ ├── MON88.COE │ ├── blk_mem_40K.asy │ ├── blk_mem_40K.gise │ ├── blk_mem_40K.ise │ ├── blk_mem_40K.mif │ ├── blk_mem_40K.ngc │ ├── blk_mem_40K.sym │ ├── blk_mem_40K.vhd │ ├── blk_mem_40K.vho │ ├── blk_mem_40K.xco │ ├── blk_mem_40K.xise │ ├── blk_mem_40K_flist.txt │ ├── blk_mem_40K_readme.txt │ ├── blk_mem_40K_xmdf.tcl │ ├── blk_mem_40Kx.vhd │ ├── coregen.cgp │ ├── coregen.log │ └── coregen.zip ├── cpu86_summary.html ├── drigmorn1_top_bitgen.xwbt ├── drigmorn1_top_guide.ncd ├── drigmorn1_top_summary.html ├── fuse.log ├── fuse.xmsgs ├── fuseRelaunch.cmd ├── iseconfig │ ├── Drigmorn1.projectmgr │ └── drigmorn1_top.xreport ├── isim.cmd ├── isim.log ├── readme.txt ├── testbench │ └── Drigmorn1_tb.vhd ├── top_drigmorn1 │ ├── Bootstrap_rtl.vhd │ ├── drigmorn1_top.vhd │ └── readme.txt └── xilinxsim.ini ├── ghdl ├── loadfname.dat ├── readme.txt ├── run.sh ├── run.sh~ └── work-obj93.cf ├── mx_sdram ├── NIOS_sdram_controller_0.v ├── assignment_defaults.qdf ├── clean.bat ├── mapping.txt ├── max1k_88_top.qsf ├── max1k_88_top.sdc ├── max1k_88_top.vhd ├── mon88.mif ├── pll12to40.qip ├── pll12to40.vhd ├── pll12to40_inst.vhd ├── ram.vhd └── top.qpf ├── p2_lcd_spi ├── Bootstrap_rtl.vhd ├── README.md ├── a_table.vhd ├── aaatop.vhd ├── alu_rtl.vhd ├── bios.s ├── bios2.s ├── biu_struct.vhd ├── biufsm_fsm.vhd ├── cpu86_struct.vhd ├── cpu86instr.vhd ├── cpu86pack.vhd ├── d_table.vhd ├── datapath_struct.vhd ├── dataregfile_rtl.vhd ├── divider_rtl_ser.vhd ├── drigmorn1_top.vhd ├── font_rom.vhd ├── formatter_struct.vhd ├── gen2.sh ├── ipcore_dir │ ├── MON88.COE │ ├── blk_mem_40K.asy │ ├── blk_mem_40K.mif │ ├── blk_mem_40K.ncf │ ├── blk_mem_40K.sym │ ├── blk_mem_40K.vhd │ ├── blk_mem_40K.vho │ ├── blk_mem_40K.xco │ ├── blk_mem_40K.xise │ ├── blk_mem_40K_flist.txt │ ├── blk_mem_40K_xmdf.tcl │ ├── clk32to40.asy │ ├── clk32to40.ncf │ ├── clk32to40.sym │ ├── clk32to40.ucf │ ├── clk32to40.v │ ├── clk32to40.veo │ ├── clk32to40.vhd │ ├── clk32to40.vho │ ├── clk32to40.xco │ ├── clk32to40.xdc │ ├── clk32to40.xise │ ├── clk32to40_flist.txt │ ├── clk32to40_xmdf.tcl │ ├── coregen.cgp │ ├── create_blk_mem_40K.tcl │ ├── create_clk32to40.tcl │ ├── edit_blk_mem_40K.tcl │ ├── gen_blk_mem_40K.tcl │ └── mon88_rom.coe ├── ipregister_rtl.vhd ├── lcdctl.vhd ├── m_table.vhd ├── multiplier_rtl.vhd ├── n_table.vhd ├── p2_lcd_spi.xise ├── papilio_duo.ucf ├── proc_rtl.vhd ├── put.s ├── r_table.vhd ├── regshiftmux_regshift.vhd ├── segregfile_rtl.vhd ├── slib_clock_div.vhd ├── slib_counter.vhd ├── slib_edge_detect.vhd ├── slib_fifo.vhd ├── slib_input_filter.vhd ├── slib_input_sync.vhd ├── slib_mv_filter.vhd ├── spi_master.vhd ├── uart_16750.vhd ├── uart_baudgen.vhd ├── uart_interrupt.vhd ├── uart_receiver.vhd ├── uart_top_struct.vhd ├── uart_transmitter.vhd ├── vga_sync.vhd ├── wingbutled.vhd └── winglcdsndbut.vhd ├── p2_vga_spi ├── BPS6001-Papilio-DUO-Computing-Shield-general.ucf ├── README.md ├── aaatop.vhd ├── drigmorn1_top.vhd ├── font_generator.vhd ├── font_rom.vhd ├── ipcore_dir │ ├── MON88.COE │ ├── blk_mem_40K.asy │ ├── blk_mem_40K.mif │ ├── blk_mem_40K.ncf │ ├── blk_mem_40K.sym │ ├── blk_mem_40K.vhd │ ├── blk_mem_40K.vho │ ├── blk_mem_40K.xco │ ├── blk_mem_40K.xise │ ├── blk_mem_40K_flist.txt │ ├── blk_mem_40K_xmdf.tcl │ ├── clk32to40.asy │ ├── clk32to40.ncf │ ├── clk32to40.sym │ ├── clk32to40.ucf │ ├── clk32to40.v │ ├── clk32to40.veo │ ├── clk32to40.vhd │ ├── clk32to40.vho │ ├── clk32to40.xco │ ├── clk32to40.xdc │ ├── clk32to40.xise │ ├── clk32to40_flist.txt │ ├── clk32to40_xmdf.tcl │ ├── coregen.cgp │ ├── create_blk_mem_40K.tcl │ ├── create_clk32to40.tcl │ ├── edit_blk_mem_40K.tcl │ ├── edit_clk32to40.tcl │ └── gen_blk_mem_40K.tcl ├── p2_vga_spi.xise ├── spi_master.vhd └── vga_sync.vhd ├── papilio1 ├── BPC3003_2.03+.ucf ├── DRIGMORN1.ucf ├── a.py ├── bbfifo_16x8.vhd ├── blk_mem_40K.mif ├── blk_mem_40K.ngc ├── blk_orig.mif ├── blk_remain.mif ├── coregen │ ├── blk_mem_40K.sym │ └── blk_mem_40K.vhd ├── dcm32to40_arwz.ucf ├── drigmorn1_top_envsettings.html ├── drigmorn1_top_guide.ncd ├── fuse.xmsgs ├── fuseRelaunch.cmd ├── ipcore_dir │ ├── _xmsgs │ │ └── cg.xmsgs │ ├── create_dcm32to40.tcl │ ├── dcm32to40.vhd │ ├── dcm32to40.xaw │ ├── dcm32to40_arwz.ucf │ ├── dcm32to40_flist.txt │ └── xaw2vhdl.log ├── iseconfig │ ├── Drigmorn1.projectmgr │ ├── drigmorn1_top.xreport │ ├── papilio1.projectmgr │ └── papilio1_top.xreport ├── kcuart_rx.vhd ├── kcuart_tx.vhd ├── papilio1.gise ├── papilio1.xise ├── papilio1_tb.vhd ├── papilio1_tb2.vhd ├── papilio1_top.vhd ├── papilio1_top_bitgen.xwbt ├── papilio1_top_guide.ncd ├── papilio1_top_summary.html ├── pepExtractor.prj ├── testbench │ └── Drigmorn1_tb.vhd ├── top_drigmorn1 │ ├── Bootstrap_rtl.vhd │ └── drigmorn1_top.vhd ├── uart_rx.vhd └── uart_tx.vhd ├── papilio1_0 ├── BPC3003_2.03+.ucf ├── DRIGMORN1.ucf ├── Drigmorn1.gise ├── blk_mem_40K.mif ├── blk_mem_40K.ngc ├── coregen │ ├── MON88.COE │ ├── blk_mem_40K.asy │ ├── blk_mem_40K.gise │ ├── blk_mem_40K.ise │ ├── blk_mem_40K.mif │ ├── blk_mem_40K.ngc │ ├── blk_mem_40K.sym │ ├── blk_mem_40K.vhd │ ├── blk_mem_40K.vho │ ├── blk_mem_40K.xco │ ├── blk_mem_40K.xise │ ├── blk_mem_40K_flist.txt │ ├── blk_mem_40K_readme.txt │ ├── blk_mem_40K_xmdf.tcl │ ├── blk_mem_40Kx.vhd │ ├── coregen.cgp │ ├── coregen.log │ └── coregen.zip ├── cpu86_summary.html ├── default.wcfg ├── fuse.xmsgs ├── fuseRelaunch.cmd ├── ipcore_dir │ ├── _xmsgs │ │ └── cg.xmsgs │ ├── create_dcm32to40.tcl │ ├── dcm32to40.vhd │ ├── dcm32to40.xaw │ ├── dcm32to40_arwz.ucf │ ├── dcm32to40_flist.txt │ └── xaw2vhdl.log ├── iseconfig │ ├── Drigmorn1.projectmgr │ └── drigmorn1_top.xreport ├── papilio1.gise ├── papilio1.xise ├── pepExtractor.prj ├── readme.txt ├── testbench │ └── papilio1_tb.vhd └── top_drigmorn1 │ ├── Bootstrap_rtl.vhd │ ├── papilio1_top.vhd │ └── readme.txt ├── papilio1_0_rom ├── BPC3003_2.03+.ucf ├── coregen │ ├── blk_mem_40K.sym │ └── blk_mem_40K.vhd ├── dcm32to40_arwz.ucf ├── ipcore_dir │ ├── dcm32to40.vhd │ └── dcm32to40.xaw ├── iseconfig │ ├── Drigmorn1.projectmgr │ ├── drigmorn1_top.xreport │ └── papilio1.projectmgr ├── papilio1_0_rom.xise ├── testbench │ └── papilio1_tb.vhd └── top_drigmorn1 │ ├── Bootstrap_rtl.vhd │ └── papilio1_top.vhd ├── papilio2 ├── LEDTop_guide.ncd ├── LEDTop_summary.html ├── MON88.COE ├── aaatop.vhd ├── blk_mem_40K.mif ├── drigmorn1_top.vhd ├── esram.vhd ├── fuse.xmsgs ├── fuseRelaunch.cmd ├── ipcore_dir │ ├── _xmsgs │ │ └── cg.xmsgs │ ├── blk_mem_40K.asy │ ├── blk_mem_40K.mif │ ├── blk_mem_40K.ncf │ ├── blk_mem_40K.ngc │ ├── blk_mem_40K.sym │ ├── blk_mem_40K.vhd │ ├── blk_mem_40K.vho │ ├── blk_mem_40K.xco │ ├── blk_mem_40K.xise │ ├── blk_mem_40K │ │ ├── blk_mem_gen_v7_3_readme.txt │ │ ├── doc │ │ │ ├── blk_mem_gen_v7_3_vinfo.html │ │ │ └── pg058-blk-mem-gen.pdf │ │ ├── example_design │ │ │ ├── blk_mem_40K_exdes.ucf │ │ │ ├── blk_mem_40K_exdes.vhd │ │ │ ├── blk_mem_40K_exdes.xdc │ │ │ └── blk_mem_40K_prod.vhd │ │ ├── implement │ │ │ ├── implement.bat │ │ │ ├── implement.sh │ │ │ ├── planAhead_ise.bat │ │ │ ├── planAhead_ise.sh │ │ │ ├── planAhead_ise.tcl │ │ │ ├── xst.prj │ │ │ └── xst.scr │ │ └── simulation │ │ │ ├── addr_gen.vhd │ │ │ ├── blk_mem_40K_synth.vhd │ │ │ ├── blk_mem_40K_tb.vhd │ │ │ ├── bmg_stim_gen.vhd │ │ │ ├── bmg_tb_pkg.vhd │ │ │ ├── checker.vhd │ │ │ ├── data_gen.vhd │ │ │ ├── functional │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.bat │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ ├── wave_mti.do │ │ │ └── wave_ncsim.sv │ │ │ ├── random.vhd │ │ │ └── timing │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.bat │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ ├── wave_mti.do │ │ │ └── wave_ncsim.sv │ ├── blk_mem_40K_flist.txt │ ├── blk_mem_40K_xmdf.tcl │ ├── clk32to40.asy │ ├── clk32to40.sym │ ├── clk32to40.ucf │ ├── clk32to40.v │ ├── clk32to40.veo │ ├── clk32to40.vhd │ ├── clk32to40.vho │ ├── clk32to40.xco │ ├── clk32to40.xdc │ ├── clk32to40.xise │ ├── clk32to40 │ │ ├── clk_wiz_v3_6_readme.txt │ │ ├── doc │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ ├── clk_wiz_v3_6_vinfo.html │ │ │ └── pg065_clk_wiz.pdf │ │ ├── example_design │ │ │ ├── clk32to40_exdes.ucf │ │ │ ├── clk32to40_exdes.v │ │ │ ├── clk32to40_exdes.vhd │ │ │ └── clk32to40_exdes.xdc │ │ ├── implement │ │ │ ├── implement.bat │ │ │ ├── implement.sh │ │ │ ├── planAhead_ise.bat │ │ │ ├── planAhead_ise.sh │ │ │ ├── planAhead_ise.tcl │ │ │ ├── planAhead_rdn.bat │ │ │ ├── planAhead_rdn.sh │ │ │ ├── planAhead_rdn.tcl │ │ │ ├── xst.prj │ │ │ └── xst.scr │ │ └── simulation │ │ │ ├── clk32to40_tb.v │ │ │ ├── clk32to40_tb.vhd │ │ │ ├── functional │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.bat │ │ │ ├── simulate_isim.sh │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ ├── wave.do │ │ │ └── wave.sv │ │ │ └── timing │ │ │ ├── clk32to40_tb.v │ │ │ ├── clk32to40_tb.vhd │ │ │ ├── sdf_cmd_file │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.sh │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ └── wave.do │ ├── clk32to40_flist.txt │ ├── clk32to40_xmdf.tcl │ ├── coregen.cgp │ ├── create_blk_mem_40K.tcl │ ├── create_clk32to40.tcl │ ├── edit_blk_mem_40K.tcl │ ├── gen_blk_mem_40K.tcl │ ├── summary.log │ └── tmp │ │ ├── _xmsgs │ │ ├── pn_parser.xmsgs │ │ └── xst.xmsgs │ │ ├── blk_mem_40K.lso │ │ ├── customization_gui.0.410740163369.out │ │ └── customization_gui.0.733166830024.out ├── iseconfig │ ├── LEDTop.xreport │ ├── aaatop.xreport │ └── template_duo.projectmgr ├── papilio1_tb.vhd ├── papilio2.xise └── papilio_duo.ucf ├── papilio2_drigmorn1 ├── aaatop.vhd ├── drigmorn1_top.vhd ├── ipcore_dir │ ├── blk_mem_40K.asy │ ├── blk_mem_40K.ncf │ ├── blk_mem_40K.sym │ ├── blk_mem_40K.xco │ ├── blk_mem_40K.xise │ ├── blk_mem_40K │ │ ├── blk_mem_gen_v7_3_readme.txt │ │ ├── doc │ │ │ ├── blk_mem_gen_v7_3_vinfo.html │ │ │ └── pg058-blk-mem-gen.pdf │ │ ├── example_design │ │ │ ├── blk_mem_40K_exdes.ucf │ │ │ ├── blk_mem_40K_exdes.vhd │ │ │ ├── blk_mem_40K_exdes.xdc │ │ │ └── blk_mem_40K_prod.vhd │ │ ├── implement │ │ │ ├── implement.bat │ │ │ ├── implement.sh │ │ │ ├── planAhead_ise.bat │ │ │ ├── planAhead_ise.sh │ │ │ ├── planAhead_ise.tcl │ │ │ ├── xst.prj │ │ │ └── xst.scr │ │ └── simulation │ │ │ ├── addr_gen.vhd │ │ │ ├── blk_mem_40K_synth.vhd │ │ │ ├── blk_mem_40K_tb.vhd │ │ │ ├── bmg_stim_gen.vhd │ │ │ ├── bmg_tb_pkg.vhd │ │ │ ├── checker.vhd │ │ │ ├── data_gen.vhd │ │ │ ├── functional │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.bat │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ ├── wave_mti.do │ │ │ └── wave_ncsim.sv │ │ │ ├── random.vhd │ │ │ └── timing │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.bat │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ ├── wave_mti.do │ │ │ └── wave_ncsim.sv │ ├── blk_mem_40K_flist.txt │ ├── blk_mem_40K_xmdf.tcl │ ├── clk32to40.asy │ ├── clk32to40.sym │ ├── clk32to40.ucf │ ├── clk32to40.v │ ├── clk32to40.veo │ ├── clk32to40.vhd │ ├── clk32to40.vho │ ├── clk32to40.xco │ ├── clk32to40.xdc │ ├── clk32to40.xise │ ├── clk32to40 │ │ ├── clk_wiz_v3_6_readme.txt │ │ ├── doc │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ ├── clk_wiz_v3_6_vinfo.html │ │ │ └── pg065_clk_wiz.pdf │ │ ├── example_design │ │ │ ├── clk32to40_exdes.ucf │ │ │ ├── clk32to40_exdes.v │ │ │ ├── clk32to40_exdes.vhd │ │ │ └── clk32to40_exdes.xdc │ │ ├── implement │ │ │ ├── implement.bat │ │ │ ├── implement.sh │ │ │ ├── planAhead_ise.bat │ │ │ ├── planAhead_ise.sh │ │ │ ├── planAhead_ise.tcl │ │ │ ├── planAhead_rdn.bat │ │ │ ├── planAhead_rdn.sh │ │ │ ├── planAhead_rdn.tcl │ │ │ ├── xst.prj │ │ │ └── xst.scr │ │ └── simulation │ │ │ ├── clk32to40_tb.v │ │ │ ├── clk32to40_tb.vhd │ │ │ ├── functional │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.bat │ │ │ ├── simulate_isim.sh │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ ├── wave.do │ │ │ └── wave.sv │ │ │ └── timing │ │ │ ├── clk32to40_tb.v │ │ │ ├── clk32to40_tb.vhd │ │ │ ├── sdf_cmd_file │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.sh │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ └── wave.do │ ├── clk32to40_flist.txt │ ├── clk32to40_xmdf.tcl │ ├── coregen.cgp │ ├── create_blk_mem_40K.tcl │ ├── create_clk32to40.tcl │ ├── edit_blk_mem_40K.tcl │ └── summary.log ├── iseconfig │ ├── LEDTop.xreport │ ├── aaatop.xreport │ ├── papilio2.projectmgr │ └── template_duo.projectmgr ├── papilio2_drigmorn1.xise └── papilio_duo.ucf ├── papilio2_lcd ├── Bootstrap_rtl.vhd ├── README.md ├── a_table.vhd ├── aaatop.vhd ├── alu_rtl.vhd ├── biu_struct.vhd ├── biufsm_fsm.vhd ├── cpu86_struct.vhd ├── cpu86instr.vhd ├── cpu86pack.vhd ├── d_table.vhd ├── datapath_struct.vhd ├── dataregfile_rtl.vhd ├── divider_rtl_ser.vhd ├── drigmorn1_top.vhd ├── font_rom.vhd ├── formatter_struct.vhd ├── ipcore_dir │ ├── MON88.COE │ ├── blk_mem_40K.asy │ ├── blk_mem_40K.mif │ ├── blk_mem_40K.ncf │ ├── blk_mem_40K.sym │ ├── blk_mem_40K.vhd │ ├── blk_mem_40K.vho │ ├── blk_mem_40K.xco │ ├── blk_mem_40K.xise │ ├── blk_mem_40K_flist.txt │ ├── blk_mem_40K_xmdf.tcl │ ├── clk32to40.asy │ ├── clk32to40.ncf │ ├── clk32to40.sym │ ├── clk32to40.ucf │ ├── clk32to40.v │ ├── clk32to40.veo │ ├── clk32to40.vhd │ ├── clk32to40.vho │ ├── clk32to40.xco │ ├── clk32to40.xdc │ ├── clk32to40.xise │ ├── clk32to40_flist.txt │ ├── clk32to40_xmdf.tcl │ ├── coregen.cgp │ ├── create_blk_mem_40K.tcl │ ├── create_clk32to40.tcl │ └── edit_blk_mem_40K.tcl ├── ipregister_rtl.vhd ├── lcdctl.vhd ├── m_table.vhd ├── multiplier_rtl.vhd ├── n_table.vhd ├── p2_8088_vga.jpg ├── papilio2_lcd.xise ├── papilio_duo.ucf ├── proc_rtl.vhd ├── r_table.vhd ├── regshiftmux_regshift.vhd ├── segregfile_rtl.vhd ├── slib_clock_div.vhd ├── slib_counter.vhd ├── slib_edge_detect.vhd ├── slib_fifo.vhd ├── slib_input_filter.vhd ├── slib_input_sync.vhd ├── slib_mv_filter.vhd ├── uart_16750.vhd ├── uart_baudgen.vhd ├── uart_interrupt.vhd ├── uart_receiver.vhd ├── uart_top_struct.vhd ├── uart_transmitter.vhd ├── vga_sync.vhd └── winglcdsndbut.vhd ├── papilio2_vga ├── BPS6001-Papilio-DUO-Computing-Shield-general.ucf ├── aaatop.vhd ├── drigmorn1_top.vhd ├── font_generator.vhd ├── font_rom.vhd ├── ipcore_dir │ ├── MON88.COE │ ├── blk_mem_40K.asy │ ├── blk_mem_40K.mif │ ├── blk_mem_40K.ncf │ ├── blk_mem_40K.sym │ ├── blk_mem_40K.vhd │ ├── blk_mem_40K.vho │ ├── blk_mem_40K.xco │ ├── blk_mem_40K.xise │ ├── blk_mem_40K_flist.txt │ ├── blk_mem_40K_xmdf.tcl │ ├── clk32to40.asy │ ├── clk32to40.ncf │ ├── clk32to40.sym │ ├── clk32to40.ucf │ ├── clk32to40.v │ ├── clk32to40.veo │ ├── clk32to40.vhd │ ├── clk32to40.vho │ ├── clk32to40.xco │ ├── clk32to40.xdc │ ├── clk32to40.xise │ ├── clk32to40_flist.txt │ ├── clk32to40_xmdf.tcl │ ├── coregen.cgp │ ├── create_blk_mem_40K.tcl │ ├── create_clk32to40.tcl │ ├── edit_blk_mem_40K.tcl │ └── edit_clk32to40.tcl ├── papilio2_vga.xise └── vga_sync.vhd ├── readme.txt ├── testbench ├── cpu86_top_tb_struct.vhd ├── sram.vhd ├── tester_behaviour.vhd ├── uartrx.vhd ├── uarttx.vhd └── utils.vhd └── top_rtl ├── Bootstrap_rtl.vhd ├── cpu86_top_struct.vhd ├── readme.txt └── uart_top_struct.vhd /Modelsim/readme.txt: -------------------------------------------------------------------------------- 1 | Quick run: 2 | 3 | 1) Open a DOSBox/Cygwin shell 4 | 2) Navigate to the web_cpu88/Modelsim directory. 5 | 3) Execute run.bat 6 | 7 | Modelsim is executed in command line mode. The simulation output should look something 8 | like this: 9 | 10 | # Initializing SRAM with zero ... 11 | # Loading SRAM from file loadfname.dat ... 12 | # RD UART : MON88 8088/8086 Monitor ver 0.12 13 | # RD UART : Copyright WWW.HT-LAB.COM 2005-2008 14 | # RD UART : All rights reserved. 15 | # RD UART : 16 | # RD UART : Cmd>R 17 | # RD UART : AX=0000 BX=0001 CX=0002 DX=0003 SP=0100 BP=0005 SI=0006 DI=0007 18 | # RD UART : DS=0380 ES=0380 SS=0380 CS=0380 IP=0100 ODIT-SZAPC=0000-00100 19 | # RD UART : 0380:0100 0000 ADD [BX+SI], AL 20 | # RD UART : Cmd>DM 0100-0124 21 | # RD UART : 0380:0100 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 22 | # RD UART : 0380:0110 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 23 | # RD UART : 0380:0120 00 00 00 00 .... 24 | 25 | Note that it might take considerable time to show this output if you have a slow PC and/or 26 | using an OEM version of Modelsim (for example Xilinx' Modelsim XE). 27 | 28 | For Modelsim SE6.5a users, if you get a SIGSEGV error message then try to run without vopt (-novopt) 29 | 30 | # ** Fatal: (SIGSEGV) Bad handle or reference. 31 | # Time: 0 ns Iteration: 0 Process: /cpu86_top_tb/u_12/memory File: ../testbench/sram.vhd 32 | # FATAL ERROR while loading design 33 | # Error loading design -------------------------------------------------------------------------------- /Modelsim/tb.tcl: -------------------------------------------------------------------------------- 1 | # For Modelsim PE6.5a use 2 | #vsim -novopt work.cpu86_top_tb 3 | 4 | #For Modelsim SE6.5a use 5 | vsim -voptargs="+acc+sram" work.cpu86_top_tb 6 | 7 | 8 | set StdArithNoWarnings 1 9 | set NumericStdNoWarnings 1 10 | run 200 ms 11 | quit -f 12 | -------------------------------------------------------------------------------- /Opencores/README: -------------------------------------------------------------------------------- 1 | ========================================== 2 | UART16750 (C) 2008-2009 Sebastian Witt 3 | ========================================== 4 | 5 | Description: 6 | 7 | Implements a synthesizable 16550/16750 UART core. 8 | 9 | Features: 10 | 11 | - Full synchronous design 12 | - Pin compatible to 16550/16750 13 | - Register compatible to 16550/16750 14 | - Baudrate generator with clock enable 15 | - Supports 5/6/7/8 bit characters 16 | - None/Even/Odd parity bit generation and detection 17 | - Supports 1/1.5/2 stop bit generation 18 | - 16/64 byte FIFO mode 19 | - Receiver FIFO trigger levels 1/4/8/14/16/32/56 20 | - Control lines RTS/CTS/DTR/DSR/DCD/RI/OUT1/OUT2 21 | - Automatic flow control with RTS/CTS 22 | - All interrupts sources/modes 23 | 24 | Todo: 25 | 26 | - Variable character time-out counter 27 | - DMA control 28 | 29 | Tests: 30 | 31 | A script is used to create a extensive functional stimuli file which 32 | can be used for simulation or real-hardware testing. 33 | The core was synthesized on a Altera Cyclone II, connected to x86 34 | standard hardware and than tested with standard OS drivers from: 35 | 36 | - Linux 2.2/2.4/2.6 37 | - Windows 2000/XP/Vista 38 | - *BSD 39 | - *DOS 40 | 41 | Files: 42 | 43 | uart_16750.vhd: Top level file 44 | uart_receiver.vhd: UART receiver part 45 | uart_transmitter.vhd: UART transmitter part 46 | uart_baudgen.vhd: Baudrate generator 47 | uart_interrupt.vhd: Interrupt register and generation 48 | 49 | The FIFO implementation should be replaced for the specific device. 50 | In slib_fifo.vhd is a generic FIFO (for simulation), slib_fifo_cyclone2.vhd 51 | can be used for a Altera Cyclone II. 52 | 53 | Rules for FIFO generation with vendor tools: 54 | 55 | The top-word is always available at the output (no read-request/delay). 56 | 57 | Resource usage: 58 | 59 | * Altera Cyclone II 60 | o 440 LE 61 | o 1216 memory bits 62 | o Frequency: 130 MHz 63 | 64 | * Xilinx Spartan 3E 65 | o 378 Slices 66 | o 1 RAMB 67 | o Frequency: 100 MHz 68 | 69 | Simulation: 70 | 71 | It's possible to simulate and test the design with GHDL [1]. 72 | A Makefile is available for starting the simulation. The testbench 73 | creates a log file (uart_log.txt). 74 | 75 | [1] http://ghdl.free.fr 76 | -------------------------------------------------------------------------------- /Opencores/fileList.txt: -------------------------------------------------------------------------------- 1 | Synthesis filelist 2 | uart_baudgen.vhd 3 | slib_clock_div.vhd 4 | slib_edge_detect.vhd 5 | slib_input_filter.vhd 6 | uart_interrupt.vhd 7 | slib_input_sync.vhd 8 | slib_counter.vhd 9 | slib_mv_filter.vhd 10 | uart_receiver.vhd 11 | slib_fifo.vhd 12 | uart_transmitter.vhd 13 | uart_16750.vhd 14 | uart_top_struct.vhd 15 | -------------------------------------------------------------------------------- /Opencores/readme.txt: -------------------------------------------------------------------------------- 1 | This directory contains only the synthesizable part of the OpenCores 16750 UART. 2 | 3 | The full design can be downloaded from http://www.opencores.org 4 | 5 | Many thanks to Sebastian Witt for making this core freely available. 6 | 7 | The core seems to synthesize with the default simulation FIFO, you might want to investigate 8 | this to make sure you are meeting timing. 9 | -------------------------------------------------------------------------------- /Opencores/slib_clock_div.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Clock divider (clock enable generator) 3 | -- 4 | -- Author: Sebastian Witt 5 | -- Date: 27.01.2008 6 | -- Version: 1.1 7 | -- 8 | -- This code is free software; you can redistribute it and/or 9 | -- modify it under the terms of the GNU Lesser General Public 10 | -- License as published by the Free Software Foundation; either 11 | -- version 2.1 of the License, or (at your option) any later version. 12 | -- 13 | -- This code is distributed in the hope that it will be useful, 14 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 | -- Lesser General Public License for more details. 17 | -- 18 | -- You should have received a copy of the GNU Lesser General Public 19 | -- License along with this library; if not, write to the 20 | -- Free Software Foundation, Inc., 59 Temple Place, Suite 330, 21 | -- Boston, MA 02111-1307 USA 22 | -- 23 | 24 | LIBRARY IEEE; 25 | USE IEEE.std_logic_1164.all; 26 | USE IEEE.numeric_std.all; 27 | 28 | 29 | entity slib_clock_div is 30 | generic ( 31 | RATIO : integer := 4 -- Clock divider ratio 32 | ); 33 | port ( 34 | CLK : in std_logic; -- Clock 35 | RST : in std_logic; -- Reset 36 | CE : in std_logic; -- Clock enable input 37 | Q : out std_logic -- New clock enable output 38 | ); 39 | end slib_clock_div; 40 | 41 | architecture rtl of slib_clock_div is 42 | -- Signals 43 | signal iQ : std_logic; -- Internal Q 44 | signal iCounter : integer range 0 to RATIO-1; -- Counter 45 | 46 | begin 47 | -- Main process 48 | CD_PROC: process (RST, CLK) 49 | begin 50 | if (RST = '1') then 51 | iCounter <= 0; 52 | iQ <= '0'; 53 | elsif (CLK'event and CLK='1') then 54 | iQ <= '0'; 55 | if (CE = '1') then 56 | if (iCounter = (RATIO-1)) then 57 | iQ <= '1'; 58 | iCounter <= 0; 59 | else 60 | iCounter <= iCounter + 1; 61 | end if; 62 | end if; 63 | end if; 64 | end process; 65 | 66 | -- Output signals 67 | Q <= iQ; 68 | 69 | end rtl; 70 | 71 | -------------------------------------------------------------------------------- /Opencores/slib_edge_detect.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Signal edge detect 3 | -- 4 | -- Author: Sebastian Witt 5 | -- Data: 27.01.2008 6 | -- Version: 1.1 7 | -- 8 | -- This code is free software; you can redistribute it and/or 9 | -- modify it under the terms of the GNU Lesser General Public 10 | -- License as published by the Free Software Foundation; either 11 | -- version 2.1 of the License, or (at your option) any later version. 12 | -- 13 | -- This code is distributed in the hope that it will be useful, 14 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 | -- Lesser General Public License for more details. 17 | -- 18 | -- You should have received a copy of the GNU Lesser General Public 19 | -- License along with this library; if not, write to the 20 | -- Free Software Foundation, Inc., 59 Temple Place, Suite 330, 21 | -- Boston, MA 02111-1307 USA 22 | -- 23 | 24 | LIBRARY IEEE; 25 | USE IEEE.std_logic_1164.all; 26 | USE IEEE.numeric_std.all; 27 | 28 | entity slib_edge_detect is 29 | port ( 30 | CLK : in std_logic; -- Clock 31 | RST : in std_logic; -- Reset 32 | D : in std_logic; -- Signal input 33 | RE : out std_logic; -- Rising edge detected 34 | FE : out std_logic -- Falling edge detected 35 | ); 36 | end slib_edge_detect; 37 | 38 | architecture rtl of slib_edge_detect is 39 | signal iDd : std_logic; -- D register 40 | begin 41 | -- Store D 42 | ED_D: process (RST, CLK) 43 | begin 44 | if (RST = '1') then 45 | iDd <= '0'; 46 | elsif (CLK'event and CLK='1') then 47 | iDd <= D; 48 | end if; 49 | end process; 50 | 51 | -- Output ports 52 | RE <= '1' when iDd = '0' and D = '1' else '0'; 53 | FE <= '1' when iDd = '1' and D = '0' else '0'; 54 | 55 | end rtl; 56 | 57 | 58 | -------------------------------------------------------------------------------- /Opencores/slib_input_filter.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Input filter 3 | -- 4 | -- Author: Sebastian Witt 5 | -- Data: 06.03.2008 6 | -- Version: 1.0 7 | -- 8 | -- This code is free software; you can redistribute it and/or 9 | -- modify it under the terms of the GNU Lesser General Public 10 | -- License as published by the Free Software Foundation; either 11 | -- version 2.1 of the License, or (at your option) any later version. 12 | -- 13 | -- This code is distributed in the hope that it will be useful, 14 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 | -- Lesser General Public License for more details. 17 | -- 18 | -- You should have received a copy of the GNU Lesser General Public 19 | -- License along with this library; if not, write to the 20 | -- Free Software Foundation, Inc., 59 Temple Place, Suite 330, 21 | -- Boston, MA 02111-1307 USA 22 | -- 23 | 24 | LIBRARY IEEE; 25 | USE IEEE.std_logic_1164.all; 26 | USE IEEE.numeric_std.all; 27 | 28 | entity slib_input_filter is 29 | generic ( 30 | SIZE : natural := 4 -- Filter counter size 31 | ); 32 | port ( 33 | CLK : in std_logic; -- Clock 34 | RST : in std_logic; -- Reset 35 | CE : in std_logic; -- Clock enable 36 | D : in std_logic; -- Signal input 37 | Q : out std_logic -- Signal output 38 | ); 39 | end slib_input_filter; 40 | 41 | architecture rtl of slib_input_filter is 42 | signal iCount : integer range 0 to SIZE; 43 | begin 44 | IF_D: process (RST, CLK) 45 | begin 46 | if (RST = '1') then 47 | iCount <= 0; 48 | Q <= '0'; 49 | elsif (CLK'event and CLK='1') then 50 | -- Input counter 51 | if (CE = '1' ) then 52 | if (D = '1' and iCount /= SIZE) then 53 | iCount <= iCount + 1; 54 | elsif (D = '0' and iCount /= 0) then 55 | iCount <= iCount - 1; 56 | end if; 57 | end if; 58 | 59 | -- Output 60 | if (iCount = SIZE) then 61 | Q <= '1'; 62 | elsif (iCount = 0) then 63 | Q <= '0'; 64 | end if; 65 | end if; 66 | end process; 67 | 68 | end rtl; 69 | 70 | -------------------------------------------------------------------------------- /Opencores/slib_input_sync.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Input synchronization 3 | -- 4 | -- Author: Sebastian Witt 5 | -- Data: 27.01.2008 6 | -- Version: 1.0 7 | -- 8 | -- This code is free software; you can redistribute it and/or 9 | -- modify it under the terms of the GNU Lesser General Public 10 | -- License as published by the Free Software Foundation; either 11 | -- version 2.1 of the License, or (at your option) any later version. 12 | -- 13 | -- This code is distributed in the hope that it will be useful, 14 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 | -- Lesser General Public License for more details. 17 | -- 18 | -- You should have received a copy of the GNU Lesser General Public 19 | -- License along with this library; if not, write to the 20 | -- Free Software Foundation, Inc., 59 Temple Place, Suite 330, 21 | -- Boston, MA 02111-1307 USA 22 | -- 23 | 24 | LIBRARY IEEE; 25 | USE IEEE.std_logic_1164.all; 26 | USE IEEE.numeric_std.all; 27 | 28 | entity slib_input_sync is 29 | port ( 30 | CLK : in std_logic; -- Clock 31 | RST : in std_logic; -- Reset 32 | D : in std_logic; -- Signal input 33 | Q : out std_logic -- Signal output 34 | ); 35 | end slib_input_sync; 36 | 37 | architecture rtl of slib_input_sync is 38 | signal iD : std_logic_vector(1 downto 0); 39 | begin 40 | IS_D: process (RST, CLK) 41 | begin 42 | if (RST = '1') then 43 | iD <= (others => '0'); 44 | elsif (CLK'event and CLK='1') then 45 | iD(0) <= D; 46 | iD(1) <= iD(0); 47 | end if; 48 | end process; 49 | 50 | -- Output ports 51 | Q <= iD(1); 52 | 53 | end rtl; 54 | 55 | -------------------------------------------------------------------------------- /Software/Mon88/MON88.COM: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/Software/Mon88/MON88.COM -------------------------------------------------------------------------------- /Software/Mon88/MON88.SYM: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/Software/Mon88/MON88.SYM -------------------------------------------------------------------------------- /Software/Mon88/mon88.bat: -------------------------------------------------------------------------------- 1 | A86.com +L1 +P0 +W0 +T0 +G2 +S mon88.asm mon88.bin 2 | ..\..\bin\bin2mem.exe mon88.bin loadfname.dat 0000:0000 3 | ..\..\bin\bin2coe.exe mon88.bin mon88.coe 4 | ..\..\bin\bin2hex.exe mon88.bin mon88.hex -s 0000 -o 0000 -e 0400 5 | copy loadfname.dat ..\..\Modelsim 6 | copy mon88.coe ..\..\drigmorn1\coregen 7 | pause 8 | -------------------------------------------------------------------------------- /Software/Mon88_rom/MON88.COM: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/Software/Mon88_rom/MON88.COM -------------------------------------------------------------------------------- /Software/Mon88_rom/MON88.SYM: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/Software/Mon88_rom/MON88.SYM -------------------------------------------------------------------------------- /Software/Mon88_rom/mon88.bat: -------------------------------------------------------------------------------- 1 | A86.com +L1 +P0 +W0 +T0 +G2 +S mon88.asm mon88.bin 2 | ..\..\bin\bin2mem.exe mon88.bin loadfname.dat 0000:0000 3 | ..\..\bin\bin2coe.exe mon88.bin mon88.coe 4 | ..\..\bin\bin2hex.exe mon88.bin mon88.hex -s 0000 -o 0000 -e 0400 5 | copy loadfname.dat ..\..\Modelsim 6 | copy mon88.coe ..\..\drigmorn1\coregen 7 | pause 8 | -------------------------------------------------------------------------------- /Software/asm/HELLO.LST: -------------------------------------------------------------------------------- 1 | 1 ;----------------------------------------------------------------------- 2 | 2 ; Hello World using int21 display string routine 3 | 3 ; 4 | 4 ; version 0.1 5 | 5 ;----------------------------------------------------------------------- 6 | 6 = : 000A LF EQU 0Ah 7 | 7 = : 000D CR EQU 0Dh 8 | 8 9 | 9 org 0100h ; result in .com start IP=0100 10 | 10 11 | 11 ; MOV AX,CS 12 | 12 ; MOV DS,AX 13 | 13 14 | 14 0100 BA 0D 01 MOV DX,OFFSET WELCOME_MESS ; OFFSET -> DX 15 | 15 0103 B8 00 09 MOV AX,0900h ; Call print string bios 16 | service 17 | 16 0106 CD 21 INT 21h 18 | 17 19 | 18 20 | 19 0108 B8 00 4C mov ax,04C00h ; exit with code 21 | 0 22 | 20 010B CD 21 int 021h ; back to bootloader/monitor 23 | 21 24 | 22 010D 0D 0A 2A 2A 2A 20 WELCOME_MESS DB CR,LF,"*** Hello World ***",CR,LF,0 25 | -------------------------------------------------------------------------------- /Software/asm/Makefile: -------------------------------------------------------------------------------- 1 | SREC_CAT:=srec_cat 2 | 3 | all: 4 | nasm hello2.asm 5 | # ndisasm.exe -b 16 hello2 -o 0x100 6 | # hello2 -binary -execution-start-address 0x380 -offset 0x100 -o hello2.hex -intel 7 | # $(SREC_CAT) hello2 -binary -offset 0x100 -o hello2.hex -intel 8 | $(SREC_CAT) hello2 -binary -offset 0x100 -o hello2.hex -Intel -Address_Length 3 --Execution_Start_Address 0x100 --disable footer 9 | @echo "Now you just have to paste the following lines in MON88 console : (notice it begins with 'l' intel hex load command)" 10 | @echo -n "l" ; cat hello2.hex 11 | 12 | # nasm hello.asm 13 | # ndisasm.exe -b 16 hello -o 0x100 14 | ## $(SREC_CAT) hello2 -binary -execution-start-address 0x380 -offset 0x100 -o hello2.hex -intel 15 | # $(SREC_CAT) hello -binary -offset 0x100 -o hello.hex2 -intel −−address−length=3 && cat hello.hex2 16 | -------------------------------------------------------------------------------- /Software/asm/asm.bat: -------------------------------------------------------------------------------- 1 | A86.com +P0 %1.asm %1.bin 2 | bin2hex.exe %1.bin %1.hex -s 0380 -o 0100 3 | -------------------------------------------------------------------------------- /Software/asm/hello.asm: -------------------------------------------------------------------------------- 1 | ;------------------------------------------------------------------------------- 2 | ; Hello World using int21 display string routine 3 | ;------------------------------------------------------------------------------- 4 | ORG 0100h ; result in .com start IP=0100 5 | 6 | MOV DX,OFFSET MESS ; String offset in DX, Segment in DS 7 | MOV AX,0900h ; Call print string bios service 8 | INT 21h ; in mon88 9 | 10 | ;waitk: MOV AH,01 ; Get char 11 | ; INT 21h 12 | ; CMP AL,'q' ; 'q' pressed? 13 | ; JNE waitk ; No, then wait 14 | 15 | MOV AX,04C00h ; exit with code 0 (in AL) 16 | INT 021h ; back to bootloader/monitor 17 | 18 | MESS DB 0Ah,0Dh,"*** Hello World ***",0 19 | DB 0Ah,0Dh,"Press q to return to MON88......",0 20 | -------------------------------------------------------------------------------- /Software/asm/hello.hex: -------------------------------------------------------------------------------- 1 | :02000002038079 2 | :20010000BA0D01B80009CD21B8004CCD210A0D2A2A2A2048656C6C6F20576F726C64202A5B 3 | :200120002A2A000A0D5072657373207120746F2072657475726E20746F204D4F4E38382E48 4 | :060140002E2E2E2E2E00D3 5 | :00000001FF 6 | -------------------------------------------------------------------------------- /Software/asm/hello2.asm: -------------------------------------------------------------------------------- 1 | ;------------------------------------------------------------------------------- 2 | ; Hello World using int21 display string routine 3 | ;------------------------------------------------------------------------------- 4 | ORG 0100h ; result in .com start IP=0100 5 | 6 | MOV DX,HELLO ; String offset in DX, Segment in DS 7 | call print 8 | 9 | mov cx,ds 10 | mov es,cx 11 | 12 | mov si,STR1 13 | mov di,DIFF2 14 | call strcmp 15 | 16 | mov si,STR1 17 | mov di,SAME2 18 | call strcmp 19 | 20 | exit: 21 | MOV AX,04C00h ; exit with code 0 (in AL) 22 | INT 021h ; back to bootloader/monitor 23 | 24 | strcmp: 25 | mov cx,6 26 | rep cmpsb 27 | 28 | jnz is_different 29 | 30 | is_same: 31 | MOV DX,SAME ; String offset in DX, Segment in DS 32 | call print 33 | jmp strcmp_exit 34 | is_different: 35 | MOV DX,DIFF ; String offset in DX, Segment in DS 36 | call print 37 | strcmp_exit: 38 | 39 | ret 40 | 41 | print: 42 | MOV AX,0900h ; Call print string bios service 43 | INT 21h ; in mon88 44 | ret 45 | 46 | STR1 db "COUCOU" 47 | DIFF2 db "AOUCOU" 48 | SAME2 db "COUCOU" 49 | 50 | HELLO DB 0Ah,0Dh,"*** Hello ***",0 51 | 52 | SAME DB 0Ah,0Dh,"*** SAME ***",0 53 | DIFF DB 0Ah,0Dh,"*** DIFFERENT ***",0 54 | -------------------------------------------------------------------------------- /Software/asm/hello2.hex: -------------------------------------------------------------------------------- 1 | :020000020000FC 2 | :20010000BA4F01E831008CD98EC1BE3D01BF4301E80E00BE3D01BF4901E80500B8004CCD50 3 | :2001200021B90600F3A67508BA5F01E80900EB06BA6E01E80100C3B80009CD21C3434F559F 4 | :20014000434F55414F55434F55434F55434F550A0D2A2A2A2048656C6C6F202A2A2A000ACD 5 | :200160000D2A2A2A2053414D45202A2A2A000A0D2A2A2A20444946464552454E54202A2A50 6 | :020180002A0053 7 | :0400000300000100F8 8 | -------------------------------------------------------------------------------- /Software/bootloader/jump0400.asm: -------------------------------------------------------------------------------- 1 | ;*********************************************************************************** 2 | ; File name : jump0400.asm 3 | ; 4 | ; Purpose : 5 | ; 6 | ; Authors : 7 | ; 8 | ; Reference : 9 | ; 10 | ; Note : 11 | ; ----------------------------------------------------------------------------------- 12 | ; Version Author Date Changes 13 | ; 0.1 Hans Tiggeler 10 October 04 First Version 14 | ;************************************************************************************ 15 | 16 | _TEXT SEGMENT BYTE PUBLIC 'CODE' 17 | 18 | ASSUME cs:_TEXT, SS:NOTHING, DS:NOTHING, ES:NOTHING 19 | 20 | ;------------------------------------------------------------------------------------ 21 | ; Reset Vector 22 | ;------------------------------------------------------------------------------------ 23 | ORG 000F0h ; Top of 256 Byte ROM address space 24 | 25 | COLD: DB 0EAh ; Jump to beginning of MON88 26 | DW 0400h ; located in the bottom 14K 27 | DW 0000h ; at 0000:0400 28 | 29 | _TEXT ENDS 30 | END COLD 31 | -------------------------------------------------------------------------------- /Software/bootloader/jump0400.bat: -------------------------------------------------------------------------------- 1 | @echo Create Bootstrap_rtl.vhd from jump to 0000:0400 file 2 | A86.com +L1 +P0 +W0 +T0 +G2 +S jump0400.asm jump0400.bin 3 | ..\..\bin\bin2case.exe jump0400.bin Bootstrap_rtl.vhd 8 4 | -------------------------------------------------------------------------------- /Software/bootloader/ldintel.bat: -------------------------------------------------------------------------------- 1 | @echo Create Bootstrap_rtl.vhd from Intel Bootloader file 2 | A86.com +L1 +P0 +W0 +T0 +G2 +S ldintel.asm ldintel.bin 3 | ..\..\bin\bin2case.exe ldintel.bin Bootstrap_intel_rtl.vhd 8 4 | -------------------------------------------------------------------------------- /bin/bin2case.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/bin/bin2case.exe -------------------------------------------------------------------------------- /bin/bin2coe.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/bin/bin2coe.exe -------------------------------------------------------------------------------- /bin/bin2hex.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/bin/bin2hex.exe -------------------------------------------------------------------------------- /bin/bin2mem.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/bin/bin2mem.exe -------------------------------------------------------------------------------- /cpu86_rtl/readme.txt: -------------------------------------------------------------------------------- 1 | This directory contains the synthesizable CPU86 (8088) processor VHDL source files. 2 | 3 | File dependency order: 4 | 5 | cpu86pack.vhd 6 | cpu86instr.vhd 7 | biufsm_fsm.vhd 8 | a_table.vhd 9 | d_table.vhd 10 | n_table.vhd 11 | r_table.vhd 12 | m_table.vhd 13 | formatter_struct.vhd 14 | regshiftmux_regshift.vhd 15 | biu_struct.vhd 16 | dataregfile_rtl.vhd 17 | segregfile_rtl.vhd 18 | divider_rtl_ser.vhd 19 | multiplier_rtl.vhd 20 | alu_rtl.vhd 21 | ipregister_rtl.vhd 22 | datapath_struct.vhd 23 | proc_rtl.vhd 24 | cpu86_struct.vhd 25 | 26 | -------------------------------------------------------------------------------- /drigmorn1/Drigmorn1.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /drigmorn1/Drigmorn1_tb_beh.prj: -------------------------------------------------------------------------------- 1 | vhdl work "../Opencores/slib_mv_filter.vhd" 2 | vhdl work "../Opencores/slib_counter.vhd" 3 | vhdl work "../cpu86_rtl/r_table.vhd" 4 | vhdl work "../cpu86_rtl/n_table.vhd" 5 | vhdl work "../cpu86_rtl/m_table.vhd" 6 | vhdl work "../cpu86_rtl/multiplier_rtl.vhd" 7 | vhdl work "../cpu86_rtl/d_table.vhd" 8 | vhdl work "../cpu86_rtl/divider_rtl_ser.vhd" 9 | vhdl work "../cpu86_rtl/cpu86pack.vhd" 10 | vhdl work "../cpu86_rtl/cpu86instr.vhd" 11 | vhdl work "../cpu86_rtl/a_table.vhd" 12 | vhdl work "../Opencores/uart_transmitter.vhd" 13 | vhdl work "../Opencores/uart_receiver.vhd" 14 | vhdl work "../Opencores/uart_interrupt.vhd" 15 | vhdl work "../Opencores/uart_baudgen.vhd" 16 | vhdl work "../Opencores/slib_input_sync.vhd" 17 | vhdl work "../Opencores/slib_input_filter.vhd" 18 | vhdl work "../Opencores/slib_fifo.vhd" 19 | vhdl work "../Opencores/slib_edge_detect.vhd" 20 | vhdl work "../Opencores/slib_clock_div.vhd" 21 | vhdl work "../cpu86_rtl/segregfile_rtl.vhd" 22 | vhdl work "../cpu86_rtl/regshiftmux_regshift.vhd" 23 | vhdl work "../cpu86_rtl/ipregister_rtl.vhd" 24 | vhdl work "../cpu86_rtl/formatter_struct.vhd" 25 | vhdl work "../cpu86_rtl/dataregfile_rtl.vhd" 26 | vhdl work "../cpu86_rtl/biufsm_fsm.vhd" 27 | vhdl work "../cpu86_rtl/alu_rtl.vhd" 28 | vhdl work "../Opencores/uart_16750.vhd" 29 | vhdl work "../cpu86_rtl/proc_rtl.vhd" 30 | vhdl work "../cpu86_rtl/datapath_struct.vhd" 31 | vhdl work "../cpu86_rtl/biu_struct.vhd" 32 | vhdl work "../top_rtl/uart_top_struct.vhd" 33 | vhdl work "top_drigmorn1/Bootstrap_rtl.vhd" 34 | vhdl work "coregen/blk_mem_40K.vhd" 35 | vhdl work "../cpu86_rtl/cpu86_struct.vhd" 36 | vhdl work "../testbench/utils.vhd" 37 | vhdl work "../testbench/uarttx.vhd" 38 | vhdl work "../testbench/uartrx.vhd" 39 | vhdl work "top_drigmorn1/drigmorn1_top.vhd" 40 | vhdl work "testbench/Drigmorn1_tb.vhd" 41 | -------------------------------------------------------------------------------- /drigmorn1/Drigmorn1_tb_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/drigmorn1/Drigmorn1_tb_isim_beh.exe -------------------------------------------------------------------------------- /drigmorn1/coregen/blk_mem_40K.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 blk_mem_40K 4 | RECTANGLE Normal 32 32 544 672 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[15:0] 8 | PINATTR Polarity IN 9 | LINE Wide 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName dina[7:0] 12 | PINATTR Polarity IN 13 | LINE Wide 0 208 32 208 14 | PIN 0 208 LEFT 36 15 | PINATTR PinName wea[0:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 272 32 272 18 | PIN 0 272 LEFT 36 19 | PINATTR PinName clka 20 | PINATTR Polarity IN 21 | LINE Wide 576 80 544 80 22 | PIN 576 80 RIGHT 36 23 | PINATTR PinName douta[7:0] 24 | PINATTR Polarity OUT 25 | 26 | -------------------------------------------------------------------------------- /drigmorn1/coregen/blk_mem_40K.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /drigmorn1/coregen/blk_mem_40K.ise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/drigmorn1/coregen/blk_mem_40K.ise -------------------------------------------------------------------------------- /drigmorn1/coregen/blk_mem_40K.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2009-8-3T15:59:8 5 | 6 | 7 | 8 | 9 | 10 | 11 | blk_mem_40K 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /drigmorn1/coregen/blk_mem_40K_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\ 3 | blk_mem_40K.asy 4 | blk_mem_40K.gise 5 | blk_mem_40K.ise 6 | blk_mem_40K.mif 7 | blk_mem_40K.ngc 8 | blk_mem_40K.sym 9 | blk_mem_40K.vhd 10 | blk_mem_40K.vho 11 | blk_mem_40K.xco 12 | blk_mem_40K.xise 13 | blk_mem_40K_flist.txt 14 | blk_mem_40K_readme.txt 15 | blk_mem_40K_xdb\tmp\ 16 | blk_mem_40K_xmdf.tcl 17 | blk_mem_gen_ds512.pdf 18 | -------------------------------------------------------------------------------- /drigmorn1/coregen/coregen.cgp: -------------------------------------------------------------------------------- 1 | # Date: Mon Aug 03 16:00:11 2009 2 | 3 | SET addpads = False 4 | SET asysymbol = True 5 | SET busformat = BusFormatAngleBracketNotRipped 6 | SET createndf = False 7 | SET designentry = VHDL 8 | SET device = xc3s500e 9 | SET devicefamily = spartan3e 10 | SET flowvendor = Foundation_ISE 11 | SET formalverification = False 12 | SET foundationsym = False 13 | SET implementationfiletype = Ngc 14 | SET package = cp132 15 | SET removerpms = False 16 | SET simulationfiles = Behavioral 17 | SET speedgrade = -4 18 | SET verilogsim = False 19 | SET vhdlsim = True 20 | SET workingdirectory = .\tmp\ 21 | 22 | # CRC: da9e1b45 23 | -------------------------------------------------------------------------------- /drigmorn1/coregen/coregen.log: -------------------------------------------------------------------------------- 1 | Welcome to Xilinx CORE Generator. 2 | Help system initialised. 3 | Wrote project file D:\hdl_designs\cpu8088\website\cpu86\drigmorn1\coregen\coregen.cgp 4 | Wrote project file D:\hdl_designs\cpu8088\website\cpu86\drigmorn1\coregen\coregen.cgp 5 | Customizing IP... 6 | Finished Customizing. 7 | Generating IP... 8 | WARNING:sim:89 - A core named already exists in the output directory. Output products for this core may be overwritten. 9 | XST: HDL Compilation 10 | XST: Design Hierarchy Analysis 11 | XST: HDL Analysis 12 | XST: HDL Synthesis 13 | XST: Advanced HDL Synthesis 14 | XST: Low Level Synthesis 15 | Generating Implementation files. 16 | Generating ISE symbol file... 17 | Generating NGC file. 18 | Finished Generation Stage. 19 | Generating ISE file... 20 | Finished ISE file generation. 21 | Generating FLIST file... 22 | Finished FLIST file generation. 23 | Preparing output directory... 24 | Finished preparing output directory. 25 | Moving files to output directory... 26 | Finished moving files to output directory. 27 | -------------------------------------------------------------------------------- /drigmorn1/coregen/coregen.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/drigmorn1/coregen/coregen.zip -------------------------------------------------------------------------------- /drigmorn1/drigmorn1_top_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=C:\nico\perso\hack\hackerspace\fpga\x86\cpu86\drigmorn1\drigmorn1_top.ncd 3 | OUTFILE=C:\nico\perso\hack\hackerspace\fpga\x86\cpu86\drigmorn1\drigmorn1_top.bit 4 | FAMILY=Spartan3E 5 | PART=xc3s500e-4cp132 6 | WORKINGDIR=C:\nico\perso\hack\hackerspace\fpga\x86\cpu86\drigmorn1 7 | LICENSE=WebPack 8 | USER_INFO=202522545_0_0_135 9 | -------------------------------------------------------------------------------- /drigmorn1/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /drigmorn1/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -o "C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/drigmorn1/Drigmorn1_tb_isim_beh.exe" -prj "C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/drigmorn1/Drigmorn1_tb_beh.prj" "work.Drigmorn1_tb" 2 | -------------------------------------------------------------------------------- /drigmorn1/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /drigmorn1/readme.txt: -------------------------------------------------------------------------------- 1 | This directory contains the files to implement the CPU86+ROM+UART+RAM on the Enterpoint Drigmorn1 2 | FPGA Development Board. 3 | 4 | -------------------------------------------------------------------------------- /drigmorn1/top_drigmorn1/readme.txt: -------------------------------------------------------------------------------- 1 | This directory contains the Synthesis top level which instantiates the CPU86, 2 | a bootstrap ROM, 40KByte RAM and the opencores UART. 3 | 4 | See http://www.ht-lab.com/hardware/drigmorn1/drigmorn1.html for more info. -------------------------------------------------------------------------------- /drigmorn1/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /ghdl/readme.txt: -------------------------------------------------------------------------------- 1 | Quick run with GHDL: 2 | 3 | 1) Open a terminal session 4 | 2) Navigate to the web_cpu88/GHDL directory. 5 | 3) Execute run.sh: 6 | 7 | sh run.sh 8 | 9 | The simulation output should look something like this: 10 | 11 | GHDL$ sh run.sh 12 | *** Compiling the CPU86 processor *** 13 | *** Compiling Opencores 16750 UART *** 14 | ../Opencores/slib_fifo.vhd:56:46:warning: universal integer bound must be numeric literal or attribute 15 | *** Compiling example top level, CPU86+ROM+UART *** 16 | *** compiling Testbench for CPU86+ROM+UART *** 17 | ../testbench/sram.vhd:352:16:warning: procedure "do_dump" is never referenced 18 | Running Testbench in command line mode 19 | Initializing SRAM with zero ... 20 | Loading SRAM from file loadfname.dat ... 21 | RD UART : MON88 8088/8086 Monitor ver 0.12 22 | RD UART : Copyright WWW.HT-LAB.COM 2005-2008 23 | RD UART : All rights reserved. 24 | RD UART : 25 | RD UART : Cmd>R 26 | RD UART : AX=0000 BX=0001 CX=0002 DX=0003 SP=0100 BP=0005 SI=0006 DI=0007 27 | RD UART : DS=0380 ES=0380 SS=0380 CS=0380 IP=0100 ODIT-SZAPC=0000-00100 28 | RD UART : 0380:0100 0000 ADD [BX+SI], AL 29 | RD UART : Cmd>DM 0100-0124 30 | RD UART : 0380:0100 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 31 | RD UART : 0380:0110 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 32 | RD UART : 0380:0120 00 00 00 00 .... 33 | 34 | Note that it might take considerable time to show this output. 35 | 36 | To run with a wave trace, add --vcd argument and view the trace with GTKWave. 37 | 38 | sh run.sh --vcd=cpu86.vcd 39 | gtkwave cpu86.vcd 40 | 41 | Please note that the file can be quite big -- around 10G -- if you leave it 42 | running for the full 200ms. Either terminate it early, modify the 200ms value 43 | at the bottom of run.sh, or convert it to FST with vcd2fst. 44 | -------------------------------------------------------------------------------- /mx_sdram/clean.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | del /s *.bak 3 | del /s *.orig 4 | del /s *.rej 5 | del /s *~ 6 | rmdir /s /q db 7 | rmdir /s /q incremental_db 8 | rmdir /s /q output_files 9 | rmdir /s /q simulation 10 | rmdir /s /q greybox_tmp 11 | rmdir /s /q hc_output 12 | rmdir /s /q .qsys_edit 13 | rmdir /s /q hps_isw_handoff 14 | rmdir /s /q sys\.qsys_edit 15 | rmdir /s /q sys\vip 16 | for /d %%i in (sys\*_sim) do rmdir /s /q "%%i" 17 | for /d %%i in (rtl\*_sim) do rmdir /s /q "%%i" 18 | del build_id.v 19 | del c5_pin_model_dump.txt 20 | del PLLJ_PLLSPE_INFO.txt 21 | del /s *.qws 22 | del /s *.ppf 23 | del /s *.ddb 24 | del /s *.csv 25 | del /s *.cmp 26 | del /s *.sip 27 | del /s *.spd 28 | del /s *.bsf 29 | del /s *.f 30 | del /s *.sopcinfo 31 | del /s *.xml 32 | del *.cdf 33 | del *.rpt 34 | del /s new_rtl_netlist 35 | del /s old_rtl_netlist 36 | exit -------------------------------------------------------------------------------- /mx_sdram/mapping.txt: -------------------------------------------------------------------------------- 1 | 1 1 2 | 9 6 8 3 | SRAM : 15 bits = 32kB : 00000000000000000000 4 | 00000-0FFFF decode 5 | 00000-07FFF contents 6 | SDRAM : 12 bits = 4kB 7 | 10000-FFEFF decode (= 959kB) 8 | 10000-10fff contents 9 | ROM : 8 bits = 256B : 11111111111100000000 10 | FFF00-FFFFF 11 | 12 | 00000 SRAM BEGIN 0000:0000 35 17 00 00 16 14 00 00 35 17 00 00 16 14 00 00 5.......5....... 13 | 07FFF SRAM END 07FF:0000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 14 | 08000 SRAM BEGIN 0800:0000 35 17 00 00 16 14 00 00 35 17 00 00 16 14 00 00 5.......5....... 15 | 0FFFF SRAM END 0FFF:0000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 16 | 10000 SDRAM BEGIN 1000:0000 31 AA AA AA AA BA AA AA AA AA AA AA AA AA AA AB 1............... 17 | FFEFF ROM END FFEF:0000 32 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 2UUUUUUUUUUUUUUU 18 | FFF00 ROM BEGIN FFF0:0000 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 ................ 19 | FFFFF ROM END FFFF:0000 EA 00 04 00 00 00 90 90 90 90 90 90 90 90 90 90 ................ 20 | 21 | SDRAM : 8MiB in 16 bits => 4Mwords => 400000 => 22 bits address ; removing 2 bits => 1MWord 22 | 14 bits address 23 | 2 bits bank 24 | -------------------------------------------------------------------------------- /mx_sdram/max1k_88_top.sdc: -------------------------------------------------------------------------------- 1 | #create input clock which is 12MHz 2 | create_clock -name CLK12M -period 83.333 [get_ports {CLK12M}] 3 | #derive PLL clocks 4 | derive_pll_clocks 5 | #derive clock uncertainty 6 | derive_clock_uncertainty 7 | #set false path 8 | set_false_path -from [get_ports {USER_BTN}] 9 | set_false_path -from * -to [get_ports {LED*}] 10 | -------------------------------------------------------------------------------- /mx_sdram/pll12to40.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll12to40.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll12to40_inst.vhd"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll12to40.cmp"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll12to40.ppf"] 8 | -------------------------------------------------------------------------------- /mx_sdram/pll12to40_inst.vhd: -------------------------------------------------------------------------------- 1 | pll12to40_inst : pll12to40 PORT MAP ( 2 | inclk0 => inclk0_sig, 3 | c0 => c0_sig, 4 | c1 => c1_sig, 5 | c2 => c2_sig, 6 | locked => locked_sig 7 | ); 8 | -------------------------------------------------------------------------------- /mx_sdram/top.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition 21 | # Date created = 11:31:31 February 04, 2018 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "17.1" 26 | DATE = "11:31:31 February 04, 2018" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "max1k_88_top" 31 | -------------------------------------------------------------------------------- /p2_lcd_spi/README.md: -------------------------------------------------------------------------------- 1 | # Papilio2 LCD SPI 2 | 3 | This project builds upon work in the Drigmorn1 project and does the following: 4 | 5 | * Uses Papilio Duo 6 | * Uses LCD wing for Sharp LCD screens (3x6 bits colors) 7 | * Instantiates Open source 808x processor and a rudimentary VGA-like controller 8 | * The integrated MON88 monitor allows to alter the memory, such as the video memory 9 | * Currently, all text is white, but any of the 4096 available colors could be used. 10 | * Instantiates SPI master, connected to external SD card 11 | 12 | isram: 65536 bytes at: 0x00000-0x0FFFF (internal BRAM) 13 | vram: 8192 bytes at: 0x0E000-0x0FFFF (video RAM - VGA text) 14 | esram: 65536 bytes at: 0x10000-0x1FFFF (external SRAM) 15 | bootstrap: 256 bytes at: 0xFFF00-0xFFFFF 16 | 17 | VRAM_BAR=0x0E000="111" & addr_read 18 | 19 | ## Links 20 | 21 | * [Open source 808x IP](http://www.ht-lab.com/cpu86.htm) 22 | * [Papilio Duo](http://papilio.cc/index.php?n=Papilio.DUOStart) 23 | * [Papilio LCD wing (Sharp LCD screens)](https://www.logre.eu/wiki/Ecran_Sharp_LQ084V1DG21/en) 24 | * [Recreating ancient 8088 PC on FPGA (in french)](https://www.logre.eu/wiki/PC_8088_sur_FPGA) 25 | -------------------------------------------------------------------------------- /p2_lcd_spi/gen2.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | export LD_LIBRARY_PATH=/usr/lib/x86_64-linux-gnu:/lib/x86_64-linux-gnu 3 | #nasm spi.s -o a 4 | #nasm hello.s -o a 5 | #nasm bios.s -o a 6 | nasm bios2.s -o a 7 | srec_cat -Output a.ihex -Intel a -Binary -offset 0x0000 -Data_Only 8 | #echo cres1000 > a2.ihex 9 | #echo >> a2.ihex 10 | echo l > a2.ihex 11 | echo >> a2.ihex 12 | cat a.ihex >> a2.ihex 13 | # either following line to exec (don't terminate upload), 14 | #echo ":0400000303800880EE" >> a2.ihex 15 | #echo ":0400000303800080F6" >> a2.ihex 16 | #echo ":040000030380000076" >> a2.ihex 17 | 18 | # or following to terminate normal upload 19 | echo ":00000001FF" >> a2.ihex 20 | # 21 | 22 | #echo >> a2.ihex 23 | #echo bs1000 >> a2.ihex 24 | #echo >> a2.ihex 25 | #echo dm00000080 >> a2.ihex 26 | #echo >> a2.ihex 27 | 28 | #abcd 29 | # 30 | #: LEN ADH ADL TYP CHK 31 | #types: 32 | #DATA 00 33 | #EOF 01 34 | #EAD 02 => set ES (Extended Segment Address Record) :02000002USBACH 35 | #SSA 03 => RETF (Start Segment Address Record) :04000003CSCSIPIPCH 36 | # 04 (Extended Linear Address Record) 37 | # 38 | #l:00000001FF 39 | # 40 | #: 00 00 00 01 FF 41 | # 42 | #:05000000616263640A67 43 | #l 44 | #:05080000616263640A5F:00000001FF 45 | # 46 | #: 02 00 00 02 00 00 FC 47 | # 48 | #l 49 | #:05080000616263640A5F:00000001FF 50 | -------------------------------------------------------------------------------- /p2_lcd_spi/ipcore_dir/blk_mem_40K.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 blk_mem_40K 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[15:0] 8 | PINATTR Polarity IN 9 | LINE Wide 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName dina[7:0] 12 | PINATTR Polarity IN 13 | LINE Wide 0 208 32 208 14 | PIN 0 208 LEFT 36 15 | PINATTR PinName wea[0:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 272 32 272 18 | PIN 0 272 LEFT 36 19 | PINATTR PinName clka 20 | PINATTR Polarity IN 21 | LINE Wide 0 432 32 432 22 | PIN 0 432 LEFT 36 23 | PINATTR PinName addrb[15:0] 24 | PINATTR Polarity IN 25 | LINE Wide 0 464 32 464 26 | PIN 0 464 LEFT 36 27 | PINATTR PinName dinb[7:0] 28 | PINATTR Polarity IN 29 | LINE Wide 0 560 32 560 30 | PIN 0 560 LEFT 36 31 | PINATTR PinName web[0:0] 32 | PINATTR Polarity IN 33 | LINE Normal 0 624 32 624 34 | PIN 0 624 LEFT 36 35 | PINATTR PinName clkb 36 | PINATTR Polarity IN 37 | LINE Wide 576 80 544 80 38 | PIN 576 80 RIGHT 36 39 | PINATTR PinName douta[7:0] 40 | PINATTR Polarity OUT 41 | LINE Wide 576 368 544 368 42 | PIN 576 368 RIGHT 36 43 | PINATTR PinName doutb[7:0] 44 | PINATTR Polarity OUT 45 | 46 | -------------------------------------------------------------------------------- /p2_lcd_spi/ipcore_dir/blk_mem_40K.ncf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/p2_lcd_spi/ipcore_dir/blk_mem_40K.ncf -------------------------------------------------------------------------------- /p2_lcd_spi/ipcore_dir/blk_mem_40K.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2015-2-20T13:17:11 5 | 6 | 7 | 8 | 9 | 10 | 11 | blk_mem_40K 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /p2_lcd_spi/ipcore_dir/blk_mem_40K_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs/pn_parser.xmsgs 3 | blk_mem_40K/blk_mem_gen_v7_3_readme.txt 4 | blk_mem_40K/doc/blk_mem_gen_v7_3_vinfo.html 5 | blk_mem_40K/doc/pg058-blk-mem-gen.pdf 6 | blk_mem_40K/example_design/blk_mem_40K_exdes.ucf 7 | blk_mem_40K/example_design/blk_mem_40K_exdes.vhd 8 | blk_mem_40K/example_design/blk_mem_40K_exdes.xdc 9 | blk_mem_40K/example_design/blk_mem_40K_prod.vhd 10 | blk_mem_40K/implement/implement.bat 11 | blk_mem_40K/implement/implement.sh 12 | blk_mem_40K/implement/planAhead_ise.bat 13 | blk_mem_40K/implement/planAhead_ise.sh 14 | blk_mem_40K/implement/planAhead_ise.tcl 15 | blk_mem_40K/implement/xst.prj 16 | blk_mem_40K/implement/xst.scr 17 | blk_mem_40K/simulation/addr_gen.vhd 18 | blk_mem_40K/simulation/blk_mem_40K_synth.vhd 19 | blk_mem_40K/simulation/blk_mem_40K_tb.vhd 20 | blk_mem_40K/simulation/bmg_stim_gen.vhd 21 | blk_mem_40K/simulation/bmg_tb_pkg.vhd 22 | blk_mem_40K/simulation/checker.vhd 23 | blk_mem_40K/simulation/data_gen.vhd 24 | blk_mem_40K/simulation/functional/simcmds.tcl 25 | blk_mem_40K/simulation/functional/simulate_isim.sh 26 | blk_mem_40K/simulation/functional/simulate_mti.bat 27 | blk_mem_40K/simulation/functional/simulate_mti.do 28 | blk_mem_40K/simulation/functional/simulate_mti.sh 29 | blk_mem_40K/simulation/functional/simulate_ncsim.sh 30 | blk_mem_40K/simulation/functional/simulate_vcs.sh 31 | blk_mem_40K/simulation/functional/ucli_commands.key 32 | blk_mem_40K/simulation/functional/vcs_session.tcl 33 | blk_mem_40K/simulation/functional/wave_mti.do 34 | blk_mem_40K/simulation/functional/wave_ncsim.sv 35 | blk_mem_40K/simulation/random.vhd 36 | blk_mem_40K/simulation/timing/simcmds.tcl 37 | blk_mem_40K/simulation/timing/simulate_isim.sh 38 | blk_mem_40K/simulation/timing/simulate_mti.bat 39 | blk_mem_40K/simulation/timing/simulate_mti.do 40 | blk_mem_40K/simulation/timing/simulate_mti.sh 41 | blk_mem_40K/simulation/timing/simulate_ncsim.sh 42 | blk_mem_40K/simulation/timing/simulate_vcs.sh 43 | blk_mem_40K/simulation/timing/ucli_commands.key 44 | blk_mem_40K/simulation/timing/vcs_session.tcl 45 | blk_mem_40K/simulation/timing/wave_mti.do 46 | blk_mem_40K/simulation/timing/wave_ncsim.sv 47 | blk_mem_40K.asy 48 | blk_mem_40K.gise 49 | blk_mem_40K.mif 50 | blk_mem_40K.ngc 51 | blk_mem_40K.vhd 52 | blk_mem_40K.vho 53 | blk_mem_40K.xco 54 | blk_mem_40K.xise 55 | blk_mem_40K_flist.txt 56 | blk_mem_40K_xmdf.tcl 57 | summary.log 58 | -------------------------------------------------------------------------------- /p2_lcd_spi/ipcore_dir/clk32to40.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clk32to40 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | 14 | -------------------------------------------------------------------------------- /p2_lcd_spi/ipcore_dir/clk32to40.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2015-2-20T12:49:10 5 | 6 | 7 | 8 | clk32to40 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /p2_lcd_spi/ipcore_dir/clk32to40_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | clk32to40.asy 4 | clk32to40.gise 5 | clk32to40.sym 6 | clk32to40.ucf 7 | clk32to40.vhd 8 | clk32to40.vho 9 | clk32to40.xco 10 | clk32to40.xdc 11 | clk32to40.xise 12 | clk32to40\clk_wiz_v3_6_readme.txt 13 | clk32to40\doc\clk_wiz_v3_6_readme.txt 14 | clk32to40\doc\clk_wiz_v3_6_vinfo.html 15 | clk32to40\doc\pg065_clk_wiz.pdf 16 | clk32to40\example_design\clk32to40_exdes.ucf 17 | clk32to40\example_design\clk32to40_exdes.vhd 18 | clk32to40\example_design\clk32to40_exdes.xdc 19 | clk32to40\implement\implement.bat 20 | clk32to40\implement\implement.sh 21 | clk32to40\implement\planAhead_ise.bat 22 | clk32to40\implement\planAhead_ise.sh 23 | clk32to40\implement\planAhead_ise.tcl 24 | clk32to40\implement\planAhead_rdn.bat 25 | clk32to40\implement\planAhead_rdn.sh 26 | clk32to40\implement\planAhead_rdn.tcl 27 | clk32to40\implement\xst.prj 28 | clk32to40\implement\xst.scr 29 | clk32to40\simulation\clk32to40_tb.vhd 30 | clk32to40\simulation\functional\simcmds.tcl 31 | clk32to40\simulation\functional\simulate_isim.bat 32 | clk32to40\simulation\functional\simulate_isim.sh 33 | clk32to40\simulation\functional\simulate_mti.bat 34 | clk32to40\simulation\functional\simulate_mti.do 35 | clk32to40\simulation\functional\simulate_mti.sh 36 | clk32to40\simulation\functional\simulate_ncsim.sh 37 | clk32to40\simulation\functional\simulate_vcs.sh 38 | clk32to40\simulation\functional\wave.do 39 | clk32to40\simulation\functional\wave.sv 40 | clk32to40\simulation\timing\clk32to40_tb.vhd 41 | clk32to40\simulation\timing\sdf_cmd_file 42 | clk32to40\simulation\timing\simcmds.tcl 43 | clk32to40\simulation\timing\simulate_isim.sh 44 | clk32to40\simulation\timing\simulate_mti.bat 45 | clk32to40\simulation\timing\simulate_mti.do 46 | clk32to40\simulation\timing\simulate_mti.sh 47 | clk32to40\simulation\timing\simulate_ncsim.sh 48 | clk32to40\simulation\timing\simulate_vcs.sh 49 | clk32to40\simulation\timing\ucli_commands.key 50 | clk32to40\simulation\timing\vcs_session.tcl 51 | clk32to40\simulation\timing\wave.do 52 | clk32to40_flist.txt 53 | clk32to40_xmdf.tcl 54 | -------------------------------------------------------------------------------- /p2_lcd_spi/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = VHDL 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -2 8 | SET verilogsim = false 9 | SET vhdlsim = true 10 | -------------------------------------------------------------------------------- /p2_lcd_spi/ipcore_dir/create_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:7.3" "blk_mem_40K" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:7.3) generated by Project Navigator" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /p2_lcd_spi/ipcore_dir/create_clk32to40.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "clk32to40" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /p2_lcd_spi/ipcore_dir/edit_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "blk_mem_40K" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /p2_lcd_spi/ipcore_dir/gen_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator regen command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_regen "blk_mem_40K" xc6slx9-2tqg144 VHDL CURRENT ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator regen command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator regen command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator regen cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /p2_lcd_spi/put.s: -------------------------------------------------------------------------------- 1 | BITS 16 2 | CPU 8086 3 | 4 | put4hex: 5 | XCHG AL,AH ; Write AX in hex 6 | CALL put2hex 7 | XCHG AL,AH 8 | CALL put2hex 9 | RET 10 | 11 | put2hex: 12 | PUSH AX ; Save the working register 13 | SHR AL,1 14 | SHR AL,1 15 | SHR AL,1 16 | SHR AL,1 17 | CALL PUTHEX1 ; Output it 18 | POP AX ; Get the LSD 19 | CALL PUTHEX1 ; Output 20 | RET 21 | 22 | PUTHEX1: 23 | PUSH AX ; Save the working register 24 | AND AL, 0FH ; Mask off any unused bits 25 | CMP AL, 0AH ; Test for alpha or numeric 26 | JL NUMERIC ; Take the branch if numeric 27 | ADD AL, 7 ; Add the adjustment for hex alpha 28 | NUMERIC: 29 | ADD AL, '0' ; Add the numeric bias 30 | CALL txchar ; Send to the console 31 | POP AX 32 | RET 33 | 34 | ; clobbers al 35 | _crlf: 36 | mov al,0xa 37 | call txchar 38 | mov al,0xd 39 | call txchar 40 | ret 41 | 42 | ;_txchar: 43 | ; mov ah,0x0E 44 | ; int 10h 45 | ; ret 46 | -------------------------------------------------------------------------------- /p2_lcd_spi/slib_clock_div.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Clock divider (clock enable generator) 3 | -- 4 | -- Author: Sebastian Witt 5 | -- Date: 27.01.2008 6 | -- Version: 1.1 7 | -- 8 | -- This code is free software; you can redistribute it and/or 9 | -- modify it under the terms of the GNU Lesser General Public 10 | -- License as published by the Free Software Foundation; either 11 | -- version 2.1 of the License, or (at your option) any later version. 12 | -- 13 | -- This code is distributed in the hope that it will be useful, 14 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 | -- Lesser General Public License for more details. 17 | -- 18 | -- You should have received a copy of the GNU Lesser General Public 19 | -- License along with this library; if not, write to the 20 | -- Free Software Foundation, Inc., 59 Temple Place, Suite 330, 21 | -- Boston, MA 02111-1307 USA 22 | -- 23 | 24 | LIBRARY IEEE; 25 | USE IEEE.std_logic_1164.all; 26 | USE IEEE.numeric_std.all; 27 | 28 | 29 | entity slib_clock_div is 30 | generic ( 31 | RATIO : integer := 4 -- Clock divider ratio 32 | ); 33 | port ( 34 | CLK : in std_logic; -- Clock 35 | RST : in std_logic; -- Reset 36 | CE : in std_logic; -- Clock enable input 37 | Q : out std_logic -- New clock enable output 38 | ); 39 | end slib_clock_div; 40 | 41 | architecture rtl of slib_clock_div is 42 | -- Signals 43 | signal iQ : std_logic; -- Internal Q 44 | signal iCounter : integer range 0 to RATIO-1; -- Counter 45 | 46 | begin 47 | -- Main process 48 | CD_PROC: process (RST, CLK) 49 | begin 50 | if (RST = '1') then 51 | iCounter <= 0; 52 | iQ <= '0'; 53 | elsif (CLK'event and CLK='1') then 54 | iQ <= '0'; 55 | if (CE = '1') then 56 | if (iCounter = (RATIO-1)) then 57 | iQ <= '1'; 58 | iCounter <= 0; 59 | else 60 | iCounter <= iCounter + 1; 61 | end if; 62 | end if; 63 | end if; 64 | end process; 65 | 66 | -- Output signals 67 | Q <= iQ; 68 | 69 | end rtl; 70 | 71 | -------------------------------------------------------------------------------- /p2_lcd_spi/slib_edge_detect.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Signal edge detect 3 | -- 4 | -- Author: Sebastian Witt 5 | -- Data: 27.01.2008 6 | -- Version: 1.1 7 | -- 8 | -- This code is free software; you can redistribute it and/or 9 | -- modify it under the terms of the GNU Lesser General Public 10 | -- License as published by the Free Software Foundation; either 11 | -- version 2.1 of the License, or (at your option) any later version. 12 | -- 13 | -- This code is distributed in the hope that it will be useful, 14 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 | -- Lesser General Public License for more details. 17 | -- 18 | -- You should have received a copy of the GNU Lesser General Public 19 | -- License along with this library; if not, write to the 20 | -- Free Software Foundation, Inc., 59 Temple Place, Suite 330, 21 | -- Boston, MA 02111-1307 USA 22 | -- 23 | 24 | LIBRARY IEEE; 25 | USE IEEE.std_logic_1164.all; 26 | USE IEEE.numeric_std.all; 27 | 28 | entity slib_edge_detect is 29 | port ( 30 | CLK : in std_logic; -- Clock 31 | RST : in std_logic; -- Reset 32 | D : in std_logic; -- Signal input 33 | RE : out std_logic; -- Rising edge detected 34 | FE : out std_logic -- Falling edge detected 35 | ); 36 | end slib_edge_detect; 37 | 38 | architecture rtl of slib_edge_detect is 39 | signal iDd : std_logic; -- D register 40 | begin 41 | -- Store D 42 | ED_D: process (RST, CLK) 43 | begin 44 | if (RST = '1') then 45 | iDd <= '0'; 46 | elsif (CLK'event and CLK='1') then 47 | iDd <= D; 48 | end if; 49 | end process; 50 | 51 | -- Output ports 52 | RE <= '1' when iDd = '0' and D = '1' else '0'; 53 | FE <= '1' when iDd = '1' and D = '0' else '0'; 54 | 55 | end rtl; 56 | 57 | 58 | -------------------------------------------------------------------------------- /p2_lcd_spi/slib_input_filter.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Input filter 3 | -- 4 | -- Author: Sebastian Witt 5 | -- Data: 06.03.2008 6 | -- Version: 1.0 7 | -- 8 | -- This code is free software; you can redistribute it and/or 9 | -- modify it under the terms of the GNU Lesser General Public 10 | -- License as published by the Free Software Foundation; either 11 | -- version 2.1 of the License, or (at your option) any later version. 12 | -- 13 | -- This code is distributed in the hope that it will be useful, 14 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 | -- Lesser General Public License for more details. 17 | -- 18 | -- You should have received a copy of the GNU Lesser General Public 19 | -- License along with this library; if not, write to the 20 | -- Free Software Foundation, Inc., 59 Temple Place, Suite 330, 21 | -- Boston, MA 02111-1307 USA 22 | -- 23 | 24 | LIBRARY IEEE; 25 | USE IEEE.std_logic_1164.all; 26 | USE IEEE.numeric_std.all; 27 | 28 | entity slib_input_filter is 29 | generic ( 30 | SIZE : natural := 4 -- Filter counter size 31 | ); 32 | port ( 33 | CLK : in std_logic; -- Clock 34 | RST : in std_logic; -- Reset 35 | CE : in std_logic; -- Clock enable 36 | D : in std_logic; -- Signal input 37 | Q : out std_logic -- Signal output 38 | ); 39 | end slib_input_filter; 40 | 41 | architecture rtl of slib_input_filter is 42 | signal iCount : integer range 0 to SIZE; 43 | begin 44 | IF_D: process (RST, CLK) 45 | begin 46 | if (RST = '1') then 47 | iCount <= 0; 48 | Q <= '0'; 49 | elsif (CLK'event and CLK='1') then 50 | -- Input counter 51 | if (CE = '1' ) then 52 | if (D = '1' and iCount /= SIZE) then 53 | iCount <= iCount + 1; 54 | elsif (D = '0' and iCount /= 0) then 55 | iCount <= iCount - 1; 56 | end if; 57 | end if; 58 | 59 | -- Output 60 | if (iCount = SIZE) then 61 | Q <= '1'; 62 | elsif (iCount = 0) then 63 | Q <= '0'; 64 | end if; 65 | end if; 66 | end process; 67 | 68 | end rtl; 69 | 70 | -------------------------------------------------------------------------------- /p2_lcd_spi/slib_input_sync.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Input synchronization 3 | -- 4 | -- Author: Sebastian Witt 5 | -- Data: 27.01.2008 6 | -- Version: 1.0 7 | -- 8 | -- This code is free software; you can redistribute it and/or 9 | -- modify it under the terms of the GNU Lesser General Public 10 | -- License as published by the Free Software Foundation; either 11 | -- version 2.1 of the License, or (at your option) any later version. 12 | -- 13 | -- This code is distributed in the hope that it will be useful, 14 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 | -- Lesser General Public License for more details. 17 | -- 18 | -- You should have received a copy of the GNU Lesser General Public 19 | -- License along with this library; if not, write to the 20 | -- Free Software Foundation, Inc., 59 Temple Place, Suite 330, 21 | -- Boston, MA 02111-1307 USA 22 | -- 23 | 24 | LIBRARY IEEE; 25 | USE IEEE.std_logic_1164.all; 26 | USE IEEE.numeric_std.all; 27 | 28 | entity slib_input_sync is 29 | port ( 30 | CLK : in std_logic; -- Clock 31 | RST : in std_logic; -- Reset 32 | D : in std_logic; -- Signal input 33 | Q : out std_logic -- Signal output 34 | ); 35 | end slib_input_sync; 36 | 37 | architecture rtl of slib_input_sync is 38 | signal iD : std_logic_vector(1 downto 0); 39 | begin 40 | IS_D: process (RST, CLK) 41 | begin 42 | if (RST = '1') then 43 | iD <= (others => '0'); 44 | elsif (CLK'event and CLK='1') then 45 | iD(0) <= D; 46 | iD(1) <= iD(0); 47 | end if; 48 | end process; 49 | 50 | -- Output ports 51 | Q <= iD(1); 52 | 53 | end rtl; 54 | 55 | -------------------------------------------------------------------------------- /p2_lcd_spi/vga_sync.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Copyright 2011, Kevin Lindsey 3 | -- See LICENSE file for licensing information 4 | -- 5 | -- Based on code from P. P. Chu, "FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version", 2008 6 | -- Chapters 12-13 7 | -- 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 11 | use ieee.numeric_std.all; 12 | 13 | entity vga_sync is 14 | port( 15 | clock: in std_logic; 16 | reset: in std_logic; 17 | hsync, vsync: out std_logic; 18 | video_on: out std_logic; 19 | pixel_tick: out std_logic; 20 | pixel_x, pixel_y: out std_logic_vector(9 downto 0) 21 | ); 22 | end vga_sync; 23 | 24 | architecture arch of vga_sync is 25 | signal h_sync_reg, v_sync_reg, video_on_reg: std_logic := '0'; 26 | signal v_count_reg: std_logic_vector(9 downto 0); 27 | signal h_count_reg: std_logic_vector(9 downto 0); 28 | -- VGA 640x480 29 | constant thp : integer := 6; -- hsync 156 30 | constant htotal : integer := 850; -- screen size, with back porch 900 31 | constant tvp : integer := 34; -- vsync 1 32 | constant vtotal : integer := 560; -- screen size, with back porch 560 33 | 34 | begin 35 | -- registers 36 | process(clock) 37 | begin 38 | if rising_edge(clock) then 39 | video_on_reg <= '1'; 40 | if h_count_reg < (thp) then 41 | h_sync_reg <= '0'; 42 | video_on_reg <= '0'; 43 | else 44 | h_sync_reg <= '1'; 45 | end if; 46 | if v_count_reg < tvp then 47 | v_sync_reg <= '0'; 48 | video_on_reg <= '0'; 49 | else 50 | v_sync_reg <= '1'; 51 | end if; 52 | if h_count_reg = htotal then 53 | h_count_reg <= (others => '0'); 54 | if v_count_reg = vtotal then 55 | v_count_reg <= (others => '0'); 56 | else 57 | v_count_reg <= v_count_reg + 1; 58 | end if; 59 | else 60 | h_count_reg <= h_count_reg + 1; 61 | end if; 62 | end if; 63 | end process; 64 | 65 | 66 | -- video on/off 67 | -- video_on <= h_sync_reg and v_sync_reg; 68 | video_on <= video_on_reg; 69 | 70 | -- output signals 71 | hsync <= h_sync_reg; 72 | vsync <= v_sync_reg; 73 | pixel_x <= std_logic_vector(h_count_reg)-thp-104; 74 | pixel_y <= std_logic_vector(v_count_reg)-tvp; 75 | -- pixel_tick <= p_tick; 76 | end arch; 77 | -------------------------------------------------------------------------------- /p2_lcd_spi/wingbutled.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 21:23:33 02/02/2011 6 | -- Design Name: 7 | -- Module Name: wingbutled - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | --use IEEE.NUMERIC_STD.ALL; 23 | entity wingbutled is 24 | Port ( 25 | io : inout STD_LOGIC_VECTOR (7 downto 0); 26 | buttons : out STD_LOGIC_VECTOR (3 downto 0); 27 | leds : in STD_LOGIC_VECTOR (3 downto 0) 28 | ); 29 | end wingbutled; 30 | architecture Behavioral of wingbutled is 31 | begin 32 | io(0) <= leds(3); 33 | io(2) <= leds(2); 34 | io(4) <= leds(1); 35 | io(6) <= leds(0); 36 | io(1) <= 'Z'; 37 | io(3) <= 'Z'; 38 | io(5) <= 'Z'; 39 | io(7) <= 'Z'; 40 | buttons(3) <= io(1); 41 | buttons(2) <= io(3); 42 | buttons(1) <= io(5); 43 | buttons(0) <= io(7); 44 | end Behavioral; 45 | -------------------------------------------------------------------------------- /p2_vga_spi/README.md: -------------------------------------------------------------------------------- 1 | # Papilio2 VGA SPI 2 | 3 | This project builds upon work in the Drigmorn1 project and does the following: 4 | 5 | * Uses Papilio Duo 6 | * Uses Classic Computing Shield for VGA output (3x4 bits colors) 7 | * Instantiates Open source 808x processor and a rudimentary VGA-like controller 8 | * The integrated MON88 monitor allows to alter the memory, such as the video memory 9 | * Currently, all text is white, but any of the 4096 available colors could be used. 10 | 11 | ## Links 12 | 13 | * [Open source 808x IP](http://www.ht-lab.com/cpu86.htm) 14 | * [Papilio Duo](http://papilio.cc/index.php?n=Papilio.DUOStart) 15 | * [Papilio Classic Computing Shield (VGA)](http://papilio.cc/index.php?n=Papilio.ClassicComputingShield#vga) 16 | * [Recreating ancient 8088 PC on FPGA (in french)](https://wiki.logre.eu/index.php/PC_8088_sur_FPGA) 17 | -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/blk_mem_40K.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 blk_mem_40K 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[15:0] 8 | PINATTR Polarity IN 9 | LINE Wide 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName dina[7:0] 12 | PINATTR Polarity IN 13 | LINE Wide 0 208 32 208 14 | PIN 0 208 LEFT 36 15 | PINATTR PinName wea[0:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 272 32 272 18 | PIN 0 272 LEFT 36 19 | PINATTR PinName clka 20 | PINATTR Polarity IN 21 | LINE Wide 0 432 32 432 22 | PIN 0 432 LEFT 36 23 | PINATTR PinName addrb[15:0] 24 | PINATTR Polarity IN 25 | LINE Wide 0 464 32 464 26 | PIN 0 464 LEFT 36 27 | PINATTR PinName dinb[7:0] 28 | PINATTR Polarity IN 29 | LINE Wide 0 560 32 560 30 | PIN 0 560 LEFT 36 31 | PINATTR PinName web[0:0] 32 | PINATTR Polarity IN 33 | LINE Normal 0 624 32 624 34 | PIN 0 624 LEFT 36 35 | PINATTR PinName clkb 36 | PINATTR Polarity IN 37 | LINE Wide 576 80 544 80 38 | PIN 576 80 RIGHT 36 39 | PINATTR PinName douta[7:0] 40 | PINATTR Polarity OUT 41 | LINE Wide 576 368 544 368 42 | PIN 576 368 RIGHT 36 43 | PINATTR PinName doutb[7:0] 44 | PINATTR Polarity OUT 45 | 46 | -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/blk_mem_40K.ncf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/p2_vga_spi/ipcore_dir/blk_mem_40K.ncf -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/blk_mem_40K.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2015-2-20T13:17:11 5 | 6 | 7 | 8 | 9 | 10 | 11 | blk_mem_40K 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/blk_mem_40K_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs/pn_parser.xmsgs 3 | blk_mem_40K/blk_mem_gen_v7_3_readme.txt 4 | blk_mem_40K/doc/blk_mem_gen_v7_3_vinfo.html 5 | blk_mem_40K/doc/pg058-blk-mem-gen.pdf 6 | blk_mem_40K.asy 7 | blk_mem_40K.gise 8 | blk_mem_40K.mif 9 | blk_mem_40K.ngc 10 | blk_mem_40K.vhd 11 | blk_mem_40K.vho 12 | blk_mem_40K.xco 13 | blk_mem_40K.xise 14 | blk_mem_40K_flist.txt 15 | blk_mem_40K_xmdf.tcl 16 | summary.log 17 | -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/clk32to40.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clk32to40 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | LINE Normal 608 176 576 176 14 | PIN 608 176 RIGHT 36 15 | PINATTR PinName clk_out2 16 | PINATTR Polarity OUT 17 | 18 | -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/clk32to40.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2015-2-20T12:49:10 5 | 6 | 7 | 8 | clk32to40 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/clk32to40_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs/pn_parser.xmsgs 3 | clk32to40/clk_wiz_v3_6_readme.txt 4 | clk32to40/doc/clk_wiz_v3_6_readme.txt 5 | clk32to40/doc/clk_wiz_v3_6_vinfo.html 6 | clk32to40/doc/pg065_clk_wiz.pdf 7 | clk32to40/example_design/clk32to40_exdes.ucf 8 | clk32to40/example_design/clk32to40_exdes.vhd 9 | clk32to40/example_design/clk32to40_exdes.xdc 10 | clk32to40/implement/implement.bat 11 | clk32to40/implement/implement.sh 12 | clk32to40/implement/planAhead_ise.bat 13 | clk32to40/implement/planAhead_ise.sh 14 | clk32to40/implement/planAhead_ise.tcl 15 | clk32to40/implement/planAhead_rdn.bat 16 | clk32to40/implement/planAhead_rdn.sh 17 | clk32to40/implement/planAhead_rdn.tcl 18 | clk32to40/implement/xst.prj 19 | clk32to40/implement/xst.scr 20 | clk32to40/simulation/clk32to40_tb.vhd 21 | clk32to40/simulation/functional/simcmds.tcl 22 | clk32to40/simulation/functional/simulate_isim.bat 23 | clk32to40/simulation/functional/simulate_isim.sh 24 | clk32to40/simulation/functional/simulate_mti.bat 25 | clk32to40/simulation/functional/simulate_mti.do 26 | clk32to40/simulation/functional/simulate_mti.sh 27 | clk32to40/simulation/functional/simulate_ncsim.sh 28 | clk32to40/simulation/functional/simulate_vcs.sh 29 | clk32to40/simulation/functional/wave.do 30 | clk32to40/simulation/functional/wave.sv 31 | clk32to40/simulation/timing/clk32to40_tb.vhd 32 | clk32to40/simulation/timing/sdf_cmd_file 33 | clk32to40/simulation/timing/simcmds.tcl 34 | clk32to40/simulation/timing/simulate_isim.sh 35 | clk32to40/simulation/timing/simulate_mti.bat 36 | clk32to40/simulation/timing/simulate_mti.do 37 | clk32to40/simulation/timing/simulate_mti.sh 38 | clk32to40/simulation/timing/simulate_ncsim.sh 39 | clk32to40/simulation/timing/simulate_vcs.sh 40 | clk32to40/simulation/timing/ucli_commands.key 41 | clk32to40/simulation/timing/vcs_session.tcl 42 | clk32to40/simulation/timing/wave.do 43 | clk32to40.asy 44 | clk32to40.gise 45 | clk32to40.ucf 46 | clk32to40.vhd 47 | clk32to40.vho 48 | clk32to40.xco 49 | clk32to40.xdc 50 | clk32to40.xise 51 | clk32to40_flist.txt 52 | clk32to40_xmdf.tcl 53 | -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = VHDL 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -2 8 | SET verilogsim = false 9 | SET vhdlsim = true 10 | -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/create_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:7.3" "blk_mem_40K" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:7.3) generated by Project Navigator" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/create_clk32to40.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "clk32to40" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/edit_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "blk_mem_40K" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/edit_clk32to40.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "clk32to40" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /p2_vga_spi/ipcore_dir/gen_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator regen command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_regen "blk_mem_40K" xc6slx9-2tqg144 VHDL CURRENT ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator regen command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator regen command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator regen cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio1/a.py: -------------------------------------------------------------------------------- 1 | f=open("blk_orig.mif") 2 | n=16383 3 | for d in f.readlines(): 4 | print("%d : %s;" % (n, d.replace("\n",""))) 5 | n -= 1 6 | while n >= 0: 7 | print("%d : 00000000;" % n) 8 | n -= 1 9 | -------------------------------------------------------------------------------- /papilio1/coregen/blk_mem_40K.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2009-8-3T15:59:8 5 | 6 | 7 | 8 | 9 | 10 | 11 | blk_mem_40K 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /papilio1/dcm32to40_arwz.ucf: -------------------------------------------------------------------------------- 1 | # Generated by Xilinx Architecture Wizard 2 | # --- UCF Template Only --- 3 | # Cut and paste these attributes into the project's UCF file, if desired 4 | INST DCM_SP_INST CLK_FEEDBACK = 1X; 5 | INST DCM_SP_INST CLKDV_DIVIDE = 2.0; 6 | INST DCM_SP_INST CLKFX_DIVIDE = 4; 7 | INST DCM_SP_INST CLKFX_MULTIPLY = 5; 8 | INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; 9 | INST DCM_SP_INST CLKIN_PERIOD = 31.250; 10 | INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; 11 | INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 12 | INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; 13 | INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; 14 | INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; 15 | INST DCM_SP_INST FACTORY_JF = C080; 16 | INST DCM_SP_INST PHASE_SHIFT = 0; 17 | INST DCM_SP_INST STARTUP_WAIT = FALSE; 18 | -------------------------------------------------------------------------------- /papilio1/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /papilio1/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -o "C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/papilio1/papilio1_tb2_isim_beh.exe" -prj "C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/papilio1/papilio1_tb2_beh.prj" "work.papilio1_tb2" 2 | -------------------------------------------------------------------------------- /papilio1/ipcore_dir/_xmsgs/cg.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Generating IP... 9 | 10 | 11 | The selected IP does not support an ASY schematic symbol. 12 | 13 | 14 | Finished generation of ASY schematic symbol. 15 | 16 | 17 | The chosen IP does not support an SYM schematic symbol. 18 | 19 | 20 | Finished FLIST file generation. 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /papilio1/ipcore_dir/create_dcm32to40.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:dcm_sp:13.1" "dcm32to40" "Single DCM_SP" "Single DCM_SP (xilinx.com:ip:dcm_sp:13.1) generated by Project Navigator" xc3s500e-4vq100 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio1/ipcore_dir/dcm32to40_arwz.ucf: -------------------------------------------------------------------------------- 1 | # Generated by Xilinx Architecture Wizard 2 | # --- UCF Template Only --- 3 | # Cut and paste these attributes into the project's UCF file, if desired 4 | INST DCM_SP_INST CLK_FEEDBACK = 1X; 5 | INST DCM_SP_INST CLKDV_DIVIDE = 2.0; 6 | INST DCM_SP_INST CLKFX_DIVIDE = 4; 7 | INST DCM_SP_INST CLKFX_MULTIPLY = 5; 8 | INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; 9 | INST DCM_SP_INST CLKIN_PERIOD = 31.250; 10 | INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; 11 | INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 12 | INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; 13 | INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; 14 | INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; 15 | INST DCM_SP_INST FACTORY_JF = C080; 16 | INST DCM_SP_INST PHASE_SHIFT = 0; 17 | INST DCM_SP_INST STARTUP_WAIT = FALSE; 18 | -------------------------------------------------------------------------------- /papilio1/ipcore_dir/dcm32to40_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | dcm32to40_flist.txt 3 | -------------------------------------------------------------------------------- /papilio1/ipcore_dir/xaw2vhdl.log: -------------------------------------------------------------------------------- 1 | xaw2vhdl: Completed successfully 2 | -------------------------------------------------------------------------------- /papilio1/papilio1_top_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=/home/nico/git/cpu86/papilio1/papilio1_top.ncd 3 | OUTFILE=/home/nico/git/cpu86/papilio1/papilio1_top.bit 4 | FAMILY=Spartan3E 5 | PART=xc3s500e-4vq100 6 | WORKINGDIR=/home/nico/git/cpu86/papilio1 7 | LICENSE=WebPack 8 | USER_INFO=202522545_0_0_650 9 | -------------------------------------------------------------------------------- /papilio1/pepExtractor.prj: -------------------------------------------------------------------------------- 1 | work "coregen/blk_mem_40K.vhd" 2 | work "dcm32to40.vhd" 3 | work "papilio1_top.vhd" 4 | work "../Opencores/slib_clock_div.vhd" 5 | work "../Opencores/slib_counter.vhd" 6 | work "../Opencores/slib_edge_detect.vhd" 7 | work "../Opencores/slib_fifo.vhd" 8 | work "../Opencores/slib_input_filter.vhd" 9 | work "../Opencores/slib_input_sync.vhd" 10 | work "../Opencores/slib_mv_filter.vhd" 11 | work "../Opencores/uart_16750.vhd" 12 | work "../Opencores/uart_baudgen.vhd" 13 | work "../Opencores/uart_interrupt.vhd" 14 | work "../Opencores/uart_receiver.vhd" 15 | work "../Opencores/uart_transmitter.vhd" 16 | work "../cpu86_rtl/a_table.vhd" 17 | work "../cpu86_rtl/alu_rtl.vhd" 18 | work "../cpu86_rtl/biu_struct.vhd" 19 | work "../cpu86_rtl/biufsm_fsm.vhd" 20 | work "../cpu86_rtl/cpu86_struct.vhd" 21 | work "../cpu86_rtl/cpu86instr.vhd" 22 | work "../cpu86_rtl/cpu86pack.vhd" 23 | work "../cpu86_rtl/d_table.vhd" 24 | work "../cpu86_rtl/datapath_struct.vhd" 25 | work "../cpu86_rtl/dataregfile_rtl.vhd" 26 | work "../cpu86_rtl/divider_rtl_ser.vhd" 27 | work "../cpu86_rtl/formatter_struct.vhd" 28 | work "../cpu86_rtl/ipregister_rtl.vhd" 29 | work "../cpu86_rtl/m_table.vhd" 30 | work "../cpu86_rtl/multiplier_rtl.vhd" 31 | work "../cpu86_rtl/n_table.vhd" 32 | work "../cpu86_rtl/proc_rtl.vhd" 33 | work "../cpu86_rtl/r_table.vhd" 34 | work "../cpu86_rtl/regshiftmux_regshift.vhd" 35 | work "../cpu86_rtl/segregfile_rtl.vhd" 36 | work "../top_rtl/uart_top_struct.vhd" 37 | work "top_drigmorn1/Bootstrap_rtl.vhd" 38 | work "top_drigmorn1/drigmorn1_top.vhd" 39 | -------------------------------------------------------------------------------- /papilio1_0/coregen/blk_mem_40K.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 blk_mem_40K 4 | RECTANGLE Normal 32 32 544 672 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[15:0] 8 | PINATTR Polarity IN 9 | LINE Wide 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName dina[7:0] 12 | PINATTR Polarity IN 13 | LINE Wide 0 208 32 208 14 | PIN 0 208 LEFT 36 15 | PINATTR PinName wea[0:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 272 32 272 18 | PIN 0 272 LEFT 36 19 | PINATTR PinName clka 20 | PINATTR Polarity IN 21 | LINE Wide 576 80 544 80 22 | PIN 576 80 RIGHT 36 23 | PINATTR PinName douta[7:0] 24 | PINATTR Polarity OUT 25 | 26 | -------------------------------------------------------------------------------- /papilio1_0/coregen/blk_mem_40K.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /papilio1_0/coregen/blk_mem_40K.ise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/papilio1_0/coregen/blk_mem_40K.ise -------------------------------------------------------------------------------- /papilio1_0/coregen/blk_mem_40K.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2009-8-3T15:59:8 5 | 6 | 7 | 8 | 9 | 10 | 11 | blk_mem_40K 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /papilio1_0/coregen/blk_mem_40K_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\ 3 | blk_mem_40K.asy 4 | blk_mem_40K.gise 5 | blk_mem_40K.ise 6 | blk_mem_40K.mif 7 | blk_mem_40K.ngc 8 | blk_mem_40K.sym 9 | blk_mem_40K.vhd 10 | blk_mem_40K.vho 11 | blk_mem_40K.xco 12 | blk_mem_40K.xise 13 | blk_mem_40K_flist.txt 14 | blk_mem_40K_readme.txt 15 | blk_mem_40K_xdb\tmp\ 16 | blk_mem_40K_xmdf.tcl 17 | blk_mem_gen_ds512.pdf 18 | -------------------------------------------------------------------------------- /papilio1_0/coregen/coregen.cgp: -------------------------------------------------------------------------------- 1 | # Date: Mon Aug 03 16:00:11 2009 2 | 3 | SET addpads = False 4 | SET asysymbol = True 5 | SET busformat = BusFormatAngleBracketNotRipped 6 | SET createndf = False 7 | SET designentry = VHDL 8 | SET device = xc3s500e 9 | SET devicefamily = spartan3e 10 | SET flowvendor = Foundation_ISE 11 | SET formalverification = False 12 | SET foundationsym = False 13 | SET implementationfiletype = Ngc 14 | SET package = cp132 15 | SET removerpms = False 16 | SET simulationfiles = Behavioral 17 | SET speedgrade = -4 18 | SET verilogsim = False 19 | SET vhdlsim = True 20 | SET workingdirectory = .\tmp\ 21 | 22 | # CRC: da9e1b45 23 | -------------------------------------------------------------------------------- /papilio1_0/coregen/coregen.log: -------------------------------------------------------------------------------- 1 | Welcome to Xilinx CORE Generator. 2 | Help system initialised. 3 | Wrote project file D:\hdl_designs\cpu8088\website\cpu86\drigmorn1\coregen\coregen.cgp 4 | Wrote project file D:\hdl_designs\cpu8088\website\cpu86\drigmorn1\coregen\coregen.cgp 5 | Customizing IP... 6 | Finished Customizing. 7 | Generating IP... 8 | WARNING:sim:89 - A core named already exists in the output directory. Output products for this core may be overwritten. 9 | XST: HDL Compilation 10 | XST: Design Hierarchy Analysis 11 | XST: HDL Analysis 12 | XST: HDL Synthesis 13 | XST: Advanced HDL Synthesis 14 | XST: Low Level Synthesis 15 | Generating Implementation files. 16 | Generating ISE symbol file... 17 | Generating NGC file. 18 | Finished Generation Stage. 19 | Generating ISE file... 20 | Finished ISE file generation. 21 | Generating FLIST file... 22 | Finished FLIST file generation. 23 | Preparing output directory... 24 | Finished preparing output directory. 25 | Moving files to output directory... 26 | Finished moving files to output directory. 27 | -------------------------------------------------------------------------------- /papilio1_0/coregen/coregen.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/papilio1_0/coregen/coregen.zip -------------------------------------------------------------------------------- /papilio1_0/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /papilio1_0/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -o "C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/papilio1_0/papilio1_tb_isim_beh.exe" -prj "C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/papilio1_0/papilio1_tb_beh.prj" "work.papilio1_tb" 2 | -------------------------------------------------------------------------------- /papilio1_0/ipcore_dir/_xmsgs/cg.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Generating IP... 9 | 10 | 11 | The selected IP does not support an ASY schematic symbol. 12 | 13 | 14 | Finished generation of ASY schematic symbol. 15 | 16 | 17 | The chosen IP does not support an SYM schematic symbol. 18 | 19 | 20 | Finished FLIST file generation. 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /papilio1_0/ipcore_dir/create_dcm32to40.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:dcm_sp:13.1" "dcm32to40" "Single DCM_SP" "Single DCM_SP (xilinx.com:ip:dcm_sp:13.1) generated by Project Navigator" xc3s500e-4cp132 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio1_0/ipcore_dir/dcm32to40_arwz.ucf: -------------------------------------------------------------------------------- 1 | # Generated by Xilinx Architecture Wizard 2 | # --- UCF Template Only --- 3 | # Cut and paste these attributes into the project's UCF file, if desired 4 | INST DCM_SP_INST CLK_FEEDBACK = 1X; 5 | INST DCM_SP_INST CLKDV_DIVIDE = 2.0; 6 | INST DCM_SP_INST CLKFX_DIVIDE = 4; 7 | INST DCM_SP_INST CLKFX_MULTIPLY = 5; 8 | INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; 9 | INST DCM_SP_INST CLKIN_PERIOD = 31.250; 10 | INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; 11 | INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 12 | INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; 13 | INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; 14 | INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; 15 | INST DCM_SP_INST FACTORY_JF = C080; 16 | INST DCM_SP_INST PHASE_SHIFT = 0; 17 | INST DCM_SP_INST STARTUP_WAIT = FALSE; 18 | -------------------------------------------------------------------------------- /papilio1_0/ipcore_dir/dcm32to40_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | dcm32to40_flist.txt 3 | -------------------------------------------------------------------------------- /papilio1_0/ipcore_dir/xaw2vhdl.log: -------------------------------------------------------------------------------- 1 | xaw2vhdl: Completed successfully 2 | -------------------------------------------------------------------------------- /papilio1_0/papilio1.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /papilio1_0/pepExtractor.prj: -------------------------------------------------------------------------------- 1 | work "dcm32to40.vhd" 2 | -------------------------------------------------------------------------------- /papilio1_0/readme.txt: -------------------------------------------------------------------------------- 1 | This directory contains the files to implement the CPU86+ROM+UART+RAM on the Enterpoint Drigmorn1 2 | FPGA Development Board. 3 | 4 | -------------------------------------------------------------------------------- /papilio1_0/top_drigmorn1/readme.txt: -------------------------------------------------------------------------------- 1 | This directory contains the Synthesis top level which instantiates the CPU86, 2 | a bootstrap ROM, 40KByte RAM and the opencores UART. 3 | 4 | See http://www.ht-lab.com/hardware/drigmorn1/drigmorn1.html for more info. -------------------------------------------------------------------------------- /papilio1_0_rom/coregen/blk_mem_40K.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2009-8-3T15:59:8 5 | 6 | 7 | 8 | 9 | 10 | 11 | blk_mem_40K 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /papilio1_0_rom/dcm32to40_arwz.ucf: -------------------------------------------------------------------------------- 1 | # Generated by Xilinx Architecture Wizard 2 | # --- UCF Template Only --- 3 | # Cut and paste these attributes into the project's UCF file, if desired 4 | INST DCM_SP_INST CLK_FEEDBACK = 1X; 5 | INST DCM_SP_INST CLKDV_DIVIDE = 2.0; 6 | INST DCM_SP_INST CLKFX_DIVIDE = 4; 7 | INST DCM_SP_INST CLKFX_MULTIPLY = 5; 8 | INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; 9 | INST DCM_SP_INST CLKIN_PERIOD = 31.250; 10 | INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; 11 | INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 12 | INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; 13 | INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; 14 | INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; 15 | INST DCM_SP_INST FACTORY_JF = C080; 16 | INST DCM_SP_INST PHASE_SHIFT = 0; 17 | INST DCM_SP_INST STARTUP_WAIT = FALSE; 18 | -------------------------------------------------------------------------------- /papilio2/esram.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 17:10:00 02/25/2015 6 | -- Design Name: 7 | -- Module Name: esram - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Uncomment the following library declaration if using 24 | -- arithmetic functions with Signed or Unsigned values 25 | --use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx primitives in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity esram is 33 | PORT ( 34 | addra : IN std_logic_VECTOR (7 DOWNTO 0); 35 | clka : IN std_logic; 36 | dina : IN std_logic_VECTOR (7 DOWNTO 0); 37 | wea : IN std_logic_VECTOR (0 DOWNTO 0); 38 | douta : OUT std_logic_VECTOR (7 DOWNTO 0) 39 | ); 40 | end esram; 41 | 42 | architecture Behavioral of esram is 43 | 44 | begin 45 | 46 | 47 | end Behavioral; 48 | 49 | -------------------------------------------------------------------------------- /papilio2/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /papilio2/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "secureip" -o "C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/papilio2/papilio1_tb_isim_beh.exe" -prj "C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/papilio2/papilio1_tb_beh.prj" "work.papilio1_tb" 2 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/_xmsgs/cg.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Generating IP... 9 | 10 | 11 | A core named 'blk_mem_40K' already exists in the project. Output products for this core may be overwritten. 12 | 13 | 14 | A core named 'blk_mem_40K' already exists in the project. Output products for this core may be overwritten. 15 | 16 | 17 | Pre-processing HDL files for 'blk_mem_40K'... 18 | 19 | 20 | Overwriting existing file C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/papilio2/ipcore_dir/tmp/_cg/blk_mem_40K/doc/blk_mem_gen_v7_3_vinfo.html with file from view xilinx_documentation 21 | 22 | 23 | Finished generation of ASY schematic symbol. 24 | 25 | 26 | Finished FLIST file generation. 27 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 blk_mem_40K 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[15:0] 8 | PINATTR Polarity IN 9 | LINE Wide 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName dina[7:0] 12 | PINATTR Polarity IN 13 | LINE Wide 0 208 32 208 14 | PIN 0 208 LEFT 36 15 | PINATTR PinName wea[0:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 272 32 272 18 | PIN 0 272 LEFT 36 19 | PINATTR PinName clka 20 | PINATTR Polarity IN 21 | LINE Wide 576 80 544 80 22 | PIN 576 80 RIGHT 36 23 | PINATTR PinName douta[7:0] 24 | PINATTR Polarity OUT 25 | 26 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K.ncf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/papilio2/ipcore_dir/blk_mem_40K.ncf -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2015-2-27T1:13:23 5 | 6 | 7 | 8 | 9 | 10 | 11 | blk_mem_40K 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/doc/pg058-blk-mem-gen.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/papilio2/ipcore_dir/blk_mem_40K/doc/pg058-blk-mem-gen.pdf -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/implement/implement.bat: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | rem Clean up the results directory 10 | rmdir /S /Q results 11 | mkdir results 12 | 13 | rem Synthesize the VHDL Wrapper Files 14 | 15 | 16 | echo 'Synthesizing example design with XST'; 17 | xst -ifn xst.scr 18 | copy blk_mem_40K_exdes.ngc .\results\ 19 | 20 | 21 | rem Copy the netlist generated by Coregen 22 | echo 'Copying files from the netlist directory to the results directory' 23 | copy ..\..\blk_mem_40K.ngc results\ 24 | 25 | 26 | rem Copy the constraints files generated by Coregen 27 | echo 'Copying files from constraints directory to results directory' 28 | copy ..\example_design\blk_mem_40K_exdes.ucf results\ 29 | 30 | cd results 31 | 32 | echo 'Running ngdbuild' 33 | ngdbuild -p xc6slx9-tqg144-2 blk_mem_40K_exdes 34 | 35 | echo 'Running map' 36 | map blk_mem_40K_exdes -o mapped.ncd -pr i 37 | 38 | echo 'Running par' 39 | par mapped.ncd routed.ncd 40 | 41 | echo 'Running trce' 42 | trce -e 10 routed.ncd mapped.pcf -o routed 43 | 44 | echo 'Running design through bitgen' 45 | bitgen -w routed 46 | 47 | echo 'Running netgen to create gate level VHDL model' 48 | netgen -ofmt vhdl -sim -tm blk_mem_40K_exdes -pcf mapped.pcf -w routed.ncd routed.vhd 49 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/implement/implement.sh: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | #!/bin/sh 10 | 11 | # Clean up the results directory 12 | rm -rf results 13 | mkdir results 14 | 15 | #Synthesize the Wrapper Files 16 | 17 | echo 'Synthesizing example design with XST'; 18 | xst -ifn xst.scr 19 | cp blk_mem_40K_exdes.ngc ./results/ 20 | 21 | 22 | # Copy the netlist generated by Coregen 23 | echo 'Copying files from the netlist directory to the results directory' 24 | cp ../../blk_mem_40K.ngc results/ 25 | 26 | # Copy the constraints files generated by Coregen 27 | echo 'Copying files from constraints directory to results directory' 28 | cp ../example_design/blk_mem_40K_exdes.ucf results/ 29 | 30 | cd results 31 | 32 | echo 'Running ngdbuild' 33 | ngdbuild -p xc6slx9-tqg144-2 blk_mem_40K_exdes 34 | 35 | echo 'Running map' 36 | map blk_mem_40K_exdes -o mapped.ncd -pr i 37 | 38 | echo 'Running par' 39 | par mapped.ncd routed.ncd 40 | 41 | echo 'Running trce' 42 | trce -e 10 routed.ncd mapped.pcf -o routed 43 | 44 | echo 'Running design through bitgen' 45 | bitgen -w routed 46 | 47 | echo 'Running netgen to create gate level VHDL model' 48 | netgen -ofmt vhdl -sim -tm blk_mem_40K_exdes -pcf mapped.pcf -w routed.ncd routed.vhd 49 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/blk_mem_40K_exdes.vhd 2 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent blk_mem_40K_exdes 4 | -p xc6slx9-tqg144-2 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn blk_mem_40K_exdes 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/simulation/functional/simulate_mti.bat: -------------------------------------------------------------------------------- 1 | #-------------------------------------------------------------------------------- 2 | 3 | vsim -c -do simulate_mti.do 4 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/simulation/functional/simulate_mti.sh: -------------------------------------------------------------------------------- 1 | #-------------------------------------------------------------------------------- 2 | 3 | vsim -c -do simulate_mti.do 4 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/simulation/functional/ucli_commands.key: -------------------------------------------------------------------------------- 1 | dump -file bmg_vcs.vpd -type VPD 2 | dump -add blk_mem_40K_tb 3 | run 4 | quit 5 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/simulation/functional/wave_mti.do: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | onerror {resume} 10 | quietly WaveActivateNextPane {} 0 11 | 12 | add wave -noupdate /blk_mem_40K_tb/status 13 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/CLKA 14 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/ADDRA 15 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DINA 16 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/WEA 17 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DOUTA 18 | 19 | TreeUpdate [SetDefaultTree] 20 | WaveRestoreCursors {{Cursor 1} {0 ps} 0} 21 | configure wave -namecolwidth 197 22 | configure wave -valuecolwidth 106 23 | configure wave -justifyvalue left 24 | configure wave -signalnamewidth 1 25 | configure wave -snapdistance 10 26 | configure wave -datasetprefix 0 27 | configure wave -rowmargin 4 28 | configure wave -childrowmargin 2 29 | configure wave -gridoffset 0 30 | configure wave -gridperiod 1 31 | configure wave -griddelta 40 32 | configure wave -timeline 0 33 | configure wave -timelineunits ps 34 | update 35 | WaveRestoreZoom {0 ps} {9464063 ps} 36 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/simulation/functional/wave_ncsim.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | window new WaveWindow -name "Waves for BMG Example Design" 11 | waveform using "Waves for BMG Example Design" 12 | 13 | waveform add -signals /blk_mem_40K_tb/status 14 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/CLKA 15 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/ADDRA 16 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DINA 17 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/WEA 18 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DOUTA 19 | 20 | console submit -using simulator -wait no "run" 21 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/simulation/timing/simulate_mti.bat: -------------------------------------------------------------------------------- 1 | #-------------------------------------------------------------------------------- 2 | 3 | vsim -c -do simulate_mti.do 4 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/simulation/timing/simulate_mti.sh: -------------------------------------------------------------------------------- 1 | #-------------------------------------------------------------------------------- 2 | 3 | vsim -c -do simulate_mti.do 4 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- 1 | dump -file bmg_vcs.vpd -type VPD 2 | dump -add blk_mem_40K_tb 3 | run 4 | quit 5 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/simulation/timing/wave_mti.do: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | onerror {resume} 10 | quietly WaveActivateNextPane {} 0 11 | 12 | 13 | add wave -noupdate /blk_mem_40K_tb/status 14 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/CLKA 15 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/ADDRA 16 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DINA 17 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/WEA 18 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DOUTA 19 | TreeUpdate [SetDefaultTree] 20 | WaveRestoreCursors {{Cursor 1} {0 ps} 0} 21 | configure wave -namecolwidth 150 22 | configure wave -valuecolwidth 100 23 | configure wave -justifyvalue left 24 | configure wave -signalnamewidth 1 25 | configure wave -snapdistance 10 26 | configure wave -datasetprefix 0 27 | configure wave -rowmargin 4 28 | configure wave -childrowmargin 2 29 | configure wave -gridoffset 0 30 | configure wave -gridperiod 1 31 | configure wave -griddelta 40 32 | configure wave -timeline 0 33 | configure wave -timelineunits ps 34 | update 35 | WaveRestoreZoom {0 ps} {9464063 ps} 36 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/blk_mem_40K/simulation/timing/wave_ncsim.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | window new WaveWindow -name "Waves for BMG Example Design" 10 | waveform using "Waves for BMG Example Design" 11 | 12 | 13 | waveform add -signals /blk_mem_40K_tb/status 14 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/CLKA 15 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/ADDRA 16 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DINA 17 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/WEA 18 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DOUTA 19 | console submit -using simulator -wait no "run" 20 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clk32to40 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | 14 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2015-2-20T12:49:10 5 | 6 | 7 | 8 | clk32to40 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40/doc/pg065_clk_wiz.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/papilio2/ipcore_dir/clk32to40/doc/pg065_clk_wiz.pdf -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40/implement/xst.prj: -------------------------------------------------------------------------------- 1 | vhdl work ../../clk32to40.vhd 2 | vhdl work ../example_design/clk32to40_exdes.vhd 3 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt MIXED 3 | -top clk32to40_exdes 4 | -p xc6slx9-tqg144-2 5 | -ifn xst.prj 6 | -ofn clk32to40_exdes 7 | -keep_hierarchy soft 8 | -equivalent_register_removal no 9 | -max_fanout 65535 10 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40/simulation/functional/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clk32to40_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40/simulation/functional/ucli_commands.key: -------------------------------------------------------------------------------- 1 | call {$vcdpluson} 2 | call {$vcdplusmemon(clk32to40_tb.dut.counter)} 3 | run 4 | call {$vcdplusclose} 5 | quit 6 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40/simulation/functional/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | gui_sg_create clk32to40_group 3 | gui_list_add_group -id Wave.1 {clk32to40_group} 4 | gui_sg_addsignal -group clk32to40_group {clk32to40_tb.test_phase} 5 | gui_set_radix -radix {ascii} -signals {clk32to40_tb.test_phase} 6 | gui_sg_addsignal -group clk32to40_group {{Input_clocks}} -divider 7 | gui_sg_addsignal -group clk32to40_group {clk32to40_tb.CLK_IN1} 8 | gui_sg_addsignal -group clk32to40_group {{Output_clocks}} -divider 9 | gui_sg_addsignal -group clk32to40_group {clk32to40_tb.dut.clk} 10 | gui_list_expand -id Wave.1 clk32to40_tb.dut.clk 11 | gui_sg_addsignal -group clk32to40_group {{Counters}} -divider 12 | gui_sg_addsignal -group clk32to40_group {clk32to40_tb.COUNT} 13 | gui_sg_addsignal -group clk32to40_group {clk32to40_tb.dut.counter} 14 | gui_list_expand -id Wave.1 clk32to40_tb.dut.counter 15 | gui_zoom -window Wave.1 -full 16 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40/simulation/timing/sdf_cmd_file: -------------------------------------------------------------------------------- 1 | COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", 2 | SCOPE = :dut; 3 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40/simulation/timing/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clk32to40_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | 10 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- 1 | 2 | run 50000ns 3 | quit 4 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/clk32to40_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | clk32to40.asy 4 | clk32to40.gise 5 | clk32to40.sym 6 | clk32to40.ucf 7 | clk32to40.vhd 8 | clk32to40.vho 9 | clk32to40.xco 10 | clk32to40.xdc 11 | clk32to40.xise 12 | clk32to40\clk_wiz_v3_6_readme.txt 13 | clk32to40\doc\clk_wiz_v3_6_readme.txt 14 | clk32to40\doc\clk_wiz_v3_6_vinfo.html 15 | clk32to40\doc\pg065_clk_wiz.pdf 16 | clk32to40\example_design\clk32to40_exdes.ucf 17 | clk32to40\example_design\clk32to40_exdes.vhd 18 | clk32to40\example_design\clk32to40_exdes.xdc 19 | clk32to40\implement\implement.bat 20 | clk32to40\implement\implement.sh 21 | clk32to40\implement\planAhead_ise.bat 22 | clk32to40\implement\planAhead_ise.sh 23 | clk32to40\implement\planAhead_ise.tcl 24 | clk32to40\implement\planAhead_rdn.bat 25 | clk32to40\implement\planAhead_rdn.sh 26 | clk32to40\implement\planAhead_rdn.tcl 27 | clk32to40\implement\xst.prj 28 | clk32to40\implement\xst.scr 29 | clk32to40\simulation\clk32to40_tb.vhd 30 | clk32to40\simulation\functional\simcmds.tcl 31 | clk32to40\simulation\functional\simulate_isim.bat 32 | clk32to40\simulation\functional\simulate_isim.sh 33 | clk32to40\simulation\functional\simulate_mti.bat 34 | clk32to40\simulation\functional\simulate_mti.do 35 | clk32to40\simulation\functional\simulate_mti.sh 36 | clk32to40\simulation\functional\simulate_ncsim.sh 37 | clk32to40\simulation\functional\simulate_vcs.sh 38 | clk32to40\simulation\functional\wave.do 39 | clk32to40\simulation\functional\wave.sv 40 | clk32to40\simulation\timing\clk32to40_tb.vhd 41 | clk32to40\simulation\timing\sdf_cmd_file 42 | clk32to40\simulation\timing\simcmds.tcl 43 | clk32to40\simulation\timing\simulate_isim.sh 44 | clk32to40\simulation\timing\simulate_mti.bat 45 | clk32to40\simulation\timing\simulate_mti.do 46 | clk32to40\simulation\timing\simulate_mti.sh 47 | clk32to40\simulation\timing\simulate_ncsim.sh 48 | clk32to40\simulation\timing\simulate_vcs.sh 49 | clk32to40\simulation\timing\ucli_commands.key 50 | clk32to40\simulation\timing\vcs_session.tcl 51 | clk32to40\simulation\timing\wave.do 52 | clk32to40_flist.txt 53 | clk32to40_xmdf.tcl 54 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = VHDL 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -2 8 | SET verilogsim = false 9 | SET vhdlsim = true 10 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/create_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:7.3" "blk_mem_40K" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:7.3) generated by Project Navigator" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/create_clk32to40.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "clk32to40" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/edit_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "blk_mem_40K" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/gen_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator regen command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_regen "blk_mem_40K" xc6slx9-2tqg144 VHDL CURRENT ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator regen command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator regen command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator regen cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/summary.log: -------------------------------------------------------------------------------- 1 | 2 | User Configuration 3 | ------------------------------------- 4 | Algorithm : Minimum_Area 5 | Memory Type : Single_Port_RAM 6 | Port A Read Width : 8 7 | Port A Write Width : 8 8 | Memory Depth : 65536 9 | -------------------------------------------------------------- 10 | 11 | Block RAM resource(s) (9K BRAMs) : 0 12 | Block RAM resource(s) (18K BRAMs) : 32 13 | -------------------------------------------------------------- 14 | Clock A Frequency : 100 15 | Port A Enable Rate : 100 16 | Port A Write Rate : 50 17 | ---------------------------------------------------------- 18 | Estimated Power for IP : 12.681892 mW 19 | ---------------------------------------------------------- 20 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Parsing VHDL file "C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/papilio2/ipcore_dir/blk_mem_40K.vhd" into library work 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /papilio2/ipcore_dir/tmp/blk_mem_40K.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 blk_mem_40K 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[15:0] 8 | PINATTR Polarity IN 9 | LINE Wide 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName dina[7:0] 12 | PINATTR Polarity IN 13 | LINE Wide 0 208 32 208 14 | PIN 0 208 LEFT 36 15 | PINATTR PinName wea[0:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 272 32 272 18 | PIN 0 272 LEFT 36 19 | PINATTR PinName clka 20 | PINATTR Polarity IN 21 | LINE Wide 576 80 544 80 22 | PIN 576 80 RIGHT 36 23 | PINATTR PinName douta[7:0] 24 | PINATTR Polarity OUT 25 | 26 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K.ncf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/papilio2_drigmorn1/ipcore_dir/blk_mem_40K.ncf -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2015-2-20T13:17:11 5 | 6 | 7 | 8 | 9 | 10 | 11 | blk_mem_40K 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/doc/pg058-blk-mem-gen.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/papilio2_drigmorn1/ipcore_dir/blk_mem_40K/doc/pg058-blk-mem-gen.pdf -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/implement/implement.bat: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | rem Clean up the results directory 10 | rmdir /S /Q results 11 | mkdir results 12 | 13 | rem Synthesize the VHDL Wrapper Files 14 | 15 | 16 | echo 'Synthesizing example design with XST'; 17 | xst -ifn xst.scr 18 | copy blk_mem_40K_exdes.ngc .\results\ 19 | 20 | 21 | rem Copy the netlist generated by Coregen 22 | echo 'Copying files from the netlist directory to the results directory' 23 | copy ..\..\blk_mem_40K.ngc results\ 24 | 25 | 26 | rem Copy the constraints files generated by Coregen 27 | echo 'Copying files from constraints directory to results directory' 28 | copy ..\example_design\blk_mem_40K_exdes.ucf results\ 29 | 30 | cd results 31 | 32 | echo 'Running ngdbuild' 33 | ngdbuild -p xc6slx9-tqg144-2 blk_mem_40K_exdes 34 | 35 | echo 'Running map' 36 | map blk_mem_40K_exdes -o mapped.ncd -pr i 37 | 38 | echo 'Running par' 39 | par mapped.ncd routed.ncd 40 | 41 | echo 'Running trce' 42 | trce -e 10 routed.ncd mapped.pcf -o routed 43 | 44 | echo 'Running design through bitgen' 45 | bitgen -w routed 46 | 47 | echo 'Running netgen to create gate level VHDL model' 48 | netgen -ofmt vhdl -sim -tm blk_mem_40K_exdes -pcf mapped.pcf -w routed.ncd routed.vhd 49 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/implement/implement.sh: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | #!/bin/sh 10 | 11 | # Clean up the results directory 12 | rm -rf results 13 | mkdir results 14 | 15 | #Synthesize the Wrapper Files 16 | 17 | echo 'Synthesizing example design with XST'; 18 | xst -ifn xst.scr 19 | cp blk_mem_40K_exdes.ngc ./results/ 20 | 21 | 22 | # Copy the netlist generated by Coregen 23 | echo 'Copying files from the netlist directory to the results directory' 24 | cp ../../blk_mem_40K.ngc results/ 25 | 26 | # Copy the constraints files generated by Coregen 27 | echo 'Copying files from constraints directory to results directory' 28 | cp ../example_design/blk_mem_40K_exdes.ucf results/ 29 | 30 | cd results 31 | 32 | echo 'Running ngdbuild' 33 | ngdbuild -p xc6slx9-tqg144-2 blk_mem_40K_exdes 34 | 35 | echo 'Running map' 36 | map blk_mem_40K_exdes -o mapped.ncd -pr i 37 | 38 | echo 'Running par' 39 | par mapped.ncd routed.ncd 40 | 41 | echo 'Running trce' 42 | trce -e 10 routed.ncd mapped.pcf -o routed 43 | 44 | echo 'Running design through bitgen' 45 | bitgen -w routed 46 | 47 | echo 'Running netgen to create gate level VHDL model' 48 | netgen -ofmt vhdl -sim -tm blk_mem_40K_exdes -pcf mapped.pcf -w routed.ncd routed.vhd 49 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/blk_mem_40K_exdes.vhd 2 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent blk_mem_40K_exdes 4 | -p xc6slx9-tqg144-2 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn blk_mem_40K_exdes 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/functional/simulate_mti.bat: -------------------------------------------------------------------------------- 1 | #-------------------------------------------------------------------------------- 2 | 3 | vsim -c -do simulate_mti.do 4 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/functional/simulate_mti.sh: -------------------------------------------------------------------------------- 1 | #-------------------------------------------------------------------------------- 2 | 3 | vsim -c -do simulate_mti.do 4 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/functional/ucli_commands.key: -------------------------------------------------------------------------------- 1 | dump -file bmg_vcs.vpd -type VPD 2 | dump -add blk_mem_40K_tb 3 | run 4 | quit 5 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/functional/wave_mti.do: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | onerror {resume} 10 | quietly WaveActivateNextPane {} 0 11 | 12 | add wave -noupdate /blk_mem_40K_tb/status 13 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/CLKA 14 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/ADDRA 15 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DINA 16 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/WEA 17 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DOUTA 18 | 19 | TreeUpdate [SetDefaultTree] 20 | WaveRestoreCursors {{Cursor 1} {0 ps} 0} 21 | configure wave -namecolwidth 197 22 | configure wave -valuecolwidth 106 23 | configure wave -justifyvalue left 24 | configure wave -signalnamewidth 1 25 | configure wave -snapdistance 10 26 | configure wave -datasetprefix 0 27 | configure wave -rowmargin 4 28 | configure wave -childrowmargin 2 29 | configure wave -gridoffset 0 30 | configure wave -gridperiod 1 31 | configure wave -griddelta 40 32 | configure wave -timeline 0 33 | configure wave -timelineunits ps 34 | update 35 | WaveRestoreZoom {0 ps} {9464063 ps} 36 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/functional/wave_ncsim.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | window new WaveWindow -name "Waves for BMG Example Design" 11 | waveform using "Waves for BMG Example Design" 12 | 13 | waveform add -signals /blk_mem_40K_tb/status 14 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/CLKA 15 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/ADDRA 16 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DINA 17 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/WEA 18 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DOUTA 19 | 20 | console submit -using simulator -wait no "run" 21 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/timing/simulate_mti.bat: -------------------------------------------------------------------------------- 1 | #-------------------------------------------------------------------------------- 2 | 3 | vsim -c -do simulate_mti.do 4 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/timing/simulate_mti.sh: -------------------------------------------------------------------------------- 1 | #-------------------------------------------------------------------------------- 2 | 3 | vsim -c -do simulate_mti.do 4 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- 1 | dump -file bmg_vcs.vpd -type VPD 2 | dump -add blk_mem_40K_tb 3 | run 4 | quit 5 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/timing/wave_mti.do: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | onerror {resume} 10 | quietly WaveActivateNextPane {} 0 11 | 12 | 13 | add wave -noupdate /blk_mem_40K_tb/status 14 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/CLKA 15 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/ADDRA 16 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DINA 17 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/WEA 18 | add wave -noupdate /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DOUTA 19 | TreeUpdate [SetDefaultTree] 20 | WaveRestoreCursors {{Cursor 1} {0 ps} 0} 21 | configure wave -namecolwidth 150 22 | configure wave -valuecolwidth 100 23 | configure wave -justifyvalue left 24 | configure wave -signalnamewidth 1 25 | configure wave -snapdistance 10 26 | configure wave -datasetprefix 0 27 | configure wave -rowmargin 4 28 | configure wave -childrowmargin 2 29 | configure wave -gridoffset 0 30 | configure wave -gridperiod 1 31 | configure wave -griddelta 40 32 | configure wave -timeline 0 33 | configure wave -timelineunits ps 34 | update 35 | WaveRestoreZoom {0 ps} {9464063 ps} 36 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/timing/wave_ncsim.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | window new WaveWindow -name "Waves for BMG Example Design" 10 | waveform using "Waves for BMG Example Design" 11 | 12 | 13 | waveform add -signals /blk_mem_40K_tb/status 14 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/CLKA 15 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/ADDRA 16 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DINA 17 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/WEA 18 | waveform add -signals /blk_mem_40K_tb/blk_mem_40K_synth_inst/bmg_port/DOUTA 19 | console submit -using simulator -wait no "run" 20 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/blk_mem_40K_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs/pn_parser.xmsgs 3 | blk_mem_40K/blk_mem_gen_v7_3_readme.txt 4 | blk_mem_40K/doc/blk_mem_gen_v7_3_vinfo.html 5 | blk_mem_40K/doc/pg058-blk-mem-gen.pdf 6 | blk_mem_40K.asy 7 | blk_mem_40K.gise 8 | blk_mem_40K.mif 9 | blk_mem_40K.ngc 10 | blk_mem_40K.vhd 11 | blk_mem_40K.vho 12 | blk_mem_40K.xco 13 | blk_mem_40K.xise 14 | blk_mem_40K_flist.txt 15 | blk_mem_40K_xmdf.tcl 16 | summary.log 17 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clk32to40 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | 14 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2015-2-20T12:49:10 5 | 6 | 7 | 8 | clk32to40 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40/doc/pg065_clk_wiz.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/papilio2_drigmorn1/ipcore_dir/clk32to40/doc/pg065_clk_wiz.pdf -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40/implement/xst.prj: -------------------------------------------------------------------------------- 1 | vhdl work ../../clk32to40.vhd 2 | vhdl work ../example_design/clk32to40_exdes.vhd 3 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt MIXED 3 | -top clk32to40_exdes 4 | -p xc6slx9-tqg144-2 5 | -ifn xst.prj 6 | -ofn clk32to40_exdes 7 | -keep_hierarchy soft 8 | -equivalent_register_removal no 9 | -max_fanout 65535 10 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40/simulation/functional/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clk32to40_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40/simulation/functional/ucli_commands.key: -------------------------------------------------------------------------------- 1 | call {$vcdpluson} 2 | call {$vcdplusmemon(clk32to40_tb.dut.counter)} 3 | run 4 | call {$vcdplusclose} 5 | quit 6 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40/simulation/functional/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | gui_sg_create clk32to40_group 3 | gui_list_add_group -id Wave.1 {clk32to40_group} 4 | gui_sg_addsignal -group clk32to40_group {clk32to40_tb.test_phase} 5 | gui_set_radix -radix {ascii} -signals {clk32to40_tb.test_phase} 6 | gui_sg_addsignal -group clk32to40_group {{Input_clocks}} -divider 7 | gui_sg_addsignal -group clk32to40_group {clk32to40_tb.CLK_IN1} 8 | gui_sg_addsignal -group clk32to40_group {{Output_clocks}} -divider 9 | gui_sg_addsignal -group clk32to40_group {clk32to40_tb.dut.clk} 10 | gui_list_expand -id Wave.1 clk32to40_tb.dut.clk 11 | gui_sg_addsignal -group clk32to40_group {{Counters}} -divider 12 | gui_sg_addsignal -group clk32to40_group {clk32to40_tb.COUNT} 13 | gui_sg_addsignal -group clk32to40_group {clk32to40_tb.dut.counter} 14 | gui_list_expand -id Wave.1 clk32to40_tb.dut.counter 15 | gui_zoom -window Wave.1 -full 16 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40/simulation/timing/sdf_cmd_file: -------------------------------------------------------------------------------- 1 | COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", 2 | SCOPE = :dut; 3 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40/simulation/timing/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clk32to40_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | 10 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- 1 | 2 | run 50000ns 3 | quit 4 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/clk32to40_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | clk32to40.asy 4 | clk32to40.gise 5 | clk32to40.sym 6 | clk32to40.ucf 7 | clk32to40.vhd 8 | clk32to40.vho 9 | clk32to40.xco 10 | clk32to40.xdc 11 | clk32to40.xise 12 | clk32to40\clk_wiz_v3_6_readme.txt 13 | clk32to40\doc\clk_wiz_v3_6_readme.txt 14 | clk32to40\doc\clk_wiz_v3_6_vinfo.html 15 | clk32to40\doc\pg065_clk_wiz.pdf 16 | clk32to40\example_design\clk32to40_exdes.ucf 17 | clk32to40\example_design\clk32to40_exdes.vhd 18 | clk32to40\example_design\clk32to40_exdes.xdc 19 | clk32to40\implement\implement.bat 20 | clk32to40\implement\implement.sh 21 | clk32to40\implement\planAhead_ise.bat 22 | clk32to40\implement\planAhead_ise.sh 23 | clk32to40\implement\planAhead_ise.tcl 24 | clk32to40\implement\planAhead_rdn.bat 25 | clk32to40\implement\planAhead_rdn.sh 26 | clk32to40\implement\planAhead_rdn.tcl 27 | clk32to40\implement\xst.prj 28 | clk32to40\implement\xst.scr 29 | clk32to40\simulation\clk32to40_tb.vhd 30 | clk32to40\simulation\functional\simcmds.tcl 31 | clk32to40\simulation\functional\simulate_isim.bat 32 | clk32to40\simulation\functional\simulate_isim.sh 33 | clk32to40\simulation\functional\simulate_mti.bat 34 | clk32to40\simulation\functional\simulate_mti.do 35 | clk32to40\simulation\functional\simulate_mti.sh 36 | clk32to40\simulation\functional\simulate_ncsim.sh 37 | clk32to40\simulation\functional\simulate_vcs.sh 38 | clk32to40\simulation\functional\wave.do 39 | clk32to40\simulation\functional\wave.sv 40 | clk32to40\simulation\timing\clk32to40_tb.vhd 41 | clk32to40\simulation\timing\sdf_cmd_file 42 | clk32to40\simulation\timing\simcmds.tcl 43 | clk32to40\simulation\timing\simulate_isim.sh 44 | clk32to40\simulation\timing\simulate_mti.bat 45 | clk32to40\simulation\timing\simulate_mti.do 46 | clk32to40\simulation\timing\simulate_mti.sh 47 | clk32to40\simulation\timing\simulate_ncsim.sh 48 | clk32to40\simulation\timing\simulate_vcs.sh 49 | clk32to40\simulation\timing\ucli_commands.key 50 | clk32to40\simulation\timing\vcs_session.tcl 51 | clk32to40\simulation\timing\wave.do 52 | clk32to40_flist.txt 53 | clk32to40_xmdf.tcl 54 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = VHDL 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -2 8 | SET verilogsim = false 9 | SET vhdlsim = true 10 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/create_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:7.3" "blk_mem_40K" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:7.3) generated by Project Navigator" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/create_clk32to40.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "clk32to40" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/edit_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "blk_mem_40K" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2_drigmorn1/ipcore_dir/summary.log: -------------------------------------------------------------------------------- 1 | 2 | User Configuration 3 | ------------------------------------- 4 | Algorithm : Minimum_Area 5 | Memory Type : Single_Port_RAM 6 | Port A Read Width : 8 7 | Port A Write Width : 8 8 | Memory Depth : 65536 9 | -------------------------------------------------------------- 10 | 11 | Block RAM resource(s) (9K BRAMs) : 0 12 | Block RAM resource(s) (18K BRAMs) : 32 13 | -------------------------------------------------------------- 14 | Clock A Frequency : 100 15 | Port A Enable Rate : 100 16 | Port A Write Rate : 50 17 | ---------------------------------------------------------- 18 | Estimated Power for IP : 12.681892 mW 19 | ---------------------------------------------------------- 20 | -------------------------------------------------------------------------------- /papilio2_lcd/README.md: -------------------------------------------------------------------------------- 1 | # Papilio2 LCD 2 | 3 | This project builds upon work in the Drigmorn1 project and does the following: 4 | 5 | * Uses Papilio Duo 6 | * Uses LCD wing for Sharp LCD screens (3x6 bits colors) 7 | * Instantiates Open source 808x processor and a rudimentary VGA-like controller 8 | * The integrated MON88 monitor allows to alter the memory, such as the video memory 9 | * Currently, all text is white, but any of the 4096 available colors could be used. 10 | 11 | ![Papilio Duo + LCD wing on a Sharp LCD screen with 8088 inside](p2_8088_vga.jpg) 12 | 13 | ## Links 14 | 15 | * [Open source 808x IP](http://www.ht-lab.com/cpu86.htm) 16 | * [Papilio Duo](http://papilio.cc/index.php?n=Papilio.DUOStart) 17 | * [Papilio LCD wing (Sharp LCD screens)](https://www.logre.eu/wiki/Ecran_Sharp_LQ084V1DG21/en) 18 | * [Recreating ancient 8088 PC on FPGA (in french)](https://wiki.logre.eu/index.php/PC_8088_sur_FPGA) 19 | -------------------------------------------------------------------------------- /papilio2_lcd/ipcore_dir/blk_mem_40K.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 blk_mem_40K 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[15:0] 8 | PINATTR Polarity IN 9 | LINE Wide 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName dina[7:0] 12 | PINATTR Polarity IN 13 | LINE Wide 0 208 32 208 14 | PIN 0 208 LEFT 36 15 | PINATTR PinName wea[0:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 272 32 272 18 | PIN 0 272 LEFT 36 19 | PINATTR PinName clka 20 | PINATTR Polarity IN 21 | LINE Wide 0 432 32 432 22 | PIN 0 432 LEFT 36 23 | PINATTR PinName addrb[15:0] 24 | PINATTR Polarity IN 25 | LINE Wide 0 464 32 464 26 | PIN 0 464 LEFT 36 27 | PINATTR PinName dinb[7:0] 28 | PINATTR Polarity IN 29 | LINE Wide 0 560 32 560 30 | PIN 0 560 LEFT 36 31 | PINATTR PinName web[0:0] 32 | PINATTR Polarity IN 33 | LINE Normal 0 624 32 624 34 | PIN 0 624 LEFT 36 35 | PINATTR PinName clkb 36 | PINATTR Polarity IN 37 | LINE Wide 576 80 544 80 38 | PIN 576 80 RIGHT 36 39 | PINATTR PinName douta[7:0] 40 | PINATTR Polarity OUT 41 | LINE Wide 576 368 544 368 42 | PIN 576 368 RIGHT 36 43 | PINATTR PinName doutb[7:0] 44 | PINATTR Polarity OUT 45 | 46 | -------------------------------------------------------------------------------- /papilio2_lcd/ipcore_dir/blk_mem_40K.ncf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/papilio2_lcd/ipcore_dir/blk_mem_40K.ncf -------------------------------------------------------------------------------- /papilio2_lcd/ipcore_dir/blk_mem_40K.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2015-2-20T13:17:11 5 | 6 | 7 | 8 | 9 | 10 | 11 | blk_mem_40K 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /papilio2_lcd/ipcore_dir/blk_mem_40K_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs/pn_parser.xmsgs 3 | blk_mem_40K/blk_mem_gen_v7_3_readme.txt 4 | blk_mem_40K/doc/blk_mem_gen_v7_3_vinfo.html 5 | blk_mem_40K/doc/pg058-blk-mem-gen.pdf 6 | blk_mem_40K/example_design/blk_mem_40K_exdes.ucf 7 | blk_mem_40K/example_design/blk_mem_40K_exdes.vhd 8 | blk_mem_40K/example_design/blk_mem_40K_exdes.xdc 9 | blk_mem_40K/example_design/blk_mem_40K_prod.vhd 10 | blk_mem_40K/implement/implement.bat 11 | blk_mem_40K/implement/implement.sh 12 | blk_mem_40K/implement/planAhead_ise.bat 13 | blk_mem_40K/implement/planAhead_ise.sh 14 | blk_mem_40K/implement/planAhead_ise.tcl 15 | blk_mem_40K/implement/xst.prj 16 | blk_mem_40K/implement/xst.scr 17 | blk_mem_40K/simulation/addr_gen.vhd 18 | blk_mem_40K/simulation/blk_mem_40K_synth.vhd 19 | blk_mem_40K/simulation/blk_mem_40K_tb.vhd 20 | blk_mem_40K/simulation/bmg_stim_gen.vhd 21 | blk_mem_40K/simulation/bmg_tb_pkg.vhd 22 | blk_mem_40K/simulation/checker.vhd 23 | blk_mem_40K/simulation/data_gen.vhd 24 | blk_mem_40K/simulation/functional/simcmds.tcl 25 | blk_mem_40K/simulation/functional/simulate_isim.sh 26 | blk_mem_40K/simulation/functional/simulate_mti.bat 27 | blk_mem_40K/simulation/functional/simulate_mti.do 28 | blk_mem_40K/simulation/functional/simulate_mti.sh 29 | blk_mem_40K/simulation/functional/simulate_ncsim.sh 30 | blk_mem_40K/simulation/functional/simulate_vcs.sh 31 | blk_mem_40K/simulation/functional/ucli_commands.key 32 | blk_mem_40K/simulation/functional/vcs_session.tcl 33 | blk_mem_40K/simulation/functional/wave_mti.do 34 | blk_mem_40K/simulation/functional/wave_ncsim.sv 35 | blk_mem_40K/simulation/random.vhd 36 | blk_mem_40K/simulation/timing/simcmds.tcl 37 | blk_mem_40K/simulation/timing/simulate_isim.sh 38 | blk_mem_40K/simulation/timing/simulate_mti.bat 39 | blk_mem_40K/simulation/timing/simulate_mti.do 40 | blk_mem_40K/simulation/timing/simulate_mti.sh 41 | blk_mem_40K/simulation/timing/simulate_ncsim.sh 42 | blk_mem_40K/simulation/timing/simulate_vcs.sh 43 | blk_mem_40K/simulation/timing/ucli_commands.key 44 | blk_mem_40K/simulation/timing/vcs_session.tcl 45 | blk_mem_40K/simulation/timing/wave_mti.do 46 | blk_mem_40K/simulation/timing/wave_ncsim.sv 47 | blk_mem_40K.asy 48 | blk_mem_40K.gise 49 | blk_mem_40K.mif 50 | blk_mem_40K.ngc 51 | blk_mem_40K.vhd 52 | blk_mem_40K.vho 53 | blk_mem_40K.xco 54 | blk_mem_40K.xise 55 | blk_mem_40K_flist.txt 56 | blk_mem_40K_xmdf.tcl 57 | summary.log 58 | -------------------------------------------------------------------------------- /papilio2_lcd/ipcore_dir/clk32to40.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clk32to40 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | 14 | -------------------------------------------------------------------------------- /papilio2_lcd/ipcore_dir/clk32to40.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2015-2-20T12:49:10 5 | 6 | 7 | 8 | clk32to40 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /papilio2_lcd/ipcore_dir/clk32to40_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | clk32to40.asy 4 | clk32to40.gise 5 | clk32to40.sym 6 | clk32to40.ucf 7 | clk32to40.vhd 8 | clk32to40.vho 9 | clk32to40.xco 10 | clk32to40.xdc 11 | clk32to40.xise 12 | clk32to40\clk_wiz_v3_6_readme.txt 13 | clk32to40\doc\clk_wiz_v3_6_readme.txt 14 | clk32to40\doc\clk_wiz_v3_6_vinfo.html 15 | clk32to40\doc\pg065_clk_wiz.pdf 16 | clk32to40\example_design\clk32to40_exdes.ucf 17 | clk32to40\example_design\clk32to40_exdes.vhd 18 | clk32to40\example_design\clk32to40_exdes.xdc 19 | clk32to40\implement\implement.bat 20 | clk32to40\implement\implement.sh 21 | clk32to40\implement\planAhead_ise.bat 22 | clk32to40\implement\planAhead_ise.sh 23 | clk32to40\implement\planAhead_ise.tcl 24 | clk32to40\implement\planAhead_rdn.bat 25 | clk32to40\implement\planAhead_rdn.sh 26 | clk32to40\implement\planAhead_rdn.tcl 27 | clk32to40\implement\xst.prj 28 | clk32to40\implement\xst.scr 29 | clk32to40\simulation\clk32to40_tb.vhd 30 | clk32to40\simulation\functional\simcmds.tcl 31 | clk32to40\simulation\functional\simulate_isim.bat 32 | clk32to40\simulation\functional\simulate_isim.sh 33 | clk32to40\simulation\functional\simulate_mti.bat 34 | clk32to40\simulation\functional\simulate_mti.do 35 | clk32to40\simulation\functional\simulate_mti.sh 36 | clk32to40\simulation\functional\simulate_ncsim.sh 37 | clk32to40\simulation\functional\simulate_vcs.sh 38 | clk32to40\simulation\functional\wave.do 39 | clk32to40\simulation\functional\wave.sv 40 | clk32to40\simulation\timing\clk32to40_tb.vhd 41 | clk32to40\simulation\timing\sdf_cmd_file 42 | clk32to40\simulation\timing\simcmds.tcl 43 | clk32to40\simulation\timing\simulate_isim.sh 44 | clk32to40\simulation\timing\simulate_mti.bat 45 | clk32to40\simulation\timing\simulate_mti.do 46 | clk32to40\simulation\timing\simulate_mti.sh 47 | clk32to40\simulation\timing\simulate_ncsim.sh 48 | clk32to40\simulation\timing\simulate_vcs.sh 49 | clk32to40\simulation\timing\ucli_commands.key 50 | clk32to40\simulation\timing\vcs_session.tcl 51 | clk32to40\simulation\timing\wave.do 52 | clk32to40_flist.txt 53 | clk32to40_xmdf.tcl 54 | -------------------------------------------------------------------------------- /papilio2_lcd/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = VHDL 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -2 8 | SET verilogsim = false 9 | SET vhdlsim = true 10 | -------------------------------------------------------------------------------- /papilio2_lcd/ipcore_dir/create_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:7.3" "blk_mem_40K" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:7.3) generated by Project Navigator" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2_lcd/ipcore_dir/create_clk32to40.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "clk32to40" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2_lcd/ipcore_dir/edit_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "blk_mem_40K" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2_lcd/p2_8088_vga.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/papilio2_lcd/p2_8088_vga.jpg -------------------------------------------------------------------------------- /papilio2_lcd/slib_clock_div.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Clock divider (clock enable generator) 3 | -- 4 | -- Author: Sebastian Witt 5 | -- Date: 27.01.2008 6 | -- Version: 1.1 7 | -- 8 | -- This code is free software; you can redistribute it and/or 9 | -- modify it under the terms of the GNU Lesser General Public 10 | -- License as published by the Free Software Foundation; either 11 | -- version 2.1 of the License, or (at your option) any later version. 12 | -- 13 | -- This code is distributed in the hope that it will be useful, 14 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 | -- Lesser General Public License for more details. 17 | -- 18 | -- You should have received a copy of the GNU Lesser General Public 19 | -- License along with this library; if not, write to the 20 | -- Free Software Foundation, Inc., 59 Temple Place, Suite 330, 21 | -- Boston, MA 02111-1307 USA 22 | -- 23 | 24 | LIBRARY IEEE; 25 | USE IEEE.std_logic_1164.all; 26 | USE IEEE.numeric_std.all; 27 | 28 | 29 | entity slib_clock_div is 30 | generic ( 31 | RATIO : integer := 4 -- Clock divider ratio 32 | ); 33 | port ( 34 | CLK : in std_logic; -- Clock 35 | RST : in std_logic; -- Reset 36 | CE : in std_logic; -- Clock enable input 37 | Q : out std_logic -- New clock enable output 38 | ); 39 | end slib_clock_div; 40 | 41 | architecture rtl of slib_clock_div is 42 | -- Signals 43 | signal iQ : std_logic; -- Internal Q 44 | signal iCounter : integer range 0 to RATIO-1; -- Counter 45 | 46 | begin 47 | -- Main process 48 | CD_PROC: process (RST, CLK) 49 | begin 50 | if (RST = '1') then 51 | iCounter <= 0; 52 | iQ <= '0'; 53 | elsif (CLK'event and CLK='1') then 54 | iQ <= '0'; 55 | if (CE = '1') then 56 | if (iCounter = (RATIO-1)) then 57 | iQ <= '1'; 58 | iCounter <= 0; 59 | else 60 | iCounter <= iCounter + 1; 61 | end if; 62 | end if; 63 | end if; 64 | end process; 65 | 66 | -- Output signals 67 | Q <= iQ; 68 | 69 | end rtl; 70 | 71 | -------------------------------------------------------------------------------- /papilio2_lcd/slib_edge_detect.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Signal edge detect 3 | -- 4 | -- Author: Sebastian Witt 5 | -- Data: 27.01.2008 6 | -- Version: 1.1 7 | -- 8 | -- This code is free software; you can redistribute it and/or 9 | -- modify it under the terms of the GNU Lesser General Public 10 | -- License as published by the Free Software Foundation; either 11 | -- version 2.1 of the License, or (at your option) any later version. 12 | -- 13 | -- This code is distributed in the hope that it will be useful, 14 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 | -- Lesser General Public License for more details. 17 | -- 18 | -- You should have received a copy of the GNU Lesser General Public 19 | -- License along with this library; if not, write to the 20 | -- Free Software Foundation, Inc., 59 Temple Place, Suite 330, 21 | -- Boston, MA 02111-1307 USA 22 | -- 23 | 24 | LIBRARY IEEE; 25 | USE IEEE.std_logic_1164.all; 26 | USE IEEE.numeric_std.all; 27 | 28 | entity slib_edge_detect is 29 | port ( 30 | CLK : in std_logic; -- Clock 31 | RST : in std_logic; -- Reset 32 | D : in std_logic; -- Signal input 33 | RE : out std_logic; -- Rising edge detected 34 | FE : out std_logic -- Falling edge detected 35 | ); 36 | end slib_edge_detect; 37 | 38 | architecture rtl of slib_edge_detect is 39 | signal iDd : std_logic; -- D register 40 | begin 41 | -- Store D 42 | ED_D: process (RST, CLK) 43 | begin 44 | if (RST = '1') then 45 | iDd <= '0'; 46 | elsif (CLK'event and CLK='1') then 47 | iDd <= D; 48 | end if; 49 | end process; 50 | 51 | -- Output ports 52 | RE <= '1' when iDd = '0' and D = '1' else '0'; 53 | FE <= '1' when iDd = '1' and D = '0' else '0'; 54 | 55 | end rtl; 56 | 57 | 58 | -------------------------------------------------------------------------------- /papilio2_lcd/slib_input_filter.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Input filter 3 | -- 4 | -- Author: Sebastian Witt 5 | -- Data: 06.03.2008 6 | -- Version: 1.0 7 | -- 8 | -- This code is free software; you can redistribute it and/or 9 | -- modify it under the terms of the GNU Lesser General Public 10 | -- License as published by the Free Software Foundation; either 11 | -- version 2.1 of the License, or (at your option) any later version. 12 | -- 13 | -- This code is distributed in the hope that it will be useful, 14 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 | -- Lesser General Public License for more details. 17 | -- 18 | -- You should have received a copy of the GNU Lesser General Public 19 | -- License along with this library; if not, write to the 20 | -- Free Software Foundation, Inc., 59 Temple Place, Suite 330, 21 | -- Boston, MA 02111-1307 USA 22 | -- 23 | 24 | LIBRARY IEEE; 25 | USE IEEE.std_logic_1164.all; 26 | USE IEEE.numeric_std.all; 27 | 28 | entity slib_input_filter is 29 | generic ( 30 | SIZE : natural := 4 -- Filter counter size 31 | ); 32 | port ( 33 | CLK : in std_logic; -- Clock 34 | RST : in std_logic; -- Reset 35 | CE : in std_logic; -- Clock enable 36 | D : in std_logic; -- Signal input 37 | Q : out std_logic -- Signal output 38 | ); 39 | end slib_input_filter; 40 | 41 | architecture rtl of slib_input_filter is 42 | signal iCount : integer range 0 to SIZE; 43 | begin 44 | IF_D: process (RST, CLK) 45 | begin 46 | if (RST = '1') then 47 | iCount <= 0; 48 | Q <= '0'; 49 | elsif (CLK'event and CLK='1') then 50 | -- Input counter 51 | if (CE = '1' ) then 52 | if (D = '1' and iCount /= SIZE) then 53 | iCount <= iCount + 1; 54 | elsif (D = '0' and iCount /= 0) then 55 | iCount <= iCount - 1; 56 | end if; 57 | end if; 58 | 59 | -- Output 60 | if (iCount = SIZE) then 61 | Q <= '1'; 62 | elsif (iCount = 0) then 63 | Q <= '0'; 64 | end if; 65 | end if; 66 | end process; 67 | 68 | end rtl; 69 | 70 | -------------------------------------------------------------------------------- /papilio2_lcd/slib_input_sync.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Input synchronization 3 | -- 4 | -- Author: Sebastian Witt 5 | -- Data: 27.01.2008 6 | -- Version: 1.0 7 | -- 8 | -- This code is free software; you can redistribute it and/or 9 | -- modify it under the terms of the GNU Lesser General Public 10 | -- License as published by the Free Software Foundation; either 11 | -- version 2.1 of the License, or (at your option) any later version. 12 | -- 13 | -- This code is distributed in the hope that it will be useful, 14 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 | -- Lesser General Public License for more details. 17 | -- 18 | -- You should have received a copy of the GNU Lesser General Public 19 | -- License along with this library; if not, write to the 20 | -- Free Software Foundation, Inc., 59 Temple Place, Suite 330, 21 | -- Boston, MA 02111-1307 USA 22 | -- 23 | 24 | LIBRARY IEEE; 25 | USE IEEE.std_logic_1164.all; 26 | USE IEEE.numeric_std.all; 27 | 28 | entity slib_input_sync is 29 | port ( 30 | CLK : in std_logic; -- Clock 31 | RST : in std_logic; -- Reset 32 | D : in std_logic; -- Signal input 33 | Q : out std_logic -- Signal output 34 | ); 35 | end slib_input_sync; 36 | 37 | architecture rtl of slib_input_sync is 38 | signal iD : std_logic_vector(1 downto 0); 39 | begin 40 | IS_D: process (RST, CLK) 41 | begin 42 | if (RST = '1') then 43 | iD <= (others => '0'); 44 | elsif (CLK'event and CLK='1') then 45 | iD(0) <= D; 46 | iD(1) <= iD(0); 47 | end if; 48 | end process; 49 | 50 | -- Output ports 51 | Q <= iD(1); 52 | 53 | end rtl; 54 | 55 | -------------------------------------------------------------------------------- /papilio2_lcd/vga_sync.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Copyright 2011, Kevin Lindsey 3 | -- See LICENSE file for licensing information 4 | -- 5 | -- Based on code from P. P. Chu, "FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version", 2008 6 | -- Chapters 12-13 7 | -- 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 11 | use ieee.numeric_std.all; 12 | 13 | entity vga_sync is 14 | port( 15 | clock: in std_logic; 16 | reset: in std_logic; 17 | hsync, vsync: out std_logic; 18 | video_on: out std_logic; 19 | pixel_tick: out std_logic; 20 | pixel_x, pixel_y: out std_logic_vector(9 downto 0) 21 | ); 22 | end vga_sync; 23 | 24 | architecture arch of vga_sync is 25 | signal h_sync_reg, v_sync_reg, video_on_reg: std_logic := '0'; 26 | signal v_count_reg: std_logic_vector(9 downto 0); 27 | signal h_count_reg: std_logic_vector(9 downto 0); 28 | -- VGA 640x480 29 | constant thp : integer := 6; -- hsync 156 30 | constant htotal : integer := 850; -- screen size, with back porch 900 31 | constant tvp : integer := 34; -- vsync 1 32 | constant vtotal : integer := 560; -- screen size, with back porch 560 33 | 34 | begin 35 | -- registers 36 | process(clock) 37 | begin 38 | if rising_edge(clock) then 39 | video_on_reg <= '1'; 40 | if h_count_reg < (thp) then 41 | h_sync_reg <= '0'; 42 | video_on_reg <= '0'; 43 | else 44 | h_sync_reg <= '1'; 45 | end if; 46 | if v_count_reg < tvp then 47 | v_sync_reg <= '0'; 48 | video_on_reg <= '0'; 49 | else 50 | v_sync_reg <= '1'; 51 | end if; 52 | if h_count_reg = htotal then 53 | h_count_reg <= (others => '0'); 54 | if v_count_reg = vtotal then 55 | v_count_reg <= (others => '0'); 56 | else 57 | v_count_reg <= v_count_reg + 1; 58 | end if; 59 | else 60 | h_count_reg <= h_count_reg + 1; 61 | end if; 62 | end if; 63 | end process; 64 | 65 | 66 | -- video on/off 67 | -- video_on <= h_sync_reg and v_sync_reg; 68 | video_on <= video_on_reg; 69 | 70 | -- output signals 71 | hsync <= h_sync_reg; 72 | vsync <= v_sync_reg; 73 | pixel_x <= std_logic_vector(h_count_reg)-thp-104; 74 | pixel_y <= std_logic_vector(v_count_reg)-tvp; 75 | -- pixel_tick <= p_tick; 76 | end arch; 77 | -------------------------------------------------------------------------------- /papilio2_vga/ipcore_dir/blk_mem_40K.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 blk_mem_40K 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[15:0] 8 | PINATTR Polarity IN 9 | LINE Wide 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName dina[7:0] 12 | PINATTR Polarity IN 13 | LINE Wide 0 208 32 208 14 | PIN 0 208 LEFT 36 15 | PINATTR PinName wea[0:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 272 32 272 18 | PIN 0 272 LEFT 36 19 | PINATTR PinName clka 20 | PINATTR Polarity IN 21 | LINE Wide 0 432 32 432 22 | PIN 0 432 LEFT 36 23 | PINATTR PinName addrb[15:0] 24 | PINATTR Polarity IN 25 | LINE Wide 0 464 32 464 26 | PIN 0 464 LEFT 36 27 | PINATTR PinName dinb[7:0] 28 | PINATTR Polarity IN 29 | LINE Wide 0 560 32 560 30 | PIN 0 560 LEFT 36 31 | PINATTR PinName web[0:0] 32 | PINATTR Polarity IN 33 | LINE Normal 0 624 32 624 34 | PIN 0 624 LEFT 36 35 | PINATTR PinName clkb 36 | PINATTR Polarity IN 37 | LINE Wide 576 80 544 80 38 | PIN 576 80 RIGHT 36 39 | PINATTR PinName douta[7:0] 40 | PINATTR Polarity OUT 41 | LINE Wide 576 368 544 368 42 | PIN 576 368 RIGHT 36 43 | PINATTR PinName doutb[7:0] 44 | PINATTR Polarity OUT 45 | 46 | -------------------------------------------------------------------------------- /papilio2_vga/ipcore_dir/blk_mem_40K.ncf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nsauzede/cpu86/2f77646c7964f2da55c872cdfd33ec94ad82dd01/papilio2_vga/ipcore_dir/blk_mem_40K.ncf -------------------------------------------------------------------------------- /papilio2_vga/ipcore_dir/blk_mem_40K.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2015-2-20T13:17:11 5 | 6 | 7 | 8 | 9 | 10 | 11 | blk_mem_40K 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /papilio2_vga/ipcore_dir/blk_mem_40K_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs/pn_parser.xmsgs 3 | blk_mem_40K/blk_mem_gen_v7_3_readme.txt 4 | blk_mem_40K/doc/blk_mem_gen_v7_3_vinfo.html 5 | blk_mem_40K/doc/pg058-blk-mem-gen.pdf 6 | blk_mem_40K/example_design/blk_mem_40K_exdes.ucf 7 | blk_mem_40K/example_design/blk_mem_40K_exdes.vhd 8 | blk_mem_40K/example_design/blk_mem_40K_exdes.xdc 9 | blk_mem_40K/example_design/blk_mem_40K_prod.vhd 10 | blk_mem_40K/implement/implement.bat 11 | blk_mem_40K/implement/implement.sh 12 | blk_mem_40K/implement/planAhead_ise.bat 13 | blk_mem_40K/implement/planAhead_ise.sh 14 | blk_mem_40K/implement/planAhead_ise.tcl 15 | blk_mem_40K/implement/xst.prj 16 | blk_mem_40K/implement/xst.scr 17 | blk_mem_40K/simulation/addr_gen.vhd 18 | blk_mem_40K/simulation/blk_mem_40K_synth.vhd 19 | blk_mem_40K/simulation/blk_mem_40K_tb.vhd 20 | blk_mem_40K/simulation/bmg_stim_gen.vhd 21 | blk_mem_40K/simulation/bmg_tb_pkg.vhd 22 | blk_mem_40K/simulation/checker.vhd 23 | blk_mem_40K/simulation/data_gen.vhd 24 | blk_mem_40K/simulation/functional/simcmds.tcl 25 | blk_mem_40K/simulation/functional/simulate_isim.sh 26 | blk_mem_40K/simulation/functional/simulate_mti.bat 27 | blk_mem_40K/simulation/functional/simulate_mti.do 28 | blk_mem_40K/simulation/functional/simulate_mti.sh 29 | blk_mem_40K/simulation/functional/simulate_ncsim.sh 30 | blk_mem_40K/simulation/functional/simulate_vcs.sh 31 | blk_mem_40K/simulation/functional/ucli_commands.key 32 | blk_mem_40K/simulation/functional/vcs_session.tcl 33 | blk_mem_40K/simulation/functional/wave_mti.do 34 | blk_mem_40K/simulation/functional/wave_ncsim.sv 35 | blk_mem_40K/simulation/random.vhd 36 | blk_mem_40K/simulation/timing/simcmds.tcl 37 | blk_mem_40K/simulation/timing/simulate_isim.sh 38 | blk_mem_40K/simulation/timing/simulate_mti.bat 39 | blk_mem_40K/simulation/timing/simulate_mti.do 40 | blk_mem_40K/simulation/timing/simulate_mti.sh 41 | blk_mem_40K/simulation/timing/simulate_ncsim.sh 42 | blk_mem_40K/simulation/timing/simulate_vcs.sh 43 | blk_mem_40K/simulation/timing/ucli_commands.key 44 | blk_mem_40K/simulation/timing/vcs_session.tcl 45 | blk_mem_40K/simulation/timing/wave_mti.do 46 | blk_mem_40K/simulation/timing/wave_ncsim.sv 47 | blk_mem_40K.asy 48 | blk_mem_40K.gise 49 | blk_mem_40K.mif 50 | blk_mem_40K.ngc 51 | blk_mem_40K.vhd 52 | blk_mem_40K.vho 53 | blk_mem_40K.xco 54 | blk_mem_40K.xise 55 | blk_mem_40K_flist.txt 56 | blk_mem_40K_xmdf.tcl 57 | summary.log 58 | -------------------------------------------------------------------------------- /papilio2_vga/ipcore_dir/clk32to40.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clk32to40 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | LINE Normal 608 176 576 176 14 | PIN 608 176 RIGHT 36 15 | PINATTR PinName clk_out2 16 | PINATTR Polarity OUT 17 | 18 | -------------------------------------------------------------------------------- /papilio2_vga/ipcore_dir/clk32to40.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2015-2-20T12:49:10 5 | 6 | 7 | 8 | clk32to40 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /papilio2_vga/ipcore_dir/clk32to40_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs/pn_parser.xmsgs 3 | clk32to40/clk_wiz_v3_6_readme.txt 4 | clk32to40/doc/clk_wiz_v3_6_readme.txt 5 | clk32to40/doc/clk_wiz_v3_6_vinfo.html 6 | clk32to40/doc/pg065_clk_wiz.pdf 7 | clk32to40/example_design/clk32to40_exdes.ucf 8 | clk32to40/example_design/clk32to40_exdes.vhd 9 | clk32to40/example_design/clk32to40_exdes.xdc 10 | clk32to40/implement/implement.bat 11 | clk32to40/implement/implement.sh 12 | clk32to40/implement/planAhead_ise.bat 13 | clk32to40/implement/planAhead_ise.sh 14 | clk32to40/implement/planAhead_ise.tcl 15 | clk32to40/implement/planAhead_rdn.bat 16 | clk32to40/implement/planAhead_rdn.sh 17 | clk32to40/implement/planAhead_rdn.tcl 18 | clk32to40/implement/xst.prj 19 | clk32to40/implement/xst.scr 20 | clk32to40/simulation/clk32to40_tb.vhd 21 | clk32to40/simulation/functional/simcmds.tcl 22 | clk32to40/simulation/functional/simulate_isim.bat 23 | clk32to40/simulation/functional/simulate_isim.sh 24 | clk32to40/simulation/functional/simulate_mti.bat 25 | clk32to40/simulation/functional/simulate_mti.do 26 | clk32to40/simulation/functional/simulate_mti.sh 27 | clk32to40/simulation/functional/simulate_ncsim.sh 28 | clk32to40/simulation/functional/simulate_vcs.sh 29 | clk32to40/simulation/functional/wave.do 30 | clk32to40/simulation/functional/wave.sv 31 | clk32to40/simulation/timing/clk32to40_tb.vhd 32 | clk32to40/simulation/timing/sdf_cmd_file 33 | clk32to40/simulation/timing/simcmds.tcl 34 | clk32to40/simulation/timing/simulate_isim.sh 35 | clk32to40/simulation/timing/simulate_mti.bat 36 | clk32to40/simulation/timing/simulate_mti.do 37 | clk32to40/simulation/timing/simulate_mti.sh 38 | clk32to40/simulation/timing/simulate_ncsim.sh 39 | clk32to40/simulation/timing/simulate_vcs.sh 40 | clk32to40/simulation/timing/ucli_commands.key 41 | clk32to40/simulation/timing/vcs_session.tcl 42 | clk32to40/simulation/timing/wave.do 43 | clk32to40.asy 44 | clk32to40.gise 45 | clk32to40.ucf 46 | clk32to40.vhd 47 | clk32to40.vho 48 | clk32to40.xco 49 | clk32to40.xdc 50 | clk32to40.xise 51 | clk32to40_flist.txt 52 | clk32to40_xmdf.tcl 53 | -------------------------------------------------------------------------------- /papilio2_vga/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | # Date: Sun May 14 11:22:52 2017 2 | 3 | SET addpads = false 4 | SET asysymbol = false 5 | SET busformat = BusFormatAngleBracketNotRipped 6 | SET createndf = false 7 | SET designentry = VHDL 8 | SET device = xc6slx9 9 | SET devicefamily = spartan6 10 | SET flowvendor = Other 11 | SET formalverification = false 12 | SET foundationsym = false 13 | SET implementationfiletype = Ngc 14 | SET package = tqg144 15 | SET removerpms = false 16 | SET simulationfiles = Behavioral 17 | SET speedgrade = -2 18 | SET verilogsim = false 19 | SET vhdlsim = true 20 | SET workingdirectory = ./tmp/ 21 | 22 | # CRC: 7315b7f3 23 | -------------------------------------------------------------------------------- /papilio2_vga/ipcore_dir/create_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:7.3" "blk_mem_40K" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:7.3) generated by Project Navigator" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2_vga/ipcore_dir/create_clk32to40.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "clk32to40" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2_vga/ipcore_dir/edit_blk_mem_40K.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "blk_mem_40K" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /papilio2_vga/ipcore_dir/edit_clk32to40.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "clk32to40" xc6slx9-2tqg144 VHDL ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /readme.txt: -------------------------------------------------------------------------------- 1 | CPU86 - Free VHDL CPU8088 IP core 2 | Copyright (C) 2005-2010 HT-LAB 3 | 4 | Quick run: 5 | 6 | 1) Open a DOSBox/Cygwin shell 7 | 2) Navigate to the web_cpu88/Modelsim directory. 8 | 3) Execute run.bat 9 | 10 | See website for more details. 11 | 12 | The CPU86 core is released under the GNU GPL license. For more information read the copying.txt 13 | file located in this directory. 14 | 15 | Bugs/Feedback: http://www.ht-lab.com/misc/feedback.html 16 | 17 | Version 0.83 Added ghdl script created by Lubomir Rintel 18 | Version 0.82 RCR REG,CL with CF set not always produced the right result. 19 | Version 0.81, Fixed CALL [REG] instruction, under certain circumstances the segment register was not set to use CS. 20 | Version 0.80, Full design release under GNU GPL. Fixed "LES SI,[xx]" instruction. 21 | Version 0.75, Ported some HTL8086 fixes back to the CPU86. 22 | Version 0.70, Fixed trace interrupt, split design into smaller files, added opencores UART. 23 | Version 0.69, Fixed INTR logic and SHL instruction as reported by Rick Kilgore 24 | Version 0.69, Added INTA/RDN fix from Rick Kilgore 25 | Version 0.68, Fixed INTA vector. The vector is read during the second interrupt acknowledge cycle, in version 0.67 26 | the vector was always 0. 27 | 28 | Good Luck, 29 | Hans. 30 | www.ht-lab.com 31 | 32 | 33 | -------------------------------------------------------------------------------- /top_rtl/readme.txt: -------------------------------------------------------------------------------- 1 | This directory contains the SIMULATION top level which instantiates the CPU86, bootstrap ROM + the opencores UART. --------------------------------------------------------------------------------