├── .gitignore ├── Readme.md ├── projects ├── iom.watch ├── lmb_ref │ └── lmb_ref.cbp ├── modbus_multi_test │ └── modbus_multi_test.cbp ├── nuc-242-rte │ └── nuc-242-rte.cbp ├── nuc-243-rte │ └── nuc-243-rte.cbp ├── nuc-247-0-rte │ └── nuc-247-0-rte.cbp ├── nuc-247-1-rte │ └── nuc-247-1-rte.cbp ├── yaplc-runtime │ └── yaplc-runtime.cbp └── yaplc.workspace └── src ├── COPYING.GPL3 ├── COPYING.LGPL3 ├── License.txt ├── bsp ├── common │ ├── plc_mbm.c │ ├── plc_mbm_ng.c │ ├── plc_mbs.c │ ├── plc_mbs_bak.c │ ├── plc_mbs_test.c │ ├── plc_tick.c │ └── stm32 │ │ ├── f1 │ │ ├── fmb_port │ │ │ ├── port.h │ │ │ ├── portevent.c │ │ │ ├── portother.c │ │ │ ├── portserial.c │ │ │ └── porttimer.c │ │ ├── libremodbus_port │ │ │ ├── portevent.c │ │ │ ├── portother.c │ │ │ ├── portserial.c │ │ │ ├── porttimer.c │ │ │ ├── serial_multi.h │ │ │ ├── serial_port.h │ │ │ └── tcp_port.h │ │ ├── mbconfig.h │ │ ├── plc_backup.c │ │ ├── plc_clock.c │ │ ├── plc_gpio.c │ │ ├── plc_isr_stubs.c │ │ ├── plc_rtc.c │ │ └── plc_serial.c │ │ ├── f2 │ │ ├── ADC │ │ │ ├── adc.c │ │ │ ├── adc.h │ │ │ └── adc_common_v1.c │ │ ├── fmb_port │ │ │ ├── port.h │ │ │ ├── portevent.c │ │ │ ├── portother.c │ │ │ ├── portserial.c │ │ │ └── porttimer.c │ │ ├── libremodbus_port │ │ │ ├── serial_multi.h │ │ │ ├── serial_port.c │ │ │ ├── serial_port.h │ │ │ ├── serial_portevent.c │ │ │ ├── serial_portother.c │ │ │ ├── serial_porttimer.c │ │ │ └── user_mb_app.h │ │ ├── plc_backup.c │ │ ├── plc_clock.c │ │ ├── plc_gpio.c │ │ ├── plc_isr_stubs.c │ │ ├── plc_rtc.c │ │ └── plc_serial.c │ │ ├── f4 │ │ ├── plc_backup.c │ │ ├── plc_clock.c │ │ ├── plc_gpio.c │ │ ├── plc_isr_stubs.c │ │ ├── plc_rtc.c │ │ └── plc_serial.c │ │ ├── plc_diag.c │ │ ├── plc_gpio.h │ │ ├── plc_hmi.bak.c │ │ ├── plc_hmi.c │ │ ├── plc_hmi.h │ │ └── plc_wait_tmr.c ├── nuc-227-dev │ ├── plc_backup.c │ ├── plc_clock.c │ ├── plc_config.h │ ├── plc_config_bak.h │ ├── plc_hw.c │ ├── plc_rtc.c │ ├── plc_serial.c │ ├── plc_tick.c │ ├── plc_wait_tmr.c │ ├── stm32f4disco-app.ld │ ├── stm32f4disco-dev.ld │ └── stm32f4disco-rte.ld ├── nuc-242 │ ├── plc_config.h │ ├── plc_hmi.c │ ├── plc_hw.c │ ├── plc_iom_reg.c │ ├── plc_isr_stubs.c │ ├── stm32f103xC-app.ld │ ├── stm32f103xC-dev.ld │ └── stm32f103xC-rte.ld ├── nuc-243 │ ├── mbconfig.h │ ├── plc_ain.c │ ├── plc_ain.h │ ├── plc_aout.c │ ├── plc_aout.h │ ├── plc_config.h │ ├── plc_hmi_sys.c │ ├── plc_hw.c │ ├── plc_iom_reg.c │ ├── plc_isr_stubs.c │ ├── plc_mbs.c │ ├── plc_mbs_bak.c │ ├── plc_wait_tmr.c │ ├── stm32f205xC-app.ld │ └── stm32f205xC-rte.ld ├── nuc-247-0 │ ├── mbconfig.h │ ├── plc_config.h │ ├── plc_hmi_sys.c │ ├── plc_hw.c │ ├── plc_iom_reg.c │ ├── plc_tick.c │ ├── plc_wait_tmr.c │ ├── stm32f205xC-app.ld │ └── stm32f205xC-rte.ld ├── nuc-247-1 │ ├── mbconfig.h │ ├── plc_config.h │ ├── plc_hmi_sys.c │ ├── plc_hw.c │ ├── plc_iom_reg.c │ ├── plc_isr_stubs.c │ ├── plc_wait_tmr.c │ ├── stm32f205xC-app.ld │ └── stm32f205xC-rte.ld ├── stm32f4 │ ├── plc_backup.c │ ├── plc_clock.c │ ├── plc_config.h │ ├── plc_config_bak.h │ ├── plc_hw.c │ ├── plc_rtc.c │ ├── plc_serial.c │ ├── plc_tick.c │ ├── plc_wait_tmr.c │ ├── stm32f4disco-app.ld │ ├── stm32f4disco-dev.ld │ └── stm32f4disco-rte.ld └── template │ ├── Readme.md │ ├── example-app.ld │ ├── example-rte.ld │ ├── plc_backup.c │ ├── plc_clock.c │ ├── plc_config.h │ ├── plc_driver_template.c │ ├── plc_hw.c │ ├── plc_iom_reg.c │ ├── plc_rtc.c │ ├── plc_serial.c │ ├── plc_tick.c │ └── plc_wait_tmr.c ├── dbnc_flt.c ├── dbnc_flt.h ├── frac_div.c ├── frac_div.h ├── main.c ├── noise_flt.c ├── noise_flt.h ├── plc_abi.h ├── plc_app_default.c ├── plc_app_default.h ├── plc_backup.h ├── plc_clock.h ├── plc_dbg.c ├── plc_dbg.h ├── plc_diag.h ├── plc_glue_dbg.c ├── plc_glue_dbg.h ├── plc_glue_rte.c ├── plc_hw.h ├── plc_iom.c ├── plc_iom.h ├── plc_ioproto_template.c ├── plc_libc.c ├── plc_rtc.h ├── plc_tick.h ├── plc_wait_tmr.h ├── xprintf.c └── xprintf.h /.gitignore: -------------------------------------------------------------------------------- 1 | # Compiled Object files # 2 | ######################### 3 | *.slo 4 | *.lo 5 | *.o 6 | *.obj 7 | 8 | # Precompiled Headers # 9 | ####################### 10 | *.gch 11 | *.pch 12 | 13 | # Compiled Dynamic libraries # 14 | ############################## 15 | *.so 16 | *.dylib 17 | *.dll 18 | 19 | # Fortran module files # 20 | ######################## 21 | *.mod 22 | 23 | # Compiled Static libraries # 24 | ############################# 25 | *.lai 26 | *.la 27 | *.a 28 | *.lib 29 | 30 | # Executables # 31 | ############### 32 | *.exe 33 | *.out 34 | *.app 35 | *.elf 36 | *.hex 37 | 38 | # IDE/Toolchain generated # 39 | ########################### 40 | *.save 41 | *.map 42 | *.lss 43 | *.d 44 | *.depend 45 | *.layout 46 | *.cscope_file_list 47 | *obj* 48 | *bin* 49 | 50 | # Something else # 51 | ################## 52 | *.py[ocd] 53 | *.rej 54 | 55 | # Backup files # 56 | ################ 57 | *~ 58 | *.orig 59 | *.swp 60 | 61 | # Directory files # 62 | ################### 63 | *directory 64 | 65 | # Docs # 66 | ######## 67 | doc/doxygen/html/** 68 | 69 | 70 | 71 | # Specific files # 72 | ################## 73 | 74 | # Makefiles # 75 | ############# 76 | #Makefile 77 | 78 | 79 | -------------------------------------------------------------------------------- /Readme.md: -------------------------------------------------------------------------------- 1 | # YAPLC/RTE 2 | This is YAPLC runtime environment project. 3 | 4 | YAPLC/RTE can run user aplications made with YAPLC/IDE. 5 | It runs on bare metal without any OS. 6 | It is small and portable. 7 | 8 | # Contributors 9 | * Paul Beltyukov aka [@shkolnick-kun](https://github.com/shkolnick-kun), 10 | * Radeon Ww , 11 | * Sergey Ovchinnikov , 12 | * Michael Volkov . 13 | 14 | # Using stm32f4-discovery board 15 | Target "yaplc" can be used to build and upload aplication to the board. 16 | 17 | If you want to run it, then folow these steps: 18 | 1. Build yaplc-runtime project and load it to the board (I do it with 19 | st-util on debug session start, I think OpenOCD may also be used). 20 | 2. Create a project with "yaplc" target, 21 | 3. build it, 22 | 4. connect to your target (see 23 | https://github.com/nucleron/RTE/blob/master/src/bsp/nuc-227-dev/plc_config.h#L27 24 | for details) 25 | 5. and transfer aplication. 26 | 6. Now you can program your discovery board with YAPLC/IDE. 27 | 28 | And yes, to use YAPLC/IDE with stock discovery you should connect Boot0 and 29 | VDD pins with jumper just before pressing "Transfer PLC" button in 30 | YAPLC/IDE. 31 | 32 | When aplication has been loaded - disconnect Boot0 from VDD. 33 | 34 | Or alternatively, you can add "mosfet with memory capasitor" circuit switch 35 | Boot0 automatically (see 36 | https://github.com/nucleron/RTE/blob/master/src/bsp/nuc-227-dev/plc_hw.c#L54 37 | and 38 | https://github.com/nucleron/RTE/blob/master/src/bsp/nuc-227-dev/plc_config.h#L44 39 | for details) 40 | -------------------------------------------------------------------------------- /projects/iom.watch: -------------------------------------------------------------------------------- 1 | ((plc_app_abi_t *)0x08008000)->l_tab 2 | ((plc_app_abi_t *)0x08008000)->w_tab 3 | plc_iom 4 | -------------------------------------------------------------------------------- /projects/yaplc.workspace: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /src/License.txt: -------------------------------------------------------------------------------- 1 | Yet Another Public License (YAPL) 2 | version 1.0, November 14th 2016 3 | 4 | The covered work is licensed under the folowing terms: 5 | 6 | 1. If used with hardware produced by the copyright holder, 7 | then the covered work is licensed under the terms of LGPLv3 or later. 8 | 9 | 2. If used with hardware produced by other persons or companies 10 | which have written permission from the copyright holder to convey 11 | the covered work and its combinations under the terms of LGPLv3 or later, 12 | then the covered work is licensed under the terms of LGPLv3 or later. 13 | 14 | 3. In all other cases the covered work is licensed under the terms 15 | of GPLv3 or later. 16 | 17 | 4. You can find GPLv3 and LGPLv3 in files COPYING.GPL3 and COPYING.LGPL3 18 | respectively in this directory. 19 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/fmb_port/port.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: BARE Port 3 | * Copyright (C) 2006 Christian Walter 4 | * 5 | * This library is free software; you can redistribute it and/or 6 | * modify it under the terms of the GNU Lesser General Public 7 | * License as published by the Free Software Foundation; either 8 | * version 2.1 of the License, or (at your option) any later version. 9 | * 10 | * This library is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * Lesser General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU Lesser General Public 16 | * License along with this library; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | * 19 | * File: $Id: port.h,v 1.1 2006/08/22 21:35:13 wolti Exp $ 20 | */ 21 | 22 | #ifndef _PORT_H 23 | #define _PORT_H 24 | 25 | #include 26 | #include 27 | 28 | #define INLINE inline 29 | #define PR_BEGIN_EXTERN_C extern "C" { 30 | #define PR_END_EXTERN_C } 31 | 32 | #define ENTER_CRITICAL_SECTION( ) vMBPortEnterCritical() 33 | #define EXIT_CRITICAL_SECTION( ) vMBPortExitCritical() 34 | 35 | typedef uint8_t BOOL; 36 | 37 | typedef unsigned char UCHAR; 38 | typedef char CHAR; 39 | 40 | typedef uint16_t USHORT; 41 | typedef int16_t SHORT; 42 | 43 | typedef uint32_t ULONG; 44 | typedef int32_t LONG; 45 | 46 | #ifndef TRUE 47 | #define TRUE 1 48 | #endif 49 | 50 | #ifndef FALSE 51 | #define FALSE 0 52 | #endif 53 | 54 | #define MB_PORT_HAS_CLOSE 1 55 | #define MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS 0 56 | 57 | /* ----------------------- Prototypes ---------------------------------------*/ 58 | void vMBPortEnterCritical( void ); 59 | void vMBPortExitCritical( void ); 60 | 61 | #endif 62 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/fmb_port/portevent.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: BARE Port 3 | * Copyright (C) 2006 Christian Walter 4 | * 5 | * This library is free software; you can redistribute it and/or 6 | * modify it under the terms of the GNU Lesser General Public 7 | * License as published by the Free Software Foundation; either 8 | * version 2.1 of the License, or (at your option) any later version. 9 | * 10 | * This library is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * Lesser General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU Lesser General Public 16 | * License along with this library; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | * 19 | * File: $Id: portevent.c,v 1.1 2006/08/22 21:35:13 wolti Exp $ 20 | */ 21 | 22 | /* ----------------------- Modbus includes ----------------------------------*/ 23 | #include 24 | #include 25 | 26 | /* ----------------------- Variables ----------------------------------------*/ 27 | static eMBEventType queued_evt; 28 | static BOOL evt_in_queue; 29 | 30 | /* ----------------------- Start implementation -----------------------------*/ 31 | BOOL 32 | xMBPortEventInit( void ) 33 | { 34 | evt_in_queue = FALSE; 35 | return TRUE; 36 | } 37 | 38 | BOOL 39 | xMBPortEventPost( eMBEventType eEvent ) 40 | { 41 | evt_in_queue = TRUE; 42 | queued_evt = eEvent; 43 | return TRUE; 44 | } 45 | 46 | BOOL 47 | xMBPortEventGet( eMBEventType * eEvent ) 48 | { 49 | BOOL xEventHappened = FALSE; 50 | 51 | if( evt_in_queue ) 52 | { 53 | *eEvent = queued_evt; 54 | evt_in_queue = FALSE; 55 | xEventHappened = TRUE; 56 | } 57 | return xEventHappened; 58 | } 59 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/fmb_port/portother.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: Atmel AT91SAM3S Demo Application 3 | * Copyright (C) 2010 Christian Walter 4 | * 5 | * 6 | * Redistribution and use in source and binary forms, with or without 7 | * modification, are permitted provided that the following conditions 8 | * are met: 9 | * 1. Redistributions of source code must retain the above copyright 10 | * notice, this list of conditions and the following disclaimer. 11 | * 2. Redistributions in binary form must reproduce the above copyright 12 | * notice, this list of conditions and the following disclaimer in the 13 | * documentation and/or other materials provided with the distribution. 14 | * 3. The name of the author may not be used to endorse or promote products 15 | * derived from this software without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 | * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * File: $Id: portother.c,v 1.1 2010/06/05 09:57:48 wolti Exp $ 29 | */ 30 | 31 | /* ----------------------- Modbus includes ----------------------------------*/ 32 | #include "mb.h" 33 | #include "mbport.h" 34 | 35 | /* ----------------------- Static variables ---------------------------------*/ 36 | static UCHAR xOriginalState; 37 | static ULONG ulNesting; 38 | 39 | /* ----------------------- Cortex-M3 PRIMASK enable/disable -----------------*/ 40 | /* Gregory Nutt */ 41 | 42 | /* Get/set the primask register to control global DI/EI*/ 43 | 44 | static inline uint8_t getprimask(void) 45 | { 46 | uint32_t primask; 47 | __asm__ __volatile__("\tmrs %0, primask\n" : "=r" (primask) : : "memory"); 48 | return (uint8_t)primask; 49 | } 50 | 51 | static inline void setprimask(uint32_t primask) 52 | { 53 | __asm__ __volatile__("\tmsr primask, %0\n" : : "r" (primask) : "memory"); 54 | } 55 | /* ----------------------- Critical Section handler -----------------------------*/ 56 | /* Check if PRIMASK was set, and disable it on entry. On exit, if it was originally 57 | set then set it back again otherwise leave it unset. */ 58 | void 59 | vMBPortEnterCritical( void ) 60 | { 61 | if(ulNesting == 0) 62 | { 63 | xOriginalState = getprimask(); 64 | } 65 | ulNesting++; 66 | setprimask(1); 67 | } 68 | 69 | void 70 | vMBPortExitCritical( void ) 71 | { 72 | ulNesting--; 73 | if(ulNesting == 0) 74 | { 75 | setprimask(xOriginalState); 76 | } 77 | } 78 | 79 | /* ----------------------- Close Ports -----------------------------*/ 80 | void 81 | vMBPortClose( void ) 82 | { 83 | extern void vMBPortSerialClose( void ); 84 | extern void vMBPortTimersDisable( void ); 85 | vMBPortSerialClose( ); 86 | vMBPortTimersDisable( ); 87 | } 88 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/fmb_port/porttimer.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: BARE Port 3 | * Copyright (C) 2006 Christian Walter 4 | * 5 | * This library is free software; you can redistribute it and/or 6 | * modify it under the terms of the GNU Lesser General Public 7 | * License as published by the Free Software Foundation; either 8 | * version 2.1 of the License, or (at your option) any later version. 9 | * 10 | * This library is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * Lesser General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU Lesser General Public 16 | * License along with this library; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | * 19 | * File: $Id: porttimer.c,v 1.1 2006/08/22 21:35:13 wolti Exp $ 20 | */ 21 | 22 | /* ----------------------- Platform includes --------------------------------*/ 23 | #include "port.h" 24 | 25 | /* ----------------------- Modbus includes ----------------------------------*/ 26 | #include "mb.h" 27 | #include "mbport.h" 28 | 29 | /* ----------------------- libopencm3 STM32F includes -------------------------------*/ 30 | #include 31 | #include 32 | #include 33 | #include 34 | 35 | #include 36 | 37 | /* ----------------------- Initialize Timer -----------------------------*/ 38 | BOOL 39 | xMBPortTimersInit( USHORT usTim1Timerout50us ) 40 | { 41 | //rcc_periph_clock_enable( RCC_GPIOA ); 42 | //gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO1); 43 | //gpio_clear( GPIOA, GPIO1 ); 44 | 45 | /* Enable TIM clock. */ 46 | rcc_periph_clock_enable(MB_TMR_PERIPH); 47 | nvic_enable_irq (MB_TMR_VECTOR); 48 | timer_reset (MB_TMR); 49 | /* Timer global mode: - Divider 4, Alignment edge, Direction up */ 50 | timer_set_mode (MB_TMR, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); 51 | timer_continuous_mode(MB_TMR); 52 | timer_set_prescaler (MB_TMR, ((2*rcc_apb1_frequency)/20000ul - 1)); /* 50 microseconds period */ 53 | timer_set_period (MB_TMR, usTim1Timerout50us); 54 | return TRUE; 55 | } 56 | 57 | /* ----------------------- Enable Timer -----------------------------*/ 58 | inline void 59 | vMBPortTimersEnable( ) 60 | { 61 | /* Restart the timer with the period value set in xMBPortTimersInit( ) */ 62 | TIM_CNT(MB_TMR) = 1; /* Yes, this must be 1 !!! */ 63 | 64 | timer_enable_irq (MB_TMR, TIM_DIER_UIE); 65 | timer_enable_counter (MB_TMR); 66 | } 67 | 68 | /* ----------------------- Disable timer -----------------------------*/ 69 | inline void 70 | vMBPortTimersDisable( ) 71 | { 72 | timer_disable_irq (MB_TMR, TIM_DIER_UIE); 73 | timer_disable_counter(MB_TMR); 74 | } 75 | 76 | void vMBPortTimersDelay( USHORT usTimeOutMS ) 77 | { 78 | /*Not supproted*/ 79 | #if MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS > 0 80 | # error "MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS > 0 is not supported!!!" 81 | #endif 82 | } 83 | 84 | 85 | /* ----------------------- Timer ISR -----------------------------*/ 86 | /* Create an ISR which is called whenever the timer has expired. This function 87 | * must then call pxMBPortCBTimerExpired( ) to notify the protocol stack that 88 | * the timer has expired. 89 | */ 90 | static CHAR count; 91 | void MB_TMR_ISR(void) 92 | { 93 | count++; 94 | if (timer_interrupt_source(MB_TMR, TIM_SR_UIF)) 95 | { 96 | timer_clear_flag(MB_TMR, TIM_SR_UIF); /* Clear interrrupt flag. */ 97 | } 98 | timer_get_flag(MB_TMR, TIM_SR_UIF); /* Reread to force the previous (buffered) write before leaving */ 99 | pxMBPortCBTimerExpired(); 100 | } 101 | 102 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/libremodbus_port/portevent.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: BARE Port 3 | * Copyright (C) 2006 Christian Walter 4 | * 5 | * This library is free software; you can redistribute it and/or 6 | * modify it under the terms of the GNU Lesser General Public 7 | * License as published by the Free Software Foundation; either 8 | * version 2.1 of the License, or (at your option) any later version. 9 | * 10 | * This library is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * Lesser General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU Lesser General Public 16 | * License along with this library; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | * 19 | * File: $Id: portevent.c, v 1.1 2006/08/22 21:35:13 wolti Exp $ 20 | */ 21 | 22 | #include 23 | 24 | #define evt_in_queue inst->evt_in_queue 25 | #define queued_evt inst->queued_evt 26 | 27 | /* ----------------------- Start implementation -----------------------------*/ 28 | BOOL 29 | mb_port_ser_evt_init(mb_port_ser_struct* inst) 30 | { 31 | evt_in_queue = FALSE; 32 | return TRUE; 33 | } 34 | 35 | BOOL 36 | mb_port_ser_evt_post( mb_port_ser_struct* inst, mb_event_enum event) 37 | { 38 | evt_in_queue = TRUE; 39 | queued_evt = event; 40 | return TRUE; 41 | } 42 | 43 | BOOL 44 | mb_port_ser_evt_get(mb_port_ser_struct* inst, void* caller, mb_event_enum * event) 45 | { 46 | BOOL xEventHappened = FALSE; 47 | 48 | (void)caller; 49 | 50 | if (evt_in_queue) 51 | { 52 | *event = queued_evt; 53 | evt_in_queue = FALSE; 54 | xEventHappened = TRUE; 55 | } 56 | return xEventHappened; 57 | } 58 | 59 | 60 | /** 61 | * This function is wait for modbus master request finish and return result. 62 | * Waiting result include request process success, request respond timeout, 63 | * receive data error and execute function error.You can use the above callback function. 64 | * @note If you are use OS, you can use OS's event mechanism. Otherwise you have to run 65 | * much user custom delay for waiting. 66 | * 67 | * @return request error code 68 | */ 69 | mb_err_enum eMBRTUMasterWaitRequestFinish(void) { 70 | 71 | /* 72 | mb_err_enum eErrStatus = MB_ENOERR; 73 | // rt_uint32_t recvedEvent; 74 | //waiting for OS event 75 | rt_event_recv(&xMasterOsEvent, 76 | EV_MASTER_PROCESS_SUCESS | EV_MASTER_ERROR_RESPOND_TIMEOUT 77 | | EV_MASTER_ERROR_RECEIVE_DATA 78 | | EV_MASTER_ERROR_EXECUTE_FUNCTION, 79 | RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, 80 | &recvedEvent); 81 | switch (recvedEvent) 82 | { 83 | case EV_MASTER_PROCESS_SUCESS: 84 | break; 85 | case EV_MASTER_ERROR_RESPOND_TIMEOUT: 86 | { 87 | eErrStatus = MB_ETIMEDOUT; 88 | break; 89 | } 90 | case EV_MASTER_ERROR_RECEIVE_DATA: 91 | { 92 | eErrStatus = MB_ERCV; 93 | break; 94 | } 95 | case EV_MASTER_ERROR_EXECUTE_FUNCTION: 96 | { 97 | eErrStatus = MB_MRE_EXE_FUN; 98 | break; 99 | } 100 | } 101 | 102 | */ 103 | return 0;//eErrStatus; 104 | } 105 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/libremodbus_port/portother.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: Atmel AT91SAM3S Demo Application 3 | * Copyright (C) 2010 Christian Walter 4 | * 5 | * 6 | * Redistribution and use in source and binary forms, with or without 7 | * modification, are permitted provided that the following conditions 8 | * are met: 9 | * 1. Redistributions of source code must retain the above copyright 10 | * notice, this list of conditions and the following disclaimer. 11 | * 2. Redistributions in binary form must reproduce the above copyright 12 | * notice, this list of conditions and the following disclaimer in the 13 | * documentation and/or other materials provided with the distribution. 14 | * 3. The name of the author may not be used to endorse or promote products 15 | * derived from this software without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 | * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * File: $Id: portother.c, v 1.1 2010/06/05 09:57:48 wolti Exp $ 29 | */ 30 | 31 | /* ----------------------- Modbus includes ----------------------------------*/ 32 | #include 33 | 34 | /* ----------------------- Static variables ---------------------------------*/ 35 | static UCHAR xOriginalState; 36 | static ULONG ulNesting; 37 | 38 | /* ----------------------- Cortex-M3 PRIMASK enable/disable -----------------*/ 39 | /* Gregory Nutt */ 40 | 41 | /* Get/set the primask register to control global DI/EI*/ 42 | 43 | static inline uint8_t getprimask(void) 44 | { 45 | uint32_t primask; 46 | __asm__ __volatile__("\tmrs %0, primask\n" : "=r" (primask) : : "memory"); 47 | return (uint8_t)primask; 48 | } 49 | 50 | static inline void setprimask(uint32_t primask) 51 | { 52 | __asm__ __volatile__("\tmsr primask, %0\n" : : "r" (primask) : "memory"); 53 | } 54 | /* ----------------------- Critical Section handler -----------------------------*/ 55 | /* Check if PRIMASK was set, and disable it on entry. On exit, if it was originally 56 | set then set it back again otherwise leave it unset. */ 57 | void 58 | vMBPortEnterCritical(void) 59 | { 60 | if (ulNesting == 0) 61 | { 62 | xOriginalState = getprimask(); 63 | } 64 | ulNesting++; 65 | setprimask(1); 66 | } 67 | 68 | void 69 | vMBPortExitCritical(void) 70 | { 71 | ulNesting--; 72 | if (ulNesting == 0) 73 | { 74 | setprimask(xOriginalState); 75 | } 76 | } 77 | 78 | /* ----------------------- Close Ports -----------------------------*/ 79 | void 80 | mb_port_ser_close(mb_port_ser_struct* inst) 81 | { 82 | extern void vMBPortSerialClose(mb_port_ser_struct* inst); 83 | //extern void mb_port_ser_tmr_disable(mb_port_ser_struct* inst); 84 | vMBPortSerialClose(inst); 85 | mb_port_ser_tmr_disable(inst); 86 | } 87 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/libremodbus_port/porttimer.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: BARE Port 3 | * Copyright (C) 2006 Christian Walter 4 | * 5 | * This library is free software; you can redistribute it and/or 6 | * modify it under the terms of the GNU Lesser General Public 7 | * License as published by the Free Software Foundation; either 8 | * version 2.1 of the License, or (at your option) any later version. 9 | * 10 | * This library is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * Lesser General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU Lesser General Public 16 | * License along with this library; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | * 19 | * File: $Id: porttimer.c, v 1.1 2006/08/22 21:35:13 wolti Exp $ 20 | */ 21 | /* ----------------------- Platform includes --------------------------------*/ 22 | #include 23 | 24 | /* ----------------------- libopencm3 STM32F includes -------------------------------*/ 25 | #include 26 | #include 27 | #include 28 | #include 29 | 30 | /* ----------------------- Modbus includes ----------------------------------*/ 31 | #include 32 | 33 | #include 34 | 35 | /* ----------------------- Initialize Timer -----------------------------*/ 36 | BOOL 37 | mb_port_ser_tmr_init(mb_port_ser_struct* inst, USHORT usTim1Timerout50us) 38 | { 39 | //rcc_periph_clock_enable(RCC_GPIOA); 40 | //gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO1); 41 | //gpio_clear(GPIOA, GPIO1); 42 | if ((&mbs_inst_usart) != inst) 43 | { 44 | return false; 45 | } 46 | 47 | /* Enable TIM clock. */ 48 | rcc_periph_clock_enable(MB_TMR_PERIPH); 49 | nvic_enable_irq (MB_TMR_VECTOR); 50 | timer_reset (MB_TMR); 51 | /* Timer global mode: - Divider 4, Alignment edge, Direction up */ 52 | timer_set_mode (MB_TMR, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); 53 | timer_continuous_mode(MB_TMR); 54 | timer_set_prescaler (MB_TMR, ((2*rcc_apb1_frequency)/20000ul - 1)); /* 50 microseconds period */ 55 | timer_set_period (MB_TMR, usTim1Timerout50us); 56 | return TRUE; 57 | } 58 | 59 | /* ----------------------- Enable Timer -----------------------------*/ 60 | void 61 | mb_port_ser_tmr_enable(mb_port_ser_struct* inst) 62 | { 63 | if ((&mbs_inst_usart) != inst) 64 | { 65 | return; 66 | } 67 | /* Restart the timer with the period value set in mb_port_ser_tmr_init() */ 68 | TIM_CNT(MB_TMR) = 1; /* Yes, this must be 1 !!! */ 69 | 70 | timer_enable_irq (MB_TMR, TIM_DIER_UIE); 71 | timer_enable_counter (MB_TMR); 72 | } 73 | 74 | /* ----------------------- Disable timer -----------------------------*/ 75 | void 76 | mb_port_ser_tmr_disable(mb_port_ser_struct* inst) 77 | { 78 | if ((&mbs_inst_usart) != inst) 79 | { 80 | return; 81 | } 82 | timer_disable_irq (MB_TMR, TIM_DIER_UIE); 83 | timer_disable_counter(MB_TMR); 84 | } 85 | 86 | void mb_port_ser_tmr_delay(mb_port_ser_struct* inst, USHORT timeout_ms) 87 | { 88 | (void)inst; 89 | (void)timeout_ms; 90 | /*Not supproted*/ 91 | #if MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS > 0 92 | # error "MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS > 0 is not supported!!!" 93 | #endif 94 | } 95 | 96 | 97 | /* ----------------------- Timer ISR -----------------------------*/ 98 | /* Create an ISR which is called whenever the timer has expired. This function 99 | * must then call pxMBPortCBTimerExpired() to notify the protocol stack that 100 | * the timer has expired. 101 | */ 102 | static CHAR count; 103 | void MB_TMR_ISR(void) 104 | { 105 | count++; 106 | if (timer_interrupt_source(MB_TMR, TIM_SR_UIF)) 107 | { 108 | timer_clear_flag(MB_TMR, TIM_SR_UIF); /* Clear interrrupt flag. */ 109 | } 110 | timer_get_flag(MB_TMR, TIM_SR_UIF); /* Reread to force the previous (buffered) write before leaving */ 111 | mbs_inst_usart.base.cb->tmr_expired(mbs_inst_usart.base.arg); 112 | //pxMBPortCBTimerExpired(); 113 | } 114 | 115 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/libremodbus_port/serial_multi.h: -------------------------------------------------------------------------------- 1 | #ifndef SERIAL_MULTI_H 2 | #define SERIAL_MULTI_H 3 | 4 | #include 5 | #include 6 | 7 | 8 | #include 9 | #include 10 | 11 | #endif 12 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/libremodbus_port/serial_port.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: Win32 Port 3 | * Copyright (C) 2006 Christian Walter 4 | * 5 | * This library is free software; you can redistribute it and/or 6 | * modify it under the terms of the GNU Lesser General Public 7 | * License as published by the Free Software Foundation; either 8 | * version 2.1 of the License, or (at your option) any later version. 9 | * 10 | * This library is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * Lesser General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU Lesser General Public 16 | * License along with this library; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | * 19 | * File: $Id: port.h, v 1.5 2006/06/26 19:25:17 wolti Exp $ 20 | */ 21 | 22 | #ifndef _PORT_H 23 | #define _PORT_H 24 | #include "serial_multi.h" 25 | #include 26 | 27 | #include 28 | PR_BEGIN_EXTERN_C 29 | 30 | 31 | 32 | /* ----------------------- Defines ------------------------------------------*/ 33 | 34 | #define ENTER_CRITICAL_SECTION() 35 | #define EXIT_CRITICAL_SECTION() 36 | #define MB_PORT_HAS_CLOSE 1 37 | #ifndef TRUE 38 | #define TRUE 1 39 | #endif 40 | #ifndef FALSE 41 | #define FALSE 0 42 | #endif 43 | #if MB_ASCII_ENABLED == 1 44 | #define BUF_SIZE 513 /* must hold a complete ASCII frame. */ 45 | #else 46 | #define BUF_SIZE 256 /* must hold a complete RTU frame. */ 47 | #endif 48 | 49 | struct _mb_port_ser 50 | { 51 | mb_port_base_struct base; 52 | uint32_t uart_num; 53 | bool tx_en; 54 | 55 | //timer 56 | DWORD timeout; 57 | BOOL timeout_enable; 58 | DWORD time_last; 59 | 60 | DWORD deafault_timeout; 61 | 62 | //events 63 | mb_event_enum queued_evt; 64 | BOOL evt_in_queue; 65 | 66 | //void* parent; 67 | }; 68 | /* ----------------------- Type definitions ---------------------------------*/ 69 | 70 | typedef enum 71 | { 72 | MB_LOG_DEBUG, 73 | MB_LOG_INFO, 74 | MB_LOG_WARN, 75 | MB_LOG_ERROR 76 | } eMBPortLogLevel; 77 | 78 | /* ----------------------- Function prototypes ------------------------------*/ 79 | /* 80 | void vMBPortLog(eMBPortLogLevel eLevel, const TCHAR * szModule, 81 | const TCHAR * szFmt, ...);*/ 82 | void vMBPortTimerPoll (mb_port_ser_struct* inst, void* caller ); //FIXME 83 | BOOL xMBPortSerialPoll (mb_port_ser_struct* inst, void* caller ); //FIXME 84 | BOOL xMBPortSerialSetTimeout(mb_port_ser_struct* inst, DWORD dwTimeoutMs); 85 | 86 | 87 | extern mb_port_ser_struct mbs_inst_usart; 88 | extern mb_port_ser_struct mbm_inst_usart; 89 | 90 | PR_END_EXTERN_C 91 | #endif 92 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/libremodbus_port/tcp_port.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: BSD Socket Library Port 3 | * Copyright (C) 2006 Christian Walter 4 | * 5 | * This library is free software; you can redistribute it and/or 6 | * modify it under the terms of the GNU Lesser General Public 7 | * License as published by the Free Software Foundation; either 8 | * version 2.1 of the License, or (at your option) any later version. 9 | * 10 | * This library is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * Lesser General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU Lesser General Public 16 | * License along with this library; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | * 19 | * File: $Id: port.h,v 1.2 2006/06/26 19:24:07 wolti Exp $ 20 | */ 21 | 22 | #ifndef _PORT_H 23 | #define _PORT_H 24 | 25 | #define INLINE 26 | #define PR_BEGIN_EXTERN_C extern "C" { 27 | #define PR_END_EXTERN_C } 28 | 29 | #ifdef __cplusplus 30 | PR_BEGIN_EXTERN_C 31 | #endif 32 | 33 | /* ----------------------- Defines ------------------------------------------*/ 34 | 35 | #define ENTER_CRITICAL_SECTION( ) 36 | #define EXIT_CRITICAL_SECTION( ) 37 | #define MB_PORT_HAS_CLOSE 1 38 | #ifndef TRUE 39 | #define TRUE 1 40 | #endif 41 | #ifndef FALSE 42 | #define FALSE 0 43 | #endif 44 | 45 | /* ----------------------- Type definitions ---------------------------------*/ 46 | 47 | typedef enum 48 | { 49 | MB_LOG_DEBUG, 50 | MB_LOG_INFO, 51 | MB_LOG_WARN, 52 | MB_LOG_ERROR 53 | } eMBPortLogLevel; 54 | 55 | /* ----------------------- Function prototypes ------------------------------*/ 56 | 57 | /*void vMBPortLog( eMBPortLogLevel eLevel, const TCHAR * szModule, 58 | const TCHAR * szFmt, ... );*/ 59 | 60 | #ifdef __cplusplus 61 | PR_END_EXTERN_C 62 | #endif 63 | #endif 64 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/plc_backup.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | #include 13 | #include 14 | #include 15 | #include 16 | 17 | #include 18 | #include 19 | #include 20 | 21 | //Use RTC backup registers for validation 22 | #define PLC_BKP_VER_1 MMIO32(BACKUP_REGS_BASE + PLC_BKP_VER1_OFFSET) 23 | #define PLC_BKP_VER_2 MMIO32(BACKUP_REGS_BASE + PLC_BKP_VER2_OFFSET) 24 | #define PLC_BKP_START_1 (uint32_t *)(BACKUP_REGS_BASE + PLC_BKP_REG_OFFSET) 25 | #define PLC_BKP_START_2 (uint32_t *)(BACKUP_REGS_BASE + PLC_BKP_REG_OFFSET + PLC_BKP_REG_NUM) 26 | 27 | #define PLC_BKP_SIZE (PLC_BKP_REG_NUM*2ul) //Lower 16bits are used 28 | 29 | #define PLC_BKP_VER_MSK (0xFFFFFFFE) 30 | #define PLC_BKP_VLD_MSK (0x01) 31 | 32 | #define PLC_BKP_GET_VER(ver) ((ver) & PLC_BKP_VER_MSK) 33 | #define PLC_BKP_IS_VALID(ver) ((ver) & PLC_BKP_VLD_MSK) 34 | 35 | /*If true, then read from v1-bank, write to v2-bank, else do vice versa.*/ 36 | #define PLC_BKP_TEST_VER(v1, v2) (PLC_BKP_GET_VER(v1) != PLC_BKP_GET_VER(v2)) 37 | 38 | static uint16_t plc_backup_buff[PLC_BKP_REG_NUM]; 39 | static uint32_t * plc_backup_reg_1 = PLC_BKP_START_1; 40 | static uint32_t * plc_backup_reg_2 = PLC_BKP_START_2; 41 | 42 | void plc_backup_init(void) 43 | { 44 | rcc_periph_clock_enable(RCC_PWR); 45 | rcc_periph_clock_enable(RCC_BKP); 46 | } 47 | 48 | void plc_backup_reset(void) 49 | { 50 | pwr_disable_backup_domain_write_protect(); 51 | PLC_BKP_VER_1=0; 52 | PLC_BKP_VER_2=0; 53 | pwr_enable_backup_domain_write_protect(); 54 | } 55 | 56 | void plc_backup_invalidate(void) 57 | { 58 | //pwr_disable_backup_domain_write_protect(); 59 | //PLC_BKP_VER1++; 60 | //pwr_enable_backup_domain_write_protect(); 61 | } 62 | 63 | void plc_backup_validate(void) 64 | { 65 | uint32_t i; 66 | //Write bank 1 67 | pwr_disable_backup_domain_write_protect(); 68 | PLC_BKP_VER_1 &= PLC_BKP_VER_MSK; //Invalidate bank 69 | 70 | for(i = 0; i < PLC_BKP_REG_NUM; i++) 71 | { 72 | plc_backup_reg_1[i] = (uint32_t)plc_backup_buff[i]; 73 | } 74 | 75 | PLC_BKP_VER_1 += 3;//Validate bank 76 | pwr_enable_backup_domain_write_protect(); 77 | 78 | //Write bank 2 79 | pwr_disable_backup_domain_write_protect(); 80 | PLC_BKP_VER_2 &= PLC_BKP_VER_MSK; //Invalidate bank 81 | 82 | for(i = 0; i < PLC_BKP_REG_NUM; i++) 83 | { 84 | plc_backup_reg_2[i] = (uint32_t)plc_backup_buff[i]; 85 | } 86 | 87 | PLC_BKP_VER_2 += 3;//Validate bank 88 | pwr_enable_backup_domain_write_protect(); 89 | } 90 | 91 | int plc_backup_check(void) 92 | { 93 | uint32_t i; 94 | if (PLC_BKP_TEST_VER(PLC_BKP_VER_1, PLC_BKP_VER_2)) 95 | { 96 | if (PLC_BKP_IS_VALID(PLC_BKP_VER_1)) 97 | { 98 | for(i = 0; i < PLC_BKP_REG_NUM; i++) 99 | { 100 | plc_backup_buff[i] = (uint16_t)(plc_backup_reg_1[i]&0xffff); 101 | } 102 | return 1;//Success!!! 103 | } 104 | } 105 | else 106 | { 107 | if (PLC_BKP_IS_VALID(PLC_BKP_VER_2)) 108 | { 109 | for(i = 0; i < PLC_BKP_REG_NUM; i++) 110 | { 111 | plc_backup_buff[i] = (uint16_t)(plc_backup_reg_2[i]&0xffff); 112 | } 113 | return 1;//Success!!! 114 | } 115 | } 116 | return 0; //Fail! Use dafaults! 117 | } 118 | 119 | 120 | 121 | void plc_backup_remind(unsigned int offset, unsigned int count, void *p) 122 | { 123 | if (offset + count < PLC_BKP_SIZE) 124 | { 125 | memcpy(p, (void *)plc_backup_buff + offset, count); 126 | } 127 | } 128 | 129 | void plc_backup_retain(unsigned int offset, unsigned int count, void *p) 130 | { 131 | if (offset + count < PLC_BKP_SIZE) 132 | { 133 | //pwr_disable_backup_domain_write_protect(); 134 | memcpy((void *)plc_backup_buff + offset, p, count); 135 | //pwr_enable_backup_domain_write_protect(); 136 | } 137 | } 138 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/plc_gpio.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include 5 | #include 6 | 7 | #include 8 | 9 | //#pragma GCC optimize ("O0") 10 | 11 | void plc_gpio_cfg_in(const plc_gpio_t * self) 12 | { 13 | rcc_periph_clock_enable(self->periph); 14 | gpio_set_mode (self->port, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, self->pin); 15 | gpio_set (self->port, self->pin); 16 | } 17 | 18 | void plc_gpio_cfg_out(const plc_gpio_t * self) 19 | { 20 | rcc_periph_clock_enable(self->periph); 21 | gpio_set_mode (self->port, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, self->pin); 22 | gpio_clear (self->port, self->pin); 23 | } 24 | 25 | void plc_gpio_gr_cfg_in(const plc_gpio_t * group, uint8_t n) 26 | { 27 | if (n==0) 28 | { 29 | return; 30 | } 31 | while (n--) 32 | { 33 | plc_gpio_cfg_in(group++); 34 | } 35 | } 36 | 37 | void plc_gpio_gr_cfg_out(const plc_gpio_t * group, uint8_t n) 38 | { 39 | if (n==0) 40 | { 41 | return; 42 | } 43 | while (n--) 44 | { 45 | plc_gpio_cfg_out(group++); 46 | } 47 | } 48 | 49 | void plc_gpio_gr_set(const plc_gpio_t * group, uint8_t n) 50 | { 51 | if (n==0) 52 | { 53 | return; 54 | } 55 | while (n--) 56 | { 57 | plc_gpio_set(group++); 58 | } 59 | } 60 | 61 | void plc_gpio_gr_clear(const plc_gpio_t * group, uint8_t n) 62 | { 63 | if (n==0) 64 | { 65 | return; 66 | } 67 | while (n--) 68 | { 69 | plc_gpio_clear(group++); 70 | } 71 | } 72 | 73 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f1/plc_serial.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nucleron/RTE/65341e5029a33f35f32de1fa41ba0276b89680b9/src/bsp/common/stm32/f1/plc_serial.c -------------------------------------------------------------------------------- /src/bsp/common/stm32/f2/fmb_port/port.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: BARE Port 3 | * Copyright (C) 2006 Christian Walter 4 | * 5 | * This library is free software; you can redistribute it and/or 6 | * modify it under the terms of the GNU Lesser General Public 7 | * License as published by the Free Software Foundation; either 8 | * version 2.1 of the License, or (at your option) any later version. 9 | * 10 | * This library is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * Lesser General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU Lesser General Public 16 | * License along with this library; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | * 19 | * File: $Id: port.h,v 1.1 2006/08/22 21:35:13 wolti Exp $ 20 | */ 21 | 22 | #ifndef _PORT_H 23 | #define _PORT_H 24 | 25 | #include 26 | #include 27 | 28 | #define INLINE inline 29 | #define PR_BEGIN_EXTERN_C extern "C" { 30 | #define PR_END_EXTERN_C } 31 | 32 | #define ENTER_CRITICAL_SECTION( ) vMBPortEnterCritical() 33 | #define EXIT_CRITICAL_SECTION( ) vMBPortExitCritical() 34 | 35 | typedef uint8_t BOOL; 36 | 37 | typedef unsigned char UCHAR; 38 | typedef char CHAR; 39 | 40 | typedef uint16_t USHORT; 41 | typedef int16_t SHORT; 42 | 43 | typedef uint32_t ULONG; 44 | typedef int32_t LONG; 45 | 46 | #ifndef TRUE 47 | #define TRUE 1 48 | #endif 49 | 50 | #ifndef FALSE 51 | #define FALSE 0 52 | #endif 53 | 54 | #define MB_PORT_HAS_CLOSE 1 55 | #define MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS 0 56 | 57 | /* ----------------------- Prototypes ---------------------------------------*/ 58 | void vMBPortEnterCritical( void ); 59 | void vMBPortExitCritical( void ); 60 | 61 | #endif 62 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f2/fmb_port/portevent.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: BARE Port 3 | * Copyright (C) 2006 Christian Walter 4 | * 5 | * This library is free software; you can redistribute it and/or 6 | * modify it under the terms of the GNU Lesser General Public 7 | * License as published by the Free Software Foundation; either 8 | * version 2.1 of the License, or (at your option) any later version. 9 | * 10 | * This library is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * Lesser General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU Lesser General Public 16 | * License along with this library; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | * 19 | * File: $Id: portevent.c,v 1.1 2006/08/22 21:35:13 wolti Exp $ 20 | */ 21 | 22 | /* ----------------------- Modbus includes ----------------------------------*/ 23 | #include 24 | #include 25 | 26 | /* ----------------------- Variables ----------------------------------------*/ 27 | static eMBEventType eQueuedEvent; 28 | static BOOL xEventInQueue; 29 | 30 | /* ----------------------- Start implementation -----------------------------*/ 31 | BOOL 32 | xMBPortEventInit( void ) 33 | { 34 | xEventInQueue = FALSE; 35 | return TRUE; 36 | } 37 | 38 | BOOL 39 | xMBPortEventPost( eMBEventType eEvent ) 40 | { 41 | xEventInQueue = TRUE; 42 | eQueuedEvent = eEvent; 43 | return TRUE; 44 | } 45 | 46 | BOOL 47 | xMBPortEventGet( eMBEventType * eEvent ) 48 | { 49 | BOOL xEventHappened = FALSE; 50 | 51 | if( xEventInQueue ) 52 | { 53 | *eEvent = eQueuedEvent; 54 | xEventInQueue = FALSE; 55 | xEventHappened = TRUE; 56 | } 57 | return xEventHappened; 58 | } 59 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f2/fmb_port/portother.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: Atmel AT91SAM3S Demo Application 3 | * Copyright (C) 2010 Christian Walter 4 | * 5 | * 6 | * Redistribution and use in source and binary forms, with or without 7 | * modification, are permitted provided that the following conditions 8 | * are met: 9 | * 1. Redistributions of source code must retain the above copyright 10 | * notice, this list of conditions and the following disclaimer. 11 | * 2. Redistributions in binary form must reproduce the above copyright 12 | * notice, this list of conditions and the following disclaimer in the 13 | * documentation and/or other materials provided with the distribution. 14 | * 3. The name of the author may not be used to endorse or promote products 15 | * derived from this software without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 | * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * File: $Id: portother.c,v 1.1 2010/06/05 09:57:48 wolti Exp $ 29 | */ 30 | 31 | /* ----------------------- Modbus includes ----------------------------------*/ 32 | #include "mb.h" 33 | #include "mbport.h" 34 | 35 | /* ----------------------- Static variables ---------------------------------*/ 36 | static UCHAR xOriginalState; 37 | static ULONG ulNesting; 38 | 39 | /* ----------------------- Cortex-M3 PRIMASK enable/disable -----------------*/ 40 | /* Gregory Nutt */ 41 | 42 | /* Get/set the primask register to control global DI/EI*/ 43 | 44 | static inline uint8_t getprimask(void) 45 | { 46 | uint32_t primask; 47 | __asm__ __volatile__("\tmrs %0, primask\n" : "=r" (primask) : : "memory"); 48 | return (uint8_t)primask; 49 | } 50 | 51 | static inline void setprimask(uint32_t primask) 52 | { 53 | __asm__ __volatile__("\tmsr primask, %0\n" : : "r" (primask) : "memory"); 54 | } 55 | /* ----------------------- Critical Section handler -----------------------------*/ 56 | /* Check if PRIMASK was set, and disable it on entry. On exit, if it was originally 57 | set then set it back again otherwise leave it unset. */ 58 | void 59 | vMBPortEnterCritical( void ) 60 | { 61 | if(ulNesting == 0) 62 | { 63 | xOriginalState = getprimask(); 64 | } 65 | ulNesting++; 66 | setprimask(1); 67 | } 68 | 69 | void 70 | vMBPortExitCritical( void ) 71 | { 72 | ulNesting--; 73 | if(ulNesting == 0) 74 | { 75 | setprimask(xOriginalState); 76 | } 77 | } 78 | 79 | /* ----------------------- Close Ports -----------------------------*/ 80 | void 81 | vMBPortClose( void ) 82 | { 83 | extern void vMBPortSerialClose( void ); 84 | extern void vMBPortTimersDisable( void ); 85 | vMBPortSerialClose( ); 86 | vMBPortTimersDisable( ); 87 | } 88 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f2/fmb_port/porttimer.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: BARE Port 3 | * Copyright (C) 2006 Christian Walter 4 | * 5 | * This library is free software; you can redistribute it and/or 6 | * modify it under the terms of the GNU Lesser General Public 7 | * License as published by the Free Software Foundation; either 8 | * version 2.1 of the License, or (at your option) any later version. 9 | * 10 | * This library is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * Lesser General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU Lesser General Public 16 | * License along with this library; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | * 19 | * File: $Id: porttimer.c,v 1.1 2006/08/22 21:35:13 wolti Exp $ 20 | */ 21 | 22 | /* ----------------------- Platform includes --------------------------------*/ 23 | #include "port.h" 24 | 25 | /* ----------------------- Modbus includes ----------------------------------*/ 26 | #include "mb.h" 27 | #include "mbport.h" 28 | 29 | /* ----------------------- libopencm3 STM32F includes -------------------------------*/ 30 | #include 31 | #include 32 | #include 33 | #include 34 | #include 35 | 36 | #include 37 | 38 | /* ----------------------- Initialize Timer -----------------------------*/ 39 | BOOL 40 | xMBPortTimersInit( USHORT usTim1Timerout50us ) 41 | { 42 | // rcc_periph_clock_enable( RCC_GPIOA ); 43 | // gpio_mode_setup(GPIOA, GPIO_OSPEED_50MHZ, GPIO_OTYPE_PP, GPIO1); 44 | // gpio_clear( GPIOA, GPIO1 ); 45 | 46 | /* Enable TIM clock. */ 47 | rcc_periph_clock_enable(MB_TMR_PERIPH); 48 | nvic_enable_irq (MB_TMR_VECTOR); 49 | timer_reset (MB_TMR); 50 | /* Timer global mode: - Divider 4, Alignment edge, Direction up */ 51 | timer_set_mode (MB_TMR, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); 52 | timer_continuous_mode(MB_TMR); 53 | timer_set_prescaler (MB_TMR, ((2*rcc_apb1_frequency)/20000ul - 1)); /* 50 microseconds period */ 54 | timer_set_period (MB_TMR, usTim1Timerout50us); 55 | return TRUE; 56 | } 57 | 58 | /* ----------------------- Enable Timer -----------------------------*/ 59 | inline void 60 | vMBPortTimersEnable( ) 61 | { 62 | /* Restart the timer with the period value set in xMBPortTimersInit( ) */ 63 | TIM_CNT(MB_TMR) = 1; /* Yes, this must be 1 !!! */ 64 | 65 | timer_enable_irq (MB_TMR, TIM_DIER_UIE); 66 | timer_enable_counter (MB_TMR); 67 | } 68 | 69 | /* ----------------------- Disable timer -----------------------------*/ 70 | inline void 71 | vMBPortTimersDisable( ) 72 | { 73 | timer_disable_irq (MB_TMR, TIM_DIER_UIE); 74 | timer_disable_counter(MB_TMR); 75 | } 76 | 77 | void vMBPortTimersDelay( USHORT usTimeOutMS ) 78 | { 79 | /*Not supproted*/ 80 | #if MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS > 0 81 | # error "MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS > 0 is not supported!!!" 82 | #endif 83 | } 84 | 85 | 86 | /* ----------------------- Timer ISR -----------------------------*/ 87 | /* Create an ISR which is called whenever the timer has expired. This function 88 | * must then call pxMBPortCBTimerExpired( ) to notify the protocol stack that 89 | * the timer has expired. 90 | */ 91 | static CHAR count; 92 | void MB_TMR_ISR(void) 93 | { 94 | count++; 95 | if (timer_interrupt_source(MB_TMR, TIM_SR_UIF)) 96 | { 97 | timer_clear_flag(MB_TMR, TIM_SR_UIF); /* Clear interrrupt flag. */ 98 | } 99 | timer_get_flag(MB_TMR, TIM_SR_UIF); /* Reread to force the previous (buffered) write before leaving */ 100 | pxMBPortCBTimerExpired(); 101 | } 102 | 103 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f2/libremodbus_port/serial_multi.h: -------------------------------------------------------------------------------- 1 | #ifndef SERIAL_MULTI_H 2 | #define SERIAL_MULTI_H 3 | 4 | #include 5 | #include 6 | 7 | 8 | #include 9 | #include 10 | 11 | 12 | 13 | #endif 14 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f2/libremodbus_port/serial_port.h: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: Win32 Port 3 | * Copyright (C) 2006 Christian Walter 4 | * 5 | * This library is free software; you can redistribute it and/or 6 | * modify it under the terms of the GNU Lesser General Public 7 | * License as published by the Free Software Foundation; either 8 | * version 2.1 of the License, or (at your option) any later version. 9 | * 10 | * This library is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * Lesser General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU Lesser General Public 16 | * License along with this library; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | * 19 | * File: $Id: port.h, v 1.5 2006/06/26 19:25:17 wolti Exp $ 20 | */ 21 | 22 | #ifndef _PORT_H 23 | #define _PORT_H 24 | 25 | #include 26 | #include 27 | 28 | #include 29 | 30 | #include "serial_multi.h" 31 | 32 | PR_BEGIN_EXTERN_C 33 | /* ----------------------- Defines ------------------------------------------*/ 34 | #define ENTER_CRITICAL_SECTION() cm_disable_interrupts() 35 | #define EXIT_CRITICAL_SECTION() cm_enable_interrupts() 36 | 37 | #define MB_PORT_HAS_CLOSE 1 38 | 39 | #ifndef TRUE 40 | #define TRUE 1 41 | #endif 42 | 43 | #ifndef FALSE 44 | #define FALSE 0 45 | #endif 46 | 47 | /* ----------------------- Type definitions ---------------------------------*/ 48 | struct _mb_port_ser 49 | { 50 | mb_port_base_struct base; 51 | uint32_t uart_num; 52 | bool tx_en; 53 | 54 | //timer 55 | DWORD timeout; 56 | BOOL timeout_enable; 57 | DWORD time_last; 58 | 59 | DWORD deafault_timeout; 60 | 61 | //events 62 | mb_event_enum queued_evt; 63 | BOOL evt_in_queue; 64 | }; 65 | /* ----------------------- Variable definitions -----------------------------*/ 66 | extern mb_port_ser_struct mbs_inst_usart; 67 | extern mb_port_ser_struct mbm_inst_usart; 68 | 69 | PR_END_EXTERN_C 70 | #endif 71 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f2/libremodbus_port/serial_portevent.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: BARE Port 3 | * Copyright (C) 2006 Christian Walter 4 | * 5 | * This library is free software; you can redistribute it and/or 6 | * modify it under the terms of the GNU Lesser General Public 7 | * License as published by the Free Software Foundation; either 8 | * version 2.1 of the License, or (at your option) any later version. 9 | * 10 | * This library is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * Lesser General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU Lesser General Public 16 | * License along with this library; if not, write to the Free Software 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | * 19 | * File: $Id: portevent.c, v 1.1 2006/08/22 21:35:13 wolti Exp $ 20 | */ 21 | 22 | /* ----------------------- Modbus includes ----------------------------------*/ 23 | #include 24 | 25 | #define evt_in_queue inst->evt_in_queue 26 | #define queued_evt inst->queued_evt 27 | 28 | /* ----------------------- Start implementation -----------------------------*/ 29 | BOOL 30 | mb_port_ser_evt_init(mb_port_ser_struct* inst) 31 | { 32 | evt_in_queue = FALSE; 33 | return TRUE; 34 | } 35 | 36 | BOOL mb_port_ser_evt_post( mb_port_ser_struct* inst, mb_event_enum event) 37 | { 38 | evt_in_queue = TRUE; 39 | queued_evt = event; 40 | return TRUE; 41 | } 42 | 43 | BOOL mb_port_ser_evt_get(mb_port_ser_struct* inst, void* caller, mb_event_enum * event) 44 | { 45 | BOOL xEventHappened = FALSE; 46 | 47 | (void)caller; 48 | if (evt_in_queue) 49 | { 50 | *event = queued_evt; 51 | evt_in_queue = FALSE; 52 | xEventHappened = TRUE; 53 | } 54 | return xEventHappened; 55 | } 56 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f2/libremodbus_port/serial_portother.c: -------------------------------------------------------------------------------- 1 | /* 2 | * FreeModbus Libary: Atmel AT91SAM3S Demo Application 3 | * Copyright (C) 2010 Christian Walter 4 | * 5 | * 6 | * Redistribution and use in source and binary forms, with or without 7 | * modification, are permitted provided that the following conditions 8 | * are met: 9 | * 1. Redistributions of source code must retain the above copyright 10 | * notice, this list of conditions and the following disclaimer. 11 | * 2. Redistributions in binary form must reproduce the above copyright 12 | * notice, this list of conditions and the following disclaimer in the 13 | * documentation and/or other materials provided with the distribution. 14 | * 3. The name of the author may not be used to endorse or promote products 15 | * derived from this software without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 | * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 | * 28 | * File: $Id: portother.c, v 1.1 2010/06/05 09:57:48 wolti Exp $ 29 | */ 30 | 31 | /* ----------------------- Modbus includes ----------------------------------*/ 32 | #include 33 | 34 | /* ----------------------- Static variables ---------------------------------*/ 35 | static UCHAR xOriginalState; 36 | static ULONG ulNesting; 37 | 38 | /* ----------------------- Cortex-M3 PRIMASK enable/disable -----------------*/ 39 | /* Gregory Nutt */ 40 | 41 | /* Get/set the primask register to control global DI/EI*/ 42 | 43 | static inline uint8_t getprimask(void) 44 | { 45 | uint32_t primask; 46 | __asm__ __volatile__("\tmrs %0, primask\n" : "=r" (primask) : : "memory"); 47 | return (uint8_t)primask; 48 | } 49 | 50 | static inline void setprimask(uint32_t primask) 51 | { 52 | __asm__ __volatile__("\tmsr primask, %0\n" : : "r" (primask) : "memory"); 53 | } 54 | /* ----------------------- Critical Section handler -----------------------------*/ 55 | /* Check if PRIMASK was set, and disable it on entry. On exit, if it was originally 56 | set then set it back again otherwise leave it unset. */ 57 | void 58 | vMBPortEnterCritical(void) 59 | { 60 | if (ulNesting == 0) 61 | { 62 | xOriginalState = getprimask(); 63 | } 64 | ulNesting++; 65 | setprimask(1); 66 | } 67 | 68 | void 69 | vMBPortExitCritical(void) 70 | { 71 | ulNesting--; 72 | if (ulNesting == 0) 73 | { 74 | setprimask(xOriginalState); 75 | } 76 | } 77 | 78 | /* ----------------------- Close Ports -----------------------------*/ 79 | void 80 | mb_port_ser_close(mb_port_ser_struct* inst) 81 | { 82 | extern void vMBPortSerialClose(mb_port_ser_struct* inst); 83 | //extern void mb_port_ser_tmr_disable(mb_port_ser_struct* inst); 84 | vMBPortSerialClose(inst); 85 | mb_port_ser_tmr_disable(inst); 86 | } 87 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f2/libremodbus_port/user_mb_app.h: -------------------------------------------------------------------------------- 1 | #ifndef USER_APP 2 | #define USER_APP 3 | /* ----------------------- Modbus includes ----------------------------------*/ 4 | #include "mb.h" 5 | #include "mbconfig.h" 6 | #include "mbframe.h" 7 | #include "mbutils.h" 8 | 9 | /* -----------------------Slave Defines -------------------------------------*/ 10 | #define S_DISCRETE_INPUT_START 0 11 | #define S_DISCRETE_INPUT_NDISCRETES 1 12 | #define S_COIL_START 0 13 | #define S_COIL_NCOILS 1 14 | #define S_REG_INPUT_START 0 15 | #define S_REG_INPUT_NREGS 1 16 | #define S_REG_HOLDING_START 0 17 | #define S_REG_HOLDING_NREGS 1 18 | /* salve mode: holding register's all address */ 19 | #define S_HD_RESERVE 0 20 | #define S_HD_CPU_USAGE_MAJOR 1 21 | #define S_HD_CPU_USAGE_MINOR 2 22 | /* salve mode: input register's all address */ 23 | #define S_IN_RESERVE 0 24 | /* salve mode: coil's all address */ 25 | #define S_CO_RESERVE 0 26 | /* salve mode: discrete's all address */ 27 | #define S_DI_RESERVE 0 28 | 29 | /* -----------------------Master Defines -------------------------------------*/ 30 | #define M_DISCRETE_INPUT_START 0 31 | #define M_DISCRETE_INPUT_NDISCRETES 1 32 | #define M_COIL_START 0 33 | #define M_COIL_NCOILS 1 34 | #define M_REG_INPUT_START 0 35 | #define M_REG_INPUT_NREGS 1 36 | #define M_REG_HOLDING_START 0 37 | #define M_REG_HOLDING_NREGS 1 38 | /* master mode: holding register's all address */ 39 | #define M_HD_RESERVE 0 40 | /* master mode: input register's all address */ 41 | #define M_IN_RESERVE 0 42 | /* master mode: coil's all address */ 43 | #define M_CO_RESERVE 0 44 | /* master mode: discrete's all address */ 45 | #define M_DI_RESERVE 0 46 | 47 | #endif 48 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f2/plc_gpio.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include 5 | #include 6 | 7 | #include 8 | 9 | void plc_gpio_cfg_in(const plc_gpio_t * self) 10 | { 11 | rcc_periph_clock_enable(self->periph); 12 | gpio_mode_setup (self->port, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, self->pin); 13 | } 14 | 15 | void plc_gpio_cfg_out(const plc_gpio_t * self) 16 | { 17 | rcc_periph_clock_enable(self->periph); 18 | gpio_mode_setup (self->port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, self->pin); 19 | gpio_set_output_options(self->port, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, self->pin); 20 | gpio_clear (self->port, self->pin); 21 | } 22 | 23 | void plc_gpio_gr_cfg_in(const plc_gpio_t * group, uint8_t n) 24 | { 25 | if (n==0) 26 | { 27 | return; 28 | } 29 | while (n--) 30 | { 31 | plc_gpio_cfg_in(group++); 32 | } 33 | } 34 | 35 | void plc_gpio_gr_cfg_out(const plc_gpio_t * group, uint8_t n) 36 | { 37 | if (n==0) 38 | { 39 | return; 40 | } 41 | while (n--) 42 | { 43 | plc_gpio_cfg_out(group++); 44 | } 45 | } 46 | 47 | void plc_gpio_gr_set(const plc_gpio_t * group, uint8_t n) 48 | { 49 | if (n==0) 50 | { 51 | return; 52 | } 53 | while (n--) 54 | { 55 | plc_gpio_set(group++); 56 | } 57 | } 58 | 59 | void plc_gpio_gr_clear(const plc_gpio_t * group, uint8_t n) 60 | { 61 | if (n==0) 62 | { 63 | return; 64 | } 65 | while (n--) 66 | { 67 | plc_gpio_clear(group++); 68 | } 69 | } 70 | 71 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f2/plc_serial.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nucleron/RTE/65341e5029a33f35f32de1fa41ba0276b89680b9/src/bsp/common/stm32/f2/plc_serial.c -------------------------------------------------------------------------------- /src/bsp/common/stm32/f4/plc_backup.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | #include 13 | #include 14 | #include 15 | 16 | #include 17 | #include 18 | 19 | #include 20 | 21 | //#define PLC_BKP_SIZE 4096 22 | 23 | #define PLC_UVP(a) ((void *)(a)) 24 | //Use RTC backup registers for validation 25 | #define PLC_BKP_VER1 MMIO32(RTC_BKP_BASE + PLC_BKP_VER1_OFFSET) 26 | #define PLC_BKP_VER2 MMIO32(RTC_BKP_BASE + PLC_BKP_VER2_OFFSET) 27 | //Use BackupSRAM to store retain vars 28 | //#define PLC_BKP_START PLC_UVP(BKPSRAM_BASE) 29 | #define PLC_BKP_START (uint32_t *)(RTC_BKP_BASE + PLC_BKP_REG_OFFSET) 30 | 31 | 32 | //watches RTC_BKP_BASE 0x40002850 33 | // PLC_BKP_START 0x40024000 34 | 35 | #define PLC_BKP_REG_NUM 4 36 | #define PLC_BKP_SIZE (PLC_BKP_REG_NUM*4ul) 37 | static uint32_t plc_backup_buff[PLC_BKP_REG_NUM]; 38 | static uint32_t * plc_backup_reg = PLC_BKP_START; 39 | 40 | void plc_backup_init(void) 41 | { 42 | uint32_t i; 43 | rcc_periph_clock_enable( RCC_PWR ); 44 | pwr_disable_backup_domain_write_protect(); 45 | 46 | PWR_CSR |= PWR_CSR_BRE; // Backup regulator enable 47 | while( 0 == ( PWR_CSR & PWR_CSR_BRR ) );// Wait for backup regulator ready 48 | 49 | pwr_enable_backup_domain_write_protect(); 50 | 51 | //rcc_periph_clock_enable( RCC_BKPSRAM ); 52 | for(i = 0; i < PLC_BKP_REG_NUM; i++) 53 | { 54 | plc_backup_buff[i] = plc_backup_reg[i]; 55 | } 56 | } 57 | 58 | void plc_backup_reset(void) 59 | { 60 | pwr_disable_backup_domain_write_protect(); 61 | PLC_BKP_VER1++; 62 | pwr_enable_backup_domain_write_protect(); 63 | } 64 | 65 | void plc_backup_invalidate(void) 66 | { 67 | //pwr_disable_backup_domain_write_protect(); 68 | //PLC_BKP_VER1++; 69 | //pwr_enable_backup_domain_write_protect(); 70 | } 71 | 72 | void plc_backup_validate(void) 73 | { 74 | uint32_t i; 75 | pwr_disable_backup_domain_write_protect(); 76 | 77 | PLC_BKP_VER1++; 78 | 79 | for(i = 0; i < PLC_BKP_REG_NUM; i++) 80 | { 81 | plc_backup_reg[i] = plc_backup_buff[i]; 82 | } 83 | 84 | PLC_BKP_VER2 = PLC_BKP_VER1; 85 | pwr_enable_backup_domain_write_protect(); 86 | } 87 | 88 | int plc_backup_check(void) 89 | { 90 | if( PLC_BKP_VER1 != PLC_BKP_VER2 ) 91 | { 92 | return 0; 93 | } 94 | else 95 | { 96 | return 1; //Success, now may remind 97 | } 98 | } 99 | 100 | 101 | 102 | void plc_backup_remind(unsigned int offset, unsigned int count, void *p) 103 | { 104 | if(offset + count < PLC_BKP_SIZE) 105 | { 106 | memcpy( p, (void *)plc_backup_buff + offset, count ); 107 | } 108 | } 109 | 110 | void plc_backup_retain(unsigned int offset, unsigned int count, void *p) 111 | { 112 | if(offset + count < PLC_BKP_SIZE) 113 | { 114 | //pwr_disable_backup_domain_write_protect(); 115 | memcpy( (void *)plc_backup_buff + offset, p, count ); 116 | //pwr_enable_backup_domain_write_protect(); 117 | } 118 | } 119 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f4/plc_gpio.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include 5 | #include 6 | 7 | #include 8 | 9 | void plc_gpio_cfg_in(const plc_gpio_t * self) 10 | { 11 | rcc_periph_clock_enable(self->periph); 12 | gpio_mode_setup (self->port, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, self->pin); 13 | } 14 | 15 | void plc_gpio_cfg_out(const plc_gpio_t * self) 16 | { 17 | rcc_periph_clock_enable(self->periph); 18 | gpio_mode_setup (self->port, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, self->pin); 19 | gpio_set_output_options(self->port, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, self->pin); 20 | gpio_clear (self->port, self->pin); 21 | } 22 | 23 | void plc_gpio_gr_cfg_in(const plc_gpio_t * group, uint8_t n) 24 | { 25 | if (n==0) 26 | { 27 | return; 28 | } 29 | while (n--) 30 | { 31 | plc_gpio_cfg_in(group++); 32 | } 33 | } 34 | 35 | void plc_gpio_gr_cfg_out(const plc_gpio_t * group, uint8_t n) 36 | { 37 | if (n==0) 38 | { 39 | return; 40 | } 41 | while (n--) 42 | { 43 | plc_gpio_cfg_out(group++); 44 | } 45 | } 46 | 47 | void plc_gpio_gr_set(const plc_gpio_t * group, uint8_t n) 48 | { 49 | if (n==0) 50 | { 51 | return; 52 | } 53 | while (n--) 54 | { 55 | plc_gpio_set(group++); 56 | } 57 | } 58 | 59 | void plc_gpio_gr_clear(const plc_gpio_t * group, uint8_t n) 60 | { 61 | if (n==0) 62 | { 63 | return; 64 | } 65 | while (n--) 66 | { 67 | plc_gpio_clear(group++); 68 | } 69 | } 70 | 71 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/f4/plc_serial.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nucleron/RTE/65341e5029a33f35f32de1fa41ba0276b89680b9/src/bsp/common/stm32/f4/plc_serial.c -------------------------------------------------------------------------------- /src/bsp/common/stm32/plc_gpio.h: -------------------------------------------------------------------------------- 1 | #ifndef _PLC_GPIO_H_ 2 | #define _PLC_GPIO_H_ 3 | 4 | #include 5 | #include 6 | 7 | typedef struct 8 | { 9 | enum rcc_periph_clken periph; 10 | uint32_t port; 11 | uint16_t pin; 12 | } plc_gpio_t; 13 | 14 | #define PLC_GPIO_CONCAT(a, b) a##b 15 | #define PLC_GPIO_CONCAT2(a, b) PLC_GPIO_CONCAT(a, b) 16 | 17 | #define PLC_GPIO_THING(n, name) (PLC_GPIO_CONCAT2(PLC_GPIO_CONCAT(PLC_, n), name)) 18 | 19 | #define PLC_GPIO_PERIPH(n) PLC_GPIO_THING(n, _PERIPH) 20 | #define PLC_GPIO_PORT(n) PLC_GPIO_THING(n, _PORT) 21 | #define PLC_GPIO_PIN(n) PLC_GPIO_THING(n, _PIN) 22 | 23 | #define PLC_GPIO_REC(n) {PLC_GPIO_PERIPH(n), PLC_GPIO_PORT(n), PLC_GPIO_PIN(n)} 24 | 25 | void plc_gpio_cfg_in (const plc_gpio_t * self); 26 | void plc_gpio_cfg_out(const plc_gpio_t * self); 27 | 28 | static inline void plc_gpio_set(const plc_gpio_t * self) 29 | { 30 | gpio_set (self->port, self->pin); 31 | } 32 | 33 | static inline void plc_gpio_clear(const plc_gpio_t * self) 34 | { 35 | gpio_clear(self->port, self->pin); 36 | } 37 | 38 | static inline bool plc_gpio_get(const plc_gpio_t * self) 39 | { 40 | return (gpio_get(self->port, self->pin)); 41 | } 42 | 43 | //group configs 44 | void plc_gpio_gr_cfg_in (const plc_gpio_t * group, uint8_t n); 45 | void plc_gpio_gr_cfg_out(const plc_gpio_t * group, uint8_t n); 46 | void plc_gpio_gr_set (const plc_gpio_t * group, uint8_t n); 47 | void plc_gpio_gr_clear (const plc_gpio_t * group, uint8_t n); 48 | 49 | //Grpups must be delared before call 50 | #define PLC_GPIO_GR_CFG_IN(grp) plc_gpio_gr_cfg_in (grp, (uint8_t)(sizeof(grp)/sizeof(plc_gpio_t))) 51 | #define PLC_GPIO_GR_CFG_OUT(grp) plc_gpio_gr_cfg_out(grp, (uint8_t)(sizeof(grp)/sizeof(plc_gpio_t))) 52 | #define PLC_GPIO_GR_SET(grp) plc_gpio_gr_set(grp, (uint8_t)(sizeof(grp)/sizeof(plc_gpio_t))) 53 | #define PLC_GPIO_GR_CLEAR(grp) plc_gpio_gr_clear(grp, (uint8_t)(sizeof(grp)/sizeof(plc_gpio_t))) 54 | 55 | #endif /* _PLC_GPIO_H_ */ 56 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/plc_hmi.h: -------------------------------------------------------------------------------- 1 | #ifndef _PLC_HMI_H_ 2 | #define _PLC_HMI_H_ 3 | 4 | #define PLC_HMI_BRI_LIM 6 5 | #define HMI_DIGITS 6 6 | #define HMI_NBUTTONS 3 7 | 8 | #define HMI_MAX_SINT 999l 9 | #define HMI_MIN_SINT -999l 10 | 11 | typedef struct 12 | { 13 | uint32_t shift; 14 | uint32_t msk; 15 | } 16 | plc_hmi_led_rec; 17 | 18 | typedef enum 19 | { 20 | PLC_HMI_NOT_USED = 0, 21 | PLC_HMI_BOOL_OO, 22 | PLC_HMI_BOOL_TF, 23 | PLC_HMI_HEX, 24 | PLC_HMI_UINT, 25 | PLC_HMI_SINT, 26 | PLC_HMI_MMDD, 27 | PLC_HMI_HHMM, 28 | PLC_HMI_RO_START, //Read only types start 29 | PLC_HMI_RO_BOOL_OO, 30 | PLC_HMI_RO_BOOL_TF, 31 | PLC_HMI_RO_HEX, 32 | PLC_HMI_RO_UINT, 33 | PLC_HMI_RO_SINT, 34 | PLC_HMI_RO_MMDD, 35 | PLC_HMI_RO_HHMM, 36 | PLC_HMI_EMPTY, //Yes, empty is read only! 37 | PLC_HMI_END 38 | }plc_hmi_par_t; //HMI parameter types 39 | 40 | typedef struct _plc_hmi_t plc_hmi_t;//HMI 41 | typedef struct _plc_hmi_dm_t plc_hmi_dm_t;//Data model (MVC pattern is used) 42 | 43 | struct _plc_hmi_dm_t 44 | { 45 | uint32_t leds; //Led satate 46 | plc_hmi_par_t * ptype; 47 | int32_t (*par_get)(uint8_t); //parameter get 48 | int32_t (*par_chk)(uint8_t, int32_t); //parameter check 49 | void (*par_set)(uint8_t, int32_t); //parameter set 50 | char (*poll)(uint32_t, char); //Poll hook 51 | uint8_t psize; 52 | }; 53 | 54 | struct _plc_hmi_t 55 | { 56 | plc_hmi_dm_t * mdl; //Current data model 57 | int32_t tmp; //Temp var for edit mode 58 | uint32_t delta; //Delta in edit mode 59 | uint8_t cursor; //Cursor in edit mode 60 | uint8_t cur_par; //Current param; 61 | uint8_t state; //HMI state 62 | char buf[HMI_DIGITS]; 63 | bool cur_show; 64 | }; 65 | 66 | #define PLC_HMI_STATE_VIEW 0 67 | #define PLC_HMI_STATE_EDIT 1 68 | 69 | int32_t hmi_sys_get(uint8_t par); 70 | int32_t hmi_sys_chk(uint8_t par, int32_t val); 71 | void hmi_sys_set(uint8_t par, int32_t val); 72 | 73 | void plc_hmi_kb_init(void); 74 | char plc_hmi_kb_poll(uint32_t tick); 75 | 76 | void plc_hmi_vout_init(void); 77 | void plc_hmi_vout_poll(void); 78 | 79 | void _plc_hmi_init(void); 80 | void _plc_hmi_poll(uint32_t tick); 81 | 82 | #endif // _PLC_HMI_H_ 83 | -------------------------------------------------------------------------------- /src/bsp/common/stm32/plc_wait_tmr.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | 11 | #include 12 | #include 13 | #include 14 | 15 | 16 | #include 17 | #include 18 | #include 19 | #include 20 | 21 | 22 | void plc_wait_tmr_init(void) 23 | { 24 | //Wait timer config, basic timers TIM6 and TIM7 may be used 25 | rcc_periph_clock_enable(PLC_WAIT_TMR_PERIPH); 26 | 27 | timer_reset (PLC_WAIT_TMR); 28 | timer_set_prescaler (PLC_WAIT_TMR, ((2*rcc_apb1_frequency)/1000000ul - 1)); //1MHz 29 | timer_disable_preload (PLC_WAIT_TMR); 30 | timer_continuous_mode (PLC_WAIT_TMR); 31 | timer_set_period (PLC_WAIT_TMR, 100); //10KHz 32 | 33 | timer_enable_counter (PLC_WAIT_TMR); 34 | timer_enable_irq (PLC_WAIT_TMR, TIM_DIER_UIE); 35 | 36 | nvic_enable_irq(PLC_WAIT_TMR_VECTOR); 37 | } 38 | 39 | volatile uint32_t plc_sys_timer = 0; 40 | volatile uint32_t plc_wait_cnt = 0; 41 | 42 | void PLC_WAIT_TMR_ISR(void) 43 | { 44 | if (timer_get_flag(PLC_WAIT_TMR, TIM_SR_UIF)) 45 | { 46 | 47 | /* Clear compare interrupt flag. */ 48 | timer_clear_flag(PLC_WAIT_TMR, TIM_SR_UIF); 49 | 50 | _plc_rtc_poll(); 51 | 52 | plc_wait_cnt++; 53 | if (10 <= plc_wait_cnt) 54 | { 55 | plc_wait_cnt = 0; 56 | 57 | plc_sys_timer++; 58 | plc_iom_tick(); 59 | } 60 | } 61 | } 62 | -------------------------------------------------------------------------------- /src/bsp/nuc-227-dev/plc_backup.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | #include 13 | #include 14 | #include 15 | 16 | #include 17 | #include 18 | 19 | #include 20 | 21 | //#define PLC_BKP_SIZE 4096 22 | 23 | #define PLC_UVP(a) ((void *)(a)) 24 | //Use RTC backup registers for validation 25 | #define PLC_BKP_VER1 MMIO32(RTC_BKP_BASE + PLC_BKP_VER1_OFFSET) 26 | #define PLC_BKP_VER2 MMIO32(RTC_BKP_BASE + PLC_BKP_VER2_OFFSET) 27 | //Use BackupSRAM to store retain vars 28 | //#define PLC_BKP_START PLC_UVP(BKPSRAM_BASE) 29 | #define PLC_BKP_START (uint32_t *)(RTC_BKP_BASE + PLC_BKP_REG_OFFSET) 30 | 31 | 32 | //watches RTC_BKP_BASE 0x40002850 33 | // PLC_BKP_START 0x40024000 34 | 35 | #define PLC_BKP_REG_NUM 10 36 | #define PLC_BKP_SIZE (PLC_BKP_REG_NUM*4ul) 37 | static uint32_t plc_backup_buff[PLC_BKP_REG_NUM]; 38 | static uint32_t * plc_backup_reg = PLC_BKP_START; 39 | 40 | void plc_backup_init(void) 41 | { 42 | uint32_t i; 43 | rcc_periph_clock_enable( RCC_PWR ); 44 | pwr_disable_backup_domain_write_protect(); 45 | 46 | PWR_CSR |= PWR_CSR_BRE; // Backup regulator enable 47 | while( 0 == ( PWR_CSR & PWR_CSR_BRR ) );// Wait for backup regulator ready 48 | 49 | pwr_enable_backup_domain_write_protect(); 50 | 51 | //rcc_periph_clock_enable( RCC_BKPSRAM ); 52 | for(i = 0; i < PLC_BKP_REG_NUM; i++) 53 | { 54 | plc_backup_buff[i] = plc_backup_reg[i]; 55 | } 56 | } 57 | 58 | void plc_backup_reset(void) 59 | { 60 | pwr_disable_backup_domain_write_protect(); 61 | PLC_BKP_VER1++; 62 | pwr_enable_backup_domain_write_protect(); 63 | } 64 | 65 | void plc_backup_invalidate(void) 66 | { 67 | //pwr_disable_backup_domain_write_protect(); 68 | //PLC_BKP_VER1++; 69 | //pwr_enable_backup_domain_write_protect(); 70 | } 71 | 72 | void plc_backup_validate(void) 73 | { 74 | uint32_t i; 75 | pwr_disable_backup_domain_write_protect(); 76 | 77 | PLC_BKP_VER1++; 78 | 79 | for(i = 0; i < PLC_BKP_REG_NUM; i++) 80 | { 81 | plc_backup_reg[i] = plc_backup_buff[i]; 82 | } 83 | 84 | PLC_BKP_VER2 = PLC_BKP_VER1; 85 | pwr_enable_backup_domain_write_protect(); 86 | } 87 | 88 | int plc_backup_check(void) 89 | { 90 | if( PLC_BKP_VER1 != PLC_BKP_VER2 ) 91 | { 92 | return 0; 93 | } 94 | else 95 | { 96 | return 1; //Success, now may remind 97 | } 98 | } 99 | 100 | 101 | 102 | void plc_backup_remind(unsigned int offset, unsigned int count, void *p) 103 | { 104 | if(offset + count < PLC_BKP_SIZE) 105 | { 106 | memcpy( p, (void *)plc_backup_buff + offset, count ); 107 | } 108 | } 109 | 110 | void plc_backup_retain(unsigned int offset, unsigned int count, void *p) 111 | { 112 | if(offset + count < PLC_BKP_SIZE) 113 | { 114 | //pwr_disable_backup_domain_write_protect(); 115 | memcpy( (void *)plc_backup_buff + offset, p, count ); 116 | //pwr_enable_backup_domain_write_protect(); 117 | } 118 | } 119 | -------------------------------------------------------------------------------- /src/bsp/nuc-227-dev/plc_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | */ 4 | 5 | #ifndef _PLC_CONFIG_H_ 6 | #define _PLC_CONFIG_H_ 7 | 8 | /* 9 | * NUC-227-DEV configuration! 10 | */ 11 | 12 | #include 13 | #include 14 | 15 | #define PLC_DISABLE_INTERRUPTS cm_disable_interrupts 16 | #define PLC_ENABLE_INTERRUPTS cm_enable_interrupts 17 | 18 | /* 19 | * PLC clocks 20 | */ 21 | #define PLC_HSE_CONFIG rcc_hse_16mhz_3v3 22 | #define PLC_RCC_AHB_FREQ 168 23 | 24 | /* 25 | * Debug USART 26 | */ 27 | #define DBG_USART USART1 28 | #define DBG_USART_PERIPH RCC_USART1 29 | #define DBG_USART_VECTOR NVIC_USART1_IRQ 30 | #define DBG_USART_ISR usart1_isr 31 | 32 | #define DBG_USART_TX_PORT GPIOA 33 | #define DBG_USART_RX_PORT GPIOA 34 | 35 | #define DBG_USART_TX_PIN GPIO9 36 | #define DBG_USART_RX_PIN GPIO10 37 | 38 | #define DBG_USART_TX_PERIPH RCC_GPIOA 39 | #define DBG_USART_RX_PERIPH RCC_GPIOA 40 | 41 | /* 42 | * Boot pin 43 | */ 44 | #define PLC_BOOT_PERIPH RCC_GPIOD 45 | #define PLC_BOOT_PORT GPIOD 46 | #define PLC_BOOT_PIN GPIO10 47 | 48 | /* 49 | * PLC LEDS 50 | */ 51 | #define PLC_LED_STG_PERIPH RCC_GPIOB 52 | #define PLC_LED_STG_PORT GPIOB 53 | #define PLC_LED_STG_PIN GPIO12 54 | 55 | #define PLC_LED_STR_PERIPH RCC_GPIOB 56 | #define PLC_LED_STR_PORT GPIOB 57 | #define PLC_LED_STR_PIN GPIO13 58 | 59 | #define PLC_LED3_PERIPH RCC_GPIOB 60 | #define PLC_LED3_PORT GPIOB 61 | #define PLC_LED3_PIN GPIO14 62 | 63 | extern void plc_heart_beat(void); 64 | 65 | #define PLC_BLINK() plc_heart_beat() 66 | 67 | /* 68 | * PLC Inputs 69 | */ 70 | #define PLC_I1_PERIPH RCC_GPIOE 71 | #define PLC_I1_PORT GPIOE 72 | #define PLC_I1_PIN GPIO0 73 | 74 | #define PLC_I2_PERIPH RCC_GPIOB 75 | #define PLC_I2_PORT GPIOB 76 | #define PLC_I2_PIN GPIO8 77 | 78 | #define PLC_I3_PERIPH RCC_GPIOB 79 | #define PLC_I3_PORT GPIOB 80 | #define PLC_I3_PIN GPIO6 81 | 82 | #define PLC_I4_PERIPH RCC_GPIOB 83 | #define PLC_I4_PORT GPIOB 84 | #define PLC_I4_PIN GPIO4 85 | 86 | #define PLC_I5_PERIPH RCC_GPIOD 87 | #define PLC_I5_PORT GPIOD 88 | #define PLC_I5_PIN GPIO6 89 | 90 | #define PLC_I6_PERIPH RCC_GPIOD 91 | #define PLC_I6_PORT GPIOD 92 | #define PLC_I6_PIN GPIO4 93 | 94 | #define PLC_I7_PERIPH RCC_GPIOD 95 | #define PLC_I7_PORT GPIOD 96 | #define PLC_I7_PIN GPIO5 97 | 98 | #define PLC_I8_PERIPH RCC_GPIOD 99 | #define PLC_I8_PORT GPIOD 100 | #define PLC_I8_PIN GPIO7 101 | 102 | /* 103 | * PLC Outputs 104 | */ 105 | #define PLC_O1_PERIPH RCC_GPIOE 106 | #define PLC_O1_PORT GPIOE 107 | #define PLC_O1_PIN GPIO1 108 | 109 | #define PLC_O2_PERIPH RCC_GPIOB 110 | #define PLC_O2_PORT GPIOB 111 | #define PLC_O2_PIN GPIO9 112 | 113 | #define PLC_O3_PERIPH RCC_GPIOB 114 | #define PLC_O3_PORT GPIOB 115 | #define PLC_O3_PIN GPIO7 116 | 117 | #define PLC_O4_PERIPH RCC_GPIOB 118 | #define PLC_O4_PORT GPIOB 119 | #define PLC_O4_PIN GPIO5 120 | 121 | /* 122 | * PLC system timer 123 | */ 124 | #define PLC_WAIT_TMR_PERIPH RCC_TIM7 125 | #define PLC_WAIT_TMR TIM7 126 | #define PLC_WAIT_TMR_VECTOR NVIC_TIM7_IRQ 127 | #define PLC_WAIT_TMR_ISR tim7_isr 128 | 129 | /* 130 | * Backup domain offsets 131 | */ 132 | #define PLC_BKP_VER1_OFFSET 0 133 | #define PLC_BKP_VER2_OFFSET 4 134 | #define PLC_BKP_RTC_IS_OK_OFFSET 8 135 | #define PLC_BKP_REG_OFFSET 0x24 136 | 137 | #define PLC_BKP_IRQ1_OFFSET 0xC 138 | #define PLC_BKP_IRQ2_OFFSET 0x10 139 | #define PLC_BKP_IRQ3_OFFSET 0x14 140 | #define PLC_BKP_IRQ4_OFFSET 0x18 141 | #define PLC_BKP_IRQ5_OFFSET 0x1C 142 | #define PLC_BKP_IRQ6_OFFSET 0x20 143 | 144 | #define BACKUP_REGS_BASE RTC_BKP_BASE 145 | //#define PLC_BKP_REG_OFFSET 0x50 146 | //#define PLC_BKP_REG_NUM 19 147 | 148 | /*Diag info*/ 149 | #define PLC_DIAG_IRQS ((uint32_t *)(BACKUP_REGS_BASE + PLC_BKP_IRQ1_OFFSET)) 150 | #define PLC_DIAG_INUM (96) 151 | 152 | 153 | /* 154 | * PLC app abi 155 | */ 156 | #define PLC_APP ((plc_app_abi_t *)0x08008000) 157 | 158 | /* 159 | * PLC RTE Version 160 | */ 161 | #define PLC_RTE_VER_MAJOR 2 162 | #define PLC_RTE_VER_MINOR 0 163 | #define PLC_RTE_VER_PATCH 0 164 | 165 | #define PLC_HW_ID 227 166 | /* 167 | * Logging 168 | */ 169 | #define LOG_LEVELS 4 170 | #define LOG_CRITICAL 0 171 | #define LOG_WARNING 1 172 | #define LOG_INFO 2 173 | #define LOG_DEBUG 3 174 | #endif /* _PLC_CONFIG_H_ */ 175 | -------------------------------------------------------------------------------- /src/bsp/nuc-227-dev/plc_config_bak.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | */ 4 | #ifndef _PLC_CONFIG_H_ 5 | #define _PLC_CONFIG_H_ 6 | 7 | #include 8 | #include 9 | 10 | #define PLC_DISABLE_INTERRUPTS cm_disable_interrupts 11 | #define PLC_ENABLE_INTERRUPTS cm_enable_interrupts 12 | 13 | #define DBG_USART USART3 14 | #define DBG_USART_PERIPH RCC_USART3 15 | #define DBG_USART_VECTOR NVIC_USART3_IRQ 16 | #define DBG_USART_ISR usart3_isr 17 | 18 | #define DBG_USART_TX_PORT GPIOB 19 | #define DBG_USART_RX_PORT GPIOB 20 | 21 | #define DBG_USART_TX_PIN GPIO10 22 | #define DBG_USART_RX_PIN GPIO11 23 | 24 | #define DBG_USART_TX_PERIPH RCC_GPIOB 25 | #define DBG_USART_RX_PERIPH RCC_GPIOB 26 | 27 | #define PLC_BOOT_PERIPH RCC_GPIOD 28 | #define PLC_BOOT_PORT GPIOD 29 | #define PLC_BOOT_PIN GPIO10 30 | 31 | #define PLC_WAIT_TMR_PERIPH RCC_TIM7 32 | #define PLC_WAIT_TMR TIM7 33 | #define PLC_WAIT_TMR_VECTOR NVIC_TIM7_IRQ 34 | #define PLC_WAIT_TMR_ISR tim7_isr 35 | 36 | #define PLC_BKP_VER1_OFFSET 0 37 | #define PLC_BKP_VER2_OFFSET 4 38 | #define PLC_BKP_RTC_IS_OK_OFFSET 8 39 | 40 | #include 41 | 42 | #endif /* _PLC_CONFIG_H_ */ 43 | -------------------------------------------------------------------------------- /src/bsp/nuc-227-dev/plc_serial.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nucleron/RTE/65341e5029a33f35f32de1fa41ba0276b89680b9/src/bsp/nuc-227-dev/plc_serial.c -------------------------------------------------------------------------------- /src/bsp/nuc-227-dev/plc_tick.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | #include 13 | #include 14 | 15 | static bool systick_set_period(uint32_t period, uint32_t ahb, uint8_t clk_source) 16 | { 17 | if (period >= (STK_RVR_RELOAD/ahb)) 18 | { 19 | return false; 20 | } 21 | else 22 | { 23 | systick_set_clocksource( clk_source ); 24 | systick_set_reload( ahb * period - 1 ); 25 | return true; 26 | } 27 | } 28 | 29 | //Минимальный период в нС. 30 | #define TICK_MIN_PER 100000ULL 31 | //Пороговый период 32 | #define TICK_THR_PER 500000000ULL 33 | //Частота в МГц 34 | #define RCC_AHB_FREQ 168UL 35 | 36 | //Контроллер системного таймера. 37 | static frac_div_t systick_ctrl; 38 | 39 | //Состояние системного таймера 40 | #define TICK_STATE_HIGH 0 41 | #define TICK_STATE_MID 1 42 | #define TICK_STATE_LOW 2 43 | static uint32_t tick_state = TICK_STATE_HIGH; 44 | 45 | void sys_tick_handler(void) 46 | { 47 | switch( tick_state ) 48 | { 49 | case TICK_STATE_MID: 50 | case TICK_STATE_HIGH: 51 | default: 52 | { 53 | systick_set_reload( RCC_AHB_FREQ * (uint32_t)frac_div_icalc( &systick_ctrl ) - 1 ); 54 | plc_tick_flag = true; 55 | break; 56 | } 57 | case TICK_STATE_LOW: 58 | { 59 | plc_tick_flag = frac_div_run( &systick_ctrl ); 60 | break; 61 | } 62 | } 63 | } 64 | 65 | volatile bool plc_tick_flag = false; 66 | 67 | //Tick period in ns 68 | void plc_tick_setup( uint64_t tick_next, uint64_t tick_period ) 69 | { 70 | (void)tick_next;//disable warning 71 | 72 | if( tick_period < TICK_MIN_PER ) 73 | { 74 | tick_period = TICK_MIN_PER; 75 | } 76 | 77 | if( tick_period < TICK_THR_PER ) 78 | { 79 | //Переменная частота работы системного таймера. 80 | if( systick_set_period( (uint32_t)(tick_period/1000ULL), RCC_AHB_FREQ, STK_CSR_CLKSOURCE_AHB) ) 81 | { 82 | //Примерно до 0.1с 83 | tick_state = TICK_STATE_HIGH; 84 | frac_div_init( &systick_ctrl, tick_period, 1000ULL ); //Коррекция приода 85 | } 86 | else 87 | { 88 | //До 0.5с 89 | tick_state = TICK_STATE_MID; 90 | systick_set_period( (uint32_t)(tick_period/8000ULL), RCC_AHB_FREQ, STK_CSR_CLKSOURCE_AHB_DIV8); 91 | frac_div_init( &systick_ctrl, tick_period, 8000ULL ); //Коррекция периода 92 | } 93 | } 94 | else 95 | { 96 | //Постоянная частота работы системного таймера. 97 | tick_state = TICK_STATE_LOW; 98 | systick_set_period( 500, RCC_AHB_FREQ, STK_CSR_CLKSOURCE_AHB);//500мкс 99 | frac_div_init( &systick_ctrl, tick_period, 500000ULL ); 100 | } 101 | 102 | systick_counter_enable(); 103 | systick_interrupt_enable(); 104 | } 105 | -------------------------------------------------------------------------------- /src/bsp/nuc-227-dev/plc_wait_tmr.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | 11 | #include 12 | #include 13 | #include 14 | 15 | 16 | #include 17 | #include 18 | #include 19 | 20 | void plc_wait_tmr_init(void) 21 | { 22 | //Wait timer config, basic timers TIM6 and TIM7 may be used 23 | rcc_periph_clock_enable( PLC_WAIT_TMR_PERIPH ); 24 | 25 | timer_reset ( PLC_WAIT_TMR ); 26 | timer_set_prescaler ( PLC_WAIT_TMR, (( rcc_apb1_frequency * 2 )/ 1000000 - 1) ); //1MHz 27 | timer_disable_preload ( PLC_WAIT_TMR ); 28 | timer_continuous_mode ( PLC_WAIT_TMR ); 29 | timer_set_period ( PLC_WAIT_TMR, 1000 ); //1KHz 30 | 31 | timer_enable_counter ( PLC_WAIT_TMR ); 32 | timer_enable_irq ( PLC_WAIT_TMR, TIM_DIER_UIE); 33 | 34 | nvic_enable_irq( PLC_WAIT_TMR_VECTOR ); 35 | } 36 | 37 | volatile uint32_t plc_sys_timer = 0; 38 | 39 | void PLC_WAIT_TMR_ISR(void) 40 | { 41 | if (timer_get_flag(PLC_WAIT_TMR, TIM_SR_UIF)) 42 | { 43 | 44 | /* Clear compare interrupt flag. */ 45 | timer_clear_flag(PLC_WAIT_TMR, TIM_SR_UIF); 46 | plc_sys_timer++; 47 | plc_iom_tick(); 48 | } 49 | } 50 | -------------------------------------------------------------------------------- /src/bsp/nuc-227-dev/stm32f4disco-app.ld: -------------------------------------------------------------------------------- 1 | /* Linker script for STM32F405RG Cortex-M4 ARM MCU */ 2 | 3 | /* Copyright (C)2013-2016, Philip Munts, President, Munts AM Corp. */ 4 | /* */ 5 | /* Redistribution and use in source and binary forms, with or without */ 6 | /* modification, are permitted provided that the following conditions are met: */ 7 | /* */ 8 | /* * Redistributions of source code must retain the above copyright notice, */ 9 | /* this list of conditions and the following disclaimer. */ 10 | /* */ 11 | /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ 12 | /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */ 13 | /* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */ 14 | /* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */ 15 | /* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */ 16 | /* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */ 17 | /* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS */ 18 | /* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN */ 19 | /* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) */ 20 | /* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */ 21 | /* POSSIBILITY OF SUCH DAMAGE. */ 22 | 23 | MEMORY 24 | { 25 | flash (rx) : ORIGIN = 0x08008000, LENGTH = 992K 26 | ram (rwx) : ORIGIN = 0x20002000, LENGTH = 120K 27 | ccm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K 28 | } 29 | 30 | __rom_start__ = ORIGIN(flash); 31 | __rom_size__ = LENGTH(flash); 32 | __ram_start__ = ORIGIN(ram); 33 | __ram_size__ = LENGTH(ram); 34 | __ram_end__ = __ram_start__ + __ram_size__; 35 | _plc_sstart = __ram_end__; /* Top of RAM */ 36 | 37 | SECTIONS 38 | { 39 | .text : { 40 | KEEP(*(.plc_app_abi_sec)) /* PLC APP ABI */ 41 | KEEP(*(.plc_md5_sec)) /* PLC APP ABI */ 42 | *(.text*) /* Program code */ 43 | KEEP(*(.rodata*)) /* Read only data */ 44 | 45 | . = ALIGN(4); 46 | _plc_pa_start = .; 47 | KEEP(*(.preinit_array)) /* Preinitarray */ 48 | _plc_pa_end = .; 49 | 50 | . = ALIGN(4); 51 | _plc_ia_start = .; 52 | KEEP (*(SORT(.init_array.*))) 53 | KEEP(*(.ctors)) /*Construcrs*/ 54 | _plc_ia_end = .; 55 | 56 | . = ALIGN(4); 57 | _plc_fia_start = .; 58 | KEEP(*(.fini_array)) /*Destructors */ 59 | KEEP (*(SORT(.fini_array.*))) 60 | _plc_fia_end = .; 61 | 62 | } >flash 63 | 64 | .data : ALIGN(16) { 65 | _plc_data_start = .; /* Used in PLC startup */ 66 | *(.data*) /* Initialized data */ 67 | _plc_data_end = .; /* Used in PLC startup */ 68 | } >ram AT > flash 69 | _plc_data_loadaddr = LOADADDR(.data); 70 | 71 | .bss (NOLOAD) : ALIGN(16) { 72 | *(.bss*) /* Uninitialized data */ 73 | *(COMMON) /* Common data */ 74 | _plc_bss_end = .; /* Used in PLC startup */ 75 | } >ram 76 | 77 | /* C++ exception unwinding stuff--needed by some toolchains */ 78 | 79 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >flash 80 | 81 | __exidx_start = .; 82 | .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >flash 83 | __exidx_end = .; 84 | 85 | 86 | ._plc_check : 87 | { 88 | KEEP(*(.plc_check_sec)) /* PLC APP ABI */ 89 | } > flash 90 | } 91 | 92 | /* Firmware entry point */ 93 | 94 | ENTRY(fake_start) 95 | 96 | -------------------------------------------------------------------------------- /src/bsp/nuc-227-dev/stm32f4disco-dev.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the libopencm3 project. 3 | * 4 | * Copyright (C) 2009 Uwe Hermann 5 | * Copyright (C) 2011 Stephen Caudle 6 | * 7 | * This library is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU Lesser General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This library is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU Lesser General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU Lesser General Public License 18 | * along with this library. If not, see . 19 | */ 20 | 21 | /* Linker script for ST STM32F4DISCOVERY (STM32F407VG, 1024K flash, 128K RAM). */ 22 | 23 | /* Define memory regions. */ 24 | MEMORY 25 | { 26 | rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K 27 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K 28 | } 29 | 30 | /* Include the common ld script. */ 31 | /* 32 | * This file is part of the libopencm3 project. 33 | * 34 | * Copyright (C) 2009 Uwe Hermann 35 | * 36 | * This library is free software: you can redistribute it and/or modify 37 | * it under the terms of the GNU Lesser General Public License as published by 38 | * the Free Software Foundation, either version 3 of the License, or 39 | * (at your option) any later version. 40 | * 41 | * This library is distributed in the hope that it will be useful, 42 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 43 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 44 | * GNU Lesser General Public License for more details. 45 | * 46 | * You should have received a copy of the GNU Lesser General Public License 47 | * along with this library. If not, see . 48 | */ 49 | 50 | /* Generic linker script for STM32 targets using libopencm3. */ 51 | 52 | /* Memory regions must be defined in the ld script which includes this one. */ 53 | 54 | /* Enforce emmition of the vector table. */ 55 | EXTERN (vector_table) 56 | 57 | /* Define the entry point of the output file. */ 58 | ENTRY(reset_handler) 59 | 60 | /* Define sections. */ 61 | SECTIONS 62 | { 63 | .text : { 64 | *(.vectors) /* Vector table */ 65 | *(.text*) /* Program code */ 66 | . = ALIGN(4); 67 | *(.rodata*) /* Read-only data */ 68 | . = ALIGN(4); 69 | } >rom 70 | 71 | /* C++ Static constructors/destructors, also used for __attribute__ 72 | * ((constructor)) and the likes */ 73 | .preinit_array : { 74 | . = ALIGN(4); 75 | __preinit_array_start = .; 76 | KEEP (*(.preinit_array)) 77 | __preinit_array_end = .; 78 | } >rom 79 | .init_array : { 80 | . = ALIGN(4); 81 | __init_array_start = .; 82 | KEEP (*(SORT(.init_array.*))) 83 | KEEP (*(.init_array)) 84 | __init_array_end = .; 85 | } >rom 86 | .fini_array : { 87 | . = ALIGN(4); 88 | __fini_array_start = .; 89 | KEEP (*(.fini_array)) 90 | KEEP (*(SORT(.fini_array.*))) 91 | __fini_array_end = .; 92 | } >rom 93 | 94 | /* 95 | * Another section used by C++ stuff, appears when using newlib with 96 | * 64bit (long long) printf support 97 | */ 98 | .ARM.extab : { 99 | *(.ARM.extab*) 100 | } >rom 101 | .ARM.exidx : { 102 | __exidx_start = .; 103 | *(.ARM.exidx*) 104 | __exidx_end = .; 105 | } >rom 106 | 107 | . = ALIGN(4); 108 | _etext = .; 109 | 110 | .data : { 111 | _data = .; 112 | *(.data*) /* Read-write initialized data */ 113 | . = ALIGN(4); 114 | _edata = .; 115 | } >ram AT >rom 116 | _data_loadaddr = LOADADDR(.data); 117 | 118 | .bss : { 119 | *(.bss*) /* Read-write zero initialized data */ 120 | *(COMMON) 121 | . = ALIGN(4); 122 | _ebss = .; 123 | } >ram 124 | 125 | /* 126 | * The .eh_frame section appears to be used for C++ exception handling. 127 | * You may need to fix this if you're using C++. 128 | */ 129 | ///DISCARD/ : { *(.eh_frame) } 130 | 131 | . = ALIGN(4); 132 | end = .; 133 | } 134 | 135 | PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); 136 | 137 | -------------------------------------------------------------------------------- /src/bsp/nuc-227-dev/stm32f4disco-rte.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the libopencm3 project. 3 | * 4 | * Copyright (C) 2009 Uwe Hermann 5 | * Copyright (C) 2011 Stephen Caudle 6 | * 7 | * This library is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU Lesser General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This library is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU Lesser General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU Lesser General Public License 18 | * along with this library. If not, see . 19 | */ 20 | 21 | /* Linker script for ST STM32F4DISCOVERY (STM32F407VG, 1024K flash, 128K RAM). */ 22 | 23 | /* Define memory regions. */ 24 | MEMORY 25 | { 26 | rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K 27 | app_flash (rx) : ORIGIN = 0x08008000, LENGTH = 992K 28 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K 29 | appram (rwx) : ORIGIN = 0x20002000, LENGTH = 120K 30 | } 31 | 32 | PROVIDE( _stack = ORIGIN(appram) + LENGTH(appram) ); 33 | PROVIDE( _app_start = ORIGIN(app_flash) ); 34 | PROVIDE( _app_end = _app_start + LENGTH(app_flash) ); 35 | 36 | /* Include the common ld script. */ 37 | /* 38 | * This file is part of the libopencm3 project. 39 | * 40 | * Copyright (C) 2009 Uwe Hermann 41 | * 42 | * This library is free software: you can redistribute it and/or modify 43 | * it under the terms of the GNU Lesser General Public License as published by 44 | * the Free Software Foundation, either version 3 of the License, or 45 | * (at your option) any later version. 46 | * 47 | * This library is distributed in the hope that it will be useful, 48 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 49 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 50 | * GNU Lesser General Public License for more details. 51 | * 52 | * You should have received a copy of the GNU Lesser General Public License 53 | * along with this library. If not, see . 54 | */ 55 | 56 | /* Generic linker script for STM32 targets using libopencm3. */ 57 | 58 | /* Memory regions must be defined in the ld script which includes this one. */ 59 | 60 | /* Enforce emmition of the vector table. */ 61 | EXTERN (vector_table) 62 | 63 | /* Define the entry point of the output file. */ 64 | ENTRY(reset_handler) 65 | 66 | /* Define sections. */ 67 | SECTIONS 68 | { 69 | .text : { 70 | *(.vectors) /* Vector table */ 71 | KEEP (*(.plc_rte_sec)) /* PLC RTE ABI */ 72 | *(.text*) /* Program code */ 73 | . = ALIGN(4); 74 | *(.rodata*) /* Read-only data */ 75 | . = ALIGN(4); 76 | } >rom 77 | 78 | /* C++ Static constructors/destructors, also used for __attribute__ 79 | * ((constructor)) and the likes */ 80 | .preinit_array : { 81 | . = ALIGN(4); 82 | __preinit_array_start = .; 83 | KEEP (*(.preinit_array)) 84 | __preinit_array_end = .; 85 | } >rom 86 | .init_array : { 87 | . = ALIGN(4); 88 | __init_array_start = .; 89 | KEEP (*(SORT(.init_array.*))) 90 | KEEP (*(.init_array)) 91 | __init_array_end = .; 92 | } >rom 93 | .fini_array : { 94 | . = ALIGN(4); 95 | __fini_array_start = .; 96 | KEEP (*(.fini_array)) 97 | KEEP (*(SORT(.fini_array.*))) 98 | __fini_array_end = .; 99 | } >rom 100 | 101 | /* 102 | * Another section used by C++ stuff, appears when using newlib with 103 | * 64bit (long long) printf support 104 | */ 105 | .ARM.extab : { 106 | *(.ARM.extab*) 107 | } >rom 108 | .ARM.exidx : { 109 | __exidx_start = .; 110 | *(.ARM.exidx*) 111 | __exidx_end = .; 112 | } >rom 113 | 114 | . = ALIGN(4); 115 | _etext = .; 116 | 117 | .data : { 118 | _data = .; 119 | *(.data*) /* Read-write initialized data */ 120 | . = ALIGN(4); 121 | _edata = .; 122 | } >ram AT >rom 123 | _data_loadaddr = LOADADDR(.data); 124 | 125 | .bss : { 126 | *(.bss*) /* Read-write zero initialized data */ 127 | *(COMMON) 128 | . = ALIGN(4); 129 | _ebss = .; 130 | } >ram 131 | 132 | . = ALIGN(4); 133 | end = .; 134 | } 135 | 136 | -------------------------------------------------------------------------------- /src/bsp/nuc-242/plc_iom_reg.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | 14 | PLC_IOM_METH_DECLS(plc_dio); 15 | PLC_IOM_METH_DECLS(plc_mb); 16 | PLC_IOM_METH_DECLS(plc_diag); 17 | PLC_IOM_METH_DECLS(plc_hmi); 18 | 19 | const plc_io_metods_t plc_iom_registry[] = 20 | { 21 | PLC_IOM_RECORD(plc_diag), 22 | PLC_IOM_RECORD(plc_dio), 23 | PLC_IOM_RECORD(plc_mb), 24 | PLC_IOM_RECORD(plc_hmi) 25 | }; 26 | //Must be declared after plc_iom_registry 27 | PLC_IOM_REG_SZ_DECL; 28 | 29 | uint8_t mid_from_pid(uint16_t proto) 30 | { 31 | switch (proto) 32 | { 33 | case 0: 34 | return 0; 35 | case 1: 36 | return 1; 37 | case 2: 38 | return 2; 39 | case 4: //lost 3 somewhere? 40 | return 3; 41 | default: 42 | return PLC_IOM_MID_ERROR; 43 | } 44 | return PLC_IOM_MID_ERROR; 45 | } 46 | -------------------------------------------------------------------------------- /src/bsp/nuc-242/stm32f103xC-app.ld: -------------------------------------------------------------------------------- 1 | /* Copyright (C)2013-2016, Philip Munts, President, Munts AM Corp. */ 2 | /* */ 3 | /* Redistribution and use in source and binary forms, with or without */ 4 | /* modification, are permitted provided that the following conditions are met: */ 5 | /* */ 6 | /* * Redistributions of source code must retain the above copyright notice, */ 7 | /* this list of conditions and the following disclaimer. */ 8 | /* */ 9 | /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ 10 | /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */ 11 | /* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */ 12 | /* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */ 13 | /* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */ 14 | /* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */ 15 | /* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS */ 16 | /* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN */ 17 | /* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) */ 18 | /* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */ 19 | /* POSSIBILITY OF SUCH DAMAGE. */ 20 | 21 | MEMORY 22 | { 23 | flash (rx) : ORIGIN = 0x08008000, LENGTH = 224K 24 | ram (rwx) : ORIGIN = 0x20002000, LENGTH = 40K 25 | } 26 | 27 | __rom_start__ = ORIGIN(flash); 28 | __rom_size__ = LENGTH(flash); 29 | __ram_start__ = ORIGIN(ram); 30 | __ram_size__ = LENGTH(ram); 31 | __ram_end__ = __ram_start__ + __ram_size__; 32 | _plc_sstart = __ram_end__; /* Top of RAM */ 33 | 34 | SECTIONS 35 | { 36 | .text : { 37 | KEEP(*(.plc_app_abi_sec)) /* PLC APP ABI */ 38 | KEEP(*(.plc_md5_sec)) /* PLC APP ABI */ 39 | *(.text*) /* Program code */ 40 | KEEP(*(.rodata*)) /* Read only data */ 41 | 42 | . = ALIGN(4); 43 | _plc_pa_start = .; 44 | KEEP(*(.preinit_array)) /* Preinitarray */ 45 | _plc_pa_end = .; 46 | 47 | . = ALIGN(4); 48 | _plc_ia_start = .; 49 | KEEP (*(SORT(.init_array.*))) 50 | KEEP(*(.ctors)) /*Construcrs*/ 51 | _plc_ia_end = .; 52 | 53 | . = ALIGN(4); 54 | _plc_fia_start = .; 55 | KEEP(*(.fini_array)) /*Destructors */ 56 | KEEP (*(SORT(.fini_array.*))) 57 | _plc_fia_end = .; 58 | 59 | } >flash 60 | 61 | .data : ALIGN(16) { 62 | _plc_data_start = .; /* Used in PLC startup */ 63 | *(.data*) /* Initialized data */ 64 | _plc_data_end = .; /* Used in PLC startup */ 65 | } >ram AT > flash 66 | _plc_data_loadaddr = LOADADDR(.data); 67 | 68 | .bss (NOLOAD) : ALIGN(16) { 69 | *(.bss*) /* Uninitialized data */ 70 | *(COMMON) /* Common data */ 71 | _plc_bss_end = .; /* Used in PLC startup */ 72 | } >ram 73 | 74 | /* C++ exception unwinding stuff--needed by some toolchains */ 75 | 76 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >flash 77 | 78 | __exidx_start = .; 79 | .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >flash 80 | __exidx_end = .; 81 | 82 | 83 | ._plc_check : 84 | { 85 | KEEP(*(.plc_check_sec)) /* PLC APP ABI */ 86 | } > flash 87 | } 88 | 89 | /* Firmware entry point */ 90 | 91 | ENTRY(fake_start) 92 | 93 | -------------------------------------------------------------------------------- /src/bsp/nuc-242/stm32f103xC-dev.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the libopencm3 project. 3 | * 4 | * Copyright (C) 2009 Uwe Hermann 5 | * Copyright (C) 2011 Stephen Caudle 6 | * 7 | * This library is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU Lesser General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This library is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU Lesser General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU Lesser General Public License 18 | * along with this library. If not, see . 19 | */ 20 | 21 | /* Linker script for ST STM32F4DISCOVERY (STM32F407VG, 1024K flash, 128K RAM). */ 22 | 23 | /* Define memory regions. */ 24 | MEMORY 25 | { 26 | rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K 27 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K 28 | } 29 | 30 | /* Include the common ld script. */ 31 | /* 32 | * This file is part of the libopencm3 project. 33 | * 34 | * Copyright (C) 2009 Uwe Hermann 35 | * 36 | * This library is free software: you can redistribute it and/or modify 37 | * it under the terms of the GNU Lesser General Public License as published by 38 | * the Free Software Foundation, either version 3 of the License, or 39 | * (at your option) any later version. 40 | * 41 | * This library is distributed in the hope that it will be useful, 42 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 43 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 44 | * GNU Lesser General Public License for more details. 45 | * 46 | * You should have received a copy of the GNU Lesser General Public License 47 | * along with this library. If not, see . 48 | */ 49 | 50 | /* Generic linker script for STM32 targets using libopencm3. */ 51 | 52 | /* Memory regions must be defined in the ld script which includes this one. */ 53 | 54 | /* Enforce emmition of the vector table. */ 55 | EXTERN (vector_table) 56 | 57 | /* Define the entry point of the output file. */ 58 | ENTRY(reset_handler) 59 | 60 | /* Define sections. */ 61 | SECTIONS 62 | { 63 | .text : { 64 | *(.vectors) /* Vector table */ 65 | *(.text*) /* Program code */ 66 | . = ALIGN(4); 67 | *(.rodata*) /* Read-only data */ 68 | . = ALIGN(4); 69 | } >rom 70 | 71 | /* C++ Static constructors/destructors, also used for __attribute__ 72 | * ((constructor)) and the likes */ 73 | .preinit_array : { 74 | . = ALIGN(4); 75 | __preinit_array_start = .; 76 | KEEP (*(.preinit_array)) 77 | __preinit_array_end = .; 78 | } >rom 79 | .init_array : { 80 | . = ALIGN(4); 81 | __init_array_start = .; 82 | KEEP (*(SORT(.init_array.*))) 83 | KEEP (*(.init_array)) 84 | __init_array_end = .; 85 | } >rom 86 | .fini_array : { 87 | . = ALIGN(4); 88 | __fini_array_start = .; 89 | KEEP (*(.fini_array)) 90 | KEEP (*(SORT(.fini_array.*))) 91 | __fini_array_end = .; 92 | } >rom 93 | 94 | /* 95 | * Another section used by C++ stuff, appears when using newlib with 96 | * 64bit (long long) printf support 97 | */ 98 | .ARM.extab : { 99 | *(.ARM.extab*) 100 | } >rom 101 | .ARM.exidx : { 102 | __exidx_start = .; 103 | *(.ARM.exidx*) 104 | __exidx_end = .; 105 | } >rom 106 | 107 | . = ALIGN(4); 108 | _etext = .; 109 | 110 | .data : { 111 | _data = .; 112 | *(.data*) /* Read-write initialized data */ 113 | . = ALIGN(4); 114 | _edata = .; 115 | } >ram AT >rom 116 | _data_loadaddr = LOADADDR(.data); 117 | 118 | .bss : { 119 | *(.bss*) /* Read-write zero initialized data */ 120 | *(COMMON) 121 | . = ALIGN(4); 122 | _ebss = .; 123 | } >ram 124 | 125 | /* 126 | * The .eh_frame section appears to be used for C++ exception handling. 127 | * You may need to fix this if you're using C++. 128 | */ 129 | ///DISCARD/ : { *(.eh_frame) } 130 | 131 | . = ALIGN(4); 132 | end = .; 133 | } 134 | 135 | PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); 136 | 137 | -------------------------------------------------------------------------------- /src/bsp/nuc-243/plc_ain.h: -------------------------------------------------------------------------------- 1 | #ifndef _PLC_AIN_H_ 2 | #define _PLC_AIN_H_ 3 | 4 | typedef union 5 | { 6 | struct 7 | { 8 | uint16_t _10v; // 9 | uint16_t _20ma; // 10 | uint16_t _100r; // 11 | uint16_t _4k; // 12 | } 13 | coef; 14 | uint32_t reg[2]; 15 | uint16_t cval[4]; 16 | } 17 | ai_clb_t; 18 | 19 | // Структура с конфигурацией и результатами для AI 20 | typedef struct 21 | { 22 | noise_flt_t median; //Median filter 23 | uint16_t mbuf[NOISE_FLT_BUFSZ]; 24 | 25 | noise_flt_t ave; //Average filter 26 | 27 | uint16_t threshold_low; // нижний порог триггера шмидта (в единицах измерения) 28 | uint16_t threshold_high; // верхний порог триггера шмидта (в единицах измерения) 29 | uint16_t signal_level; // измеренный сигнал в (в единицах измерения) 30 | 31 | ai_clb_t clb; 32 | 33 | uint16_t polling_counter; // счёт милисекунд периодичности 34 | uint16_t polling_period; // период опроса канала в мс 35 | 36 | uint8_t flag; // флаг обработки результатов, на это время низзя изменять данные в прерывании 37 | uint8_t mode; // режим работы порта, см. _plc_ain_cfg() 38 | 39 | bool signal_schmitt; // значение выхода триггера Шмидта в канале 40 | } ai_data_t; 41 | 42 | // Структура с конфигурацией и результатами для прочих каналов АЦП 43 | typedef struct 44 | { 45 | uint32_t data_in; // сбор усреднённых данных (питание, температура, VBAT) 46 | uint32_t data_out; // итоговые данные для использования по назначению 47 | uint16_t calc; // пересчитанные в физ.величины: темп. в десятых градуса, напряжения в мВ 48 | uint8_t sum; // количество данных для усреднения (изм. раз в мс) 49 | uint8_t counter; // счёт штук для усреденения 50 | uint8_t flag; // 51 | } adc_data_t; 52 | 53 | typedef uint16_t (*calc_func)(uint16_t, ai_data_t *); //указатель на обрабтчик аналогового канала 54 | typedef uint16_t (*other_calc_func)(uint32_t, uint8_t); //указатель на обрабтчик аналогового канала 55 | 56 | // *** int ADC для AI *** 57 | extern ai_data_t analog_input[4]; // четыре комплекта для конфигурации аналоговых входов 58 | 59 | extern adc_data_t other_analog[4]; // четыре других аналоговых - напряжения, температура и VBAT 60 | 61 | 62 | void _plc_ain_init(void); 63 | #define PLC_ADC_CNT_THR 10 64 | void _plc_ain_adc_poll(void); 65 | void _plc_ain_other_data_calc(void); 66 | void _plc_ain_data_calc(void); 67 | 68 | #define PLC_AIN_MODE_OFF 0 69 | #define PLC_AIN_MODE_10V 1 70 | #define PLC_AIN_MODE_20MA 2 71 | #define PLC_AIN_MODE_100R 3 72 | #define PLC_AIN_MODE_4K 4 73 | /* port - номер порта: 0...3, 74 | mode - режим работы: 75 | 0 - шунты отключены, стабилизаторы тока отключены, 76 | 1 - шунт 21.5 кОм, 0...10 В, порт "b", 77 | 2 - шунт 127 Ом, 4...20 мА, порт "a", 78 | 3 - шунты отключены, измерение сопротивления 0...100R, порт "a", 79 | 4 - шунты отключены, измерение сопротивления 0...4000R, порт "a". 80 | */ 81 | void _plc_ain_cfg(uint32_t port, uint32_t mode); 82 | 83 | #endif /* _PLC_AIN_H_ */ 84 | -------------------------------------------------------------------------------- /src/bsp/nuc-243/plc_aout.h: -------------------------------------------------------------------------------- 1 | #ifndef _PLC_AOUT_H_ 2 | #define _PLC_AOUT_H_ 3 | 4 | #define PLC_DAC_SYNC_MSK 0x0060 5 | 6 | extern uint16_t plc_aout_dataA; 7 | extern uint16_t plc_aout_dataB; 8 | 9 | typedef union 10 | { 11 | uint32_t reg; 12 | uint16_t val[2]; 13 | }aout_clb_t; 14 | 15 | void _plc_aout_dac_poll(void); 16 | 17 | #endif /* _PLC_AOUT_H_ */ 18 | -------------------------------------------------------------------------------- /src/bsp/nuc-243/plc_iom_reg.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | 14 | PLC_IOM_METH_DECLS(plc_dio); 15 | PLC_IOM_METH_DECLS(plc_mb); 16 | PLC_IOM_METH_DECLS(plc_diag); 17 | PLC_IOM_METH_DECLS(plc_hmi); 18 | PLC_IOM_METH_DECLS(plc_ain); 19 | PLC_IOM_METH_DECLS(plc_aout); 20 | 21 | const plc_io_metods_t plc_iom_registry[] = 22 | { 23 | PLC_IOM_RECORD(plc_diag), 24 | PLC_IOM_RECORD(plc_dio), 25 | PLC_IOM_RECORD(plc_mb), 26 | PLC_IOM_RECORD(plc_hmi), 27 | PLC_IOM_RECORD(plc_aout), 28 | PLC_IOM_RECORD(plc_ain) 29 | }; 30 | //Must be declared after plc_iom_registry 31 | PLC_IOM_REG_SZ_DECL; 32 | 33 | uint8_t mid_from_pid(uint16_t proto) 34 | { 35 | switch (proto) 36 | { 37 | case 0: 38 | return 0; 39 | case 1: 40 | return 1; 41 | case 2: 42 | return 2; 43 | case 4: 44 | return 3; 45 | case 5: 46 | return 4; 47 | case 6: 48 | return 5; 49 | default: 50 | return PLC_IOM_MID_ERROR; 51 | } 52 | return PLC_IOM_MID_ERROR; 53 | } 54 | -------------------------------------------------------------------------------- /src/bsp/nuc-243/plc_wait_tmr.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | 11 | #include 12 | #include 13 | #include 14 | 15 | 16 | #include 17 | #include 18 | #include 19 | 20 | void plc_wait_tmr_init(void) 21 | { 22 | //Wait timer config, basic timers TIM6 and TIM7 may be used 23 | rcc_periph_clock_enable(PLC_WAIT_TMR_PERIPH); 24 | 25 | timer_reset (PLC_WAIT_TMR); 26 | timer_set_prescaler (PLC_WAIT_TMR, ((2*rcc_apb1_frequency)/1000000ul - 1)); //1MHz 27 | timer_disable_preload (PLC_WAIT_TMR); 28 | timer_continuous_mode (PLC_WAIT_TMR); 29 | timer_set_period (PLC_WAIT_TMR, 100); //10KHz 30 | 31 | timer_enable_counter (PLC_WAIT_TMR); 32 | timer_enable_irq (PLC_WAIT_TMR, TIM_DIER_UIE); 33 | 34 | nvic_enable_irq(PLC_WAIT_TMR_VECTOR); 35 | } 36 | 37 | volatile uint32_t plc_sys_timer = 0; 38 | volatile uint32_t plc_wait_cnt = 0; 39 | 40 | extern void plc_hmi_vout_poll(void); 41 | extern void _plc_ain_adc_poll(void); 42 | extern void _plc_aout_dac_poll(void); 43 | extern void _plc_rtc_poll(void); 44 | 45 | void PLC_WAIT_TMR_ISR(void) 46 | { 47 | if (timer_get_flag(PLC_WAIT_TMR, TIM_SR_UIF)) 48 | { 49 | /* Clear compare interrupt flag. */ 50 | timer_clear_flag(PLC_WAIT_TMR, TIM_SR_UIF); 51 | 52 | 53 | plc_hmi_vout_poll(); 54 | _plc_ain_adc_poll(); 55 | _plc_aout_dac_poll(); 56 | _plc_rtc_poll(); 57 | 58 | plc_wait_cnt++; 59 | if (10 <= plc_wait_cnt) 60 | { 61 | plc_wait_cnt = 0; 62 | 63 | plc_sys_timer++; 64 | plc_iom_tick(); 65 | } 66 | } 67 | } 68 | -------------------------------------------------------------------------------- /src/bsp/nuc-243/stm32f205xC-app.ld: -------------------------------------------------------------------------------- 1 | /* Linker script for STM32F205xV Cortex-M3 ARM MCU */ 2 | 3 | /* Copyright (C)2013-2016, Philip Munts, President, Munts AM Corp. */ 4 | /* */ 5 | /* Redistribution and use in source and binary forms, with or without */ 6 | /* modification, are permitted provided that the following conditions are met: */ 7 | /* */ 8 | /* * Redistributions of source code must retain the above copyright notice, */ 9 | /* this list of conditions and the following disclaimer. */ 10 | /* */ 11 | /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ 12 | /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */ 13 | /* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */ 14 | /* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */ 15 | /* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */ 16 | /* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */ 17 | /* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS */ 18 | /* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN */ 19 | /* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) */ 20 | /* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */ 21 | /* POSSIBILITY OF SUCH DAMAGE. */ 22 | 23 | MEMORY 24 | { 25 | flash (rx) : ORIGIN = 0x08008000, LENGTH = 224K 26 | ram (rwx) : ORIGIN = 0x20002000, LENGTH = 84K 27 | ccm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K 28 | } 29 | 30 | __rom_start__ = ORIGIN(flash); 31 | __rom_size__ = LENGTH(flash); 32 | __ram_start__ = ORIGIN(ram); 33 | __ram_size__ = LENGTH(ram); 34 | __ram_end__ = __ram_start__ + __ram_size__; 35 | _plc_sstart = __ram_end__; /* Top of RAM */ 36 | 37 | SECTIONS 38 | { 39 | .text : { 40 | KEEP(*(.plc_app_abi_sec)) /* PLC APP ABI */ 41 | KEEP(*(.plc_md5_sec)) /* PLC APP ABI */ 42 | *(.text*) /* Program code */ 43 | KEEP(*(.rodata*)) /* Read only data */ 44 | 45 | . = ALIGN(4); 46 | _plc_pa_start = .; 47 | KEEP(*(.preinit_array)) /* Preinitarray */ 48 | _plc_pa_end = .; 49 | 50 | . = ALIGN(4); 51 | _plc_ia_start = .; 52 | KEEP (*(SORT(.init_array.*))) 53 | KEEP(*(.ctors)) /*Construcrs*/ 54 | _plc_ia_end = .; 55 | 56 | . = ALIGN(4); 57 | _plc_fia_start = .; 58 | KEEP(*(.fini_array)) /*Destructors */ 59 | KEEP (*(SORT(.fini_array.*))) 60 | _plc_fia_end = .; 61 | 62 | } >flash 63 | 64 | .data : ALIGN(16) { 65 | _plc_data_start = .; /* Used in PLC startup */ 66 | *(.data*) /* Initialized data */ 67 | _plc_data_end = .; /* Used in PLC startup */ 68 | } >ram AT > flash 69 | _plc_data_loadaddr = LOADADDR(.data); 70 | 71 | .bss (NOLOAD) : ALIGN(16) { 72 | *(.bss*) /* Uninitialized data */ 73 | *(COMMON) /* Common data */ 74 | _plc_bss_end = .; /* Used in PLC startup */ 75 | } >ram 76 | 77 | /* C++ exception unwinding stuff--needed by some toolchains */ 78 | 79 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >flash 80 | 81 | __exidx_start = .; 82 | .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >flash 83 | __exidx_end = .; 84 | 85 | 86 | ._plc_check : 87 | { 88 | KEEP(*(.plc_check_sec)) /* PLC APP ABI */ 89 | } > flash 90 | } 91 | 92 | /* Firmware entry point */ 93 | 94 | ENTRY(fake_start) 95 | 96 | -------------------------------------------------------------------------------- /src/bsp/nuc-243/stm32f205xC-rte.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the libopencm3 project. 3 | * 4 | * Copyright (C) 2009 Uwe Hermann 5 | * Copyright (C) 2011 Stephen Caudle 6 | * 7 | * This library is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU Lesser General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This library is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU Lesser General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU Lesser General Public License 18 | * along with this library. If not, see . 19 | */ 20 | 21 | /* Linker script for ST STM32F4DISCOVERY (STM32F205VC, 256K flash, 128K RAM). */ 22 | 23 | /* Define memory regions. */ 24 | MEMORY 25 | { 26 | rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K 27 | app_flash (rx) : ORIGIN = 0x08008000, LENGTH = 224K 28 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K 29 | appram (rwx) : ORIGIN = 0x20002000, LENGTH = 84K 30 | } 31 | 32 | PROVIDE(_stack = ORIGIN(appram) + LENGTH(appram)); 33 | PROVIDE(_app_start = ORIGIN(app_flash) ); 34 | PROVIDE(_app_end = _app_start + LENGTH(app_flash) ); 35 | 36 | /* Include the common ld script. */ 37 | /* 38 | * This file is part of the libopencm3 project. 39 | * 40 | * Copyright (C) 2009 Uwe Hermann 41 | * 42 | * This library is free software: you can redistribute it and/or modify 43 | * it under the terms of the GNU Lesser General Public License as published by 44 | * the Free Software Foundation, either version 3 of the License, or 45 | * (at your option) any later version. 46 | * 47 | * This library is distributed in the hope that it will be useful, 48 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 49 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 50 | * GNU Lesser General Public License for more details. 51 | * 52 | * You should have received a copy of the GNU Lesser General Public License 53 | * along with this library. If not, see . 54 | */ 55 | 56 | /* Generic linker script for STM32 targets using libopencm3. */ 57 | 58 | /* Memory regions must be defined in the ld script which includes this one. */ 59 | 60 | /* Enforce emmition of the vector table. */ 61 | EXTERN (vector_table) 62 | 63 | /* Define the entry point of the output file. */ 64 | ENTRY(reset_handler) 65 | 66 | /* Define sections. */ 67 | SECTIONS 68 | { 69 | .text : { 70 | *(.vectors) /* Vector table */ 71 | KEEP (*(.plc_rte_sec)) /* PLC RTE ABI */ 72 | *(.text*) /* Program code */ 73 | . = ALIGN(4); 74 | *(.rodata*) /* Read-only data */ 75 | . = ALIGN(4); 76 | } >rom 77 | 78 | /* C++ Static constructors/destructors, also used for __attribute__ 79 | * ((constructor)) and the likes */ 80 | .preinit_array : { 81 | . = ALIGN(4); 82 | __preinit_array_start = .; 83 | KEEP (*(.preinit_array)) 84 | __preinit_array_end = .; 85 | } >rom 86 | .init_array : { 87 | . = ALIGN(4); 88 | __init_array_start = .; 89 | KEEP (*(SORT(.init_array.*))) 90 | KEEP (*(.init_array)) 91 | __init_array_end = .; 92 | } >rom 93 | .fini_array : { 94 | . = ALIGN(4); 95 | __fini_array_start = .; 96 | KEEP (*(.fini_array)) 97 | KEEP (*(SORT(.fini_array.*))) 98 | __fini_array_end = .; 99 | } >rom 100 | 101 | /* 102 | * Another section used by C++ stuff, appears when using newlib with 103 | * 64bit (long long) printf support 104 | */ 105 | .ARM.extab : { 106 | *(.ARM.extab*) 107 | } >rom 108 | .ARM.exidx : { 109 | __exidx_start = .; 110 | *(.ARM.exidx*) 111 | __exidx_end = .; 112 | } >rom 113 | 114 | . = ALIGN(4); 115 | _etext = .; 116 | 117 | .data : { 118 | _data = .; 119 | *(.data*) /* Read-write initialized data */ 120 | . = ALIGN(4); 121 | _edata = .; 122 | } >ram AT >rom 123 | _data_loadaddr = LOADADDR(.data); 124 | 125 | .bss : { 126 | *(.bss*) /* Read-write zero initialized data */ 127 | *(COMMON) 128 | . = ALIGN(4); 129 | _ebss = .; 130 | } >ram 131 | 132 | . = ALIGN(4); 133 | end = .; 134 | } 135 | 136 | -------------------------------------------------------------------------------- /src/bsp/nuc-247-0/plc_iom_reg.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | 14 | PLC_IOM_METH_DECLS(plc_dio); 15 | PLC_IOM_METH_DECLS(plc_mb); 16 | PLC_IOM_METH_DECLS(plc_diag); 17 | PLC_IOM_METH_DECLS(plc_hmi); 18 | 19 | const plc_io_metods_t plc_iom_registry[] = 20 | { 21 | PLC_IOM_RECORD(plc_diag), 22 | PLC_IOM_RECORD(plc_dio), 23 | PLC_IOM_RECORD(plc_mb), 24 | PLC_IOM_RECORD(plc_hmi) 25 | }; 26 | //Must be declared after plc_iom_registry 27 | PLC_IOM_REG_SZ_DECL; 28 | 29 | uint8_t mid_from_pid(uint16_t proto) 30 | { 31 | switch (proto) 32 | { 33 | case 0: 34 | return 0; 35 | case 1: 36 | return 1; 37 | case 2: 38 | return 2; 39 | case 4: //lost 3 somewhere? 40 | return 3; 41 | default: 42 | return PLC_IOM_MID_ERROR; 43 | } 44 | return PLC_IOM_MID_ERROR; 45 | } 46 | -------------------------------------------------------------------------------- /src/bsp/nuc-247-0/plc_tick.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | #include 13 | #include 14 | #include 15 | #include 16 | 17 | static bool systick_set_period(uint32_t period, uint32_t ahb, uint8_t clk_source) 18 | { 19 | if (period >= (STK_RVR_RELOAD/ahb)) 20 | { 21 | return false; 22 | } 23 | else 24 | { 25 | systick_set_clocksource( clk_source ); 26 | systick_set_reload( ahb * period - 1 ); 27 | return true; 28 | } 29 | } 30 | 31 | //Минимальный период в нС. 32 | #define TICK_MIN_PER 100000ULL 33 | //Пороговый период 34 | #define TICK_THR_PER 500000000ULL 35 | //Частота в МГц 36 | #define RCC_AHB_FREQ 120UL 37 | 38 | //Контроллер системного таймера. 39 | static frac_div_t systick_ctrl; 40 | 41 | //Состояние системного таймера 42 | #define TICK_STATE_HIGH 0 43 | #define TICK_STATE_MID 1 44 | #define TICK_STATE_LOW 2 45 | static uint32_t tick_state = TICK_STATE_HIGH; 46 | 47 | volatile bool plc_tick_flag = false; 48 | 49 | extern void plc_irq_stub(void); 50 | 51 | extern bool plc_dbg_mode; 52 | extern volatile uint32_t plc_hw_status; 53 | 54 | void sys_tick_handler(void) 55 | { 56 | //Soft watchdog 57 | if (plc_tick_flag) 58 | { 59 | plc_irq_stub(); 60 | if (plc_dbg_mode) 61 | { 62 | plc_hw_status |= PLC_HW_ERR_DEADLINE; 63 | } 64 | else 65 | { 66 | plc_irq_stub(); 67 | } 68 | } 69 | 70 | switch (tick_state) 71 | { 72 | case TICK_STATE_MID: 73 | case TICK_STATE_HIGH: 74 | default: 75 | systick_set_reload(RCC_AHB_FREQ * (uint32_t)frac_div_icalc( &systick_ctrl ) - 1); 76 | plc_tick_flag = true; 77 | break; 78 | 79 | case TICK_STATE_LOW: 80 | plc_tick_flag = frac_div_run(&systick_ctrl); 81 | break; 82 | } 83 | } 84 | 85 | //Tick period in ns 86 | void plc_tick_setup( uint64_t tick_next, uint64_t tick_period ) 87 | { 88 | (void)tick_next;//disable warning 89 | 90 | if (TICK_MIN_PER > tick_period) 91 | { 92 | tick_period = TICK_MIN_PER; 93 | } 94 | 95 | if (TICK_THR_PER > tick_period) 96 | { 97 | //Переменная частота работы системного таймера. 98 | if (systick_set_period((uint32_t)(tick_period/1000ULL), RCC_AHB_FREQ, STK_CSR_CLKSOURCE_AHB)) 99 | { 100 | //Примерно до 0.1с 101 | tick_state = TICK_STATE_HIGH; 102 | frac_div_init(&systick_ctrl, tick_period, 1000ULL); //Коррекция периода 103 | } 104 | else 105 | { 106 | //До 0.5с 107 | tick_state = TICK_STATE_MID; 108 | systick_set_period((uint32_t)(tick_period/8000ULL), RCC_AHB_FREQ, STK_CSR_CLKSOURCE_AHB_DIV8); 109 | frac_div_init(&systick_ctrl, tick_period, 8000ULL); //Коррекция периода 110 | } 111 | } 112 | else 113 | { 114 | //Постоянная частота работы системного таймера. 115 | tick_state = TICK_STATE_LOW; 116 | systick_set_period(500, RCC_AHB_FREQ, STK_CSR_CLKSOURCE_AHB);//500мкс 117 | frac_div_init(&systick_ctrl, tick_period, 500000ULL); 118 | } 119 | 120 | systick_counter_enable(); 121 | systick_interrupt_enable(); 122 | } 123 | -------------------------------------------------------------------------------- /src/bsp/nuc-247-0/plc_wait_tmr.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | 11 | #include 12 | #include 13 | #include 14 | 15 | 16 | #include 17 | #include 18 | #include 19 | 20 | void plc_wait_tmr_init(void) 21 | { 22 | //Wait timer config, basic timers TIM6 and TIM7 may be used 23 | rcc_periph_clock_enable(PLC_WAIT_TMR_PERIPH); 24 | 25 | timer_reset (PLC_WAIT_TMR); 26 | timer_set_prescaler (PLC_WAIT_TMR, ((2*rcc_apb1_frequency)/1000000ul - 1)); //1MHz 27 | timer_disable_preload (PLC_WAIT_TMR); 28 | timer_continuous_mode (PLC_WAIT_TMR); 29 | timer_set_period (PLC_WAIT_TMR, 100); //10KHz 30 | 31 | timer_enable_counter (PLC_WAIT_TMR); 32 | timer_enable_irq (PLC_WAIT_TMR, TIM_DIER_UIE); 33 | 34 | nvic_enable_irq(PLC_WAIT_TMR_VECTOR); 35 | } 36 | 37 | volatile uint32_t plc_sys_timer = 0; 38 | volatile uint32_t plc_wait_cnt = 0; 39 | 40 | extern void plc_hmi_vout_poll(void); 41 | extern void _plc_rtc_poll(void); 42 | 43 | void PLC_WAIT_TMR_ISR(void) 44 | { 45 | if (timer_get_flag(PLC_WAIT_TMR, TIM_SR_UIF)) 46 | { 47 | /* Clear compare interrupt flag. */ 48 | timer_clear_flag(PLC_WAIT_TMR, TIM_SR_UIF); 49 | 50 | plc_hmi_vout_poll(); 51 | _plc_rtc_poll(); 52 | 53 | plc_wait_cnt++; 54 | if (10 <= plc_wait_cnt) 55 | { 56 | plc_wait_cnt = 0; 57 | 58 | plc_sys_timer++; 59 | plc_iom_tick(); 60 | } 61 | } 62 | } 63 | -------------------------------------------------------------------------------- /src/bsp/nuc-247-0/stm32f205xC-app.ld: -------------------------------------------------------------------------------- 1 | /* Linker script for STM32F205xV Cortex-M3 ARM MCU */ 2 | 3 | /* Copyright (C)2013-2016, Philip Munts, President, Munts AM Corp. */ 4 | /* */ 5 | /* Redistribution and use in source and binary forms, with or without */ 6 | /* modification, are permitted provided that the following conditions are met: */ 7 | /* */ 8 | /* * Redistributions of source code must retain the above copyright notice, */ 9 | /* this list of conditions and the following disclaimer. */ 10 | /* */ 11 | /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ 12 | /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */ 13 | /* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */ 14 | /* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */ 15 | /* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */ 16 | /* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */ 17 | /* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS */ 18 | /* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN */ 19 | /* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) */ 20 | /* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */ 21 | /* POSSIBILITY OF SUCH DAMAGE. */ 22 | 23 | MEMORY 24 | { 25 | flash (rx) : ORIGIN = 0x08008000, LENGTH = 224K 26 | ram (rwx) : ORIGIN = 0x20002000, LENGTH = 84K 27 | ccm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K 28 | } 29 | 30 | __rom_start__ = ORIGIN(flash); 31 | __rom_size__ = LENGTH(flash); 32 | __ram_start__ = ORIGIN(ram); 33 | __ram_size__ = LENGTH(ram); 34 | __ram_end__ = __ram_start__ + __ram_size__; 35 | _plc_sstart = __ram_end__; /* Top of RAM */ 36 | 37 | SECTIONS 38 | { 39 | .text : { 40 | KEEP(*(.plc_app_abi_sec)) /* PLC APP ABI */ 41 | KEEP(*(.plc_md5_sec)) /* PLC APP ABI */ 42 | *(.text*) /* Program code */ 43 | KEEP(*(.rodata*)) /* Read only data */ 44 | 45 | . = ALIGN(4); 46 | _plc_pa_start = .; 47 | KEEP(*(.preinit_array)) /* Preinitarray */ 48 | _plc_pa_end = .; 49 | 50 | . = ALIGN(4); 51 | _plc_ia_start = .; 52 | KEEP (*(SORT(.init_array.*))) 53 | KEEP(*(.ctors)) /*Construcrs*/ 54 | _plc_ia_end = .; 55 | 56 | . = ALIGN(4); 57 | _plc_fia_start = .; 58 | KEEP(*(.fini_array)) /*Destructors */ 59 | KEEP (*(SORT(.fini_array.*))) 60 | _plc_fia_end = .; 61 | 62 | } >flash 63 | 64 | .data : ALIGN(16) { 65 | _plc_data_start = .; /* Used in PLC startup */ 66 | *(.data*) /* Initialized data */ 67 | _plc_data_end = .; /* Used in PLC startup */ 68 | } >ram AT > flash 69 | _plc_data_loadaddr = LOADADDR(.data); 70 | 71 | .bss (NOLOAD) : ALIGN(16) { 72 | *(.bss*) /* Uninitialized data */ 73 | *(COMMON) /* Common data */ 74 | _plc_bss_end = .; /* Used in PLC startup */ 75 | } >ram 76 | 77 | /* C++ exception unwinding stuff--needed by some toolchains */ 78 | 79 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >flash 80 | 81 | __exidx_start = .; 82 | .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >flash 83 | __exidx_end = .; 84 | 85 | 86 | ._plc_check : 87 | { 88 | KEEP(*(.plc_check_sec)) /* PLC APP ABI */ 89 | } > flash 90 | } 91 | 92 | /* Firmware entry point */ 93 | 94 | ENTRY(fake_start) 95 | 96 | -------------------------------------------------------------------------------- /src/bsp/nuc-247-0/stm32f205xC-rte.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the libopencm3 project. 3 | * 4 | * Copyright (C) 2009 Uwe Hermann 5 | * Copyright (C) 2011 Stephen Caudle 6 | * 7 | * This library is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU Lesser General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This library is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU Lesser General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU Lesser General Public License 18 | * along with this library. If not, see . 19 | */ 20 | 21 | /* Linker script for ST STM32F4DISCOVERY (STM32F205VC, 256K flash, 128K RAM). */ 22 | 23 | /* Define memory regions. */ 24 | MEMORY 25 | { 26 | rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K 27 | app_flash (rx) : ORIGIN = 0x08008000, LENGTH = 224K 28 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K 29 | appram (rwx) : ORIGIN = 0x20002000, LENGTH = 84K 30 | } 31 | 32 | PROVIDE(_stack = ORIGIN(appram) + LENGTH(appram)); 33 | PROVIDE(_app_start = ORIGIN(app_flash) ); 34 | PROVIDE(_app_end = _app_start + LENGTH(app_flash) ); 35 | 36 | /* Include the common ld script. */ 37 | /* 38 | * This file is part of the libopencm3 project. 39 | * 40 | * Copyright (C) 2009 Uwe Hermann 41 | * 42 | * This library is free software: you can redistribute it and/or modify 43 | * it under the terms of the GNU Lesser General Public License as published by 44 | * the Free Software Foundation, either version 3 of the License, or 45 | * (at your option) any later version. 46 | * 47 | * This library is distributed in the hope that it will be useful, 48 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 49 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 50 | * GNU Lesser General Public License for more details. 51 | * 52 | * You should have received a copy of the GNU Lesser General Public License 53 | * along with this library. If not, see . 54 | */ 55 | 56 | /* Generic linker script for STM32 targets using libopencm3. */ 57 | 58 | /* Memory regions must be defined in the ld script which includes this one. */ 59 | 60 | /* Enforce emmition of the vector table. */ 61 | EXTERN (vector_table) 62 | 63 | /* Define the entry point of the output file. */ 64 | ENTRY(reset_handler) 65 | 66 | /* Define sections. */ 67 | SECTIONS 68 | { 69 | .text : { 70 | *(.vectors) /* Vector table */ 71 | KEEP (*(.plc_rte_sec)) /* PLC RTE ABI */ 72 | *(.text*) /* Program code */ 73 | . = ALIGN(4); 74 | *(.rodata*) /* Read-only data */ 75 | . = ALIGN(4); 76 | } >rom 77 | 78 | /* C++ Static constructors/destructors, also used for __attribute__ 79 | * ((constructor)) and the likes */ 80 | .preinit_array : { 81 | . = ALIGN(4); 82 | __preinit_array_start = .; 83 | KEEP (*(.preinit_array)) 84 | __preinit_array_end = .; 85 | } >rom 86 | .init_array : { 87 | . = ALIGN(4); 88 | __init_array_start = .; 89 | KEEP (*(SORT(.init_array.*))) 90 | KEEP (*(.init_array)) 91 | __init_array_end = .; 92 | } >rom 93 | .fini_array : { 94 | . = ALIGN(4); 95 | __fini_array_start = .; 96 | KEEP (*(.fini_array)) 97 | KEEP (*(SORT(.fini_array.*))) 98 | __fini_array_end = .; 99 | } >rom 100 | 101 | /* 102 | * Another section used by C++ stuff, appears when using newlib with 103 | * 64bit (long long) printf support 104 | */ 105 | .ARM.extab : { 106 | *(.ARM.extab*) 107 | } >rom 108 | .ARM.exidx : { 109 | __exidx_start = .; 110 | *(.ARM.exidx*) 111 | __exidx_end = .; 112 | } >rom 113 | 114 | . = ALIGN(4); 115 | _etext = .; 116 | 117 | .data : { 118 | _data = .; 119 | *(.data*) /* Read-write initialized data */ 120 | . = ALIGN(4); 121 | _edata = .; 122 | } >ram AT >rom 123 | _data_loadaddr = LOADADDR(.data); 124 | 125 | .bss : { 126 | *(.bss*) /* Read-write zero initialized data */ 127 | *(COMMON) 128 | . = ALIGN(4); 129 | _ebss = .; 130 | } >ram 131 | 132 | . = ALIGN(4); 133 | end = .; 134 | } 135 | 136 | -------------------------------------------------------------------------------- /src/bsp/nuc-247-1/plc_iom_reg.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | 14 | PLC_IOM_METH_DECLS(plc_dio); 15 | PLC_IOM_METH_DECLS(plc_mb); 16 | PLC_IOM_METH_DECLS(plc_diag); 17 | PLC_IOM_METH_DECLS(plc_hmi); 18 | PLC_IOM_METH_DECLS(plc_mbm); 19 | 20 | const plc_io_metods_t plc_iom_registry[] = 21 | { 22 | PLC_IOM_RECORD(plc_diag), 23 | PLC_IOM_RECORD(plc_dio), 24 | PLC_IOM_RECORD(plc_mb), 25 | PLC_IOM_RECORD(plc_hmi), 26 | PLC_IOM_RECORD(plc_mbm) 27 | }; 28 | //Must be declared after plc_iom_registry 29 | PLC_IOM_REG_SZ_DECL; 30 | 31 | uint8_t mid_from_pid(uint16_t proto) 32 | { 33 | switch (proto) 34 | { 35 | case 0: 36 | return 0; 37 | case 1: 38 | return 1; 39 | case 2: 40 | return 2; 41 | case 4: 42 | return 3; 43 | case 3: 44 | return 4; 45 | default: 46 | return PLC_IOM_MID_ERROR; 47 | } 48 | return PLC_IOM_MID_ERROR; 49 | } 50 | -------------------------------------------------------------------------------- /src/bsp/nuc-247-1/plc_wait_tmr.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | 11 | #include 12 | #include 13 | #include 14 | 15 | 16 | #include 17 | #include 18 | #include 19 | 20 | void plc_wait_tmr_init(void) 21 | { 22 | //Wait timer config, basic timers TIM6 and TIM7 may be used 23 | rcc_periph_clock_enable(PLC_WAIT_TMR_PERIPH); 24 | 25 | timer_reset (PLC_WAIT_TMR); 26 | timer_set_prescaler (PLC_WAIT_TMR, ((2*rcc_apb1_frequency)/1000000ul - 1)); //1MHz 27 | timer_disable_preload (PLC_WAIT_TMR); 28 | timer_continuous_mode (PLC_WAIT_TMR); 29 | timer_set_period (PLC_WAIT_TMR, 100); //10KHz 30 | 31 | timer_enable_counter (PLC_WAIT_TMR); 32 | timer_enable_irq (PLC_WAIT_TMR, TIM_DIER_UIE); 33 | 34 | nvic_enable_irq(PLC_WAIT_TMR_VECTOR); 35 | } 36 | 37 | volatile uint32_t plc_sys_timer = 0; 38 | volatile uint32_t plc_wait_cnt = 0; 39 | 40 | extern void plc_hmi_vout_poll(void); 41 | extern void _plc_rtc_poll(void); 42 | 43 | void PLC_WAIT_TMR_ISR(void) 44 | { 45 | if (timer_get_flag(PLC_WAIT_TMR, TIM_SR_UIF)) 46 | { 47 | /* Clear compare interrupt flag. */ 48 | timer_clear_flag(PLC_WAIT_TMR, TIM_SR_UIF); 49 | 50 | plc_hmi_vout_poll(); 51 | _plc_rtc_poll(); 52 | 53 | plc_wait_cnt++; 54 | if (10 <= plc_wait_cnt) 55 | { 56 | plc_wait_cnt = 0; 57 | 58 | plc_sys_timer++; 59 | plc_iom_tick(); 60 | } 61 | } 62 | } 63 | -------------------------------------------------------------------------------- /src/bsp/nuc-247-1/stm32f205xC-app.ld: -------------------------------------------------------------------------------- 1 | /* Linker script for STM32F205xV Cortex-M3 ARM MCU */ 2 | 3 | /* Copyright (C)2013-2016, Philip Munts, President, Munts AM Corp. */ 4 | /* */ 5 | /* Redistribution and use in source and binary forms, with or without */ 6 | /* modification, are permitted provided that the following conditions are met: */ 7 | /* */ 8 | /* * Redistributions of source code must retain the above copyright notice, */ 9 | /* this list of conditions and the following disclaimer. */ 10 | /* */ 11 | /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ 12 | /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */ 13 | /* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */ 14 | /* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */ 15 | /* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */ 16 | /* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */ 17 | /* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS */ 18 | /* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN */ 19 | /* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) */ 20 | /* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */ 21 | /* POSSIBILITY OF SUCH DAMAGE. */ 22 | 23 | MEMORY 24 | { 25 | flash (rx) : ORIGIN = 0x08008000, LENGTH = 224K 26 | ram (rwx) : ORIGIN = 0x20002000, LENGTH = 84K 27 | ccm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K 28 | } 29 | 30 | __rom_start__ = ORIGIN(flash); 31 | __rom_size__ = LENGTH(flash); 32 | __ram_start__ = ORIGIN(ram); 33 | __ram_size__ = LENGTH(ram); 34 | __ram_end__ = __ram_start__ + __ram_size__; 35 | _plc_sstart = __ram_end__; /* Top of RAM */ 36 | 37 | SECTIONS 38 | { 39 | .text : { 40 | KEEP(*(.plc_app_abi_sec)) /* PLC APP ABI */ 41 | KEEP(*(.plc_md5_sec)) /* PLC APP ABI */ 42 | *(.text*) /* Program code */ 43 | KEEP(*(.rodata*)) /* Read only data */ 44 | 45 | . = ALIGN(4); 46 | _plc_pa_start = .; 47 | KEEP(*(.preinit_array)) /* Preinitarray */ 48 | _plc_pa_end = .; 49 | 50 | . = ALIGN(4); 51 | _plc_ia_start = .; 52 | KEEP (*(SORT(.init_array.*))) 53 | KEEP(*(.ctors)) /*Construcrs*/ 54 | _plc_ia_end = .; 55 | 56 | . = ALIGN(4); 57 | _plc_fia_start = .; 58 | KEEP(*(.fini_array)) /*Destructors */ 59 | KEEP (*(SORT(.fini_array.*))) 60 | _plc_fia_end = .; 61 | 62 | } >flash 63 | 64 | .data : ALIGN(16) { 65 | _plc_data_start = .; /* Used in PLC startup */ 66 | *(.data*) /* Initialized data */ 67 | _plc_data_end = .; /* Used in PLC startup */ 68 | } >ram AT > flash 69 | _plc_data_loadaddr = LOADADDR(.data); 70 | 71 | .bss (NOLOAD) : ALIGN(16) { 72 | *(.bss*) /* Uninitialized data */ 73 | *(COMMON) /* Common data */ 74 | _plc_bss_end = .; /* Used in PLC startup */ 75 | } >ram 76 | 77 | /* C++ exception unwinding stuff--needed by some toolchains */ 78 | 79 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >flash 80 | 81 | __exidx_start = .; 82 | .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >flash 83 | __exidx_end = .; 84 | 85 | 86 | ._plc_check : 87 | { 88 | KEEP(*(.plc_check_sec)) /* PLC APP ABI */ 89 | } > flash 90 | } 91 | 92 | /* Firmware entry point */ 93 | 94 | ENTRY(fake_start) 95 | 96 | -------------------------------------------------------------------------------- /src/bsp/nuc-247-1/stm32f205xC-rte.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the libopencm3 project. 3 | * 4 | * Copyright (C) 2009 Uwe Hermann 5 | * Copyright (C) 2011 Stephen Caudle 6 | * 7 | * This library is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU Lesser General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This library is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU Lesser General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU Lesser General Public License 18 | * along with this library. If not, see . 19 | */ 20 | 21 | /* Linker script for ST STM32F4DISCOVERY (STM32F205VC, 256K flash, 128K RAM). */ 22 | 23 | /* Define memory regions. */ 24 | MEMORY 25 | { 26 | rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K 27 | app_flash (rx) : ORIGIN = 0x08008000, LENGTH = 224K 28 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K 29 | appram (rwx) : ORIGIN = 0x20002000, LENGTH = 84K 30 | } 31 | 32 | PROVIDE(_stack = ORIGIN(appram) + LENGTH(appram)); 33 | PROVIDE(_app_start = ORIGIN(app_flash) ); 34 | PROVIDE(_app_end = _app_start + LENGTH(app_flash) ); 35 | 36 | /* Include the common ld script. */ 37 | /* 38 | * This file is part of the libopencm3 project. 39 | * 40 | * Copyright (C) 2009 Uwe Hermann 41 | * 42 | * This library is free software: you can redistribute it and/or modify 43 | * it under the terms of the GNU Lesser General Public License as published by 44 | * the Free Software Foundation, either version 3 of the License, or 45 | * (at your option) any later version. 46 | * 47 | * This library is distributed in the hope that it will be useful, 48 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 49 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 50 | * GNU Lesser General Public License for more details. 51 | * 52 | * You should have received a copy of the GNU Lesser General Public License 53 | * along with this library. If not, see . 54 | */ 55 | 56 | /* Generic linker script for STM32 targets using libopencm3. */ 57 | 58 | /* Memory regions must be defined in the ld script which includes this one. */ 59 | 60 | /* Enforce emmition of the vector table. */ 61 | EXTERN (vector_table) 62 | 63 | /* Define the entry point of the output file. */ 64 | ENTRY(reset_handler) 65 | 66 | /* Define sections. */ 67 | SECTIONS 68 | { 69 | .text : { 70 | *(.vectors) /* Vector table */ 71 | KEEP (*(.plc_rte_sec)) /* PLC RTE ABI */ 72 | *(.text*) /* Program code */ 73 | . = ALIGN(4); 74 | *(.rodata*) /* Read-only data */ 75 | . = ALIGN(4); 76 | } >rom 77 | 78 | /* C++ Static constructors/destructors, also used for __attribute__ 79 | * ((constructor)) and the likes */ 80 | .preinit_array : { 81 | . = ALIGN(4); 82 | __preinit_array_start = .; 83 | KEEP (*(.preinit_array)) 84 | __preinit_array_end = .; 85 | } >rom 86 | .init_array : { 87 | . = ALIGN(4); 88 | __init_array_start = .; 89 | KEEP (*(SORT(.init_array.*))) 90 | KEEP (*(.init_array)) 91 | __init_array_end = .; 92 | } >rom 93 | .fini_array : { 94 | . = ALIGN(4); 95 | __fini_array_start = .; 96 | KEEP (*(.fini_array)) 97 | KEEP (*(SORT(.fini_array.*))) 98 | __fini_array_end = .; 99 | } >rom 100 | 101 | /* 102 | * Another section used by C++ stuff, appears when using newlib with 103 | * 64bit (long long) printf support 104 | */ 105 | .ARM.extab : { 106 | *(.ARM.extab*) 107 | } >rom 108 | .ARM.exidx : { 109 | __exidx_start = .; 110 | *(.ARM.exidx*) 111 | __exidx_end = .; 112 | } >rom 113 | 114 | . = ALIGN(4); 115 | _etext = .; 116 | 117 | .data : { 118 | _data = .; 119 | *(.data*) /* Read-write initialized data */ 120 | . = ALIGN(4); 121 | _edata = .; 122 | } >ram AT >rom 123 | _data_loadaddr = LOADADDR(.data); 124 | 125 | .bss : { 126 | *(.bss*) /* Read-write zero initialized data */ 127 | *(COMMON) 128 | . = ALIGN(4); 129 | _ebss = .; 130 | } >ram 131 | 132 | . = ALIGN(4); 133 | end = .; 134 | } 135 | 136 | -------------------------------------------------------------------------------- /src/bsp/stm32f4/plc_backup.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | #include 13 | #include 14 | #include 15 | 16 | #include 17 | #include 18 | 19 | #include 20 | 21 | //#define PLC_BKP_SIZE 4096 22 | 23 | #define PLC_UVP(a) ((void *)(a)) 24 | //Use RTC backup registers for validation 25 | #define PLC_BKP_VER1 MMIO32(RTC_BKP_BASE + PLC_BKP_VER1_OFFSET) 26 | #define PLC_BKP_VER2 MMIO32(RTC_BKP_BASE + PLC_BKP_VER2_OFFSET) 27 | //Use BackupSRAM to store retain vars 28 | //#define PLC_BKP_START PLC_UVP(BKPSRAM_BASE) 29 | #define PLC_BKP_START (uint32_t *)(RTC_BKP_BASE + PLC_BKP_REG_OFFSET) 30 | 31 | 32 | //watches RTC_BKP_BASE 0x40002850 33 | // PLC_BKP_START 0x40024000 34 | 35 | #define PLC_BKP_REG_NUM 10 36 | #define PLC_BKP_SIZE (PLC_BKP_REG_NUM*4ul) 37 | static uint32_t plc_backup_buff[PLC_BKP_REG_NUM]; 38 | static uint32_t * plc_backup_reg = PLC_BKP_START; 39 | 40 | void plc_backup_init(void) 41 | { 42 | uint32_t i; 43 | rcc_periph_clock_enable( RCC_PWR ); 44 | pwr_disable_backup_domain_write_protect(); 45 | 46 | PWR_CSR |= PWR_CSR_BRE; // Backup regulator enable 47 | while( 0 == ( PWR_CSR & PWR_CSR_BRR ) );// Wait for backup regulator ready 48 | 49 | pwr_enable_backup_domain_write_protect(); 50 | 51 | //rcc_periph_clock_enable( RCC_BKPSRAM ); 52 | for(i = 0; i < PLC_BKP_REG_NUM; i++) 53 | { 54 | plc_backup_buff[i] = plc_backup_reg[i]; 55 | } 56 | } 57 | 58 | void plc_backup_reset(void) 59 | { 60 | pwr_disable_backup_domain_write_protect(); 61 | PLC_BKP_VER1++; 62 | pwr_enable_backup_domain_write_protect(); 63 | } 64 | 65 | void plc_backup_invalidate(void) 66 | { 67 | //pwr_disable_backup_domain_write_protect(); 68 | //PLC_BKP_VER1++; 69 | //pwr_enable_backup_domain_write_protect(); 70 | } 71 | 72 | void plc_backup_validate(void) 73 | { 74 | uint32_t i; 75 | pwr_disable_backup_domain_write_protect(); 76 | 77 | PLC_BKP_VER1++; 78 | 79 | for(i = 0; i < PLC_BKP_REG_NUM; i++) 80 | { 81 | plc_backup_reg[i] = plc_backup_buff[i]; 82 | } 83 | 84 | PLC_BKP_VER2 = PLC_BKP_VER1; 85 | pwr_enable_backup_domain_write_protect(); 86 | } 87 | 88 | int plc_backup_check(void) 89 | { 90 | if( PLC_BKP_VER1 != PLC_BKP_VER2 ) 91 | { 92 | return 0; 93 | } 94 | else 95 | { 96 | return 1; //Success, now may remind 97 | } 98 | } 99 | 100 | 101 | 102 | void plc_backup_remind(unsigned int offset, unsigned int count, void *p) 103 | { 104 | if(offset + count < PLC_BKP_SIZE) 105 | { 106 | memcpy( p, (void *)plc_backup_buff + offset, count ); 107 | } 108 | } 109 | 110 | void plc_backup_retain(unsigned int offset, unsigned int count, void *p) 111 | { 112 | if(offset + count < PLC_BKP_SIZE) 113 | { 114 | //pwr_disable_backup_domain_write_protect(); 115 | memcpy( (void *)plc_backup_buff + offset, p, count ); 116 | //pwr_enable_backup_domain_write_protect(); 117 | } 118 | } 119 | -------------------------------------------------------------------------------- /src/bsp/stm32f4/plc_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | */ 4 | 5 | #ifndef _PLC_CONFIG_H_ 6 | #define _PLC_CONFIG_H_ 7 | 8 | /* 9 | * NUC-227-DEV configuration! 10 | */ 11 | 12 | #include 13 | #include 14 | 15 | #define PLC_DISABLE_INTERRUPTS cm_disable_interrupts 16 | #define PLC_ENABLE_INTERRUPTS cm_enable_interrupts 17 | 18 | /* 19 | * PLC clocks 20 | */ 21 | #define PLC_HSE_CONFIG rcc_hse_16mhz_3v3 22 | 23 | /* 24 | * Debug USART 25 | */ 26 | #define DBG_USART USART1 27 | #define DBG_USART_PERIPH RCC_USART1 28 | #define DBG_USART_VECTOR NVIC_USART1_IRQ 29 | #define DBG_USART_ISR usart1_isr 30 | 31 | #define DBG_USART_TX_PORT GPIOA 32 | #define DBG_USART_RX_PORT GPIOA 33 | 34 | #define DBG_USART_TX_PIN GPIO9 35 | #define DBG_USART_RX_PIN GPIO10 36 | 37 | #define DBG_USART_TX_PERIPH RCC_GPIOA 38 | #define DBG_USART_RX_PERIPH RCC_GPIOA 39 | 40 | /* 41 | * Boot pin 42 | */ 43 | #define PLC_BOOT_PERIPH RCC_GPIOD 44 | #define PLC_BOOT_PORT GPIOD 45 | #define PLC_BOOT_PIN GPIO10 46 | 47 | /* 48 | * PLC LEDS 49 | */ 50 | #define PLC_LED1_PERIPH RCC_GPIOB 51 | #define PLC_LED1_PORT GPIOB 52 | #define PLC_LED1_PIN GPIO12 53 | 54 | #define PLC_LED2_PERIPH RCC_GPIOB 55 | #define PLC_LED2_PORT GPIOB 56 | #define PLC_LED2_PIN GPIO13 57 | 58 | #define PLC_LED3_PERIPH RCC_GPIOB 59 | #define PLC_LED3_PORT GPIOB 60 | #define PLC_LED3_PIN GPIO14 61 | 62 | extern void plc_heart_beat(void); 63 | 64 | #define PLC_BLINK() plc_heart_beat() 65 | 66 | /* 67 | * PLC Inputs 68 | */ 69 | #define PLC_I1_PERIPH RCC_GPIOE 70 | #define PLC_I1_PORT GPIOE 71 | #define PLC_I1_PIN GPIO0 72 | 73 | #define PLC_I2_PERIPH RCC_GPIOB 74 | #define PLC_I2_PORT GPIOB 75 | #define PLC_I2_PIN GPIO8 76 | 77 | #define PLC_I3_PERIPH RCC_GPIOB 78 | #define PLC_I3_PORT GPIOB 79 | #define PLC_I3_PIN GPIO6 80 | 81 | #define PLC_I4_PERIPH RCC_GPIOB 82 | #define PLC_I4_PORT GPIOB 83 | #define PLC_I4_PIN GPIO4 84 | 85 | #define PLC_I5_PERIPH RCC_GPIOD 86 | #define PLC_I5_PORT GPIOD 87 | #define PLC_I5_PIN GPIO6 88 | 89 | #define PLC_I6_PERIPH RCC_GPIOD 90 | #define PLC_I6_PORT GPIOD 91 | #define PLC_I6_PIN GPIO4 92 | 93 | #define PLC_I7_PERIPH RCC_GPIOD 94 | #define PLC_I7_PORT GPIOD 95 | #define PLC_I7_PIN GPIO5 96 | 97 | #define PLC_I8_PERIPH RCC_GPIOD 98 | #define PLC_I8_PORT GPIOD 99 | #define PLC_I8_PIN GPIO7 100 | 101 | /* 102 | * PLC Outputs 103 | */ 104 | #define PLC_O1_PERIPH RCC_GPIOE 105 | #define PLC_O1_PORT GPIOE 106 | #define PLC_O1_PIN GPIO1 107 | 108 | #define PLC_O2_PERIPH RCC_GPIOB 109 | #define PLC_O2_PORT GPIOB 110 | #define PLC_O2_PIN GPIO9 111 | 112 | #define PLC_O3_PERIPH RCC_GPIOB 113 | #define PLC_O3_PORT GPIOB 114 | #define PLC_O3_PIN GPIO7 115 | 116 | #define PLC_O4_PERIPH RCC_GPIOB 117 | #define PLC_O4_PORT GPIOB 118 | #define PLC_O4_PIN GPIO5 119 | 120 | /* 121 | * PLC system timer 122 | */ 123 | #define PLC_WAIT_TMR_PERIPH RCC_TIM7 124 | #define PLC_WAIT_TMR TIM7 125 | #define PLC_WAIT_TMR_VECTOR NVIC_TIM7_IRQ 126 | #define PLC_WAIT_TMR_ISR tim7_isr 127 | 128 | /* 129 | * Backup domain offsets 130 | */ 131 | #define PLC_BKP_VER1_OFFSET 0 132 | #define PLC_BKP_VER2_OFFSET 4 133 | #define PLC_BKP_RTC_IS_OK_OFFSET 8 134 | #define PLC_BKP_REG_OFFSET 12 135 | 136 | /* 137 | * PLC app abi 138 | */ 139 | #define PLC_APP ((plc_app_abi_t *)0x08008000) 140 | 141 | /* 142 | * PLC RTE Version 143 | */ 144 | #define PLC_RTE_VER_MAJOR 2 145 | #define PLC_RTE_VER_MINOR 0 146 | #define PLC_RTE_VER_PATCH 0 147 | 148 | /* 149 | * Logging 150 | */ 151 | #define LOG_LEVELS 4 152 | #define LOG_CRITICAL 0 153 | #define LOG_WARNING 1 154 | #define LOG_INFO 2 155 | #define LOG_DEBUG 3 156 | #endif /* _PLC_CONFIG_H_ */ 157 | -------------------------------------------------------------------------------- /src/bsp/stm32f4/plc_config_bak.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | */ 4 | #ifndef _PLC_CONFIG_H_ 5 | #define _PLC_CONFIG_H_ 6 | 7 | #include 8 | #include 9 | 10 | #define PLC_DISABLE_INTERRUPTS cm_disable_interrupts 11 | #define PLC_ENABLE_INTERRUPTS cm_enable_interrupts 12 | 13 | #define DBG_USART USART3 14 | #define DBG_USART_PERIPH RCC_USART3 15 | #define DBG_USART_VECTOR NVIC_USART3_IRQ 16 | #define DBG_USART_ISR usart3_isr 17 | 18 | #define DBG_USART_TX_PORT GPIOB 19 | #define DBG_USART_RX_PORT GPIOB 20 | 21 | #define DBG_USART_TX_PIN GPIO10 22 | #define DBG_USART_RX_PIN GPIO11 23 | 24 | #define DBG_USART_TX_PERIPH RCC_GPIOB 25 | #define DBG_USART_RX_PERIPH RCC_GPIOB 26 | 27 | #define PLC_BOOT_PERIPH RCC_GPIOD 28 | #define PLC_BOOT_PORT GPIOD 29 | #define PLC_BOOT_PIN GPIO10 30 | 31 | #define PLC_WAIT_TMR_PERIPH RCC_TIM7 32 | #define PLC_WAIT_TMR TIM7 33 | #define PLC_WAIT_TMR_VECTOR NVIC_TIM7_IRQ 34 | #define PLC_WAIT_TMR_ISR tim7_isr 35 | 36 | #define PLC_BKP_VER1_OFFSET 0 37 | #define PLC_BKP_VER2_OFFSET 4 38 | #define PLC_BKP_RTC_IS_OK_OFFSET 8 39 | 40 | #include 41 | 42 | #endif /* _PLC_CONFIG_H_ */ 43 | -------------------------------------------------------------------------------- /src/bsp/stm32f4/plc_serial.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nucleron/RTE/65341e5029a33f35f32de1fa41ba0276b89680b9/src/bsp/stm32f4/plc_serial.c -------------------------------------------------------------------------------- /src/bsp/stm32f4/plc_tick.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | #include 13 | #include 14 | 15 | static bool systick_set_period(uint32_t period, uint32_t ahb, uint8_t clk_source) 16 | { 17 | if (period >= (STK_RVR_RELOAD/ahb)) 18 | { 19 | return false; 20 | } 21 | else 22 | { 23 | systick_set_clocksource( clk_source ); 24 | systick_set_reload( ahb * period - 1 ); 25 | return true; 26 | } 27 | } 28 | 29 | //Минимальный период в нС. 30 | #define TICK_MIN_PER 100000ULL 31 | //Пороговый период 32 | #define TICK_THR_PER 500000000ULL 33 | //Частота в МГц 34 | #define RCC_AHB_FREQ 168UL 35 | 36 | //Контроллер системного таймера. 37 | static frac_div_t systick_ctrl; 38 | 39 | //Состояние системного таймера 40 | #define TICK_STATE_HIGH 0 41 | #define TICK_STATE_MID 1 42 | #define TICK_STATE_LOW 2 43 | static uint32_t tick_state = TICK_STATE_HIGH; 44 | 45 | void sys_tick_handler(void) 46 | { 47 | switch( tick_state ) 48 | { 49 | case TICK_STATE_MID: 50 | case TICK_STATE_HIGH: 51 | default: 52 | { 53 | systick_set_reload( RCC_AHB_FREQ * (uint32_t)frac_div_icalc( &systick_ctrl ) - 1 ); 54 | plc_tick_flag = true; 55 | break; 56 | } 57 | case TICK_STATE_LOW: 58 | { 59 | plc_tick_flag = frac_div_run( &systick_ctrl ); 60 | break; 61 | } 62 | } 63 | } 64 | 65 | bool plc_tick_flag = false; 66 | 67 | //Tick period in ns 68 | void plc_tick_setup( uint64_t tick_next, uint64_t tick_period ) 69 | { 70 | (void)tick_next;//disable warning 71 | 72 | if( tick_period < TICK_MIN_PER ) 73 | { 74 | tick_period = TICK_MIN_PER; 75 | } 76 | 77 | if( tick_period < TICK_THR_PER ) 78 | { 79 | //Переменная частота работы системного таймера. 80 | if( systick_set_period( (uint32_t)(tick_period/1000ULL), RCC_AHB_FREQ, STK_CSR_CLKSOURCE_AHB) ) 81 | { 82 | //Примерно до 0.1с 83 | tick_state = TICK_STATE_HIGH; 84 | frac_div_init( &systick_ctrl, tick_period, 1000ULL ); //Коррекция приода 85 | } 86 | else 87 | { 88 | //До 0.5с 89 | tick_state = TICK_STATE_MID; 90 | systick_set_period( (uint32_t)(tick_period/8000ULL), RCC_AHB_FREQ, STK_CSR_CLKSOURCE_AHB_DIV8); 91 | frac_div_init( &systick_ctrl, tick_period, 8000ULL ); //Коррекция периода 92 | } 93 | } 94 | else 95 | { 96 | //Постоянная частота работы системного таймера. 97 | tick_state = TICK_STATE_LOW; 98 | systick_set_period( 500, RCC_AHB_FREQ, STK_CSR_CLKSOURCE_AHB);//500мкс 99 | frac_div_init( &systick_ctrl, tick_period, 500000ULL ); 100 | } 101 | 102 | systick_counter_enable(); 103 | systick_interrupt_enable(); 104 | } 105 | -------------------------------------------------------------------------------- /src/bsp/stm32f4/plc_wait_tmr.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | 11 | #include 12 | #include 13 | #include 14 | 15 | 16 | #include 17 | #include 18 | #include 19 | 20 | void plc_wait_tmr_init(void) 21 | { 22 | //Wait timer config, basic timers TIM6 and TIM7 may be used 23 | rcc_periph_clock_enable( PLC_WAIT_TMR_PERIPH ); 24 | 25 | timer_reset ( PLC_WAIT_TMR ); 26 | timer_set_prescaler ( PLC_WAIT_TMR, (( rcc_apb1_frequency * 2 )/ 1000000 - 1) ); //1MHz 27 | timer_disable_preload ( PLC_WAIT_TMR ); 28 | timer_continuous_mode ( PLC_WAIT_TMR ); 29 | timer_set_period ( PLC_WAIT_TMR, 1000 ); //1KHz 30 | 31 | timer_enable_counter ( PLC_WAIT_TMR ); 32 | timer_enable_irq ( PLC_WAIT_TMR, TIM_DIER_UIE); 33 | 34 | nvic_enable_irq( PLC_WAIT_TMR_VECTOR ); 35 | } 36 | 37 | uint32_t plc_sys_timer = 0; 38 | 39 | void PLC_WAIT_TMR_ISR(void) 40 | { 41 | if (timer_get_flag(PLC_WAIT_TMR, TIM_SR_UIF)) 42 | { 43 | 44 | /* Clear compare interrupt flag. */ 45 | timer_clear_flag(PLC_WAIT_TMR, TIM_SR_UIF); 46 | plc_sys_timer++; 47 | plc_iom_tick(); 48 | } 49 | } 50 | -------------------------------------------------------------------------------- /src/bsp/stm32f4/stm32f4disco-app.ld: -------------------------------------------------------------------------------- 1 | /* Linker script for STM32F405RG Cortex-M4 ARM MCU */ 2 | 3 | /* Copyright (C)2013-2016, Philip Munts, President, Munts AM Corp. */ 4 | /* */ 5 | /* Redistribution and use in source and binary forms, with or without */ 6 | /* modification, are permitted provided that the following conditions are met: */ 7 | /* */ 8 | /* * Redistributions of source code must retain the above copyright notice, */ 9 | /* this list of conditions and the following disclaimer. */ 10 | /* */ 11 | /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ 12 | /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */ 13 | /* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */ 14 | /* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */ 15 | /* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */ 16 | /* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */ 17 | /* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS */ 18 | /* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN */ 19 | /* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) */ 20 | /* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */ 21 | /* POSSIBILITY OF SUCH DAMAGE. */ 22 | 23 | MEMORY 24 | { 25 | flash (rx) : ORIGIN = 0x08008000, LENGTH = 992K 26 | ram (rwx) : ORIGIN = 0x20002000, LENGTH = 120K 27 | ccm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K 28 | } 29 | 30 | __rom_start__ = ORIGIN(flash); 31 | __rom_size__ = LENGTH(flash); 32 | __ram_start__ = ORIGIN(ram); 33 | __ram_size__ = LENGTH(ram); 34 | __ram_end__ = __ram_start__ + __ram_size__; 35 | _plc_sstart = __ram_end__; /* Top of RAM */ 36 | 37 | SECTIONS 38 | { 39 | .text : { 40 | KEEP(*(.plc_app_abi_sec)) /* PLC APP ABI */ 41 | KEEP(*(.plc_md5_sec)) /* PLC APP ABI */ 42 | *(.text*) /* Program code */ 43 | KEEP(*(.rodata*)) /* Read only data */ 44 | 45 | . = ALIGN(4); 46 | _plc_pa_start = .; 47 | KEEP(*(.preinit_array)) /* Preinitarray */ 48 | _plc_pa_end = .; 49 | 50 | . = ALIGN(4); 51 | _plc_ia_start = .; 52 | KEEP (*(SORT(.init_array.*))) 53 | KEEP(*(.ctors)) /*Construcrs*/ 54 | _plc_ia_end = .; 55 | 56 | . = ALIGN(4); 57 | _plc_fia_start = .; 58 | KEEP(*(.fini_array)) /*Destructors */ 59 | KEEP (*(SORT(.fini_array.*))) 60 | _plc_fia_end = .; 61 | 62 | } >flash 63 | 64 | .data : ALIGN(16) { 65 | _plc_data_start = .; /* Used in PLC startup */ 66 | *(.data*) /* Initialized data */ 67 | _plc_data_end = .; /* Used in PLC startup */ 68 | } >ram AT > flash 69 | _plc_data_loadaddr = LOADADDR(.data); 70 | 71 | .bss (NOLOAD) : ALIGN(16) { 72 | *(.bss*) /* Uninitialized data */ 73 | *(COMMON) /* Common data */ 74 | _plc_bss_end = .; /* Used in PLC startup */ 75 | } >ram 76 | 77 | /* C++ exception unwinding stuff--needed by some toolchains */ 78 | 79 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >flash 80 | 81 | __exidx_start = .; 82 | .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >flash 83 | __exidx_end = .; 84 | 85 | 86 | ._plc_check : 87 | { 88 | KEEP(*(.plc_check_sec)) /* PLC APP ABI */ 89 | } > flash 90 | } 91 | 92 | /* Firmware entry point */ 93 | 94 | ENTRY(fake_start) 95 | 96 | -------------------------------------------------------------------------------- /src/bsp/stm32f4/stm32f4disco-dev.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the libopencm3 project. 3 | * 4 | * Copyright (C) 2009 Uwe Hermann 5 | * Copyright (C) 2011 Stephen Caudle 6 | * 7 | * This library is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU Lesser General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This library is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU Lesser General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU Lesser General Public License 18 | * along with this library. If not, see . 19 | */ 20 | 21 | /* Linker script for ST STM32F4DISCOVERY (STM32F407VG, 1024K flash, 128K RAM). */ 22 | 23 | /* Define memory regions. */ 24 | MEMORY 25 | { 26 | rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K 27 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K 28 | } 29 | 30 | /* Include the common ld script. */ 31 | /* 32 | * This file is part of the libopencm3 project. 33 | * 34 | * Copyright (C) 2009 Uwe Hermann 35 | * 36 | * This library is free software: you can redistribute it and/or modify 37 | * it under the terms of the GNU Lesser General Public License as published by 38 | * the Free Software Foundation, either version 3 of the License, or 39 | * (at your option) any later version. 40 | * 41 | * This library is distributed in the hope that it will be useful, 42 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 43 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 44 | * GNU Lesser General Public License for more details. 45 | * 46 | * You should have received a copy of the GNU Lesser General Public License 47 | * along with this library. If not, see . 48 | */ 49 | 50 | /* Generic linker script for STM32 targets using libopencm3. */ 51 | 52 | /* Memory regions must be defined in the ld script which includes this one. */ 53 | 54 | /* Enforce emmition of the vector table. */ 55 | EXTERN (vector_table) 56 | 57 | /* Define the entry point of the output file. */ 58 | ENTRY(reset_handler) 59 | 60 | /* Define sections. */ 61 | SECTIONS 62 | { 63 | .text : { 64 | *(.vectors) /* Vector table */ 65 | *(.text*) /* Program code */ 66 | . = ALIGN(4); 67 | *(.rodata*) /* Read-only data */ 68 | . = ALIGN(4); 69 | } >rom 70 | 71 | /* C++ Static constructors/destructors, also used for __attribute__ 72 | * ((constructor)) and the likes */ 73 | .preinit_array : { 74 | . = ALIGN(4); 75 | __preinit_array_start = .; 76 | KEEP (*(.preinit_array)) 77 | __preinit_array_end = .; 78 | } >rom 79 | .init_array : { 80 | . = ALIGN(4); 81 | __init_array_start = .; 82 | KEEP (*(SORT(.init_array.*))) 83 | KEEP (*(.init_array)) 84 | __init_array_end = .; 85 | } >rom 86 | .fini_array : { 87 | . = ALIGN(4); 88 | __fini_array_start = .; 89 | KEEP (*(.fini_array)) 90 | KEEP (*(SORT(.fini_array.*))) 91 | __fini_array_end = .; 92 | } >rom 93 | 94 | /* 95 | * Another section used by C++ stuff, appears when using newlib with 96 | * 64bit (long long) printf support 97 | */ 98 | .ARM.extab : { 99 | *(.ARM.extab*) 100 | } >rom 101 | .ARM.exidx : { 102 | __exidx_start = .; 103 | *(.ARM.exidx*) 104 | __exidx_end = .; 105 | } >rom 106 | 107 | . = ALIGN(4); 108 | _etext = .; 109 | 110 | .data : { 111 | _data = .; 112 | *(.data*) /* Read-write initialized data */ 113 | . = ALIGN(4); 114 | _edata = .; 115 | } >ram AT >rom 116 | _data_loadaddr = LOADADDR(.data); 117 | 118 | .bss : { 119 | *(.bss*) /* Read-write zero initialized data */ 120 | *(COMMON) 121 | . = ALIGN(4); 122 | _ebss = .; 123 | } >ram 124 | 125 | /* 126 | * The .eh_frame section appears to be used for C++ exception handling. 127 | * You may need to fix this if you're using C++. 128 | */ 129 | ///DISCARD/ : { *(.eh_frame) } 130 | 131 | . = ALIGN(4); 132 | end = .; 133 | } 134 | 135 | PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); 136 | 137 | -------------------------------------------------------------------------------- /src/bsp/template/example-app.ld: -------------------------------------------------------------------------------- 1 | /* Linker script for STM32F205xV Cortex-M3 ARM MCU */ 2 | 3 | /* Copyright (C)2013-2016, Philip Munts, President, Munts AM Corp. */ 4 | /* */ 5 | /* Redistribution and use in source and binary forms, with or without */ 6 | /* modification, are permitted provided that the following conditions are met: */ 7 | /* */ 8 | /* * Redistributions of source code must retain the above copyright notice, */ 9 | /* this list of conditions and the following disclaimer. */ 10 | /* */ 11 | /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ 12 | /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */ 13 | /* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */ 14 | /* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */ 15 | /* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */ 16 | /* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */ 17 | /* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS */ 18 | /* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN */ 19 | /* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) */ 20 | /* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */ 21 | /* POSSIBILITY OF SUCH DAMAGE. */ 22 | 23 | MEMORY 24 | { 25 | flash (rx) : ORIGIN = 0x08008000, LENGTH = 224K 26 | ram (rwx) : ORIGIN = 0x20002000, LENGTH = 84K 27 | ccm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K 28 | } 29 | 30 | __rom_start__ = ORIGIN(flash); 31 | __rom_size__ = LENGTH(flash); 32 | __ram_start__ = ORIGIN(ram); 33 | __ram_size__ = LENGTH(ram); 34 | __ram_end__ = __ram_start__ + __ram_size__; 35 | _plc_sstart = __ram_end__; /* Top of RAM */ 36 | 37 | SECTIONS 38 | { 39 | .text : { 40 | KEEP(*(.plc_app_abi_sec)) /* PLC APP ABI */ 41 | KEEP(*(.plc_md5_sec)) /* PLC APP ABI */ 42 | *(.text*) /* Program code */ 43 | KEEP(*(.rodata*)) /* Read only data */ 44 | 45 | . = ALIGN(4); 46 | _plc_pa_start = .; 47 | KEEP(*(.preinit_array)) /* Preinitarray */ 48 | _plc_pa_end = .; 49 | 50 | . = ALIGN(4); 51 | _plc_ia_start = .; 52 | KEEP (*(SORT(.init_array.*))) 53 | KEEP(*(.ctors)) /*Construcrs*/ 54 | _plc_ia_end = .; 55 | 56 | . = ALIGN(4); 57 | _plc_fia_start = .; 58 | KEEP(*(.fini_array)) /*Destructors */ 59 | KEEP (*(SORT(.fini_array.*))) 60 | _plc_fia_end = .; 61 | 62 | } >flash 63 | 64 | .data : ALIGN(16) { 65 | _plc_data_start = .; /* Used in PLC startup */ 66 | *(.data*) /* Initialized data */ 67 | _plc_data_end = .; /* Used in PLC startup */ 68 | } >ram AT > flash 69 | _plc_data_loadaddr = LOADADDR(.data); 70 | 71 | .bss (NOLOAD) : ALIGN(16) { 72 | *(.bss*) /* Uninitialized data */ 73 | *(COMMON) /* Common data */ 74 | _plc_bss_end = .; /* Used in PLC startup */ 75 | } >ram 76 | 77 | /* C++ exception unwinding stuff--needed by some toolchains */ 78 | 79 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >flash 80 | 81 | __exidx_start = .; 82 | .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >flash 83 | __exidx_end = .; 84 | 85 | 86 | ._plc_check : 87 | { 88 | KEEP(*(.plc_check_sec)) /* PLC APP ABI */ 89 | } > flash 90 | } 91 | 92 | /* Firmware entry point */ 93 | 94 | ENTRY(fake_start) 95 | 96 | -------------------------------------------------------------------------------- /src/bsp/template/example-rte.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the libopencm3 project. 3 | * 4 | * Copyright (C) 2009 Uwe Hermann 5 | * Copyright (C) 2011 Stephen Caudle 6 | * 7 | * This library is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU Lesser General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This library is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU Lesser General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU Lesser General Public License 18 | * along with this library. If not, see . 19 | */ 20 | 21 | /* Linker script for ST STM32F4DISCOVERY (STM32F205VC, 256K flash, 128K RAM). */ 22 | 23 | /* Define memory regions. */ 24 | MEMORY 25 | { 26 | rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K 27 | app_flash (rx) : ORIGIN = 0x08008000, LENGTH = 224K 28 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K 29 | appram (rwx) : ORIGIN = 0x20002000, LENGTH = 84K 30 | } 31 | 32 | PROVIDE(_stack = ORIGIN(appram) + LENGTH(appram)); 33 | PROVIDE(_app_start = ORIGIN(app_flash) ); 34 | PROVIDE(_app_end = _app_start + LENGTH(app_flash) ); 35 | 36 | /* Include the common ld script. */ 37 | /* 38 | * This file is part of the libopencm3 project. 39 | * 40 | * Copyright (C) 2009 Uwe Hermann 41 | * 42 | * This library is free software: you can redistribute it and/or modify 43 | * it under the terms of the GNU Lesser General Public License as published by 44 | * the Free Software Foundation, either version 3 of the License, or 45 | * (at your option) any later version. 46 | * 47 | * This library is distributed in the hope that it will be useful, 48 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 49 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 50 | * GNU Lesser General Public License for more details. 51 | * 52 | * You should have received a copy of the GNU Lesser General Public License 53 | * along with this library. If not, see . 54 | */ 55 | 56 | /* Generic linker script for STM32 targets using libopencm3. */ 57 | 58 | /* Memory regions must be defined in the ld script which includes this one. */ 59 | 60 | /* Enforce emmition of the vector table. */ 61 | EXTERN (vector_table) 62 | 63 | /* Define the entry point of the output file. */ 64 | ENTRY(reset_handler) 65 | 66 | /* Define sections. */ 67 | SECTIONS 68 | { 69 | .text : { 70 | *(.vectors) /* Vector table */ 71 | KEEP (*(.plc_rte_sec)) /* PLC RTE ABI */ 72 | *(.text*) /* Program code */ 73 | . = ALIGN(4); 74 | *(.rodata*) /* Read-only data */ 75 | . = ALIGN(4); 76 | } >rom 77 | 78 | /* C++ Static constructors/destructors, also used for __attribute__ 79 | * ((constructor)) and the likes */ 80 | .preinit_array : { 81 | . = ALIGN(4); 82 | __preinit_array_start = .; 83 | KEEP (*(.preinit_array)) 84 | __preinit_array_end = .; 85 | } >rom 86 | .init_array : { 87 | . = ALIGN(4); 88 | __init_array_start = .; 89 | KEEP (*(SORT(.init_array.*))) 90 | KEEP (*(.init_array)) 91 | __init_array_end = .; 92 | } >rom 93 | .fini_array : { 94 | . = ALIGN(4); 95 | __fini_array_start = .; 96 | KEEP (*(.fini_array)) 97 | KEEP (*(SORT(.fini_array.*))) 98 | __fini_array_end = .; 99 | } >rom 100 | 101 | /* 102 | * Another section used by C++ stuff, appears when using newlib with 103 | * 64bit (long long) printf support 104 | */ 105 | .ARM.extab : { 106 | *(.ARM.extab*) 107 | } >rom 108 | .ARM.exidx : { 109 | __exidx_start = .; 110 | *(.ARM.exidx*) 111 | __exidx_end = .; 112 | } >rom 113 | 114 | . = ALIGN(4); 115 | _etext = .; 116 | 117 | .data : { 118 | _data = .; 119 | *(.data*) /* Read-write initialized data */ 120 | . = ALIGN(4); 121 | _edata = .; 122 | } >ram AT >rom 123 | _data_loadaddr = LOADADDR(.data); 124 | 125 | .bss : { 126 | *(.bss*) /* Read-write zero initialized data */ 127 | *(COMMON) 128 | . = ALIGN(4); 129 | _ebss = .; 130 | } >ram 131 | 132 | . = ALIGN(4); 133 | end = .; 134 | } 135 | 136 | -------------------------------------------------------------------------------- /src/bsp/template/plc_backup.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * This file contains retain memory related stuff * 3 | *You can use src/bsp/common/stm32/f2/plc_backup.c as reference implementation.* 4 | ******************************************************************************/ 5 | 6 | /* Standard includes needed for memcpy and friends */ 7 | #include 8 | #include 9 | #include 10 | 11 | /*****************************************************************************/ 12 | /* Platform specific includes should be places here*/ 13 | 14 | /* 15 | STM32 example: 16 | #include 17 | #include 18 | #include 19 | #include 20 | */ 21 | 22 | /*****************************************************************************/ 23 | /* YAPLC includes */ 24 | #include 25 | #include 26 | 27 | /*****************************************************************************/ 28 | /* Add project specific includes here. */ 29 | 30 | /*****************************************************************************/ 31 | /* Retain memory implementation */ 32 | 33 | /*---------------------------------------------------------------------------*/ 34 | /* 35 | This function is used to setup backup/retain memory 36 | after the device reset. 37 | */ 38 | void plc_backup_init(void) 39 | { 40 | /* Insert your code here. */ 41 | } 42 | 43 | /*---------------------------------------------------------------------------*/ 44 | /* 45 | This function is used whrn we want to reset RTC date/time 46 | and backup/retain memory content. 47 | */ 48 | void plc_backup_reset(void) //used to reset 49 | { 50 | /* Insert your code here. */ 51 | } 52 | 53 | /*---------------------------------------------------------------------------*/ 54 | /* 55 | This function gets called by Beremiz generated __publish_debug before softPLC 56 | starts to save retain variables. 57 | */ 58 | void plc_backup_invalidate(void) 59 | { 60 | /* Insert your code here. */ 61 | } 62 | 63 | /*---------------------------------------------------------------------------*/ 64 | /* 65 | This function gets called by Beremiz generated __publish_debug after softPLC 66 | has saved retain variables. 67 | */ 68 | void plc_backup_validate(void) 69 | { 70 | /* Insert your code here. */ 71 | } 72 | 73 | /*---------------------------------------------------------------------------*/ 74 | /* 75 | This function gets called by Beremiz generated __init_debug when softPLC 76 | gets started. 77 | 78 | It must return 1 if there is a valid retain memory bank, 79 | else it must rturn 0 80 | */ 81 | int plc_backup_check(void) 82 | { 83 | /* Insert your code here. */ 84 | return 0; /*No valid retains present by default.*/ 85 | } 86 | 87 | /*---------------------------------------------------------------------------*/ 88 | /* 89 | This function gets called by Beremiz generated __init_debug when softPLC 90 | gets started. 91 | 92 | It must read backup/retain memory content and place it to "p" address. 93 | 94 | "Count" bytes are restored from "retain_memory_start + offset" 95 | address. 96 | */ 97 | void plc_backup_remind(unsigned int offset, unsigned int count, void *p) 98 | { 99 | /* Insert your code here. */ 100 | } 101 | 102 | /*---------------------------------------------------------------------------*/ 103 | /* 104 | This function gets called by Beremiz generated __publish_debug when softPLC 105 | saves retain variables. 106 | 107 | It must read softPLC data from "p" address and place it to backup/retain memory. 108 | 109 | "Count" bytes are stored at "retain_memory_start + offset" address. 110 | */ 111 | void plc_backup_retain(unsigned int offset, unsigned int count, void *p) 112 | { 113 | /* Insert your code here. */ 114 | } 115 | -------------------------------------------------------------------------------- /src/bsp/template/plc_clock.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * This file contains PLC clock related stuff * 3 | *You can use src/bsp/common/stm32/f2/plc_clock.c as reference implementation. * 4 | ******************************************************************************/ 5 | /* Standard includes are placed here*/ 6 | #include 7 | 8 | /* Platform specific includes should be places here*/ 9 | /* 10 | #include 11 | #include 12 | #include 13 | 14 | #include 15 | #include 16 | #include 17 | */ 18 | 19 | /*****************************************************************************/ 20 | /* YAPLC includes */ 21 | #include 22 | #include 23 | 24 | /*****************************************************************************/ 25 | /* Add project specific includes here. */ 26 | 27 | /*****************************************************************************/ 28 | /* 29 | This is clock setup function. 30 | It is responsible for setting up main MCU clock frequency. 31 | 32 | If you MCU has somethicng like "clock sequrity system", 33 | we recomend you to setup it here. 34 | */ 35 | void plc_clock_setup(void) 36 | { 37 | /*Insert your code here.*/ 38 | } 39 | 40 | /* 41 | You may need to add aditional functions here, 42 | e.g. interrupt handler for the case of main clock fail, so... 43 | */ 44 | /*Insert your code here, if needed.*/ 45 | -------------------------------------------------------------------------------- /src/bsp/template/plc_hw.c: -------------------------------------------------------------------------------- 1 | 2 | /****************************************************************************** 3 | * This file contains Boot pin and Jumpers related stuff. * 4 | ******************************************************************************/ 5 | 6 | /* Standard includes */ 7 | #include 8 | 9 | /*****************************************************************************/ 10 | /* Platform specific includes */ 11 | 12 | /* STM32 example 13 | #include 14 | #include 15 | #include 16 | 17 | #include 18 | #include 19 | #include 20 | */ 21 | 22 | /*****************************************************************************/ 23 | /* YAPLC includes */ 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | 31 | 32 | /*****************************************************************************/ 33 | /* Jumper related stuff. */ 34 | 35 | /*---------------------------------------------------------------------------*/ 36 | /* 37 | This function is used to setup reset and debug jumpers at device reset. 38 | */ 39 | void plc_jmpr_init(void) 40 | { 41 | /* Insert your code here. */ 42 | } 43 | 44 | /*---------------------------------------------------------------------------*/ 45 | /* Get debug jumper */ 46 | bool plc_dbg_jmpr_get(void) 47 | { 48 | /* Insert your code here. */ 49 | return false; /*Default*/ 50 | } 51 | 52 | /*---------------------------------------------------------------------------*/ 53 | /* Get reset jumper */ 54 | bool plc_rst_jmpr_get(void) 55 | { 56 | /* Insert your code here. */ 57 | return false; /*Default*/ 58 | } 59 | 60 | 61 | /*****************************************************************************/ 62 | /* Boot mode related stuff */ 63 | 64 | /*---------------------------------------------------------------------------*/ 65 | /* 66 | This function is used to setup the device bootloader at the device reset. 67 | */ 68 | void plc_boot_init(void) 69 | { 70 | /* Insert your code here. */ 71 | } 72 | 73 | /*---------------------------------------------------------------------------*/ 74 | /* 75 | This function is used to enter boot mode. 76 | 77 | Ir must transfer the controll to the bootloader. 78 | 79 | The bootloader must restart RTE after softPLC load. 80 | */ 81 | void plc_boot_mode_enter(void) 82 | { 83 | /* Insert your code here. */ 84 | } 85 | 86 | 87 | /****************************************************************************** 88 | * Deprecated stuff. Will be removed at YAPLC-3.0.0 release. * 89 | * Discrete and Analog IO is handled by IO manager, see plc_iom.c/h for details* 90 | ******************************************************************************/ 91 | /*---------------------------------------------------------------------------*/ 92 | bool plc_get_din(uint32_t i) 93 | { 94 | return false; 95 | } 96 | 97 | /*---------------------------------------------------------------------------*/ 98 | bool plc_get_dout(uint32_t i) 99 | { 100 | return false; 101 | } 102 | 103 | /*---------------------------------------------------------------------------*/ 104 | void plc_set_dout(uint32_t i, bool val) 105 | { 106 | (void)i; 107 | (void)val; 108 | } 109 | 110 | /*---------------------------------------------------------------------------*/ 111 | uint32_t plc_get_ain(uint32_t i) 112 | { 113 | (void)i; 114 | return 0; 115 | } 116 | 117 | /*---------------------------------------------------------------------------*/ 118 | void plc_set_aout(uint32_t i, uint32_t val) 119 | { 120 | (void)i; 121 | (void)val; 122 | } 123 | -------------------------------------------------------------------------------- /src/bsp/template/plc_iom_reg.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * This file contains IOM registry related stuff. * 3 | * You can use src/bsp/nuc-243/plc_iom_reg.c as reference implementation. * 4 | ******************************************************************************/ 5 | 6 | /*****************************************************************************/ 7 | /* YAPLC includes */ 8 | #include 9 | #include 10 | #include 11 | 12 | /*****************************************************************************/ 13 | /* Add project specific includes here. */ 14 | 15 | /*****************************************************************************/ 16 | /* 17 | Declare your PLC driver interfaces here. 18 | */ 19 | 20 | /* 21 | Every hardware driver which should be accessible by softPLC 22 | must be declared here. 23 | 24 | Use 25 | PLC_IOM_METH_DECLS(plc_something); 26 | for declarations. 27 | */ 28 | 29 | /*****************************************************************************/ 30 | /* 31 | This is PLC IO manager registry array. 32 | 33 | It is used by PLC IO manager, see plc_iom.c/h for details. 34 | 35 | Every hardware driver which should be accessible by softPLC 36 | must be registered here. 37 | */ 38 | const plc_io_metods_t plc_iom_registry[] = 39 | { 40 | /* 41 | Use PLC_IOM_RECORD(plc_something) here to register your PLC drivers. 42 | */ 43 | }; 44 | 45 | /*****************************************************************************/ 46 | /* Must be declared after plc_iom_registry */ 47 | PLC_IOM_REG_SZ_DECL; 48 | 49 | /*****************************************************************************/ 50 | /* 51 | This function is heavily used by PLC IO manager. 52 | 53 | It takes the variable location protocol ID and returns corresponding 54 | "plc_iom_registry" index. 55 | 56 | See plc_iom.c/h for details. 57 | */ 58 | uint8_t mid_from_pid(uint16_t proto) 59 | { 60 | switch (proto) 61 | { 62 | /*Insert your code here.*/ 63 | 64 | /*Don't delete this case!*/ 65 | default: 66 | return PLC_IOM_MID_ERROR; 67 | } 68 | return PLC_IOM_MID_ERROR;/*Don't delete this line!*/ 69 | } 70 | -------------------------------------------------------------------------------- /src/bsp/template/plc_rtc.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * This file contains RTC related stuff. * 3 | * You can use src/bsp/common/stm32/f2/plc_rtc.c as reference implementation. * 4 | ******************************************************************************/ 5 | 6 | /* Platform specific includes. */ 7 | /* 8 | STM32 example: 9 | #include 10 | #include 11 | #include 12 | */ 13 | 14 | /*****************************************************************************/ 15 | /* YAPLC includes. */ 16 | #include 17 | #include 18 | 19 | /*****************************************************************************/ 20 | /* Add project specific includes here. */ 21 | 22 | 23 | /*****************************************************************************/ 24 | /* RTC failure flag. */ 25 | volatile uint8_t plc_rtc_failure = 0; //Not failed by default 26 | 27 | /*****************************************************************************/ 28 | /* 29 | This function is called on device reset. 30 | It sets up all hardware needed for propper RTC work and checks RTC status. 31 | 32 | If RTC is OK then this function must return 1, else 0. 33 | */ 34 | uint32_t plc_rtc_clken_and_check(void) 35 | { 36 | uint32_t ret = 1; /*RTC is OK by default!*/ 37 | /* Insert your code here. */ 38 | return ret; 39 | } 40 | 41 | /*---------------------------------------------------------------------------*/ 42 | /* This function is called when we need to init/reset the RTC. */ 43 | void plc_rtc_init(tm* time) 44 | { 45 | (void)time; /*A pointer to date/time buffer variable.*/ 46 | /* Insert your code here. */ 47 | } 48 | 49 | /*---------------------------------------------------------------------------*/ 50 | /* This function is called when we need to change date/time. */ 51 | void plc_rtc_dt_set(tm* time) 52 | { 53 | (void)time; /*A pointer to date/time buffer variable.*/ 54 | /* Insert your code here. */ 55 | } 56 | 57 | /*---------------------------------------------------------------------------*/ 58 | /* 59 | This function is called when we need to get current date/time. 60 | 61 | Time is written to *time variable. 62 | */ 63 | void plc_rtc_dt_get(tm* time) 64 | { 65 | (void)time; /*A pointer to date/time buffer variable.*/ 66 | /* Insert your code here. */ 67 | } 68 | 69 | /*---------------------------------------------------------------------------*/ 70 | /* 71 | This function is called by periodic timer interrupt handler. 72 | 73 | It is needed to update RTC state. 74 | */ 75 | void _plc_rtc_poll(void) 76 | { 77 | /* Insert your code here. */ 78 | } 79 | 80 | /*---------------------------------------------------------------------------*/ 81 | /* 82 | This function is called by Beremiz-generated code. 83 | 84 | It works just like plc_rtc_dt_get but the output format is IEC_TIME. 85 | */ 86 | void plc_rtc_time_get(IEC_TIME *current_time) 87 | { 88 | /* Insert your code here. */ 89 | } 90 | 91 | 92 | 93 | -------------------------------------------------------------------------------- /src/bsp/template/plc_serial.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * This file contains debug serial port related stuff * 3 | *You can use src/bsp/common/stm32/f2/plc_serial.c as reference implementation.* 4 | * * 5 | * Debug serial port is used to connect PLC with Host which is running IDE. * 6 | * We use full duplex serial link for the debug. Two FIFOs are used to transfer* 7 | * the data in each direction. * 8 | * * 9 | * This file should be used as Low level part of PLC side debuger. I must * 10 | * contain debug UART driver with the following API. * 11 | ******************************************************************************/ 12 | 13 | /*****************************************************************************/ 14 | /* Platform specific includes */ 15 | 16 | /* STM32 example 17 | #include 18 | #include 19 | #include 20 | 21 | #include 22 | #include 23 | */ 24 | 25 | /*****************************************************************************/ 26 | /* YAPLC includes */ 27 | #include 28 | #include /*See this file for dbg_fifo API.*/ 29 | 30 | /* FIFOS or TX and RX */ 31 | static dbg_fifo_t usart_rx_buf, usart_tx_buf; 32 | 33 | /*****************************************************************************/ 34 | /* This function is used to setup the debug serial port at the device reset. */ 35 | void dbg_serial_init(void) 36 | { 37 | /* First init FIFOs. */ 38 | dbg_fifo_flush(&usart_rx_buf); 39 | dbg_fifo_flush(&usart_tx_buf); 40 | 41 | /* Then init serial port. */ 42 | 43 | /* Insert your code here. */ 44 | } 45 | 46 | /*---------------------------------------------------------------------------*/ 47 | /* This function is used to write data to usart_tx_buf. */ 48 | int dbg_serial_write(unsigned char *d, unsigned short n) 49 | { 50 | int res = 0; 51 | PLC_DISABLE_INTERRUPTS(); 52 | /* Insert your code here. */ 53 | /* dbg_fifo_write_byte, and dbg_fifo_write can be used here.*/ 54 | PLC_ENABLE_INTERRUPTS(); 55 | return res; /*Return number of bytes written.*/ 56 | } 57 | 58 | /* This function is used to read data from usart_rx_buf. */ 59 | int dbg_serial_read(unsigned char *d, unsigned short n) 60 | { 61 | int res = 0; 62 | PLC_DISABLE_INTERRUPTS(); 63 | /* Insert your code here. */ 64 | /* dbg_fifo_read_byte, and dbg_fifo_read can be used here.*/ 65 | PLC_ENABLE_INTERRUPTS(); 66 | return res; /*Return number of bytes red.*/ 67 | } 68 | -------------------------------------------------------------------------------- /src/bsp/template/plc_tick.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * This file contains PLC tick related stuff * 3 | * You can use src/bsp/common/plc_tick.c as reference implementation. * 4 | ******************************************************************************/ 5 | 6 | /* Platform specific includes should be places here*/ 7 | /* 8 | STM32 example 9 | #include 10 | #include 11 | #include 12 | */ 13 | 14 | 15 | /*****************************************************************************/ 16 | /* YAPLC includes */ 17 | #include 18 | #include 19 | 20 | /*****************************************************************************/ 21 | /* Add project specific includes here. */ 22 | 23 | 24 | /*****************************************************************************/ 25 | /* Variables */ 26 | uint64_t plc_tick_time = PLC_TICK_MIN_PER; /*softPLC tick time in nanoseconds*/ 27 | 28 | /* 29 | This flag is set by periodic timer interrupt when softPLC must be called. 30 | This should happen every "plc_tick_time" nanoseconds. 31 | */ 32 | volatile bool plc_tick_flag = false; 33 | 34 | /*****************************************************************************/ 35 | /* 36 | This function sets up soft/hardware needed to generte ticks. 37 | It is called on the device reset. 38 | */ 39 | void plc_tick_init(void) 40 | { 41 | /* Insert your code here. */ 42 | } 43 | 44 | /*---------------------------------------------------------------------------*/ 45 | /* 46 | This function is called in "main" loop. 47 | 48 | Actually it is empty now and it's likely to bedeprecated in next 49 | YAPLC releases. 50 | */ 51 | void plc_tick_poll(void) 52 | { 53 | } 54 | 55 | /*---------------------------------------------------------------------------*/ 56 | /* 57 | This function must be called every "plc_tick_time" nanoseconds by 58 | priodic timer interrupt handler. 59 | 60 | Or it can be priodic timer interrupt handler itself. 61 | 62 | Feel free to rename this function as you need! 63 | */ 64 | void please_rename_me_tick_handler(void) 65 | { 66 | //Soft watchdog 67 | if (plc_tick_flag) 68 | { 69 | /* 70 | If "plc_tick_flag" wasn't cleared by "main" function, 71 | then softPLC didn't met deadline, this is error 72 | which should be handled. 73 | */ 74 | /* Insert your code here. */ 75 | } 76 | else 77 | { 78 | /* 79 | softPLC should be called 80 | */ 81 | plc_tick_flag = true; 82 | /* Insert your code here if needed. */ 83 | } 84 | /* Insert your code here if needed. */ 85 | } 86 | 87 | /*---------------------------------------------------------------------------*/ 88 | /* 89 | This function is called by softPLC on start. 90 | And may be called from "align_tick" function, 91 | see next comments. 92 | */ 93 | void plc_tick_setup(uint64_t tick_next, uint64_t tick_period) 94 | { 95 | /* 96 | Do next tick in "tick_next" nanoseconds. 97 | 98 | This parameter may be leaved unused, if you won't use "align_tick" 99 | function, see beremiz/targets/plc_main_tail.c for details. 100 | 101 | We don't use it in RTE code. 102 | */ 103 | (void)tick_next;//disable warning 104 | /* 105 | Do tick every "tick_period" nanoseconds, or "PLC_TICK_MIN_PER" nanoseconds 106 | if "tick_period" is too small. 107 | 108 | This is mandatory parameter. 109 | */ 110 | (void)tick_period;//disable warning 111 | 112 | /* Insert your code here. */ 113 | } 114 | -------------------------------------------------------------------------------- /src/bsp/template/plc_wait_tmr.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * This file contains wait timer related stuff. * 3 | *You can use src/bsp/common/stm32/plc_wait_tmr.c as reference implementation. * 4 | ******************************************************************************/ 5 | 6 | /*****************************************************************************/ 7 | /* Platform specific includes should be places here*/ 8 | 9 | /* 10 | STM32 example: 11 | #include 12 | #include 13 | 14 | #include 15 | #include 16 | #include 17 | */ 18 | 19 | 20 | /*****************************************************************************/ 21 | /* YAPLC includes */ 22 | #include 23 | #include 24 | 25 | 26 | /*****************************************************************************/ 27 | /* Add project specific includes here. */ 28 | 29 | /*****************************************************************************/ 30 | /* 31 | Delay timer base variable. 32 | 33 | This variable is used to count milliseconds for delays in PLC hardware drivers. 34 | 35 | It must be incremented by periodic timer interrupt handler every millisecond. 36 | */ 37 | volatile uint32_t plc_sys_timer = 0; 38 | 39 | /*****************************************************************************/ 40 | /*This function should be used to setup periodic timer at device reset.*/ 41 | void plc_wait_tmr_init(void) 42 | { 43 | /*Insert your code here.*/ 44 | } 45 | 46 | /*---------------------------------------------------------------------------*/ 47 | /* 48 | This function must inrement "plc_sys_timer" every millisecond. 49 | 50 | It should be called by priodic timer interrupt handler. 51 | 52 | Or it can be priodic timer interrupt handler itself. 53 | 54 | Feel free to rename this function as you need! 55 | */ 56 | void please_rename_me_wait_timer_tick_handler(void) 57 | { 58 | /* 59 | You should use this function to increment "plc_sys_timer" and 60 | to do other periodic actions. 61 | */ 62 | 63 | /*Insert your code here.*/ 64 | } 65 | -------------------------------------------------------------------------------- /src/dbnc_flt.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include "dbnc_flt.h" 9 | 10 | void dbnc_flt_init(dbnc_flt_t * self) 11 | { 12 | self->thr_on = DBNC_FLT_THR_ON; 13 | self->tim_on = 0; 14 | self->thr_off = DBNC_FLT_THR_OFF; 15 | self->tim_off = 0; 16 | self->flg = false; 17 | } 18 | 19 | void dbnc_flt_poll(dbnc_flt_t * self, uint32_t tick, bool in) 20 | { 21 | if (self->flg) 22 | { 23 | if (in) 24 | { 25 | self->tim_off = tick; 26 | } 27 | else 28 | { 29 | if ((tick - self->tim_off) > self->thr_off) 30 | { 31 | self->flg = false; 32 | self->tim_on = tick; 33 | } 34 | } 35 | } 36 | else 37 | { 38 | if (in) 39 | { 40 | if ((tick - self->tim_on) > self->thr_on) 41 | { 42 | self->flg = true; 43 | self->tim_off = tick; 44 | } 45 | } 46 | else 47 | { 48 | self->tim_on = tick; 49 | } 50 | } 51 | } 52 | 53 | bool dbnc_flt_get(dbnc_flt_t * self) 54 | { 55 | return self->flg; 56 | } 57 | -------------------------------------------------------------------------------- /src/dbnc_flt.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #ifndef _DBNC_FLT_H_ 9 | #define _DBNC_FLT_H_ 10 | 11 | #include "stdbool.h" 12 | #include "stdint.h" 13 | 14 | typedef struct _dbnc_flt_t dbnc_flt_t; 15 | struct _dbnc_flt_t 16 | { 17 | uint32_t thr_on; 18 | uint32_t tim_on; 19 | uint32_t thr_off; 20 | uint32_t tim_off; 21 | bool flg; 22 | }; 23 | 24 | /* Default threasholds */ 25 | #define DBNC_FLT_THR_ON 2 26 | #define DBNC_FLT_THR_OFF 10 27 | 28 | void dbnc_flt_init(dbnc_flt_t * self); 29 | void dbnc_flt_poll(dbnc_flt_t * self, uint32_t tick, bool in); 30 | bool dbnc_flt_get(dbnc_flt_t * self); 31 | 32 | #endif // _DBNC_FLT_H_ 33 | -------------------------------------------------------------------------------- /src/frac_div.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include "frac_div.h" 9 | 10 | void frac_div_set(frac_div_t * div, uint64_t period) 11 | { 12 | div->idefault = period / div->base; 13 | div->fdelta = period % div->base; 14 | } 15 | 16 | void frac_div_init(frac_div_t * div, uint64_t period, uint64_t base) 17 | { 18 | div->base = base; 19 | 20 | frac_div_set(div, period); 21 | 22 | div->icurrent = div->idefault; 23 | div->iaccum = 0; 24 | div->faccum = div->fdelta; 25 | } 26 | 27 | uint64_t frac_div_icalc(frac_div_t * div) 28 | { 29 | div->faccum += div->fdelta; 30 | if (div->base > div->faccum) 31 | { 32 | return div->idefault; 33 | } 34 | else 35 | { 36 | div->faccum %= div->base; 37 | return div->idefault + 1; 38 | } 39 | } 40 | 41 | bool frac_div_run(frac_div_t * div) 42 | { 43 | if (div->iaccum < div->icurrent) 44 | { 45 | div->iaccum++; 46 | return false; 47 | } 48 | else 49 | { 50 | div->iaccum = 1; 51 | div->icurrent = frac_div_icalc(div); 52 | return true; 53 | } 54 | } 55 | -------------------------------------------------------------------------------- /src/frac_div.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #ifndef _FRAC_DIV_H_ 9 | #define _FRAC_DIV_H_ 10 | 11 | #include 12 | #include 13 | 14 | typedef struct 15 | { 16 | uint64_t idefault; //!< Default intger part of period 17 | uint64_t icurrent; //!< Current intger part of period 18 | uint64_t iaccum; //!< Integer part accumulator 19 | uint64_t fdelta; //!< Fractionsl part delta 20 | uint64_t faccum; //!< Fractional part accumulator 21 | uint64_t base; //!< Base 22 | } 23 | frac_div_t;//!< Fractional frequency divider 24 | 25 | void frac_div_init(frac_div_t * div, uint64_t period, uint64_t base); 26 | void frac_div_set(frac_div_t * div, uint64_t period); 27 | uint64_t frac_div_icalc(frac_div_t * div); //may be used to correct systick reload value during the work 28 | bool frac_div_run(frac_div_t * div); 29 | 30 | #endif // _FRAC_DIV_H_ 31 | -------------------------------------------------------------------------------- /src/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | 11 | //#include 12 | #include 13 | 14 | #include 15 | 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | #include 25 | #include 26 | #include 27 | 28 | bool plc_dbg_mode = false; 29 | unsigned char plc_state = PLC_STATE_STOPED; 30 | plc_app_abi_t * plc_curr_app = (plc_app_abi_t *)&plc_app_default; 31 | 32 | extern bool plc_app_is_valid(void); 33 | extern void plc_app_cstratup(void); 34 | 35 | const tm default_date = 36 | { 37 | .tm_sec = 0, 38 | .tm_min = 0, 39 | .tm_hour = 0, 40 | .tm_day = 1, 41 | .tm_mon = 3, 42 | .tm_year = 2016 43 | }; 44 | 45 | const char plc_start_msg[] = "This is YAPLC! Everything is OK!"; 46 | const char plc_app_err_msg[] = "PLC app is not valid!!!"; 47 | const char plc_hw_err_msg[] = "PLC hardware is damaged!!!"; 48 | 49 | #ifndef PLC_RESET_HOOK 50 | #define PLC_RESET_HOOK() do{}while(0) 51 | #endif 52 | 53 | int main(void) 54 | { 55 | PLC_DISABLE_INTERRUPTS(); 56 | 57 | plc_app_default_init(); 58 | plc_clock_setup(); 59 | plc_wait_tmr_init(); 60 | plc_jmpr_init(); 61 | plc_boot_init(); 62 | plc_tick_init(); 63 | plc_iom_init(); 64 | 65 | if (plc_iom_test_hw()) 66 | { 67 | // H/W is OK, continue init... 68 | plc_backup_init(); 69 | if (plc_rst_jmpr_get()) 70 | { 71 | //do reset 72 | PLC_RESET_HOOK(); 73 | plc_rtc_init((tm *)&default_date); 74 | plc_backup_reset(); 75 | } 76 | 77 | if (0 == plc_rtc_clken_and_check()) 78 | { 79 | //rtc is not OK, must reset it! 80 | plc_rtc_init((tm *)&default_date); 81 | } 82 | 83 | if (plc_app_is_valid()) 84 | { 85 | //App code is OK, do cstartup 86 | plc_app_cstratup(); 87 | //Check plc io locations 88 | if (plc_iom_check_and_sort()) 89 | { 90 | //Everything is OK may use app code 91 | plc_curr_app = (plc_app_abi_t *)PLC_APP; 92 | plc_curr_app->log_msg_post(LOG_DEBUG, (char *)plc_start_msg, sizeof(plc_start_msg)); 93 | } 94 | else 95 | { 96 | plc_diag_status |= PLC_DIAG_ERR_LOCATION; //Message is allready posted! 97 | } 98 | } 99 | else 100 | { 101 | plc_diag_status |= PLC_DIAG_ERR_INVALID; 102 | PLC_LOG_ERROR(plc_app_err_msg); 103 | } 104 | } 105 | else 106 | { 107 | plc_diag_status |= PLC_DIAG_ERR_HW_OTHER; 108 | PLC_LOG_ERROR(plc_hw_err_msg); 109 | } 110 | 111 | dbg_init(); 112 | PLC_ENABLE_INTERRUPTS(); 113 | 114 | if (plc_dbg_jmpr_get()) 115 | { 116 | plc_dbg_mode = true; 117 | //Wait for debug connection, app won't be started! 118 | plc_state = PLC_STATE_STOPED; 119 | } 120 | else 121 | { 122 | //May start the app immediately 123 | plc_app_start(); 124 | } 125 | 126 | while (1) 127 | { 128 | //Hadnle debug connection 129 | dbg_handler(); 130 | //Heart bit 131 | plc_tick_poll(); 132 | plc_iom_poll(); 133 | //App run 134 | if (plc_tick_flag) 135 | { 136 | plc_tick_flag = false; 137 | if (PLC_STATE_STARTED == plc_state) 138 | { 139 | plc_iom_get(); 140 | plc_curr_app->run(); 141 | plc_iom_set(); 142 | } 143 | } 144 | } 145 | } 146 | -------------------------------------------------------------------------------- /src/noise_flt.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | 11 | #include 12 | 13 | void noise_flt_init(noise_flt_t * self, uint8_t depth, uint16_t val) 14 | { 15 | uint8_t i; 16 | for (i=0; idata[i] = val; 19 | } 20 | self->depth = depth; 21 | self->idx = 0; 22 | } 23 | 24 | 25 | void noise_flt_write(noise_flt_t * self, uint16_t val) 26 | { 27 | self->data[self->idx++] = val; 28 | self->idx %= self->depth; 29 | } 30 | 31 | // C.A.R. Hoare's Quick Median 32 | static inline uint8_t quick_median(uint16_t *data, uint8_t n) 33 | { 34 | uint8_t l = 0; 35 | uint8_t r = n-1; 36 | uint8_t k = n/2; 37 | 38 | while (l < r) 39 | { 40 | uint16_t x = data[k]; 41 | uint8_t i = l; 42 | uint8_t j = r; 43 | //Split dada 44 | do 45 | { 46 | while (data[i] < x) 47 | { 48 | i++; 49 | } 50 | while (x < data[j]) 51 | { 52 | j--; 53 | } 54 | if (i <= j) 55 | { 56 | uint16_t ii = data[i]; 57 | data[i] = data[j]; 58 | data[j] = ii; 59 | i++; 60 | j--; 61 | } 62 | } 63 | while (i <= j); 64 | 65 | if (j < k) 66 | { 67 | l = i; 68 | } 69 | if (k < i) 70 | { 71 | r = j; 72 | } 73 | } 74 | return k; 75 | } 76 | 77 | uint16_t noise_flt_median(noise_flt_t * self, uint16_t * buf) 78 | { 79 | uint8_t i; 80 | uint8_t n = self->depth; 81 | //Copy data to buf 82 | for(i=0; idata[i]; 85 | } 86 | 87 | i = quick_median(buf, n); 88 | 89 | return buf[i]; 90 | } 91 | 92 | uint16_t noise_flt_ave(noise_flt_t * self) 93 | { 94 | uint8_t i; 95 | uint8_t n; 96 | uint32_t s = 0; 97 | 98 | n = self->depth; 99 | for(i=0; idata[i]; 102 | } 103 | return (uint16_t)(s/n); 104 | } 105 | -------------------------------------------------------------------------------- /src/noise_flt.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | #ifndef _NOISE_FLT_H_ 8 | #define _NOISE_FLT_H_ 9 | 10 | #ifndef NOISE_FLT_BUFSZ 11 | #define NOISE_FLT_BUFSZ 8 12 | #endif//NOISE_FLT_BUFSZ 13 | 14 | typedef struct 15 | { 16 | volatile uint16_t data[NOISE_FLT_BUFSZ]; 17 | uint8_t depth; 18 | volatile uint8_t idx; 19 | } 20 | noise_flt_t; 21 | 22 | void noise_flt_init(noise_flt_t * self, uint8_t depth, uint16_t val); 23 | 24 | void noise_flt_write(noise_flt_t * self, uint16_t val); 25 | 26 | uint16_t noise_flt_median(noise_flt_t * self, uint16_t * buf); 27 | uint16_t noise_flt_ave(noise_flt_t * self); 28 | 29 | #endif /* _NOISE_FLT_H_ */ 30 | -------------------------------------------------------------------------------- /src/plc_abi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nucleron/RTE/65341e5029a33f35f32de1fa41ba0276b89680b9/src/plc_abi.h -------------------------------------------------------------------------------- /src/plc_app_default.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #ifndef _PLC_APP_DEFAULT_H_ 9 | #define _PLC_APP_DEFAULT_H_ 10 | 11 | #include 12 | 13 | extern const plc_app_abi_t plc_app_default; 14 | void plc_app_default_init(void); 15 | 16 | #endif // _PLC_APP_DEFAULT_H_ 17 | -------------------------------------------------------------------------------- /src/plc_backup.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #ifndef _DBG_BACKUP_H_ 9 | #define _DBG_BACKUP_H_ 10 | 11 | /*YAPLC related functions*/ 12 | void plc_backup_init(void); 13 | void plc_backup_reset(void); 14 | 15 | /*Bereiz related functions: these functions are used by Beremiz generated plc_debug.c file*/ 16 | void plc_backup_invalidate(void); 17 | void plc_backup_validate(void); 18 | int plc_backup_check(void); 19 | void plc_backup_remind(unsigned int offset, unsigned int count, void *p); 20 | void plc_backup_retain(unsigned int offset, unsigned int count, void *p); 21 | 22 | #endif /* _DBG_BACKUP_H_ */ 23 | -------------------------------------------------------------------------------- /src/plc_clock.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #ifndef _PLC_CLOCK_H_ 9 | #define _PLC_CLOCK_H_ 10 | 11 | extern volatile uint8_t plc_clock_hse_failure; 12 | void plc_clock_setup(void); 13 | 14 | #endif /* _PLC_CLOCK_H_ */ 15 | -------------------------------------------------------------------------------- /src/plc_diag.h: -------------------------------------------------------------------------------- 1 | #ifndef _PLC_DIAG_H_ 2 | #define _PLC_DIAG_H_ 3 | 4 | #define PLC_DIAG_ERR_HSE 0x001 5 | #define PLC_DIAG_ERR_LSE 0x002 6 | #define PLC_DIAG_ERR_APP_INFO 0x004 //User programm warning 7 | #define PLC_DIAG_ERR_APP_WARN 0x008 //User programm warning 8 | 9 | #define PLC_DIAG_ERR_OTHER_CRIT 0xFFFFFFF0 //Critical errors 10 | 11 | #define PLC_DIAG_ERR_APP_CRIT 0x010 //User programm abort 12 | #define PLC_DIAG_ERR_DEADLINE 0x020 //Deadline violation detected 13 | #define PLC_DIAG_ERR_INVALID 0x040 //App code check error 14 | #define PLC_DIAG_ERR_LOCATION 0x080 //location check efrror 15 | #define PLC_DIAG_ERR_HW_OTHER 0x100 //Faailed HW 16 | 17 | extern volatile uint32_t plc_diag_status; 18 | 19 | #endif // _PLC_DIAG_H_ 20 | -------------------------------------------------------------------------------- /src/plc_glue_dbg.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include "plc_glue_dbg.h" 9 | 10 | #ifndef PLC_MD5 11 | #define PLC_MD5 "375254725509a3f2b9f0867e11074526Unknown#Unnamed#Unnamed#" 12 | #endif 13 | 14 | const char plc_md5[] = PLC_MD5; 15 | 16 | extern int startPLC(int argc,char **argv); 17 | extern int stopPLC(); 18 | extern void runPLC(void); 19 | 20 | extern void resumeDebug(void); 21 | extern void suspendDebug(int disable); 22 | 23 | extern void FreeDebugData(void); 24 | extern int GetDebugData(unsigned long *tick, unsigned long *size, void **buffer); 25 | 26 | extern void ResetDebugVariables(void); 27 | extern void RegisterDebugVariable(int idx, void* force); 28 | 29 | extern void ResetLogCount(void); 30 | extern uint32_t GetLogCount(uint8_t level); 31 | extern uint32_t GetLogMessage(uint8_t level, uint32_t msgidx, char* buf, uint32_t max_size, uint32_t* tick, uint32_t* tv_sec, uint32_t* tv_nsec); 32 | 33 | const plc_app_abi_t plc_glue_app = 34 | { 35 | .id = plc_md5, 36 | 37 | .start = startPLC, 38 | .stop = stopPLC, 39 | .run = runPLC, 40 | 41 | .dbg_resume = resumeDebug, 42 | .dbg_suspend = suspendDebug, 43 | 44 | .dbg_data_get = GetDebugData, 45 | .dbg_data_free = FreeDebugData, 46 | 47 | .dbg_vars_reset = ResetDebugVariables, 48 | .dbg_var_register = RegisterDebugVariable, 49 | 50 | .log_cnt_get = GetLogCount, 51 | .log_msg_get = GetLogMessage, 52 | .log_cnt_reset = ResetLogCount, 53 | .log_msg_post = LogMessage 54 | }; 55 | 56 | #include 57 | #include 58 | #include 59 | 60 | const plc_rte_abi_t plc_glue_rte = 61 | { 62 | .get_time = plc_rtc_time_get, 63 | .set_timer = plc_tick_setup, 64 | 65 | .check_retain_buf = plc_backup_check, 66 | .invalidate_retain_buf = plc_backup_invalidate, 67 | .validate_retain_buf = plc_backup_validate, 68 | 69 | .retain = plc_backup_retain, 70 | .remind = plc_backup_remind 71 | //Other unused rigth now 72 | }; 73 | 74 | 75 | bool plc_app_is_valid(void) 76 | { 77 | return true; 78 | } 79 | void plc_app_cstratup(void) 80 | { 81 | return; 82 | } 83 | -------------------------------------------------------------------------------- /src/plc_glue_dbg.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #ifndef _PLC_DBG_GLUE_H_ 9 | #define _PLC_DBG_GLUE_H_ 10 | 11 | #include 12 | 13 | #define PLC_APP (&plc_glue_app) 14 | 15 | #define PLC_ADDR(a) (&a) 16 | 17 | extern const plc_app_abi_t plc_glue_app; 18 | extern const plc_rte_abi_t plc_glue_rte; 19 | 20 | 21 | 22 | #endif // _PLC_DBG_GLUE_H_ 23 | -------------------------------------------------------------------------------- /src/plc_hw.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #ifndef _PLC_HW_H_ 9 | #define _PLC_HW_H_ 10 | 11 | #include 12 | #include 13 | 14 | void plc_jmpr_init(void); 15 | bool plc_dbg_jmpr_get(void); 16 | bool plc_rst_jmpr_get(void); 17 | 18 | void plc_tick_init(void); 19 | void plc_tick_poll(void); 20 | 21 | void plc_boot_init(void); 22 | void plc_boot_mode_enter(void); 23 | 24 | bool plc_get_din(uint32_t i); 25 | 26 | bool plc_get_dout(uint32_t i); 27 | void plc_set_dout(uint32_t i, bool val); 28 | 29 | uint32_t plc_get_ain(uint32_t i); 30 | void plc_set_aout(uint32_t i, uint32_t val); 31 | #endif /* _PLC_HW_H_ */ 32 | -------------------------------------------------------------------------------- /src/plc_ioproto_template.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | 10 | #define LOCAL_PROTO p1 11 | void PLC_IOM_LOCAL_INIT(void) 12 | { 13 | } 14 | bool PLC_IOM_LOCAL_TEST_HW(void) 15 | { 16 | return true; 17 | } 18 | bool PLC_IOM_LOCAL_CHECK(uint16_t lid) 19 | { 20 | return false; 21 | } 22 | void PLC_IOM_LOCAL_BEGIN(uint16_t lid) 23 | { 24 | } 25 | void PLC_IOM_LOCAL_END(uint16_t lid) 26 | { 27 | } 28 | 29 | void PLC_IOM_LOCAL_START(void) 30 | { 31 | } 32 | 33 | uint32_t PLC_IOM_LOCAL_SCHED(uint16_t lid, uint32_t tick) 34 | { 35 | return 0; 36 | } 37 | 38 | void PLC_IOM_LOCAL_POLL(uint32_t tick) 39 | { 40 | } 41 | 42 | void PLC_IOM_LOCAL_STOP(void) 43 | { 44 | } 45 | 46 | uint32_t PLC_IOM_LOCAL_WEIGTH(uint16_t lid) 47 | { 48 | return PLC_APP->l_tab[lid]->a_data[0]; 49 | } 50 | 51 | uint32_t PLC_IOM_LOCAL_GET(uint16_t lid) 52 | { 53 | return 0; 54 | } 55 | 56 | uint32_t PLC_IOM_LOCAL_SET(uint16_t lid) 57 | { 58 | return 0; 59 | } 60 | #undef LOCAL_PROTO 61 | -------------------------------------------------------------------------------- /src/plc_libc.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | #include 12 | 13 | #include "xprintf.h" 14 | /* Portions of standart library to run Linker with -nostdlib -lgcc */ 15 | void *memset(void *dest, int c, size_t count) 16 | { 17 | char * d; 18 | 19 | c &= 0xff; 20 | d = (char *)dest; 21 | 22 | while (count--) 23 | { 24 | *d++ = (char)c; 25 | } 26 | return (void *)d; 27 | } 28 | 29 | void *memcpy(void *dest, const void *src, size_t count) 30 | { 31 | char *d, *s; 32 | 33 | d = (char *)dest; 34 | s = (char *)src; 35 | 36 | while (count--) 37 | { 38 | *d++ = *s++; 39 | } 40 | return (void *)d; 41 | } 42 | 43 | static char * out_ptr; 44 | static uint8_t out_cnt = 0; 45 | static void out_stub(unsigned char c) 46 | { 47 | out_ptr[out_cnt++] = c; 48 | } 49 | 50 | 51 | int sprintf(char *buf, const char *fmt, ...) 52 | { 53 | va_list args; 54 | 55 | out_ptr = buf; 56 | out_cnt = 0; 57 | xdev_out(out_stub); 58 | 59 | va_start(args, fmt); 60 | xvprintf(fmt, args); 61 | va_end(args); 62 | 63 | xdev_out(0); 64 | buf[out_cnt] = 0;//Terminate string. 65 | 66 | return out_cnt; 67 | } 68 | 69 | -------------------------------------------------------------------------------- /src/plc_rtc.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #ifndef _RTC_H_ 9 | #define _RTC_H_ 10 | 11 | typedef struct { 12 | int tm_sec; /* Seconds. [0-60] (1 leap second) */ 13 | int tm_min; /* Minutes. [0-59] */ 14 | int tm_hour; /* Hours. [0-23] */ 15 | int tm_day; /* Day. [1-31] */ 16 | int tm_mon; /* Month. [0-11] */ 17 | int tm_year; /* Year */ 18 | } tm; 19 | 20 | #include 21 | 22 | extern volatile uint8_t plc_rtc_failure; 23 | 24 | //For internal usage 25 | void _plc_rtc_poll(void); 26 | 27 | uint32_t plc_rtc_clken_and_check(void); 28 | 29 | void plc_rtc_init(tm* time); 30 | void plc_rtc_dt_set(tm* time); 31 | void plc_rtc_dt_get(tm* time); 32 | void plc_rtc_time_get(IEC_TIME *curent_time); 33 | 34 | #endif //_RTC_H_ 35 | -------------------------------------------------------------------------------- /src/plc_tick.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #ifndef _PLC_TICK_H_ 9 | #define _PLC_TICK_H_ 10 | 11 | #include 12 | 13 | extern volatile bool plc_tick_flag; 14 | extern uint64_t plc_tick_time; 15 | 16 | void plc_tick_setup(unsigned long long tick_next, unsigned long long tick_period); 17 | 18 | #endif /* _PLC_TICK_H_ */ 19 | -------------------------------------------------------------------------------- /src/plc_wait_tmr.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright Nucleron R&D LLC 2016 3 | * 4 | * This file is licensed under the terms of YAPL, 5 | * see License.txt for details. 6 | */ 7 | 8 | #ifndef _PLC_WAIT_TMR_H_ 9 | #define _PLC_WAIT_TMR_H_ 10 | 11 | extern volatile uint32_t plc_sys_timer; 12 | 13 | void plc_wait_tmr_init(void); 14 | 15 | #define PLC_TIMER(t) (plc_sys_timer - t) 16 | #define PLC_CLEAR_TIMER(t) (t = plc_sys_timer) 17 | 18 | #endif /* _PLC_WAIT_TMR_H_ */ 19 | -------------------------------------------------------------------------------- /src/xprintf.h: -------------------------------------------------------------------------------- 1 | /*------------------------------------------------------------------------*/ 2 | /* Universal string handler for user console interface (C)ChaN, 2011 */ 3 | /*------------------------------------------------------------------------*/ 4 | 5 | #ifndef _STRFUNC 6 | #define _STRFUNC 7 | 8 | #define _USE_XFUNC_OUT 1 /* 1: Use output functions */ 9 | #define _CR_CRLF 0 /* 1: Convert \n ==> \r\n in the output char */ 10 | 11 | #define _USE_XFUNC_IN 0 /* 1: Use input function */ 12 | #define _LINE_ECHO 0 /* 1: Echo back input chars in xgets function */ 13 | 14 | 15 | #if _USE_XFUNC_OUT 16 | #include 17 | #define xdev_out(func) xfunc_out = (void(*)(unsigned char))(func) 18 | extern void (*xfunc_out)(unsigned char); 19 | void xputc (char c); 20 | void xputs (const char* str); 21 | void xfputs (void (*func)(unsigned char), const char* str); 22 | void xvprintf (const char* fmt, va_list arp); 23 | void xprintf (const char* fmt, ...); 24 | void xsprintf (char* buff, const char* fmt, ...); 25 | void xfprintf (void (*func)(unsigned char), const char* fmt, ...); 26 | void put_dump (const void* buff, unsigned long addr, int len, int width); 27 | #define DW_CHAR sizeof(char) 28 | #define DW_SHORT sizeof(short) 29 | #define DW_LONG sizeof(long) 30 | #endif 31 | 32 | #if _USE_XFUNC_IN 33 | #define xdev_in(func) xfunc_in = (unsigned char(*)(void))(func) 34 | extern unsigned char (*xfunc_in)(void); 35 | int xgets (char* buff, int len); 36 | int xfgets (unsigned char (*func)(void), char* buff, int len); 37 | int xatoi (char** str, long* res); 38 | #endif 39 | 40 | #endif 41 | --------------------------------------------------------------------------------