├── LICENSE ├── README.md ├── sblaster.v ├── testbench.jpg ├── ym_lib.v └── ymf262.v /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 2, June 1991 3 | 4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc., 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | Preamble 10 | 11 | The licenses for most software are designed to take away your 12 | freedom to share and change it. By contrast, the GNU General Public 13 | License is intended to guarantee your freedom to share and change free 14 | software--to make sure the software is free for all its users. This 15 | General Public License applies to most of the Free Software 16 | Foundation's software and to any other program whose authors commit to 17 | using it. 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If this is what you want to do, use the GNU Lesser General 339 | Public License instead of this License. 340 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # LPC-Sound-Blaster 2 | FPGA Sound Blaster over LPC bus experiments 3 | 4 | ## Notes 5 | * Basic playback functions of sb pro 2 are implemented, but not mixer chip 6 | * OPL3 is emulated using verilog port of [YMF262-LLE](https://github.com/nukeykt/YMF262-LLE) 7 | * LPC bus is easily accessible on some boards through TPM header, but LDRQ pin usually is missing. LDRQ pin is vital for sound blaster support. Some motherboards can be modded to expose LDRQ signal. 8 | * Also chipset is needed to be configured to allow IO ports access and enable LDRQ pin (for combined GPIO/LDRQ pin). See this for example software: https://github.com/rasteri/dISAppointment/tree/main 9 | * Sending malformed data to LPC bus can potentially corrupt BIOS of the PC, so PLEASE do backup of BIOS image before trying to attach anything to LPC bus. 10 | 11 | ## Testbench 12 | 13 | DE10-Nano attached to ASUS Maximus VII Ranger board (modded to expose LDRQ) 14 | 15 | ![image](testbench.jpg) 16 | -------------------------------------------------------------------------------- /sblaster.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2023 nukeykt 3 | * 4 | * This file is part of LPC-Sound-Blaster. 5 | * 6 | * This program is free software; you can redistribute it and/or 7 | * modify it under the terms of the GNU General Public License 8 | * as published by the Free Software Foundation; either version 2 9 | * of the License, or (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * Sound Blaster over LPC 17 | * Thanks: 18 | * Tube Time: 19 | * sound blaster firmware disassembly 20 | * The DOSBox Team: 21 | * useful info from sblaster.cpp 22 | * 23 | */ 24 | // lpc sound blaster 25 | module sblaster 26 | ( 27 | input CLK, // LPC Clock 28 | input reset, 29 | input LPC_FRM, 30 | inout [3:0] LPC_DATA, 31 | inout SERIRQ, 32 | output reg LPC_DREQ, 33 | 34 | output [15:0] audio_l, 35 | output [15:0] audio_r 36 | ); 37 | 38 | wire ym_clk = CLK; 39 | 40 | reg [16:0] ym_cnt; 41 | 42 | wire ym_clk2 = ym_cnt[16]; 43 | 44 | always @(posedge CLK) 45 | begin 46 | ym_cnt <= ym_cnt + 56301; 47 | end 48 | 49 | wire ym_ic = ~reset; 50 | 51 | reg [15:0] ym_left; 52 | reg [15:0] ym_right; 53 | reg [15:0] dac_shifter; 54 | reg o_sy; 55 | reg o_smpac; 56 | reg o_smpbd; 57 | reg sy; 58 | 59 | wire ym_sy; 60 | wire ym_doab; 61 | wire ym_smpac; 62 | wire ym_smpbd; 63 | 64 | reg ym_a0; 65 | reg ym_a1; 66 | reg ym_wr; 67 | reg ym_rd; 68 | reg ym_dir; 69 | 70 | always @(posedge ym_clk) 71 | begin 72 | if (~sy & o_sy) 73 | begin 74 | 75 | if (o_smpbd & ~ym_smpbd) 76 | ym_left <= dac_shifter ^ 16'h8000; 77 | if (o_smpac & ~ym_smpac) 78 | ym_right <= dac_shifter ^ 16'h8000; 79 | 80 | dac_shifter <= { ym_doab, dac_shifter[15:1] }; 81 | o_smpac <= ym_smpac; 82 | o_smpbd <= ym_smpbd; 83 | end 84 | 85 | o_sy <= sy; 86 | 87 | sy <= ym_sy; 88 | end 89 | 90 | reg [7:0] lpc_cnt; 91 | reg io_write; 92 | reg io_read; 93 | reg io_dmaread; 94 | reg [15:0] io_address; 95 | reg [7:0] wr_data; 96 | reg lpc_state; 97 | reg [3:0] lpc_out; 98 | reg ym_dir2; 99 | 100 | wire [7:0] ym_data_o; 101 | wire ym_data_d; 102 | 103 | reg [7:0] rd_data; 104 | 105 | ymf262 opl3 106 | ( 107 | .MCLK(ym_clk), 108 | .CLK(ym_clk2), 109 | .IC(ym_ic), 110 | .ADDRESS({ym_a1, ym_a0}), 111 | .DATA_i(wr_data), 112 | .DATA_o(ym_data_o), 113 | .DATA_d(ym_data_d), 114 | .WR(ym_wr), 115 | .RD(ym_rd), 116 | .CS(1'h0), 117 | .SY(ym_sy), 118 | .DOAB(ym_doab), 119 | .SMPAC(ym_smpac), 120 | .SMPBD(ym_smpbd) 121 | ); 122 | 123 | assign LPC_DATA = lpc_state ? lpc_out : 'hz; 124 | 125 | //assign ym_data = ym_dir2 ? wr_data : 'hz; 126 | 127 | wire [15:0] sbbase = 16'h220; 128 | wire [2:0] sbdma = 1; 129 | wire [7:0] sbirq = 7; 130 | 131 | wire issbaddr = (io_address & 16'hfff0) == sbbase; 132 | 133 | wire sba_adlib = io_address[3:2] == 2'h0 | io_address[3:1] == 3'h4; 134 | wire sba_mixer_a = io_address[3:0] == 4'h4; 135 | wire sba_mixer_d = io_address[3:0] == 4'h5; 136 | wire sba_reset = io_address[3:0] == 4'h6; 137 | wire sba_read_data = io_address[3:0] == 4'ha; 138 | wire sba_read_status = io_address[3:0] == 4'he; 139 | wire sba_write_data = io_address[3:0] == 4'hc; 140 | wire sba_dsp_busy = io_address[3:0] == 4'hc; 141 | 142 | wire isadlib = (io_address & 16'hfffc) == 16'h388 | (issbaddr & sba_adlib); 143 | 144 | wire goodaddr = isadlib | issbaddr; 145 | 146 | reg dsp_busy; 147 | 148 | 149 | reg [7:0] dsp_write; 150 | reg [7:0] dsp_read; 151 | 152 | reg dsp_write_rdy; 153 | reg dsp_read_rdy; 154 | reg dsp_reset; 155 | 156 | reg [15:0] dsp_fsm; 157 | reg [15:0] dsp_fsm_shadow; 158 | 159 | reg [15:0] dsp_length; 160 | reg [15:0] dsp_length2; 161 | reg [15:0] dsp_length3; 162 | 163 | reg [15:0] dsp_blocksize; 164 | 165 | reg dsp_dma; 166 | reg dsp_dma2; 167 | reg dsp_autoinit; 168 | reg dsp_pause; 169 | reg dsp_stereosel; 170 | 171 | reg [7:0] mxr_address; 172 | reg [7:0] mxr_reg4; 173 | reg [7:0] mxr_rega; 174 | reg [7:0] mxr_regc; 175 | reg [7:0] mxr_rege; 176 | reg [7:0] mxr_reg22; 177 | reg [7:0] mxr_reg26; 178 | reg [7:0] mxr_reg28; 179 | reg [7:0] mxr_reg2e; 180 | 181 | wire mxr_stereo = mxr_rege[1]; 182 | 183 | reg [7:0] dsp_tc; 184 | 185 | reg [16:0] dsp_prescaler; 186 | reg dsp_pof_o; 187 | wire dsp_pof = dsp_prescaler[16]; 188 | reg [7:0] dsp_counter; 189 | 190 | reg [7:0] dsp_dma_req; 191 | 192 | reg [2:0] io_dma_chan; 193 | reg [1:0] io_dma_size; 194 | reg [15:0] io_dma_data; 195 | reg io_dma_rdy; 196 | 197 | reg dsp_irq_req; 198 | reg dsp_irq_val; 199 | 200 | 201 | reg irq_sleep; 202 | reg [7:0] irq_state; 203 | reg [7:0] irq_stopcnt; 204 | 205 | reg sr_state; 206 | reg sr_value; 207 | reg sr_clear; 208 | 209 | reg [15:0] dsp_left; 210 | reg [15:0] dsp_right; 211 | 212 | reg [16:0] dac_left; 213 | reg [16:0] dac_right; 214 | 215 | assign audio_l = dac_left[15:0]; 216 | assign audio_r = dac_right[15:0]; 217 | 218 | reg dsp_spk; 219 | 220 | `define ADPCM_NONE 0 221 | `define ADPCM_4b 1 222 | `define ADPCM_3b 2 223 | `define ADPCM_2b 3 224 | reg [1:0] dsp_adpcm; 225 | reg [1:0] dsp_adpcm_cnt; 226 | reg [7:0] dsp_adpcm_ref; 227 | reg [2:0] dsp_adpcm_shift; 228 | reg [7:0] dsp_adpcm_byte; 229 | reg dsp_adpcm_refbyte; 230 | reg dsp_adpcm_rdy; 231 | 232 | reg dsp_adpcm_sign; 233 | reg [2:0] dsp_adpcm_val; 234 | reg dsp_adpcm_of; 235 | reg dsp_adpcm_adju; 236 | reg dsp_adpcm_adjd; 237 | reg [2:0] dsp_adpcm_shiftmax; 238 | 239 | wire [7:0] dsp_adpcm_add1 = ({ 6'h0, dsp_adpcm_val } << dsp_adpcm_shift) + (dsp_adpcm_shift != 3'h0 ? 8'h1 << (dsp_adpcm_shift - 3'h1) : 8'h0); 240 | wire [7:0] dsp_adpcm_adds = dsp_adpcm_sign ? -dsp_adpcm_add1 : dsp_adpcm_add1; 241 | wire [7:0] dsp_adpcm_sum = dsp_adpcm_ref + dsp_adpcm_adds; 242 | wire dsp_adpcm_sum_of = dsp_adpcm_ref[7] & ~dsp_adpcm_adds[7] & ~dsp_adpcm_sum[7]; 243 | wire dsp_adpcm_sum_uf = ~dsp_adpcm_ref[7] & dsp_adpcm_adds[7] & dsp_adpcm_sum[7]; 244 | wire [7:0] dsp_adpcm_clip = dsp_adpcm_sum_of ? 8'hff : (dsp_adpcm_sum_uf ? 8'h00 : dsp_adpcm_sum); 245 | 246 | reg dsp_silence; 247 | 248 | reg [7:0] dsp_cmd; 249 | 250 | always @(*) 251 | begin 252 | case (dsp_adpcm) 253 | `ADPCM_NONE: 254 | begin 255 | dsp_adpcm_sign <= 1'h0; 256 | dsp_adpcm_val <= 3'h0; 257 | dsp_adpcm_of <= 1'h0; 258 | dsp_adpcm_adju <= 1'h0; 259 | dsp_adpcm_adjd <= 1'h0; 260 | dsp_adpcm_shiftmax <= 3'h0; 261 | end 262 | `ADPCM_4b: 263 | begin 264 | if (dsp_adpcm_cnt == 2'h0) 265 | begin 266 | dsp_adpcm_sign <= dsp_adpcm_byte[7]; 267 | dsp_adpcm_val <= dsp_adpcm_byte[6:4]; 268 | end 269 | else 270 | begin 271 | dsp_adpcm_sign <= dsp_adpcm_byte[3]; 272 | dsp_adpcm_val <= dsp_adpcm_byte[2:0]; 273 | end 274 | dsp_adpcm_of <= dsp_adpcm_cnt == 2'h1; 275 | dsp_adpcm_adjd <= dsp_adpcm_val == 3'h0; 276 | dsp_adpcm_adju <= dsp_adpcm_val >= 3'h5; 277 | dsp_adpcm_shiftmax <= 3'h3; 278 | end 279 | `ADPCM_3b: 280 | begin 281 | if (dsp_adpcm_cnt == 2'h0) 282 | begin 283 | dsp_adpcm_sign <= dsp_adpcm_byte[7]; 284 | dsp_adpcm_val <= { 1'h0, dsp_adpcm_byte[6:5] }; 285 | end 286 | else if (dsp_adpcm_cnt == 2'h1) 287 | begin 288 | dsp_adpcm_sign <= dsp_adpcm_byte[4]; 289 | dsp_adpcm_val <= { 1'h0, dsp_adpcm_byte[3:2] }; 290 | end 291 | else 292 | begin 293 | dsp_adpcm_sign <= dsp_adpcm_byte[1]; 294 | dsp_adpcm_val <= { 2'h0, dsp_adpcm_byte[0] }; 295 | end 296 | dsp_adpcm_of <= dsp_adpcm_cnt == 2'h2; 297 | dsp_adpcm_adjd <= dsp_adpcm_val == 3'h0; 298 | dsp_adpcm_adju <= dsp_adpcm_val == 3'h3; 299 | dsp_adpcm_shiftmax <= 3'h4; 300 | end 301 | `ADPCM_2b: 302 | begin 303 | if (dsp_adpcm_cnt == 2'h0) 304 | begin 305 | dsp_adpcm_sign <= dsp_adpcm_byte[7]; 306 | dsp_adpcm_val <= { 2'h0, dsp_adpcm_byte[6] }; 307 | end 308 | else if (dsp_adpcm_cnt == 2'h1) 309 | begin 310 | dsp_adpcm_sign <= dsp_adpcm_byte[5]; 311 | dsp_adpcm_val <= { 2'h0, dsp_adpcm_byte[4] }; 312 | end 313 | else if (dsp_adpcm_cnt == 2'h2) 314 | begin 315 | dsp_adpcm_sign <= dsp_adpcm_byte[3]; 316 | dsp_adpcm_val <= { 2'h0, dsp_adpcm_byte[2] }; 317 | end 318 | else 319 | begin 320 | dsp_adpcm_sign <= dsp_adpcm_byte[1]; 321 | dsp_adpcm_val <= { 2'h0, dsp_adpcm_byte[0] }; 322 | end 323 | dsp_adpcm_of <= dsp_adpcm_cnt == 2'h3; 324 | dsp_adpcm_adjd <= dsp_adpcm_val == 3'h0; 325 | dsp_adpcm_adju <= dsp_adpcm_val == 3'h1; 326 | dsp_adpcm_shiftmax <= 3'h5; 327 | end 328 | endcase 329 | end 330 | 331 | assign SERIRQ = sr_state ? sr_value : 'hz; 332 | 333 | always @(posedge CLK) 334 | begin 335 | if (reset) 336 | begin 337 | lpc_cnt <= 0; 338 | io_write <= 0; 339 | io_read <= 0; 340 | lpc_state <= 0; 341 | lpc_out <= 0; 342 | ym_a0 <= 0; 343 | ym_a1 <= 0; 344 | ym_wr <= 1; 345 | ym_rd <= 1; 346 | ym_dir <= 1; 347 | ym_dir2 <= 1; 348 | 349 | io_dma_rdy <= 0; 350 | 351 | irq_sleep <= 1; 352 | irq_state <= 0; 353 | sr_state <= 0; 354 | sr_value <= 0; 355 | sr_clear <= 0; 356 | 357 | dsp_busy <= 0; 358 | dsp_write <= 0; 359 | dsp_read <= 0; 360 | dsp_write_rdy <= 0; 361 | dsp_read_rdy <= 0; 362 | dsp_reset <= 0; 363 | dsp_fsm <= 0; 364 | dsp_dma <= 0; 365 | dsp_dma2 <= 0; 366 | dsp_blocksize <= 0; 367 | dsp_autoinit <= 0; 368 | dsp_tc <= 0; 369 | dsp_length <= 0; 370 | dsp_length2 <= 0; 371 | dsp_length3 <= 0; 372 | dsp_dma_req <= 0; 373 | dsp_irq_req <= 0; 374 | dsp_irq_val <= 0; 375 | dsp_left <= 0; 376 | dsp_right <= 0; 377 | dsp_spk <= 0; 378 | dsp_pause <= 0; 379 | dsp_stereosel <= 0; 380 | dsp_cmd <= 0; 381 | 382 | dsp_adpcm <= 0; 383 | dsp_adpcm_cnt <= 0; 384 | dsp_adpcm_ref <= 0; 385 | dsp_adpcm_shift <= 0; 386 | dsp_adpcm_byte <= 0; 387 | dsp_adpcm_refbyte <= 0; 388 | dsp_adpcm_rdy <= 0; 389 | 390 | dsp_silence <= 0; 391 | 392 | mxr_address <= 0; 393 | mxr_reg4 <= 0; 394 | mxr_rega <= 0; 395 | mxr_regc <= 0; 396 | mxr_rege <= 0; 397 | mxr_reg22 <= 0; 398 | mxr_reg26 <= 0; 399 | mxr_reg28 <= 0; 400 | mxr_reg2e <= 0; 401 | 402 | LPC_DREQ <= 1; 403 | end 404 | else 405 | begin 406 | if (~LPC_FRM & LPC_DATA == 4'h0) 407 | begin 408 | lpc_cnt <= 1; 409 | end 410 | else if (lpc_cnt == 1) 411 | begin 412 | io_write <= LPC_DATA == 4'h2; 413 | io_read <= LPC_DATA == 4'h0; 414 | io_dmaread <= LPC_DATA == 4'h8; 415 | lpc_cnt <= 2; 416 | end 417 | else if (io_write) 418 | begin 419 | if (lpc_cnt == 6 & ~goodaddr) // ignore 420 | lpc_cnt <= 0; 421 | else if (lpc_cnt == 15) 422 | lpc_cnt <= 0; 423 | else 424 | lpc_cnt <= lpc_cnt + 1; 425 | case (lpc_cnt) 426 | 2: io_address[15:12] <= LPC_DATA; 427 | 3: io_address[11:8] <= LPC_DATA; 428 | 4: io_address[7:4] <= LPC_DATA; 429 | 5: io_address[3:0] <= LPC_DATA; 430 | 6: wr_data[3:0] <= LPC_DATA; 431 | 7: wr_data[7:4] <= LPC_DATA; 432 | 8: begin ym_a0 <= io_address[0]; ym_a1 <= io_address[1]; end 433 | // 8, 9 TAR 434 | 9: begin lpc_state <= 1; lpc_out <= 4'h6; end 435 | 13: lpc_out <= 4'h0; 436 | 14: lpc_out <= 4'hf; 437 | 15: begin lpc_state <= 0; end 438 | endcase 439 | if (isadlib) 440 | begin 441 | case (lpc_cnt) 442 | 9: ym_wr <= 0; 443 | 14: ym_wr <= 1; 444 | endcase 445 | end 446 | else if (issbaddr) 447 | begin 448 | if (lpc_cnt == 9) 449 | begin 450 | if (sba_reset) dsp_reset <= wr_data[0]; 451 | if (sba_write_data) begin dsp_write <= wr_data; dsp_write_rdy <= 1; end 452 | if (sba_mixer_a) mxr_address <= wr_data; 453 | if (sba_mixer_d) 454 | begin 455 | case (mxr_address) 456 | 8'h0: 457 | begin 458 | mxr_reg4 <= 8'h88; 459 | mxr_rega <= 8'h0; 460 | mxr_regc <= 8'h0; 461 | mxr_rege <= 8'h0; 462 | mxr_reg22 <= 8'h88; 463 | mxr_reg26 <= 8'h88; 464 | mxr_reg28 <= 8'h8; 465 | mxr_reg2e <= 8'h0; 466 | end 467 | 8'h4: mxr_reg4 <= wr_data; 468 | 8'ha: mxr_rega <= wr_data; 469 | 8'hc: mxr_regc <= wr_data; 470 | 8'he: mxr_rege <= wr_data; 471 | 8'h22: mxr_reg22 <= wr_data; 472 | 8'h26: mxr_reg26 <= wr_data; 473 | 8'h28: mxr_reg28 <= wr_data; 474 | 8'h2e: mxr_reg2e <= wr_data; 475 | endcase 476 | end 477 | end 478 | end 479 | end 480 | else if (io_read) 481 | begin 482 | if (lpc_cnt == 6 & ~goodaddr) // ignore 483 | lpc_cnt <= 0; 484 | else if (lpc_cnt == 15) 485 | lpc_cnt <= 0; 486 | else 487 | lpc_cnt <= lpc_cnt + 1; 488 | case (lpc_cnt) 489 | 2: io_address[15:12] <= LPC_DATA; 490 | 3: io_address[11:8] <= LPC_DATA; 491 | 4: io_address[7:4] <= LPC_DATA; 492 | 5: io_address[3:0] <= LPC_DATA; 493 | 6: begin ym_a0 <= io_address[0]; ym_a1 <= io_address[1]; end 494 | // 6, 7 TAR 495 | 7: begin lpc_state <= 1; lpc_out <= 4'h6; end 496 | 11: begin lpc_out <= 4'h0; end 497 | 12: lpc_out <= rd_data[3:0]; 498 | 13: lpc_out <= rd_data[7:4]; 499 | 14: begin lpc_out <= 4'hf; end 500 | 15: begin lpc_state <= 0; end 501 | endcase 502 | if (isadlib) 503 | begin 504 | case (lpc_cnt) 505 | 6: ym_dir2 <= 0; 506 | 7: begin ym_rd <= 0; ym_dir <= 0; end 507 | 11: rd_data <= ym_data_d ? 8'hff : ym_data_o; 508 | 14: begin ym_rd <= 1; ym_dir <= 1; end 509 | 15: ym_dir2 <= 1; 510 | endcase 511 | end 512 | else if (issbaddr) 513 | begin 514 | if (lpc_cnt == 7) 515 | begin 516 | if (sba_read_data) begin rd_data <= dsp_read; dsp_read_rdy <= 0; end 517 | else if (sba_read_status) begin rd_data <= { dsp_read_rdy, 7'h7f }; if (dsp_irq_val) begin dsp_irq_val <= 0; dsp_irq_req <= 1; end end 518 | else if (sba_dsp_busy) rd_data <= { dsp_busy, 7'h7f }; 519 | else if (sba_mixer_d) 520 | begin 521 | case (mxr_address) 522 | 8'h4: rd_data <= mxr_reg4; 523 | 8'ha: rd_data <= mxr_rega; 524 | 8'hc: rd_data <= mxr_regc; 525 | 8'he: rd_data <= mxr_rege; 526 | 8'h22: rd_data <= mxr_reg22; 527 | 8'h26: rd_data <= mxr_reg26; 528 | 8'h28: rd_data <= mxr_reg28; 529 | 8'h2e: rd_data <= mxr_reg2e; 530 | default: rd_data <= 8'h0; 531 | endcase 532 | end 533 | else rd_data <= 8'hff; 534 | end 535 | end 536 | end 537 | else if (io_dmaread) 538 | begin 539 | if (lpc_cnt == 4 & (io_dma_chan != sbdma | io_dma_size[1])) // ignore 540 | lpc_cnt <= 0; 541 | else if (lpc_cnt == 11) 542 | lpc_cnt <= 0; 543 | else if (lpc_cnt == 5 & ~io_dma_size[0]) 544 | lpc_cnt <= 8; 545 | else 546 | lpc_cnt <= lpc_cnt + 1; 547 | case (lpc_cnt) 548 | 2: io_dma_chan <= LPC_DATA[2:0]; 549 | 3: io_dma_size <= LPC_DATA[1:0]; 550 | 4: io_dma_data[3:0] <= LPC_DATA; 551 | 5: io_dma_data[7:4] <= LPC_DATA; 552 | 6: io_dma_data[11:8] <= LPC_DATA; 553 | 7: io_dma_data[15:12] <= LPC_DATA; 554 | // 8, 9 TAR 555 | 8: io_dma_rdy <= 1; 556 | 9: begin lpc_state <= 1; lpc_out <= 4'h0; end 557 | 10: lpc_out <= 4'hf; 558 | 11: lpc_state <= 0; 559 | endcase 560 | end 561 | else 562 | lpc_cnt <= 0; 563 | 564 | // sb dsp emulation 565 | 566 | `define DSP_IDLE 0 567 | `define DSP_READY_STATUS 1 568 | `define DSP_WAIT_READ 2 569 | `define DSP_WAIT_WRITE 3 570 | `define DSP_DSP_VERSION 16 571 | `define DSP_TC 32 572 | `define DSP_PLAYBACK 48 573 | `define DSP_PLAYBACK2 64 574 | `define DSP_BLOCKSIZE 80 575 | `define DSP_PLAYBACKAUTO 96 576 | `define DSP_SPKSTATUS 112 577 | `define DSP_PLAYBACK_ADPCM 128 578 | `define DSP_PLAYBACK_SILENCE 144 579 | `define DSP_CHECK 160 580 | 581 | if (dsp_reset) 582 | begin 583 | dsp_write_rdy <= 0; 584 | dsp_read_rdy <= 0; 585 | dsp_busy <= 0; 586 | dsp_dma <= 0; 587 | dsp_tc <= 0; 588 | dsp_blocksize <= 0; 589 | dsp_autoinit <= 0; 590 | dsp_length <= 0; 591 | dsp_length2 <= 0; 592 | dsp_length3 <= 0; 593 | dsp_dma_req <= 0; 594 | dsp_irq_req <= 0; 595 | dsp_left <= 0; 596 | dsp_right <= 0; 597 | // dsp_spk <= 0; disable for DIGPAK 598 | dsp_pause <= 0; 599 | dsp_stereosel <= 0; 600 | dsp_cmd <= 0; 601 | 602 | dsp_adpcm <= 0; 603 | dsp_adpcm_cnt <= 0; 604 | dsp_adpcm_ref <= 0; 605 | dsp_adpcm_shift <= 0; 606 | dsp_adpcm_byte <= 0; 607 | dsp_adpcm_refbyte <= 0; 608 | dsp_adpcm_rdy <= 0; 609 | 610 | dsp_silence <= 0; 611 | 612 | dsp_fsm <= `DSP_READY_STATUS; 613 | end 614 | else if (dsp_fsm == `DSP_IDLE) // idle 615 | begin 616 | if (dsp_write_rdy) 617 | begin 618 | case (dsp_write) 619 | 8'h14, 8'h91: begin if (dsp_dma & dsp_autoinit) dsp_fsm <= `DSP_PLAYBACK2; else dsp_fsm <= `DSP_PLAYBACK; dsp_stereosel <= 0; end 620 | 8'h1c, 8'h90: 621 | begin 622 | dsp_dma <= 1; 623 | dsp_length <= dsp_blocksize; 624 | dsp_autoinit <= 1; 625 | dsp_pause <= 0; 626 | dsp_stereosel <= 0; 627 | dsp_adpcm <= 2'h0; 628 | dsp_silence <= 0; 629 | end 630 | 8'h40: begin dsp_fsm <= `DSP_TC; end 631 | 8'h48: begin dsp_fsm <= `DSP_BLOCKSIZE; end 632 | 8'hd0: begin dsp_pause <= 1; end 633 | 8'hd1: begin dsp_spk <= 1; end 634 | 8'hd3: begin dsp_spk <= 0; end 635 | 8'hd4: begin dsp_pause <= 0; end 636 | 8'hd8: begin dsp_fsm <= `DSP_SPKSTATUS; end 637 | 8'hda: begin dsp_autoinit <= 0; end 638 | 8'he0: begin dsp_fsm <= `DSP_CHECK; end 639 | 8'he1: begin dsp_fsm <= `DSP_DSP_VERSION; end 640 | 8'h74,8'h75,8'h76,8'h77,8'h16,8'h17: 641 | begin 642 | dsp_fsm <= `DSP_PLAYBACK_ADPCM; 643 | end 644 | 8'h7d, 8'h7f, 8'h1f: 645 | begin 646 | dsp_dma <= 1; 647 | dsp_length <= dsp_blocksize; 648 | dsp_autoinit <= 1; 649 | dsp_pause <= 0; 650 | dsp_adpcm_refbyte <= 1; 651 | if (dsp_write == 8'h7d) 652 | dsp_adpcm <= `ADPCM_4b; 653 | else if (dsp_write == 8'h7f) 654 | dsp_adpcm <= `ADPCM_3b; 655 | else if (dsp_write == 8'h1f) 656 | dsp_adpcm <= `ADPCM_2b; 657 | else 658 | dsp_adpcm <= 2'h0; 659 | end 660 | 8'h80: 661 | begin 662 | dsp_fsm <= `DSP_PLAYBACK_SILENCE; 663 | end 664 | 8'hf2: 665 | begin 666 | dsp_irq_req <= 1; 667 | dsp_irq_val <= 1; 668 | end 669 | endcase 670 | dsp_write_rdy <= 0; 671 | dsp_cmd <= dsp_write; 672 | end 673 | end 674 | else if (dsp_fsm == `DSP_READY_STATUS) 675 | begin 676 | dsp_read <= 8'haa; 677 | dsp_read_rdy <= 1; 678 | dsp_fsm <= `DSP_WAIT_READ; 679 | dsp_fsm_shadow <= `DSP_IDLE; 680 | dsp_irq_req <= 1; // pull IRQ low (wolf3d/duke2) 681 | dsp_irq_val <= 0; 682 | end 683 | else if (dsp_fsm == `DSP_WAIT_READ) 684 | begin 685 | if (~dsp_read_rdy) 686 | dsp_fsm <= dsp_fsm_shadow; 687 | end 688 | else if (dsp_fsm == `DSP_WAIT_WRITE) 689 | begin 690 | if (dsp_write_rdy) 691 | dsp_fsm <= dsp_fsm_shadow; 692 | end 693 | else if (dsp_fsm == `DSP_DSP_VERSION) 694 | begin 695 | dsp_read <= 8'h03; 696 | dsp_read_rdy <= 1; 697 | dsp_fsm <= `DSP_WAIT_READ; 698 | dsp_fsm_shadow <= dsp_fsm + 1; 699 | end 700 | else if (dsp_fsm == `DSP_DSP_VERSION + 1) 701 | begin 702 | dsp_read <= 8'h00; 703 | dsp_read_rdy <= 1; 704 | dsp_fsm <= `DSP_WAIT_READ; 705 | dsp_fsm_shadow <= `DSP_IDLE; 706 | end 707 | else if (dsp_fsm == `DSP_TC) 708 | begin 709 | dsp_fsm <= `DSP_WAIT_WRITE; 710 | dsp_fsm_shadow <= dsp_fsm + 1; 711 | end 712 | else if (dsp_fsm == `DSP_TC + 1) 713 | begin 714 | dsp_tc <= dsp_write; 715 | dsp_write_rdy <= 0; 716 | dsp_fsm <= `DSP_IDLE; 717 | end 718 | else if (dsp_fsm == `DSP_PLAYBACK) 719 | begin 720 | dsp_fsm <= `DSP_WAIT_WRITE; 721 | dsp_fsm_shadow <= dsp_fsm + 1; 722 | end 723 | else if (dsp_fsm == `DSP_PLAYBACK + 1) 724 | begin 725 | dsp_length[7:0] <= dsp_write; 726 | dsp_write_rdy <= 0; 727 | dsp_fsm <= `DSP_WAIT_WRITE; 728 | dsp_fsm_shadow <= dsp_fsm + 1; 729 | end 730 | else if (dsp_fsm == `DSP_PLAYBACK + 2) 731 | begin 732 | dsp_length[15:8] <= dsp_write; 733 | dsp_dma <= 1; 734 | dsp_silence <= 0; 735 | dsp_pause <= 0; 736 | dsp_adpcm <= 2'h0; 737 | dsp_write_rdy <= 0; 738 | dsp_fsm <= `DSP_IDLE; 739 | end 740 | else if (dsp_fsm == `DSP_PLAYBACK2) 741 | begin 742 | dsp_fsm <= `DSP_WAIT_WRITE; 743 | dsp_fsm_shadow <= dsp_fsm + 1; 744 | end 745 | else if (dsp_fsm == `DSP_PLAYBACK2 + 1) 746 | begin 747 | dsp_length2[7:0] <= dsp_write; 748 | dsp_write_rdy <= 0; 749 | dsp_fsm <= `DSP_WAIT_WRITE; 750 | dsp_fsm_shadow <= dsp_fsm + 1; 751 | end 752 | else if (dsp_fsm == `DSP_PLAYBACK2 + 2) 753 | begin 754 | dsp_length2[15:8] <= dsp_write; 755 | dsp_dma2 <= 1; 756 | dsp_write_rdy <= 0; 757 | dsp_fsm <= `DSP_IDLE; 758 | end 759 | else if (dsp_fsm == `DSP_BLOCKSIZE) 760 | begin 761 | dsp_fsm <= `DSP_WAIT_WRITE; 762 | dsp_fsm_shadow <= dsp_fsm + 1; 763 | end 764 | else if (dsp_fsm == `DSP_BLOCKSIZE + 1) 765 | begin 766 | dsp_blocksize[7:0] <= dsp_write; 767 | dsp_write_rdy <= 0; 768 | dsp_fsm <= `DSP_WAIT_WRITE; 769 | dsp_fsm_shadow <= dsp_fsm + 1; 770 | end 771 | else if (dsp_fsm == `DSP_BLOCKSIZE + 2) 772 | begin 773 | dsp_blocksize[15:8] <= dsp_write; 774 | dsp_write_rdy <= 0; 775 | dsp_fsm <= `DSP_IDLE; 776 | end 777 | else if (dsp_fsm == `DSP_SPKSTATUS) 778 | begin 779 | dsp_read <= {8{dsp_spk}}; 780 | dsp_read_rdy <= 1; 781 | dsp_fsm <= `DSP_WAIT_READ; 782 | dsp_fsm_shadow <= `DSP_IDLE; 783 | end 784 | else if (dsp_fsm == `DSP_PLAYBACK_ADPCM) 785 | begin 786 | dsp_fsm <= `DSP_WAIT_WRITE; 787 | dsp_fsm_shadow <= dsp_fsm + 1; 788 | end 789 | else if (dsp_fsm == `DSP_PLAYBACK_ADPCM + 1) 790 | begin 791 | dsp_length[7:0] <= dsp_write; 792 | dsp_write_rdy <= 0; 793 | dsp_fsm <= `DSP_WAIT_WRITE; 794 | dsp_fsm_shadow <= dsp_fsm + 1; 795 | end 796 | else if (dsp_fsm == `DSP_PLAYBACK_ADPCM + 2) 797 | begin 798 | dsp_length[15:8] <= dsp_write; 799 | dsp_dma <= 1; 800 | dsp_silence <= 0; 801 | if (dsp_cmd[7:1] == 7'h3a) // 74 802 | dsp_adpcm <= `ADPCM_4b; 803 | else if (dsp_cmd[7:1] == 7'h3b) // 76 804 | dsp_adpcm <= `ADPCM_3b; 805 | else if (dsp_cmd[7:1] == 7'h0b) // 16 806 | dsp_adpcm <= `ADPCM_2b; 807 | else 808 | dsp_adpcm <= 2'h0; 809 | 810 | dsp_pause <= 0; 811 | dsp_adpcm_refbyte <= dsp_adpcm[0]; 812 | dsp_write_rdy <= 0; 813 | dsp_fsm <= `DSP_IDLE; 814 | end 815 | else if (dsp_fsm == `DSP_PLAYBACK_SILENCE) 816 | begin 817 | dsp_fsm <= `DSP_WAIT_WRITE; 818 | dsp_fsm_shadow <= dsp_fsm + 1; 819 | end 820 | else if (dsp_fsm == `DSP_PLAYBACK_SILENCE + 1) 821 | begin 822 | dsp_length3[7:0] <= dsp_write; 823 | dsp_write_rdy <= 0; 824 | dsp_fsm <= `DSP_WAIT_WRITE; 825 | dsp_fsm_shadow <= dsp_fsm + 1; 826 | end 827 | else if (dsp_fsm == `DSP_PLAYBACK_SILENCE + 2) 828 | begin 829 | dsp_length3[15:8] <= dsp_write; 830 | dsp_pause <= 0; 831 | dsp_silence <= 1; 832 | dsp_write_rdy <= 0; 833 | dsp_fsm <= `DSP_IDLE; 834 | end 835 | else if (dsp_fsm == `DSP_CHECK) 836 | begin 837 | dsp_fsm <= `DSP_WAIT_WRITE; 838 | dsp_fsm_shadow <= dsp_fsm + 1; 839 | end 840 | else if (dsp_fsm == `DSP_CHECK+1) 841 | begin 842 | dsp_read <= ~dsp_write; 843 | dsp_read_rdy <= 1; 844 | dsp_fsm <= `DSP_WAIT_READ; 845 | dsp_fsm_shadow <= `DSP_IDLE; 846 | end 847 | else 848 | dsp_fsm <= `DSP_IDLE; 849 | 850 | dsp_busy <= dsp_fsm != `DSP_IDLE & dsp_fsm != `DSP_WAIT_WRITE; 851 | 852 | // dsp timer 853 | dsp_prescaler <= dsp_prescaler + 1966; 854 | dsp_pof_o <= dsp_pof; 855 | if (dsp_pof_o != dsp_pof) 856 | begin 857 | dsp_counter = dsp_counter + 1; 858 | if (dsp_counter == 0 & ~dsp_pause) 859 | begin 860 | dsp_counter = dsp_tc; 861 | if (dsp_silence) 862 | begin 863 | dsp_length3 <= dsp_length3 - 1; 864 | if (dsp_length3 == 0) 865 | begin 866 | dsp_irq_req <= 1; 867 | dsp_irq_val <= 1; 868 | dsp_silence <= 0; 869 | end 870 | end 871 | else if (dsp_dma) 872 | begin 873 | if (dsp_adpcm != 2'h0) 874 | begin 875 | if (dsp_adpcm_refbyte) 876 | begin 877 | // request first byte as-is 878 | dsp_dma_req <= 1; 879 | dsp_length <= dsp_length - 1; 880 | end 881 | else 882 | begin 883 | dsp_adpcm_ref <= dsp_adpcm_clip; 884 | dsp_adpcm_rdy <= 1; 885 | if (dsp_adpcm_adju) 886 | begin 887 | if (dsp_adpcm_shift != dsp_adpcm_shiftmax) 888 | dsp_adpcm_shift <= dsp_adpcm_shift + 3'h1; 889 | end 890 | else if (dsp_adpcm_adjd) 891 | begin 892 | if (dsp_adpcm_shift != 3'h0) 893 | dsp_adpcm_shift <= dsp_adpcm_shift - 3'h1; 894 | end 895 | if (dsp_adpcm_of) 896 | begin 897 | dsp_adpcm_cnt <= 2'h0; 898 | dsp_dma_req <= 1; 899 | dsp_length <= dsp_length - 1; 900 | end 901 | else 902 | dsp_adpcm_cnt <= dsp_adpcm_cnt + 2'h1; 903 | end 904 | end 905 | else 906 | begin 907 | dsp_dma_req <= 1; 908 | dsp_length <= dsp_length - 1; 909 | end 910 | if (dsp_length == 0 && (dsp_adpcm == 2'h0 || dsp_adpcm_of)) 911 | begin 912 | if (dsp_autoinit) 913 | begin 914 | dsp_length <= dsp_blocksize; 915 | end 916 | else if (dsp_dma2) 917 | begin 918 | dsp_length <= dsp_length2; 919 | dsp_dma2 <= 0; 920 | dsp_dma <= 1; 921 | dsp_adpcm <= 2'h0; 922 | end 923 | else 924 | dsp_dma <= 0; 925 | dsp_irq_req <= 1; 926 | dsp_irq_val <= 1; 927 | dsp_silence <= 0; 928 | end 929 | end 930 | end 931 | end 932 | 933 | // dma ctrl 934 | if (dsp_dma_req == 1) 935 | begin 936 | LPC_DREQ <= 0; 937 | dsp_dma_req <= 2; 938 | end 939 | else if (dsp_dma_req == 2) 940 | begin 941 | LPC_DREQ <= sbdma[2]; 942 | dsp_dma_req <= 3; 943 | end 944 | else if (dsp_dma_req == 3) 945 | begin 946 | LPC_DREQ <= sbdma[1]; 947 | dsp_dma_req <= 4; 948 | end 949 | else if (dsp_dma_req == 4) 950 | begin 951 | LPC_DREQ <= sbdma[0]; 952 | dsp_dma_req <= 5; 953 | end 954 | else if (dsp_dma_req == 5) 955 | begin 956 | LPC_DREQ <= 1; 957 | dsp_dma_req <= 6; 958 | end 959 | else if (dsp_dma_req == 6) 960 | begin 961 | LPC_DREQ <= 1; 962 | dsp_dma_req <= 0; 963 | end 964 | 965 | // dma cancel 966 | if (dsp_dma_req == 11) 967 | begin 968 | LPC_DREQ <= 0; 969 | dsp_dma_req <= 12; 970 | end 971 | else if (dsp_dma_req == 12) 972 | begin 973 | LPC_DREQ <= sbdma[2]; 974 | dsp_dma_req <= 13; 975 | end 976 | else if (dsp_dma_req == 13) 977 | begin 978 | LPC_DREQ <= sbdma[1]; 979 | dsp_dma_req <= 14; 980 | end 981 | else if (dsp_dma_req == 14) 982 | begin 983 | LPC_DREQ <= sbdma[0]; 984 | dsp_dma_req <= 15; 985 | end 986 | else if (dsp_dma_req == 15) 987 | begin 988 | LPC_DREQ <= 0; 989 | dsp_dma_req <= 16; 990 | end 991 | else if (dsp_dma_req == 16) 992 | begin 993 | LPC_DREQ <= 1; 994 | dsp_dma_req <= 0; 995 | end 996 | 997 | if (irq_sleep & dsp_irq_req & irq_state == 0) 998 | begin 999 | sr_state <= 1; 1000 | sr_value <= 0; 1001 | sr_clear <= 1; 1002 | irq_sleep <= 0; 1003 | dsp_irq_req <= 0; 1004 | end 1005 | else if (sr_clear) 1006 | begin 1007 | sr_state <= 0; 1008 | sr_clear <= 0; 1009 | end 1010 | 1011 | if (irq_state == 0) 1012 | begin 1013 | if (~SERIRQ) 1014 | irq_state <= 1; 1015 | end 1016 | else if (irq_state == 1) 1017 | begin 1018 | if (SERIRQ) 1019 | irq_state <= 255; 1020 | end 1021 | else if (irq_state == 100) 1022 | begin 1023 | irq_state <= 101; 1024 | end 1025 | else if (irq_state == 101) 1026 | begin 1027 | irq_sleep <= SERIRQ; 1028 | irq_state <= 102; 1029 | end 1030 | else if (irq_state == 102) 1031 | begin 1032 | irq_state <= 103; 1033 | end 1034 | else if (irq_state == 103) 1035 | begin 1036 | irq_state <= 0; 1037 | end 1038 | else if (irq_state == 255 - sbirq * 3) 1039 | begin 1040 | sr_state <= 1; 1041 | sr_value <= dsp_irq_val; 1042 | irq_state <= irq_state - 1; 1043 | end 1044 | else if (irq_state == 254 - sbirq * 3) 1045 | begin 1046 | sr_value <= 1; 1047 | irq_state <= irq_state - 1; 1048 | end 1049 | else if (irq_state == 253 - sbirq * 3) 1050 | begin 1051 | sr_state <= 0; 1052 | irq_state <= irq_state - 1; 1053 | end 1054 | else if (irq_state == 255 - 48) 1055 | begin 1056 | if (~SERIRQ) 1057 | irq_state <= 100; 1058 | end 1059 | else 1060 | begin 1061 | irq_state <= irq_state - 1; 1062 | end 1063 | 1064 | 1065 | if (dsp_adpcm != 2'h0) 1066 | begin 1067 | if (io_dma_rdy & dsp_adpcm_refbyte) 1068 | begin 1069 | // reference byte 1070 | dsp_adpcm_ref <= io_dma_data; 1071 | dsp_left <= { {2{~io_dma_data[7]}}, io_dma_data[6:0], 7'h0 }; 1072 | dsp_right <= { {2{~io_dma_data[7]}}, io_dma_data[6:0], 7'h0 }; 1073 | dsp_adpcm_refbyte <= 1'h0; 1074 | io_dma_rdy <= 0; 1075 | end 1076 | else 1077 | begin 1078 | if (dsp_adpcm_rdy) 1079 | begin 1080 | dsp_left <= { {2{~dsp_adpcm_ref[7]}}, dsp_adpcm_ref[6:0], 7'h0 }; 1081 | dsp_right <= { {2{~dsp_adpcm_ref[7]}}, dsp_adpcm_ref[6:0], 7'h0 }; 1082 | dsp_adpcm_rdy <= 1'h0; 1083 | end 1084 | if (io_dma_rdy) 1085 | begin 1086 | dsp_adpcm_byte <= io_dma_data; 1087 | io_dma_rdy <= 0; 1088 | end 1089 | end 1090 | end 1091 | else if (io_dma_rdy) 1092 | begin 1093 | if (~mxr_stereo | dsp_stereosel == 1) 1094 | dsp_left <= { {2{~io_dma_data[7]}}, io_dma_data[6:0], 7'h0 }; 1095 | if (~mxr_stereo | dsp_stereosel == 0) 1096 | dsp_right <= { {2{~io_dma_data[7]}}, io_dma_data[6:0], 7'h0 }; 1097 | 1098 | dsp_stereosel <= ~dsp_stereosel; 1099 | io_dma_rdy <= 0; 1100 | end 1101 | 1102 | if (dsp_silence) 1103 | begin 1104 | dsp_left <= 16'h0; 1105 | dsp_right <= 16'h0; 1106 | end 1107 | 1108 | dac_left = { ym_left[15], ym_left } + (dsp_spk ? { dsp_left[15], dsp_left } : 17'h0); 1109 | dac_right = { ym_right[15], ym_right } + (dsp_spk ? { dsp_right[15], dsp_right } : 17'h0); 1110 | 1111 | if (dac_left[16:15] == 2'b01) 1112 | dac_left = 17'h07fff; 1113 | if (dac_left[16:15] == 2'b10) 1114 | dac_left = 17'h18000; 1115 | 1116 | if (dac_right[16:15] == 2'b01) 1117 | dac_right = 17'h07fff; 1118 | if (dac_right[16:15] == 2'b10) 1119 | dac_right = 17'h18000; 1120 | 1121 | end 1122 | end 1123 | 1124 | endmodule 1125 | -------------------------------------------------------------------------------- /testbench.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nukeykt/LPC-Sound-Blaster/9b8063d5f1d76b2921aebf7b5c8420e33c221a04/testbench.jpg -------------------------------------------------------------------------------- /ym_lib.v: -------------------------------------------------------------------------------- 1 | module ym_sr_bit #(parameter SR_LENGTH = 1) 2 | ( 3 | input MCLK, 4 | input c1, 5 | input c2, 6 | input inp, 7 | output val 8 | ); 9 | 10 | reg [SR_LENGTH-1:0] v1 = 0; 11 | reg [SR_LENGTH-1:0] v2 = 0; 12 | 13 | wire [SR_LENGTH-1:0] v2_assign = c2 ? v1 : v2; 14 | 15 | assign val = v2[SR_LENGTH-1]; 16 | 17 | always @(posedge MCLK) 18 | begin 19 | if (c1) 20 | begin 21 | if (SR_LENGTH == 1) 22 | v1 <= inp; 23 | else 24 | v1 <= { v2[SR_LENGTH-2:0], inp }; 25 | end 26 | v2 <= v2_assign; 27 | end 28 | endmodule 29 | 30 | module ym_sr_bit_array #(parameter SR_LENGTH = 1, DATA_WIDTH = 1) 31 | ( 32 | input MCLK, 33 | input c1, 34 | input c2, 35 | input [DATA_WIDTH-1:0] inp, 36 | output [DATA_WIDTH-1:0] val 37 | ); 38 | 39 | wire out[0:DATA_WIDTH-1]; 40 | 41 | generate 42 | genvar i; 43 | for (i = 0; i < DATA_WIDTH; i = i + 1) 44 | begin : l1 45 | ym_sr_bit #(.SR_LENGTH(SR_LENGTH)) sr ( 46 | .MCLK(MCLK), 47 | .c1(c1), 48 | .c2(c2), 49 | .inp(inp[i]), 50 | .val(out[i]) 51 | ); 52 | 53 | assign val[i] = out[i]; 54 | end 55 | endgenerate 56 | 57 | endmodule 58 | 59 | module ym_cnt_bit #(parameter DATA_WIDTH = 1) 60 | ( 61 | input MCLK, 62 | input c1, 63 | input c2, 64 | input c_in, 65 | input rst, 66 | output [DATA_WIDTH-1:0] val, 67 | output c_out 68 | ); 69 | 70 | wire [DATA_WIDTH-1:0] data_in; 71 | wire [DATA_WIDTH-1:0] data_out; 72 | wire [DATA_WIDTH:0] sum; 73 | 74 | ym_sr_bit_array #(.DATA_WIDTH(DATA_WIDTH)) mem 75 | ( 76 | .MCLK(MCLK), 77 | .c1(c1), 78 | .c2(c2), 79 | .inp(data_in), 80 | .val(data_out) 81 | ); 82 | 83 | assign sum = { 1'h0, data_out } + {{DATA_WIDTH{1'h0}}, c_in}; 84 | assign val = data_out; 85 | assign data_in = rst ? {DATA_WIDTH{1'h0}} : sum[DATA_WIDTH-1:0]; 86 | assign c_out = sum[DATA_WIDTH]; 87 | 88 | endmodule 89 | 90 | module ym_dlatch #(parameter DATA_WIDTH = 1) 91 | ( 92 | input MCLK, 93 | input en, 94 | input [DATA_WIDTH-1:0] inp, 95 | output [DATA_WIDTH-1:0] val, 96 | output [DATA_WIDTH-1:0] nval 97 | ); 98 | 99 | reg [DATA_WIDTH-1:0] mem = {DATA_WIDTH{1'h0}}; 100 | 101 | wire [DATA_WIDTH-1:0] mem_assign = en ? inp : mem; 102 | 103 | always @(posedge MCLK) 104 | begin 105 | mem <= mem_assign; 106 | end 107 | 108 | //assign val = mem_assign; 109 | //assign nval = ~mem_assign; 110 | assign val = mem; 111 | assign nval = ~mem; 112 | 113 | endmodule 114 | 115 | module ym_edge_detect 116 | ( 117 | input MCLK, 118 | input c1, 119 | input inp, 120 | output val 121 | ); 122 | 123 | wire prev_out; 124 | 125 | ym_dlatch prev 126 | ( 127 | .MCLK(MCLK), 128 | .en(c1), 129 | .inp(inp), 130 | .val(prev_out), 131 | .nval() 132 | ); 133 | assign val = ~(prev_out | ~inp); 134 | endmodule 135 | 136 | module ym_slatch #(parameter DATA_WIDTH = 1) 137 | ( 138 | input MCLK, 139 | input en, 140 | input [DATA_WIDTH-1:0] inp, 141 | output [DATA_WIDTH-1:0] val, 142 | output [DATA_WIDTH-1:0] nval 143 | ); 144 | 145 | reg [DATA_WIDTH-1:0] mem = {DATA_WIDTH{1'h0}}; 146 | 147 | wire [DATA_WIDTH-1:0] mem_assign = en ? inp : mem; 148 | 149 | always @(posedge MCLK) 150 | begin 151 | mem <= mem_assign; 152 | end 153 | 154 | assign val = mem; 155 | assign nval = ~mem; 156 | 157 | endmodule 158 | 159 | module ym_rs_trig 160 | ( 161 | input MCLK, 162 | input set, 163 | input rst, 164 | output reg q = 1'h0, 165 | output reg nq = 1'h1 166 | ); 167 | 168 | always @(posedge MCLK) 169 | begin 170 | q <= rst ? 1'h0 : (set ? 1'h1 : q); 171 | nq <= set ? 1'h0 : (rst ? 1'h1 : ~q); 172 | end 173 | 174 | endmodule 175 | 176 | module ym_cnt_bit_load #(parameter DATA_WIDTH = 1) 177 | ( 178 | input MCLK, 179 | input c1, 180 | input c2, 181 | input c_in, 182 | input rst, 183 | input load, 184 | input [DATA_WIDTH-1:0] load_val, 185 | output [DATA_WIDTH-1:0] val, 186 | output c_out 187 | ); 188 | 189 | wire [DATA_WIDTH-1:0] data_in; 190 | wire [DATA_WIDTH-1:0] data_out; 191 | wire [DATA_WIDTH:0] sum; 192 | 193 | ym_sr_bit_array #(.DATA_WIDTH(DATA_WIDTH)) mem 194 | ( 195 | .MCLK(MCLK), 196 | .c1(c1), 197 | .c2(c2), 198 | .inp(data_in), 199 | .val(data_out) 200 | ); 201 | 202 | wire [DATA_WIDTH-1:0] base_val = load ? load_val : data_out; 203 | 204 | assign sum = {1'h0, base_val} + {{DATA_WIDTH{1'h0}},c_in}; 205 | assign data_in = rst ? {DATA_WIDTH{1'h0}} : sum[DATA_WIDTH-1:0]; 206 | assign val = data_out; 207 | assign c_out = sum[DATA_WIDTH]; 208 | 209 | endmodule 210 | 211 | module ym_dbg_read #(parameter DATA_WIDTH = 1) 212 | ( 213 | input MCLK, 214 | input c1, 215 | input c2, 216 | input prev, 217 | input load, 218 | input [DATA_WIDTH-1:0] load_val, 219 | output next 220 | ); 221 | 222 | wire [DATA_WIDTH-1:0] data_in; 223 | wire [DATA_WIDTH-1:0] data_out; 224 | 225 | ym_sr_bit_array #(.DATA_WIDTH(DATA_WIDTH)) mem 226 | ( 227 | .MCLK(MCLK), 228 | .c1(c1), 229 | .c2(c2), 230 | .inp(data_in), 231 | .val(data_out) 232 | ); 233 | 234 | wire [DATA_WIDTH-1:0] chain; 235 | 236 | assign data_in = chain | (load ? load_val : {DATA_WIDTH{1'h0}}); 237 | 238 | generate 239 | if (DATA_WIDTH == 1) 240 | assign chain = prev; 241 | else 242 | assign chain = { prev, data_out[DATA_WIDTH-1:1] }; 243 | endgenerate 244 | 245 | assign next = data_out[0]; 246 | 247 | endmodule 248 | 249 | module ym_dbg_read_eg #(parameter DATA_WIDTH = 1) 250 | ( 251 | input MCLK, 252 | input c1, 253 | input c2, 254 | input prev, 255 | input load, 256 | input [DATA_WIDTH-1:0] load_val, 257 | output next 258 | ); 259 | 260 | wire [DATA_WIDTH-1:0] data_in; 261 | wire [DATA_WIDTH-1:0] data_out; 262 | 263 | ym_sr_bit_array #(.DATA_WIDTH(DATA_WIDTH)) mem 264 | ( 265 | .MCLK(MCLK), 266 | .c1(c1), 267 | .c2(c2), 268 | .data_in(data_in), 269 | .data_out(data_out) 270 | ); 271 | 272 | wire [DATA_WIDTH-1:0] chain; 273 | 274 | assign data_in = chain | (load ? load_val : {DATA_WIDTH{1'h0}}); 275 | 276 | generate 277 | if (DATA_WIDTH == 1) 278 | assign chain = prev; 279 | else 280 | assign chain = { data_out[DATA_WIDTH-2:0], prev }; 281 | endgenerate 282 | 283 | assign next = data_out[DATA_WIDTH-1]; 284 | 285 | endmodule 286 | 287 | module ym_slatch_r #(parameter DATA_WIDTH = 1) 288 | ( 289 | input MCLK, 290 | input en, 291 | input rst, 292 | input [DATA_WIDTH-1:0] inp, 293 | output [DATA_WIDTH-1:0] val, 294 | output [DATA_WIDTH-1:0] nval 295 | ); 296 | 297 | reg [DATA_WIDTH-1:0] mem = {DATA_WIDTH{1'h0}}; 298 | 299 | wire [DATA_WIDTH-1:0] mem_assign = rst ? {DATA_WIDTH{1'h0}} : (en ? inp : mem); 300 | 301 | always @(posedge MCLK) 302 | begin 303 | mem <= mem_assign; 304 | end 305 | 306 | assign val = mem; 307 | assign nval = ~mem; 308 | 309 | endmodule 310 | -------------------------------------------------------------------------------- /ymf262.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2023 nukeykt 3 | * 4 | * This file is part of LPC-Sound-Blaster. 5 | * 6 | * This program is free software; you can redistribute it and/or 7 | * modify it under the terms of the GNU General Public License 8 | * as published by the Free Software Foundation; either version 2 9 | * of the License, or (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * YMF262 emulator 17 | * Thanks: 18 | * John McMaster (siliconpr0n.org): 19 | * YMF262 decap and die shot 20 | * 21 | */ 22 | module ymf262 23 | ( 24 | input MCLK, 25 | input CLK, 26 | input IC, 27 | input [1:0] ADDRESS, 28 | input [7:0] DATA_i, 29 | output [7:0] DATA_o, 30 | output DATA_d, 31 | input WR, 32 | input RD, 33 | input CS, 34 | output TEST, 35 | output SY, 36 | output DOCD, 37 | output DOAB, 38 | output SMPAC, 39 | output SMPBD, 40 | output IRQ_pull 41 | ); 42 | 43 | wire mclk1 = ~CLK; 44 | wire mclk2 = CLK; 45 | 46 | wire io_rd = ~RD; 47 | wire io_wr = ~WR; 48 | wire io_cs = ~CS; 49 | wire io_a0 = ADDRESS[0]; 50 | wire io_a1 = ADDRESS[1]; 51 | 52 | wire reset0; 53 | ym_sr_bit #(.SR_LENGTH(2)) l_ic_latch(.MCLK(MCLK), .c1(mclk1), .c2(mclk2), .inp(~IC), .val(reset0)); 54 | 55 | wire io_read = ~reset0 & io_cs & io_rd & ~io_a0 & ~io_a1; 56 | wire io_write = ~reset0 & io_cs & io_wr; 57 | wire io_write0 = ~reset0 & io_cs & io_wr & ~io_a0; 58 | wire io_write1 = ~reset0 & io_cs & io_wr & io_a0; 59 | 60 | wire [7:0] data_latch; 61 | ym_slatch_r #(.DATA_WIDTH(8)) l_data_latch(.MCLK(MCLK), .en(io_write), .rst(reset0), .inp(DATA_i), .val(data_latch)); 62 | wire bank_latch; 63 | ym_slatch_r l_bank_latch(.MCLK(MCLK), .en(io_write), .rst(reset0), .inp(io_a1), .val(bank_latch)); 64 | 65 | wire [7:0]reg_test1; 66 | wire reset1 = reset0 | reg_test1[7:6] == 2'h3; 67 | 68 | wire prescaler1_reset; 69 | ym_sr_bit #(.SR_LENGTH(2)) l_prescaler1_reset(.MCLK(MCLK), .c1(mclk1), .c2(mclk2), .inp(reset1), .val(prescaler1_reset)); 70 | 71 | wire [1:0] prescaler1_cnt; 72 | ym_cnt_bit #(.DATA_WIDTH(2)) l_prescaler1_cnt(.MCLK(MCLK), .c1(mclk1), .c2(mclk2), .c_in(1'h1), .rst(~prescaler1_reset & reset1), .val(prescaler1_cnt)); 73 | 74 | wire prescaler1_clk = reg_test1[6] ? CLK : ~prescaler1_cnt[1]; 75 | 76 | wire aclk1 = ~prescaler1_clk; 77 | wire aclk2 = prescaler1_clk; 78 | 79 | wire prescaler2_reset_l; 80 | ym_sr_bit #(.SR_LENGTH(2)) l_prescaler2_reset(.MCLK(MCLK), .c1(aclk1), .c2(aclk2), .inp(reset1), .val(prescaler2_reset_l)); 81 | 82 | wire prescaler2_reset = ~prescaler2_reset_l & reset1; 83 | 84 | wire [1:0] prescaler2_cnt; 85 | ym_cnt_bit #(.DATA_WIDTH(2)) l_prescaler2_cnt(.MCLK(MCLK), .c1(aclk1), .c2(aclk2), .c_in(1'h1), .rst(prescaler2_reset), .val(prescaler2_cnt)); 86 | 87 | wire prescaler2_l1; 88 | ym_sr_bit l_prescaler2_l1(.MCLK(MCLK), .c1(aclk1), .c2(aclk2), .inp(~prescaler2_reset & ~prescaler2_cnt[0]), .val(prescaler2_l1)); 89 | 90 | wire clk1; 91 | ym_edge_detect l_clk1(.MCLK(MCLK), .c1(aclk1), .inp(prescaler2_l1), .val(clk1)); 92 | 93 | wire prescaler2_l3; 94 | ym_sr_bit l_prescaler2_l3(.MCLK(MCLK), .c1(aclk1), .c2(aclk2), .inp(~prescaler2_reset & prescaler2_cnt[0]), .val(prescaler2_l3)); 95 | 96 | wire clk2; 97 | ym_edge_detect l_clk2(.MCLK(MCLK), .c1(aclk1), .inp(prescaler2_l3), .val(clk2)); 98 | 99 | wire rclk2; 100 | ym_sr_bit l_prescaler2_l5(.MCLK(MCLK), .c1(aclk1), .c2(aclk2), .inp(~prescaler2_reset & prescaler2_cnt == 2'h3), .val(rclk2)); 101 | 102 | wire rclk1; 103 | ym_sr_bit l_prescaler2_l6(.MCLK(MCLK), .c1(aclk1), .c2(aclk2), .inp(~prescaler2_reset & prescaler2_cnt == 2'h1), .val(rclk1)); 104 | 105 | wire prescaler2_l7; 106 | ym_dlatch l_prescaler2_l7(.MCLK(MCLK), .en(aclk1), .inp(~prescaler2_cnt[0]), .val(prescaler2_l7)); 107 | 108 | wire bclk = ~prescaler2_reset & prescaler2_l7 & ~prescaler2_cnt[0]; 109 | 110 | wire reg_sel1; 111 | ym_slatch_r l_reg_sel1(.MCLK(MCLK), .en(write0), .rst(reset0), .inp(data_latch == 8'h1), .val(reg_sel1)); 112 | wire reg_sel2; 113 | ym_slatch_r l_reg_sel2(.MCLK(MCLK), .en(write0), .rst(reset0), .inp(data_latch == 8'h2), .val(reg_sel2)); 114 | wire reg_sel3; 115 | ym_slatch_r l_reg_sel3(.MCLK(MCLK), .en(write0), .rst(reset0), .inp(data_latch == 8'h3), .val(reg_sel3)); 116 | wire reg_sel4; 117 | ym_slatch_r l_reg_sel4(.MCLK(MCLK), .en(write0), .rst(reset0), .inp(data_latch == 8'h4), .val(reg_sel4)); 118 | wire reg_sel5; 119 | ym_slatch_r l_reg_sel5(.MCLK(MCLK), .en(write0), .rst(reset0), .inp(data_latch == 8'h5), .val(reg_sel5)); 120 | wire reg_sel8; 121 | ym_slatch_r l_reg_sel8(.MCLK(MCLK), .en(write0), .rst(reset0), .inp(data_latch == 8'h8), .val(reg_sel8)); 122 | wire reg_selbd; 123 | ym_slatch_r l_reg_selbd(.MCLK(MCLK), .en(write0), .rst(reset0), .inp(data_latch == 8'hbd), .val(reg_selbd)); 124 | 125 | wire write0_l; 126 | wire write1_l; 127 | 128 | reg write0_sr; 129 | reg write1_sr; 130 | always @(posedge MCLK) 131 | begin 132 | if (io_write0) 133 | write0_sr <= 1'h1; 134 | else if (reset0 | write0_l) 135 | write0_sr <= 1'h0; 136 | if (io_write1) 137 | write1_sr <= 1'h1; 138 | else if (reset0 | write1_l) 139 | write1_sr <= 1'h0; 140 | end 141 | 142 | ym_sr_bit l_write0_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(write0_sr), .val(write0_l)); 143 | ym_sr_bit l_write1_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(write1_sr), .val(write1_l)); 144 | wire write0_l2; 145 | ym_sr_bit l_write0_l2(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(write0_l), .val(write0_l2)); 146 | wire write1_l2; 147 | ym_sr_bit l_write1_l2(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(write1_l), .val(write1_l2)); 148 | 149 | wire write0 = write0_l2 & ~write0_l; 150 | wire write1 = write1_l2 & ~write1_l; 151 | 152 | wire reg_new; 153 | ym_slatch_r l_reg_new(.MCLK(MCLK), .en(write1 & bank_latch & reg_sel5), .rst(reset0), .inp(data_latch[0]), .val(reg_new)); 154 | 155 | wire bank_masked = reg_new & bank_latch; 156 | 157 | wire [7:0] reg_test0; 158 | ym_slatch_r #(.DATA_WIDTH(8)) l_reg_test0(.MCLK(MCLK), .en(write1 & ~bank_masked & reg_sel1), .rst(reset0), .inp(data_latch), .val(reg_test0)); 159 | 160 | wire [7:0] reg_timer1; 161 | ym_slatch_r #(.DATA_WIDTH(8)) l_reg_timer1(.MCLK(MCLK), .en(write1 & ~bank_masked & reg_sel2), .rst(reset0), .inp(data_latch), .val(reg_timer1)); 162 | 163 | wire [7:0] reg_timer2; 164 | ym_slatch_r #(.DATA_WIDTH(8)) l_reg_timer2(.MCLK(MCLK), .en(write1 & ~bank_masked & reg_sel3), .rst(reset0), .inp(data_latch), .val(reg_timer2)); 165 | 166 | wire reg_notesel; 167 | ym_slatch_r l_reg_notesel(.MCLK(MCLK), .en(write1 & ~bank_masked & reg_sel8), .rst(reset0), .inp(data_latch[6]), .val(reg_notesel)); 168 | 169 | wire [4:0] reg_rh_kon; 170 | ym_slatch_r #(.DATA_WIDTH(5)) l_reg_rh_kon(.MCLK(MCLK), .en(write1 & ~bank_masked & reg_selbd), .rst(reset0), .inp(data_latch[4:0]), .val(reg_rh_kon)); 171 | wire rhythm; 172 | ym_slatch_r l_rhythm(.MCLK(MCLK), .en(write1 & ~bank_masked & reg_selbd), .rst(reset0), .inp(data_latch[5]), .val(rhythm)); 173 | wire reg_dv; 174 | ym_slatch_r l_reg_dv(.MCLK(MCLK), .en(write1 & ~bank_masked & reg_selbd), .rst(reset0), .inp(data_latch[6]), .val(reg_dv)); 175 | wire reg_da; 176 | ym_slatch_r l_reg_da(.MCLK(MCLK), .en(write1 & ~bank_masked & reg_selbd), .rst(reset0), .inp(data_latch[7]), .val(reg_da)); 177 | 178 | ym_slatch_r #(.DATA_WIDTH(8)) l_reg_test1(.MCLK(MCLK), .en(write1 & bank_masked & reg_sel1), .rst(reset0), .inp(data_latch), .val(reg_test1)); 179 | wire [5:0] reg_4op; 180 | ym_slatch_r #(.DATA_WIDTH(6)) l_reg_4op(.MCLK(MCLK), .en(write1 & bank_masked & reg_sel4), .rst(reset0), .inp(data_latch[5:0]), .val(reg_4op)); 181 | 182 | wire reg_sel4_wr = write1 & reg_sel4 & ~bank_masked & ~data_latch[7]; 183 | wire reg_sel4_rst = (write1 & reg_sel4 & ~bank_masked & data_latch[7]) | reset0; 184 | 185 | wire reg_t1_mask; 186 | ym_slatch_r l_reg_t1_mask(.MCLK(MCLK), .en(reg_sel4_wr), .rst(reset0), .inp(data_latch[6]), .val(reg_t1_mask)); 187 | wire reg_t2_mask; 188 | ym_slatch_r l_reg_t2_mask(.MCLK(MCLK), .en(reg_sel4_wr), .rst(reset0), .inp(data_latch[5]), .val(reg_t2_mask)); 189 | wire reg_t1_start; 190 | ym_slatch_r l_reg_t1_start(.MCLK(MCLK), .en(reg_sel4_wr), .rst(reset0), .inp(data_latch[0]), .val(reg_t1_start)); 191 | wire reg_t2_start; 192 | ym_slatch_r l_reg_t2_start(.MCLK(MCLK), .en(reg_sel4_wr), .rst(reset0), .inp(data_latch[1]), .val(reg_t2_start)); 193 | 194 | wire fsm_out[17]; 195 | 196 | wire ga = data_latch[7:5] != 3'h0; 197 | 198 | wire [8:0] ra_address_latch; 199 | ym_slatch_r #(.DATA_WIDTH(9)) l_ra_address_latch(.MCLK(MCLK), .en(write0 & ga), .rst(reset1), .inp({bank_masked, data_latch}), .val(ra_address_latch)); 200 | 201 | wire ra_address_good; 202 | ym_slatch_r l_ra_address_good(.MCLK(MCLK), .en(write0), .rst(reset1), .inp(ga), .val(ra_address_good)); 203 | 204 | wire [7:0] ra_data_latch; 205 | ym_slatch_r #(.DATA_WIDTH(8)) l_ra_data_latch(.MCLK(MCLK), .en(write1 & ra_address_good), .rst(reset1), .inp(data_latch), .val(ra_data_latch)); 206 | 207 | wire ra_write0 = ga & write0 & reg_test1[4]; 208 | wire ra_write_comb = write1 | ra_write0; 209 | 210 | wire ra_write_comb_ed1; 211 | ym_edge_detect l_ra_write_comb_ed1(.MCLK(MCLK), .c1(aclk1), .inp(ra_write_comb), .val(ra_write_comb_ed1)); 212 | 213 | 214 | wire ra_write = ra_write_comb_ed1 | (reset1 & clk2); 215 | 216 | wire ra_write_comb_ed2; 217 | ym_edge_detect l_ra_write_comb_ed2(.MCLK(MCLK), .c1(clk1), .inp(ra_write_comb), .val(ra_write_comb_ed2)); 218 | 219 | wire ra_write_a = ra_write_comb_ed2; 220 | 221 | wire ra_rst_l; 222 | ym_sr_bit l_ra_rst_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(reset1), .val(ra_rst_l)); 223 | 224 | wire [2:0] ra_cnt1; 225 | wire [1:0] ra_cnt2; 226 | wire ra_cnt3; 227 | wire [1:0] ra_cnt4; 228 | 229 | wire ra_cnt_rst = (reset1 & ~ra_rst_l) | fsm_out[5]; 230 | 231 | wire ra_cnt_of1 = ra_cnt1[2] & ra_cnt1[0]; 232 | wire ra_cnt_of2 = ra_cnt2[1] & ra_cnt_of1; 233 | wire ra_cnt_of4 = ra_cnt4[1]; 234 | 235 | ym_cnt_bit #(.DATA_WIDTH(3)) l_ra_cnt1(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(1'h1), .rst(ra_cnt_rst | ra_cnt_of1), .val(ra_cnt1)); 236 | ym_cnt_bit #(.DATA_WIDTH(2)) l_ra_cnt2(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(ra_cnt_of1), .rst(ra_cnt_rst | ra_cnt_of2), .val(ra_cnt2)); 237 | ym_cnt_bit l_ra_cnt3(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(ra_cnt_of2), .rst(ra_cnt_rst), .val(ra_cnt3)); 238 | ym_cnt_bit #(.DATA_WIDTH(2)) l_ra_cnt4(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(1'h1), .rst(ra_cnt_rst | ra_cnt_of4 | ra_cnt_of1), .val(ra_cnt4)); 239 | 240 | wire [5:0] ra_cnt = { ra_cnt3, ra_cnt2, ra_cnt1 }; 241 | 242 | function [4:0] ch_map; 243 | input [4:0] index; 244 | begin 245 | case (index) 246 | 5'h0: ch_map = 5'h0; 247 | 5'h1: ch_map = 5'h1; 248 | 5'h2: ch_map = 5'h2; 249 | 250 | 5'h4: ch_map = 5'h3; 251 | 5'h5: ch_map = 5'h4; 252 | 5'h6: ch_map = 5'h5; 253 | 254 | 5'h8: ch_map = 5'h6; 255 | 5'h9: ch_map = 5'h7; 256 | 5'ha: ch_map = 5'h8; 257 | 258 | 5'h10: ch_map = 5'h9; 259 | 5'h11: ch_map = 5'ha; 260 | 5'h12: ch_map = 5'hb; 261 | 262 | 5'h14: ch_map = 5'hc; 263 | 5'h15: ch_map = 5'hd; 264 | 5'h16: ch_map = 5'he; 265 | 266 | 5'h18: ch_map = 5'hf; 267 | 5'h19: ch_map = 5'h10; 268 | 5'h1a: ch_map = 5'h11; 269 | 270 | default: ch_map = 5'h1f; 271 | endcase 272 | end 273 | endfunction 274 | 275 | function [5:0] op_map; 276 | input [5:0] index; 277 | begin 278 | case (index) 279 | 6'h0: op_map = 6'h0; 280 | 6'h1: op_map = 6'h1; 281 | 6'h2: op_map = 6'h2; 282 | 6'h3: op_map = 6'h3; 283 | 6'h4: op_map = 6'h4; 284 | 6'h5: op_map = 6'h5; 285 | 286 | 6'h8: op_map = 6'h6; 287 | 6'h9: op_map = 6'h7; 288 | 6'ha: op_map = 6'h8; 289 | 6'hb: op_map = 6'h9; 290 | 6'hc: op_map = 6'ha; 291 | 6'hd: op_map = 6'hb; 292 | 293 | 6'h10: op_map = 6'hc; 294 | 6'h11: op_map = 6'hd; 295 | 6'h12: op_map = 6'he; 296 | 6'h13: op_map = 6'hf; 297 | 6'h14: op_map = 6'h10; 298 | 6'h15: op_map = 6'h11; 299 | 300 | 6'h20: op_map = 6'h12; 301 | 6'h21: op_map = 6'h13; 302 | 6'h22: op_map = 6'h14; 303 | 6'h23: op_map = 6'h15; 304 | 6'h24: op_map = 6'h16; 305 | 6'h25: op_map = 6'h17; 306 | 307 | 6'h28: op_map = 6'h18; 308 | 6'h29: op_map = 6'h19; 309 | 6'h2a: op_map = 6'h1a; 310 | 6'h2b: op_map = 6'h1b; 311 | 6'h2c: op_map = 6'h1c; 312 | 6'h2d: op_map = 6'h1d; 313 | 314 | 6'h30: op_map = 6'h1e; 315 | 6'h31: op_map = 6'h1f; 316 | 6'h32: op_map = 6'h20; 317 | 6'h33: op_map = 6'h21; 318 | 6'h34: op_map = 6'h22; 319 | 6'h35: op_map = 6'h23; 320 | 321 | default: op_map = 6'h3f; 322 | endcase 323 | end 324 | endfunction 325 | 326 | wire [5:0] op_address = ra_write_a ? { ra_address_latch[8], ra_address_latch[4:0] } : ra_cnt; 327 | wire [5:0] op_idx = op_map(op_address); 328 | 329 | wire [3:0] ch_address_write = ra_address_latch[3:0]; 330 | 331 | wire [1:0] ch_address_add; 332 | 333 | assign ch_address_add[0] = ch_address_write == 4'h3 | ch_address_write == 4'h4 | ch_address_write == 4'h5; 334 | assign ch_address_add[1] = ch_address_write == 4'h6 | ch_address_write == 4'h7 | ch_address_write == 4'h8; 335 | 336 | wire [1:0] ch_address_sum1 = { 1'h0, ch_address_write[0] } + { 1'h0, ch_address_add[0] }; 337 | wire [2:0] ch_address_sum2 = ch_address_write[3:1] + { 2'h0, ch_address_sum1[1] | ch_address_add[1] }; 338 | 339 | wire [4:0] ch_address_mapped = { ra_address_latch[8], ch_address_sum2, ch_address_sum1[0] }; 340 | wire [4:0] ch_address_mapped2; 341 | 342 | assign ch_address_mapped2[1:0] = ch_address_mapped[1:0]; 343 | assign ch_address_mapped2[2] = ch_address_mapped[3:2] == 2'h2; 344 | assign ch_address_mapped2[3] = ch_address_mapped[3:2] == 2'h0; 345 | assign ch_address_mapped2[4] = ch_address_mapped[4:2] == 3'h0 | ch_address_mapped[4:2] == 3'h5 | ch_address_mapped[4:2] == 3'h6; 346 | 347 | wire [4:0] ch_address_read = { ra_cnt3, ra_cnt2, ra_cnt4 }; 348 | wire [4:0] ch_address = ra_write_a ? ch_address_mapped : ch_address_read; 349 | 350 | wire [4:0] ch_address_read_4op; 351 | 352 | assign ch_address_read_4op[1:0] = ch_address_read[1:0]; 353 | assign ch_address_read_4op[4:3] = ch_address_read[4:3]; 354 | 355 | assign ch_address_read_4op[2] = ch_address_read[2] & ~(~ra_cnt2[1] & ( 356 | (reg_4op[0] & ra_cnt3 == 1'h0 & ra_cnt4 == 2'h0) | 357 | (reg_4op[1] & ra_cnt3 == 1'h0 & ra_cnt4 == 2'h1) | 358 | (reg_4op[2] & ra_cnt3 == 1'h0 & ra_cnt4 == 2'h2) | 359 | (reg_4op[3] & ra_cnt3 == 1'h1 & ra_cnt4 == 2'h0) | 360 | (reg_4op[4] & ra_cnt3 == 1'h1 & ra_cnt4 == 2'h1) | 361 | (reg_4op[5] & ra_cnt3 == 1'h1 & ra_cnt4 == 2'h2))); 362 | 363 | wire [4:0] ch_address_4op = ra_write_a ? ch_address_mapped : ch_address_read_4op; 364 | wire [4:0] ch_address_fb = ra_write_a ? ch_address_mapped2 : ch_address_read; 365 | 366 | wire [4:0] ch_idx1 = ch_map(ch_address); 367 | wire [4:0] ch_idx2 = ch_map(ch_address_4op); 368 | wire [4:0] ch_idx3 = ch_map(ch_address_fb); 369 | 370 | reg [3:0] ra_multi[36]; 371 | reg ra_ksr[36]; 372 | reg ra_egt[36]; 373 | reg ra_vib[36]; 374 | reg ra_am[36]; 375 | reg [5:0] ra_tl[36]; 376 | reg [1:0] ra_ksl[36]; 377 | reg [3:0] ra_dr[36]; 378 | reg [3:0] ra_ar[36]; 379 | reg [3:0] ra_rr[36]; 380 | reg [3:0] ra_sl[36]; 381 | reg [2:0] ra_wf[36]; 382 | 383 | reg [3:0] ra_multi_o; 384 | reg ra_ksr_o; 385 | reg ra_egt_o; 386 | reg ra_vib_o; 387 | reg ra_am_o; 388 | reg [5:0] ra_tl_o; 389 | reg [1:0] ra_ksl_o; 390 | reg [3:0] ra_dr_o; 391 | reg [3:0] ra_ar_o; 392 | reg [3:0] ra_rr_o; 393 | reg [3:0] ra_sl_o; 394 | reg [2:0] ra_wf_o; 395 | 396 | reg ra_connect[18]; 397 | reg [3:0] ra_pan[18]; 398 | reg [9:0] ra_fnum[18]; 399 | reg [2:0] ra_block[18]; 400 | reg ra_keyon[18]; 401 | reg ra_connect_pair[18]; 402 | reg [2:0] ra_fb[18]; 403 | 404 | reg ra_connect_o; 405 | reg [3:0] ra_pan_o; 406 | reg [9:0] ra_fnum_o; 407 | reg [2:0] ra_block_o; 408 | reg ra_keyon_o; 409 | reg ra_connect_pair_o; 410 | reg [2:0] ra_fb_o; 411 | 412 | always @(posedge MCLK) 413 | begin 414 | if (op_idx < 6'd36) 415 | begin 416 | if (ra_write) 417 | begin 418 | if (ra_address_latch[7:5] == 3'h1 | ra_write0 | reset1) 419 | begin 420 | ra_multi[op_idx] <= ra_data_latch[3:0]; 421 | ra_ksr[op_idx] <= ra_data_latch[4]; 422 | ra_egt[op_idx] <= ra_data_latch[5]; 423 | ra_vib[op_idx] <= ra_data_latch[6]; 424 | ra_am[op_idx] <= ra_data_latch[7]; 425 | end 426 | if (ra_address_latch[7:5] == 3'h2 | ra_write0 | reset1) 427 | begin 428 | ra_tl[op_idx] <= ra_data_latch[5:0]; 429 | ra_ksl[op_idx] <= ra_data_latch[7:6]; 430 | end 431 | if (ra_address_latch[7:5] == 3'h3 | ra_write0 | reset1) 432 | begin 433 | ra_dr[op_idx] <= ra_data_latch[3:0]; 434 | ra_ar[op_idx] <= ra_data_latch[7:4]; 435 | end 436 | if (ra_address_latch[7:5] == 3'h4 | ra_write0 | reset1) 437 | begin 438 | ra_rr[op_idx] <= ra_data_latch[3:0]; 439 | ra_sl[op_idx] <= ra_data_latch[7:4]; 440 | end 441 | if (ra_address_latch[7:5] == 3'h7 | ra_write0 | reset1) 442 | begin 443 | ra_wf[op_idx][1:0] <= ra_data_latch[1:0]; 444 | ra_wf[op_idx][2] <= ra_data_latch[2] & reg_new; 445 | end 446 | end 447 | if (clk1) 448 | begin 449 | ra_multi_o <= ra_multi[op_idx]; 450 | ra_ksr_o <= ra_ksr[op_idx]; 451 | ra_egt_o <= ra_egt[op_idx]; 452 | ra_vib_o <= ra_vib[op_idx]; 453 | ra_am_o <= ra_am[op_idx]; 454 | ra_tl_o <= ra_tl[op_idx]; 455 | ra_ksl_o <= ra_ksl[op_idx]; 456 | ra_dr_o <= ra_dr[op_idx]; 457 | ra_ar_o <= ra_ar[op_idx]; 458 | ra_rr_o <= ra_rr[op_idx]; 459 | ra_sl_o <= ra_sl[op_idx]; 460 | ra_wf_o <= ra_wf[op_idx]; 461 | end 462 | end 463 | if (ch_idx1 < 5'd18) 464 | begin 465 | if (ra_write) 466 | begin 467 | if (ra_address_latch[7:4] == 4'hc | ra_write0 | reset1) 468 | begin 469 | ra_connect[ch_idx1] <= ra_data_latch[0]; 470 | ra_pan[ch_idx1] <= ((~reg_new | reset1) ? 4'h3 : 4'h0) | (reg_new ? ra_data_latch[7:4] : 4'h0); 471 | end 472 | end 473 | if (clk1) 474 | begin 475 | ra_connect_o <= ra_connect[ch_idx1]; 476 | ra_pan_o <= ra_pan[ch_idx1]; 477 | end 478 | end 479 | if (ch_idx2 < 5'd18) 480 | begin 481 | if (ra_write) 482 | begin 483 | if (ra_address_latch[7:4] == 4'ha | ra_write0 | reset1) 484 | begin 485 | ra_fnum[ch_idx2][7:0] <= ra_data_latch; 486 | end 487 | if (ra_address_latch[7:4] == 4'hb | ra_write0 | reset1) 488 | begin 489 | ra_fnum[ch_idx2][9:8] <= ra_data_latch[1:0]; 490 | ra_block[ch_idx2] <= ra_data_latch[4:2]; 491 | ra_keyon[ch_idx2] <= ra_data_latch[5]; 492 | end 493 | end 494 | if (clk1) 495 | begin 496 | ra_fnum_o <= ra_fnum[ch_idx2]; 497 | ra_block_o <= ra_block[ch_idx2]; 498 | ra_keyon_o <= ra_keyon[ch_idx2]; 499 | end 500 | end 501 | if (ch_idx3 < 5'd18) 502 | begin 503 | if (ra_write) 504 | begin 505 | if (ra_address_latch[7:4] == 4'hc | ra_write0 | reset1) 506 | begin 507 | ra_connect_pair[ch_idx3] <= ra_data_latch[0]; 508 | ra_fb[ch_idx3] <= ra_data_latch[3:1]; 509 | end 510 | end 511 | if (clk1) 512 | begin 513 | ra_connect_pair_o <= ra_connect_pair[ch_idx3]; 514 | ra_fb_o <= ra_fb[ch_idx3]; 515 | end 516 | end 517 | end 518 | 519 | wire [3:0] multi; 520 | wire ksr; 521 | wire egt; 522 | wire vib; 523 | wire am; 524 | wire [5:0] tl; 525 | wire [1:0] ksl; 526 | wire [3:0] dr; 527 | wire [3:0] ar; 528 | wire [3:0] rr; 529 | wire [3:0] sl; 530 | wire [2:0] wf; 531 | wire connect; 532 | wire [3:0] pan; 533 | wire [9:0] fnum; 534 | wire [2:0] blk; 535 | wire keyon; 536 | wire connect_pair; 537 | wire [2:0] fb; 538 | 539 | ym_sr_bit_array #(.DATA_WIDTH(4)) l_multi(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_multi_o), .val(multi)); 540 | ym_sr_bit l_ksr(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_ksr_o), .val(ksr)); 541 | ym_sr_bit l_egt(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_egt_o), .val(egt)); 542 | ym_sr_bit l_vib(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_vib_o), .val(vib)); 543 | ym_sr_bit l_am(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_am_o), .val(am)); 544 | ym_sr_bit_array #(.DATA_WIDTH(6)) l_tl(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_tl_o), .val(tl)); 545 | ym_sr_bit_array #(.DATA_WIDTH(2)) l_ksl(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_ksl_o), .val(ksl)); 546 | ym_sr_bit_array #(.DATA_WIDTH(4)) l_dr(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_dr_o), .val(dr)); 547 | ym_sr_bit_array #(.DATA_WIDTH(4)) l_ar(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_ar_o), .val(ar)); 548 | ym_sr_bit_array #(.DATA_WIDTH(4)) l_rr(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_rr_o), .val(rr)); 549 | ym_sr_bit_array #(.DATA_WIDTH(4)) l_sl(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_sl_o), .val(sl)); 550 | ym_sr_bit_array #(.DATA_WIDTH(3)) l_wf(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_wf_o), .val(wf)); 551 | ym_sr_bit l_connect(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_connect_o), .val(connect)); 552 | ym_sr_bit_array #(.DATA_WIDTH(4)) l_pan(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_pan_o), .val(pan)); 553 | ym_sr_bit_array #(.DATA_WIDTH(10)) l_fnum(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_fnum_o), .val(fnum)); 554 | ym_sr_bit_array #(.DATA_WIDTH(3)) l_block(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_block_o), .val(blk)); 555 | ym_sr_bit l_keyon(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_keyon_o), .val(keyon)); 556 | ym_sr_bit l_connect_pair(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_connect_pair_o), .val(connect_pair)); 557 | ym_sr_bit_array #(.DATA_WIDTH(3)) l_fb(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(ra_fb_o), .val(fb)); 558 | 559 | 560 | wire connect_l; 561 | wire connect_pair_l; 562 | wire [2:0] fb_l; 563 | wire [3:0] pan_l; 564 | ym_sr_bit #(.SR_LENGTH(2)) l_connect_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(connect), .val(connect_l)); 565 | ym_sr_bit #(.SR_LENGTH(2)) l_connect_pair_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(connect_pair), .val(connect_pair_l)); 566 | ym_sr_bit_array #(.DATA_WIDTH(3), .SR_LENGTH(2)) l_fb_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(fb), .val(fb_l)); 567 | ym_sr_bit_array #(.DATA_WIDTH(4), .SR_LENGTH(2)) l_pan_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(pan), .val(pan_l)); 568 | 569 | 570 | 571 | wire [2:0] fsm_cnt1; 572 | wire [1:0] fsm_cnt2; 573 | wire fsm_cnt3; 574 | 575 | wire fsm_reset_l; 576 | ym_sr_bit #(.SR_LENGTH(2)) l_fsm_reset_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(reset1), .val(fsm_reset_l)); 577 | 578 | wire fsm_reset = ~fsm_reset_l & reset1; 579 | 580 | wire fsm_of1 = fsm_cnt1[2] & fsm_cnt1[0]; 581 | wire fsm_of2 = fsm_cnt2[1] & fsm_of1; 582 | 583 | ym_cnt_bit #(.DATA_WIDTH(3)) l_fsm_cnt1(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(1'h1), .rst(fsm_reset | fsm_of1), .val(fsm_cnt1)); 584 | ym_cnt_bit #(.DATA_WIDTH(2)) l_fsm_cnt2(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(fsm_of1), .rst(fsm_reset | fsm_of2), .val(fsm_cnt2)); 585 | ym_cnt_bit l_fsm_cnt3(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(fsm_of2), .rst(fsm_reset), .val(fsm_cnt3)); 586 | 587 | wire [5:0] fsm_cnt = { fsm_cnt3, fsm_cnt2, fsm_cnt1 }; 588 | 589 | wire fsm_4op = 590 | (fsm_cnt == 6'd5 & reg_4op[0]) | 591 | (fsm_cnt == 6'd8 & reg_4op[1]) | 592 | (fsm_cnt == 6'd9 & reg_4op[2]) | 593 | (fsm_cnt == 6'd37 & reg_4op[3]) | 594 | (fsm_cnt == 6'd40 & reg_4op[4]) | 595 | (fsm_cnt == 6'd41 & reg_4op[5]); 596 | 597 | wire fsm_l1; 598 | wire fsm_l2; 599 | wire fsm_l3; 600 | wire fsm_l4; 601 | wire fsm_l5; 602 | wire fsm_l6; 603 | wire fsm_l7; 604 | wire fsm_l8; 605 | wire fsm_l9; 606 | wire fsm_l10; 607 | 608 | wire con_4op = fsm_4op & fsm_l10; 609 | 610 | ym_sr_bit l_fsm_l1(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(fsm_cnt == 6'd53), .val(fsm_l1)); 611 | ym_sr_bit l_fsm_l2(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(fsm_cnt == 6'd16), .val(fsm_l2)); 612 | ym_sr_bit l_fsm_l3(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(fsm_cnt == 6'd20), .val(fsm_l3)); 613 | ym_sr_bit l_fsm_l4(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(fsm_cnt == 6'd52), .val(fsm_l4)); 614 | ym_sr_bit #(.SR_LENGTH(3)) l_fsm_l5(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp((fsm_cnt & 6'd56) == 6'd0), .val(fsm_l5)); 615 | ym_sr_bit #(.SR_LENGTH(2)) l_fsm_l6(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp((fsm_cnt & 6'd56) == 6'd8 | (fsm_cnt & 6'd62) == 6'd16), .val(fsm_l6)); 616 | ym_sr_bit #(.SR_LENGTH(2)) l_fsm_l7(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp((fsm_cnt & 6'd56) == 6'd40 | (fsm_cnt & 6'd62) == 6'd48), .val(fsm_l7)); 617 | ym_sr_bit #(.SR_LENGTH(2)) l_fsm_l8(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp((fsm_cnt & 6'd48) == 6'd16), .val(fsm_l8)); 618 | ym_sr_bit #(.SR_LENGTH(3)) l_fsm_l9(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(con_4op), .val(fsm_l9)); 619 | ym_sr_bit #(.SR_LENGTH(3)) l_fsm_l10(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(~connect_l & connect_pair_l), .val(fsm_l10)); 620 | 621 | assign fsm_out[0] = fsm_l1; 622 | assign fsm_out[1] = fsm_cnt == 6'd16; 623 | assign fsm_out[2] = fsm_l2; 624 | assign fsm_out[3] = fsm_cnt == 6'd20; 625 | assign fsm_out[4] = fsm_l3; 626 | assign fsm_out[5] = fsm_cnt == 6'd52; 627 | assign fsm_out[6] = fsm_l4; 628 | assign fsm_out[7] = fsm_l5 | ((fsm_cnt & 6'd56) == 6'd0); 629 | assign fsm_out[8] = (fsm_cnt & 6'd32) == 6'd0; 630 | assign fsm_out[9] = fsm_l6; 631 | assign fsm_out[10] = fsm_l7; 632 | assign fsm_out[11] = rhythm & fsm_l8; 633 | 634 | wire fsm_mc = ~((fsm_cnt & 6'd5) == 6'd4 | (fsm_cnt & 6'd2) != 6'd0); 635 | wire fsm_mc_4op = fsm_mc & ~fsm_4op; 636 | wire rhy_19_20 = rhythm & (fsm_cnt == 6'd19 | fsm_cnt == 6'd20); 637 | 638 | assign fsm_out[12] = fsm_mc_4op & ~(rhythm & (fsm_cnt == 6'd16 | fsm_cnt == 6'd17)); 639 | assign fsm_out[14] = con_4op | (~fsm_4op & ~fsm_l9 & connect_l); 640 | assign fsm_out[13] = ~(rhythm & fsm_cnt == 6'd18) & (fsm_mc_4op | rhy_19_20 | fsm_out[14]); 641 | assign fsm_out[15] = ~fsm_mc & ~rhy_19_20; 642 | assign fsm_out[16] = ~fsm_mc_4op & ~rhy_19_20; 643 | 644 | wire [9:0] lfo_cnt; 645 | wire lfo_reset = reg_test0[1] | reset1; 646 | 647 | wire lfo_cnt_c1; 648 | wire lfo_cnt_c2; 649 | wire lfo_cnt_c3; 650 | wire lfo_cnt_c4; 651 | 652 | ym_cnt_bit #(.DATA_WIDTH(2)) l_lfo_cnt1(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(fsm_out[6]), .rst(lfo_reset), .val(lfo_cnt[1:0]), .c_out(lfo_cnt_c1)); 653 | ym_cnt_bit #(.DATA_WIDTH(2)) l_lfo_cnt2(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(lfo_cnt_c1), .rst(lfo_reset), .val(lfo_cnt[3:2]), .c_out(lfo_cnt_c2)); 654 | ym_cnt_bit #(.DATA_WIDTH(2)) l_lfo_cnt3(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(lfo_cnt_c2), .rst(lfo_reset), .val(lfo_cnt[5:4]), .c_out(lfo_cnt_c3)); 655 | ym_cnt_bit #(.DATA_WIDTH(4)) l_lfo_cnt4(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(lfo_cnt_c3), .rst(lfo_reset), .val(lfo_cnt[9:6]), .c_out(lfo_cnt_c4)); 656 | 657 | wire timer_st_load; 658 | ym_edge_detect l_timer_st_load(.MCLK(MCLK), .c1(clk1), .inp(fsm_out[6]), .val(timer_st_load)); 659 | 660 | wire t1_start; 661 | ym_slatch l_t1_start(.MCLK(MCLK), .en(timer_st_load), .inp(reg_t1_start), .val(t1_start)); 662 | wire t2_start; 663 | ym_slatch l_t2_start(.MCLK(MCLK), .en(timer_st_load), .inp(reg_t2_start), .val(t2_start)); 664 | 665 | 666 | wire t1_step = lfo_cnt_c1; 667 | wire t2_step = lfo_cnt_c2; 668 | 669 | wire t1_start_l; 670 | wire t1_start_l2; 671 | wire t1_of; 672 | wire [7:0] t1_cnt; 673 | wire t1_cnt_c; 674 | ym_cnt_bit_load #(.DATA_WIDTH(8)) l_t1_cnt(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in((t1_start_l & t1_step) | reg_test1[3]), .rst(~t1_start_l), 675 | .load(t1_of | (~t1_start_l2 & t1_start_l)), .load_val(reg_timer1), .val(t1_cnt), .c_out(t1_cnt_c)); 676 | ym_sr_bit l_t1_of(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(t1_cnt_c), .val(t1_of)); 677 | ym_sr_bit l_t1_start_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(t1_start), .val(t1_start_l)); 678 | ym_sr_bit l_t1_start_l2(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(t1_start_l), .val(t1_start_l2)); 679 | 680 | wire t2_start_l; 681 | wire t2_start_l2; 682 | wire t2_of; 683 | wire [7:0] t2_cnt; 684 | wire t2_cnt_c; 685 | ym_cnt_bit_load #(.DATA_WIDTH(8)) l_t2_cnt(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in((t2_start_l & t2_step) | reg_test1[3]), .rst(~t2_start_l), 686 | .load(t2_of | (~t2_start_l2 & t2_start_l)), .load_val(reg_timer2), .val(t2_cnt), .c_out(t2_cnt_c)); 687 | ym_sr_bit l_t2_of(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(t2_cnt_c), .val(t2_of)); 688 | ym_sr_bit l_t2_start_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(t2_start), .val(t2_start_l)); 689 | ym_sr_bit l_t2_start_l2(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(t2_start_l), .val(t2_start_l2)); 690 | 691 | wire t1_status; 692 | ym_rs_trig l_t1_status(.MCLK(MCLK), .rst(reg_sel4_rst | reg_t1_mask), .set(t1_of), .q(t1_status)); 693 | wire t2_status; 694 | ym_rs_trig l_t2_status(.MCLK(MCLK), .rst(reg_sel4_rst | reg_t2_mask), .set(t2_of), .q(t2_status)); 695 | 696 | wire rh_sel0 = rhythm & fsm_out[1]; 697 | wire rh_sel1; 698 | wire rh_sel2; 699 | wire rh_sel3; 700 | wire rh_sel4; 701 | wire rh_sel5; 702 | 703 | ym_sr_bit l_rh_sel1(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(rh_sel0), .val(rh_sel1)); 704 | ym_sr_bit l_rh_sel2(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(rh_sel1), .val(rh_sel2)); 705 | ym_sr_bit l_rh_sel3(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(rh_sel2), .val(rh_sel3)); 706 | ym_sr_bit l_rh_sel4(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(rh_sel3), .val(rh_sel4)); 707 | ym_sr_bit l_rh_sel5(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(rh_sel4), .val(rh_sel5)); 708 | 709 | wire keyon_comb = keyon | 710 | (rh_sel0 & reg_rh_kon[4]) | 711 | (rh_sel1 & reg_rh_kon[0]) | 712 | (rh_sel2 & reg_rh_kon[2]) | 713 | (rh_sel3 & reg_rh_kon[4]) | 714 | (rh_sel4 & reg_rh_kon[3]) | 715 | (rh_sel5 & reg_rh_kon[1]); 716 | 717 | reg [11:0] eg_cells0[18]; 718 | reg [11:0] eg_cells1[18]; 719 | 720 | reg [4:0] eg_index[2]; 721 | wire [4:0] eg_index1 = eg_index[1]; 722 | wire [4:0] eg_index2 = eg_index1 == 5'd0 ? 5'd17 : (eg_index1 - 5'd1); 723 | 724 | wire [11:0] eg_cells_i; 725 | reg [1:0] eg_state_o[4]; 726 | reg [8:0] eg_level_o[4]; 727 | reg eg_timer_o[4]; 728 | 729 | always @(posedge MCLK) 730 | begin 731 | if (clk1) 732 | begin 733 | if (fsm_out[4] | fsm_out[6]) 734 | eg_index[0] <= 5'h0; 735 | else if (eg_index[1] == 5'h1f) 736 | eg_index[0] <= 5'h1f; 737 | else 738 | eg_index[0] <= eg_index[1] + 5'h1; 739 | 740 | if (eg_index[1] < 5'd18) 741 | begin 742 | eg_cells0[eg_index2] <= eg_cells_i; 743 | eg_cells1[eg_index2] <= eg_cells0[eg_index1]; 744 | eg_state_o[0] <= eg_cells1[eg_index1][1:0]; 745 | eg_level_o[0] <= eg_cells1[eg_index1][10:2]; 746 | eg_timer_o[0] <= eg_cells1[eg_index1][11]; 747 | end 748 | eg_state_o[2] <= eg_state_o[1]; 749 | eg_level_o[2] <= eg_level_o[1]; 750 | eg_timer_o[2] <= eg_timer_o[1]; 751 | end 752 | if (clk2) 753 | begin 754 | eg_index[1] <= eg_index[0]; 755 | eg_state_o[1] <= eg_state_o[0]; 756 | eg_state_o[3] <= eg_state_o[2]; 757 | eg_level_o[1] <= eg_level_o[0]; 758 | eg_level_o[3] <= eg_level_o[2]; 759 | eg_timer_o[1] <= eg_timer_o[0]; 760 | eg_timer_o[3] <= eg_timer_o[2]; 761 | end 762 | end 763 | 764 | wire trem_load; 765 | ym_edge_detect l_trem_load(.MCLK(MCLK), .c1(clk1), .inp(fsm_out[0]), .val(trem_load)); 766 | wire trem_st_load; 767 | ym_edge_detect l_trem_st_load(.MCLK(MCLK), .c1(clk1), .inp(fsm_out[6]), .val(trem_st_load)); 768 | 769 | wire am_step = lfo_cnt_c3; 770 | wire trem_step; 771 | ym_slatch l_trem_step(.MCLK(MCLK), .en(trem_st_load), .inp(am_step), .val(trem_step)); 772 | 773 | wire [8:0] trem_value; 774 | wire trem_value_bit; 775 | ym_sr_bit_array #(.DATA_WIDTH(9)) l_trem_value(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp({ trem_value_bit, trem_value[8:1]}), .val(trem_value)); 776 | 777 | wire [6:0] trem_out; 778 | ym_slatch #(.DATA_WIDTH(7)) l_trem_out(.MCLK(MCLK), .en(trem_load), .inp(trem_value[6:0]), .val(trem_out)); 779 | 780 | wire trem_bit = trem_value[0]; 781 | wire trem_reset = reset1 | reg_test0[1]; 782 | 783 | wire trem_dir; 784 | wire trem_carry; 785 | 786 | wire trem_step_add = ((trem_step | reg_test0[4]) & (fsm_out[0] | trem_dir)) & fsm_out[7]; 787 | wire trem_carry_add = fsm_out[7] & trem_carry; 788 | 789 | wire [1:0] trem_sum = { 1'h0, trem_bit } + { 1'h0, trem_step_add } + { 1'h0, trem_carry_add }; 790 | 791 | assign trem_value_bit = ~trem_reset & trem_sum[0]; 792 | 793 | ym_sr_bit l_trem_carry(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(trem_sum[1]), .val(trem_carry)); 794 | 795 | wire trem_of = trem_out == 7'd0 | (trem_out & 7'd105) == 7'd105; 796 | wire trem_of_l; 797 | ym_sr_bit l_trem_of_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(trem_of), .val(trem_of_l)); 798 | 799 | ym_sr_bit l_trem_dir(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(trem_reset ? 1'h0 : (trem_dir ^ (trem_of & ~trem_of_l))), .val(trem_dir)); 800 | 801 | wire eg_carry; 802 | wire eg_subcnt; 803 | wire eg_sync_l; 804 | 805 | wire eg_timer_bit = eg_timer_o[3]; 806 | wire eg_timer_carry = eg_carry | (eg_subcnt & eg_sync_l); 807 | wire [1:0] eg_timer_sum = { 1'h0, eg_timer_bit } + { 1'h0, eg_timer_carry }; 808 | wire eg_timer_rst = reset1 | reg_test1[3]; 809 | 810 | wire eg_timer_bit2 = eg_timer_sum[0] & ~eg_timer_rst; 811 | 812 | assign eg_cells_i[11] = eg_timer_bit2; 813 | 814 | ym_sr_bit l_eg_carry(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(eg_timer_sum[1]), .val(eg_carry)); 815 | ym_sr_bit l_eg_sync_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(fsm_out[6]), .val(eg_sync_l)); 816 | 817 | wire eg_mask; 818 | ym_sr_bit l_eg_mask(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp((eg_mask | eg_timer_bit2) & ~(eg_timer_rst | fsm_out[6])), .val(eg_mask)); 819 | 820 | wire eg_timer_dbg; 821 | wire [35:0] eg_timer_masked; 822 | ym_sr_bit_array #(.DATA_WIDTH(36)) l_eg_timer_masked(.MCLK(MCLK), .c1(clk1), .c2(clk2), 823 | .inp( { (~eg_mask & eg_timer_bit2) | (~eg_timer_dbg & reg_test0[6]), eg_timer_masked[35:1] } ), .val(eg_timer_masked)); 824 | 825 | ym_sr_bit l_eg_timer_dbg(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(reg_test0[6]), .val(eg_timer_dbg)); 826 | 827 | ym_cnt_bit l_eg_subcnt(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(fsm_out[6]), .rst(reset1), .val(eg_subcnt)); 828 | 829 | wire eg_load_l1; 830 | ym_sr_bit l_eg_load_l1(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(eg_subcnt & fsm_out[6]), .val(eg_load_l1)); 831 | 832 | wire eg_load; 833 | ym_edge_detect l_eg_load(.MCLK(MCLK), .c1(clk1), .inp(eg_load_l1), .val(eg_load)); 834 | 835 | wire [1:0] eg_timer_low; 836 | ym_slatch_r #(.DATA_WIDTH(2)) l_eg_timer_low(.MCLK(MCLK), .en(eg_load), .inp({ eg_timer_o[1], eg_timer_o[3] }), .rst(reset1), .val(eg_timer_low)); 837 | wire [3:0] eg_shift; 838 | wire [3:0] eg_shift_i; 839 | assign eg_shift_i[0] = (eg_timer_masked & 36'h1555) != 36'h0; 840 | assign eg_shift_i[1] = (eg_timer_masked & 36'h666) != 36'h0; 841 | assign eg_shift_i[2] = (eg_timer_masked & 36'h1878) != 36'h0; 842 | assign eg_shift_i[3] = (eg_timer_masked & 36'h1f80) != 36'h0; 843 | ym_slatch_r #(.DATA_WIDTH(4)) l_eg_shift(.MCLK(MCLK), .en(eg_load), .inp(eg_shift_i), .rst(reset1), .val(eg_shift)); 844 | 845 | 846 | wire eg_rst = reset1 | reg_test1[5]; 847 | 848 | wire [1:0] state = eg_state_o[3]; 849 | wire dokon = state == 2'h3 & keyon_comb; 850 | wire [1:0] rate_sel = dokon ? 2'h0 : state; 851 | 852 | wire [3:0] rate = (rate_sel == 2'h0 ? ar : 4'h0) | 853 | (rate_sel == 2'h1 ? dr : 4'h0) | 854 | ((rate_sel == 2'h3 | (rate_sel == 2'h2 & ~egt)) ? rr : 4'h0); 855 | 856 | wire [4:0] sl2 = { sl == 4'hf, sl }; 857 | 858 | wire ns = reg_notesel ? fnum[8] : fnum[9]; 859 | 860 | wire [3:0] ksrv = ksr ? { blk, ns } : { 2'h0, blk[2:1] }; 861 | 862 | wire [4:0] rate_sum = { 1'h0, rate } + { 3'h0, ksrv[3:2] }; 863 | 864 | wire [3:0] rate_hi = rate_sum[4] ? 4'hf : rate_sum[3:0]; 865 | 866 | wire rate12 = rate_hi == 4'hc; 867 | wire rate13 = rate_hi == 4'hd; 868 | wire rate14 = rate_hi == 4'he; 869 | wire rate15 = rate_hi == 4'hf; 870 | 871 | wire [3:0] shift_sum = rate_hi + eg_shift; 872 | 873 | wire rate_ls12 = rate_hi[3:2] != 2'h3; 874 | wire rate_nz = rate != 4'h0; 875 | 876 | wire inclow = rate_ls12 & rate_nz & eg_subcnt & shift_sum[3:2] == 2'h3 & 877 | (shift_sum[1:0] == 2'h0 | (shift_sum[1:0] == 2'h1 & ksrv[1]) | (shift_sum[1:0] == 2'h2 & ksrv[0])); 878 | 879 | wire stephi = (eg_timer_low == 2'h1 & ksrv[1:0] == 2'h3) | 880 | (eg_timer_low == 2'h0 & ksrv[0]) | 881 | (~eg_timer_low[0] & ksrv[1]); 882 | 883 | wire step1 = (rate12 & (stephi | eg_subcnt)) | (rate13 & ~stephi) | inclow; 884 | wire step2 = (rate13 & stephi) | (rate14 & ~stephi); 885 | wire step3 = (rate14 & stephi) | rate15; 886 | 887 | wire [8:0] level = eg_level_o[3]; 888 | wire slreach = level[8:4] == sl2; 889 | wire zeroreach = level == 9'h0; 890 | wire silent = level[8:3] == 6'h3f; 891 | 892 | wire [1:0] nextstate; 893 | assign eg_cells_i[1:0] = nextstate; 894 | 895 | assign nextstate = (eg_rst ? 2'h3 : 2'h0) | 896 | ((~dokon & ~keyon_comb) ? 2'h3 : 2'h0) | 897 | ((~dokon & state == 2'h0 & zeroreach) ? 2'h1 : 2'h0) | 898 | ((~dokon & state == 2'h1 & ~slreach) ? 2'h1 : 2'h0) | 899 | ((~dokon & state == 2'h1 & slreach) ? 2'h2 : 2'h0) | 900 | ((~dokon & state == 2'h2) ? 2'h2 : 2'h0) | 901 | ((~dokon & state == 2'h3) ? 2'h3 : 2'h0); 902 | 903 | wire linear = ~dokon & ~silent & (state[1] | (state == 2'h1 & ~slreach)); 904 | wire exponent = state == 2'h0 & keyon_comb & ~rate15 & ~zeroreach; 905 | wire instantattack = (dokon & rate15) | reg_test0[4]; 906 | wire mute = eg_rst | (state != 2'h0 & silent & ~dokon & ~reg_test0[4]); 907 | 908 | wire [8:0] level2 = mute ? 9'h1ff : (instantattack ? 9'h0 : level); 909 | 910 | wire [7:0] eg_add = (exponent ? ~level[8:1] : 8'h0) | 911 | (linear ? 8'h4 : 8'h0); 912 | 913 | wire [8:0] eg_addshift = ((exponent & (step1 | step2 | step3)) ? 9'h100 : 9'h0) | 914 | (step1 ? { 1'h0, exponent, exponent, eg_add[7:3], eg_add[2] | linear } : 9'h0) | 915 | (step2 ? { 1'h0, exponent, eg_add[7:3], eg_add[2] | linear, eg_add[1] } : 9'h0) | 916 | (step3 ? { 1'h0, eg_add[7:3], eg_add[2] | linear, eg_add[1:0] } : 9'h0); 917 | 918 | wire [8:0] levelnext = level2 + eg_addshift; 919 | assign eg_cells_i[10:2] = levelnext; 920 | 921 | reg [6:0] ksltable; 922 | 923 | always @(*) 924 | begin 925 | case (fnum[9:6]) 926 | 4'h0: ksltable <= 7'd0; 927 | 4'h1: ksltable <= 7'd32; 928 | 4'h2: ksltable <= 7'd40; 929 | 4'h3: ksltable <= 7'd45; 930 | 4'h4: ksltable <= 7'd48; 931 | 4'h5: ksltable <= 7'd51; 932 | 4'h6: ksltable <= 7'd53; 933 | 4'h7: ksltable <= 7'd55; 934 | 4'h8: ksltable <= 7'd56; 935 | 4'h9: ksltable <= 7'd58; 936 | 4'ha: ksltable <= 7'd59; 937 | 4'hb: ksltable <= 7'd60; 938 | 4'hc: ksltable <= 7'd61; 939 | 4'hd: ksltable <= 7'd62; 940 | 4'he: ksltable <= 7'd63; 941 | 4'hf: ksltable <= 7'd64; 942 | endcase 943 | end 944 | 945 | wire [6:0] ksl_sum = { 1'h0, ksltable[5:0] } + { 1'h0, blk, 3'h0 }; 946 | wire [5:0] ksl_clamp = (ksltable[6] | ksl_sum[6]) ? ksl_sum[5:0] : 6'h0; 947 | 948 | wire [7:0] ksl_shift = ((ksl == 2'h1) ? { 1'h0, ksl_clamp, 1'h0 } : 8'h0) | 949 | ((ksl == 2'h2) ? { 2'h0, ksl_clamp } : 8'h0) | 950 | ((ksl == 2'h3) ? { ksl_clamp, 2'h0 } : 8'h0); 951 | 952 | wire [8:0] ksltl = {1'h0, ksl_shift } + {1'h0, tl, 2'h0}; 953 | 954 | wire [4:0] tremolo = ((reg_da & am) ? trem_out[6:2] : 5'h0) | 955 | ((~reg_da & am) ? { 2'h0, trem_out[6:4] } : 5'h0); 956 | 957 | wire [9:0] ksltltrem = { 1'h0, ksltl } + { 5'h0, tremolo }; 958 | 959 | wire [9:0] totallevel = { 1'h0, ksltltrem[8:0] } + { 1'h0, level }; 960 | 961 | wire [8:0] totallevelclamp = reg_test0[0] ? 9'h0 : ((ksltltrem[9] | totallevel[9]) ? 9'h1ff : totallevel[8:0]); 962 | 963 | wire [8:0] eg_out; 964 | ym_sr_bit_array #(.DATA_WIDTH(9)) l_eg_out(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(totallevelclamp), .val(eg_out)); 965 | 966 | wire eg_dbg_load_l; 967 | ym_sr_bit l_eg_dbg_load_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(reg_test0[5]), .val(eg_dbg_load_l)); 968 | wire eg_dbg; 969 | ym_dbg_read #(.DATA_WIDTH(9)) l_eg_ebg(.MCLK(MCLK), .c1(clk1), .c2(clk2), .prev(1'h0), .load(reg_test0[5] & ~eg_dbg_load_l), .load_val(eg_out), 970 | .next(eg_dbg)); 971 | 972 | 973 | reg [18:0] pg_cells0[18]; 974 | reg [18:0] pg_cells1[18]; 975 | 976 | reg [4:0] pg_index[2]; 977 | wire [4:0] pg_index1 = pg_index[1]; 978 | wire [4:0] pg_index2 = pg_index1 == 5'd0 ? 5'd17 : (pg_index1 - 5'd1); 979 | 980 | wire [18:0] pg_cells_i; 981 | reg [18:0] pg_phase_o[4]; 982 | 983 | always @(posedge MCLK) 984 | begin 985 | if (clk1) 986 | begin 987 | if (fsm_out[4] | fsm_out[6]) 988 | pg_index[0] <= 5'h0; 989 | else if (pg_index[1] == 5'h1f) 990 | pg_index[0] <= 5'h1f; 991 | else 992 | pg_index[0] <= pg_index[1] + 5'h1; 993 | 994 | if (pg_index[1] < 5'd18) 995 | begin 996 | pg_cells0[pg_index2] <= pg_cells_i; 997 | pg_cells1[pg_index2] <= pg_cells0[pg_index1]; 998 | pg_phase_o[0] <= pg_cells1[pg_index1]; 999 | end 1000 | pg_phase_o[2] <= pg_phase_o[1]; 1001 | end 1002 | if (clk2) 1003 | begin 1004 | pg_index[1] <= pg_index[0]; 1005 | pg_phase_o[1] <= pg_phase_o[0]; 1006 | pg_phase_o[3] <= pg_phase_o[2]; 1007 | end 1008 | end 1009 | 1010 | 1011 | 1012 | wire vib_step = lfo_cnt_c4 | (reg_test0[4] & fsm_out[6]); 1013 | wire [2:0] vib_cnt; 1014 | ym_cnt_bit #(.DATA_WIDTH(3)) l_vib_cnt(.MCLK(MCLK), .c1(clk1), .c2(clk2), .c_in(vib_step), .rst(lfo_reset), .val(vib_cnt)); 1015 | 1016 | wire vib_sel1 = vib_cnt[1:0] == 2'h2; 1017 | wire vib_sel2 = vib_cnt[0]; 1018 | wire vib_sh0 = reg_dv & vib & vib_sel1; 1019 | wire vib_sh1 = (reg_dv & vib & vib_sel2) | (~reg_dv & vib & vib_sel1); 1020 | wire vib_sh2 = ~reg_dv & vib & vib_sel2; 1021 | wire vib_sign = vib_cnt[2] & vib; 1022 | 1023 | wire [2:0] vib_add = (vib_sh0 ? fnum[9:7] : 3'h0) | (vib_sh1 ? { 1'h0, fnum[9:8] } : 3'h0) | (vib_sh2 ? { 2'h0, fnum[9] } : 3'h0); 1024 | 1025 | wire [10:0] fnum_vib1; 1026 | 1027 | assign fnum_vib1 = { 1'h0, fnum } + { 1'h0, {7{vib_sign}}, vib_sign ? ~vib_add : vib_add } + { 9'h0, vib_sign }; 1028 | 1029 | wire [10:0] fnum_vib; 1030 | assign fnum_vib[9:0] = fnum_vib1[9:0]; 1031 | assign fnum_vib[10] = fnum_vib1[10] & ~vib_sign; 1032 | 1033 | wire [13:0] fnum_sh0 = (blk[1:0] == 2'h0 ? { 3'h0, fnum_vib } : 14'h0) | 1034 | (blk[1:0] == 2'h1 ? { 2'h0, fnum_vib, 1'h0 } : 14'h0) | 1035 | (blk[1:0] == 2'h2 ? { 1'h0, fnum_vib, 2'h0 } : 14'h0) | 1036 | (blk[1:0] == 2'h3 ? { fnum_vib, 3'h0 } : 14'h0); 1037 | 1038 | wire [16:0] fnum_blk = blk[2] ? { fnum_sh0, 3'h0 } : { 4'h0, fnum_sh0[13:1] }; 1039 | 1040 | wire multi_sel[13]; 1041 | assign multi_sel[0] = multi == 4'h0; 1042 | assign multi_sel[1] = multi == 4'h1; 1043 | assign multi_sel[2] = multi == 4'h2; 1044 | assign multi_sel[3] = multi == 4'h3; 1045 | assign multi_sel[4] = multi == 4'h4; 1046 | assign multi_sel[5] = multi == 4'h5; 1047 | assign multi_sel[6] = multi == 4'h6; 1048 | assign multi_sel[7] = multi == 4'h7; 1049 | assign multi_sel[8] = multi == 4'h8; 1050 | assign multi_sel[9] = multi == 4'h9; 1051 | assign multi_sel[10] = multi[3:1] == 3'h5; 1052 | assign multi_sel[11] = multi[3:1] == 3'h6; 1053 | assign multi_sel[12] = multi[3:1] == 3'h7; 1054 | 1055 | wire multi_ctrl[8]; 1056 | assign multi_ctrl[0] = multi_sel[11]; // 12, 13 1057 | assign multi_ctrl[1] = multi_sel[1] | multi_sel[5] | multi_sel[9]; // 1, 5, 9 1058 | assign multi_ctrl[2] = multi_sel[2] | multi_sel[6] | multi_sel[10]; // 2, 6, 10, 11 1059 | assign multi_ctrl[3] = multi_sel[3] | multi_sel[7] | multi_sel[12]; // 3, 7, 14, 15 1060 | assign multi_ctrl[4] = multi_sel[0]; // 0 1061 | 1062 | assign multi_ctrl[5] = multi_sel[12]; // 14, 15 1063 | assign multi_ctrl[6] = multi_sel[7] | multi_sel[8] | multi_sel[9] | multi_sel[10] | multi_sel[11]; 1064 | assign multi_ctrl[7] = multi_sel[3] | multi_sel[4] | multi_sel[5] | multi_sel[6]; 1065 | 1066 | wire [16:0] fnum_m1 = multi_ctrl[7] ? fnum_blk : 1067 | (multi_ctrl[6] ? { fnum_blk[15:0], 1'h0 } : 1068 | (multi_ctrl[5] ? { fnum_blk[14:0], 2'h0 } : 17'h0)); 1069 | 1070 | wire [18:0] fnum_m2 = multi_ctrl[4] ? { 3'h0, fnum_blk[16:1] } : 1071 | (multi_ctrl[3] ? { 2'h3, ~fnum_blk } : 1072 | (multi_ctrl[2] ? { 1'h0, fnum_blk, 1'h0 } : 1073 | (multi_ctrl[1] ? { 2'h0, fnum_blk } : 1074 | (multi_ctrl[0] ? { fnum_blk, 2'h0 } : 19'h0)))); 1075 | 1076 | 1077 | wire [18:0] fnum_multi = { fnum_m1, 2'h0 } + fnum_m2 + { 18'h0, multi_ctrl[3] }; 1078 | 1079 | 1080 | wire [18:0] phase = ((dokon | reg_test0[2] | reset1) ? 19'h0 : pg_phase_o[3]) + fnum_multi; 1081 | assign pg_cells_i = phase; 1082 | 1083 | wire [22:0] noise_lfsr; 1084 | wire noise_bit = ~reset1 & ((noise_lfsr[22] ^ noise_lfsr[8]) | reg_test0[1] | noise_lfsr == 23'h0); 1085 | ym_sr_bit_array #(.DATA_WIDTH(23)) l_noise_lfsr(.MCLK(MCLK), .c1(rclk1), .c2(rclk2), .inp({noise_lfsr[21:0], noise_bit}), .val(noise_lfsr)); 1086 | 1087 | wire [9:0] pg_out = pg_phase_o[3][18:9]; 1088 | 1089 | wire hh = fsm_out[2] & rhythm; 1090 | wire sd = fsm_out[3] & rhythm; 1091 | wire tc = fsm_out[4] & rhythm; 1092 | wire rhy = (fsm_out[2] | fsm_out[3] | fsm_out[4]) & rhythm; 1093 | 1094 | wire hh_load; 1095 | ym_edge_detect l_hh_load(.MCLK(MCLK), .c1(clk1), .inp(fsm_out[2]), .val(hh_load)); 1096 | wire hh_bit2, hh_bit3, hh_bit7, hh_bit8; 1097 | ym_slatch l_hh_bit2(.MCLK(MCLK), .en(hh_load), .inp(pg_out[2]), .val(hh_bit2)); 1098 | ym_slatch l_hh_bit3(.MCLK(MCLK), .en(hh_load), .inp(pg_out[3]), .val(hh_bit3)); 1099 | ym_slatch l_hh_bit7(.MCLK(MCLK), .en(hh_load), .inp(pg_out[7]), .val(hh_bit7)); 1100 | ym_slatch l_hh_bit8(.MCLK(MCLK), .en(hh_load), .inp(pg_out[8]), .val(hh_bit8)); 1101 | wire tc_load; 1102 | ym_edge_detect l_tc_load(.MCLK(MCLK), .c1(clk1), .inp(tc), .val(tc_load)); 1103 | wire tc_bit3, tc_bit5; 1104 | ym_slatch l_tc_bit3(.MCLK(MCLK), .en(tc_load), .inp(pg_out[3]), .val(tc_bit3)); 1105 | ym_slatch l_tc_bit5(.MCLK(MCLK), .en(tc_load), .inp(pg_out[5]), .val(tc_bit5)); 1106 | 1107 | wire noise = noise_lfsr[22]; 1108 | 1109 | wire rm_bit = (hh_bit2 ^ hh_bit7) | (tc_bit5 ^ hh_bit3) | (tc_bit5 ^ tc_bit3); 1110 | 1111 | wire hh_xor = noise ^ rm_bit; 1112 | 1113 | wire [9:0] pg_out_rhy = (~rhy ? pg_out : 10'h0) | 1114 | (hh ? { rm_bit, 1'h0, hh_xor, hh_xor, ~hh_xor, hh_xor | ~hh_xor, 1'h0, ~hh_xor, 1'h0, 1'h0 } : 10'h0) | 1115 | (sd ? { hh_bit8, noise ^ hh_bit8, 8'h0 } : 10'h0) | 1116 | (tc ? { rm_bit, 9'h80 } : 10'h0); 1117 | 1118 | wire pg_dbg_load_l; 1119 | ym_sr_bit l_pg_dbg_load_l(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(reg_test0[3]), .val(pg_dbg_load_l)); 1120 | wire pg_dbg; 1121 | ym_dbg_read #(.DATA_WIDTH(19)) l_pg_ebg(.MCLK(MCLK), .c1(clk1), .c2(clk2), .prev(1'h0), .load(reg_test0[3] & ~pg_dbg_load_l), 1122 | .load_val({ pg_out_rhy, pg_phase_o[3][8:0] }), .next(pg_dbg)); 1123 | 1124 | wire [9:0] op_mod; 1125 | wire [9:0] op_phase = pg_out_rhy + op_mod; 1126 | wire sawtooth = wf == 3'h7; 1127 | 1128 | wire [9:0] op_phase2 = (wf == 3'h4 | wf == 3'h5) ? { op_phase[8:0], 1'h0 } : op_phase; 1129 | 1130 | wire [8:0] op_phase3; 1131 | 1132 | assign op_phase3 = (sawtooth ? op_phase2[9] : op_phase2[8]) ? ~op_phase2[8:0] : op_phase2[8:0]; 1133 | 1134 | 1135 | wire wf_mute = (op_phase[9] & (wf == 3'h1 | wf == 3'h4 | wf == 3'h5)) | (op_phase[8] & wf == 3'h3); 1136 | wire wf_sign = (wf == 3'h2 | wf == 3'h3 | wf == 3'h5) ? 1'h0 : op_phase2[9]; 1137 | 1138 | wire op_mute; 1139 | wire op_sign; 1140 | ym_sr_bit #(.SR_LENGTH(2)) l_op_mute(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(wf_mute), .val(op_mute)); 1141 | ym_sr_bit #(.SR_LENGTH(2)) l_op_sign(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(wf_sign), .val(op_sign)); 1142 | 1143 | wire [7:0] sin_index = (wf == 3'h6) ? 8'hff : op_phase3[7:0]; 1144 | 1145 | wire [4:0] sin_lut_index = sin_index[5:1]; 1146 | 1147 | reg [45:0] sine_lut_out; 1148 | 1149 | always @(sin_lut_index) 1150 | begin 1151 | case (sin_lut_index) 1152 | 5'h1f: sine_lut_out = 46'b0001100001000100100001000010101010101000100101; 1153 | 5'h1e: sine_lut_out = 46'b0001100001010100001000000001001001001100010100; 1154 | 5'h1d: sine_lut_out = 46'b0001100001010100001000110000101011001100000110; 1155 | 5'h1c: sine_lut_out = 46'b0001110000010000000000110011001001001100100111; 1156 | 5'h1b: sine_lut_out = 46'b0001110000010000011000000011101010001110010110; 1157 | 5'h1a: sine_lut_out = 46'b0001110000010100010001100000001000101110100111; 1158 | 5'h19: sine_lut_out = 46'b0001110000010100011001100001001011001110100101; 1159 | 5'h18: sine_lut_out = 46'b0001110000011100001001010011101000101111001111; 1160 | 5'h17: sine_lut_out = 46'b0001110001011000000001110010101110001101110111; 1161 | 5'h16: sine_lut_out = 46'b0001110001011000101000111001100101011001101010; 1162 | 5'h15: sine_lut_out = 46'b0001110001011100110000011011100100001010100111; 1163 | 5'h14: sine_lut_out = 46'b0001110001011100111000111110100011001001110111; 1164 | 5'h13: sine_lut_out = 46'b0100100010010000100001011100100000111001111011; 1165 | 5'h12: sine_lut_out = 46'b0100100010010100100001001111000001111110100010; 1166 | 5'h11: sine_lut_out = 46'b0100100010010100101001101111110110100101100100; 1167 | 5'h10: sine_lut_out = 46'b0100100111000000010000011101000110101110010111; 1168 | 5'h0f: sine_lut_out = 46'b0100100111000100010000101110001101001011111110; 1169 | 5'h0e: sine_lut_out = 46'b0100100111001100001011011000001001011000011011; 1170 | 5'h0d: sine_lut_out = 46'b0100110110001000001011101000001010111011111011; 1171 | 5'h0c: sine_lut_out = 46'b0100110110001100010011011010111110110100011000; 1172 | 5'h0b: sine_lut_out = 46'b0100110111001000110010111100101010001100010111; 1173 | 5'h0a: sine_lut_out = 46'b0100110111001100110110110111110001010111110000; 1174 | 5'h09: sine_lut_out = 46'b0111000100000000101111000101010101010101111001; 1175 | 5'h08: sine_lut_out = 46'b0111000100000100101111110111011101010010111011; 1176 | 5'h07: sine_lut_out = 46'b0111000101010101010100101000110000010010010001; 1177 | 5'h06: sine_lut_out = 46'b0111010100011001001100011010011100010000101001; 1178 | 5'h05: sine_lut_out = 46'b0111010101011011001001100100010000110100110010; 1179 | 5'h04: sine_lut_out = 46'b1010000100011011011001011110010001110010101001; 1180 | 5'h03: sine_lut_out = 46'b1010000101011111111100100101011100010010010011; 1181 | 5'h02: sine_lut_out = 46'b1010010111110101100010001011110001010100001010; 1182 | 5'h01: sine_lut_out = 46'b1011010110110011110111011000011100110000011010; 1183 | 5'h00: sine_lut_out = 46'b1110011111010001110111100110011001110101111010; 1184 | endcase 1185 | end 1186 | 1187 | wire sin_index_top_sel[4]; 1188 | assign sin_index_top_sel[0] = sin_index[7:6] == 2'h0; 1189 | assign sin_index_top_sel[1] = sin_index[7:6] == 2'h1; 1190 | assign sin_index_top_sel[2] = sin_index[7:6] == 2'h2; 1191 | assign sin_index_top_sel[3] = sin_index[7:6] == 2'h3; 1192 | 1193 | wire [18:0] sin_lut_mux; 1194 | 1195 | assign sin_lut_mux[0] = (sine_lut_out[0] & sin_index_top_sel[0]) | (sine_lut_out[1] & sin_index_top_sel[1]) 1196 | | (sine_lut_out[2] & sin_index_top_sel[2]) | (sine_lut_out[3] & sin_index_top_sel[3]); 1197 | assign sin_lut_mux[1] = (sine_lut_out[4] & sin_index_top_sel[0]) | (sine_lut_out[5] & sin_index_top_sel[1]) 1198 | | (sine_lut_out[6] & sin_index_top_sel[2]) | (sine_lut_out[7] & sin_index_top_sel[3]); 1199 | assign sin_lut_mux[2] = (sine_lut_out[8] & sin_index_top_sel[0]) | (sine_lut_out[9] & sin_index_top_sel[1]) 1200 | | (sine_lut_out[10] & sin_index_top_sel[2]); 1201 | assign sin_lut_mux[3] = (sine_lut_out[11] & sin_index_top_sel[0]) | (sine_lut_out[12] & sin_index_top_sel[1]) 1202 | | (sine_lut_out[13] & sin_index_top_sel[2]) | (sine_lut_out[14] & sin_index_top_sel[3]); 1203 | assign sin_lut_mux[4] = (sine_lut_out[15] & sin_index_top_sel[0]) | (sine_lut_out[16] & sin_index_top_sel[1]); 1204 | assign sin_lut_mux[5] = (sine_lut_out[17] & sin_index_top_sel[0]) | (sine_lut_out[18] & sin_index_top_sel[1]) 1205 | | (sine_lut_out[19] & sin_index_top_sel[2]) | (sine_lut_out[20] & sin_index_top_sel[3]); 1206 | assign sin_lut_mux[6] = sine_lut_out[21] & sin_index_top_sel[0]; 1207 | assign sin_lut_mux[7] = (sine_lut_out[22] & sin_index_top_sel[0]) | (sine_lut_out[23] & sin_index_top_sel[1]) 1208 | | (sine_lut_out[24] & sin_index_top_sel[2]) | (sine_lut_out[25] & sin_index_top_sel[3]); 1209 | assign sin_lut_mux[8] = sine_lut_out[26] & sin_index_top_sel[0]; 1210 | assign sin_lut_mux[9] = (sine_lut_out[27] & sin_index_top_sel[0]) | (sine_lut_out[28] & sin_index_top_sel[1]) 1211 | | (sine_lut_out[29] & sin_index_top_sel[2]) | (sine_lut_out[30] & sin_index_top_sel[3]); 1212 | assign sin_lut_mux[10] = sine_lut_out[31] & sin_index_top_sel[0]; 1213 | assign sin_lut_mux[11] = (sine_lut_out[32] & sin_index_top_sel[0]) | (sine_lut_out[33] & sin_index_top_sel[1]) 1214 | | (sine_lut_out[34] & sin_index_top_sel[2]); 1215 | assign sin_lut_mux[12] = sine_lut_out[35] & sin_index_top_sel[0]; 1216 | assign sin_lut_mux[13] = (sine_lut_out[36] & sin_index_top_sel[0]) | (sine_lut_out[37] & sin_index_top_sel[1]) 1217 | | (sine_lut_out[38] & sin_index_top_sel[2]); 1218 | assign sin_lut_mux[14] = sine_lut_out[39] & sin_index_top_sel[0]; 1219 | assign sin_lut_mux[15] = (sine_lut_out[40] & sin_index_top_sel[0]) | (sine_lut_out[41] & sin_index_top_sel[1]); 1220 | assign sin_lut_mux[16] = (sine_lut_out[42] & sin_index_top_sel[0]) | (sine_lut_out[43] & sin_index_top_sel[1]); 1221 | assign sin_lut_mux[17] = sine_lut_out[44] & sin_index_top_sel[0]; 1222 | assign sin_lut_mux[18] = sine_lut_out[45] & sin_index_top_sel[0]; 1223 | 1224 | wire [10:0] sin_base = { sin_lut_mux[18:15], sin_lut_mux[13], sin_lut_mux[11], sin_lut_mux[9], sin_lut_mux[7], sin_lut_mux[5], sin_lut_mux[3], sin_lut_mux[1] }; 1225 | 1226 | wire [7:0] sin_delta = sin_index[0] ? 8'h0 : { sin_lut_mux[14], sin_lut_mux[12], sin_lut_mux[10], sin_lut_mux[8], sin_lut_mux[6], sin_lut_mux[4], sin_lut_mux[2], sin_lut_mux[0] }; 1227 | 1228 | wire [11:0] sin_sum = sin_base + { sin_delta[7], sin_delta }; 1229 | 1230 | wire [11:0] op_logsin; 1231 | 1232 | ym_sr_bit_array #(.DATA_WIDTH(12)) l_op_logsin(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(sin_sum), .val(op_logsin)); 1233 | 1234 | wire op_saw; 1235 | ym_sr_bit l_op_saw(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(sawtooth), .val(op_saw)); 1236 | wire [8:0] op_saw_phase; 1237 | ym_sr_bit_array #(.DATA_WIDTH(9)) l_op_saw_phase(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(op_phase3), .val(op_saw_phase)); 1238 | 1239 | wire [12:0] att = {1'h0, op_saw ? { op_saw_phase, 3'h0 } : op_logsin } + { 1'h0, eg_out, 3'h0 }; 1240 | 1241 | wire [11:0] att_clamp = ~(att[12] ? 12'hfff : att[11:0]); 1242 | 1243 | wire [7:0] pow_index = att_clamp[7:0]; 1244 | 1245 | wire [4:0] pow_lut_index = pow_index[5:1]; 1246 | 1247 | reg [47:0] pow_lut_out; 1248 | 1249 | always @(pow_lut_index) 1250 | begin 1251 | case (pow_lut_index) 1252 | 5'h1f: pow_lut_out = 48'b111011111100011111101000111101000001000110011101; 1253 | 5'h1e: pow_lut_out = 48'b111011111100011010011111011000001011100010110011; 1254 | 5'h1d: pow_lut_out = 48'b111011111100000011110110111101101001110111011010; 1255 | 5'h1c: pow_lut_out = 48'b111011111100000011100001111101100101000001010110; 1256 | 5'h1b: pow_lut_out = 48'b111011111100000010000110011100100101000001011011; 1257 | 5'h1a: pow_lut_out = 48'b111011101001010101011101111101000001111111011101; 1258 | 5'h19: pow_lut_out = 48'b111011001011011101111010011111001000011011000000; 1259 | 5'h18: pow_lut_out = 48'b111011001011011100100101111100001001001111011110; 1260 | 5'h17: pow_lut_out = 48'b111011001011001101000110111101000001101011011010; 1261 | 5'h16: pow_lut_out = 48'b111011001011000001110011011101110001010111010100; 1262 | 5'h15: pow_lut_out = 48'b111011000011100010111100111100110001110110010101; 1263 | 5'h14: pow_lut_out = 48'b111010000111110011001111011101111001110010011011; 1264 | 5'h13: pow_lut_out = 48'b111010000111110011000000111001111011001110111101; 1265 | 5'h12: pow_lut_out = 48'b111010000100111110110111111100110101101001010001; 1266 | 5'h11: pow_lut_out = 48'b111010000100111110110000011100110001001110010011; 1267 | 5'h10: pow_lut_out = 48'b111010000100101101011010111101001001110011010101; 1268 | 5'h0f: pow_lut_out = 48'b111010000100101100001101011001001011010110110111; 1269 | 5'h0e: pow_lut_out = 48'b111010000100100100101010011000000011111010110001; 1270 | 5'h0d: pow_lut_out = 48'b111010000000110001110101111000000011011110110011; 1271 | 5'h0c: pow_lut_out = 48'b111010000000110000010110011001011011100011110101; 1272 | 5'h0b: pow_lut_out = 48'b111010000000010010001001111101011001000110010101; 1273 | 5'h0a: pow_lut_out = 48'b101110100010001011101110111000010011101010110101; 1274 | 5'h09: pow_lut_out = 48'b101100110011001111111001011000010011001111110011; 1275 | 5'h08: pow_lut_out = 48'b101100110011001110010011111001001011100010110001; 1276 | 5'h07: pow_lut_out = 48'b100101110111011111010100111001000011000010101010; 1277 | 5'h06: pow_lut_out = 48'b100101110111010111100011011000000011101110111000; 1278 | 5'h05: pow_lut_out = 48'b100101110111010100101100111100001001001010011010; 1279 | 5'h04: pow_lut_out = 48'b100101110111010000011011011100011001000110010000; 1280 | 5'h03: pow_lut_out = 48'b100101110111000001011000011001010011101010110001; 1281 | 5'h02: pow_lut_out = 48'b100101110101001000100111111001010011001110111011; 1282 | 5'h01: pow_lut_out = 48'b100101110101001000100001011101001001000100000000; 1283 | 5'h00: pow_lut_out = 48'b100101110001011001000110011000000011101010110000; 1284 | endcase 1285 | end 1286 | 1287 | wire pow_index_top_sel[4]; 1288 | assign pow_index_top_sel[0] = pow_index[7:6] == 2'h0; 1289 | assign pow_index_top_sel[1] = pow_index[7:6] == 2'h1; 1290 | assign pow_index_top_sel[2] = pow_index[7:6] == 2'h2; 1291 | assign pow_index_top_sel[3] = pow_index[7:6] == 2'h3; 1292 | 1293 | wire [12:0] pow_lut_mux; 1294 | 1295 | assign pow_lut_mux[0] = (pow_lut_out[0] & pow_index_top_sel[0]) | (pow_lut_out[1] & pow_index_top_sel[1]) 1296 | | (pow_lut_out[2] & pow_index_top_sel[2]) | (pow_lut_out[3] & pow_index_top_sel[3]); 1297 | assign pow_lut_mux[1] = (pow_lut_out[4] & pow_index_top_sel[0]) | (pow_lut_out[5] & pow_index_top_sel[1]) 1298 | | (pow_lut_out[6] & pow_index_top_sel[2]) | (pow_lut_out[7] & pow_index_top_sel[3]); 1299 | assign pow_lut_mux[2] = (pow_lut_out[8] & pow_index_top_sel[0]) | (pow_lut_out[9] & pow_index_top_sel[1]) 1300 | | (pow_lut_out[10] & pow_index_top_sel[2]) | (pow_lut_out[11] & pow_index_top_sel[3]); 1301 | assign pow_lut_mux[3] = (pow_lut_out[12] & pow_index_top_sel[0]) | (pow_lut_out[13] & pow_index_top_sel[1]) 1302 | | (pow_lut_out[14] & pow_index_top_sel[3]); 1303 | assign pow_lut_mux[4] = (pow_lut_out[15] & pow_index_top_sel[0]) | (pow_lut_out[16] & pow_index_top_sel[1]) 1304 | | (pow_lut_out[17] & pow_index_top_sel[2]) | (pow_lut_out[18] & pow_index_top_sel[3]); 1305 | assign pow_lut_mux[5] = (pow_lut_out[19] & pow_index_top_sel[0]) | (pow_lut_out[20] & pow_index_top_sel[1]) 1306 | | (pow_lut_out[21] & pow_index_top_sel[2]) | (pow_lut_out[22] & pow_index_top_sel[3]); 1307 | assign pow_lut_mux[6] = (pow_lut_out[23] & pow_index_top_sel[0]) | (pow_lut_out[24] & pow_index_top_sel[1]) 1308 | | (pow_lut_out[25] & pow_index_top_sel[2]) | (pow_lut_out[26] & pow_index_top_sel[3]); 1309 | assign pow_lut_mux[7] = (pow_lut_out[27] & pow_index_top_sel[0]) | (pow_lut_out[28] & pow_index_top_sel[1]) 1310 | | (pow_lut_out[29] & pow_index_top_sel[2]) | (pow_lut_out[30] & pow_index_top_sel[3]); 1311 | assign pow_lut_mux[8] = (pow_lut_out[31] & pow_index_top_sel[0]) | (pow_lut_out[32] & pow_index_top_sel[1]) 1312 | | (pow_lut_out[33] & pow_index_top_sel[2]) | (pow_lut_out[34] & pow_index_top_sel[3]); 1313 | assign pow_lut_mux[9] = (pow_lut_out[35] & pow_index_top_sel[0]) | (pow_lut_out[36] & pow_index_top_sel[1]) 1314 | | (pow_lut_out[37] & pow_index_top_sel[2]) | (pow_lut_out[38] & pow_index_top_sel[3]); 1315 | assign pow_lut_mux[10] = (pow_lut_out[39] & pow_index_top_sel[0]) | (pow_lut_out[40] & pow_index_top_sel[1]) 1316 | | (pow_lut_out[41] & pow_index_top_sel[2]) | (pow_lut_out[42] & pow_index_top_sel[3]); 1317 | assign pow_lut_mux[11] = (pow_lut_out[43] & pow_index_top_sel[1]) 1318 | | (pow_lut_out[44] & pow_index_top_sel[2]) | (pow_lut_out[45] & pow_index_top_sel[3]); 1319 | assign pow_lut_mux[12] = (pow_lut_out[46] & pow_index_top_sel[2]) | (pow_lut_out[47] & pow_index_top_sel[3]); 1320 | 1321 | wire [9:0] pow_base = { pow_lut_mux[12:6], pow_lut_mux[4], pow_lut_mux[2], pow_lut_mux[0] }; 1322 | wire [2:0] pow_delta = pow_index[0] ? { pow_lut_mux[5], pow_lut_mux[3], pow_lut_mux[1] } : 3'h0; 1323 | 1324 | wire [9:0] pow_sum = pow_base + pow_delta; 1325 | 1326 | wire [9:0] op_pow; 1327 | ym_sr_bit_array #(.DATA_WIDTH(10)) l_op_pow(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(pow_sum), .val(op_pow)); 1328 | wire [3:0] op_shift; 1329 | ym_sr_bit_array #(.DATA_WIDTH(4)) l_op_shift(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(att_clamp[11:8]), .val(op_shift)); 1330 | 1331 | wire sh_sel1[4]; 1332 | 1333 | assign sh_sel1[0] = op_shift[1:0] == 2'h0; 1334 | assign sh_sel1[1] = op_shift[1:0] == 2'h1; 1335 | assign sh_sel1[2] = op_shift[1:0] == 2'h2; 1336 | assign sh_sel1[3] = op_shift[1:0] == 2'h3; 1337 | 1338 | wire sh_sel2[1:3]; 1339 | 1340 | assign sh_sel2[1] = op_shift[3:2] == 2'h1 & ~op_mute; 1341 | assign sh_sel2[2] = op_shift[3:2] == 2'h2 & ~op_mute; 1342 | assign sh_sel2[3] = op_shift[3:2] == 2'h3 & ~op_mute; 1343 | 1344 | wire [11:0] pow_shift1 = ({12{sh_sel1[3]}} & { 1'h1, op_pow, 1'h0 }) 1345 | | ({12{sh_sel1[2]}} & { 2'h1, op_pow }) 1346 | | ({12{sh_sel1[1]}} & { 3'h1, op_pow[9:1] }) 1347 | | ({12{sh_sel1[0]}} & { 4'h1, op_pow[9:2] }); 1348 | 1349 | wire [11:0] pow_shift2 = ({12{sh_sel2[3]}} & pow_shift1 ) 1350 | | ({12{sh_sel2[2]}} & { 4'h0, pow_shift1[11:4] } ) 1351 | | ({12{sh_sel2[1]}} & { 8'h0, pow_shift1[11:8] } ); 1352 | 1353 | wire [12:0] op_value = (~op_mute & op_sign) ? { 1'h1, ~pow_shift2 } : { 1'h0, pow_shift2 }; 1354 | 1355 | wire [12:0] op_fb[4]; 1356 | wire [12:0] op_fb1_o; 1357 | wire [12:0] op_fb3_o; 1358 | 1359 | ym_sr_bit_array #(.DATA_WIDTH(13), .SR_LENGTH(9)) l_op_fb0(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(fsm_out[15] ? op_value : op_fb[0]), .val(op_fb[0])); 1360 | ym_sr_bit_array #(.DATA_WIDTH(13), .SR_LENGTH(6)) l_op_fb1_0(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(fsm_out[15] ? op_fb[0] : op_fb[1]), .val(op_fb1_o)); 1361 | ym_sr_bit_array #(.DATA_WIDTH(13), .SR_LENGTH(3)) l_op_fb1_1(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(op_fb1_o), .val(op_fb[1])); 1362 | 1363 | ym_sr_bit_array #(.DATA_WIDTH(13), .SR_LENGTH(9)) l_op_fb2(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(fsm_out[15] ? op_fb[1] : op_fb[2]), .val(op_fb[2])); 1364 | ym_sr_bit_array #(.DATA_WIDTH(13), .SR_LENGTH(6)) l_op_fb3_0(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(fsm_out[15] ? op_fb[2] : op_fb[3]), .val(op_fb3_o)); 1365 | ym_sr_bit_array #(.DATA_WIDTH(13), .SR_LENGTH(3)) l_op_fb3_1(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(op_fb3_o), .val(op_fb[3])); 1366 | 1367 | wire [13:0] fb_sum = { op_fb1_o[12], op_fb1_o } + { op_fb3_o[12], op_fb3_o }; 1368 | 1369 | wire [9:0] mod = ((fsm_out[16] & ~fsm_out[14]) ? op_value[9:0] : 10'h0) | 1370 | ((fsm_out[12] & fb_l == 3'h1) ? { {4{fb_sum[13]}}, fb_sum[13:8] } : 10'h0) | 1371 | ((fsm_out[12] & fb_l == 3'h2) ? { {3{fb_sum[13]}}, fb_sum[13:7] } : 10'h0) | 1372 | ((fsm_out[12] & fb_l == 3'h3) ? { {2{fb_sum[13]}}, fb_sum[13:6] } : 10'h0) | 1373 | ((fsm_out[12] & fb_l == 3'h4) ? { fb_sum[13], fb_sum[13:5] } : 10'h0) | 1374 | ((fsm_out[12] & fb_l == 3'h5) ? fb_sum[13:4] : 10'h0) | 1375 | ((fsm_out[12] & fb_l == 3'h6) ? fb_sum[12:3] : 10'h0) | 1376 | ((fsm_out[12] & fb_l == 3'h7) ? fb_sum[11:2] : 10'h0); 1377 | 1378 | ym_sr_bit_array #(.DATA_WIDTH(10)) l_op_mod(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(mod), .val(op_mod)); 1379 | 1380 | 1381 | wire [18:0] op_out; 1382 | assign op_out[13:0] = fsm_out[13] ? (fsm_out[11] ? { op_value, 1'h0 } : { op_value[12], op_value }) : 13'h0; 1383 | assign op_out[18:14] = {5{op_out[13]}}; 1384 | 1385 | wire accm_load_ac; 1386 | ym_edge_detect l_accm_load_ac(.MCLK(MCLK), .c1(clk1), .inp(fsm_out[6]), .val(accm_load_ac)); 1387 | wire accm_load_bd; 1388 | ym_edge_detect l_accm_load_bd(.MCLK(MCLK), .c1(clk1), .inp(fsm_out[4]), .val(accm_load_bd)); 1389 | 1390 | wire [18:0] accm_a; 1391 | ym_sr_bit_array #(.DATA_WIDTH(19)) l_accm_a(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp((fsm_out[6] ? 19'h0 : accm_a) + (pan_l[0] ? op_out : 19'h0)), .val(accm_a)); 1392 | wire [18:0] accm_b; 1393 | ym_sr_bit_array #(.DATA_WIDTH(19)) l_accm_b(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp((fsm_out[4] ? 19'h0 : accm_b) + (pan_l[1] ? op_out : 19'h0)), .val(accm_b)); 1394 | wire [18:0] accm_c; 1395 | ym_sr_bit_array #(.DATA_WIDTH(19)) l_accm_c(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp((fsm_out[6] ? 19'h0 : accm_c) + (pan_l[2] ? op_out : 19'h0)), .val(accm_c)); 1396 | wire [18:0] accm_d; 1397 | ym_sr_bit_array #(.DATA_WIDTH(19)) l_accm_d(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp((fsm_out[4] ? 19'h0 : accm_d) + (pan_l[3] ? op_out : 19'h0)), .val(accm_d)); 1398 | 1399 | wire accm_a_sign; 1400 | wire accm_a_of; 1401 | ym_slatch l_accm_a_sign(.MCLK(MCLK), .en(accm_load_ac), .inp(~accm_a[18]), .val(accm_a_sign)); 1402 | ym_slatch l_accm_a_of(.MCLK(MCLK), .en(accm_load_ac), .inp(~(accm_a[18:15] == 4'h0 | accm_a[18:15] == 4'hf)), .val(accm_a_of)); 1403 | wire accm_c_sign; 1404 | wire accm_c_of; 1405 | ym_slatch l_accm_c_sign(.MCLK(MCLK), .en(accm_load_ac), .inp(~accm_c[18]), .val(accm_c_sign)); 1406 | ym_slatch l_accm_c_of(.MCLK(MCLK), .en(accm_load_ac), .inp(~(accm_c[18:15] == 4'h0 | accm_c[18:15] == 4'hf)), .val(accm_c_of)); 1407 | wire accm_b_sign; 1408 | wire accm_b_of; 1409 | ym_slatch l_accm_b_sign(.MCLK(MCLK), .en(accm_load_bd), .inp(~accm_b[18]), .val(accm_b_sign)); 1410 | ym_slatch l_accm_b_of(.MCLK(MCLK), .en(accm_load_bd), .inp(~(accm_b[18:15] == 4'h0 | accm_b[18:15] == 4'hf)), .val(accm_b_of)); 1411 | wire accm_d_sign; 1412 | wire accm_d_of; 1413 | ym_slatch l_accm_d_sign(.MCLK(MCLK), .en(accm_load_bd), .inp(~accm_d[18]), .val(accm_d_sign)); 1414 | ym_slatch l_accm_d_of(.MCLK(MCLK), .en(accm_load_bd), .inp(~(accm_d[18:15] == 4'h0 | accm_d[18:15] == 4'hf)), .val(accm_d_of)); 1415 | 1416 | wire accm_shift_a; 1417 | ym_dbg_read #(.DATA_WIDTH(16)) l_accm_shift_a(.MCLK(MCLK), .c1(clk1), .c2(clk2), .prev(1'h0), .load(fsm_out[6]), 1418 | .load_val({ ~accm_a[18], accm_a[14:0] }), .next(accm_shift_a)); 1419 | wire accm_shift_b; 1420 | ym_dbg_read #(.DATA_WIDTH(16)) l_accm_shift_b(.MCLK(MCLK), .c1(clk1), .c2(clk2), .prev(1'h0), .load(fsm_out[4]), 1421 | .load_val({ ~accm_b[18], accm_b[14:0] }), .next(accm_shift_b)); 1422 | wire accm_shift_c; 1423 | ym_dbg_read #(.DATA_WIDTH(16)) l_accm_shift_c(.MCLK(MCLK), .c1(clk1), .c2(clk2), .prev(1'h0), .load(fsm_out[6]), 1424 | .load_val({ ~accm_c[18], accm_c[14:0] }), .next(accm_shift_c)); 1425 | wire accm_shift_d; 1426 | ym_dbg_read #(.DATA_WIDTH(16)) l_accm_shift_d(.MCLK(MCLK), .c1(clk1), .c2(clk2), .prev(1'h0), .load(fsm_out[4]), 1427 | .load_val({ ~accm_d[18], accm_d[14:0] }), .next(accm_shift_d)); 1428 | 1429 | assign DOAB = fsm_out[8] ? (accm_a_of ? accm_a_sign : accm_shift_a) : (accm_b_of ? accm_b_sign : accm_shift_b); 1430 | assign DOCD = fsm_out[8] ? (accm_c_of ? accm_c_sign : accm_shift_c) : (accm_d_of ? accm_d_sign : accm_shift_d); 1431 | 1432 | assign SY = clk2; 1433 | 1434 | assign SMPAC = fsm_out[10]; 1435 | 1436 | assign SMPBD = fsm_out[9]; 1437 | 1438 | assign IRQ_pull = t1_status | t2_status; 1439 | 1440 | assign DATA_o = { t1_status | t2_status, t1_status, t2_status, 5'h0 }; 1441 | assign DATA_d = ~io_read; 1442 | 1443 | wire ra_dbg_load; 1444 | ym_sr_bit l_ra_dbg_load(.MCLK(MCLK), .c1(clk1), .c2(clk2), .inp(reg_test0[7]), .val(ra_dbg_load)); 1445 | 1446 | wire ra_dbg1; 1447 | ym_dbg_read #(.DATA_WIDTH(35)) l_ra_dbg1(.MCLK(MCLK), .c1(clk1), .c2(clk2), .prev(1'h0), .load(reg_test0[7] & ~ra_dbg_load), 1448 | .load_val({ wf, sl, rr, ar, dr, ksl, tl, am, vib, egt, ksr, multi}), .next(ra_dbg1)); 1449 | wire ra_dbg2; 1450 | ym_dbg_read #(.DATA_WIDTH(23)) l_ra_dbg2(.MCLK(MCLK), .c1(clk1), .c2(clk2), .prev(1'h0), .load(reg_test0[7] & ~ra_dbg_load), 1451 | .load_val({ fb, connect_pair, pan, connect, keyon, blk, fnum }), .next(ra_dbg2)); 1452 | 1453 | assign TEST = (reg_test1[3:0] == 3'h0 ? 1'h0 : 1'h0) | 1454 | (reg_test1[3:0] == 3'h1 ? ra_dbg1 : 1'h0) | 1455 | (reg_test1[3:0] == 3'h2 ? ra_dbg2 : 1'h0) | 1456 | (reg_test1[3:0] == 3'h3 ? pg_dbg : 1'h0) | 1457 | (reg_test1[3:0] == 3'h4 ? eg_dbg : 1'h0); 1458 | 1459 | endmodule 1460 | --------------------------------------------------------------------------------