├── opnb.h ├── opnb.c └── LICENSE /opnb.h: -------------------------------------------------------------------------------- 1 | /* Nuked OPNB 2 | * Copyright (C) 2020 Nuke.YKT 3 | * 4 | * This file is part of Nuked OPNB. 5 | * 6 | * Nuked OPNB is free software: you can redistribute it and/or modify 7 | * it under the terms of the GNU Lesser General Public License as 8 | * published by the Free Software Foundation, either version 2.1 9 | * of the License, or (at your option) any later version. 10 | * 11 | * Nuked OPNB is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU Lesser General Public License for more details. 15 | * 16 | * You should have received a copy of the GNU Lesser General Public License 17 | * along with Nuked OPNB. If not, see . 18 | * 19 | * Nuked OPNB emulator. 20 | * Thanks: 21 | * siliconpr0n.org(John McMaster, digshadow): 22 | * YM2610 and other FM chip decaps and die shots. 23 | * 24 | * version: 0.0 25 | */ 26 | #ifndef _OPM_H_ 27 | #define _OPM_H_ 28 | 29 | #include 30 | 31 | 32 | typedef struct { 33 | uint32_t clock_state; 34 | uint32_t cycles; 35 | uint8_t ic; 36 | uint32_t ic_sr; 37 | uint32_t ic2; 38 | uint32_t ic_latch; 39 | 40 | uint32_t fmcycles; 41 | uint32_t fmstate_l, fmstate_h; 42 | uint32_t slot_counter_l, slot_counter_h; 43 | uint32_t fmcycle[24]; 44 | uint8_t fm_data; 45 | uint16_t fm_address; 46 | uint16_t timer_a_reg; 47 | uint8_t timer_b_reg; 48 | uint8_t mode_1c; 49 | uint8_t mode_ch3; 50 | uint8_t mode_csm; 51 | uint8_t mode_test; 52 | uint8_t mode_test2; 53 | uint8_t mode_kon_operator[4]; 54 | uint8_t mode_kon_channel; 55 | uint8_t lfo_en; 56 | uint8_t lfo_freq; 57 | uint8_t timer_a_load; 58 | uint8_t timer_a_enable; 59 | uint8_t timer_a_reset; 60 | uint8_t timer_b_load; 61 | uint8_t timer_b_enable; 62 | uint8_t timer_b_reset; 63 | uint8_t write_fm_address; 64 | uint8_t write_fm_data; 65 | uint8_t write_mode_1c; 66 | uint8_t write_mode_27; 67 | uint8_t write_mode_25; 68 | uint8_t write_mode_24; 69 | uint8_t write_mode_21; 70 | uint8_t write_mode_28; 71 | uint8_t write_mode_26; 72 | uint8_t write_mode_22; 73 | uint8_t write_mode_02; 74 | uint8_t write_d; 75 | uint8_t write_d_en; 76 | uint8_t write_a; 77 | uint8_t write_a_en; 78 | uint16_t write_data; 79 | uint8_t write_ssg; 80 | uint8_t fm_multi[2][12]; 81 | uint8_t fm_dt[2][12]; 82 | uint8_t fm_tl[2][12]; 83 | uint8_t fm_ar[2][12]; 84 | uint8_t fm_ks[2][12]; 85 | uint8_t fm_ar[2][12]; 86 | uint8_t fm_ks[2][12]; 87 | uint8_t fm_dr[2][12]; 88 | uint8_t fm_am[2][12]; 89 | uint8_t fm_sr[2][12]; 90 | uint8_t fm_rr[2][12]; 91 | uint8_t fm_sl[2][12]; 92 | uint8_t fm_ssg_eg[2][12]; 93 | uint8_t fm_reg_a4; 94 | uint8_t fm_reg_ac; 95 | uint16_t fm_fnum[6]; 96 | uint8_t fm_block[6]; 97 | uint16_t fm_fnum_3ch[6]; 98 | uint8_t fm_block_3ch[6]; 99 | uint8_t fm_connect[6]; 100 | uint8_t fm_fb[6]; 101 | uint8_t fm_pms[6]; 102 | uint8_t fm_ams[6]; 103 | uint8_t fm_pan_l[6]; 104 | uint8_t fm_pan_r[6]; 105 | } opnb_t; 106 | 107 | #endif 108 | -------------------------------------------------------------------------------- /opnb.c: -------------------------------------------------------------------------------- 1 | /* Nuked OPNB 2 | * Copyright (C) 2020 Nuke.YKT 3 | * 4 | * This file is part of Nuked OPNB. 5 | * 6 | * Nuked OPNB is free software: you can redistribute it and/or modify 7 | * it under the terms of the GNU Lesser General Public License as 8 | * published by the Free Software Foundation, either version 2.1 9 | * of the License, or (at your option) any later version. 10 | * 11 | * Nuked OPNB is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU Lesser General Public License for more details. 15 | * 16 | * You should have received a copy of the GNU Lesser General Public License 17 | * along with Nuked OPNB. If not, see . 18 | * 19 | * Nuked OPNB emulator. 20 | * Thanks: 21 | * siliconpr0n.org(John McMaster, digshadow): 22 | * YM2610 and other FM chip decaps and die shots. 23 | * 24 | * version: 0.0 25 | */ 26 | #include 27 | #include 28 | #include "opnb.h" 29 | 30 | enum { 31 | eg_num_attack = 0, 32 | eg_num_decay = 1, 33 | eg_num_sustain = 2, 34 | eg_num_release = 3 35 | }; 36 | 37 | enum { 38 | clock_fm_1 = 0, 39 | clock_fm_2, 40 | }; 41 | 42 | /* logsin table */ 43 | static const uint16_t logsinrom[256] = { 44 | 0x859, 0x6c3, 0x607, 0x58b, 0x52e, 0x4e4, 0x4a6, 0x471, 45 | 0x443, 0x41a, 0x3f5, 0x3d3, 0x3b5, 0x398, 0x37e, 0x365, 46 | 0x34e, 0x339, 0x324, 0x311, 0x2ff, 0x2ed, 0x2dc, 0x2cd, 47 | 0x2bd, 0x2af, 0x2a0, 0x293, 0x286, 0x279, 0x26d, 0x261, 48 | 0x256, 0x24b, 0x240, 0x236, 0x22c, 0x222, 0x218, 0x20f, 49 | 0x206, 0x1fd, 0x1f5, 0x1ec, 0x1e4, 0x1dc, 0x1d4, 0x1cd, 50 | 0x1c5, 0x1be, 0x1b7, 0x1b0, 0x1a9, 0x1a2, 0x19b, 0x195, 51 | 0x18f, 0x188, 0x182, 0x17c, 0x177, 0x171, 0x16b, 0x166, 52 | 0x160, 0x15b, 0x155, 0x150, 0x14b, 0x146, 0x141, 0x13c, 53 | 0x137, 0x133, 0x12e, 0x129, 0x125, 0x121, 0x11c, 0x118, 54 | 0x114, 0x10f, 0x10b, 0x107, 0x103, 0x0ff, 0x0fb, 0x0f8, 55 | 0x0f4, 0x0f0, 0x0ec, 0x0e9, 0x0e5, 0x0e2, 0x0de, 0x0db, 56 | 0x0d7, 0x0d4, 0x0d1, 0x0cd, 0x0ca, 0x0c7, 0x0c4, 0x0c1, 57 | 0x0be, 0x0bb, 0x0b8, 0x0b5, 0x0b2, 0x0af, 0x0ac, 0x0a9, 58 | 0x0a7, 0x0a4, 0x0a1, 0x09f, 0x09c, 0x099, 0x097, 0x094, 59 | 0x092, 0x08f, 0x08d, 0x08a, 0x088, 0x086, 0x083, 0x081, 60 | 0x07f, 0x07d, 0x07a, 0x078, 0x076, 0x074, 0x072, 0x070, 61 | 0x06e, 0x06c, 0x06a, 0x068, 0x066, 0x064, 0x062, 0x060, 62 | 0x05e, 0x05c, 0x05b, 0x059, 0x057, 0x055, 0x053, 0x052, 63 | 0x050, 0x04e, 0x04d, 0x04b, 0x04a, 0x048, 0x046, 0x045, 64 | 0x043, 0x042, 0x040, 0x03f, 0x03e, 0x03c, 0x03b, 0x039, 65 | 0x038, 0x037, 0x035, 0x034, 0x033, 0x031, 0x030, 0x02f, 66 | 0x02e, 0x02d, 0x02b, 0x02a, 0x029, 0x028, 0x027, 0x026, 67 | 0x025, 0x024, 0x023, 0x022, 0x021, 0x020, 0x01f, 0x01e, 68 | 0x01d, 0x01c, 0x01b, 0x01a, 0x019, 0x018, 0x017, 0x017, 69 | 0x016, 0x015, 0x014, 0x014, 0x013, 0x012, 0x011, 0x011, 70 | 0x010, 0x00f, 0x00f, 0x00e, 0x00d, 0x00d, 0x00c, 0x00c, 71 | 0x00b, 0x00a, 0x00a, 0x009, 0x009, 0x008, 0x008, 0x007, 72 | 0x007, 0x007, 0x006, 0x006, 0x005, 0x005, 0x005, 0x004, 73 | 0x004, 0x004, 0x003, 0x003, 0x003, 0x002, 0x002, 0x002, 74 | 0x002, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 75 | 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000 76 | }; 77 | 78 | /* exp table */ 79 | static const uint16_t exprom[256] = { 80 | 0x7fa, 0x7f5, 0x7ef, 0x7ea, 0x7e4, 0x7df, 0x7da, 0x7d4, 81 | 0x7cf, 0x7c9, 0x7c4, 0x7bf, 0x7b9, 0x7b4, 0x7ae, 0x7a9, 82 | 0x7a4, 0x79f, 0x799, 0x794, 0x78f, 0x78a, 0x784, 0x77f, 83 | 0x77a, 0x775, 0x770, 0x76a, 0x765, 0x760, 0x75b, 0x756, 84 | 0x751, 0x74c, 0x747, 0x742, 0x73d, 0x738, 0x733, 0x72e, 85 | 0x729, 0x724, 0x71f, 0x71a, 0x715, 0x710, 0x70b, 0x706, 86 | 0x702, 0x6fd, 0x6f8, 0x6f3, 0x6ee, 0x6e9, 0x6e5, 0x6e0, 87 | 0x6db, 0x6d6, 0x6d2, 0x6cd, 0x6c8, 0x6c4, 0x6bf, 0x6ba, 88 | 0x6b5, 0x6b1, 0x6ac, 0x6a8, 0x6a3, 0x69e, 0x69a, 0x695, 89 | 0x691, 0x68c, 0x688, 0x683, 0x67f, 0x67a, 0x676, 0x671, 90 | 0x66d, 0x668, 0x664, 0x65f, 0x65b, 0x657, 0x652, 0x64e, 91 | 0x649, 0x645, 0x641, 0x63c, 0x638, 0x634, 0x630, 0x62b, 92 | 0x627, 0x623, 0x61e, 0x61a, 0x616, 0x612, 0x60e, 0x609, 93 | 0x605, 0x601, 0x5fd, 0x5f9, 0x5f5, 0x5f0, 0x5ec, 0x5e8, 94 | 0x5e4, 0x5e0, 0x5dc, 0x5d8, 0x5d4, 0x5d0, 0x5cc, 0x5c8, 95 | 0x5c4, 0x5c0, 0x5bc, 0x5b8, 0x5b4, 0x5b0, 0x5ac, 0x5a8, 96 | 0x5a4, 0x5a0, 0x59c, 0x599, 0x595, 0x591, 0x58d, 0x589, 97 | 0x585, 0x581, 0x57e, 0x57a, 0x576, 0x572, 0x56f, 0x56b, 98 | 0x567, 0x563, 0x560, 0x55c, 0x558, 0x554, 0x551, 0x54d, 99 | 0x549, 0x546, 0x542, 0x53e, 0x53b, 0x537, 0x534, 0x530, 100 | 0x52c, 0x529, 0x525, 0x522, 0x51e, 0x51b, 0x517, 0x514, 101 | 0x510, 0x50c, 0x509, 0x506, 0x502, 0x4ff, 0x4fb, 0x4f8, 102 | 0x4f4, 0x4f1, 0x4ed, 0x4ea, 0x4e7, 0x4e3, 0x4e0, 0x4dc, 103 | 0x4d9, 0x4d6, 0x4d2, 0x4cf, 0x4cc, 0x4c8, 0x4c5, 0x4c2, 104 | 0x4be, 0x4bb, 0x4b8, 0x4b5, 0x4b1, 0x4ae, 0x4ab, 0x4a8, 105 | 0x4a4, 0x4a1, 0x49e, 0x49b, 0x498, 0x494, 0x491, 0x48e, 106 | 0x48b, 0x488, 0x485, 0x482, 0x47e, 0x47b, 0x478, 0x475, 107 | 0x472, 0x46f, 0x46c, 0x469, 0x466, 0x463, 0x460, 0x45d, 108 | 0x45a, 0x457, 0x454, 0x451, 0x44e, 0x44b, 0x448, 0x445, 109 | 0x442, 0x43f, 0x43c, 0x439, 0x436, 0x433, 0x430, 0x42d, 110 | 0x42a, 0x428, 0x425, 0x422, 0x41f, 0x41c, 0x419, 0x416, 111 | 0x414, 0x411, 0x40e, 0x40b, 0x408, 0x406, 0x403, 0x400 112 | }; 113 | 114 | /* Note table */ 115 | static const uint32_t fn_note[16] = { 116 | 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 3, 3, 3, 3, 3, 3 117 | }; 118 | 119 | /* Envelope generator */ 120 | static const uint32_t eg_stephi[4][4] = { 121 | { 0, 0, 0, 0 }, 122 | { 1, 0, 0, 0 }, 123 | { 1, 0, 1, 0 }, 124 | { 1, 1, 1, 0 } 125 | }; 126 | 127 | static const uint8_t eg_am_shift[4] = { 128 | 7, 3, 1, 0 129 | }; 130 | 131 | /* Phase generator */ 132 | static const uint32_t pg_detune[8] = { 16, 17, 19, 20, 22, 24, 27, 29 }; 133 | 134 | static const uint32_t pg_lfo_sh1[8][8] = { 135 | { 7, 7, 7, 7, 7, 7, 7, 7 }, 136 | { 7, 7, 7, 7, 7, 7, 7, 7 }, 137 | { 7, 7, 7, 7, 7, 7, 1, 1 }, 138 | { 7, 7, 7, 7, 1, 1, 1, 1 }, 139 | { 7, 7, 7, 1, 1, 1, 1, 0 }, 140 | { 7, 7, 1, 1, 0, 0, 0, 0 }, 141 | { 7, 7, 1, 1, 0, 0, 0, 0 }, 142 | { 7, 7, 1, 1, 0, 0, 0, 0 } 143 | }; 144 | 145 | static const uint32_t pg_lfo_sh2[8][8] = { 146 | { 7, 7, 7, 7, 7, 7, 7, 7 }, 147 | { 7, 7, 7, 7, 2, 2, 2, 2 }, 148 | { 7, 7, 7, 2, 2, 2, 7, 7 }, 149 | { 7, 7, 2, 2, 7, 7, 2, 2 }, 150 | { 7, 7, 2, 7, 7, 7, 2, 7 }, 151 | { 7, 7, 7, 2, 7, 7, 2, 1 }, 152 | { 7, 7, 7, 2, 7, 7, 2, 1 }, 153 | { 7, 7, 7, 2, 7, 7, 2, 1 } 154 | }; 155 | 156 | /* Address decoder */ 157 | static const uint32_t slot_map[16] = { 158 | 0x000, /* Ch1 OP1/OP2 */ 159 | 0x001, /* Ch2 OP1/OP2 */ 160 | 0x002, /* Ch3 OP1/OP2 */ 161 | 0x003, /* Illegal */ 162 | 0x100, /* Ch4 OP1/OP2 */ 163 | 0x101, /* Ch5 OP1/OP2 */ 164 | 0x102, /* Ch6 OP1/OP2 */ 165 | 0x103, /* Illegal */ 166 | 0x004, /* Ch1 OP3/OP4 */ 167 | 0x005, /* Ch2 OP3/OP4 */ 168 | 0x006, /* Ch3 OP3/OP4 */ 169 | 0x007, /* Illegal */ 170 | 0x104, /* Ch4 OP3/OP4 */ 171 | 0x105, /* Ch5 OP3/OP4 */ 172 | 0x106 /* Ch6 OP3/OP4 */ 173 | 0x107, /* Illegal */ 174 | }; 175 | 176 | /* LFO */ 177 | static const uint32_t lfo_cycles[8] = { 178 | 108, 77, 71, 67, 62, 44, 8, 5 179 | }; 180 | 181 | /* FM algorithm */ 182 | static const uint32_t fm_algorithm[4][6][8] = { 183 | { 184 | { 1, 1, 1, 1, 1, 1, 1, 1 }, /* OP1_0 */ 185 | { 1, 1, 1, 1, 1, 1, 1, 1 }, /* OP1_1 */ 186 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP2 */ 187 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */ 188 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */ 189 | { 0, 0, 0, 0, 0, 0, 0, 1 } /* Out */ 190 | }, 191 | { 192 | { 0, 1, 0, 0, 0, 1, 0, 0 }, /* OP1_0 */ 193 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_1 */ 194 | { 1, 1, 1, 0, 0, 0, 0, 0 }, /* OP2 */ 195 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */ 196 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */ 197 | { 0, 0, 0, 0, 0, 1, 1, 1 } /* Out */ 198 | }, 199 | { 200 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_0 */ 201 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_1 */ 202 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP2 */ 203 | { 1, 0, 0, 1, 1, 1, 1, 0 }, /* Last operator */ 204 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */ 205 | { 0, 0, 0, 0, 1, 1, 1, 1 } /* Out */ 206 | }, 207 | { 208 | { 0, 0, 1, 0, 0, 1, 0, 0 }, /* OP1_0 */ 209 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_1 */ 210 | { 0, 0, 0, 1, 0, 0, 0, 0 }, /* OP2 */ 211 | { 1, 1, 0, 1, 1, 0, 0, 0 }, /* Last operator */ 212 | { 0, 0, 1, 0, 0, 0, 0, 0 }, /* Last operator */ 213 | { 1, 1, 1, 1, 1, 1, 1, 1 } /* Out */ 214 | } 215 | }; 216 | 217 | static void OPNB_FMDoIO1(opnb_t *chip) 218 | { 219 | chip->write_d_en = (chip->write_d & 20) == 4; 220 | chip->write_a_en = (chip->write_a & 20) == 4; 221 | chip->write_d <<= 1; 222 | chip->write_a <<= 1; 223 | } 224 | 225 | static void OPNB_FMDoIO2(opnb_t *chip) 226 | { 227 | chip->write_d <<= 1; 228 | chip->write_a <<= 1; 229 | } 230 | 231 | static void OPNB_DoRegWrite(opnb_t *chip) 232 | { 233 | uint32_t i, bank, slot, channel; 234 | uint16_t bus, businv, addr; 235 | 236 | if (chip->ic_latch & 2) 237 | { 238 | bus = 0; 239 | businv = (chip->write_data ^ 255) & 255; 240 | } 241 | else 242 | { 243 | bus = chip->write_data & 255; 244 | businv = bus ^ 255; 245 | } 246 | bus |= chip->write_data & 256; 247 | /* Update registers */ 248 | if (chip->write_fm_data) 249 | { 250 | /* Slot */ 251 | if (slot_map[chip->slot_counter_h * 4 + chip->slot_counter_l] == (chip->fm_address & 0x107)) 252 | { 253 | slot = chip->fmcycles % 12; 254 | bank = (chip->fm_address & 8) != 0; 255 | switch (chip->fm_address & 0xf0) 256 | { 257 | case 0x30: /* DT, MULTI */ 258 | chip->fm_multi[bank][slot] = chip->fm_data & 0x0f; 259 | chip->fm_dt[bank][slot] = (chip->fm_data >> 4) & 0x07; 260 | break; 261 | case 0x40: /* TL */ 262 | chip->fm_tl[bank][slot] = chip->fm_data & 0x7f; 263 | break; 264 | case 0x50: /* KS, AR */ 265 | chip->fm_ar[bank][slot] = chip->fm_data & 0x1f; 266 | chip->fm_ks[bank][slot] = (chip->fm_data >> 6) & 0x03; 267 | break; 268 | case 0x60: /* AM, DR */ 269 | chip->fm_dr[bank][slot] = chip->fm_data & 0x1f; 270 | chip->fm_am[bank][slot] = (chip->fm_data >> 7) & 0x01; 271 | break; 272 | case 0x70: /* SR */ 273 | chip->fm_sr[bank][slot] = chip->fm_data & 0x1f; 274 | break; 275 | case 0x80: /* SL, RR */ 276 | chip->fm_rr[bank][slot] = chip->fm_data & 0x0f; 277 | chip->fm_sl[bank][slot] = (chip->fm_data >> 4) & 0x0f; 278 | break; 279 | case 0x90: /* SSG-EG */ 280 | chip->fm_ssg_eg[bank][slot] = chip->fm_data & 0x0f; 281 | break; 282 | } 283 | } 284 | /* Channel */ 285 | if (slot_map[(chip->slot_counter_h & 1) * 4 + chip->slot_counter_l] == (chip->fm_address & 0x103)) 286 | { 287 | channel = chip->fmcycles % 6; 288 | switch (chip->fm_address & 0xfc) 289 | { 290 | case 0xa0: 291 | chip->fm_fnum[channel] = (chip->fm_data & 0xff) | ((chip->fm_reg_a4 & 0x07) << 8); 292 | chip->fm_block[channel] = (chip->fm_reg_a4 >> 3) & 0x07; 293 | break; 294 | case 0xa4: 295 | chip->fm_reg_a4 = chip->fm_data & 0x3f; 296 | break; 297 | case 0xa8: 298 | chip->fm_fnum_3ch[channel] = (chip->fm_data & 0xff) | ((chip->fm_reg_ac & 0x07) << 8); 299 | chip->fm_block_3ch[channel] = (chip->fm_reg_ac >> 3) & 0x07; 300 | break; 301 | case 0xac: 302 | chip->fm_reg_ac = chip->fm_data & 0x3f; 303 | break; 304 | case 0xb0: 305 | chip->fm_connect[channel] = chip->fm_data & 0x07; 306 | chip->fm_fb[channel] = (chip->fm_data >> 3) & 0x07; 307 | break; 308 | case 0xb4: 309 | chip->fm_pms[channel] = chip->fm_data & 0x07; 310 | chip->fm_ams[channel] = (chip->fm_data >> 4) & 0x07; 311 | chip->fm_pan_l[channel] = (chip->fm_data >> 7) & 0x01; 312 | chip->fm_pan_r[channel] = (chip->fm_data >> 6) & 0x01; 313 | break; 314 | } 315 | } 316 | } 317 | /* Data */ 318 | if (chip->write_d_en) 319 | { 320 | if ((bus & 256) == 0) 321 | { 322 | if (chip->write_mode_1c) 323 | { 324 | chip->mode_1c = bus & 191; 325 | } 326 | if (chip->write_mode_27) /* CSM, Timer control */ 327 | { 328 | chip->mode_ch3 = (bus & 0xc0) >> 6; 329 | chip->mode_csm = chip->mode_ch3 == 2; 330 | chip->timer_a_load = bus & 0x01; 331 | chip->timer_a_enable = (bus >> 2) & 0x01; 332 | chip->timer_a_reset = (bus >> 4) & 0x01; 333 | chip->timer_b_load = (bus >> 1) & 0x01; 334 | chip->timer_b_enable = (bus >> 3) & 0x01; 335 | chip->timer_b_reset = (bus >> 5) & 0x01; 336 | } 337 | if (chip->write_mode_25) /* Timer A */ 338 | { 339 | chip->timer_a_reg &= 0x3fc; 340 | chip->timer_a_reg |= bus & 0x03; 341 | } 342 | if (chip->write_mode_24) 343 | { 344 | chip->timer_a_reg &= 0x03; 345 | chip->timer_a_reg |= (bus & 0xff) << 2; 346 | } 347 | if (chip->write_mode_21) /* LSI test */ 348 | { 349 | chip->mode_test = bus & 253; 350 | } 351 | if (chip->write_mode_28) /* Key on/off */ 352 | { 353 | for (i = 0; i < 4; i++) 354 | { 355 | chip->mode_kon_operator[i] = (bus >> (4 + i)) & 0x01; 356 | } 357 | chip->mode_kon_channel = bus & 0x07; 358 | } 359 | if (chip->write_mode_26) /* Timer B */ 360 | { 361 | chip->timer_b_reg = bus & 255; 362 | } 363 | if (chip->write_mode_22) /* LFO control */ 364 | { 365 | if ((bus >> 3) & 0x01) 366 | { 367 | chip->lfo_en = 0x7f; 368 | } 369 | else 370 | { 371 | chip->lfo_en = 0; 372 | } 373 | chip->lfo_freq = bus & 0x07; 374 | } 375 | if (chip->write_mode_02) /* ADPCM LSI Test */ 376 | { 377 | chip->mode_test2 = bus & 184; 378 | } 379 | } 380 | if (chip->write_fm_address) 381 | { 382 | chip->fm_data = bus; 383 | } 384 | } 385 | if (chip->write_a_en) 386 | { 387 | chip->write_fm_data = 0; 388 | } 389 | if (chip->write_fm_address && chip->write_d_en) 390 | { 391 | chip->write_fm_data = 1; 392 | } 393 | /* Address */ 394 | if (chip->write_a_en) 395 | { 396 | chip->write_fm_address = (bus & 0xf0) != 0; 397 | if (chip->write_fm_address) 398 | { 399 | chip->fm_address = bus & 0x1ff; 400 | } 401 | if (chip->ic_latch & 2) 402 | { 403 | chip->write_mode_1c = (bus & 0x100) == 0 && (businv & 0x1c) == 0; 404 | chip->write_mode_27 = (bus & 0x100) == 0 && (businv & 0x27) == 0; 405 | chip->write_mode_25 = (bus & 0x100) == 0 && (businv & 0x25) == 0; 406 | chip->write_mode_24 = (bus & 0x100) == 0 && (businv & 0x24) == 0; 407 | chip->write_mode_21 = (bus & 0x100) == 0 && (businv & 0x21) == 0; 408 | chip->write_mode_28 = (bus & 0x100) == 0 && (businv & 0x28) == 0; 409 | chip->write_mode_26 = (bus & 0x100) == 0 && (businv & 0x26) == 0; 410 | chip->write_mode_22 = (bus & 0x100) == 0 && (businv & 0x22) == 0; 411 | chip->write_mode_02 = (bus & 0x100) == 0 && (businv & 0x02) == 0; 412 | } 413 | else 414 | { 415 | chip->write_mode_1c = bus == 0x1c; 416 | chip->write_mode_27 = bus == 0x27; 417 | chip->write_mode_25 = bus == 0x25; 418 | chip->write_mode_24 = bus == 0x24; 419 | chip->write_mode_21 = bus == 0x21; 420 | chip->write_mode_28 = bus == 0x28; 421 | chip->write_mode_26 = bus == 0x26; 422 | chip->write_mode_22 = bus == 0x22; 423 | chip->write_mode_02 = bus == 0x02; 424 | } 425 | } 426 | if (chip->slot_counter_l & 2) 427 | { 428 | chip->slot_counter_h = (chip->slot_counter_h + 1) & 3; 429 | chip->slot_counter_l = 0; 430 | } 431 | else 432 | { 433 | chip->slot_counter_l++; 434 | } 435 | if (chip->fmcycles[22] & 2) 436 | { 437 | chip->slot_counter_h = 0; 438 | chip->slot_counter_l = 0; 439 | } 440 | if (chip->ic) 441 | { 442 | chip->mode_1c = 0; 443 | chip->mode_ch3 = 0; 444 | chip->mode_csm = 0; 445 | chip->timer_a_load = 0; 446 | chip->timer_a_enable = 0; 447 | chip->timer_a_reset = 0; 448 | chip->timer_b_load = 0; 449 | chip->timer_b_enable = 0; 450 | chip->timer_b_reset = 0; 451 | chip->timer_a_reg = 0; 452 | chip->mode_test = 0; 453 | chip->mode_kon_operator[0] = 0; 454 | chip->mode_kon_operator[1] = 0; 455 | chip->mode_kon_operator[2] = 0; 456 | chip->mode_kon_operator[3] = 0; 457 | chip->mode_kon_channel = 0; 458 | chip->timer_b_reg = 0; 459 | chip->lfo_en = 0; 460 | chip->lfo_freq = 0; 461 | chip->mode_test2 = 0; 462 | chip->fm_address = 0; 463 | chip->fm_data = 0; 464 | chip->slot_counter_h = 0; 465 | chip->slot_counter_l = 0; 466 | slot = chip->fmcycles % 12; 467 | channel = chip->fmcycles % 6; 468 | chip->fm_reg_a4 = 0; 469 | chip->fm_reg_ac = 0; 470 | chip->fm_fnum[channel] = 0; 471 | chip->fm_block[channel] = 0; 472 | chip->fm_fnum_3ch[channel] = 0; 473 | chip->fm_block_3ch[channel] = 0; 474 | chip->fm_connect[channel] = 0; 475 | chip->fm_fb[channel] = 0; 476 | chip->fm_pms[channel] = 0; 477 | chip->fm_ams[channel] = 0; 478 | chip->fm_pan_l[channel] = 1; 479 | chip->fm_pan_r[channel] = 1; 480 | chip->fm_ssg_eg[0][slot] = 0; 481 | chip->fm_ssg_eg[1][slot] = 0; 482 | chip->fm_dt[0][slot] = 0; 483 | chip->fm_dt[1][slot] = 0; 484 | chip->fm_multi[0][slot] = 0; 485 | chip->fm_multi[1][slot] = 0; 486 | chip->fm_tl[0][slot] = 0; 487 | chip->fm_tl[1][slot] = 0; 488 | chip->fm_ks[0][slot] = 0; 489 | chip->fm_ks[1][slot] = 0; 490 | chip->fm_ar[0][slot] = 0; 491 | chip->fm_ar[1][slot] = 0; 492 | chip->fm_am[0][slot] = 0; 493 | chip->fm_am[1][slot] = 0; 494 | chip->fm_dr[0][slot] = 0; 495 | chip->fm_dr[1][slot] = 0; 496 | chip->fm_sr[0][slot] = 0; 497 | chip->fm_sr[1][slot] = 0; 498 | chip->fm_rr[0][slot] = 0; 499 | chip->fm_rr[1][slot] = 0; 500 | chip->fm_sl[0][slot] = 0; 501 | chip->fm_sl[1][slot] = 0; 502 | } 503 | } 504 | 505 | static void OPNB_FMCounter1(opnb_t *chip) 506 | { 507 | if (chip->fmstate_l & 2) 508 | { 509 | chip->fmstate_h = (chip->fmstate_h + 1) & 7; 510 | chip->fmstate_l = 0; 511 | } 512 | else 513 | { 514 | chip->fmstate_l++; 515 | } 516 | if (chip->ic2 & 8) 517 | { 518 | chip->fmstate_h = 0; 519 | chip->fmstate_l = 0; 520 | } 521 | } 522 | 523 | static void OPNB_FMCounter2(opnb_t* chip) 524 | { 525 | chip->fmcycle[22] <<= 1; 526 | chip->fmcycle[22] |= chip->fmstate_h == 7 && chip->fmstate_l == 1; 527 | } 528 | 529 | static void OPNB_FMClock1(opnb_t *chip) 530 | { 531 | chip->ic_latch |= chip->ic; 532 | OPNB_FMDoIO1(chip); 533 | OPNB_DoRegWrite(chip); 534 | OPNB_FMCounter1(chip); 535 | } 536 | 537 | static void OPNB_FMClock2(opnb_t *chip) 538 | { 539 | chip->ic_latch <<= 1; 540 | OPNB_FMDoIO2(chip); 541 | chip->fmcycles = (chip->fmcycles + 1) % 24; 542 | 543 | } 544 | 545 | static uint8_t OPNB_ReadBus(opnb_t *chip, uint32_t ssgread) 546 | { 547 | if (chip->ic_latch & 2) 548 | { 549 | return 0; 550 | } 551 | if (ssgread) 552 | { 553 | return 0; // TODO: 554 | } 555 | return chip->write_data & 255; 556 | } 557 | 558 | void OPNB_Clock(opnb_t *chip) 559 | { 560 | uint32_t cycle; 561 | if (chip->ic) 562 | { 563 | chip->write_data = 0; 564 | } 565 | for (cycle = 0; cycle < 12; cycle++) 566 | { 567 | if (chip->cycles & (1 << cycle)) 568 | { 569 | // FM clock 570 | switch (cycle % 6) 571 | { 572 | case 2: // rising 573 | case 3: 574 | if (!(chip->clock_state & clock_fm_1)) 575 | { 576 | OPNB_FMClock1(chip); 577 | chip->clock_state |= clock_fm_1; 578 | } 579 | break; 580 | case 4: // falling 581 | chip->clock_state &= ~clock_fm_1; 582 | break; 583 | case 0: // rising 584 | case 5: 585 | case 3: 586 | if (!(chip->clock_state & clock_fm_2)) 587 | { 588 | OPNB_FMClock2(chip); 589 | chip->clock_state |= clock_fm_2; 590 | } 591 | break; 592 | case 1: // falling 593 | chip->clock_state &= ~clock_fm_2; 594 | break; 595 | default: 596 | break; 597 | } 598 | } 599 | } 600 | 601 | // Cycle one-hot 602 | chip->cycles <<= 1; 603 | if ((chip->cycles & 0xffe) == 0) 604 | { 605 | chip->cycles |= 1; 606 | } 607 | chip->ic2 <<= 1; 608 | if ((chip->ic_sr & 1) && !(chip->ic_sr & (1<<18))) 609 | { 610 | chip->cycles &= ~1; 611 | chip->ic2 |= 1; 612 | } 613 | chip->ic_sr <<= 1; 614 | chip->ic_sr |= chip->ic; 615 | } 616 | 617 | void OPNB_Write(opnb_t *chip, uint32_t port, uint8_t data) 618 | { 619 | port &= 3; 620 | chip->write_data = ((port << 7) & 0x100) | data; 621 | if (port & 1) 622 | { 623 | if (!(chip->write_d & 4)) 624 | { 625 | chip->write_d |= 1; 626 | } 627 | } 628 | else 629 | { 630 | if (!(chip->write_a & 4)) 631 | { 632 | chip->write_a |= 1; 633 | } 634 | } 635 | } 636 | 637 | uint8_t OPNB_Read(opnb_t *chip, uint32_t port) 638 | { 639 | uint8_t ret = 0; 640 | switch (port & 3) 641 | { 642 | case 1: 643 | ret = OPNB_ReadBus(chip, 1); 644 | break; 645 | default: 646 | break; 647 | } 648 | return ret; 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