├── README.md ├── fmopn.h ├── LICENSE └── fmopn.c /README.md: -------------------------------------------------------------------------------- 1 | # YM2203-LLE 2 | 3 | Very low-level Yamaha YM2203C(OPN) emulator using die shot. 4 | 5 | Special thanks to John McMaster for decapping YM2203C. 6 | 7 | https://siliconpr0n.org/map/yamaha/ym2203c/ 8 | -------------------------------------------------------------------------------- /fmopn.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2025 nukeykt 3 | * 4 | * This file is part of YM2203-LLE. 5 | * 6 | * This program is free software; you can redistribute it and/or 7 | * modify it under the terms of the GNU General Public License 8 | * as published by the Free Software Foundation; either version 2 9 | * of the License, or (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * YM2203 emulator. 17 | * Thanks: 18 | * John McMaster (siliconpr0n.org): 19 | * YM2203 decap 20 | * 21 | */ 22 | #pragma once 23 | 24 | typedef struct { 25 | int clk; 26 | int ic; // neg 27 | int cs; // neg 28 | int wr; // neg 29 | int rd; // neg 30 | int a0; 31 | int data; 32 | int gpio_a; 33 | int gpio_b; 34 | } fmopn_input_t; 35 | 36 | typedef struct { 37 | fmopn_input_t input; 38 | 39 | int mclk1; 40 | int mclk2; 41 | int clk1; 42 | int clk2; 43 | int aclk1; 44 | int aclk2; 45 | 46 | int o_clk1; 47 | int o_clk2; 48 | int o_aclk1; 49 | int o_aclk2; 50 | 51 | 52 | int data_l; 53 | int data_bus1; 54 | int data_bus2; 55 | 56 | int write0_trig; 57 | int write0_l[6]; 58 | int write1_trig; 59 | int write1_l[6]; 60 | int writep_trig; 61 | int writep_l[3]; 62 | 63 | int ps1[2]; 64 | int ps1_l0; 65 | int ps1_l1; 66 | int ps2[2]; 67 | 68 | int ic_latch[2]; 69 | 70 | int prescaler_sel[2]; 71 | 72 | int write_fm_address[2]; 73 | int write_fm_data[2]; 74 | 75 | int fm_address[2]; 76 | int fm_data[2]; 77 | 78 | int reg_cnt1[2]; 79 | int reg_cnt2[2]; 80 | 81 | int reg_key_cnt1[2]; 82 | int reg_key_cnt2[2]; 83 | 84 | int reg_test_21[2]; 85 | int reg_timer_a[2]; 86 | int reg_timer_b[2]; 87 | int reg_ch3[2]; 88 | int reg_timer_a_load[2]; 89 | int reg_timer_b_load[2]; 90 | int reg_timer_a_enable[2]; 91 | int reg_timer_b_enable[2]; 92 | int reg_timer_a_reset[2]; 93 | int reg_timer_b_reset[2]; 94 | int reg_kon_operator[2]; 95 | int reg_kon_channel[2]; 96 | int reg_kon_match; 97 | int reg_ch3_sel; 98 | 99 | int timer_a_status[2]; 100 | int timer_b_status[2]; 101 | int timer_a_cnt[2]; 102 | int timer_a_of[2]; 103 | int timer_a_load; 104 | int timer_a_reg_load; 105 | int reg_sync_timer_load; 106 | int reg_sync_timer_l[2]; 107 | int reg_sync_timer; 108 | int timer_a_reg_load_l[2]; 109 | int timer_b_subcnt[2]; 110 | int timer_b_subcnt_of[2]; 111 | int timer_b_cnt[2]; 112 | int timer_b_reg_load; 113 | int timer_b_load; 114 | int timer_b_of[2]; 115 | int timer_b_reg_load_l[2]; 116 | 117 | int ch3_en; 118 | int ch3_csm; 119 | int ch3_csm_load; 120 | 121 | int addr_21[2]; 122 | int addr_24[2]; 123 | int addr_25[2]; 124 | int addr_26[2]; 125 | int addr_27[2]; 126 | int addr_28[2]; 127 | 128 | int reg_kon[4][2]; 129 | 130 | int fm_is30; 131 | int fm_is40; 132 | int fm_is50; 133 | int fm_is60; 134 | int fm_is70; 135 | int fm_is80; 136 | int fm_is90; 137 | int fm_isa0; 138 | int fm_isa4; 139 | int fm_isa8; 140 | int fm_isac; 141 | int fm_isb0; 142 | 143 | int reg_cnt_sync; 144 | 145 | int busy_cnt[2]; 146 | int busy_cnt_en[2]; 147 | 148 | int fsm_cnt1[2]; 149 | int fsm_cnt2[2]; 150 | int fsm_out[14]; 151 | int fsm_sh; 152 | int fsm_sh_l[2]; 153 | int fsm_sel_11[2]; 154 | int fsm_acc_sync[2]; 155 | int fsm_ch3_sync[2]; 156 | 157 | int fsm_op1_sel_l; 158 | int fsm_op2_sel_l; 159 | int fsm_op3_sel_l; 160 | int fsm_op4_sel_l; 161 | int fsm_connect; 162 | int alg_mod_op1_0_l; 163 | int alg_mod_op1_1_l; 164 | int alg_mod_op2_l; 165 | int alg_mod_prev_0_l; 166 | int alg_mod_prev_1_l; 167 | int alg_output_l; 168 | int alg_do_fb[2]; 169 | int alg_load_fb; 170 | 171 | unsigned short reg_freq[2][3]; 172 | unsigned short reg_freq_3ch[2][3]; 173 | unsigned char reg_connect_fb[2][3]; 174 | unsigned char op_multi_dt[2][12]; 175 | unsigned char op_tl[2][12]; 176 | unsigned char op_ar_ks[2][12]; 177 | unsigned char op_dr_a[2][12]; 178 | unsigned char op_sr[2][12]; 179 | unsigned char op_rr_sl[2][12]; 180 | unsigned char op_ssg[2][12]; 181 | int reg_a4[2]; 182 | int reg_ac[2]; 183 | 184 | int ch3_sel[2]; 185 | 186 | int fnum[5]; 187 | int kcode[4]; 188 | 189 | int pg_block; 190 | int pg_freq; 191 | int pg_dt_multi; 192 | int pg_dt_add; 193 | int pg_freqdt[2]; 194 | int pg_multi[5]; 195 | int pg_add[6]; 196 | int pg_reset[4]; 197 | int pg_phase[2][11]; 198 | int pg_phase2[2]; 199 | int pg_out; 200 | int pg_dbgsync; 201 | int pg_dbg[2]; 202 | int dt_add1; 203 | int dt_add2; 204 | int dt_enable[2]; 205 | int dt_sum; 206 | int dt_blockmax[2]; 207 | int dt_note[2]; 208 | int dt_sign[2]; 209 | 210 | int eg_sync; 211 | int eg_prescaler[2]; 212 | int eg_prescaler_clock_l[2]; 213 | int eg_ic[2]; 214 | 215 | int eg_step[3]; 216 | int eg_timer_step[2]; 217 | 218 | int eg_timer[2]; 219 | int eg_timer_sum[2]; 220 | int eg_timer_carry[2]; 221 | int eg_timer_mask[2]; 222 | int eg_timer_masked[2]; 223 | int eg_timer_low_lock; 224 | int eg_shift_lock; 225 | 226 | int eg_rate_sel; 227 | int eg_rate_ar; 228 | int eg_rate_dr; 229 | int eg_rate_sr; 230 | int eg_rate_rr; 231 | int eg_rate; 232 | int eg_rate_nonzero[3]; 233 | unsigned char eg_state[2][11]; 234 | int eg_ks; 235 | int eg_ksv; 236 | int eg_rate2; 237 | int eg_ratenz; 238 | int eg_rate12; 239 | int eg_rate13; 240 | int eg_rate14; 241 | int eg_rate15; 242 | int eg_rate_low; 243 | int eg_rate_slow; 244 | int eg_rate_sum; 245 | int eg_maxrate[2]; 246 | int eg_inc2; 247 | int eg_incsh0[2]; 248 | int eg_incsh1[2]; 249 | int eg_incsh2[2]; 250 | int eg_incsh3[2]; 251 | int eg_output; 252 | unsigned short eg_level[2][10]; 253 | int eg_ssg_inv; 254 | int eg_ssg_enable[2]; 255 | int eg_ssg_sign[2]; 256 | int eg_ssg_holdup[2]; 257 | int eg_ssg_pgreset[2]; 258 | int eg_ssg_dir[2]; 259 | int eg_ssg_egrepeat[2]; 260 | int eg_key[2]; 261 | int eg_kon_latch[2]; 262 | int eg_kon_event; 263 | int eg_pg_reset[2]; 264 | int eg_sl[2][2]; 265 | int eg_tl[3][2]; 266 | int eg_level_ssg[2]; 267 | int eg_slreach; 268 | int eg_level_l[2]; 269 | int eg_zeroreach; 270 | int eg_off; 271 | int eg_nextstate; 272 | int eg_state_l; 273 | int eg_mute; 274 | int eg_exp; 275 | int eg_linear; 276 | int eg_inc_total; 277 | int eg_nextlevel[2]; 278 | int eg_istantattack; 279 | int eg_kon_csm[2]; 280 | int eg_output2; 281 | int eg_csm_tl; 282 | int eg_ch3_l[2]; 283 | int eg_out; 284 | int eg_dbg_sync; 285 | int eg_debug[2]; 286 | 287 | int op_phase1; 288 | int op_phase2; 289 | int op_phase_index; 290 | int op_sign[2]; 291 | int op_logsin_base; 292 | int op_logsin_delta; 293 | int op_eglevel; 294 | int op_att; 295 | int op_shift[2]; 296 | int op_pow_base; 297 | int op_pow_delta; 298 | int op_pow; 299 | int op_output[4]; 300 | unsigned short op_op1_0[2][3]; 301 | unsigned short op_op1_1[2][3]; 302 | unsigned short op_op2[2][3]; 303 | int op_loadfb; 304 | int op_loadop2; 305 | int op_mod_op1_0; 306 | int op_mod_op1_1; 307 | int op_mod_op2; 308 | int op_mod_prev_0; 309 | int op_mod_prev_1; 310 | int op_mod1; 311 | int op_mod2; 312 | int op_mod_sum; 313 | int op_do_fb; 314 | int op_fb; 315 | 316 | int ssg_prescaler1[2]; 317 | int ssg_prescaler2[2]; 318 | int ssg_div1[2]; 319 | int ssg_div2[2]; 320 | int ssg_clk; 321 | int ssg_clk1; 322 | int ssg_clk2; 323 | int ssg_ssg_addr; 324 | int ssg_address; 325 | int ssg_freq_a[2]; 326 | int ssg_freq_b[2]; 327 | int ssg_freq_c[2]; 328 | int ssg_noise; 329 | int ssg_mode; 330 | int ssg_level_a; 331 | int ssg_level_b; 332 | int ssg_level_c; 333 | int ssg_env[2]; 334 | int ssg_envmode; 335 | int ssg_envadd; 336 | int ssg_envcnt[2]; 337 | int ssg_dir[2]; 338 | int ssg_hold[2]; 339 | int ssg_t2[2]; 340 | int ssg_egtrig; 341 | int ssg_egtrig_s; 342 | int ssg_egtrig_rst; 343 | int ssg_eg_sel_l; 344 | int ssg_sel[2]; 345 | int ssg_sel_freq; 346 | int ssg_freq_cnt[8]; 347 | int ssg_cnt_of[2]; 348 | int ssg_sign[2]; 349 | int ssg_sign_toggle; 350 | int ssg_cnt_of_l; 351 | int ssg_freq_cnt2[8]; 352 | int ssg_sel_freq_l; 353 | int ssg_cnt2_add; 354 | int ssg_sel_eg_l[2]; 355 | int ssg_ch_of; 356 | int ssg_cnt_reload; 357 | int ssg_eg_of[2]; 358 | int ssg_fr_rst_l; 359 | int ssg_noise_add; 360 | int ssg_noise_cnt[2]; 361 | int ssg_noise_of_low; 362 | int ssg_noise_of; 363 | int ssg_noise_step; 364 | int ssg_noise_lfsr[2]; 365 | int ssg_noise_bit; 366 | 367 | 368 | int ac_fm_output; 369 | int ac_accum[2]; 370 | int ac_accum_l; 371 | int ac_shifter1[2]; 372 | int ac_sync[2]; 373 | int ac_sync2[2]; 374 | int ac_clip_h; 375 | int ac_clip_l; 376 | int ac_shifter2[2]; 377 | int ac_hi_bits; 378 | int ac_exp; 379 | int ac_sign; 380 | int ac_out[2]; 381 | int ac_load2_l; 382 | 383 | int read_test; 384 | int read_op; 385 | 386 | int read_data; 387 | 388 | int o_sh; 389 | int o_opo; 390 | int o_sy; 391 | float o_analog_a; 392 | float o_analog_b; 393 | float o_analog_c; 394 | int o_gpio_a_d; 395 | int o_gpio_a; 396 | int o_gpio_b_d; 397 | int o_gpio_b; 398 | int o_data; 399 | int o_irq_pull; 400 | 401 | 402 | short dbg_out; 403 | } fmopn_t; 404 | 405 | void FMOPN_Clock(fmopn_t* chip, int clk); 406 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 2, June 1991 3 | 4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc., 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | Preamble 10 | 11 | The licenses for most software are designed to take away your 12 | freedom to share and change it. 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See the 304 | GNU General Public License for more details. 305 | 306 | You should have received a copy of the GNU General Public License along 307 | with this program; if not, write to the Free Software Foundation, Inc., 308 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 309 | 310 | Also add information on how to contact you by electronic and paper mail. 311 | 312 | If the program is interactive, make it output a short notice like this 313 | when it starts in an interactive mode: 314 | 315 | Gnomovision version 69, Copyright (C) year name of author 316 | Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 317 | This is free software, and you are welcome to redistribute it 318 | under certain conditions; type `show c' for details. 319 | 320 | The hypothetical commands `show w' and `show c' should show the appropriate 321 | parts of the General Public License. Of course, the commands you use may 322 | be called something other than `show w' and `show c'; they could even be 323 | mouse-clicks or menu items--whatever suits your program. 324 | 325 | You should also get your employer (if you work as a programmer) or your 326 | school, if any, to sign a "copyright disclaimer" for the program, if 327 | necessary. Here is a sample; alter the names: 328 | 329 | Yoyodyne, Inc., hereby disclaims all copyright interest in the program 330 | `Gnomovision' (which makes passes at compilers) written by James Hacker. 331 | 332 | , 1 April 1989 333 | Ty Coon, President of Vice 334 | 335 | This General Public License does not permit incorporating your program into 336 | proprietary programs. If your program is a subroutine library, you may 337 | consider it more useful to permit linking proprietary applications with the 338 | library. If this is what you want to do, use the GNU Lesser General 339 | Public License instead of this License. 340 | -------------------------------------------------------------------------------- /fmopn.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2025 nukeykt 3 | * 4 | * This file is part of YM2203-LLE. 5 | * 6 | * This program is free software; you can redistribute it and/or 7 | * modify it under the terms of the GNU General Public License 8 | * as published by the Free Software Foundation; either version 2 9 | * of the License, or (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * YM2203 emulator. 17 | * Thanks: 18 | * John McMaster (siliconpr0n.org): 19 | * YM2203 decap 20 | * 21 | */ 22 | #include 23 | #include "fmopn.h" 24 | 25 | enum { 26 | eg_state_attack = 0, 27 | eg_state_decay, 28 | eg_state_sustain, 29 | eg_state_release 30 | }; 31 | 32 | static const int fm_algorithm[4][6][8] = { 33 | { 34 | { 1, 1, 1, 1, 1, 1, 1, 1 }, /* OP1_0 */ 35 | { 1, 1, 1, 1, 1, 1, 1, 1 }, /* OP1_1 */ 36 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP2 */ 37 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */ 38 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */ 39 | { 0, 0, 0, 0, 0, 0, 0, 1 } /* Out */ 40 | }, 41 | { 42 | { 0, 1, 0, 0, 0, 1, 0, 0 }, /* OP1_0 */ 43 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_1 */ 44 | { 1, 1, 1, 0, 0, 0, 0, 0 }, /* OP2 */ 45 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */ 46 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */ 47 | { 0, 0, 0, 0, 0, 1, 1, 1 } /* Out */ 48 | }, 49 | { 50 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_0 */ 51 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_1 */ 52 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP2 */ 53 | { 1, 0, 0, 1, 1, 1, 1, 0 }, /* Last operator */ 54 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */ 55 | { 0, 0, 0, 0, 1, 1, 1, 1 } /* Out */ 56 | }, 57 | { 58 | { 0, 0, 1, 0, 0, 1, 0, 0 }, /* OP1_0 */ 59 | { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_1 */ 60 | { 0, 0, 0, 1, 0, 0, 0, 0 }, /* OP2 */ 61 | { 1, 1, 0, 1, 1, 0, 0, 0 }, /* Last operator */ 62 | { 0, 0, 1, 0, 0, 0, 0, 0 }, /* Last operator */ 63 | { 1, 1, 1, 1, 1, 1, 1, 1 } /* Out */ 64 | } 65 | }; 66 | 67 | 68 | void FMOPN_Clock(fmopn_t* chip, int clk) 69 | { 70 | int i; 71 | 72 | chip->input.clk = clk; 73 | 74 | int ic = !chip->input.ic; 75 | 76 | chip->mclk1 = !chip->input.clk; 77 | chip->mclk2 = chip->input.clk; 78 | 79 | if (chip->mclk1) 80 | { 81 | chip->ic_latch[0] = (chip->ic_latch[1] & 63) << 1; 82 | chip->ic_latch[0] |= ic; 83 | } 84 | else 85 | chip->ic_latch[1] = chip->ic_latch[0]; 86 | 87 | int ic2 = (chip->ic_latch[0] & 64) == 0 && (chip->ic_latch[0] & 1) != 0; 88 | 89 | if (chip->mclk1) 90 | { 91 | chip->ps1[0] = (chip->ps1[1] & 3) << 1; 92 | if (!ic2 && (chip->ps1[1] & 3) == 0) 93 | chip->ps1[0] |= 1; 94 | chip->ps1_l0 = chip->ps1[1] & 1; 95 | chip->ps1_l1 = (chip->ps1[1] >> 1) & 1; 96 | } 97 | else 98 | { 99 | chip->ps1[1] = chip->ps1[0]; 100 | } 101 | 102 | if ((chip->prescaler_sel[1] & 2) == 0) // div 2 103 | { 104 | chip->aclk1 = !chip->mclk1; 105 | chip->aclk2 = !chip->mclk2; 106 | } 107 | else if ((chip->prescaler_sel[1] & 1) == 0) // div 6 108 | { 109 | chip->aclk1 = (chip->ps1[1] >> 2) & 1; 110 | chip->aclk2 = chip->ps1[1] & 1; 111 | } 112 | else // div 3 113 | { 114 | chip->aclk1 = (chip->mclk1 && (chip->ps1[1] & 4) != 0) || (!chip->ps1_l1 && (chip->ps1[1] & 2) != 0); 115 | chip->aclk2 = (chip->mclk1 && (chip->ps1[1] & 1) != 0) || (!chip->ps1_l0 && (chip->ps1[1] & 1) != 0); 116 | } 117 | 118 | chip->o_sy = chip->aclk2; 119 | 120 | if (ic2) 121 | { 122 | chip->ps2[0] = 0; 123 | chip->ps2[1] = 0; 124 | } 125 | else 126 | { 127 | if (chip->aclk1) 128 | { 129 | chip->ps2[0] = !chip->ps2[1]; 130 | } 131 | if (chip->aclk2) 132 | { 133 | chip->ps2[1] = chip->ps2[0]; 134 | } 135 | } 136 | 137 | chip->clk1 = chip->ps2[0]; 138 | chip->clk2 = !chip->ps2[0]; 139 | 140 | 141 | int write_0_en; 142 | int write_1_en; 143 | int write_p_en; 144 | int read0; 145 | int read1; 146 | int write_addr; 147 | int write_data; 148 | int read; 149 | { 150 | int write = !chip->input.wr && !chip->input.cs; 151 | read0 = !ic && !chip->input.rd && !chip->input.cs && !chip->input.a0; 152 | read1 = !ic && !chip->input.rd && !chip->input.cs && chip->input.a0; 153 | write_addr = ic || (!chip->input.wr && !chip->input.cs && !chip->input.a0); 154 | write_data = !ic && !chip->input.wr && !chip->input.cs && chip->input.a0; 155 | read = !ic && !chip->input.rd && !chip->input.cs; 156 | 157 | if (write) 158 | chip->data_l = chip->input.data; 159 | 160 | if (!read1 && !ic) 161 | { 162 | chip->data_bus1 = chip->data_l; 163 | chip->data_bus2 = chip->data_l ^ 255; 164 | } 165 | else 166 | { 167 | chip->data_l &= ~32; // FIXME 168 | } 169 | 170 | if (ic) 171 | { 172 | chip->data_bus1 = 0; 173 | chip->data_bus2 = 255; 174 | } 175 | 176 | if (chip->write0_l[5]) 177 | chip->write0_trig = 0; 178 | else if (write_addr) 179 | chip->write0_trig = 1; 180 | 181 | if (chip->mclk2) 182 | chip->write0_l[0] = chip->write0_trig; 183 | else if (chip->mclk1) 184 | chip->write0_l[0] = chip->write0_l[0]; 185 | 186 | if (chip->mclk1) 187 | chip->write0_l[1] = chip->write0_l[0]; 188 | if (chip->mclk2) 189 | chip->write0_l[2] = chip->write0_l[1]; 190 | 191 | if (chip->clk2) 192 | chip->write0_l[3] = chip->write0_l[2]; 193 | else if (chip->clk1) 194 | chip->write0_l[3] = chip->write0_l[3]; 195 | 196 | if (chip->clk1) 197 | chip->write0_l[4] = chip->write0_l[3]; 198 | if (chip->clk2) 199 | chip->write0_l[5] = chip->write0_l[4]; 200 | 201 | if (chip->write1_l[5]) 202 | chip->write1_trig = 0; 203 | else if (write_data) 204 | chip->write1_trig = 1; 205 | 206 | if (chip->mclk2) 207 | chip->write1_l[0] = chip->write1_trig; 208 | else if (chip->mclk1) 209 | chip->write1_l[0] = chip->write1_l[0]; 210 | 211 | if (chip->mclk1) 212 | chip->write1_l[1] = chip->write1_l[0]; 213 | if (chip->mclk2) 214 | chip->write1_l[2] = chip->write1_l[1]; 215 | 216 | if (chip->clk2) 217 | chip->write1_l[3] = chip->write1_l[2]; 218 | else if (chip->clk1) 219 | chip->write1_l[3] = chip->write1_l[3]; 220 | 221 | if (chip->clk1) 222 | chip->write1_l[4] = chip->write1_l[3]; 223 | if (chip->clk2) 224 | chip->write1_l[5] = chip->write1_l[4]; 225 | 226 | if (chip->writep_l[2]) 227 | chip->writep_trig = 0; 228 | else if (write_addr) 229 | chip->writep_trig = 1; 230 | 231 | if (chip->mclk2) 232 | chip->writep_l[0] = chip->writep_trig; 233 | else if (chip->mclk1) 234 | chip->writep_l[0] = chip->writep_l[0]; 235 | 236 | if (chip->mclk1) 237 | chip->writep_l[1] = chip->writep_l[0]; 238 | if (chip->mclk2) 239 | chip->writep_l[2] = chip->writep_l[1]; 240 | 241 | #define ADDRESS_MATCH(x) ((chip->data_bus2 & x) == 0 && (chip->data_bus1 & (x^255)) == 0) 242 | 243 | write_0_en = chip->write0_l[5]; 244 | write_1_en = chip->write1_l[5]; 245 | write_p_en = chip->writep_l[2]; 246 | 247 | if (chip->mclk1) 248 | { 249 | int addr2d = write_p_en && ADDRESS_MATCH(0x2d); 250 | int addr2e = write_p_en && ADDRESS_MATCH(0x2e); 251 | int addr2f = write_p_en && ADDRESS_MATCH(0x2f); 252 | chip->prescaler_sel[0] = chip->prescaler_sel[1]; 253 | if (addr2f) 254 | chip->prescaler_sel[0] = 0; 255 | if (addr2d || ic) 256 | chip->prescaler_sel[0] |= 2; 257 | if (addr2e) 258 | chip->prescaler_sel[0] |= 1; 259 | } 260 | if (chip->mclk2) 261 | { 262 | chip->prescaler_sel[1] = chip->prescaler_sel[0]; 263 | if (ic) 264 | chip->prescaler_sel[1] &= ~1; 265 | } 266 | } 267 | 268 | #if 1 269 | if (chip->o_clk1 == chip->clk1 270 | && chip->o_clk2 == chip->clk2 271 | && chip->o_aclk1 == chip->aclk1 272 | && chip->o_aclk2 == chip->aclk2) 273 | return; 274 | 275 | chip->o_clk1 = chip->clk1; 276 | chip->o_clk2 = chip->clk2; 277 | chip->o_aclk1 = chip->aclk1; 278 | chip->o_aclk2 = chip->aclk2; 279 | 280 | if (!chip->aclk1 && !chip->aclk2) 281 | return; 282 | #endif 283 | 284 | { 285 | if (chip->clk1) 286 | { 287 | int is_fm = (chip->data_bus1 & 0xe0) != 0; 288 | 289 | chip->write_fm_address[0] = write_0_en ? is_fm : chip->write_fm_address[1]; 290 | 291 | if (ic) 292 | chip->fm_address[0] = 0; 293 | else if (is_fm && write_0_en) 294 | chip->fm_address[0] = chip->data_bus1; 295 | else 296 | chip->fm_address[0] = chip->fm_address[1]; 297 | 298 | if (ic) 299 | chip->fm_data[0] = 0; 300 | else if (chip->write_fm_address[1] && write_1_en) 301 | chip->fm_data[0] = chip->data_bus1 & 255; 302 | else 303 | chip->fm_data[0] = chip->fm_data[1]; 304 | 305 | chip->write_fm_data[0] = (chip->write_fm_address[1] && write_1_en) || (chip->write_fm_data[1] && !write_0_en); 306 | 307 | chip->addr_21[0] = write_0_en ? ADDRESS_MATCH(0x21) : chip->addr_21[1]; 308 | chip->addr_24[0] = write_0_en ? ADDRESS_MATCH(0x24) : chip->addr_24[1]; 309 | chip->addr_25[0] = write_0_en ? ADDRESS_MATCH(0x25) : chip->addr_25[1]; 310 | chip->addr_26[0] = write_0_en ? ADDRESS_MATCH(0x26) : chip->addr_26[1]; 311 | chip->addr_27[0] = write_0_en ? ADDRESS_MATCH(0x27) : chip->addr_27[1]; 312 | chip->addr_28[0] = write_0_en ? ADDRESS_MATCH(0x28) : chip->addr_28[1]; 313 | 314 | if (ic) 315 | { 316 | chip->reg_test_21[0] = 0; 317 | chip->reg_timer_a[0] = 0; 318 | chip->reg_timer_b[0] = 0; 319 | chip->reg_ch3[0] = 0; 320 | chip->reg_timer_a_load[0] = 0; 321 | chip->reg_timer_b_load[0] = 0; 322 | chip->reg_timer_a_enable[0] = 0; 323 | chip->reg_timer_b_enable[0] = 0; 324 | chip->reg_kon_operator[0] = 0; 325 | chip->reg_kon_channel[0] = 0; 326 | } 327 | else 328 | { 329 | if (chip->addr_21[1] && write_1_en) 330 | { 331 | chip->reg_test_21[0] = chip->data_bus1 & 0xde; 332 | } 333 | else 334 | { 335 | chip->reg_test_21[0] = chip->reg_test_21[1]; 336 | } 337 | chip->reg_timer_a[0] = 0; 338 | if (chip->addr_24[1] && write_1_en) 339 | { 340 | chip->reg_timer_a[0] |= (chip->data_bus1 & 255) << 2; 341 | } 342 | else 343 | { 344 | chip->reg_timer_a[0] |= chip->reg_timer_a[1] & 0x3fc; 345 | } 346 | if (chip->addr_25[1] && write_1_en) 347 | { 348 | chip->reg_timer_a[0] |= chip->data_bus1 & 3; 349 | } 350 | else 351 | { 352 | chip->reg_timer_a[0] |= chip->reg_timer_a[1] & 3; 353 | } 354 | if (chip->addr_26[1] && write_1_en) 355 | { 356 | chip->reg_timer_b[0] = chip->data_bus1 & 255; 357 | } 358 | else 359 | { 360 | chip->reg_timer_b[0] = chip->reg_timer_b[1]; 361 | } 362 | if (chip->addr_27[1] && write_1_en) 363 | { 364 | chip->reg_ch3[0] = (chip->data_bus1 >> 6) & 3; 365 | chip->reg_timer_a_load[0] = (chip->data_bus1 >> 0) & 1; 366 | chip->reg_timer_b_load[0] = (chip->data_bus1 >> 1) & 1; 367 | chip->reg_timer_a_enable[0] = (chip->data_bus1 >> 2) & 1; 368 | chip->reg_timer_b_enable[0] = (chip->data_bus1 >> 3) & 1; 369 | } 370 | else 371 | { 372 | chip->reg_ch3[0] = chip->reg_ch3[1]; 373 | chip->reg_timer_a_load[0] = chip->reg_timer_a_load[1]; 374 | chip->reg_timer_b_load[0] = chip->reg_timer_b_load[1]; 375 | chip->reg_timer_a_enable[0] = chip->reg_timer_a_enable[1]; 376 | chip->reg_timer_b_enable[0] = chip->reg_timer_b_enable[1]; 377 | } 378 | if (chip->addr_28[1] && write_1_en) 379 | { 380 | chip->reg_kon_operator[0] = (chip->data_bus1 >> 4) & 15; 381 | chip->reg_kon_channel[0] = (chip->data_bus1 >> 0) & 3; 382 | } 383 | else 384 | { 385 | chip->reg_kon_operator[0] = chip->reg_kon_operator[1]; 386 | chip->reg_kon_channel[0] = chip->reg_kon_channel[1]; 387 | } 388 | } 389 | chip->reg_timer_a_reset[0] = chip->addr_27[1] && write_1_en && ((chip->data_bus1 >> 4) & 1) != 0; 390 | chip->reg_timer_b_reset[0] = chip->addr_27[1] && write_1_en && ((chip->data_bus1 >> 5) & 1) != 0; 391 | 392 | int rst1 = chip->reg_cnt_sync; 393 | int of = (chip->reg_cnt1[1] & 2) != 0; 394 | 395 | chip->reg_cnt1[0] = (rst1 || of) ? 0 : ((chip->reg_cnt1[1] + 1) & 3); 396 | chip->reg_cnt2[0] = rst1 ? 0 : ((chip->reg_cnt2[1] + of) & 3); 397 | 398 | int of2 = (chip->reg_key_cnt1[1] & 2) != 0; 399 | chip->reg_key_cnt1[0] = (rst1 || of2) ? 0 : ((chip->reg_key_cnt1[1] + 1) & 3); 400 | chip->reg_key_cnt2[0] = rst1 ? 0 : ((chip->reg_key_cnt2[1] + of2) & 3); 401 | 402 | chip->reg_kon[0][0] = chip->reg_kon[0][1] << 1; 403 | chip->reg_kon[1][0] = chip->reg_kon[1][1] << 1; 404 | chip->reg_kon[2][0] = chip->reg_kon[2][1] << 1; 405 | chip->reg_kon[3][0] = chip->reg_kon[3][1] << 1; 406 | 407 | if (chip->reg_kon_match) 408 | { 409 | chip->reg_kon[0][0] |= (chip->reg_kon_operator[1] >> 0) & 1; 410 | chip->reg_kon[1][0] |= (chip->reg_kon_operator[1] >> 3) & 1; 411 | chip->reg_kon[2][0] |= (chip->reg_kon_operator[1] >> 1) & 1; 412 | chip->reg_kon[3][0] |= (chip->reg_kon_operator[1] >> 2) & 1; 413 | } 414 | else 415 | { 416 | if (!ic) 417 | chip->reg_kon[0][0] |= (chip->reg_kon[3][1] >> 2) & 1; 418 | chip->reg_kon[1][0] |= (chip->reg_kon[0][1] >> 2) & 1; 419 | chip->reg_kon[2][0] |= (chip->reg_kon[1][1] >> 2) & 1; 420 | chip->reg_kon[3][0] |= (chip->reg_kon[2][1] >> 2) & 1; 421 | } 422 | 423 | chip->reg_sync_timer_l[0] = chip->reg_sync_timer; 424 | 425 | int time = chip->timer_a_cnt[1]; 426 | time += (chip->reg_test_21[1] & 4) != 0 || (chip->timer_a_reg_load && chip->reg_sync_timer); 427 | 428 | chip->timer_a_cnt[0] = chip->timer_a_load ? chip->reg_timer_a[1] : (!chip->timer_a_reg_load ? 0 : (time & 1023)); 429 | chip->timer_a_of[0] = (time & 1024) != 0; 430 | 431 | chip->timer_a_reg_load_l[0] = chip->timer_a_reg_load; 432 | 433 | int rst_a = chip->reg_timer_a_reset[1] || ic; 434 | 435 | if (rst_a) 436 | chip->timer_a_status[0] = 0; 437 | else 438 | chip->timer_a_status[0] = chip->timer_a_status[1]; 439 | 440 | chip->timer_a_status[0] |= !rst_a && chip->reg_timer_a_enable[1] && chip->timer_a_of[1]; 441 | 442 | int subcnt = chip->timer_b_subcnt[1] + chip->reg_sync_timer; 443 | chip->timer_b_subcnt[0] = ic ? 0 : subcnt & 15; 444 | chip->timer_b_subcnt_of[0] = (subcnt & 16) != 0; 445 | 446 | time = chip->timer_b_cnt[1]; 447 | time += (chip->reg_test_21[1] & 4) != 0 || (chip->timer_b_reg_load && chip->timer_b_subcnt_of[1]); 448 | 449 | chip->timer_b_cnt[0] = chip->timer_b_load ? chip->reg_timer_b[1] : (!chip->timer_b_reg_load ? 0 : (time & 255)); 450 | chip->timer_b_of[0] = (time & 256) != 0; 451 | 452 | chip->timer_b_reg_load_l[0] = chip->timer_b_reg_load; 453 | 454 | int rst_b = chip->reg_timer_b_reset[1] || ic; 455 | 456 | if (rst_b) 457 | chip->timer_b_status[0] = 0; 458 | else 459 | chip->timer_b_status[0] = chip->timer_b_status[1]; 460 | 461 | chip->timer_b_status[0] |= !rst_b && chip->reg_timer_b_enable[1] && chip->timer_b_of[1]; 462 | 463 | 464 | memcpy(&chip->reg_freq[0][1], &chip->reg_freq[1][0], 2 * sizeof(unsigned short)); 465 | memcpy(&chip->reg_freq_3ch[0][1], &chip->reg_freq_3ch[1][0], 2 * sizeof(unsigned short)); 466 | memcpy(&chip->reg_connect_fb[0][1], &chip->reg_connect_fb[1][0], 2 * sizeof(unsigned char)); 467 | memcpy(&chip->op_multi_dt[0][1], &chip->op_multi_dt[1][0], 11 * sizeof(unsigned char)); 468 | memcpy(&chip->op_tl[0][1], &chip->op_tl[1][0], 11 * sizeof(unsigned char)); 469 | memcpy(&chip->op_ar_ks[0][1], &chip->op_ar_ks[1][0], 11 * sizeof(unsigned char)); 470 | memcpy(&chip->op_dr_a[0][1], &chip->op_dr_a[1][0], 11 * sizeof(unsigned char)); 471 | memcpy(&chip->op_sr[0][1], &chip->op_sr[1][0], 11 * sizeof(unsigned char)); 472 | memcpy(&chip->op_rr_sl[0][1], &chip->op_rr_sl[1][0], 11 * sizeof(unsigned char)); 473 | memcpy(&chip->op_ssg[0][1], &chip->op_ssg[1][0], 11 * sizeof(unsigned char)); 474 | 475 | if (ic) 476 | { 477 | chip->reg_a4[0] = 0; 478 | chip->reg_freq[0][0] = 0; 479 | chip->reg_ac[0] = 0; 480 | chip->reg_freq_3ch[0][0] = 0; 481 | chip->reg_connect_fb[0][0] = 0; 482 | 483 | chip->op_multi_dt[0][0] = 0; 484 | chip->op_tl[0][0] = 0; 485 | chip->op_ar_ks[0][0] = 0; 486 | chip->op_dr_a[0][0] = 0; 487 | chip->op_sr[0][0] = 0; 488 | chip->op_rr_sl[0][0] = 0; 489 | chip->op_ssg[0][0] = 0; 490 | } 491 | else 492 | { 493 | chip->reg_a4[0] = chip->fm_isa4 ? (chip->fm_data[1] & 0x3f) : chip->reg_a4[1]; 494 | chip->reg_freq[0][0] = chip->fm_isa0 ? (chip->fm_data[1] & 0xff) | (chip->reg_a4[1] << 8) : chip->reg_freq[1][2]; 495 | chip->reg_ac[0] = chip->fm_isac ? (chip->fm_data[1] & 0x3f) : chip->reg_ac[1]; 496 | chip->reg_freq_3ch[0][0] = chip->fm_isa8 ? (chip->fm_data[1] & 0xff) | (chip->reg_ac[1] << 8) : chip->reg_freq_3ch[1][2]; 497 | chip->reg_connect_fb[0][0] = chip->fm_isb0 ? (chip->fm_data[1] & 0x3f) : chip->reg_connect_fb[1][2]; 498 | 499 | chip->op_multi_dt[0][0] = chip->fm_is30 ? (chip->fm_data[1] & 0x7f) : chip->op_multi_dt[1][11]; 500 | chip->op_tl[0][0] = chip->fm_is40 ? (chip->fm_data[1] & 0x7f) : chip->op_tl[1][11]; 501 | chip->op_ar_ks[0][0] = chip->fm_is50 ? (chip->fm_data[1] & 0xdf) : chip->op_ar_ks[1][11]; 502 | chip->op_dr_a[0][0] = chip->fm_is60 ? (chip->fm_data[1] & 0x9f) : chip->op_dr_a[1][11]; 503 | chip->op_sr[0][0] = chip->fm_is70 ? (chip->fm_data[1] & 0x1f) : chip->op_sr[1][11]; 504 | chip->op_rr_sl[0][0] = chip->fm_is80 ? (chip->fm_data[1] & 0xff) : chip->op_rr_sl[1][11]; 505 | chip->op_ssg[0][0] = chip->fm_is90 ? (chip->fm_data[1] & 0xf) : chip->op_ssg[1][11]; 506 | } 507 | 508 | 509 | int freq = 0; 510 | if (chip->ch3_en && (chip->ch3_sel[1] & 2) != 0) 511 | freq |= chip->reg_freq_3ch[1][2]; 512 | if (chip->ch3_en && (chip->ch3_sel[1] & 16) != 0) 513 | freq |= chip->reg_freq_3ch[1][0]; 514 | if (chip->ch3_en && (chip->ch3_sel[1] & 128) != 0) 515 | freq |= chip->reg_freq_3ch[1][1]; 516 | if (chip->reg_cnt_sync || (chip->ch3_sel[1] & (1+4+8+32+64+256+512+1024)) != 0 || (!chip->ch3_en && (chip->ch3_sel[1] & (2+16+128)) != 0)) 517 | freq |= chip->reg_freq[1][1]; 518 | 519 | chip->fnum[0] = freq & 0x7ff; 520 | chip->kcode[0] = ((freq >> 11) & 7) << 2; 521 | if (freq & 0x400) 522 | { 523 | chip->kcode[0] |= 2; 524 | if ((freq & 0x380) != 0) 525 | chip->kcode[0] |= 1; 526 | } 527 | else 528 | { 529 | if ((freq & 0x380) == 0x380) 530 | chip->kcode[0] |= 1; 531 | } 532 | 533 | chip->fnum[2] = chip->fnum[1]; 534 | chip->kcode[2] = chip->kcode[1]; 535 | chip->fnum[4] = chip->fnum[3]; 536 | 537 | chip->ch3_sel[0] = (chip->ch3_sel[1] << 1) | chip->reg_cnt_sync; 538 | } 539 | if (chip->clk2) 540 | { 541 | chip->fm_address[1] = chip->fm_address[0]; 542 | chip->write_fm_address[1] = chip->write_fm_address[0]; 543 | chip->fm_data[1] = chip->fm_data[0]; 544 | chip->write_fm_data[1] = chip->write_fm_data[0]; 545 | 546 | chip->addr_21[1] = chip->addr_21[0]; 547 | chip->addr_24[1] = chip->addr_24[0]; 548 | chip->addr_25[1] = chip->addr_25[0]; 549 | chip->addr_26[1] = chip->addr_26[0]; 550 | chip->addr_27[1] = chip->addr_27[0]; 551 | chip->addr_28[1] = chip->addr_28[0]; 552 | 553 | chip->reg_test_21[1] = chip->reg_test_21[0]; 554 | chip->reg_timer_a[1] = chip->reg_timer_a[0]; 555 | chip->reg_timer_b[1] = chip->reg_timer_b[0]; 556 | chip->reg_ch3[1] = chip->reg_ch3[0]; 557 | chip->reg_timer_a_load[1] = chip->reg_timer_a_load[0]; 558 | chip->reg_timer_b_load[1] = chip->reg_timer_b_load[0]; 559 | chip->reg_timer_a_enable[1] = chip->reg_timer_a_enable[0]; 560 | chip->reg_timer_b_enable[1] = chip->reg_timer_b_enable[0]; 561 | chip->reg_timer_a_reset[1] = chip->reg_timer_a_reset[0]; 562 | chip->reg_timer_b_reset[1] = chip->reg_timer_b_reset[0]; 563 | chip->reg_kon_operator[1] = chip->reg_kon_operator[0]; 564 | chip->reg_kon_channel[1] = chip->reg_kon_channel[0]; 565 | 566 | int op_match = chip->write_fm_data[0] && (chip->reg_cnt1[0] == (chip->fm_address[0] & 3)) 567 | && (chip->reg_cnt2[0] & 3) == ((chip->fm_address[0] >> 2) & 3); 568 | int ch_match = chip->write_fm_data[0] && (chip->reg_cnt1[0] == (chip->fm_address[0] & 3)); 569 | 570 | chip->fm_is30 = op_match && (chip->fm_address[0] & 0xf0) == 0x30; 571 | chip->fm_is40 = op_match && (chip->fm_address[0] & 0xf0) == 0x40; 572 | chip->fm_is50 = op_match && (chip->fm_address[0] & 0xf0) == 0x50; 573 | chip->fm_is60 = op_match && (chip->fm_address[0] & 0xf0) == 0x60; 574 | chip->fm_is70 = op_match && (chip->fm_address[0] & 0xf0) == 0x70; 575 | chip->fm_is80 = op_match && (chip->fm_address[0] & 0xf0) == 0x80; 576 | chip->fm_is90 = op_match && (chip->fm_address[0] & 0xf0) == 0x90; 577 | chip->fm_isa0 = ch_match && (chip->fm_address[0] & 0xfc) == 0xa0; 578 | chip->fm_isa4 = ch_match && (chip->fm_address[0] & 0xfc) == 0xa4; 579 | chip->fm_isa8 = ch_match && (chip->fm_address[0] & 0xfc) == 0xa8; 580 | chip->fm_isac = ch_match && (chip->fm_address[0] & 0xfc) == 0xac; 581 | chip->fm_isb0 = ch_match && (chip->fm_address[0] & 0xfc) == 0xb0; 582 | 583 | chip->reg_cnt1[1] = chip->reg_cnt1[0]; 584 | chip->reg_cnt2[1] = chip->reg_cnt2[0]; 585 | 586 | chip->reg_kon_match = chip->reg_key_cnt1[0] == (chip->reg_kon_channel[0] & 3) 587 | && chip->reg_key_cnt2[0] == 0; 588 | 589 | chip->reg_key_cnt1[1] = chip->reg_key_cnt1[0]; 590 | chip->reg_key_cnt2[1] = chip->reg_key_cnt2[0]; 591 | 592 | chip->reg_kon[0][1] = chip->reg_kon[0][0]; 593 | chip->reg_kon[1][1] = chip->reg_kon[1][0]; 594 | chip->reg_kon[2][1] = chip->reg_kon[2][0]; 595 | chip->reg_kon[3][1] = chip->reg_kon[3][0]; 596 | 597 | chip->ch3_en = chip->reg_ch3[0] != 0; 598 | chip->ch3_csm = chip->reg_ch3[0] == 2; 599 | 600 | chip->timer_a_cnt[1] = chip->timer_a_cnt[0]; 601 | chip->timer_a_of[1] = chip->timer_a_of[0]; 602 | 603 | chip->reg_sync_timer = (chip->ch3_sel[0] & 2) != 0; 604 | chip->reg_sync_timer_l[1] = chip->reg_sync_timer_l[0]; 605 | 606 | chip->timer_a_reg_load_l[1] = chip->timer_a_reg_load_l[0]; 607 | 608 | chip->reg_sync_timer_load = chip->reg_sync_timer_l[0] && chip->reg_sync_timer_l[1]; 609 | if (chip->reg_sync_timer_load) 610 | { 611 | chip->timer_a_reg_load = chip->reg_timer_a_load[1]; 612 | chip->timer_b_reg_load = chip->reg_timer_b_load[1]; 613 | } 614 | 615 | chip->timer_a_load = chip->timer_a_of[1] || (!chip->timer_a_reg_load_l[1] && chip->timer_a_reg_load); 616 | 617 | if (chip->reg_sync_timer_load) 618 | { 619 | chip->ch3_csm_load = chip->ch3_csm && chip->timer_a_load; 620 | } 621 | 622 | chip->timer_a_status[1] = chip->timer_a_status[0]; 623 | 624 | chip->timer_b_subcnt[1] = chip->timer_b_subcnt[0]; 625 | chip->timer_b_subcnt_of[1] = chip->timer_b_subcnt_of[0]; 626 | 627 | chip->timer_b_cnt[1] = chip->timer_b_cnt[0]; 628 | chip->timer_b_of[1] = chip->timer_b_of[0]; 629 | 630 | chip->timer_b_reg_load_l[1] = chip->timer_b_reg_load_l[0]; 631 | 632 | chip->timer_b_load = chip->timer_b_of[1] || (!chip->timer_b_reg_load_l[1] && chip->timer_b_reg_load); 633 | 634 | chip->timer_b_status[1] = chip->timer_b_status[0]; 635 | 636 | memcpy(&chip->reg_freq[1][0], &chip->reg_freq[0][0], 3 * sizeof(unsigned short)); 637 | memcpy(&chip->reg_freq_3ch[1][0], &chip->reg_freq_3ch[0][0], 3 * sizeof(unsigned short)); 638 | memcpy(&chip->reg_connect_fb[1][0], &chip->reg_connect_fb[0][0], 3 * sizeof(unsigned char)); 639 | memcpy(&chip->op_multi_dt[1][0], &chip->op_multi_dt[0][0], 12 * sizeof(unsigned char)); 640 | memcpy(&chip->op_tl[1][0], &chip->op_tl[0][0], 12 * sizeof(unsigned char)); 641 | memcpy(&chip->op_ar_ks[1][0], &chip->op_ar_ks[0][0], 12 * sizeof(unsigned char)); 642 | memcpy(&chip->op_dr_a[1][0], &chip->op_dr_a[0][0], 12 * sizeof(unsigned char)); 643 | memcpy(&chip->op_sr[1][0], &chip->op_sr[0][0], 12 * sizeof(unsigned char)); 644 | memcpy(&chip->op_rr_sl[1][0], &chip->op_rr_sl[0][0], 12 * sizeof(unsigned char)); 645 | memcpy(&chip->op_ssg[1][0], &chip->op_ssg[0][0], 12 * sizeof(unsigned char)); 646 | 647 | chip->reg_a4[1] = chip->reg_a4[0]; 648 | chip->reg_ac[1] = chip->reg_ac[0]; 649 | 650 | chip->fnum[1] = chip->fnum[0]; 651 | chip->fnum[3] = chip->fnum[2]; 652 | 653 | chip->ch3_sel[1] = chip->ch3_sel[0]; 654 | 655 | chip->kcode[1] = chip->kcode[0]; 656 | chip->kcode[3] = chip->kcode[2]; 657 | 658 | chip->o_irq_pull = chip->timer_a_status[0] || chip->timer_b_status[0]; 659 | 660 | chip->reg_ch3_sel = chip->fsm_ch3_sync[1]; 661 | } 662 | } 663 | 664 | { 665 | if (chip->clk1) 666 | { 667 | chip->ic_latch[0] = chip->ic_latch[1]; 668 | 669 | int fsm_ic = (chip->ic_latch[1] & 4) != 0; 670 | 671 | int fsm_cnt; 672 | int of1 = (chip->fsm_cnt1[1] & 2) != 0; 673 | chip->fsm_cnt1[0] = (fsm_ic || of1) ? 0 : (chip->fsm_cnt1[1] + 1) & 3; 674 | chip->fsm_cnt2[0] = fsm_ic ? 0 : (chip->fsm_cnt2[1] + of1) & 3; 675 | 676 | fsm_cnt = (chip->fsm_cnt2[0] << 2) | chip->fsm_cnt1[0]; 677 | 678 | // 0 - 0000 679 | // 1 - 0001 680 | // 2 - 0010 681 | // 3 - 0100 682 | // 4 - 0101 683 | // 5 - 0110 684 | // 6 - 1000 685 | // 7 - 1001 686 | // 8 - 1010 687 | // 9 - 1100 688 | // 10 - 1101 689 | // 11 - 1110 690 | 691 | chip->fsm_out[0] = (fsm_cnt & 14) == 4; // 3, 4 692 | chip->fsm_out[1] = fsm_cnt == 2; // 2 693 | chip->fsm_out[2] = fsm_cnt == 14; // 11 694 | chip->fsm_out[3] = (fsm_cnt & 14) == 0; // 0, 1 695 | chip->fsm_out[4] = (fsm_cnt & 14) == 12; // 9, 10 696 | chip->fsm_out[5] = fsm_cnt == 10; // 8 697 | chip->fsm_out[6] = fsm_cnt == 6; // 5 698 | chip->fsm_out[7] = (fsm_cnt & 14) == 8; // 6, 7 699 | 700 | chip->fsm_out[8] = (fsm_cnt & 14) == 12; // 9, 10 701 | chip->fsm_out[9] = fsm_cnt == 10; // 8 702 | chip->fsm_out[10] = (fsm_cnt & 13) == 9; // 7 703 | chip->fsm_out[11] = (fsm_cnt & 3) == 1; // 1, 4, 7, 10 704 | chip->fsm_out[12] = (fsm_cnt & 14) == 10; // 8 705 | chip->fsm_out[13] = (fsm_cnt & 13) == 13; // 10 706 | 707 | chip->fsm_sh_l[0] = (chip->fsm_sh_l[1] << 1) | chip->fsm_sh; 708 | 709 | chip->alg_mod_op1_0_l = 0; 710 | chip->alg_mod_op1_1_l = 0; 711 | chip->alg_mod_op2_l = 0; 712 | chip->alg_mod_prev_0_l = 0; 713 | chip->alg_mod_prev_1_l = 0; 714 | chip->alg_output_l = 0; 715 | 716 | if (chip->fsm_op2_sel_l) 717 | { 718 | chip->alg_mod_op1_0_l |= fm_algorithm[0][0][chip->fsm_connect]; 719 | chip->alg_mod_op1_1_l |= fm_algorithm[0][1][chip->fsm_connect]; 720 | chip->alg_mod_op2_l |= fm_algorithm[0][2][chip->fsm_connect]; 721 | chip->alg_mod_prev_0_l |= fm_algorithm[0][3][chip->fsm_connect]; 722 | chip->alg_mod_prev_1_l |= fm_algorithm[0][4][chip->fsm_connect]; 723 | chip->alg_output_l |= fm_algorithm[2][5][chip->fsm_connect]; 724 | } 725 | if (chip->fsm_op4_sel_l) 726 | { 727 | chip->alg_mod_op1_0_l |= fm_algorithm[1][0][chip->fsm_connect]; 728 | chip->alg_mod_op1_1_l |= fm_algorithm[1][1][chip->fsm_connect]; 729 | chip->alg_mod_op2_l |= fm_algorithm[1][2][chip->fsm_connect]; 730 | chip->alg_mod_prev_0_l |= fm_algorithm[1][3][chip->fsm_connect]; 731 | chip->alg_mod_prev_1_l |= fm_algorithm[1][4][chip->fsm_connect]; 732 | chip->alg_output_l |= fm_algorithm[3][5][chip->fsm_connect]; 733 | } 734 | if (chip->fsm_op1_sel_l) 735 | { 736 | chip->alg_mod_op1_0_l |= fm_algorithm[2][0][chip->fsm_connect]; 737 | chip->alg_mod_op1_1_l |= fm_algorithm[2][1][chip->fsm_connect]; 738 | chip->alg_mod_op2_l |= fm_algorithm[2][2][chip->fsm_connect]; 739 | chip->alg_mod_prev_0_l |= fm_algorithm[2][3][chip->fsm_connect]; 740 | chip->alg_mod_prev_1_l |= fm_algorithm[2][4][chip->fsm_connect]; 741 | chip->alg_output_l |= fm_algorithm[0][5][chip->fsm_connect]; 742 | } 743 | if (chip->fsm_op3_sel_l) 744 | { 745 | chip->alg_mod_op1_0_l |= fm_algorithm[3][0][chip->fsm_connect]; 746 | chip->alg_mod_op1_1_l |= fm_algorithm[3][1][chip->fsm_connect]; 747 | chip->alg_mod_op2_l |= fm_algorithm[3][2][chip->fsm_connect]; 748 | chip->alg_mod_prev_0_l |= fm_algorithm[3][3][chip->fsm_connect]; 749 | chip->alg_mod_prev_1_l |= fm_algorithm[3][4][chip->fsm_connect]; 750 | chip->alg_output_l |= fm_algorithm[1][5][chip->fsm_connect]; 751 | } 752 | 753 | chip->alg_do_fb[1] = chip->alg_do_fb[0]; 754 | 755 | chip->alg_load_fb = chip->fsm_op1_sel_l; 756 | 757 | chip->fsm_sel_11[1] = chip->fsm_sel_11[0]; 758 | 759 | chip->fsm_acc_sync[1] = chip->fsm_acc_sync[0]; 760 | chip->fsm_ch3_sync[1] = chip->fsm_ch3_sync[0]; 761 | } 762 | if (chip->clk2) 763 | { 764 | chip->ic_latch[1] = (chip->ic_latch[0] << 1) | ic; 765 | 766 | chip->fsm_cnt1[1] = chip->fsm_cnt1[0]; 767 | chip->fsm_cnt2[1] = chip->fsm_cnt2[0]; 768 | 769 | chip->fsm_op4_sel_l = chip->fsm_out[0] || chip->fsm_out[1]; // 2, 3, 4 770 | chip->fsm_op2_sel_l = chip->fsm_out[2] || chip->fsm_out[3]; // 11, 0, 1 771 | chip->fsm_op3_sel_l = chip->fsm_out[4] || chip->fsm_out[5]; // 8, 9, 10 772 | chip->fsm_op1_sel_l = chip->fsm_out[6] || chip->fsm_out[7]; // 5, 6, 7 773 | 774 | chip->fsm_connect = chip->reg_connect_fb[0][1] & 7; 775 | 776 | chip->alg_do_fb[0] = chip->alg_mod_op1_1_l; 777 | 778 | chip->fsm_sh = chip->fsm_out[8] || chip->fsm_out[9] || chip->fsm_out[10]; // 7, 8, 9, 10 779 | 780 | chip->fsm_sh_l[1] = chip->fsm_sh_l[0]; 781 | 782 | chip->reg_cnt_sync = chip->fsm_sel_11[1]; 783 | 784 | chip->fsm_sel_11[0] = chip->fsm_out[13]; 785 | 786 | chip->fsm_acc_sync[0] = chip->fsm_out[12]; 787 | chip->fsm_ch3_sync[0] = chip->fsm_out[11]; 788 | } 789 | } 790 | 791 | chip->o_sh = (chip->fsm_sh_l[0] >> 8) & 1; 792 | 793 | 794 | { 795 | if (chip->clk1) 796 | { 797 | chip->pg_block = chip->kcode[3] >> 2; 798 | 799 | chip->pg_dt_multi = chip->op_multi_dt[1][11]; 800 | 801 | chip->dt_note[1] = chip->dt_note[0]; 802 | chip->dt_blockmax[1] = chip->dt_blockmax[0]; 803 | 804 | chip->dt_enable[1] = chip->dt_enable[0]; 805 | 806 | chip->dt_sign[1] = chip->dt_sign[0]; 807 | 808 | chip->dt_sum = chip->dt_add1 + chip->dt_add2 + 1; 809 | 810 | chip->pg_freqdt[0] = (chip->pg_freq + chip->pg_dt_add) & 0x1ffff; 811 | 812 | chip->pg_multi[1] = chip->pg_multi[0]; 813 | chip->pg_multi[3] = chip->pg_multi[2]; 814 | 815 | chip->pg_add[0] = chip->pg_multi[4] ? chip->pg_freqdt[1] * chip->pg_multi[4] : 816 | (chip->pg_freqdt[1] >> 1); 817 | chip->pg_add[2] = chip->pg_add[1]; 818 | chip->pg_add[4] = chip->pg_add[3]; 819 | 820 | chip->pg_reset[1] = chip->pg_reset[0]; 821 | chip->pg_reset[3] = chip->pg_reset[2] || (chip->reg_test_21[1] & 8) != 0; 822 | 823 | memcpy(&chip->pg_phase[0][1], &chip->pg_phase[1][0], 10 * sizeof(int)); 824 | 825 | chip->pg_phase2[0] = chip->pg_phase[1][10]; 826 | 827 | chip->pg_phase[0][0] = (chip->pg_phase2[1] + chip->pg_add[5]) & 0xfffff; 828 | 829 | chip->pg_dbg[0] = chip->pg_dbg[1] >> 1; 830 | if (chip->pg_dbgsync) 831 | chip->pg_dbg[0] |= chip->pg_phase[1][10] & 1023; 832 | 833 | } 834 | if (chip->clk2) 835 | { 836 | chip->pg_freq = (chip->fnum[4] << chip->pg_block) >> 1; 837 | 838 | chip->dt_note[0] = chip->kcode[2] & 3; 839 | chip->dt_blockmax[0] = (chip->kcode[2] & 28) == 28; 840 | chip->dt_add1 = (chip->kcode[2] >> 2) & 7; 841 | if ((chip->pg_dt_multi & 0x30) != 0) 842 | chip->dt_add1 |= 8; 843 | chip->dt_add2 = 0; 844 | if ((chip->pg_dt_multi & 0x30) == 0x30) 845 | chip->dt_add2 |= 1; 846 | if (chip->pg_dt_multi & 0x20) 847 | chip->dt_add2 |= 2; 848 | 849 | chip->dt_enable[0] = (chip->pg_dt_multi & 0x30) != 0; 850 | 851 | chip->dt_sign[0] = (chip->pg_dt_multi & 0x40) != 0; 852 | 853 | int dt_l = (chip->dt_sum & 1) << 2; 854 | if (!chip->dt_blockmax[1]) 855 | dt_l |= chip->dt_note[1]; 856 | int dt_h = chip->dt_sum >> 1; 857 | 858 | static const int pg_detune[8] = { 16, 17, 19, 20, 22, 24, 27, 29 }; 859 | 860 | int dt_freq = pg_detune[dt_l] >> (9 - dt_h); 861 | 862 | if (chip->dt_sign[1]) 863 | dt_freq = -dt_freq; 864 | 865 | chip->pg_dt_add = dt_freq; 866 | 867 | chip->pg_multi[0] = chip->pg_dt_multi & 15; 868 | chip->pg_multi[2] = chip->pg_multi[1]; 869 | chip->pg_multi[4] = chip->pg_multi[3]; 870 | 871 | chip->pg_freqdt[1] = chip->pg_freqdt[0]; 872 | 873 | chip->pg_add[1] = chip->pg_add[0]; 874 | chip->pg_add[3] = chip->pg_reset[1] ? 0 : chip->pg_add[2]; 875 | chip->pg_add[5] = chip->pg_add[4]; 876 | 877 | chip->pg_reset[0] = (chip->eg_pg_reset[0] & 2) != 0; 878 | chip->pg_reset[2] = chip->pg_reset[1]; 879 | memcpy(&chip->pg_phase[1][0], &chip->pg_phase[0][0], 11 * sizeof(int)); 880 | 881 | chip->pg_out = chip->pg_phase[1][6] >> 10; 882 | 883 | chip->pg_phase2[1] = chip->pg_reset[3] ? 0 : chip->pg_phase2[0]; 884 | 885 | chip->pg_dbgsync = (chip->ch3_sel[0] & 4) != 0; 886 | 887 | chip->pg_dbg[1] = chip->pg_dbg[0]; 888 | } 889 | } 890 | 891 | { 892 | if (chip->clk1) 893 | { 894 | chip->eg_prescaler_clock_l[0] = chip->eg_sync; 895 | chip->eg_prescaler[0] = (chip->eg_prescaler[1] + chip->eg_sync) & 3; 896 | if (((chip->eg_prescaler[1] & 2) != 0 && chip->eg_sync) || ic) 897 | chip->eg_prescaler[0] = 0; 898 | chip->eg_step[0] = chip->eg_prescaler[1] >> 1; 899 | chip->eg_step[2] = chip->eg_step[1]; 900 | chip->eg_timer_step[1] = chip->eg_timer_step[0]; 901 | 902 | chip->eg_ic[0] = ic; 903 | 904 | 905 | int sum = (chip->eg_timer[1] >> 10) & 1; 906 | int add = chip->eg_timer_carry[1]; 907 | if ((chip->eg_prescaler[1] & 2) != 0 && chip->eg_prescaler_clock_l[1]) 908 | add = 1; 909 | sum += add; 910 | 911 | chip->eg_timer[0] = (chip->eg_timer[1] << 1) | chip->eg_timer_sum[1]; 912 | 913 | chip->eg_timer_carry[0] = sum >> 1; 914 | chip->eg_timer_sum[0] = sum & 1; 915 | 916 | int timer_bit = chip->eg_timer_sum[1]; 917 | 918 | chip->eg_timer_mask[0] = timer_bit | chip->eg_timer_mask[1]; 919 | if (chip->eg_prescaler_clock_l[1] || chip->eg_ic[1]) 920 | chip->eg_timer_mask[0] = 0; 921 | 922 | int timer_bit_masked = timer_bit && !chip->eg_timer_mask[1]; 923 | 924 | chip->eg_timer_masked[0] = (chip->eg_timer_masked[1] << 1) | timer_bit_masked; 925 | 926 | if (chip->eg_timer_step[0] && chip->eg_timer_step[1]) 927 | { 928 | int b0, b1, b2, b3; 929 | b0 = (chip->eg_timer[0] >> 11) & 1; 930 | b1 = (chip->eg_timer[0] >> 10) & 1; 931 | chip->eg_timer_low_lock = b1 * 2 + b0; 932 | 933 | b0 = (chip->eg_timer_masked[0] & 0xaaa) != 0; 934 | b1 = (chip->eg_timer_masked[0] & 0x666) != 0; 935 | b2 = (chip->eg_timer_masked[0] & 0x1e1) != 0; 936 | b3 = (chip->eg_timer_masked[0] & 0x1f) != 0; 937 | chip->eg_shift_lock = b3 * 8 + b2 * 4 + b1 * 2 + b0; 938 | } 939 | 940 | chip->eg_rate_ar = chip->op_ar_ks[1][11] & 0x1f; 941 | chip->eg_ks = (chip->op_ar_ks[1][11] >> 6) & 3; 942 | chip->eg_rate_dr = chip->op_dr_a[1][11] & 0x1f; 943 | chip->eg_rate_sr = chip->op_sr[1][11] & 0x1f; 944 | chip->eg_rate_rr = chip->op_rr_sl[1][11] & 0xf; 945 | 946 | chip->eg_rate_nonzero[1] = chip->eg_rate_nonzero[0]; 947 | 948 | chip->eg_rate2 = (chip->eg_rate << 1) + chip->eg_ksv; 949 | 950 | chip->eg_maxrate[1] = chip->eg_maxrate[0]; 951 | 952 | int inc1 = 0; 953 | if (chip->eg_rate_slow && chip->eg_rate_nonzero[2]) 954 | { 955 | switch (chip->eg_rate_sum) 956 | { 957 | case 12: 958 | inc1 = chip->eg_ratenz; 959 | break; 960 | case 13: 961 | inc1 = (chip->eg_rate_low >> 1) & 1; 962 | break; 963 | case 14: 964 | inc1 = chip->eg_rate_low & 1; 965 | break; 966 | } 967 | } 968 | 969 | chip->eg_incsh0[0] = inc1; 970 | chip->eg_incsh3[0] = chip->eg_rate15; 971 | if (!chip->eg_inc2) 972 | { 973 | chip->eg_incsh0[0] |= chip->eg_rate12; 974 | chip->eg_incsh1[0] = chip->eg_rate13; 975 | chip->eg_incsh2[0] = chip->eg_rate14; 976 | } 977 | else 978 | { 979 | chip->eg_incsh1[0] = chip->eg_rate12; 980 | chip->eg_incsh2[0] = chip->eg_rate13; 981 | chip->eg_incsh3[0] |= chip->eg_rate14; 982 | } 983 | 984 | int kon_comb; 985 | 986 | kon_comb = (chip->reg_kon[3][1] >> 2) & 1; 987 | kon_comb |= chip->reg_ch3_sel && chip->ch3_csm_load; 988 | 989 | chip->eg_kon_latch[0] = (chip->eg_kon_latch[1] << 1) | kon_comb; 990 | int csm_kon = chip->reg_ch3_sel && chip->ch3_csm_load; 991 | chip->eg_kon_csm[0] = (chip->eg_kon_csm[1] << 1) | csm_kon; 992 | 993 | int kon = (chip->eg_kon_latch[1] >> 1) & 1; 994 | int okon = (chip->eg_key[1] >> 11) & 1; 995 | int pg_reset = (kon && !okon) || (chip->eg_ssg_pgreset[1] & 2) != 0; 996 | chip->eg_pg_reset[0] = (chip->eg_pg_reset[1] << 1) | pg_reset; 997 | chip->eg_kon_event = (kon && !okon) || (okon && (chip->eg_ssg_egrepeat[1] & 2) != 0); 998 | 999 | chip->eg_key[0] = (chip->eg_key[1] << 1) | kon; 1000 | 1001 | int okon2 = (chip->eg_key[1] >> 9) & 1; 1002 | 1003 | 1004 | chip->eg_ssg_sign[0] = (chip->eg_level[1][6] & 0x200) != 0; 1005 | 1006 | int ssg_eg = chip->op_ssg[1][11] & 15; 1007 | int ssg_enable = (ssg_eg & 8) != 0; 1008 | chip->eg_ssg_enable[0] = (chip->eg_ssg_enable[1] << 1) | ssg_enable; 1009 | int ssg_inv_e = ssg_enable && (ssg_eg & 4) != 0; 1010 | int ssg_holdup = ssg_enable && ((ssg_eg & 7) == 3 || (ssg_eg & 7) == 5) && kon_comb; 1011 | chip->eg_ssg_holdup[0] = (chip->eg_ssg_holdup[1] << 1) | ssg_holdup; 1012 | int ssg_pgreset = ssg_enable && chip->eg_ssg_sign[1] && (ssg_eg & 3) == 0; 1013 | chip->eg_ssg_pgreset[0] = (chip->eg_ssg_pgreset[1] << 1) | ssg_pgreset; 1014 | int ssg_egrepeat = ssg_enable && chip->eg_ssg_sign[1] && (ssg_eg & 1) == 0; 1015 | chip->eg_ssg_egrepeat[0] = (chip->eg_ssg_egrepeat[1] << 1) | ssg_egrepeat; 1016 | 1017 | chip->eg_rate_sel = (okon2 ? ssg_egrepeat : kon_comb) ? eg_state_attack : chip->eg_state[1][8]; 1018 | 1019 | int ssg_odir = (chip->eg_ssg_dir[1] >> 11) & 1; 1020 | int ssg_dir = ssg_enable && okon2 && 1021 | ((ssg_odir ^ ((ssg_eg & 3) == 2 && chip->eg_ssg_sign[1])) || ((ssg_eg & 3) == 3 && chip->eg_ssg_sign[1])); 1022 | chip->eg_ssg_dir[0] = (chip->eg_ssg_dir[1] << 1) | ssg_dir; 1023 | 1024 | int ssg_inv = okon2 && (ssg_odir ^ ssg_inv_e); 1025 | 1026 | chip->eg_ssg_inv = ssg_inv; 1027 | 1028 | chip->eg_level_ssg[0] = chip->eg_output; 1029 | 1030 | int sl = (chip->op_rr_sl[1][11] >> 4) & 15; 1031 | 1032 | if (sl == 15) 1033 | sl |= 16; 1034 | 1035 | chip->eg_sl[0][0] = sl; 1036 | chip->eg_sl[1][0] = chip->eg_sl[0][1]; 1037 | chip->eg_tl[0][0] = chip->op_tl[1][11]; 1038 | chip->eg_tl[1][0] = chip->eg_tl[0][1]; 1039 | chip->eg_tl[2][0] = chip->eg_tl[1][1]; 1040 | 1041 | int level = (okon && !kon) ? chip->eg_level_ssg[1] : chip->eg_level[1][9]; 1042 | 1043 | chip->eg_off = (chip->eg_ssg_enable[1] & 2) != 0 ? (level & 512) != 0 : (level & 0x3f0) == 0x3f0; 1044 | chip->eg_slreach = (level >> 4) == (chip->eg_sl[1][1] << 1); 1045 | chip->eg_zeroreach = level == 0; 1046 | 1047 | chip->eg_level_l[0] = level; 1048 | 1049 | chip->eg_state_l = chip->eg_state[1][10]; 1050 | 1051 | memcpy(&chip->eg_state[0][1], &chip->eg_state[1][0], 10 * sizeof(unsigned char)); 1052 | chip->eg_state[0][0] = chip->eg_nextstate; 1053 | 1054 | int inc_total = 0; 1055 | if (chip->eg_exp) 1056 | { 1057 | if (chip->eg_incsh0[1]) 1058 | inc_total |= ~chip->eg_level_l[1] >> 4; 1059 | if (chip->eg_incsh1[1]) 1060 | inc_total |= ~chip->eg_level_l[1] >> 3; 1061 | if (chip->eg_incsh2[1]) 1062 | inc_total |= ~chip->eg_level_l[1] >> 2; 1063 | if (chip->eg_incsh3[1]) 1064 | inc_total |= ~chip->eg_level_l[1] >> 1; 1065 | } 1066 | if (chip->eg_linear) 1067 | { 1068 | if (chip->eg_ssg_enable[1] & 4) 1069 | { 1070 | if (chip->eg_incsh0[1]) 1071 | inc_total |= 4; 1072 | if (chip->eg_incsh1[1]) 1073 | inc_total |= 8; 1074 | if (chip->eg_incsh2[1]) 1075 | inc_total |= 16; 1076 | if (chip->eg_incsh3[1]) 1077 | inc_total |= 32; 1078 | } 1079 | else 1080 | { 1081 | if (chip->eg_incsh0[1]) 1082 | inc_total |= 1; 1083 | if (chip->eg_incsh1[1]) 1084 | inc_total |= 2; 1085 | if (chip->eg_incsh2[1]) 1086 | inc_total |= 4; 1087 | if (chip->eg_incsh3[1]) 1088 | inc_total |= 8; 1089 | } 1090 | } 1091 | 1092 | chip->eg_inc_total = inc_total; 1093 | 1094 | int nextlevel = 0; 1095 | 1096 | if (!chip->eg_istantattack) 1097 | nextlevel |= chip->eg_level_l[1]; 1098 | 1099 | if (chip->eg_kon_csm[1] & 4) 1100 | nextlevel |= chip->eg_tl[2][1] << 3; 1101 | 1102 | if (chip->eg_mute || ic) 1103 | nextlevel |= 0x3ff; 1104 | 1105 | chip->eg_nextlevel[0] = nextlevel; 1106 | 1107 | memcpy(&chip->eg_level[0][1], &chip->eg_level[1][0], 9 * sizeof(unsigned short)); 1108 | chip->eg_level[0][0] = chip->eg_nextlevel[1]; 1109 | 1110 | chip->eg_output2 = chip->eg_output & 1023; 1111 | 1112 | chip->eg_ch3_l[1] = chip->eg_ch3_l[0]; 1113 | 1114 | chip->eg_csm_tl = (chip->ch3_csm && (chip->eg_ch3_l[0] & 2) != 0) ? 0 : chip->eg_tl[1][0]; 1115 | 1116 | chip->eg_debug[0] = chip->eg_debug[1] << 1; 1117 | 1118 | if (chip->eg_dbg_sync) 1119 | { 1120 | chip->eg_debug[0] |= chip->eg_out; 1121 | } 1122 | } 1123 | if (chip->clk2) 1124 | { 1125 | chip->eg_sync = (chip->ch3_sel[0] & 1) != 0; 1126 | chip->eg_prescaler_clock_l[1] = chip->eg_prescaler_clock_l[0]; 1127 | chip->eg_prescaler[1] = chip->eg_prescaler[0]; 1128 | chip->eg_step[1] = chip->eg_step[0]; 1129 | chip->eg_timer_step[0] = chip->eg_step[0] && chip->eg_prescaler_clock_l[0]; 1130 | 1131 | chip->eg_ic[1] = chip->eg_ic[0]; 1132 | 1133 | chip->eg_timer_sum[1] = chip->eg_timer_sum[0] && !chip->eg_ic[0]; 1134 | chip->eg_timer[1] = chip->eg_timer[0]; 1135 | chip->eg_timer_carry[1] = chip->eg_timer_carry[0]; 1136 | chip->eg_timer_mask[1] = chip->eg_timer_mask[0]; 1137 | chip->eg_timer_masked[1] = chip->eg_timer_masked[0]; 1138 | 1139 | int rate = 0; 1140 | switch (chip->eg_rate_sel) 1141 | { 1142 | case eg_state_attack: 1143 | rate = chip->eg_rate_ar; 1144 | break; 1145 | case eg_state_decay: 1146 | rate = chip->eg_rate_dr; 1147 | break; 1148 | case eg_state_sustain: 1149 | rate = chip->eg_rate_sr; 1150 | break; 1151 | case eg_state_release: 1152 | rate = (chip->eg_rate_rr * 2) | 1; 1153 | break; 1154 | } 1155 | 1156 | chip->eg_rate_nonzero[0] = rate != 0; 1157 | chip->eg_rate_nonzero[2] = chip->eg_rate_nonzero[1]; 1158 | chip->eg_rate = rate; 1159 | chip->eg_ksv = chip->kcode[2] >> (chip->eg_ks ^ 3); 1160 | 1161 | int rate2 = chip->eg_rate2; 1162 | if (rate2 & 64) 1163 | rate2 = 63; 1164 | 1165 | rate2 &= 63; 1166 | 1167 | static const int eg_stephi[4][4] = { 1168 | { 0, 0, 0, 0 }, 1169 | { 1, 0, 0, 0 }, 1170 | { 1, 0, 1, 0 }, 1171 | { 1, 1, 1, 0 } 1172 | }; 1173 | 1174 | chip->eg_inc2 = eg_stephi[rate2 & 3][chip->eg_timer_low_lock]; 1175 | chip->eg_ratenz = rate2 != 0; 1176 | chip->eg_rate12 = (rate2 & 60) == 48; 1177 | chip->eg_rate13 = (rate2 & 60) == 52; 1178 | chip->eg_rate14 = (rate2 & 60) == 56; 1179 | chip->eg_rate15 = (rate2 & 60) == 60; 1180 | chip->eg_maxrate[0] = (rate2 & 62) == 62; 1181 | chip->eg_rate_low = rate2 & 3; 1182 | chip->eg_rate_slow = (rate2 & 48) != 48; 1183 | 1184 | chip->eg_rate_sum = (chip->eg_shift_lock + (rate2 >> 2)) & 15; 1185 | 1186 | chip->eg_incsh0[1] = chip->eg_step[2] && chip->eg_incsh0[0]; 1187 | chip->eg_incsh1[1] = chip->eg_step[2] && chip->eg_incsh1[0]; 1188 | chip->eg_incsh2[1] = chip->eg_step[2] && chip->eg_incsh2[0]; 1189 | chip->eg_incsh3[1] = chip->eg_step[2] && chip->eg_incsh3[0]; 1190 | 1191 | chip->eg_kon_latch[1] = chip->eg_kon_latch[0]; 1192 | chip->eg_key[1] = chip->eg_key[0]; 1193 | 1194 | chip->eg_level_ssg[1] = chip->eg_level_ssg[0]; 1195 | 1196 | chip->eg_pg_reset[1] = chip->eg_pg_reset[0]; 1197 | 1198 | chip->eg_ssg_sign[1] = chip->eg_ssg_sign[0]; 1199 | 1200 | chip->eg_ssg_enable[1] = chip->eg_ssg_enable[0]; 1201 | chip->eg_ssg_dir[1] = chip->eg_ssg_dir[0]; 1202 | chip->eg_ssg_holdup[1] = chip->eg_ssg_holdup[0]; 1203 | chip->eg_ssg_pgreset[1] = chip->eg_ssg_pgreset[0]; 1204 | chip->eg_ssg_egrepeat[1] = chip->eg_ssg_egrepeat[0]; 1205 | 1206 | chip->eg_sl[0][1] = chip->eg_sl[0][0]; 1207 | chip->eg_sl[1][1] = chip->eg_sl[1][0]; 1208 | chip->eg_tl[0][1] = chip->eg_tl[0][0]; 1209 | chip->eg_tl[1][1] = chip->eg_tl[1][0]; 1210 | chip->eg_tl[2][1] = chip->eg_tl[2][0]; 1211 | 1212 | chip->eg_nextlevel[1] = chip->eg_nextlevel[0] + chip->eg_inc_total; 1213 | 1214 | chip->eg_kon_csm[1] = chip->eg_kon_csm[0]; 1215 | 1216 | int inv = ((chip->eg_level[0][8] ^ 1023) + 513) & 1023; 1217 | 1218 | chip->eg_output = chip->eg_ssg_inv ? inv : chip->eg_level[0][8]; 1219 | 1220 | chip->eg_level_l[1] = chip->eg_level_l[0]; 1221 | 1222 | 1223 | int nextstate = eg_state_attack; 1224 | 1225 | int eg_mute = !chip->eg_kon_event && chip->eg_off && (chip->eg_ssg_holdup[0] & 4) == 0 && chip->eg_state_l != eg_state_attack; 1226 | chip->eg_mute = eg_mute; 1227 | 1228 | if (eg_mute) 1229 | { 1230 | nextstate |= eg_state_release; 1231 | } 1232 | 1233 | if (!chip->eg_kon_event && chip->eg_state_l == eg_state_sustain) 1234 | { 1235 | nextstate |= eg_state_sustain; 1236 | } 1237 | 1238 | if (!chip->eg_kon_event && chip->eg_state_l == eg_state_decay && !chip->eg_slreach) 1239 | { 1240 | nextstate |= eg_state_decay; 1241 | } 1242 | if (!chip->eg_kon_event && chip->eg_state_l == eg_state_decay && chip->eg_slreach) 1243 | { 1244 | nextstate |= eg_state_sustain; 1245 | } 1246 | 1247 | if ((chip->eg_kon_latch[0] & 4) == 0 && !chip->eg_kon_event) 1248 | { 1249 | nextstate |= eg_state_release; 1250 | } 1251 | if (!chip->eg_kon_event && chip->eg_state_l == eg_state_release) 1252 | { 1253 | nextstate |= eg_state_release; 1254 | } 1255 | 1256 | if (!chip->eg_kon_event && chip->eg_state_l == eg_state_attack && chip->eg_zeroreach) 1257 | { 1258 | nextstate |= eg_state_decay; 1259 | } 1260 | if (chip->eg_ic[0]) 1261 | { 1262 | nextstate |= eg_state_release; 1263 | } 1264 | 1265 | chip->eg_nextstate = nextstate; 1266 | memcpy(&chip->eg_state[1][0], &chip->eg_state[0][0], 11 * sizeof(unsigned char)); 1267 | 1268 | chip->eg_exp = (chip->eg_kon_latch[0] & 4) != 0 && (chip->eg_state_l == eg_state_attack) && !chip->eg_maxrate[1] && !chip->eg_zeroreach; 1269 | chip->eg_linear = !chip->eg_kon_event && !chip->eg_off && (chip->eg_state_l == eg_state_sustain || chip->eg_state_l == eg_state_release); 1270 | chip->eg_linear |= !chip->eg_kon_event && !chip->eg_off && !chip->eg_slreach && chip->eg_state_l == eg_state_decay; 1271 | 1272 | chip->eg_istantattack = chip->eg_maxrate[1] && (!chip->eg_maxrate[1] || chip->eg_kon_event); 1273 | 1274 | memcpy(&chip->eg_level[1][0], &chip->eg_level[0][0], 10 * sizeof(unsigned short)); 1275 | 1276 | chip->eg_ch3_l[0] = (chip->eg_ch3_l[1] << 1) | chip->fsm_ch3_sync[1]; 1277 | 1278 | int levelsum = chip->eg_output2 + (chip->eg_csm_tl << 3); 1279 | 1280 | int eg_of = (levelsum & 1024) != 0; 1281 | 1282 | if (eg_of) 1283 | levelsum = 1023; 1284 | 1285 | chip->eg_out = levelsum; 1286 | 1287 | chip->eg_dbg_sync = (chip->ch3_sel[0] & 4) != 0; 1288 | 1289 | chip->eg_debug[1] = chip->eg_debug[0]; 1290 | } 1291 | } 1292 | 1293 | { 1294 | if (chip->clk1) 1295 | { 1296 | chip->op_phase1 = chip->pg_out; 1297 | 1298 | chip->op_sign[1] = chip->op_sign[0]; 1299 | static const int logsin[128] = { 1300 | 0x6c3, 0x58b, 0x4e4, 0x471, 0x41a, 0x3d3, 0x398, 0x365, 0x339, 0x311, 0x2ed, 0x2cd, 0x2af, 0x293, 0x279, 0x261, 1301 | 0x24b, 0x236, 0x222, 0x20f, 0x1fd, 0x1ec, 0x1dc, 0x1cd, 0x1be, 0x1b0, 0x1a2, 0x195, 0x188, 0x17c, 0x171, 0x166, 1302 | 0x15b, 0x150, 0x146, 0x13c, 0x133, 0x129, 0x121, 0x118, 0x10f, 0x107, 0x0ff, 0x0f8, 0x0f0, 0x0e9, 0x0e2, 0x0db, 1303 | 0x0d4, 0x0cd, 0x0c7, 0x0c1, 0x0bb, 0x0b5, 0x0af, 0x0a9, 0x0a4, 0x09f, 0x099, 0x094, 0x08f, 0x08a, 0x086, 0x081, 1304 | 0x07d, 0x078, 0x074, 0x070, 0x06c, 0x068, 0x064, 0x060, 0x05c, 0x059, 0x055, 0x052, 0x04e, 0x04b, 0x048, 0x045, 1305 | 0x042, 0x03f, 0x03c, 0x039, 0x037, 0x034, 0x031, 0x02f, 0x02d, 0x02a, 0x028, 0x026, 0x024, 0x022, 0x020, 0x01e, 1306 | 0x01c, 0x01a, 0x018, 0x017, 0x015, 0x014, 0x012, 0x011, 0x00f, 0x00e, 0x00d, 0x00c, 0x00a, 0x009, 0x008, 0x007, 1307 | 0x007, 0x006, 0x005, 0x004, 0x004, 0x003, 0x002, 0x002, 0x001, 0x001, 0x001, 0x001, 0x000, 0x000, 0x000, 0x000 1308 | }; 1309 | static const int logsin_d[128] = { 1310 | 0x196, 0x07c, 0x04a, 0x035, 0x029, 0x022, 0x01d, 0x019, 0x015, 0x013, 0x012, 0x00f, 0x00e, 0x00d, 0x00d, 0x00c, 1311 | 0x00b, 0x00a, 0x00a, 0x009, 0x009, 0x009, 0x008, 0x007, 0x007, 0x007, 0x007, 0x006, 0x007, 0x006, 0x006, 0x005, 1312 | 0x005, 0x005, 0x005, 0x005, 0x004, 0x005, 0x004, 0x004, 0x005, 0x004, 0x004, 0x003, 0x004, 0x003, 0x003, 0x003, 1313 | 0x003, 0x004, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x002, 0x003, 0x003, 0x003, 0x003, 0x002, 0x002, 1314 | 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x002, 0x001, 0x002, 0x002, 0x002, 0x001, 1315 | 0x001, 0x001, 0x002, 0x002, 0x001, 0x001, 0x002, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 1316 | 0x001, 0x001, 0x001, 0x000, 0x001, 0x000, 0x001, 0x000, 0x001, 0x001, 0x000, 0x000, 0x001, 0x001, 0x001, 0x001, 1317 | 0x000, 0x000, 0x000, 0x001, 0x000, 0x000, 0x001, 0x000, 0x001, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000 1318 | }; 1319 | static const int pow[128] = { 1320 | 0x3f5, 0x3ea, 0x3df, 0x3d4, 0x3c9, 0x3bf, 0x3b4, 0x3a9, 0x39f, 0x394, 0x38a, 0x37f, 0x375, 0x36a, 0x360, 0x356, 1321 | 0x34c, 0x342, 0x338, 0x32e, 0x324, 0x31a, 0x310, 0x306, 0x2fd, 0x2f3, 0x2e9, 0x2e0, 0x2d6, 0x2cd, 0x2c4, 0x2ba, 1322 | 0x2b1, 0x2a8, 0x29e, 0x295, 0x28c, 0x283, 0x27a, 0x271, 0x268, 0x25f, 0x257, 0x24e, 0x245, 0x23c, 0x234, 0x22b, 1323 | 0x223, 0x21a, 0x212, 0x209, 0x201, 0x1f9, 0x1f0, 0x1e8, 0x1e0, 0x1d8, 0x1d0, 0x1c8, 0x1c0, 0x1b8, 0x1b0, 0x1a8, 1324 | 0x1a0, 0x199, 0x191, 0x189, 0x181, 0x17a, 0x172, 0x16b, 0x163, 0x15c, 0x154, 0x14d, 0x146, 0x13e, 0x137, 0x130, 1325 | 0x129, 0x122, 0x11b, 0x114, 0x10c, 0x106, 0x0ff, 0x0f8, 0x0f1, 0x0ea, 0x0e3, 0x0dc, 0x0d6, 0x0cf, 0x0c8, 0x0c2, 1326 | 0x0bb, 0x0b5, 0x0ae, 0x0a8, 0x0a1, 0x09b, 0x094, 0x08e, 0x088, 0x082, 0x07b, 0x075, 0x06f, 0x069, 0x063, 0x05d, 1327 | 0x057, 0x051, 0x04b, 0x045, 0x03f, 0x039, 0x033, 0x02d, 0x028, 0x022, 0x01c, 0x016, 0x011, 0x00b, 0x006, 0x000, 1328 | }; 1329 | static const int pow_d[128] = { 1330 | 0x005, 0x005, 0x005, 0x006, 0x006, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x006, 0x005, 0x005, 1331 | 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x004, 0x005, 1332 | 0x004, 0x004, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x005, 0x004, 0x004, 0x004, 0x005, 0x004, 0x005, 1333 | 0x004, 0x004, 0x004, 0x005, 0x004, 0x004, 0x005, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 1334 | 0x004, 0x003, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x004, 0x003, 0x004, 0x004, 0x004, 1335 | 0x003, 0x003, 0x003, 0x003, 0x004, 0x003, 0x003, 0x003, 0x003, 0x003, 0x004, 0x004, 0x003, 0x003, 0x004, 0x003, 1336 | 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x004, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 1337 | 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x003, 0x002, 0x003, 0x003, 0x003, 0x003, 0x003, 0x002, 0x003, 1338 | }; 1339 | 1340 | chip->op_logsin_base = logsin[(chip->op_phase_index >> 1) & 127]; 1341 | chip->op_logsin_delta = (chip->op_phase_index & 1) != 0 ? 0 : logsin_d[(chip->op_phase_index >> 1) & 127]; 1342 | 1343 | chip->op_eglevel = chip->eg_out; 1344 | 1345 | chip->op_shift[0] = chip->op_att >> 8; 1346 | 1347 | chip->op_pow_base = pow[(chip->op_att >> 1) & 127]; 1348 | chip->op_pow_delta = (chip->op_att & 1) != 0 ? 0 : pow_d[(chip->op_att >> 1) & 127]; 1349 | 1350 | int output = chip->op_pow; 1351 | output = (output << 2) >> chip->op_shift[1]; 1352 | 1353 | if (chip->reg_test_21[1] & 16) 1354 | output ^= 1 << 13; 1355 | 1356 | if (chip->op_sign[0] & 4) 1357 | output ^= 0x3fff; 1358 | 1359 | chip->op_output[0] = output; 1360 | chip->op_output[2] = chip->op_output[1]; 1361 | 1362 | memcpy(&chip->op_op1_0[0][1], &chip->op_op1_0[1][0], 2 * sizeof(unsigned short)); 1363 | memcpy(&chip->op_op1_1[0][1], &chip->op_op1_1[1][0], 2 * sizeof(unsigned short)); 1364 | memcpy(&chip->op_op2[0][1], &chip->op_op2[1][0], 2 * sizeof(unsigned short)); 1365 | 1366 | chip->op_op1_0[0][0] = chip->op_loadfb ? chip->op_output[3] : chip->op_op1_0[1][2]; 1367 | chip->op_op1_1[0][0] = chip->op_loadfb ? chip->op_op1_0[1][2] : chip->op_op1_1[1][2]; 1368 | chip->op_op2[0][0] = chip->op_loadop2 ? chip->op_output[3] : chip->op_op2[1][2]; 1369 | 1370 | int mod1 = 0; 1371 | int mod2 = 0; 1372 | 1373 | if (chip->op_mod_op1_0) 1374 | { 1375 | mod2 |= chip->op_op1_0[1][2]; 1376 | } 1377 | if (chip->op_mod_op1_1) 1378 | { 1379 | mod1 |= chip->op_op1_1[1][2]; 1380 | } 1381 | if (chip->op_mod_op2) 1382 | { 1383 | mod1 |= chip->op_op2[1][2]; 1384 | } 1385 | if (chip->op_mod_prev_0) 1386 | { 1387 | mod2 |= chip->op_output[3]; 1388 | } 1389 | if (chip->op_mod_prev_1) 1390 | { 1391 | mod1 |= chip->op_output[3]; 1392 | } 1393 | if (mod1 & (1 << 13)) 1394 | mod1 |= 1 << 14; 1395 | if (mod2 & (1 << 13)) 1396 | mod2 |= 1 << 14; 1397 | chip->op_mod1 = mod1; 1398 | chip->op_mod2 = mod2; 1399 | 1400 | int mod; 1401 | 1402 | if (chip->op_do_fb) 1403 | { 1404 | if (!chip->op_fb) 1405 | mod = 0; 1406 | else 1407 | { 1408 | mod = chip->op_mod_sum; 1409 | if (mod & (1 << 13)) 1410 | mod |= ~0x3fff; 1411 | 1412 | mod = mod >> (9 - chip->op_fb); 1413 | } 1414 | } 1415 | else 1416 | mod = chip->op_mod_sum; 1417 | 1418 | chip->op_phase2 = mod; 1419 | } 1420 | if (chip->clk2) 1421 | { 1422 | 1423 | int phase = chip->op_phase1 + chip->op_phase2; 1424 | 1425 | int phase2 = phase & 255; 1426 | if (phase & 256) 1427 | phase2 ^= 255; 1428 | 1429 | chip->op_phase_index = phase2; 1430 | 1431 | chip->op_sign[0] = chip->op_sign[1] << 1; 1432 | if (phase & 512) 1433 | chip->op_sign[0] |= 1; 1434 | 1435 | //chip->op_eglevel = 256; // 1436 | int level = chip->op_logsin_base + chip->op_logsin_delta + (chip->op_eglevel << 2); 1437 | if (level & 4096) 1438 | level = 4095; 1439 | chip->op_att = level; 1440 | 1441 | chip->op_shift[1] = chip->op_shift[0]; 1442 | 1443 | chip->op_pow = (chip->op_pow_base + chip->op_pow_delta) | 0x400; 1444 | 1445 | int output = chip->op_output[0]; 1446 | 1447 | if (chip->op_sign[1] & 4) 1448 | output++; 1449 | 1450 | chip->op_output[1] = output & 0x3fff; 1451 | chip->op_output[3] = chip->op_output[2]; 1452 | 1453 | chip->op_loadfb = chip->alg_load_fb; 1454 | chip->op_loadop2 = chip->alg_mod_op1_1_l; 1455 | chip->op_mod_op1_0 = chip->alg_mod_op1_0_l; 1456 | chip->op_mod_op1_1 = chip->alg_mod_op1_1_l; 1457 | chip->op_mod_op2 = chip->alg_mod_op2_l; 1458 | chip->op_mod_prev_0 = chip->alg_mod_prev_0_l; 1459 | chip->op_mod_prev_1 = chip->alg_mod_prev_1_l; 1460 | chip->op_do_fb = chip->alg_do_fb[1]; 1461 | 1462 | chip->op_fb = (chip->reg_connect_fb[0][0] >> 3) & 7; 1463 | 1464 | memcpy(&chip->op_op1_0[1][0], &chip->op_op1_0[0][0], 3 * sizeof(unsigned short)); 1465 | memcpy(&chip->op_op1_1[1][0], &chip->op_op1_1[0][0], 3 * sizeof(unsigned short)); 1466 | memcpy(&chip->op_op2[1][0], &chip->op_op2[0][0], 3 * sizeof(unsigned short)); 1467 | 1468 | int mod = (chip->op_mod1 + chip->op_mod2) >> 1; 1469 | mod &= 0x3fff; 1470 | chip->op_mod_sum = mod; 1471 | } 1472 | } 1473 | { 1474 | int ssg_write1 = ic || write_data; 1475 | 1476 | if (!chip->mclk2) 1477 | { 1478 | int addr2d = write_p_en && ADDRESS_MATCH(0x2d); 1479 | int addr2e = write_p_en && ADDRESS_MATCH(0x2e); 1480 | int addr2f = write_p_en && ADDRESS_MATCH(0x2f); 1481 | chip->ssg_prescaler1[0] = (chip->ssg_prescaler1[1] && !addr2f) || addr2e; 1482 | chip->ssg_prescaler2[0] = (chip->ssg_prescaler2[1] && !addr2f) || addr2d || ic; 1483 | } 1484 | else 1485 | { 1486 | chip->ssg_prescaler1[1] = chip->ssg_prescaler1[0] && !ic; 1487 | chip->ssg_prescaler2[1] = chip->ssg_prescaler2[0]; 1488 | } 1489 | if (!chip->mclk2) 1490 | { 1491 | chip->ssg_div1[0] = !chip->ssg_div1[1]; 1492 | } 1493 | else 1494 | { 1495 | chip->ssg_div1[1] = chip->ssg_div1[0]; 1496 | } 1497 | if (!chip->ssg_div1[0]) 1498 | { 1499 | chip->ssg_div2[0] = !chip->ssg_div2[1]; 1500 | } 1501 | else 1502 | { 1503 | chip->ssg_div2[1] = chip->ssg_div2[0]; 1504 | } 1505 | if (ic) 1506 | { 1507 | chip->ssg_div1[0] = 0; 1508 | chip->ssg_div1[1] = 0; 1509 | chip->ssg_div2[0] = 0; 1510 | chip->ssg_div2[1] = 0; 1511 | } 1512 | 1513 | if (chip->ssg_prescaler2[1]) 1514 | { 1515 | if (chip->ssg_prescaler1[1]) 1516 | { 1517 | chip->ssg_clk = chip->ssg_div1[0]; 1518 | } 1519 | else 1520 | { 1521 | chip->ssg_clk = chip->ssg_div2[0]; 1522 | } 1523 | } 1524 | else 1525 | chip->ssg_clk = chip->mclk2; 1526 | 1527 | chip->ssg_clk1 = !chip->ssg_clk; 1528 | chip->ssg_clk2 = chip->ssg_clk; 1529 | 1530 | if (ic) 1531 | chip->ssg_ssg_addr = 0; 1532 | else if (write_addr) 1533 | chip->ssg_ssg_addr = (chip->data_bus1 & 0xe0) == 0; 1534 | 1535 | if (ic) 1536 | chip->ssg_address = 0; 1537 | else if (write_addr && (chip->data_bus1 & 0xe0) == 0) 1538 | chip->ssg_address = chip->data_bus1 & 0x1f; 1539 | 1540 | int ssg_access = chip->ssg_ssg_addr && (write_data || read1); 1541 | 1542 | if (chip->ssg_egtrig_rst) 1543 | chip->ssg_egtrig = 0; 1544 | 1545 | if (ic) 1546 | { 1547 | chip->ssg_freq_a[0] = chip->data_bus1 & 255; 1548 | chip->ssg_freq_a[1] = chip->data_bus1 & 15; 1549 | chip->ssg_freq_b[0] = chip->data_bus1 & 255; 1550 | chip->ssg_freq_b[1] = chip->data_bus1 & 15; 1551 | chip->ssg_freq_c[0] = chip->data_bus1 & 255; 1552 | chip->ssg_freq_c[1] = chip->data_bus1 & 15; 1553 | chip->ssg_noise = chip->data_bus1 & 31; 1554 | chip->ssg_mode = chip->data_bus1 & 255; 1555 | chip->ssg_level_a = chip->data_bus1 & 31; 1556 | chip->ssg_level_b = chip->data_bus1 & 31; 1557 | chip->ssg_level_c = chip->data_bus1 & 31; 1558 | chip->ssg_env[0] = chip->data_bus1 & 255; 1559 | chip->ssg_env[1] = chip->data_bus1 & 255; 1560 | chip->ssg_envmode = chip->data_bus1 & 15; 1561 | chip->o_gpio_a = chip->data_bus1 & 255; 1562 | chip->o_gpio_b = chip->data_bus1 & 255; 1563 | 1564 | chip->ssg_egtrig = 1; 1565 | } 1566 | else if (ssg_access && ssg_write1) 1567 | { 1568 | switch (chip->ssg_address) 1569 | { 1570 | case 0x0: 1571 | chip->ssg_freq_a[0] = chip->data_bus1 & 255; 1572 | break; 1573 | case 0x1: 1574 | chip->ssg_freq_a[1] = chip->data_bus1 & 15; 1575 | break; 1576 | case 0x2: 1577 | chip->ssg_freq_b[0] = chip->data_bus1 & 255; 1578 | break; 1579 | case 0x3: 1580 | chip->ssg_freq_b[1] = chip->data_bus1 & 15; 1581 | break; 1582 | case 0x4: 1583 | chip->ssg_freq_c[0] = chip->data_bus1 & 255; 1584 | break; 1585 | case 0x5: 1586 | chip->ssg_freq_c[1] = chip->data_bus1 & 15; 1587 | break; 1588 | case 0x6: 1589 | chip->ssg_noise = chip->data_bus1 & 31; 1590 | break; 1591 | case 0x7: 1592 | chip->ssg_mode = chip->data_bus1 & 255; 1593 | break; 1594 | case 0x8: 1595 | chip->ssg_level_a = chip->data_bus1 & 31; 1596 | break; 1597 | case 0x9: 1598 | chip->ssg_level_b = chip->data_bus1 & 31; 1599 | break; 1600 | case 0xa: 1601 | chip->ssg_level_c = chip->data_bus1 & 31; 1602 | break; 1603 | case 0xb: 1604 | chip->ssg_env[0] = chip->data_bus1 & 255; 1605 | break; 1606 | case 0xc: 1607 | chip->ssg_env[1] = chip->data_bus1 & 255; 1608 | break; 1609 | case 0xd: 1610 | chip->ssg_envmode = chip->data_bus1 & 15; 1611 | chip->ssg_egtrig = 1; 1612 | break; 1613 | case 0xe: 1614 | chip->o_gpio_a = chip->data_bus1 & 255; 1615 | break; 1616 | case 0xf: 1617 | chip->o_gpio_b = chip->data_bus1 & 255; 1618 | break; 1619 | } 1620 | } 1621 | if (ssg_access && read1) 1622 | { 1623 | switch (chip->ssg_address) 1624 | { 1625 | case 0x0: 1626 | chip->data_bus1 &= ~255; 1627 | chip->data_bus1 |= chip->ssg_freq_a[0] & 255; 1628 | break; 1629 | case 0x1: 1630 | chip->data_bus1 &= ~15; 1631 | chip->data_bus1 |= chip->ssg_freq_a[1] & 15; 1632 | break; 1633 | case 0x2: 1634 | chip->data_bus1 &= ~255; 1635 | chip->data_bus1 |= chip->ssg_freq_b[0] & 255; 1636 | break; 1637 | case 0x3: 1638 | chip->data_bus1 &= ~15; 1639 | chip->data_bus1 |= chip->ssg_freq_b[1] & 15; 1640 | break; 1641 | case 0x4: 1642 | chip->data_bus1 &= ~255; 1643 | chip->data_bus1 |= chip->ssg_freq_c[0] & 255; 1644 | break; 1645 | case 0x5: 1646 | chip->data_bus1 &= ~15; 1647 | chip->data_bus1 |= chip->ssg_freq_c[1] & 15; 1648 | break; 1649 | case 0x6: 1650 | chip->data_bus1 &= ~31; 1651 | chip->data_bus1 |= chip->ssg_noise & 31; 1652 | break; 1653 | case 0x7: 1654 | chip->data_bus1 &= ~255; 1655 | chip->data_bus1 |= chip->ssg_mode & 255; 1656 | break; 1657 | case 0x8: 1658 | chip->data_bus1 &= ~31; 1659 | chip->data_bus1 |= chip->ssg_level_a & 31; 1660 | break; 1661 | case 0x9: 1662 | chip->data_bus1 &= ~31; 1663 | chip->data_bus1 |= chip->ssg_level_b & 31; 1664 | break; 1665 | case 0xa: 1666 | chip->data_bus1 &= ~31; 1667 | chip->data_bus1 |= chip->ssg_level_c & 31; 1668 | break; 1669 | case 0xb: 1670 | chip->data_bus1 &= ~255; 1671 | chip->data_bus1 |= chip->ssg_env[0] & 255; 1672 | break; 1673 | case 0xc: 1674 | chip->data_bus1 &= ~255; 1675 | chip->data_bus1 |= chip->ssg_env[1] & 255; 1676 | break; 1677 | case 0xd: 1678 | chip->data_bus1 &= ~15; 1679 | chip->data_bus1 |= chip->ssg_envmode & 15; 1680 | break; 1681 | case 0xe: 1682 | chip->data_bus1 &= ~255; 1683 | chip->data_bus1 |= chip->input.gpio_a & 255; 1684 | break; 1685 | case 0xf: 1686 | chip->data_bus1 &= ~255; 1687 | chip->data_bus1 |= chip->input.gpio_b & 255; 1688 | break; 1689 | } 1690 | } 1691 | 1692 | if (chip->ssg_clk1) 1693 | { 1694 | chip->ssg_envadd = (chip->ssg_eg_of[1] & 4) != 0 && (chip->ssg_sel[1] & 8) != 0; 1695 | chip->ssg_envcnt[1] = chip->ssg_hold[0] ? 31 : chip->ssg_envcnt[0]; 1696 | chip->ssg_dir[1] = chip->ssg_dir[0]; 1697 | chip->ssg_hold[1] = chip->ssg_hold[0]; 1698 | chip->ssg_t2[1] = chip->ssg_t2[0]; 1699 | 1700 | chip->ssg_egtrig_s = chip->ssg_egtrig; 1701 | 1702 | chip->ssg_eg_sel_l = (chip->ssg_sel[1] & 8) != 0; 1703 | 1704 | chip->ssg_sel[0] = chip->ssg_sel[1] << 1; 1705 | chip->ssg_sel[0] |= (chip->ssg_sel[1] & 7) == 0 && !ic; 1706 | 1707 | chip->ssg_sel_freq = 0; 1708 | if (chip->ssg_sel[1] & 1) 1709 | chip->ssg_sel_freq |= (chip->ssg_freq_c[1] << 8) | chip->ssg_freq_c[0]; 1710 | if (chip->ssg_sel[1] & 2) 1711 | chip->ssg_sel_freq |= (chip->ssg_freq_b[1] << 8) | chip->ssg_freq_b[0]; 1712 | if (chip->ssg_sel[1] & 4) 1713 | chip->ssg_sel_freq |= (chip->ssg_freq_a[1] << 8) | chip->ssg_freq_a[0]; 1714 | if (chip->ssg_sel[1] & 8) 1715 | chip->ssg_sel_freq |= (chip->ssg_env[1] << 8) | chip->ssg_env[0]; 1716 | 1717 | int cnt = chip->ssg_freq_cnt[7] + 1; 1718 | int of = (cnt & 0x1000) != 0; 1719 | chip->ssg_freq_cnt[0] = cnt & 0xfff; 1720 | chip->ssg_freq_cnt[4] = chip->ssg_freq_cnt[3]; 1721 | chip->ssg_freq_cnt[6] = chip->ssg_freq_cnt[5]; 1722 | 1723 | chip->ssg_cnt_of[1] = chip->ssg_cnt_of[0]; 1724 | 1725 | if (chip->ssg_sel[1] & 8) 1726 | chip->ssg_sign_toggle = chip->ssg_cnt_of[0] & 7; 1727 | else 1728 | chip->ssg_sign_toggle = 0; 1729 | 1730 | chip->ssg_freq_cnt2[1] = chip->ssg_freq_cnt2[0]; 1731 | chip->ssg_freq_cnt2[3] = chip->ssg_freq_cnt2[2]; 1732 | chip->ssg_freq_cnt2[5] = chip->ssg_freq_cnt2[4]; 1733 | chip->ssg_freq_cnt2[7] = chip->ssg_freq_cnt2[6]; 1734 | 1735 | chip->ssg_sign[1] = chip->ssg_sign[0]; 1736 | 1737 | int cnt_of = !chip->ssg_cnt_reload && (chip->ssg_sel_freq_l - chip->ssg_cnt_of_l < chip->ssg_freq_cnt2[0]); 1738 | 1739 | chip->ssg_cnt2_add = (chip->ssg_sel[1] & 8) != 0 && of; 1740 | 1741 | chip->ssg_sel_eg_l[0] = (chip->ssg_sel[1] & 8) != 0; 1742 | 1743 | chip->ssg_eg_of[0] = (chip->ssg_eg_of[1] << 1) | cnt_of; 1744 | 1745 | int fr_rst = chip->ssg_ch_of || ((cnt_of || chip->ssg_cnt_reload) && chip->ssg_sel_eg_l[1]); 1746 | 1747 | chip->ssg_freq_cnt[2] = fr_rst ? 0 : chip->ssg_freq_cnt[1]; 1748 | 1749 | chip->ssg_fr_rst_l = fr_rst; 1750 | 1751 | chip->ssg_noise_add = (chip->ssg_sel[1] & 1) != 0; 1752 | 1753 | chip->ssg_noise_cnt[1] = chip->ssg_noise_cnt[0]; 1754 | 1755 | int noise_of = chip->ssg_noise <= (chip->ssg_noise_cnt[0] >> 1); 1756 | 1757 | chip->ssg_noise_of = noise_of && chip->ssg_noise_of_low; 1758 | 1759 | chip->ssg_noise_step = chip->ssg_noise_of || ic; 1760 | } 1761 | if (chip->ssg_clk2) 1762 | { 1763 | int sum = chip->ssg_envcnt[1] + chip->ssg_envadd; 1764 | int of = (sum & 32) != 0; 1765 | chip->ssg_envcnt[0] = chip->ssg_egtrig_s ? 0 : sum & 31; 1766 | 1767 | int dir = of && (chip->ssg_envmode & 2) != 0 && !chip->ssg_hold[1]; 1768 | chip->ssg_dir[0] = chip->ssg_egtrig_s ? 0 : chip->ssg_dir[1] ^ dir; 1769 | 1770 | chip->ssg_hold[0] = chip->ssg_egtrig_s ? 0 : chip->ssg_hold[1] || (of && (chip->ssg_envmode & 1) != 0); 1771 | 1772 | chip->ssg_t2[0] = chip->ssg_egtrig_s ? 0 : chip->ssg_t2[1] || of; 1773 | 1774 | chip->ssg_egtrig_rst = chip->ssg_egtrig_s && chip->ssg_eg_sel_l; 1775 | 1776 | 1777 | chip->ssg_sel[1] = chip->ssg_sel[0]; 1778 | 1779 | chip->ssg_freq_cnt[1] = chip->ssg_freq_cnt[0]; 1780 | chip->ssg_freq_cnt[3] = chip->ssg_freq_cnt[2]; 1781 | chip->ssg_freq_cnt[5] = chip->ssg_freq_cnt[4]; 1782 | chip->ssg_freq_cnt[7] = chip->ssg_freq_cnt[6]; 1783 | 1784 | int cnt_of = (chip->ssg_sel_freq & 0xfff) <= chip->ssg_freq_cnt[0]; 1785 | 1786 | chip->ssg_cnt_of_l = cnt_of; 1787 | chip->ssg_sel_freq_l = (chip->ssg_sel_freq >> 12) & 0xf; 1788 | 1789 | chip->ssg_cnt_of[0] = (chip->ssg_cnt_of[1] << 1) | cnt_of; 1790 | 1791 | if (ic) 1792 | chip->ssg_sign[0] = 0; 1793 | else 1794 | chip->ssg_sign[0] = chip->ssg_sign[1] ^ chip->ssg_sign_toggle; 1795 | 1796 | int cnt = chip->ssg_freq_cnt2[7] + chip->ssg_cnt2_add; 1797 | chip->ssg_freq_cnt2[0] = cnt & 0xf; 1798 | chip->ssg_freq_cnt2[2] = chip->ssg_fr_rst_l ? 0 : chip->ssg_freq_cnt2[1]; 1799 | chip->ssg_freq_cnt2[4] = chip->ssg_freq_cnt2[3]; 1800 | chip->ssg_freq_cnt2[6] = chip->ssg_freq_cnt2[5]; 1801 | 1802 | chip->ssg_sel_eg_l[1] = chip->ssg_sel_eg_l[0]; 1803 | 1804 | chip->ssg_ch_of = (!chip->ssg_sel_eg_l[0] && cnt_of) || ic; 1805 | 1806 | chip->ssg_cnt_reload = chip->ssg_sel_eg_l[0] && chip->ssg_egtrig_s; 1807 | 1808 | chip->ssg_eg_of[1] = chip->ssg_eg_of[0]; 1809 | 1810 | 1811 | chip->ssg_noise_cnt[0] = chip->ssg_noise_step ? 0 : ((chip->ssg_noise_cnt[1] + chip->ssg_noise_add) & 63); 1812 | 1813 | chip->ssg_noise_of_low = (chip->ssg_noise_cnt[1] & 1) != 0 && chip->ssg_noise_add; 1814 | 1815 | } 1816 | 1817 | if (!chip->ssg_noise_step) 1818 | { 1819 | int bit = ((chip->ssg_noise_lfsr[1] >> 16) ^ (chip->ssg_noise_lfsr[1] >> 13)) & 1; 1820 | 1821 | if ((chip->ssg_noise_lfsr[1] & 0x1ffff) == 0) 1822 | bit |= 1; 1823 | 1824 | chip->ssg_noise_lfsr[0] = (chip->ssg_noise_lfsr[1] << 1) | bit; 1825 | } 1826 | else 1827 | { 1828 | chip->ssg_noise_lfsr[1] = ic ? 0 : chip->ssg_noise_lfsr[0]; 1829 | } 1830 | 1831 | if (chip->ssg_clk2) 1832 | chip->ssg_noise_bit = (chip->ssg_noise_lfsr[1] >> 16) & 1; 1833 | 1834 | int envlevel = chip->ssg_hold[0] ? 31 : chip->ssg_envcnt[0]; 1835 | envlevel = (chip->ssg_dir[0] ^ ((chip->ssg_envmode >> 2) & 1)) == 0 ? (envlevel ^ 31) : envlevel; 1836 | envlevel = (chip->ssg_t2[0] && (chip->ssg_envmode & 8) == 0) ? 0 : envlevel; 1837 | 1838 | int vol_a = (chip->ssg_level_a & 0x10) != 0 ? envlevel : (((chip->ssg_level_a & 15) << 1) | 1); 1839 | int vol_b = (chip->ssg_level_b & 0x10) != 0 ? envlevel : (((chip->ssg_level_b & 15) << 1) | 1); 1840 | int vol_c = (chip->ssg_level_c & 0x10) != 0 ? envlevel : (((chip->ssg_level_c & 15) << 1) | 1); 1841 | 1842 | int sign_a = ((chip->ssg_mode & 1) == 0 && (chip->ssg_sign[0] & 1) != 0) || ((chip->ssg_mode & 8) == 0 && chip->ssg_noise_bit); 1843 | int sign_b = ((chip->ssg_mode & 2) == 0 && (chip->ssg_sign[0] & 2) != 0) || ((chip->ssg_mode & 16) == 0 && chip->ssg_noise_bit); 1844 | int sign_c = ((chip->ssg_mode & 4) == 0 && (chip->ssg_sign[0] & 4) != 0) || ((chip->ssg_mode & 32) == 0 && chip->ssg_noise_bit); 1845 | 1846 | static const float volume_lut[32] = { 1847 | 0.0000, 0.0000, 0.0049, 0.0075, 0.0105, 0.0131, 0.0156, 0.0183, 1848 | 0.0228, 0.0276, 0.0321, 0.0367, 0.0448, 0.0535, 0.0626, 0.0713, 1849 | 0.0884, 0.1057, 0.1225, 0.1392, 0.1691, 0.2013, 0.2348, 0.2670, 1850 | 0.3307, 0.3951, 0.4573, 0.5196, 0.6316, 0.7528, 0.8787, 1.0000 1851 | }; 1852 | 1853 | 1854 | chip->o_analog_a = volume_lut[sign_a ? 0 : vol_a]; 1855 | chip->o_analog_b = volume_lut[sign_b ? 0 : vol_b]; 1856 | chip->o_analog_c = volume_lut[sign_c ? 0 : vol_c]; 1857 | 1858 | chip->o_gpio_a_d = (chip->ssg_mode & 64) == 0; 1859 | chip->o_gpio_b_d = (chip->ssg_mode & 128) == 0; 1860 | } 1861 | 1862 | { 1863 | if (chip->clk1) 1864 | { 1865 | chip->ac_accum[0] = chip->ac_accum[1] + chip->ac_fm_output; 1866 | 1867 | chip->ac_sync[1] = chip->ac_sync[0]; 1868 | } 1869 | if (chip->clk2) 1870 | { 1871 | if (chip->alg_output_l) 1872 | { 1873 | chip->ac_fm_output = chip->op_output[2] & 0x1fff; 1874 | if (chip->op_output[2] & 0x2000) 1875 | chip->ac_fm_output |= 0x3e000; 1876 | } 1877 | else 1878 | chip->ac_fm_output = 0; 1879 | 1880 | chip->ac_accum[1] = (chip->ac_sync[1] & 2) != 0 ? 0 : chip->ac_accum[0]; 1881 | chip->ac_accum_l = chip->ac_accum[0]; 1882 | 1883 | chip->ac_sync[0] = (chip->ac_sync[1] << 1) | chip->fsm_acc_sync[1]; 1884 | } 1885 | 1886 | int load = (chip->ac_sync[0] & 4) != 0 && (chip->ac_sync[1] & 4) == 0; 1887 | if (chip->aclk2) 1888 | chip->ac_load2_l = (chip->ac_sync[0] & 1) != 0; 1889 | 1890 | int load2 = (chip->ac_sync[0] & 1) != 0 && !chip->ac_load2_l; 1891 | 1892 | if (load) 1893 | { 1894 | chip->ac_clip_l = (chip->ac_accum_l & 0x38000) == 0x30000 1895 | || (chip->ac_accum_l & 0x38000) == 0x28000 1896 | || (chip->ac_accum_l & 0x38000) == 0x20000; 1897 | chip->ac_clip_h = (chip->ac_accum_l & 0x38000) == 0x18000 1898 | || (chip->ac_accum_l & 0x38000) == 0x10000 1899 | || (chip->ac_accum_l & 0x38000) == 0x8000; 1900 | } 1901 | 1902 | if (chip->aclk2) 1903 | { 1904 | chip->ac_shifter1[0] = chip->ac_shifter1[1] >> 1; 1905 | if (load) 1906 | { 1907 | chip->ac_shifter1[0] = chip->ac_accum_l & 0x7fff; 1908 | if ((chip->ac_accum_l & 0x20000) == 0) 1909 | chip->ac_shifter1[0] |= 0x8000; 1910 | chip->dbg_out = chip->ac_accum_l; 1911 | } 1912 | 1913 | chip->ac_shifter2[0] = chip->ac_shifter2[1] >> 1; 1914 | chip->ac_shifter2[0] |= (chip->ac_shifter1[1] & 1) << 24; 1915 | if (chip->ac_clip_l) 1916 | chip->ac_shifter2[0] |= 1 << 22; 1917 | if (chip->ac_clip_h) 1918 | chip->ac_shifter2[0] &= ~(1 << 22); 1919 | 1920 | int sync = (chip->ac_sync[0] & 128) != 0 && (chip->ac_sync[1] & 128) != 0; 1921 | chip->ac_sync2[0] = (chip->ac_sync2[1] << 1) | sync; 1922 | 1923 | int bit = 0; 1924 | 1925 | if (sync) 1926 | { 1927 | bit |= chip->ac_sign; 1928 | } 1929 | if (chip->ac_sync2[1] & 1) 1930 | { 1931 | bit |= (chip->ac_exp & (1 + 4 + 16 + 64)) != 0; 1932 | } 1933 | if (chip->ac_sync2[1] & 2) 1934 | { 1935 | bit |= (chip->ac_exp & (2 + 4 + 32 + 64)) != 0; 1936 | } 1937 | if (chip->ac_sync2[1] & 4) 1938 | { 1939 | bit |= (chip->ac_exp & (8 + 16 + 32 + 64)) != 0; 1940 | } 1941 | if (!(chip->ac_sync2[1] & 7) && !sync) 1942 | { 1943 | if (chip->ac_exp & 1) 1944 | bit |= (chip->ac_shifter2[1] & 1) != 0; 1945 | if (chip->ac_exp & 2) 1946 | bit |= (chip->ac_shifter2[1] & 2) != 0; 1947 | if (chip->ac_exp & 4) 1948 | bit |= (chip->ac_shifter2[1] & 4) != 0; 1949 | if (chip->ac_exp & 8) 1950 | bit |= (chip->ac_shifter2[1] & 8) != 0; 1951 | if (chip->ac_exp & 16) 1952 | bit |= (chip->ac_shifter2[1] & 16) != 0; 1953 | if (chip->ac_exp & 32) 1954 | bit |= (chip->ac_shifter2[1] & 32) != 0; 1955 | if (chip->ac_exp & 64) 1956 | bit |= (chip->ac_shifter2[1] & 64) != 0; 1957 | } 1958 | chip->ac_out[0] = (chip->ac_out[1] << 1) | bit; 1959 | } 1960 | if (chip->aclk1) 1961 | { 1962 | chip->ac_shifter1[1] = chip->ac_shifter1[0]; 1963 | chip->ac_shifter2[1] = chip->ac_shifter2[0]; 1964 | 1965 | chip->ac_sync2[1] = chip->ac_sync2[0]; 1966 | chip->ac_out[1] = chip->ac_out[0]; 1967 | } 1968 | 1969 | if (load2) 1970 | { 1971 | chip->ac_hi_bits = (chip->ac_shifter2[1] >> 15) & 127; 1972 | } 1973 | if (chip->ac_sync[0] & 8) 1974 | { 1975 | chip->ac_exp = 0; 1976 | int sign = (chip->ac_hi_bits & 64) != 0; 1977 | int ss = chip->ac_hi_bits & 63; 1978 | if (!sign) 1979 | ss ^= 63; 1980 | if (ss & 32) 1981 | chip->ac_exp |= 64; 1982 | if ((ss & 48) == 16) 1983 | chip->ac_exp |= 32; 1984 | if ((ss & 56) == 8) 1985 | chip->ac_exp |= 16; 1986 | if ((ss & 60) == 4) 1987 | chip->ac_exp |= 8; 1988 | if ((ss & 62) == 2) 1989 | chip->ac_exp |= 4; 1990 | if (ss == 1) 1991 | chip->ac_exp |= 2; 1992 | if (ss == 0) 1993 | chip->ac_exp |= 1; 1994 | 1995 | chip->ac_sign = sign; 1996 | } 1997 | 1998 | chip->o_opo = (chip->ac_out[1] & 2) != 0; 1999 | } 2000 | 2001 | { 2002 | if (chip->clk1) 2003 | { 2004 | int inc = chip->busy_cnt_en[1]; 2005 | int sum = chip->busy_cnt[1] + inc; 2006 | int of = (sum & 16) != 0; 2007 | if (ic) 2008 | chip->busy_cnt[0] = 0; 2009 | else 2010 | chip->busy_cnt[0] = sum & 15; 2011 | 2012 | chip->busy_cnt_en[0] = write_1_en || (chip->busy_cnt_en[1] && !(of || ic)); 2013 | 2014 | } 2015 | if (chip->clk2) 2016 | { 2017 | chip->busy_cnt[1] = chip->busy_cnt[0]; 2018 | chip->busy_cnt_en[1] = chip->busy_cnt_en[0]; 2019 | } 2020 | } 2021 | { 2022 | if (chip->clk1) 2023 | { 2024 | int testdata; 2025 | chip->read_test = (chip->reg_test_21[1] & 64) != 0; 2026 | testdata = chip->op_output[3] & 0x3fff; 2027 | testdata |= (chip->pg_dbg[1] & 1) << 15; 2028 | if (chip->eg_debug[1] & 0x200) 2029 | testdata |= 1 << 14; 2030 | 2031 | if (chip->reg_test_21[1] & 128) 2032 | chip->read_op = testdata & 255; 2033 | else 2034 | chip->read_op = testdata >> 8; 2035 | } 2036 | 2037 | if (chip->read_test) 2038 | { 2039 | chip->read_data = chip->read_op; 2040 | } 2041 | if (read1) 2042 | { 2043 | chip->read_data = chip->data_bus1; 2044 | } 2045 | if (!chip->read_test && !read1) 2046 | { 2047 | chip->read_data = 0; // FIXME: floating bus 2048 | if (chip->busy_cnt_en[1]) 2049 | chip->read_data |= 128; 2050 | if (chip->timer_a_status[1]) 2051 | chip->read_data |= 1; 2052 | if (chip->timer_b_status[1]) 2053 | chip->read_data |= 2; 2054 | } 2055 | 2056 | if (!read0) 2057 | { 2058 | chip->o_data = chip->read_data; 2059 | } 2060 | } 2061 | } 2062 | --------------------------------------------------------------------------------