├── LICENSE ├── LICENSE.asl ├── LICENSE.nvdla ├── README.md ├── cl_memdut ├── build │ ├── README.md │ ├── constraints │ │ ├── cl_pnr_user.xdc │ │ └── cl_synth_user.xdc │ └── scripts │ │ ├── create_dcp_from_cl.tcl │ │ ├── encrypt.tcl │ │ └── synth_cl_memdut.tcl ├── design │ ├── axil_slave.sv │ ├── cl_dma_pcis_slv.sv │ ├── cl_id_defines.vh │ ├── cl_ila.sv │ ├── cl_memdut.sv │ ├── cl_memdut_defines.vh │ ├── cl_memdut_pkg.sv │ ├── cl_memdut_wrap.sv │ ├── cl_vio.sv │ └── simple_dut │ │ ├── NV_FPGA_unit_checkbox_mem_dut.v │ │ ├── NV_FPGA_unit_checkbox_mem_dut_apb_slave.v │ │ ├── NV_FPGA_unit_checkbox_mem_dut_axi_256_256.v │ │ ├── NV_FPGA_unit_checkbox_mem_dut_axi_req_256.v │ │ ├── NV_FPGA_unit_checkbox_mem_dut_axi_req_gen_256.v │ │ ├── NV_FPGA_unit_checkbox_mem_dut_axi_resp_256.v │ │ ├── nv_ram_rws_256x128.v │ │ ├── nv_ram_rws_256x27.v │ │ ├── nv_ram_rws_512x256.v │ │ └── nv_ram_rws_512x32.v ├── software │ ├── include │ │ ├── memdut_regs.h │ │ └── test_utils.h │ └── src │ │ ├── Makefile │ │ ├── test_memdut.c │ │ ├── test_null.c │ │ └── test_utils.c └── verif │ ├── README.md │ ├── scripts │ ├── Makefile │ ├── Makefile.vcs │ ├── top.vcs.f │ └── waves.tcl │ └── tests │ └── test_null.sv ├── cl_nvdla ├── build │ ├── README.md │ ├── constraints │ │ ├── cl_pnr_user.xdc │ │ └── cl_synth_user.xdc │ └── scripts │ │ ├── README.md │ │ ├── create_dcp_from_cl.tcl │ │ ├── download_f1 │ │ ├── encrypt.tcl │ │ ├── filelist.sh │ │ ├── synth_cl_nvdla.tcl │ │ └── upload_f1 ├── design │ ├── cl_dma_pcis_slv.sv │ ├── cl_id_defines.vh │ ├── cl_ila.sv │ ├── cl_nvdla.sv │ ├── cl_nvdla_defines.vh │ ├── cl_nvdla_pkg.sv │ ├── cl_nvdla_wrap.sv │ ├── cl_sim_mem.sv │ ├── cl_sim_mem_wrap.sv │ ├── cl_vio.sv │ └── rams │ │ ├── nv_ram_model │ │ ├── nv_ram_rws_128x18.v │ │ ├── nv_ram_rws_16x256.v │ │ ├── nv_ram_rws_16x272.v │ │ ├── nv_ram_rws_16x64.v │ │ ├── nv_ram_rws_256x3.v │ │ ├── nv_ram_rws_256x512.v │ │ ├── nv_ram_rws_256x7.v │ │ ├── nv_ram_rws_32x16.v │ │ ├── nv_ram_rws_32x512.v │ │ ├── nv_ram_rws_32x544.v │ │ ├── nv_ram_rws_32x768.v │ │ ├── nv_ram_rws_512x512.v │ │ ├── nv_ram_rws_512x64.v │ │ ├── nv_ram_rws_64x10.v │ │ ├── nv_ram_rws_64x1024.v │ │ ├── nv_ram_rws_64x1088.v │ │ ├── nv_ram_rws_64x116.v │ │ ├── nv_ram_rws_64x18.v │ │ ├── nv_ram_rwsp_128x11.v │ │ ├── nv_ram_rwsp_128x6.v │ │ ├── nv_ram_rwsp_160x16.v │ │ ├── nv_ram_rwsp_160x514.v │ │ ├── nv_ram_rwsp_160x65.v │ │ ├── nv_ram_rwsp_20x289.v │ │ ├── nv_ram_rwsp_245x514.v │ │ ├── nv_ram_rwsp_256x11.v │ │ ├── nv_ram_rwsp_32x32.v │ │ ├── nv_ram_rwsp_61x514.v │ │ ├── nv_ram_rwsp_61x64.v │ │ ├── nv_ram_rwsp_61x65.v │ │ ├── nv_ram_rwsp_80x14.v │ │ ├── nv_ram_rwsp_80x16.v │ │ ├── nv_ram_rwsp_80x256.v │ │ ├── nv_ram_rwsp_80x514.v │ │ ├── nv_ram_rwsp_80x65.v │ │ ├── nv_ram_rwst_256x8.v │ │ ├── nv_ram_rwsthp_19x32.v │ │ ├── nv_ram_rwsthp_19x4.v │ │ ├── nv_ram_rwsthp_19x80.v │ │ ├── nv_ram_rwsthp_60x168.v │ │ ├── nv_ram_rwsthp_60x21.v │ │ ├── nv_ram_rwsthp_80x15.v │ │ ├── nv_ram_rwsthp_80x72.v │ │ └── nv_ram_rwsthp_80x9.v ├── software │ ├── src │ │ ├── Makefile │ │ ├── test_null.c │ │ ├── trace_test.c │ │ └── trace_test_impl.c │ └── traces │ │ ├── bdma_sanity │ │ ├── bdma_sanity.cfg │ │ ├── bdma_sanity_input.dat │ │ └── bdma_sanity_output.dat │ │ └── cdp_8x8x32_lrn3_int8_1 │ │ ├── CDP_0_input.dat │ │ ├── CDP_0_output.dat │ │ └── cdp_8x8x32_lrn3_int8_1.cfg └── verif │ ├── README.md │ ├── regression │ ├── Makefile │ ├── nv_large_random │ ├── nv_large_sanity │ ├── nv_medium_1024_full_random │ ├── nv_medium_1024_full_sanity │ ├── nv_medium_512_random │ ├── nv_medium_512_sanity │ ├── nv_small_256_full_random │ ├── nv_small_256_full_sanity │ ├── nv_small_256_random │ ├── nv_small_256_sanity │ ├── nv_small_random │ └── nv_small_sanity │ ├── scripts │ ├── Makefile │ ├── Makefile.vcs │ ├── top.vcs.f │ └── waves.tcl │ └── tests │ ├── cosim_test.sv │ ├── test_null.sv │ └── trace_test.sv └── common ├── design ├── transactors │ ├── cfg │ │ └── cl_cfgreg.sv │ └── irq │ │ ├── cl_irq_up.v │ │ ├── cl_irq_up_bit.v │ │ └── simulate_x_tick.vh ├── vlibs │ ├── NV_BLKBOX_SINK.v │ ├── NV_CLK_gate_power.v │ ├── p_SSYNC2DO_C_PP.v │ ├── p_SSYNC3DO_C_PPP.v │ ├── sync2d_c_pp.v │ └── sync3d_c_ppp.v └── xilinx_ip │ └── README.md ├── software ├── include │ ├── cl_common_utils.h │ ├── cosim_top.h │ ├── sh_dpi_tasks.h │ └── shm_lib │ │ ├── shm_defs.h │ │ └── simdb.hpp └── src │ ├── cl_common_utils.c │ ├── cosim_top.cpp │ └── sh_dpi_tasks.c ├── trace_player ├── Makefile.inc ├── build │ └── Makefile ├── include │ ├── trace_player.h │ ├── trace_player_cmd.h │ ├── trace_player_impl.h │ ├── trace_player_intr.h │ ├── trace_player_mem.h │ ├── trace_player_parser.h │ ├── trace_player_reg.h │ ├── trace_player_sync.h │ ├── trace_player_thread.h │ └── trace_player_utils.h ├── parser │ └── nvdla_trace_parser.py ├── src │ ├── trace_player.c │ ├── trace_player_cmd.c │ ├── trace_player_intr.c │ ├── trace_player_mem.c │ ├── trace_player_reg.c │ ├── trace_player_sync.c │ └── trace_player_thread.c └── test │ ├── test_trace │ ├── test_trace.cfg │ ├── test_trace_input.dat │ └── test_trace_output.dat │ ├── trace_player_test.c │ └── trace_player_test_impl.c └── verif └── include └── sh_dpi_tasks.svh /LICENSE: -------------------------------------------------------------------------------- 1 | This repository contains some files that are licensed under the Amazon 2 | Software License, and some files that are licensed under the NVIDIA Open 3 | NVDLA License and Agreement v1.0. When editing, redistributing, or 4 | contributing to this repository, please ensure that you are aware of the 5 | terms of each component that you are working with. 6 | 7 | The Amazon Software License is included in this distribution as 8 | 'LICENSE.asl'; the NVIDIA Open NVDLA License and Agreement v1.0 is included 9 | in this distribution as 'LICENSE.nvdla'. 10 | -------------------------------------------------------------------------------- /LICENSE.asl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nvdla/vp_awsfpga/ea0bfe2f60226a319fbf6e7a0cf1ef9918461925/LICENSE.asl -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Virtual Platform On AWS FPGA 2 | ## NVDLA 3 | 4 | The NVIDIA Deep Learning Accelerator (NVDLA) is a free and open architecture that promotes a standard way to design deep learning inference accelerators. With its modular architecture, NVDLA is scalable, highly configurable, and designed to simplify integration and portability. Learn more about NVDLA on the project web page. 5 | 6 | 7 | 8 | ## Online Documentation 9 | 10 | You can find the latest NVDLA Virtual Platform documentation for AWS FPGA [here](http://nvdla.org/vp_fpga.html). 11 | 12 | ## NVIDIA Sample AFI 13 | 14 | nv_small: agfi-05d68b424ef03f66e 15 | nv_small_256: agfi-04aac7585d90d7b7b 16 | nv_small_256_full: agfi-0d9cf88f1002a1efb 17 | nv_medium_512: agfi-06497597cc7376b4c 18 | nv_medium_1024_full: agfi-0d4e2503b5f71d257 19 | nv_large: agfi-0f541fc533cba53ef 20 | 21 | ## EC2 FPGA Hardware and Software Development Kits version 22 | 23 | v1.4.0 24 | -------------------------------------------------------------------------------- /cl_memdut/build/constraints/cl_pnr_user.xdc: -------------------------------------------------------------------------------- 1 | # This contains the CL specific constraints for Top level PNR 2 | 3 | # False paths between main clock and tck 4 | set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]] 5 | set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck] 6 | set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] 7 | -------------------------------------------------------------------------------- /cl_memdut/build/constraints/cl_synth_user.xdc: -------------------------------------------------------------------------------- 1 | # This contains the CL specific constraints for synthesis at the CL level 2 | 3 | 4 | -------------------------------------------------------------------------------- /cl_memdut/build/scripts/encrypt.tcl: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | # NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | # TODO: 20 | # Add check if CL_DIR and HDK_SHELL_DIR directories exist 21 | # Add check if /build and /build/src_port_encryption directories exist 22 | # Add check if the vivado_keyfile exist 23 | 24 | set HDK_SHELL_DIR $::env(HDK_SHELL_DIR) 25 | set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR) 26 | set CL_DIR $::env(CL_DIR) 27 | 28 | set TARGET_DIR $CL_DIR/build/src_post_encryption 29 | set UNUSED_TEMPLATES_DIR $HDK_SHELL_DESIGN_DIR/interfaces 30 | 31 | 32 | # Remove any previously encrypted files, that may no longer be used 33 | exec rm -rf $TARGET_DIR/* 34 | 35 | #---- Developr would replace this section with design files ---- 36 | 37 | ## Change file names and paths below to reflect your CL area. DO NOT include AWS RTL files. 38 | file copy -force $CL_DIR/design/cl_memdut_defines.vh $TARGET_DIR 39 | file copy -force $CL_DIR/design/cl_id_defines.vh $TARGET_DIR 40 | file copy -force $CL_DIR/design/cl_memdut_pkg.sv $TARGET_DIR 41 | file copy -force $CL_DIR/design/cl_memdut_wrap.sv $TARGET_DIR 42 | file copy -force $CL_DIR/design/cl_memdut.sv $TARGET_DIR 43 | file copy -force $CL_DIR/design/axil_slave.sv $TARGET_DIR 44 | file copy -force $CL_DIR/design/cl_dma_pcis_slv.sv $TARGET_DIR 45 | file copy -force $CL_DIR/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut.v $TARGET_DIR 46 | file copy -force $CL_DIR/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_apb_slave.v $TARGET_DIR 47 | file copy -force $CL_DIR/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_256_256.v $TARGET_DIR 48 | file copy -force $CL_DIR/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_256.v $TARGET_DIR 49 | file copy -force $CL_DIR/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_gen_256.v $TARGET_DIR 50 | file copy -force $CL_DIR/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_resp_256.v $TARGET_DIR 51 | file copy -force $CL_DIR/design/simple_dut/nv_ram_rws_256x128.v $TARGET_DIR 52 | file copy -force $CL_DIR/design/simple_dut/nv_ram_rws_256x27.v $TARGET_DIR 53 | file copy -force $CL_DIR/design/simple_dut/nv_ram_rws_512x256.v $TARGET_DIR 54 | file copy -force $CL_DIR/design/simple_dut/nv_ram_rws_512x32.v $TARGET_DIR 55 | file copy -force $CL_DIR/../common/design/transactors/cfg/cl_cfgreg.sv $TARGET_DIR 56 | file copy -force $CL_DIR/../common/design/transactors/irq/cl_irq_up.v $TARGET_DIR 57 | file copy -force $CL_DIR/../common/design/transactors/irq/cl_irq_up_bit.v $TARGET_DIR 58 | file copy -force $CL_DIR/../common/design/transactors/irq/simulate_x_tick.vh $TARGET_DIR 59 | file copy -force $CL_DIR/../common/design/vlibs/NV_CLK_gate_power.v $TARGET_DIR 60 | file copy -force $CL_DIR/../common/design/vlibs/p_SSYNC2DO_C_PP.v $TARGET_DIR 61 | file copy -force $CL_DIR/../common/design/vlibs/p_SSYNC3DO_C_PPP.v $TARGET_DIR 62 | file copy -force $CL_DIR/../common/design/vlibs/sync2d_c_pp.v $TARGET_DIR 63 | file copy -force $CL_DIR/../common/design/vlibs/sync3d_c_ppp.v $TARGET_DIR 64 | file copy -force $UNUSED_TEMPLATES_DIR/unused_cl_sda_template.inc $TARGET_DIR 65 | file copy -force $UNUSED_TEMPLATES_DIR/unused_pcim_template.inc $TARGET_DIR 66 | file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_a_b_d_template.inc $TARGET_DIR 67 | 68 | #---- End of section replaced by Developr --- 69 | 70 | 71 | 72 | # Make sure files have write permissions for the encryption 73 | 74 | exec chmod +w {*}[glob $TARGET_DIR/*] 75 | 76 | # encrypt .v/.sv/.vh/inc as verilog files 77 | encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc] 78 | 79 | # encrypt *vhdl files 80 | encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ] 81 | 82 | -------------------------------------------------------------------------------- /cl_memdut/design/axil_slave.sv: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | module axil_slave ( 17 | input clk, 18 | input rst_n, 19 | 20 | input awvalid, 21 | input[63:0] awaddr, 22 | output logic awready, 23 | 24 | //Write data 25 | input wvalid, 26 | input[31:0] wdata, 27 | input[3:0] wstrb, 28 | output logic wready, 29 | 30 | //Write response 31 | output logic bvalid, 32 | output logic[1:0] bresp, 33 | input bready, 34 | 35 | //Read address 36 | input arvalid, 37 | input[63:0] araddr, 38 | output logic arready, 39 | 40 | //Read data/response 41 | output logic rvalid, 42 | output logic[31:0] rdata, 43 | output logic[1:0] rresp, 44 | 45 | input rready 46 | ); 47 | 48 | logic[63:0] awaddr_q; 49 | logic arvalid_q; 50 | 51 | // Does not work when awvalid and wvalid are asserted at the same time 52 | //assign awready = !wvalid; 53 | //assign wready = !arvalid; 54 | // 55 | //always_ff @(negedge rst_n or posedge clk) 56 | // if (!rst_n) 57 | // awaddr_q <= 0; 58 | // else if (awvalid && awready) 59 | // awaddr_q <= awaddr; 60 | // 61 | //always_ff @(negedge rst_n or posedge clk) 62 | // if (!rst_n) 63 | // begin 64 | // bvalid <= 0; 65 | // bresp <= 0; 66 | // end 67 | // else 68 | // begin 69 | // bvalid <= wvalid && wready; 70 | // bresp <= 0; 71 | // end 72 | 73 | 74 | logic wr_active; 75 | logic [63:0] wr_addr; 76 | 77 | always_ff @(negedge rst_n or posedge clk) 78 | if (!rst_n) begin 79 | wr_active <= 0; 80 | wr_addr <= 0; 81 | end 82 | else begin 83 | wr_active <= wr_active && bvalid && bready ? 1'b0 : 84 | awvalid && ~wr_active ? 1'b1 : 85 | wr_active; 86 | wr_addr <= awvalid && ~wr_active ? awaddr : wr_addr; 87 | end 88 | 89 | assign awready = ~wr_active; 90 | assign wready = wr_active && wvalid; 91 | 92 | always_ff @(negedge rst_n or posedge clk) 93 | if (!rst_n) 94 | bvalid <= 0; 95 | else 96 | bvalid <= bvalid && bready ? 1'b0 : 97 | ~bvalid && wready ? 1'b1 : 98 | bvalid; 99 | assign bresp = 0; 100 | 101 | assign arready = !arvalid_q && !rvalid; 102 | 103 | always_ff @(negedge rst_n or posedge clk) 104 | if (!rst_n) 105 | arvalid_q <= 0; 106 | else 107 | arvalid_q <= arvalid; 108 | 109 | logic[31:0] ram_rdata; 110 | 111 | always_ff @(negedge rst_n or posedge clk) 112 | if (!rst_n) 113 | begin 114 | rvalid <= 0; 115 | rdata <= 0; 116 | rresp <= 0; 117 | end 118 | else if (rvalid && rready) 119 | begin 120 | rvalid <= 0; 121 | rdata <= 0; 122 | rresp <= 0; 123 | end 124 | else if (arvalid_q) 125 | begin 126 | rvalid <= 1; 127 | rdata <= ram_rdata; 128 | rresp <= 0; 129 | end 130 | 131 | bram_2rw #(.WIDTH(32), .ADDR_WIDTH(8), .DEPTH(256) ) AXIL_RAM ( 132 | .clk(clk), 133 | // .wea(wvalid), 134 | // .ena(wvalid), 135 | // .addra(awaddr_q[10:2]), 136 | // .da(wdata), 137 | .wea(wready), 138 | .ena(wready), 139 | .addra(wr_addr[9:2]), 140 | .da(wdata), 141 | 142 | .qa(), 143 | 144 | .web(1'b0), 145 | .enb(arvalid), 146 | .addrb(araddr[9:2]), 147 | .db(32'h0), 148 | .qb(ram_rdata) 149 | ); 150 | 151 | endmodule 152 | 153 | 154 | -------------------------------------------------------------------------------- /cl_memdut/design/cl_id_defines.vh: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | // CL_SH_ID0 17 | // - PCIe Vendor/Device ID Values 18 | // 31:16: PCIe Device ID 19 | // 15: 0: PCIe Vendor ID 20 | // - A Vendor ID value of 0x8086 is not valid. 21 | // - If using a Vendor ID value of 0x1D0F (Amazon) then valid 22 | // values for Device ID's are in the range of 0xF000 - 0xF0FF. 23 | // - A Vendor/Device ID of 0 (zero) is not valid. 24 | `define CL_SH_ID0 32'hF001_1D0F 25 | 26 | // CL_SH_ID1 27 | // - PCIe Subsystem/Subsystem Vendor ID Values 28 | // 31:16: PCIe Subsystem ID 29 | // 15: 0: PCIe Subsystem Vendor ID 30 | // - A PCIe Subsystem/Subsystem Vendor ID of 0 (zero) is not valid 31 | `define CL_SH_ID1 32'h1D51_FEDC 32 | 33 | 34 | -------------------------------------------------------------------------------- /cl_memdut/design/cl_memdut_defines.vh: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | // Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | // NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | `ifndef CL_MEMDUT_DEFINES 20 | `define CL_MEMDUT_DEFINES 21 | 22 | //Put module name of the CL design here. This is used to instantiate in top.sv 23 | `define CL_NAME cl_memdut 24 | 25 | //Highly recommeneded. For lib FIFO block, uses less async reset (take advantage of 26 | // FPGA flop init capability). This will help with routing resources. 27 | `define FPGA_LESS_RST 28 | 29 | `define SH_SDA 30 | //uncomment below to make SH and CL async 31 | `define SH_CL_ASYNC 32 | 33 | // Uncomment to disable Virtual JTAG 34 | //`define DISABLE_VJTAG_DEBUG 35 | 36 | `endif 37 | 38 | -------------------------------------------------------------------------------- /cl_memdut/design/cl_memdut_pkg.sv: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | // Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | // NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | `ifndef CL_MEMDUT_PKG 20 | `define CL_MEMDUT_PKG 21 | 22 | interface axi_bus_t; 23 | parameter AWS_FPGA_AXI_BUS_DATA_WIDTH = 512; 24 | parameter AWS_FPGA_AXI_BUS_ID_WIDTH = 16; 25 | parameter AWS_FPGA_AXI_BUS_ADDR_WIDTH = 64; 26 | parameter AWS_FPGA_AXI_BUS_LEN_WIDTH = 8; 27 | logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] awid; 28 | logic[AWS_FPGA_AXI_BUS_ADDR_WIDTH-1:0] awaddr; 29 | logic[AWS_FPGA_AXI_BUS_LEN_WIDTH-1:0] awlen; 30 | logic [2:0] awsize; 31 | logic awvalid; 32 | logic awready; 33 | 34 | logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] wid; 35 | logic[AWS_FPGA_AXI_BUS_DATA_WIDTH-1:0] wdata; 36 | logic[AWS_FPGA_AXI_BUS_DATA_WIDTH/8-1:0] wstrb; 37 | logic wlast; 38 | logic wvalid; 39 | logic wready; 40 | 41 | logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] bid; 42 | logic[1:0] bresp; 43 | logic bvalid; 44 | logic bready; 45 | 46 | logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] arid; 47 | logic[AWS_FPGA_AXI_BUS_ADDR_WIDTH-1:0] araddr; 48 | logic[AWS_FPGA_AXI_BUS_LEN_WIDTH-1:0] arlen; 49 | logic [2:0] arsize; 50 | logic arvalid; 51 | logic arready; 52 | 53 | logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] rid; 54 | logic[AWS_FPGA_AXI_BUS_DATA_WIDTH-1:0] rdata; 55 | logic[1:0] rresp; 56 | logic rlast; 57 | logic rvalid; 58 | logic rready; 59 | 60 | modport master (input awid, awaddr, awlen, awsize, awvalid, output awready, 61 | input wid, wdata, wstrb, wlast, wvalid, output wready, 62 | output bid, bresp, bvalid, input bready, 63 | input arid, araddr, arlen, arsize, arvalid, output arready, 64 | output rid, rdata, rresp, rlast, rvalid, input rready); 65 | 66 | modport slave (output awid, awaddr, awlen, awsize, awvalid, input awready, 67 | output wid, wdata, wstrb, wlast, wvalid, input wready, 68 | input bid, bresp, bvalid, output bready, 69 | output arid, araddr, arlen, arsize, arvalid, input arready, 70 | input rid, rdata, rresp, rlast, rvalid, output rready); 71 | endinterface 72 | 73 | 74 | interface cfg_bus_t; 75 | logic [31:0] addr; 76 | logic [31:0] wdata; 77 | logic wr; 78 | logic rd; 79 | logic ack; 80 | logic[31:0] rdata; 81 | 82 | modport master (input addr, wdata, wr, rd, output ack, rdata); 83 | 84 | modport slave (output addr, wdata, wr, rd, input ack, rdata); 85 | endinterface 86 | 87 | interface scrb_bus_t; 88 | logic [63:0] addr; 89 | logic [2:0] state; 90 | logic enable; 91 | logic done; 92 | 93 | modport master (input enable, output addr, state, done); 94 | 95 | modport slave (output enable, input addr, state, done); 96 | endinterface 97 | 98 | `endif //CL_MEMDUT_PKG 99 | -------------------------------------------------------------------------------- /cl_memdut/design/cl_vio.sv: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | module cl_vio ( 17 | input clk_extra_a1 18 | 19 | ); 20 | 21 | // Counter running at 125MHz 22 | 23 | logic vo_cnt_enable; 24 | logic vo_cnt_load; 25 | logic vo_cnt_clear; 26 | logic vo_cnt_oneshot; 27 | logic [7:0] vo_tick_value; 28 | logic [15:0] vo_cnt_load_value; 29 | logic [15:0] vo_cnt_watermark; 30 | 31 | logic vo_cnt_enable_q = 0; 32 | logic vo_cnt_load_q = 0; 33 | logic vo_cnt_clear_q = 0; 34 | logic vo_cnt_oneshot_q = 0; 35 | logic [7:0] vo_tick_value_q = 0; 36 | logic [15:0] vo_cnt_load_value_q = 0; 37 | logic [15:0] vo_cnt_watermark_q = 0; 38 | 39 | logic vi_tick; 40 | logic vi_cnt_ge_watermark; 41 | logic [7:0] vi_tick_cnt = 0; 42 | logic [15:0] vi_cnt = 0; 43 | 44 | // Tick counter and main counter 45 | always @(posedge clk_extra_a1) begin 46 | 47 | vo_cnt_enable_q <= vo_cnt_enable ; 48 | vo_cnt_load_q <= vo_cnt_load ; 49 | vo_cnt_clear_q <= vo_cnt_clear ; 50 | vo_cnt_oneshot_q <= vo_cnt_oneshot ; 51 | vo_tick_value_q <= vo_tick_value ; 52 | vo_cnt_load_value_q <= vo_cnt_load_value; 53 | vo_cnt_watermark_q <= vo_cnt_watermark ; 54 | 55 | vi_tick_cnt = vo_cnt_clear_q ? 0 : 56 | ~vo_cnt_enable_q ? vi_tick_cnt : 57 | (vi_tick_cnt >= vo_tick_value_q) ? 0 : 58 | vi_tick_cnt + 1; 59 | 60 | vi_cnt = vo_cnt_clear_q ? 0 : 61 | vo_cnt_load_q ? vo_cnt_load_value_q : 62 | ~vo_cnt_enable_q ? vi_cnt : 63 | (vi_tick_cnt >= vo_tick_value_q) && (~vo_cnt_oneshot_q || (vi_cnt <= 16'hFFFF)) ? vi_cnt + 1 : 64 | vi_cnt; 65 | 66 | vi_tick = (vi_tick_cnt >= vo_tick_value_q); 67 | 68 | vi_cnt_ge_watermark = (vi_cnt >= vo_cnt_watermark_q); 69 | 70 | end // always @ (posedge clk_extra_a1) 71 | 72 | 73 | vio_0 CL_VIO_0 ( 74 | .clk (clk_extra_a1), 75 | .probe_in0 (vi_tick), 76 | .probe_in1 (vi_cnt_ge_watermark), 77 | .probe_in2 (vi_tick_cnt), 78 | .probe_in3 (vi_cnt), 79 | .probe_out0 (vo_cnt_enable), 80 | .probe_out1 (vo_cnt_load), 81 | .probe_out2 (vo_cnt_clear), 82 | .probe_out3 (vo_cnt_oneshot), 83 | .probe_out4 (vo_tick_value), 84 | .probe_out5 (vo_cnt_load_value), 85 | .probe_out6 (vo_cnt_watermark) 86 | ); 87 | 88 | ila_vio_counter CL_VIO_ILA ( 89 | .clk (clk_extra_a1), 90 | .probe0 (vi_tick), 91 | .probe1 (vi_cnt_ge_watermark), 92 | .probe2 (vi_tick_cnt), 93 | .probe3 (vi_cnt), 94 | .probe4 (vo_cnt_enable_q), 95 | .probe5 (vo_cnt_load_q), 96 | .probe6 (vo_cnt_clear_q), 97 | .probe7 (vo_cnt_oneshot_q), 98 | .probe8 (vo_tick_value_q), 99 | .probe9 (vo_cnt_load_value_q), 100 | .probe10 (vo_cnt_watermark_q) 101 | ); 102 | 103 | 104 | endmodule 105 | 106 | -------------------------------------------------------------------------------- /cl_memdut/design/simple_dut/nv_ram_rws_256x128.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_256x128.v 10 | 11 | module nv_ram_rws_256x128 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | // port list 23 | input clk; 24 | input [7:0] ra; 25 | input re; 26 | output [127:0] dout; 27 | input [7:0] wa; 28 | input we; 29 | input [127:0] di; 30 | input [31:0] pwrbus_ram_pd; 31 | 32 | //reg and wire list 33 | reg [7:0] ra_d; 34 | wire [127:0] dout; 35 | reg [127:0] M [255:0]; 36 | 37 | always @( posedge clk ) begin 38 | if (we) 39 | M[wa] <= di; 40 | end 41 | 42 | always @( posedge clk ) begin 43 | if (re) 44 | ra_d <= ra; 45 | end 46 | assign dout = M[ra_d]; 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /cl_memdut/design/simple_dut/nv_ram_rws_256x27.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_256x27.v 10 | 11 | module nv_ram_rws_256x27 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | // port list 23 | input clk; 24 | input [7:0] ra; 25 | input re; 26 | output [26:0] dout; 27 | input [7:0] wa; 28 | input we; 29 | input [26:0] di; 30 | input [31:0] pwrbus_ram_pd; 31 | 32 | //reg and wire list 33 | reg [7:0] ra_d; 34 | wire [26:0] dout; 35 | reg [26:0] M [255:0]; 36 | 37 | always @( posedge clk ) begin 38 | if (we) 39 | M[wa] <= di; 40 | end 41 | 42 | always @( posedge clk ) begin 43 | if (re) 44 | ra_d <= ra; 45 | end 46 | assign dout = M[ra_d]; 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /cl_memdut/design/simple_dut/nv_ram_rws_512x256.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_512x256.v 10 | 11 | module nv_ram_rws_512x256 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | // port list 23 | input clk; 24 | input [8:0] ra; 25 | input re; 26 | output [255:0] dout; 27 | input [8:0] wa; 28 | input we; 29 | input [255:0] di; 30 | input [31:0] pwrbus_ram_pd; 31 | 32 | //reg and wire list 33 | reg [8:0] ra_d; 34 | wire [255:0] dout; 35 | reg [255:0] M [511:0]; 36 | 37 | always @( posedge clk ) begin 38 | if (we) 39 | M[wa] <= di; 40 | end 41 | 42 | always @( posedge clk ) begin 43 | if (re) 44 | ra_d <= ra; 45 | end 46 | assign dout = M[ra_d]; 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /cl_memdut/design/simple_dut/nv_ram_rws_512x32.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_512x32.v 10 | 11 | module nv_ram_rws_512x32 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | // port list 23 | input clk; 24 | input [8:0] ra; 25 | input re; 26 | output [31:0] dout; 27 | input [8:0] wa; 28 | input we; 29 | input [31:0] di; 30 | input [31:0] pwrbus_ram_pd; 31 | 32 | //reg and wire list 33 | reg [8:0] ra_d; 34 | wire [31:0] dout; 35 | reg [31:0] M [511:0]; 36 | 37 | always @( posedge clk ) begin 38 | if (we) 39 | M[wa] <= di; 40 | end 41 | 42 | always @( posedge clk ) begin 43 | if (re) 44 | ra_d <= ra; 45 | end 46 | assign dout = M[ra_d]; 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /cl_memdut/software/include/memdut_regs.h: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: memdut_regs.h 10 | 11 | #ifndef _MEMDUT_REGS_H_ 12 | #define _MEMDUT_REGS_H_ 13 | 14 | #define MEMDUT_APB_TRAN_BASE_ADDR (0x00000000) 15 | #define MEMDUT_AXI_PORT_SPACE (0x00100000) 16 | #define MEMDUT_AXI_PORT_SPACE_NUM (1) 17 | 18 | #define MEMDUT_APB_DELAY (MEMDUT_APB_TRAN_BASE_ADDR + 0x0080) 19 | #define MEMDUT_APB_TEST_REG(n) (MEMDUT_APB_TRAN_BASE_ADDR + 0x0100+n*4) 20 | #define MEMDUT_INTR_TEST_SET (MEMDUT_APB_TRAN_BASE_ADDR + 0x2000) 21 | #define MEMDUT_INTR_TEST_CLEAR (MEMDUT_APB_TRAN_BASE_ADDR + 0x2004) 22 | #define MEMDUT_INTR_TEST_MODE1 (MEMDUT_APB_TRAN_BASE_ADDR + 0x2008) 23 | #define MEMDUT_INTR_TEST_MODE2 (MEMDUT_APB_TRAN_BASE_ADDR + 0x200C) 24 | #define MEMDUT_INTR_TEST_EN (MEMDUT_APB_TRAN_BASE_ADDR + 0x2010) 25 | 26 | #define MEMDUT_N_TEST_CTRL(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0000) 27 | #define MEMDUT_N_CMD_NUM_TOTAL(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0004) 28 | #define MEMDUT_N_CMD_LINE_CTRL(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0008) 29 | #define MEMDUT_N_WDATA_LINE_CTRL(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x000C) 30 | #define MEMDUT_N_WCMD_LINE_CTRL(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0010) 31 | #define MEMDUT_N_RDATA_LINE_CTRL(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0014) 32 | #define MEMDUT_N_RESP_DELAY_CTRL(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0018) 33 | #define MEMDUT_N_ATG_CMD_CTRL(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0020) 34 | #define MEMDUT_N_ATG_AXI_ID(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0024) 35 | #define MEMDUT_N_ATG_ADDR_BASE(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0028) 36 | #define MEMDUT_N_ATG_ADDR_LOW(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x002C) 37 | #define MEMDUT_N_ATG_DATA_CTRL(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0030) 38 | #define MEMDUT_N_ATG_WSTRB(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0034) 39 | #define MEMDUT_N_OUTSTAND_STATUS(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0040) 40 | #define MEMDUT_N_TEST_STATUS(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0044) 41 | #define MEMDUT_N_TEST_ERR_LOC(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0048) 42 | #define MEMDUT_N_RESP_CNT(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x004C) 43 | #define MEMDUT_N_RRESP_CNT(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0050) 44 | #define MEMDUT_N_RDATA_CNT(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0054) 45 | #define MEMDUT_N_REQ_CNT(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0058) 46 | #define MEMDUT_N_REQ_WR_CNT(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x005C) 47 | #define MEMDUT_N_REQ_WD_CNT(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0060) 48 | #define MEMDUT_N_TEST_TIMER(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x0064) 49 | #define MEMDUT_N_CMD_RAM_BASE(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x10000) 50 | #define MEMDUT_N_WE_RAM_BASE(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x30000) 51 | #define MEMDUT_N_WDATA_RAM_BASE(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0x40000) 52 | #define MEMDUT_N_RDATA_RAM_BASE(n) (MEMDUT_APB_TRAN_BASE_ADDR + n*MEMDUT_AXI_PORT_SPACE + 0xA0000) 53 | 54 | #endif /* _MEMDUT_REGS_H_ */ 55 | -------------------------------------------------------------------------------- /cl_memdut/software/src/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | #VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 17 | VPATH = src:../../../common/software/src 18 | 19 | INCLUDES = -I../../../common/software/include -I../include 20 | ifndef VP_TEST 21 | INCLUDES += -I$(SDK_DIR)/userspace/include 22 | endif 23 | 24 | ifdef VP_TEST 25 | CC = aarch64-linux-gnu-gcc 26 | else 27 | CC = gcc 28 | endif 29 | 30 | CFLAGS = -DCONFIG_LOGLEVEL=4 -g -Wall $(INCLUDES) 31 | ifdef VP_TEST 32 | CFLAGS += -DVP_TEST 33 | else 34 | CFLAGS += -L$(SDK_DIR)/userspace/lib/so 35 | endif 36 | 37 | ifndef VP_TEST 38 | LDLIBS = -lfpga_mgmt -lrt -lpthread 39 | endif 40 | 41 | SRC = test_memdut.c cl_common_utils.c test_utils.c 42 | OBJ = $(SRC:.c=.o) 43 | ifdef VP_TEST 44 | BIN = aarch64_test_memdut 45 | else 46 | BIN = test_memdut 47 | endif 48 | 49 | ifdef VP_TEST 50 | all: $(BIN) 51 | else 52 | all: $(BIN) check_env 53 | endif 54 | 55 | $(BIN): $(OBJ) 56 | $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LDLIBS) 57 | 58 | clean: 59 | rm -f *.o $(BIN) 60 | 61 | ifndef VP_TEST 62 | check_env: 63 | ifndef SDK_DIR 64 | $(error SDK_DIR is undefined. Try "source sdk_setup.sh" to set the software environment) 65 | endif 66 | endif 67 | -------------------------------------------------------------------------------- /cl_memdut/software/src/test_null.c: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | #include 17 | #include 18 | #include 19 | 20 | // Vivado does not support svGetScopeFromName 21 | #ifdef INCLUDE_DPI_CALLS 22 | #ifndef VIVADO_SIM 23 | #include "svdpi.h" 24 | #endif 25 | #endif 26 | 27 | #include "sh_dpi_tasks.h" 28 | 29 | void test_main(uint32_t *exit_code) { 30 | 31 | // NULL Test 32 | 33 | *exit_code = 0; 34 | } 35 | -------------------------------------------------------------------------------- /cl_memdut/software/src/test_utils.c: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: test_utils.c 10 | 11 | #include "test_utils.h" 12 | #include "cl_common_utils.h" 13 | #include "memdut_regs.h" 14 | 15 | // Util functions 16 | void apb_write_test_reg(uint32_t reg_n, uint32_t data) 17 | { 18 | apb_write(MEMDUT_APB_TEST_REG(reg_n), data); 19 | } 20 | 21 | void apb_read_test_reg(uint32_t reg_n, uint32_t *data) 22 | { 23 | apb_read(MEMDUT_APB_TEST_REG(reg_n), data); 24 | } 25 | 26 | void apb_write_cmd_ram(uint32_t inst, uint32_t offset, const uint32_t* wdata) 27 | { 28 | int i; 29 | for (i=0; i<4; i++) { 30 | apb_write(MEMDUT_N_CMD_RAM_BASE(inst)+(offset<<4)+(i<<2), wdata[i]); 31 | } 32 | } 33 | 34 | void apb_read_cmd_ram(uint32_t inst, uint32_t offset, uint32_t* rdata) 35 | { 36 | int i; 37 | for (i=0; i<4; i++) { 38 | apb_read(MEMDUT_N_CMD_RAM_BASE(inst)+(offset<<4)+(i<<2), &rdata[i]); 39 | } 40 | } 41 | 42 | void apb_write_we_ram(uint32_t inst, uint32_t offset, uint32_t wdata) 43 | { 44 | apb_write(MEMDUT_N_WE_RAM_BASE(inst)+(offset<<2), wdata); 45 | } 46 | 47 | void apb_read_we_ram(uint32_t inst, uint32_t offset, uint32_t* rdata) 48 | { 49 | apb_read(MEMDUT_N_WE_RAM_BASE(inst)+(offset<<2), rdata); 50 | } 51 | 52 | void apb_write_wdata_ram(uint32_t inst, uint32_t offset, const uint32_t* wdata) 53 | { 54 | int i; 55 | for (i=0; i<8; i++) { 56 | apb_write(MEMDUT_N_WDATA_RAM_BASE(inst)+(offset<<5)+(i<<2), wdata[i]); 57 | } 58 | } 59 | 60 | void apb_read_wdata_ram(uint32_t inst, uint32_t offset, uint32_t* rdata) 61 | { 62 | int i; 63 | for (i=0; i<8; i++) { 64 | apb_read(MEMDUT_N_WDATA_RAM_BASE(inst)+(offset<<5)+(i<<2), &rdata[i]); 65 | } 66 | } 67 | 68 | void apb_write_rdata_ram(uint32_t inst, uint32_t offset, const uint32_t* wdata) 69 | { 70 | int i; 71 | for (i=0; i<8; i++) { 72 | apb_write(MEMDUT_N_RDATA_RAM_BASE(inst)+(offset<<5)+(i<<2), wdata[i]); 73 | } 74 | } 75 | 76 | void apb_read_rdata_ram(uint32_t inst, uint32_t offset, uint32_t* rdata) 77 | { 78 | int i; 79 | for (i=0; i<8; i++) { 80 | apb_read(MEMDUT_N_RDATA_RAM_BASE(inst)+(offset<<5)+(i<<2), &rdata[i]); 81 | } 82 | } 83 | 84 | void memdut_set_atg_ctrl(const memdut_atg_ctrl *atg_ctrl, uint32_t inst) 85 | { 86 | apb_write(MEMDUT_N_ATG_CMD_CTRL(inst), atg_ctrl->atg_cmd_ctrl.value); 87 | apb_write(MEMDUT_N_ATG_AXI_ID(inst), atg_ctrl->atg_axi_id.value); 88 | apb_write(MEMDUT_N_ATG_ADDR_BASE(inst), atg_ctrl->atg_addr_base.value); 89 | apb_write(MEMDUT_N_ATG_ADDR_LOW(inst), atg_ctrl->atg_addr_low.value); 90 | apb_write(MEMDUT_N_ATG_DATA_CTRL(inst), atg_ctrl->atg_data_ctrl.value); 91 | apb_write(MEMDUT_N_ATG_WSTRB(inst), atg_ctrl->atg_wstrb.value); 92 | } 93 | 94 | void memdut_set_num_req(const num_req_reg num_req, uint32_t inst) 95 | { 96 | apb_write(MEMDUT_N_CMD_NUM_TOTAL(inst), num_req.value); 97 | } 98 | 99 | void memdut_set_test_ctrl(const test_ctrl_reg ctrl, uint32_t inst) 100 | { 101 | apb_write(MEMDUT_N_TEST_CTRL(inst), ctrl.value); 102 | } 103 | 104 | void memdut_get_test_ctrl(test_ctrl_reg *ctrl, uint32_t inst) 105 | { 106 | apb_read(MEMDUT_N_TEST_CTRL(inst), &(ctrl->value)); 107 | } 108 | 109 | void memdut_get_test_cnt(memdut_test_cnt *cnt, uint32_t inst) 110 | { 111 | apb_read(MEMDUT_N_RESP_CNT(inst), &(cnt->resp_cnt.value)); 112 | apb_read(MEMDUT_N_RRESP_CNT(inst), &(cnt->rresp_cnt.value)); 113 | apb_read(MEMDUT_N_RDATA_CNT(inst), &(cnt->rdata_cnt.value)); 114 | apb_read(MEMDUT_N_REQ_CNT(inst), &(cnt->req_cnt.value)); 115 | apb_read(MEMDUT_N_REQ_WR_CNT(inst), &(cnt->req_wr_cnt.value)); 116 | apb_read(MEMDUT_N_REQ_WD_CNT(inst), &(cnt->req_wd_cnt.value)); 117 | } 118 | 119 | void memdut_get_test_status(test_status_reg *status, uint32_t inst) 120 | { 121 | apb_read(MEMDUT_N_TEST_STATUS(inst), &(status->value)); 122 | } 123 | -------------------------------------------------------------------------------- /cl_memdut/verif/README.md: -------------------------------------------------------------------------------- 1 | # CL_MEMDUT Simulation 2 | 3 | The cl_memdut includes a basic test that exercises the BAR1, DDR_C, and interrupt. 4 | 5 | The test can be run from the [verif/scripts] (scripts) directory with one of three different simulators: 6 | 7 | ``` 8 | $ make C_TEST=test_memdut 9 | $ make C_TEST=test_memdut VCS=1 10 | $ make C_TEST=test_memdut QUESTA=1 11 | ``` 12 | 13 | Note that the appropriate simulators must be installed. 14 | 15 | -------------------------------------------------------------------------------- /cl_memdut/verif/scripts/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | # NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | 20 | export TEST ?= test_null 21 | export C_TEST ?= test_null 22 | 23 | export CL_ROOT = $(PWD)/../.. 24 | 25 | export CL_COMMON_ROOT = $(PWD)/../../../common 26 | 27 | export C_INC_DIR = $(CL_ROOT)/software/include 28 | export C_SRC_DIR = $(CL_ROOT)/software/src 29 | 30 | export TEST_NAME = $(CL_ROOT)/verif/tests/$(TEST).sv 31 | export C_TEST_NAME = $(C_SRC_DIR)/$(C_TEST).c $(C_SRC_DIR)/test_utils.c $(CL_COMMON_ROOT)/software/src/cl_common_utils.c $(CL_COMMON_ROOT)/software/src/sh_dpi_tasks.c 32 | 33 | export SIM_ROOT = $(CL_ROOT)/verif/sim 34 | 35 | ifeq ($(C_TEST),test_null) 36 | export SIM_DIR = $(SIM_ROOT)/$(TEST) 37 | else 38 | export SIM_DIR = $(SIM_ROOT)/$(C_TEST) 39 | endif 40 | 41 | export SCRIPTS_DIR = $(PWD) 42 | export XILINX_IP = $(HDK_SHELL_DESIGN_DIR)/ip 43 | export SH_LIB_DIR = $(HDK_SHELL_DESIGN_DIR)/lib 44 | export SH_INF_DIR = $(HDK_SHELL_DESIGN_DIR)/interfaces 45 | 46 | SV_TEST_LIST = 47 | C_TEST_LIST = test_memdut.c 48 | 49 | all: make_sim_dir compile run 50 | 51 | include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.common.inc 52 | 53 | -------------------------------------------------------------------------------- /cl_memdut/verif/scripts/Makefile.vcs: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | # NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | 20 | ################################################################## 21 | ## Makefile For VCS compiles and simulations 22 | ## Step to run : 23 | ## 1. make create_libs VCS=1 -> To generate xilinx compile 24 | ## libraries. This is a one time step 25 | ## 2. make all VCS=1 -> Runs the test 26 | ################################################################## 27 | 28 | compile: $(COMPLIB_DIR) 29 | mkdir -p $(SIM_DIR) 30 | cd ${SIM_DIR} && ln -s -f ../vcs_complib/synopsys_sim.setup 31 | cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFINES) +lint=TFIPC-L 32 | cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR) -I$(CL_COMMON_ROOT)/software/include -DSV_TEST" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log 33 | 34 | run: 35 | cd $(SIM_DIR) && ./simv -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd 36 | 37 | $(COMPLIB_DIR): 38 | cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl 39 | cd $(SIM_ROOT)/.. && vivado -mode batch -source create_libs.tcl 40 | cd $(SIM_ROOT)/.. && rm -rf create_libs.tcl 41 | -------------------------------------------------------------------------------- /cl_memdut/verif/scripts/top.vcs.f: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | # NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | +define+VCS_SIM 20 | 21 | +libext+.v 22 | +libext+.sv 23 | +libext+.svh 24 | 25 | -y ${CL_ROOT}/design 26 | -y ${SH_LIB_DIR} 27 | -y ${SH_INF_DIR} 28 | -y ${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim 29 | 30 | +incdir+${CL_ROOT}/design 31 | +incdir+${CL_ROOT}/verif/sv 32 | +incdir+${CL_COMMON_ROOT}/verif/include 33 | +incdir+${SH_LIB_DIR} 34 | +incdir+${SH_INF_DIR} 35 | +incdir+${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim 36 | 37 | ${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_xbar_0/sim/cl_axi_interconnect_xbar_0.v 38 | ${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_s00_regslice_0/sim/cl_axi_interconnect_s00_regslice_0.v 39 | ${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_s01_regslice_0/sim/cl_axi_interconnect_s01_regslice_0.v 40 | ${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/sim/cl_axi_interconnect_m00_regslice_0.v 41 | ${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/sim/cl_axi_interconnect_m01_regslice_0.v 42 | ${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_m02_regslice_0/sim/cl_axi_interconnect_m02_regslice_0.v 43 | ${SH_LIB_DIR}/../ip/cl_axi_interconnect/ip/cl_axi_interconnect_m03_regslice_0/sim/cl_axi_interconnect_m03_regslice_0.v 44 | ${SH_LIB_DIR}/../ip/cl_axi_interconnect/hdl/cl_axi_interconnect.v 45 | ${SH_LIB_DIR}/../ip/axi_clock_converter_0/sim/axi_clock_converter_0.v 46 | ${SH_LIB_DIR}/../ip/dest_register_slice/sim/dest_register_slice.v 47 | ${SH_LIB_DIR}/../ip/src_register_slice/sim/src_register_slice.v 48 | ${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v 49 | ${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v 50 | 51 | +define+DISABLE_VJTAG_DEBUG 52 | ${CL_ROOT}/design/axil_slave.sv 53 | ${CL_ROOT}/design/cl_memdut_defines.vh 54 | ${CL_ROOT}/design/cl_memdut_pkg.sv 55 | ${CL_ROOT}/design/cl_dma_pcis_slv.sv 56 | ${CL_ROOT}/design/cl_ila.sv 57 | ${CL_ROOT}/design/cl_vio.sv 58 | ${CL_ROOT}/design/cl_memdut.sv 59 | ${CL_ROOT}/design/cl_memdut_wrap.sv 60 | 61 | ${CL_COMMON_ROOT}/design/xilinx_ip/axi_interconnect_nvdla_256b/axi_interconnect_nvdla_256b_sim_netlist.v 62 | ${CL_COMMON_ROOT}/design/xilinx_ip/axi_apb_bridge_0/axi_apb_bridge_0_sim_netlist.v 63 | ${CL_COMMON_ROOT}/design/transactors/irq/cl_irq_up.v 64 | ${CL_COMMON_ROOT}/design/transactors/irq/cl_irq_up_bit.v 65 | ${CL_COMMON_ROOT}/design/transactors/cfg/cl_cfgreg.sv 66 | 67 | -y ${CL_COMMON_ROOT}/design/vlibs 68 | +incdir+${CL_COMMON_ROOT}/design/transactors/irq 69 | 70 | +define+NO_PLI_OR_EMU 71 | +define+VLIB_BYPASS_POWER_CG 72 | +define+VERILINT 73 | +define+PRAND_OFF 74 | +define+SYNC_PL_NO_RANDOMIZATION 75 | +define+NO_PERFMON_HISTOGRAM 76 | 77 | ${CL_ROOT}/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut.v 78 | ${CL_ROOT}/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_apb_slave.v 79 | ${CL_ROOT}/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_256_256.v 80 | ${CL_ROOT}/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_256.v 81 | ${CL_ROOT}/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_req_gen_256.v 82 | ${CL_ROOT}/design/simple_dut/NV_FPGA_unit_checkbox_mem_dut_axi_resp_256.v 83 | ${CL_ROOT}/design/simple_dut/nv_ram_rws_256x128.v 84 | ${CL_ROOT}/design/simple_dut/nv_ram_rws_256x27.v 85 | ${CL_ROOT}/design/simple_dut/nv_ram_rws_512x256.v 86 | ${CL_ROOT}/design/simple_dut/nv_ram_rws_512x32.v 87 | +define+NO_INIT_MEM_RANDOM_TASK 88 | +define+NO_INIT_MEM_VAL_TASKS 89 | 90 | -f ${HDK_COMMON_DIR}/verif/tb/filelists/tb.${SIMULATOR}.f 91 | 92 | ${TEST_NAME} 93 | -------------------------------------------------------------------------------- /cl_memdut/verif/scripts/waves.tcl: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | set curr_wave [current_wave_config] 17 | if { [string length $curr_wave] == 0 } { 18 | if { [llength [get_objects]] > 0} { 19 | add_wave / 20 | set_property needs_save false [current_wave_config] 21 | } else { 22 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 23 | } 24 | } 25 | 26 | run 200 us 27 | quit 28 | -------------------------------------------------------------------------------- /cl_memdut/verif/tests/test_null.sv: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | module test_null(); 17 | 18 | initial begin 19 | int exit_code; 20 | 21 | tb.power_up(); 22 | 23 | // tb.nsec_delay(500); 24 | // tb.poke_stat(.addr(8'h0c), .ddr_idx(0), .data(32'h0000_0000)); 25 | // tb.poke_stat(.addr(8'h0c), .ddr_idx(1), .data(32'h0000_0000)); 26 | // tb.poke_stat(.addr(8'h0c), .ddr_idx(2), .data(32'h0000_0000)); 27 | // 28 | tb.test_main(exit_code); 29 | 30 | #50ns; 31 | 32 | tb.power_down(); 33 | 34 | $finish; 35 | end 36 | 37 | endmodule // test_null 38 | -------------------------------------------------------------------------------- /cl_nvdla/build/constraints/cl_pnr_user.xdc: -------------------------------------------------------------------------------- 1 | # This contains the CL specific constraints for Top level PNR 2 | 3 | # False path between vled on CL clock and Shell asynchronous clock 4 | set_false_path -from [get_cells WRAPPER_INST/CL/vled_q_reg*] 5 | 6 | # False paths between main clock and tck 7 | set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]] 8 | set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck] 9 | set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] 10 | 11 | -------------------------------------------------------------------------------- /cl_nvdla/build/constraints/cl_synth_user.xdc: -------------------------------------------------------------------------------- 1 | # This contains the CL specific constraints for synthesis at the CL level 2 | 3 | 4 | -------------------------------------------------------------------------------- /cl_nvdla/build/scripts/README.md: -------------------------------------------------------------------------------- 1 | # Step by step to build nvdla(small configuration) in AWS F1: 2 | 1. Setup environment variables: 3 | > export CL_DIR=/vp/fpga/aws-fpga/cl_nvdla 4 | > export NV_HW_ROOT= 5 | 2. Git clone aws-fpga from github: 6 | > git clone https://github.com/aws/aws-fpga.git 7 | 3. Souce aws-fpga hdk environment: 8 | > source aws-fpga/hdk_setup.sh 9 | 4. Generate nvdla file list: 10 | > ./filelist.sh [nv_large | nv_medium_1024_full | nv_medium_512 | nv_small_256_full | nv_small_256 | nv_small] 11 | 5. Change the verilog define in file synth_cl_nvdla.tcl for different configure 12 | > -verilog_define NV_LARGE | NV_MEDIUM_1024_FULL | NV_MEDIUM_512 | NV_SMALL_256_FULL | NV_SMALL_256 | NV_SMALL 13 | 6. Command line to build nvdla in aws fpga: 14 | > $HDK_DIR/common/shell_stable/build/scripts/aws_build_dcp_from_cl.sh -foreground -clock_recipe_a A2 15 | 16 | -------------------------------------------------------------------------------- /cl_nvdla/build/scripts/download_f1: -------------------------------------------------------------------------------- 1 | # ================================================================ 2 | # NVDLA Open Source Project 3 | # 4 | # Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | # NVDLA Open Hardware License; Check \"LICENSE\" which comes with 6 | # this distribution for more information. 7 | # ================================================================ 8 | 9 | sudo fpga-clear-local-image -S 0 10 | sudo fpga-describe-local-image -S 0 -H 11 | sudo fpga-load-local-image -S 0 -I "agfi-0f43c1ea1b624384e" 12 | sudo fpga-describe-local-image -S 0 -R -H 13 | sudo rmmod edma-drv && sudo insmod $SDK_DIR/linux_kernel_drivers/edma/edma-drv.ko 14 | -------------------------------------------------------------------------------- /cl_nvdla/build/scripts/encrypt.tcl: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | # NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | # TODO: 20 | # Add check if CL_DIR and HDK_SHELL_DIR directories exist 21 | # Add check if /build and /build/src_port_encryption directories exist 22 | # Add check if the vivado_keyfile exist 23 | 24 | set HDK_SHELL_DIR $::env(HDK_SHELL_DIR) 25 | set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR) 26 | set CL_DIR $::env(CL_DIR) 27 | set NV_HW_ROOT $::env(NV_HW_ROOT) 28 | 29 | set TARGET_DIR $CL_DIR/build/src_post_encryption 30 | set UNUSED_TEMPLATES_DIR $HDK_SHELL_DESIGN_DIR/interfaces 31 | 32 | 33 | # Remove any previously encrypted files, that may no longer be used 34 | exec rm -f $TARGET_DIR/* 35 | 36 | #---- Developr would replace this section with design files ---- 37 | 38 | ## Change file names and paths below to reflect your CL area. DO NOT include AWS RTL files. 39 | file copy -force $CL_DIR/design/cl_nvdla_defines.vh $TARGET_DIR 40 | file copy -force $CL_DIR/../common/design/transactors/cfg/cl_cfgreg.sv $TARGET_DIR 41 | file copy -force $CL_DIR/../common/design/transactors/irq/cl_irq_up.v $TARGET_DIR 42 | file copy -force $CL_DIR/../common/design/transactors/irq/cl_irq_up_bit.v $TARGET_DIR 43 | file copy -force $CL_DIR/../common/design/transactors/irq/simulate_x_tick.vh $TARGET_DIR 44 | file copy -force $CL_DIR/design/cl_dma_pcis_slv.sv $TARGET_DIR 45 | file copy -force $CL_DIR/design/cl_id_defines.vh $TARGET_DIR 46 | file copy -force $CL_DIR/design/cl_ila.sv $TARGET_DIR 47 | file copy -force $CL_DIR/design/cl_nvdla_pkg.sv $TARGET_DIR 48 | file copy -force $CL_DIR/design/cl_nvdla_wrap.sv $TARGET_DIR 49 | file copy -force $CL_DIR/design/cl_vio.sv $TARGET_DIR 50 | file copy -force $CL_DIR/design/cl_nvdla.sv $TARGET_DIR 51 | file copy -force $UNUSED_TEMPLATES_DIR/unused_apppf_irq_template.inc $TARGET_DIR 52 | file copy -force $UNUSED_TEMPLATES_DIR/unused_cl_sda_template.inc $TARGET_DIR 53 | file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_a_b_d_template.inc $TARGET_DIR 54 | file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_c_template.inc $TARGET_DIR 55 | file copy -force $UNUSED_TEMPLATES_DIR/unused_dma_pcis_template.inc $TARGET_DIR 56 | file copy -force $UNUSED_TEMPLATES_DIR/unused_pcim_template.inc $TARGET_DIR 57 | file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc $TARGET_DIR 58 | file copy -force $UNUSED_TEMPLATES_DIR/unused_flr_template.inc $TARGET_DIR 59 | source ./nvdla_file.tcl 60 | 61 | #---- End of section replaced by Developr --- 62 | exec chmod +w {*}[glob $TARGET_DIR/*] 63 | #encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc] 64 | -------------------------------------------------------------------------------- /cl_nvdla/build/scripts/filelist.sh: -------------------------------------------------------------------------------- 1 | # ================================================================ 2 | # NVDLA Open Source Project 3 | # 4 | # Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | # NVDLA Open Hardware License; Check \"LICENSE\" which comes with 6 | # this distribution for more information. 7 | # ================================================================ 8 | 9 | rm -rf ./nvdla_file.tcl 10 | rm -rf ../src_post_encryption 11 | version=$1 12 | 13 | SelecSource(){ 14 | local_folder=$1 15 | local_file_type=$2 16 | 17 | echo processing the folder: $local_folder 18 | file_list=`ls ${NV_HW_ROOT}/${local_folder}/*.${local_file_type}` 19 | #echo ${file_list} 20 | for file in ${file_list} 21 | do 22 | tmp_file=`basename $file` 23 | echo file copy -force \$NV_HW_ROOT/$local_folder/$tmp_file \$TARGET_DIR >> ./nvdla_file.tcl 24 | done 25 | } 26 | 27 | RemoveFile(){ 28 | local_file=$1 29 | echo "remove file $local_file" 30 | sed '/'$local_file'/d' nvdla_file.tcl > nvdla_file.tcl_temp 31 | mv nvdla_file.tcl_temp nvdla_file.tcl 32 | } 33 | 34 | ip_path=outdir/$version/spec/manual 35 | file_type=v 36 | SelecSource $ip_path $file_type 37 | 38 | ip_path=outdir/$version/vmod/nvdla 39 | file_type=v 40 | folder_list=`ls ${NV_HW_ROOT}/${ip_path}` 41 | echo ${folder_list} 42 | for folder in ${folder_list} 43 | do 44 | SelecSource ${ip_path}/$folder $file_type 45 | done 46 | 47 | ip_path=outdir/$version/vmod/include 48 | file_type=vh 49 | SelecSource ${ip_path} $file_type 50 | 51 | ip_path=outdir/$version/vmod/vlibs 52 | file_type=v 53 | SelecSource ${ip_path} $file_type 54 | 55 | ip_path=outdir/$version/spec/defs 56 | file_type=vh 57 | SelecSource ${ip_path} $file_type 58 | 59 | #export PATH=.:$PATH 60 | #echo "dla_ramgen -m nv_ram_rwsp_8x65" >> ${NV_HW_ROOT}/vmod/rams/fpga/run_small_ram 61 | #echo "dla_ramgen -m nv_ram_rws_256x64" >> ${NV_HW_ROOT}/vmod/rams/fpga/run_small_ram 62 | #cur_path=`pwd` 63 | #cd ${NV_HW_ROOT}/vmod/rams/fpga 64 | #./run_small_ram 65 | #mkdir -p ${NV_HW_ROOT}/outdir/$version/vmod/rams/fpga/small_rams 66 | #mv ${NV_HW_ROOT}/vmod/rams/fpga/*.v ${NV_HW_ROOT}/outdir/$version/vmod/rams/fpga/small_rams 67 | #cd ${cur_path} 68 | 69 | ip_path=outdir/$version/vmod/rams/fpga/model 70 | file_type=v 71 | SelecSource ${ip_path} $file_type 72 | 73 | ip_path=outdir/$version/vmod/fifos 74 | file_type=v 75 | SelecSource ${ip_path} $file_type 76 | 77 | if [ $version == "nv_large" ] 78 | then 79 | file_remove_list="NV_NVDLA_CDP_DP_bufferin_tp1.v NV_NVDLA_CVIF_WRITE_IG_arb.v" 80 | elif [ $version == "nv_medium_1024_full" ] 81 | then 82 | file_remove_list="NV_NVDLA_CDP_DP_bufferin_tp1.v" 83 | elif [ $version == "nv_medium_512" ] 84 | then 85 | file_remove_list="NV_NVDLA_SDP_CORE_Y_lut.v NV_NVDLA_SDP_HLS_Y_cvt_top.v NV_NVDLA_SDP_HLS_Y_idx_top.v NV_NVDLA_SDP_HLS_Y_inp_top.v NV_NVDLA_SDP_HLS_Y_int_core.v" 86 | elif [ $version == "nv_small_256_full" ] 87 | then 88 | #file_remove_list="NV_NVDLA_SDP_CORE_Y_lut.v NV_NVDLA_SDP_HLS_Y_idx_top.v NV_NVDLA_SDP_HLS_Y_inp_top.v" 89 | file_remove_list="" 90 | else 91 | file_remove_list="NV_NVDLA_SDP_CORE_Y_lut.v NV_NVDLA_SDP_HLS_Y_cvt_top.v NV_NVDLA_SDP_HLS_Y_idx_top.v NV_NVDLA_SDP_HLS_Y_inp_top.v NV_NVDLA_SDP_HLS_Y_int_core.v" 92 | fi 93 | 94 | for each_file in $file_remove_list 95 | do 96 | RemoveFile $each_file 97 | done 98 | -------------------------------------------------------------------------------- /cl_nvdla/build/scripts/upload_f1: -------------------------------------------------------------------------------- 1 | # ================================================================ 2 | # NVDLA Open Source Project 3 | # 4 | # Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | # NVDLA Open Hardware License; Check \"LICENSE\" which comes with 6 | # this distribution for more information. 7 | # ================================================================ 8 | 9 | aws s3 mb s3://sqi 10 | aws s3 mb s3://sqi/nv_small_64/ 11 | aws s3 cp $CL_DIR/build/checkpoints/to_aws/18_04_16-221842.Developer_CL.tar s3://sqi/nv_small_64/ 12 | aws s3 mb s3://sqi/nv_small_64_log/ 13 | touch LOGS_FILES_GO_HERE.txt 14 | aws s3 cp LOGS_FILES_GO_HERE.txt s3://sqi/nv_small_64_log/ 15 | aws ec2 create-fpga-image --name nvdla_small_64_18_04_16_221842 --description nvdla_small_18_04_16_221842 --input-storage-location Bucket=sqi,Key=nv_small_64/18_04_16-221842.Developer_CL.tar --logs-storage-location Bucket=sqi,Key=nv_small_64_log 16 | -------------------------------------------------------------------------------- /cl_nvdla/design/cl_id_defines.vh: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | // CL_SH_ID0 17 | // - PCIe Vendor/Device ID Values 18 | // 31:16: PCIe Device ID 19 | // 15: 0: PCIe Vendor ID 20 | // - A Vendor ID value of 0x8086 is not valid. 21 | // - If using a Vendor ID value of 0x1D0F (Amazon) then valid 22 | // values for Device ID's are in the range of 0xF000 - 0xF0FF. 23 | // - A Vendor/Device ID of 0 (zero) is not valid. 24 | `define CL_SH_ID0 32'hF001_1D0F 25 | 26 | // CL_SH_ID1 27 | // - PCIe Subsystem/Subsystem Vendor ID Values 28 | // 31:16: PCIe Subsystem ID 29 | // 15: 0: PCIe Subsystem Vendor ID 30 | // - A PCIe Subsystem/Subsystem Vendor ID of 0 (zero) is not valid 31 | `define CL_SH_ID1 32'h1D51_FEDC 32 | 33 | 34 | -------------------------------------------------------------------------------- /cl_nvdla/design/cl_nvdla_defines.vh: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | // Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | // NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | `ifndef CL_NVDLA_DEFINES 20 | `define CL_NVDLA_DEFINES 21 | 22 | //Put module name of the CL design here. This is used to instantiate in top.sv 23 | `define CL_NAME cl_nvdla 24 | 25 | //Highly recommeneded. For lib FIFO block, uses less async reset (take advantage of 26 | // FPGA flop init capability). This will help with routing resources. 27 | `define FPGA_LESS_RST 28 | 29 | `define SH_SDA 30 | //uncomment below to make SH and CL async 31 | `define SH_CL_ASYNC 32 | 33 | // Uncomment to disable Virtual JTAG 34 | `define DISABLE_VJTAG_DEBUG 35 | `define FPGA 36 | `define SYNTHESIS 37 | `define DESIGNWARE_NOEXIST 38 | `define VLIB_BYPASS_POWER_CG 39 | `define NV_FPGA_UNIT 40 | `define NV_FPGA_FIFOGEN 41 | `ifdef NV_LARGE 42 | `define NVDLA_CVSRAM_PRESENT 43 | `define NVDLA_AXI_WIDTH_256 44 | `endif 45 | `ifdef NV_MEDIUM_1024_FULL 46 | `define NVDLA_CVSRAM_PRESENT 47 | `define NVDLA_AXI_WIDTH_256 48 | `endif 49 | `ifdef NV_MEDIUM_512 50 | `define NVDLA_AXI_WIDTH_128 51 | `endif 52 | `ifdef NV_SMALL_256_FULL 53 | `define NVDLA_CVSRAM_PRESENT 54 | `define NVDLA_AXI_WIDTH_64 55 | `endif 56 | `ifdef NV_SMALL_256 57 | `define NVDLA_AXI_WIDTH_64 58 | `endif 59 | `ifdef NV_SMALL 60 | `define NVDLA_AXI_WIDTH_64 61 | `endif 62 | 63 | `endif 64 | 65 | -------------------------------------------------------------------------------- /cl_nvdla/design/cl_nvdla_pkg.sv: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | // Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | // NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | `ifndef CL_NVDLA_PKG 20 | `define CL_NVDLA_PKG 21 | 22 | interface axi_bus_t; 23 | parameter AWS_FPGA_AXI_BUS_DATA_WIDTH = 512; 24 | parameter AWS_FPGA_AXI_BUS_ID_WIDTH = 16; 25 | parameter AWS_FPGA_AXI_BUS_ADDR_WIDTH = 64; 26 | parameter AWS_FPGA_AXI_BUS_LEN_WIDTH = 8; 27 | logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] awid; 28 | logic[AWS_FPGA_AXI_BUS_ADDR_WIDTH-1:0] awaddr; 29 | logic[AWS_FPGA_AXI_BUS_LEN_WIDTH-1:0] awlen; 30 | logic [2:0] awsize; 31 | logic awvalid; 32 | logic awready; 33 | 34 | logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] wid; 35 | logic[AWS_FPGA_AXI_BUS_DATA_WIDTH-1:0] wdata; 36 | logic[AWS_FPGA_AXI_BUS_DATA_WIDTH/8-1:0] wstrb; 37 | logic wlast; 38 | logic wvalid; 39 | logic wready; 40 | 41 | logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] bid; 42 | logic[1:0] bresp; 43 | logic bvalid; 44 | logic bready; 45 | 46 | logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] arid; 47 | logic[AWS_FPGA_AXI_BUS_ADDR_WIDTH-1:0] araddr; 48 | logic[AWS_FPGA_AXI_BUS_LEN_WIDTH-1:0] arlen; 49 | logic [2:0] arsize; 50 | logic arvalid; 51 | logic arready; 52 | 53 | logic[AWS_FPGA_AXI_BUS_ID_WIDTH-1:0] rid; 54 | logic[AWS_FPGA_AXI_BUS_DATA_WIDTH-1:0] rdata; 55 | logic[1:0] rresp; 56 | logic rlast; 57 | logic rvalid; 58 | logic rready; 59 | 60 | modport master (input awid, awaddr, awlen, awsize, awvalid, output awready, 61 | input wid, wdata, wstrb, wlast, wvalid, output wready, 62 | output bid, bresp, bvalid, input bready, 63 | input arid, araddr, arlen, arsize, arvalid, output arready, 64 | output rid, rdata, rresp, rlast, rvalid, input rready); 65 | 66 | modport slave (output awid, awaddr, awlen, awsize, awvalid, input awready, 67 | output wid, wdata, wstrb, wlast, wvalid, input wready, 68 | input bid, bresp, bvalid, output bready, 69 | output arid, araddr, arlen, arsize, arvalid, input arready, 70 | input rid, rdata, rresp, rlast, rvalid, output rready); 71 | endinterface 72 | 73 | 74 | interface cfg_bus_t; 75 | logic [31:0] addr; 76 | logic [31:0] wdata; 77 | logic wr; 78 | logic rd; 79 | logic ack; 80 | logic[31:0] rdata; 81 | 82 | modport master (input addr, wdata, wr, rd, output ack, rdata); 83 | 84 | modport slave (output addr, wdata, wr, rd, input ack, rdata); 85 | endinterface 86 | 87 | interface scrb_bus_t; 88 | logic [63:0] addr; 89 | logic [2:0] state; 90 | logic enable; 91 | logic done; 92 | 93 | modport master (input enable, output addr, state, done); 94 | 95 | modport slave (output enable, input addr, state, done); 96 | endinterface 97 | 98 | `endif //CL_NVDLA_PKG 99 | -------------------------------------------------------------------------------- /cl_nvdla/design/cl_sim_mem.sv: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: cl_sim_mem.sv 10 | 11 | module cl_sim_mem ( 12 | input clk, 13 | input rstn, 14 | input mem_axi_awvalid, 15 | output mem_axi_awready, 16 | input [63:0] mem_axi_awaddr, 17 | 18 | input mem_axi_wvalid, 19 | output reg mem_axi_wready, 20 | input [63:0] mem_axi_wdata, 21 | input [7:0] mem_axi_wstrb, 22 | 23 | output reg mem_axi_bvalid, 24 | input mem_axi_bready, 25 | output reg [1:0] mem_axi_bresp, 26 | 27 | input mem_axi_arvalid, 28 | output reg mem_axi_arready, 29 | input [63:0] mem_axi_araddr, 30 | 31 | output reg mem_axi_rvalid, 32 | input mem_axi_rready, 33 | output reg [1:0] mem_axi_rresp, 34 | output reg [63:0] mem_axi_rdata 35 | ); 36 | 37 | 38 | // internal signals 39 | wire [63:0] mem_axi_awaddr_t; 40 | reg [63:0] mem_axi_awaddr_reg; 41 | reg mem_axi_write_pend; 42 | reg mem_axi_write_pend_reg; 43 | 44 | wire [63:0] mem_axi_araddr_t; 45 | reg [63:0] mem_axi_araddr_reg; 46 | reg mem_axi_read_pend; 47 | 48 | // write channel 49 | 50 | assign mem_axi_awaddr_t = (mem_axi_awvalid & mem_axi_awready) ? mem_axi_awaddr : mem_axi_awaddr_reg; 51 | always @ (posedge clk or negedge rstn) 52 | if(!rstn) 53 | mem_axi_awaddr_reg <= 64'b0; 54 | else if(mem_axi_awvalid & mem_axi_awready) 55 | mem_axi_awaddr_reg <= mem_axi_awaddr; 56 | 57 | always @ (posedge clk or negedge rstn) 58 | if(!rstn) 59 | mem_axi_write_pend <= 1'b0; 60 | else if(mem_axi_awvalid & mem_axi_awready) 61 | mem_axi_write_pend <= 1'b1; 62 | else if(mem_axi_bvalid & mem_axi_bready) 63 | mem_axi_write_pend <= 1'b0; 64 | assign mem_axi_awready = !mem_axi_write_pend; 65 | 66 | always @ (posedge clk or negedge rstn) 67 | if(!rstn) 68 | mem_axi_write_pend_reg <= 1'b0; 69 | else 70 | mem_axi_write_pend_reg <= mem_axi_write_pend; 71 | 72 | always @ (posedge clk or negedge rstn) 73 | if(!rstn) 74 | mem_axi_wready <= 1'b0; 75 | else if(mem_axi_wvalid & mem_axi_wready) 76 | mem_axi_wready <= 1'b0; 77 | else if(mem_axi_write_pend & !mem_axi_write_pend_reg) 78 | mem_axi_wready <= 1'b1; 79 | 80 | always @ (posedge clk or negedge rstn) 81 | if(!rstn) 82 | mem_axi_bvalid <= 1'b0; 83 | else if(mem_axi_bvalid & mem_axi_bready) 84 | mem_axi_bvalid <= 1'b0; 85 | else if(mem_axi_wvalid & mem_axi_wready) 86 | mem_axi_bvalid <= 1'b1; 87 | 88 | 89 | always @ (posedge clk or negedge rstn) 90 | if(!rstn) begin 91 | mem_axi_bresp <= 2'b0; 92 | end 93 | else begin 94 | if(mem_axi_wvalid & mem_axi_wready) begin 95 | tb.backdoor_mem_write({mem_axi_awaddr_t[63:3],3'b0}, mem_axi_wdata, 8, mem_axi_wstrb); 96 | end 97 | end 98 | 99 | // read channel 100 | 101 | assign mem_axi_araddr_t = (mem_axi_arvalid & mem_axi_arready) ? mem_axi_araddr : mem_axi_araddr_reg; 102 | always @ (posedge clk or negedge rstn) 103 | if(!rstn) 104 | mem_axi_araddr_reg <= 32'b0; 105 | else if(mem_axi_arvalid & mem_axi_arready) 106 | mem_axi_araddr_reg <= mem_axi_araddr; 107 | 108 | always @ (posedge clk or negedge rstn) 109 | if(!rstn) 110 | mem_axi_read_pend <= 1'b0; 111 | else if(mem_axi_arvalid & mem_axi_arready) 112 | mem_axi_read_pend <= 1'b1; 113 | else if(mem_axi_rvalid & mem_axi_rready) 114 | mem_axi_read_pend <= 1'b0; 115 | assign mem_axi_arready = !mem_axi_read_pend; 116 | 117 | always @ (posedge clk or negedge rstn) 118 | if(!rstn) 119 | mem_axi_rvalid <= 1'b0; 120 | else if(mem_axi_rvalid & mem_axi_rready) 121 | mem_axi_rvalid <= 1'b0; 122 | else if(mem_axi_arvalid & mem_axi_arready) 123 | mem_axi_rvalid <= 1'b1; 124 | 125 | always @ (posedge clk or negedge rstn) 126 | if(!rstn) 127 | mem_axi_rresp <= 2'b00; 128 | else if(mem_axi_arvalid & mem_axi_arready) begin 129 | mem_axi_rdata <= tb.backdoor_mem_read({mem_axi_araddr[63:3],3'b0}, 8); 130 | end 131 | 132 | endmodule 133 | -------------------------------------------------------------------------------- /cl_nvdla/design/cl_vio.sv: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | module cl_vio ( 17 | input clk_extra_a1 18 | 19 | ); 20 | 21 | // Counter running at 125MHz 22 | 23 | logic vo_cnt_enable; 24 | logic vo_cnt_load; 25 | logic vo_cnt_clear; 26 | logic vo_cnt_oneshot; 27 | logic [7:0] vo_tick_value; 28 | logic [15:0] vo_cnt_load_value; 29 | logic [15:0] vo_cnt_watermark; 30 | 31 | logic vo_cnt_enable_q = 0; 32 | logic vo_cnt_load_q = 0; 33 | logic vo_cnt_clear_q = 0; 34 | logic vo_cnt_oneshot_q = 0; 35 | logic [7:0] vo_tick_value_q = 0; 36 | logic [15:0] vo_cnt_load_value_q = 0; 37 | logic [15:0] vo_cnt_watermark_q = 0; 38 | 39 | logic vi_tick; 40 | logic vi_cnt_ge_watermark; 41 | logic [7:0] vi_tick_cnt = 0; 42 | logic [15:0] vi_cnt = 0; 43 | 44 | // Tick counter and main counter 45 | always @(posedge clk_extra_a1) begin 46 | 47 | vo_cnt_enable_q <= vo_cnt_enable ; 48 | vo_cnt_load_q <= vo_cnt_load ; 49 | vo_cnt_clear_q <= vo_cnt_clear ; 50 | vo_cnt_oneshot_q <= vo_cnt_oneshot ; 51 | vo_tick_value_q <= vo_tick_value ; 52 | vo_cnt_load_value_q <= vo_cnt_load_value; 53 | vo_cnt_watermark_q <= vo_cnt_watermark ; 54 | 55 | vi_tick_cnt = vo_cnt_clear_q ? 0 : 56 | ~vo_cnt_enable_q ? vi_tick_cnt : 57 | (vi_tick_cnt >= vo_tick_value_q) ? 0 : 58 | vi_tick_cnt + 1; 59 | 60 | vi_cnt = vo_cnt_clear_q ? 0 : 61 | vo_cnt_load_q ? vo_cnt_load_value_q : 62 | ~vo_cnt_enable_q ? vi_cnt : 63 | (vi_tick_cnt >= vo_tick_value_q) && (~vo_cnt_oneshot_q || (vi_cnt <= 16'hFFFF)) ? vi_cnt + 1 : 64 | vi_cnt; 65 | 66 | vi_tick = (vi_tick_cnt >= vo_tick_value_q); 67 | 68 | vi_cnt_ge_watermark = (vi_cnt >= vo_cnt_watermark_q); 69 | 70 | end // always @ (posedge clk_extra_a1) 71 | 72 | 73 | vio_0 CL_VIO_0 ( 74 | .clk (clk_extra_a1), 75 | .probe_in0 (vi_tick), 76 | .probe_in1 (vi_cnt_ge_watermark), 77 | .probe_in2 (vi_tick_cnt), 78 | .probe_in3 (vi_cnt), 79 | .probe_out0 (vo_cnt_enable), 80 | .probe_out1 (vo_cnt_load), 81 | .probe_out2 (vo_cnt_clear), 82 | .probe_out3 (vo_cnt_oneshot), 83 | .probe_out4 (vo_tick_value), 84 | .probe_out5 (vo_cnt_load_value), 85 | .probe_out6 (vo_cnt_watermark) 86 | ); 87 | 88 | ila_vio_counter CL_VIO_ILA ( 89 | .clk (clk_extra_a1), 90 | .probe0 (vi_tick), 91 | .probe1 (vi_cnt_ge_watermark), 92 | .probe2 (vi_tick_cnt), 93 | .probe3 (vi_cnt), 94 | .probe4 (vo_cnt_enable_q), 95 | .probe5 (vo_cnt_load_q), 96 | .probe6 (vo_cnt_clear_q), 97 | .probe7 (vo_cnt_oneshot_q), 98 | .probe8 (vo_tick_value_q), 99 | .probe9 (vo_cnt_load_value_q), 100 | .probe10 (vo_cnt_watermark_q) 101 | ); 102 | 103 | 104 | endmodule 105 | 106 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_model: -------------------------------------------------------------------------------- 1 | nv_ram_rws_128x18.v 2 | nv_ram_rws_16x256.v 3 | nv_ram_rws_16x272.v 4 | nv_ram_rws_16x64.v 5 | nv_ram_rws_256x3.v 6 | nv_ram_rws_256x512.v 7 | nv_ram_rws_256x7.v 8 | nv_ram_rws_32x16.v 9 | nv_ram_rws_32x512.v 10 | nv_ram_rws_32x544.v 11 | nv_ram_rws_32x768.v 12 | nv_ram_rws_512x512.v 13 | nv_ram_rws_512x64.v 14 | nv_ram_rws_64x10.v 15 | nv_ram_rws_64x1024.v 16 | nv_ram_rws_64x1088.v 17 | nv_ram_rws_64x116.v 18 | nv_ram_rws_64x18.v 19 | nv_ram_rwsp_128x11.v 20 | nv_ram_rwsp_128x6.v 21 | nv_ram_rwsp_160x16.v 22 | nv_ram_rwsp_160x514.v 23 | nv_ram_rwsp_160x65.v 24 | nv_ram_rwsp_20x289.v 25 | nv_ram_rwsp_245x514.v 26 | nv_ram_rwsp_256x11.v 27 | nv_ram_rwsp_32x32.v 28 | nv_ram_rwsp_61x514.v 29 | nv_ram_rwsp_61x64.v 30 | nv_ram_rwsp_61x65.v 31 | nv_ram_rwsp_80x14.v 32 | nv_ram_rwsp_80x16.v 33 | nv_ram_rwsp_80x256.v 34 | nv_ram_rwsp_80x514.v 35 | nv_ram_rwsp_80x65.v 36 | nv_ram_rwst_256x8.v 37 | nv_ram_rwsthp_19x32.v 38 | nv_ram_rwsthp_19x4.v 39 | nv_ram_rwsthp_19x80.v 40 | nv_ram_rwsthp_60x168.v 41 | nv_ram_rwsthp_60x21.v 42 | nv_ram_rwsthp_80x15.v 43 | nv_ram_rwsthp_80x72.v 44 | nv_ram_rwsthp_80x9.v 45 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_128x18.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_128x18.v 10 | 11 | module nv_ram_rws_128x18 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [6:0] ra; 27 | input re; 28 | output [17:0] dout; 29 | input [6:0] wa; 30 | input we; 31 | input [17:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [6:0] ra_d; 36 | wire [17:0] dout; 37 | reg [17:0] M [127:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_16x256.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_16x256.v 10 | 11 | module nv_ram_rws_16x256 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [3:0] ra; 27 | input re; 28 | output [255:0] dout; 29 | input [3:0] wa; 30 | input we; 31 | input [255:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [3:0] ra_d; 36 | wire [255:0] dout; 37 | reg [255:0] M [15:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_16x272.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_16x272.v 10 | 11 | module nv_ram_rws_16x272 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [3:0] ra; 27 | input re; 28 | output [271:0] dout; 29 | input [3:0] wa; 30 | input we; 31 | input [271:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [3:0] ra_d; 36 | wire [271:0] dout; 37 | reg [271:0] M [15:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_16x64.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_16x64.v 10 | 11 | module nv_ram_rws_16x64 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [3:0] ra; 27 | input re; 28 | output [63:0] dout; 29 | input [3:0] wa; 30 | input we; 31 | input [63:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [3:0] ra_d; 36 | wire [63:0] dout; 37 | reg [63:0] M [15:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_256x3.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_256x3.v 10 | 11 | module nv_ram_rws_256x3 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [7:0] ra; 27 | input re; 28 | output [2:0] dout; 29 | input [7:0] wa; 30 | input we; 31 | input [2:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [7:0] ra_d; 36 | wire [2:0] dout; 37 | reg [2:0] M [255:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_256x512.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_256x512.v 10 | 11 | module nv_ram_rws_256x512 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [7:0] ra; 27 | input re; 28 | output [511:0] dout; 29 | input [7:0] wa; 30 | input we; 31 | input [511:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [7:0] ra_d; 36 | wire [511:0] dout; 37 | reg [511:0] M [255:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_256x7.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_256x7.v 10 | 11 | module nv_ram_rws_256x7 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [7:0] ra; 27 | input re; 28 | output [6:0] dout; 29 | input [7:0] wa; 30 | input we; 31 | input [6:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [7:0] ra_d; 36 | wire [6:0] dout; 37 | reg [6:0] M [255:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_32x16.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_32x16.v 10 | 11 | module nv_ram_rws_32x16 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [4:0] ra; 27 | input re; 28 | output [15:0] dout; 29 | input [4:0] wa; 30 | input we; 31 | input [15:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [4:0] ra_d; 36 | wire [15:0] dout; 37 | reg [15:0] M [31:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_32x512.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_32x512.v 10 | 11 | module nv_ram_rws_32x512 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [4:0] ra; 27 | input re; 28 | output [511:0] dout; 29 | input [4:0] wa; 30 | input we; 31 | input [511:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [4:0] ra_d; 36 | wire [511:0] dout; 37 | reg [511:0] M [31:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_32x544.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_32x544.v 10 | 11 | module nv_ram_rws_32x544 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [4:0] ra; 27 | input re; 28 | output [543:0] dout; 29 | input [4:0] wa; 30 | input we; 31 | input [543:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [4:0] ra_d; 36 | wire [543:0] dout; 37 | reg [543:0] M [31:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_32x768.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_32x768.v 10 | 11 | module nv_ram_rws_32x768 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [4:0] ra; 27 | input re; 28 | output [767:0] dout; 29 | input [4:0] wa; 30 | input we; 31 | input [767:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [4:0] ra_d; 36 | wire [767:0] dout; 37 | reg [767:0] M [31:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_512x512.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_512x512.v 10 | 11 | module nv_ram_rws_512x512 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [8:0] ra; 27 | input re; 28 | output [511:0] dout; 29 | input [8:0] wa; 30 | input we; 31 | input [511:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [8:0] ra_d; 36 | wire [511:0] dout; 37 | reg [511:0] M [511:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_512x64.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_512x64.v 10 | 11 | module nv_ram_rws_512x64 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [8:0] ra; 27 | input re; 28 | output [63:0] dout; 29 | input [8:0] wa; 30 | input we; 31 | input [63:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [8:0] ra_d; 36 | wire [63:0] dout; 37 | reg [63:0] M [511:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_64x10.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_64x10.v 10 | 11 | module nv_ram_rws_64x10 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [5:0] ra; 27 | input re; 28 | output [9:0] dout; 29 | input [5:0] wa; 30 | input we; 31 | input [9:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [5:0] ra_d; 36 | wire [9:0] dout; 37 | reg [9:0] M [63:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_64x1024.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_64x1024.v 10 | 11 | module nv_ram_rws_64x1024 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [5:0] ra; 27 | input re; 28 | output [1023:0] dout; 29 | input [5:0] wa; 30 | input we; 31 | input [1023:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [5:0] ra_d; 36 | wire [1023:0] dout; 37 | reg [1023:0] M [63:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_64x1088.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_64x1088.v 10 | 11 | module nv_ram_rws_64x1088 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [5:0] ra; 27 | input re; 28 | output [1087:0] dout; 29 | input [5:0] wa; 30 | input we; 31 | input [1087:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [5:0] ra_d; 36 | wire [1087:0] dout; 37 | reg [1087:0] M [63:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_64x116.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_64x116.v 10 | 11 | module nv_ram_rws_64x116 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [5:0] ra; 27 | input re; 28 | output [115:0] dout; 29 | input [5:0] wa; 30 | input we; 31 | input [115:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [5:0] ra_d; 36 | wire [115:0] dout; 37 | reg [115:0] M [63:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rws_64x18.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rws_64x18.v 10 | 11 | module nv_ram_rws_64x18 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [5:0] ra; 27 | input re; 28 | output [17:0] dout; 29 | input [5:0] wa; 30 | input we; 31 | input [17:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [5:0] ra_d; 36 | wire [17:0] dout; 37 | reg [17:0] M [63:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_128x11.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_128x11.v 10 | 11 | module nv_ram_rwsp_128x11 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [6:0] ra; 28 | input re; 29 | input ore; 30 | output [10:0] dout; 31 | input [6:0] wa; 32 | input we; 33 | input [10:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [6:0] ra_d; 38 | wire [10:0] dout; 39 | reg [10:0] M [127:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [10:0] dout_ram = M[ra_d]; 52 | 53 | reg [10:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_128x6.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_128x6.v 10 | 11 | module nv_ram_rwsp_128x6 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [6:0] ra; 28 | input re; 29 | input ore; 30 | output [5:0] dout; 31 | input [6:0] wa; 32 | input we; 33 | input [5:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [6:0] ra_d; 38 | wire [5:0] dout; 39 | reg [5:0] M [127:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [5:0] dout_ram = M[ra_d]; 52 | 53 | reg [5:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_160x16.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_160x16.v 10 | 11 | module nv_ram_rwsp_160x16 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [7:0] ra; 28 | input re; 29 | input ore; 30 | output [15:0] dout; 31 | input [7:0] wa; 32 | input we; 33 | input [15:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [7:0] ra_d; 38 | wire [15:0] dout; 39 | reg [15:0] M [159:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [15:0] dout_ram = M[ra_d]; 52 | 53 | reg [15:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_160x514.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_160x514.v 10 | 11 | module nv_ram_rwsp_160x514 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [7:0] ra; 28 | input re; 29 | input ore; 30 | output [513:0] dout; 31 | input [7:0] wa; 32 | input we; 33 | input [513:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [7:0] ra_d; 38 | wire [513:0] dout; 39 | reg [513:0] M [159:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [513:0] dout_ram = M[ra_d]; 52 | 53 | reg [513:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_160x65.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_160x65.v 10 | 11 | module nv_ram_rwsp_160x65 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [7:0] ra; 28 | input re; 29 | input ore; 30 | output [64:0] dout; 31 | input [7:0] wa; 32 | input we; 33 | input [64:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [7:0] ra_d; 38 | wire [64:0] dout; 39 | reg [64:0] M [159:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [64:0] dout_ram = M[ra_d]; 52 | 53 | reg [64:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_20x289.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_20x289.v 10 | 11 | module nv_ram_rwsp_20x289 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [4:0] ra; 28 | input re; 29 | input ore; 30 | output [288:0] dout; 31 | input [4:0] wa; 32 | input we; 33 | input [288:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [4:0] ra_d; 38 | wire [288:0] dout; 39 | reg [288:0] M [19:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [288:0] dout_ram = M[ra_d]; 52 | 53 | reg [288:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_245x514.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_245x514.v 10 | 11 | module nv_ram_rwsp_245x514 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [7:0] ra; 28 | input re; 29 | input ore; 30 | output [513:0] dout; 31 | input [7:0] wa; 32 | input we; 33 | input [513:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [7:0] ra_d; 38 | wire [513:0] dout; 39 | reg [513:0] M [244:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [513:0] dout_ram = M[ra_d]; 52 | 53 | reg [513:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_256x11.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_256x11.v 10 | 11 | module nv_ram_rwsp_256x11 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [7:0] ra; 28 | input re; 29 | input ore; 30 | output [10:0] dout; 31 | input [7:0] wa; 32 | input we; 33 | input [10:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [7:0] ra_d; 38 | wire [10:0] dout; 39 | reg [10:0] M [255:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [10:0] dout_ram = M[ra_d]; 52 | 53 | reg [10:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_32x32.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_32x32.v 10 | 11 | module nv_ram_rwsp_32x32 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [4:0] ra; 28 | input re; 29 | input ore; 30 | output [31:0] dout; 31 | input [4:0] wa; 32 | input we; 33 | input [31:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [4:0] ra_d; 38 | wire [31:0] dout; 39 | reg [31:0] M [31:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [31:0] dout_ram = M[ra_d]; 52 | 53 | reg [31:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_61x514.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_61x514.v 10 | 11 | module nv_ram_rwsp_61x514 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [5:0] ra; 28 | input re; 29 | input ore; 30 | output [513:0] dout; 31 | input [5:0] wa; 32 | input we; 33 | input [513:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [5:0] ra_d; 38 | wire [513:0] dout; 39 | reg [513:0] M [60:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [513:0] dout_ram = M[ra_d]; 52 | 53 | reg [513:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_61x64.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_61x64.v 10 | 11 | module nv_ram_rwsp_61x64 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [5:0] ra; 28 | input re; 29 | input ore; 30 | output [63:0] dout; 31 | input [5:0] wa; 32 | input we; 33 | input [63:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [5:0] ra_d; 38 | wire [63:0] dout; 39 | reg [63:0] M [60:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [63:0] dout_ram = M[ra_d]; 52 | 53 | reg [63:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_61x65.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_61x65.v 10 | 11 | module nv_ram_rwsp_61x65 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [5:0] ra; 28 | input re; 29 | input ore; 30 | output [64:0] dout; 31 | input [5:0] wa; 32 | input we; 33 | input [64:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [5:0] ra_d; 38 | wire [64:0] dout; 39 | reg [64:0] M [60:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [64:0] dout_ram = M[ra_d]; 52 | 53 | reg [64:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_80x14.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_80x14.v 10 | 11 | module nv_ram_rwsp_80x14 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [6:0] ra; 28 | input re; 29 | input ore; 30 | output [13:0] dout; 31 | input [6:0] wa; 32 | input we; 33 | input [13:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [6:0] ra_d; 38 | wire [13:0] dout; 39 | reg [13:0] M [79:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [13:0] dout_ram = M[ra_d]; 52 | 53 | reg [13:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_80x16.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_80x16.v 10 | 11 | module nv_ram_rwsp_80x16 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [6:0] ra; 28 | input re; 29 | input ore; 30 | output [15:0] dout; 31 | input [6:0] wa; 32 | input we; 33 | input [15:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [6:0] ra_d; 38 | wire [15:0] dout; 39 | reg [15:0] M [79:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [15:0] dout_ram = M[ra_d]; 52 | 53 | reg [15:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_80x256.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_80x256.v 10 | 11 | module nv_ram_rwsp_80x256 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [6:0] ra; 28 | input re; 29 | input ore; 30 | output [255:0] dout; 31 | input [6:0] wa; 32 | input we; 33 | input [255:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [6:0] ra_d; 38 | wire [255:0] dout; 39 | reg [255:0] M [79:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [255:0] dout_ram = M[ra_d]; 52 | 53 | reg [255:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_80x514.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_80x514.v 10 | 11 | module nv_ram_rwsp_80x514 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [6:0] ra; 28 | input re; 29 | input ore; 30 | output [513:0] dout; 31 | input [6:0] wa; 32 | input we; 33 | input [513:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [6:0] ra_d; 38 | wire [513:0] dout; 39 | reg [513:0] M [79:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [513:0] dout_ram = M[ra_d]; 52 | 53 | reg [513:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsp_80x65.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsp_80x65.v 10 | 11 | module nv_ram_rwsp_80x65 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | pwrbus_ram_pd 21 | ); 22 | 23 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 24 | 25 | // port list 26 | input clk; 27 | input [6:0] ra; 28 | input re; 29 | input ore; 30 | output [64:0] dout; 31 | input [6:0] wa; 32 | input we; 33 | input [64:0] di; 34 | input [31:0] pwrbus_ram_pd; 35 | 36 | //reg and wire list 37 | reg [6:0] ra_d; 38 | wire [64:0] dout; 39 | reg [64:0] M [79:0]; 40 | 41 | always @( posedge clk ) begin 42 | if (we) 43 | M[wa] <= di; 44 | end 45 | 46 | always @( posedge clk ) begin 47 | if (re) 48 | ra_d <= ra; 49 | end 50 | 51 | wire [64:0] dout_ram = M[ra_d]; 52 | 53 | reg [64:0] dout_r; 54 | always @( posedge clk ) begin 55 | if (ore) 56 | dout_r <= dout_ram; 57 | end 58 | 59 | assign dout = dout_r; 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwst_256x8.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwst_256x8.v 10 | 11 | module nv_ram_rwst_256x8 ( 12 | clk, 13 | ra, 14 | re, 15 | dout, 16 | wa, 17 | we, 18 | di, 19 | pwrbus_ram_pd 20 | ); 21 | 22 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 23 | 24 | // port list 25 | input clk; 26 | input [7:0] ra; 27 | input re; 28 | output [7:0] dout; 29 | input [7:0] wa; 30 | input we; 31 | input [7:0] di; 32 | input [31:0] pwrbus_ram_pd; 33 | 34 | //reg and wire list 35 | reg [7:0] ra_d; 36 | wire [7:0] dout; 37 | reg [7:0] M [255:0]; 38 | 39 | always @( posedge clk ) begin 40 | if (we) 41 | M[wa] <= di; 42 | end 43 | 44 | always @( posedge clk ) begin 45 | if (re) 46 | ra_d <= ra; 47 | end 48 | assign dout = M[ra_d]; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsthp_19x32.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsthp_19x32.v 10 | 11 | module nv_ram_rwsthp_19x32 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | byp_sel, 21 | dbyp, 22 | pwrbus_ram_pd 23 | ); 24 | 25 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 26 | 27 | // port list 28 | input clk; 29 | input [4:0] ra; 30 | input re; 31 | input ore; 32 | output [31:0] dout; 33 | input [4:0] wa; 34 | input we; 35 | input [31:0] di; 36 | input byp_sel; 37 | input [31:0] dbyp; 38 | input [31:0] pwrbus_ram_pd; 39 | 40 | //reg and wire list 41 | reg [4:0] ra_d; 42 | wire [31:0] dout; 43 | reg [31:0] M [18:0]; 44 | 45 | always @( posedge clk ) begin 46 | if (we) 47 | M[wa] <= di; 48 | end 49 | 50 | always @( posedge clk ) begin 51 | if (re) 52 | ra_d <= ra; 53 | end 54 | 55 | wire [31:0] dout_ram = M[ra_d]; 56 | 57 | wire [31:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); 58 | 59 | reg [31:0] dout_r; 60 | always @( posedge clk ) begin 61 | if (ore) 62 | dout_r <= fbypass_dout_ram; 63 | end 64 | 65 | assign dout = dout_r; 66 | 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsthp_19x4.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsthp_19x4.v 10 | 11 | module nv_ram_rwsthp_19x4 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | byp_sel, 21 | dbyp, 22 | pwrbus_ram_pd 23 | ); 24 | 25 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 26 | 27 | // port list 28 | input clk; 29 | input [4:0] ra; 30 | input re; 31 | input ore; 32 | output [3:0] dout; 33 | input [4:0] wa; 34 | input we; 35 | input [3:0] di; 36 | input byp_sel; 37 | input [3:0] dbyp; 38 | input [31:0] pwrbus_ram_pd; 39 | 40 | //reg and wire list 41 | reg [4:0] ra_d; 42 | wire [3:0] dout; 43 | reg [3:0] M [18:0]; 44 | 45 | always @( posedge clk ) begin 46 | if (we) 47 | M[wa] <= di; 48 | end 49 | 50 | always @( posedge clk ) begin 51 | if (re) 52 | ra_d <= ra; 53 | end 54 | 55 | wire [3:0] dout_ram = M[ra_d]; 56 | 57 | wire [3:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); 58 | 59 | reg [3:0] dout_r; 60 | always @( posedge clk ) begin 61 | if (ore) 62 | dout_r <= fbypass_dout_ram; 63 | end 64 | 65 | assign dout = dout_r; 66 | 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsthp_19x80.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsthp_19x80.v 10 | 11 | module nv_ram_rwsthp_19x80 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | byp_sel, 21 | dbyp, 22 | pwrbus_ram_pd 23 | ); 24 | 25 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 26 | 27 | // port list 28 | input clk; 29 | input [4:0] ra; 30 | input re; 31 | input ore; 32 | output [79:0] dout; 33 | input [4:0] wa; 34 | input we; 35 | input [79:0] di; 36 | input byp_sel; 37 | input [79:0] dbyp; 38 | input [31:0] pwrbus_ram_pd; 39 | 40 | //reg and wire list 41 | reg [4:0] ra_d; 42 | wire [79:0] dout; 43 | reg [79:0] M [18:0]; 44 | 45 | always @( posedge clk ) begin 46 | if (we) 47 | M[wa] <= di; 48 | end 49 | 50 | always @( posedge clk ) begin 51 | if (re) 52 | ra_d <= ra; 53 | end 54 | 55 | wire [79:0] dout_ram = M[ra_d]; 56 | 57 | wire [79:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); 58 | 59 | reg [79:0] dout_r; 60 | always @( posedge clk ) begin 61 | if (ore) 62 | dout_r <= fbypass_dout_ram; 63 | end 64 | 65 | assign dout = dout_r; 66 | 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsthp_60x168.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsthp_60x168.v 10 | 11 | module nv_ram_rwsthp_60x168 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | byp_sel, 21 | dbyp, 22 | pwrbus_ram_pd 23 | ); 24 | 25 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 26 | 27 | // port list 28 | input clk; 29 | input [5:0] ra; 30 | input re; 31 | input ore; 32 | output [167:0] dout; 33 | input [5:0] wa; 34 | input we; 35 | input [167:0] di; 36 | input byp_sel; 37 | input [167:0] dbyp; 38 | input [31:0] pwrbus_ram_pd; 39 | 40 | //reg and wire list 41 | reg [5:0] ra_d; 42 | wire [167:0] dout; 43 | reg [167:0] M [59:0]; 44 | 45 | always @( posedge clk ) begin 46 | if (we) 47 | M[wa] <= di; 48 | end 49 | 50 | always @( posedge clk ) begin 51 | if (re) 52 | ra_d <= ra; 53 | end 54 | 55 | wire [167:0] dout_ram = M[ra_d]; 56 | 57 | wire [167:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); 58 | 59 | reg [167:0] dout_r; 60 | always @( posedge clk ) begin 61 | if (ore) 62 | dout_r <= fbypass_dout_ram; 63 | end 64 | 65 | assign dout = dout_r; 66 | 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsthp_60x21.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsthp_60x21.v 10 | 11 | module nv_ram_rwsthp_60x21 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | byp_sel, 21 | dbyp, 22 | pwrbus_ram_pd 23 | ); 24 | 25 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 26 | 27 | // port list 28 | input clk; 29 | input [5:0] ra; 30 | input re; 31 | input ore; 32 | output [20:0] dout; 33 | input [5:0] wa; 34 | input we; 35 | input [20:0] di; 36 | input byp_sel; 37 | input [20:0] dbyp; 38 | input [31:0] pwrbus_ram_pd; 39 | 40 | //reg and wire list 41 | reg [5:0] ra_d; 42 | wire [20:0] dout; 43 | reg [20:0] M [59:0]; 44 | 45 | always @( posedge clk ) begin 46 | if (we) 47 | M[wa] <= di; 48 | end 49 | 50 | always @( posedge clk ) begin 51 | if (re) 52 | ra_d <= ra; 53 | end 54 | 55 | wire [20:0] dout_ram = M[ra_d]; 56 | 57 | wire [20:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); 58 | 59 | reg [20:0] dout_r; 60 | always @( posedge clk ) begin 61 | if (ore) 62 | dout_r <= fbypass_dout_ram; 63 | end 64 | 65 | assign dout = dout_r; 66 | 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsthp_80x15.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsthp_80x15.v 10 | 11 | module nv_ram_rwsthp_80x15 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | byp_sel, 21 | dbyp, 22 | pwrbus_ram_pd 23 | ); 24 | 25 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 26 | 27 | // port list 28 | input clk; 29 | input [6:0] ra; 30 | input re; 31 | input ore; 32 | output [14:0] dout; 33 | input [6:0] wa; 34 | input we; 35 | input [14:0] di; 36 | input byp_sel; 37 | input [14:0] dbyp; 38 | input [31:0] pwrbus_ram_pd; 39 | 40 | //reg and wire list 41 | reg [6:0] ra_d; 42 | wire [14:0] dout; 43 | reg [14:0] M [79:0]; 44 | 45 | always @( posedge clk ) begin 46 | if (we) 47 | M[wa] <= di; 48 | end 49 | 50 | always @( posedge clk ) begin 51 | if (re) 52 | ra_d <= ra; 53 | end 54 | 55 | wire [14:0] dout_ram = M[ra_d]; 56 | 57 | wire [14:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); 58 | 59 | reg [14:0] dout_r; 60 | always @( posedge clk ) begin 61 | if (ore) 62 | dout_r <= fbypass_dout_ram; 63 | end 64 | 65 | assign dout = dout_r; 66 | 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsthp_80x72.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsthp_80x72.v 10 | 11 | module nv_ram_rwsthp_80x72 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | byp_sel, 21 | dbyp, 22 | pwrbus_ram_pd 23 | ); 24 | 25 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 26 | 27 | // port list 28 | input clk; 29 | input [6:0] ra; 30 | input re; 31 | input ore; 32 | output [71:0] dout; 33 | input [6:0] wa; 34 | input we; 35 | input [71:0] di; 36 | input byp_sel; 37 | input [71:0] dbyp; 38 | input [31:0] pwrbus_ram_pd; 39 | 40 | //reg and wire list 41 | reg [6:0] ra_d; 42 | wire [71:0] dout; 43 | reg [71:0] M [79:0]; 44 | 45 | always @( posedge clk ) begin 46 | if (we) 47 | M[wa] <= di; 48 | end 49 | 50 | always @( posedge clk ) begin 51 | if (re) 52 | ra_d <= ra; 53 | end 54 | 55 | wire [71:0] dout_ram = M[ra_d]; 56 | 57 | wire [71:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); 58 | 59 | reg [71:0] dout_r; 60 | always @( posedge clk ) begin 61 | if (ore) 62 | dout_r <= fbypass_dout_ram; 63 | end 64 | 65 | assign dout = dout_r; 66 | 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /cl_nvdla/design/rams/nv_ram_rwsthp_80x9.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: nv_ram_rwsthp_80x9.v 10 | 11 | module nv_ram_rwsthp_80x9 ( 12 | clk, 13 | ra, 14 | re, 15 | ore, 16 | dout, 17 | wa, 18 | we, 19 | di, 20 | byp_sel, 21 | dbyp, 22 | pwrbus_ram_pd 23 | ); 24 | 25 | parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; 26 | 27 | // port list 28 | input clk; 29 | input [6:0] ra; 30 | input re; 31 | input ore; 32 | output [8:0] dout; 33 | input [6:0] wa; 34 | input we; 35 | input [8:0] di; 36 | input byp_sel; 37 | input [8:0] dbyp; 38 | input [31:0] pwrbus_ram_pd; 39 | 40 | //reg and wire list 41 | reg [6:0] ra_d; 42 | wire [8:0] dout; 43 | reg [8:0] M [79:0]; 44 | 45 | always @( posedge clk ) begin 46 | if (we) 47 | M[wa] <= di; 48 | end 49 | 50 | always @( posedge clk ) begin 51 | if (re) 52 | ra_d <= ra; 53 | end 54 | 55 | wire [8:0] dout_ram = M[ra_d]; 56 | 57 | wire [8:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); 58 | 59 | reg [8:0] dout_r; 60 | always @( posedge clk ) begin 61 | if (ore) 62 | dout_r <= fbypass_dout_ram; 63 | end 64 | 65 | assign dout = dout_r; 66 | 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /cl_nvdla/software/src/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | # NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | #VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 20 | 21 | .PHONY: default 22 | default: all 23 | 24 | NVDLA_HW_ROOT ?= $(abspath ../../../../../../hw) 25 | NVDLA_HW_PROJECT ?= nv_small 26 | 27 | NVDLA_TRACE_PLAYER_ROOT ?= $(abspath ../../../common/trace_player) 28 | NVDLA_TRACE_PLAYER_CFLAGS = "-DDEBUG -g" 29 | NVDLA_REGISTER_HEADER_DIR ?= $(NVDLA_HW_ROOT)/outdir/$(NVDLA_HW_PROJECT)/spec/manual 30 | NVDLA_TRACE ?= ../test_bdma/test_bdma.cfg 31 | 32 | include $(NVDLA_TRACE_PLAYER_ROOT)/Makefile.inc 33 | 34 | VPATH = src:../../../common/software/src:$(NVDLA_TRACE_PLAYER_SRC_DIR) 35 | INCLUDES = -I../../../common/software/include -I../include -I$(NVDLA_REGISTER_HEADER_DIR) -I$(NVDLA_TRACE_PLAYER_INCLUDES) 36 | ifndef VP_TEST 37 | INCLUDES += -I$(SDK_DIR)/userspace/include 38 | endif 39 | 40 | ifdef VP_TEST 41 | CC = aarch64-linux-gnu-gcc 42 | else 43 | CC = gcc 44 | endif 45 | CFLAGS = -DCONFIG_LOGLEVEL=4 -g -Wall $(INCLUDES) 46 | ifdef VP_TEST 47 | CFLAGS += -DVP_TEST 48 | else 49 | CFLAGS += -L$(SDK_DIR)/userspace/lib/so 50 | endif 51 | 52 | LDFLAGS = -Wl,-rpath $(NVDLA_TRACE_PLAYER_LIB_DIR) -L$(NVDLA_TRACE_PLAYER_LIB_DIR) 53 | LDLIBS = -l$(NVDLA_TRACE_PLAYER_LIB) 54 | ifndef VP_TEST 55 | LDLIBS += -lfpga_mgmt -lrt -lpthread 56 | endif 57 | 58 | SRC = trace_test.c trace_test_impl.c cl_common_utils.c 59 | OBJ = $(SRC:.c=.o) 60 | ifdef VP_TEST 61 | BIN = aarch64_trace_test 62 | else 63 | BIN = trace_test 64 | endif 65 | 66 | ifdef VP_TEST 67 | all: $(NVDLA_TRACE_PARSER_COMMAND_LIB) $(NVDLA_TRACE_PLAYER_LIB_DIR)/$(NVDLA_TRACE_PLAYER_LIB) $(BIN) 68 | else 69 | all: $(NVDLA_TRACE_PARSER_COMMAND_LIB) $(NVDLA_TRACE_PLAYER_LIB_DIR)/$(NVDLA_TRACE_PLAYER_LIB) $(BIN) check_env 70 | endif 71 | 72 | $(BIN): $(OBJ) 73 | $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LDLIBS) 74 | 75 | clean: 76 | rm -f *.o $(BIN) $(NVDLA_TRACE_PARSER_COMMAND_SRC) $(NVDLA_TRACE_PARSER_COMMAND_OBJ) $(NVDLA_TRACE_PARSER_COMMAND_LIB) *.dat *.log 77 | 78 | ifndef VP_TEST 79 | check_env: 80 | ifndef SDK_DIR 81 | $(error SDK_DIR is undefined. Try "source sdk_setup.sh" to set the software environment) 82 | endif 83 | endif 84 | -------------------------------------------------------------------------------- /cl_nvdla/software/src/test_null.c: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | #include 17 | #include 18 | #include 19 | 20 | // Vivado does not support svGetScopeFromName 21 | #ifdef INCLUDE_DPI_CALLS 22 | #ifndef VIVADO_SIM 23 | #include "svdpi.h" 24 | #endif 25 | #endif 26 | 27 | #include "sh_dpi_tasks.h" 28 | 29 | void test_main(uint32_t *exit_code) { 30 | 31 | // NULL Test 32 | 33 | *exit_code = 0; 34 | } 35 | -------------------------------------------------------------------------------- /cl_nvdla/software/traces/bdma_sanity/bdma_sanity.cfg: -------------------------------------------------------------------------------- 1 | mem_load(pri_mem, 0xC0000000, "bdma_sanity_input.dat"); 2 | reg_write(NVDLA_BDMA.CFG_SRC_ADDR_HIGH_0, 0); 3 | reg_write(NVDLA_BDMA.CFG_SRC_ADDR_LOW_0, 0xC0000000); 4 | reg_write(NVDLA_BDMA.CFG_DST_ADDR_HIGH_0, 0); 5 | reg_write(NVDLA_BDMA.CFG_DST_ADDR_LOW_0 , 0xC00017C0); 6 | reg_write(NVDLA_BDMA.CFG_DST_SURF_0, 0x800); 7 | reg_write(NVDLA_BDMA.CFG_DST_LINE_0, 0x100); 8 | reg_write(NVDLA_BDMA.CFG_SRC_SURF_0, 0x800); 9 | reg_write(NVDLA_BDMA.CFG_SRC_LINE_0, 0x100); 10 | reg_write(NVDLA_BDMA.CFG_SURF_REPEAT_0, 0); 11 | reg_write(NVDLA_BDMA.CFG_LINE_REPEAT_0, 7); 12 | reg_write(NVDLA_BDMA.CFG_LINE_0, 7); 13 | reg_write(NVDLA_BDMA.CFG_CMD_0, 3); 14 | reg_write(NVDLA_BDMA.CFG_OP_0, 1); 15 | reg_write(NVDLA_BDMA.CFG_LAUNCH0_0, 1); 16 | intr_notify(BDMA_0, BDMA_0_BDMA_0_interrupt); 17 | check_file(BDMA_0_BDMA_0_interrupt, pri_mem, 0xC00017C0, 0x800, "bdma_sanity_output.dat"); 18 | -------------------------------------------------------------------------------- /cl_nvdla/verif/README.md: -------------------------------------------------------------------------------- 1 | # CL_NVDLA Simulation 2 | 3 | The cl_nvdla includes a basic test that exercises the BAR1, DDR_C, and interrupt. 4 | 5 | The test can be run from the [verif/scripts] (scripts) directory with one of three different simulators: 6 | 7 | ``` 8 | $ make C_TEST=test_nvdla 9 | $ make C_TEST=test_nvdla VCS=1 10 | $ make C_TEST=test_nvdla QUESTA=1 11 | ``` 12 | 13 | Note that the appropriate simulators must be installed. 14 | 15 | -------------------------------------------------------------------------------- /cl_nvdla/verif/regression/nv_large_sanity: -------------------------------------------------------------------------------- 1 | cdp_8x8x64_lrn9_int8_0 2 | cdp_passthrough_8x8x32_pack_inc_int8 3 | dc_8x16x128_3x3x128x32_int8 4 | dc_8x8x32_1x1x32x32_int8_0 5 | img_51x96x4_1x10x4x32_R8G8B8A8_int8_0 6 | pdp_3x3x33_2x2_ave_int8_0 7 | pdp_8x8x32_1x1_max_int8_0 8 | pdp_passthrough_8x8x32_pack_all_zero_int8 9 | pdp_passthrough_8x8x32_pack_inc_int8 10 | sdp_13x4x29_ew_lut_int8 11 | sdp_passthrough_8x8x32_pack_all_zero_int8 12 | sdp_passthrough_8x8x32_pack_inc_int8 13 | -------------------------------------------------------------------------------- /cl_nvdla/verif/regression/nv_medium_1024_full_sanity: -------------------------------------------------------------------------------- 1 | cdp_8x8x64_lrn9_int8_0 2 | dc_8x16x128_3x3x128x32_int8 3 | img_51x96x4_1x10x4x32_R8G8B8A8_int8_0 4 | pdp_8x8x32_1x1_max_int8_0 5 | sdp_13x4x29_ew_lut_int8 6 | -------------------------------------------------------------------------------- /cl_nvdla/verif/regression/nv_medium_512_random: -------------------------------------------------------------------------------- 1 | cc_feature_data_full_reuse_rtest_0 2 | cc_feature_data_full_reuse_rtest_1 3 | cc_feature_data_full_reuse_rtest_2 4 | cc_feature_data_full_reuse_rtest_3 5 | cc_feature_data_full_reuse_rtest_4 6 | cc_feature_data_full_reuse_rtest_5 7 | cc_feature_data_full_reuse_rtest_6 8 | cc_feature_data_full_reuse_rtest_7 9 | cc_feature_data_full_reuse_rtest_8 10 | cc_feature_data_full_reuse_rtest_9 11 | cc_feature_rtest_0 12 | cc_feature_rtest_1 13 | cc_feature_rtest_2 14 | cc_feature_rtest_3 15 | cc_feature_rtest_4 16 | cc_feature_rtest_5 17 | cc_feature_rtest_6 18 | cc_feature_rtest_7 19 | cc_feature_rtest_8 20 | cc_feature_rtest_9 21 | cc_feature_weight_full_reuse_rtest_0 22 | cc_feature_weight_full_reuse_rtest_1 23 | cc_feature_weight_full_reuse_rtest_2 24 | cc_feature_weight_full_reuse_rtest_3 25 | cc_feature_weight_full_reuse_rtest_4 26 | cc_feature_weight_full_reuse_rtest_5 27 | cc_feature_weight_full_reuse_rtest_6 28 | cc_feature_weight_full_reuse_rtest_7 29 | cc_feature_weight_full_reuse_rtest_8 30 | cc_feature_weight_full_reuse_rtest_9 31 | cc_image_data_full_reuse_rtest_0 32 | cc_image_data_full_reuse_rtest_1 33 | cc_image_data_full_reuse_rtest_2 34 | cc_image_data_full_reuse_rtest_3 35 | cc_image_data_full_reuse_rtest_4 36 | cc_image_data_full_reuse_rtest_5 37 | cc_image_data_full_reuse_rtest_6 38 | cc_image_data_full_reuse_rtest_7 39 | cc_image_data_full_reuse_rtest_8 40 | cc_image_data_full_reuse_rtest_9 41 | cc_pitch_rtest_0 42 | cc_pitch_rtest_1 43 | cc_pitch_rtest_2 44 | cc_pitch_rtest_3 45 | cc_pitch_rtest_4 46 | cc_pitch_rtest_5 47 | cc_pitch_rtest_6 48 | cc_pitch_rtest_7 49 | cc_pitch_rtest_8 50 | cc_pitch_rtest_9 51 | cc_rtest_0 52 | cc_rtest_1 53 | cc_rtest_2 54 | cc_rtest_3 55 | cc_rtest_4 56 | cc_rtest_5 57 | cc_rtest_6 58 | cc_rtest_7 59 | cc_rtest_8 60 | cc_rtest_9 61 | cc_sdp_pdp_rtest_0 62 | cc_sdp_pdp_rtest_1 63 | cc_sdp_pdp_rtest_2 64 | cc_sdp_pdp_rtest_3 65 | cc_sdp_pdp_rtest_4 66 | cc_sdp_pdp_rtest_5 67 | cc_sdp_pdp_rtest_6 68 | cc_sdp_pdp_rtest_7 69 | cc_sdp_pdp_rtest_8 70 | cc_sdp_pdp_rtest_9 71 | cc_sdprdma_sdp_pdp_rtest_0 72 | cc_sdprdma_sdp_pdp_rtest_1 73 | cc_sdprdma_sdp_pdp_rtest_2 74 | cc_sdprdma_sdp_pdp_rtest_3 75 | cc_sdprdma_sdp_pdp_rtest_4 76 | cc_sdprdma_sdp_pdp_rtest_5 77 | cc_sdprdma_sdp_pdp_rtest_6 78 | cc_sdprdma_sdp_pdp_rtest_7 79 | cc_sdprdma_sdp_pdp_rtest_8 80 | cc_sdprdma_sdp_pdp_rtest_9 81 | cc_sdprdma_sdp_rtest_0 82 | cc_sdprdma_sdp_rtest_1 83 | cc_sdprdma_sdp_rtest_2 84 | cc_sdprdma_sdp_rtest_3 85 | cc_sdprdma_sdp_rtest_4 86 | cc_sdprdma_sdp_rtest_5 87 | cc_sdprdma_sdp_rtest_6 88 | cc_sdprdma_sdp_rtest_7 89 | cc_sdprdma_sdp_rtest_8 90 | cc_sdprdma_sdp_rtest_9 91 | cdp_exp_rtest_0 92 | cdp_exp_rtest_1 93 | cdp_exp_rtest_2 94 | cdp_exp_rtest_3 95 | cdp_exp_rtest_4 96 | cdp_exp_rtest_5 97 | cdp_exp_rtest_6 98 | cdp_exp_rtest_7 99 | cdp_exp_rtest_8 100 | cdp_exp_rtest_9 101 | cdp_lin_rtest_0 102 | cdp_lin_rtest_1 103 | cdp_lin_rtest_2 104 | cdp_lin_rtest_3 105 | cdp_lin_rtest_4 106 | cdp_lin_rtest_5 107 | cdp_lin_rtest_6 108 | cdp_lin_rtest_7 109 | cdp_lin_rtest_8 110 | cdp_lin_rtest_9 111 | cdp_rtest_0 112 | cdp_rtest_1 113 | cdp_rtest_2 114 | cdp_rtest_3 115 | cdp_rtest_4 116 | cdp_rtest_5 117 | cdp_rtest_6 118 | cdp_rtest_7 119 | cdp_rtest_8 120 | cdp_rtest_9 121 | multi_scenario_rtest_0 122 | multi_scenario_rtest_1 123 | multi_scenario_rtest_2 124 | multi_scenario_rtest_3 125 | multi_scenario_rtest_4 126 | multi_scenario_rtest_5 127 | multi_scenario_rtest_6 128 | multi_scenario_rtest_7 129 | multi_scenario_rtest_8 130 | multi_scenario_rtest_9 131 | pdp_non_split_rtest_0 132 | pdp_non_split_rtest_1 133 | pdp_non_split_rtest_2 134 | pdp_non_split_rtest_3 135 | pdp_non_split_rtest_4 136 | pdp_non_split_rtest_5 137 | pdp_non_split_rtest_6 138 | pdp_non_split_rtest_7 139 | pdp_non_split_rtest_8 140 | pdp_non_split_rtest_9 141 | pdp_rtest_0 142 | pdp_rtest_1 143 | pdp_rtest_2 144 | pdp_rtest_3 145 | pdp_rtest_4 146 | pdp_rtest_5 147 | pdp_rtest_6 148 | pdp_rtest_7 149 | pdp_rtest_8 150 | pdp_rtest_9 151 | pdp_split_rtest_0 152 | pdp_split_rtest_1 153 | pdp_split_rtest_2 154 | pdp_split_rtest_3 155 | pdp_split_rtest_4 156 | pdp_split_rtest_5 157 | pdp_split_rtest_6 158 | pdp_split_rtest_7 159 | pdp_split_rtest_8 160 | pdp_split_rtest_9 161 | sdp_bn_rtest_0 162 | sdp_bn_rtest_1 163 | sdp_bn_rtest_2 164 | sdp_bn_rtest_3 165 | sdp_bn_rtest_4 166 | sdp_bn_rtest_5 167 | sdp_bn_rtest_6 168 | sdp_bn_rtest_7 169 | sdp_bn_rtest_8 170 | sdp_bn_rtest_9 171 | sdp_bs_rtest_0 172 | sdp_bs_rtest_1 173 | sdp_bs_rtest_2 174 | sdp_bs_rtest_3 175 | sdp_bs_rtest_4 176 | sdp_bs_rtest_5 177 | sdp_bs_rtest_6 178 | sdp_bs_rtest_7 179 | sdp_bs_rtest_8 180 | sdp_bs_rtest_9 181 | sdp_rtest_0 182 | sdp_rtest_1 183 | sdp_rtest_2 184 | sdp_rtest_3 185 | sdp_rtest_4 186 | sdp_rtest_5 187 | sdp_rtest_6 188 | sdp_rtest_7 189 | sdp_rtest_8 190 | sdp_rtest_9 191 | sdprdma_sdp_pdp_rtest_0 192 | sdprdma_sdp_pdp_rtest_1 193 | sdprdma_sdp_pdp_rtest_2 194 | sdprdma_sdp_pdp_rtest_3 195 | sdprdma_sdp_pdp_rtest_4 196 | sdprdma_sdp_pdp_rtest_5 197 | sdprdma_sdp_pdp_rtest_6 198 | sdprdma_sdp_pdp_rtest_7 199 | sdprdma_sdp_pdp_rtest_8 200 | sdprdma_sdp_pdp_rtest_9 201 | -------------------------------------------------------------------------------- /cl_nvdla/verif/regression/nv_medium_512_sanity: -------------------------------------------------------------------------------- 1 | cdp_8x8x64_lrn9_int8_0 2 | dc_8x16x128_3x3x128x32_int8 3 | img_51x96x4_1x10x4x32_R8G8B8A8_int8_0 4 | pdp_8x8x64_2x2_ave_int8_0 5 | -------------------------------------------------------------------------------- /cl_nvdla/verif/regression/nv_small_256_full_sanity: -------------------------------------------------------------------------------- 1 | cdp_1x1x1_lrn3_int8_0 2 | cdp_1x1x31_lrn3_int8_0 3 | cdp_33x17x34_lrn5_int8_0 4 | cdp_8x8x32_lrn3_int8_0 5 | cdp_8x8x32_lrn3_int8_1 6 | cdp_8x8x32_lrn3_int8_2 7 | cdp_8x8x32_lrn5_int8_0 8 | cdp_8x8x32_lrn7_int8_0 9 | cdp_8x8x32_lrn9_int8_0 10 | cdp_8x8x64_lrn3_int8_0 11 | cdp_8x8x64_lrn3_int8_1 12 | cdp_8x8x64_lrn3_int8_10 13 | cdp_8x8x64_lrn3_int8_11 14 | cdp_8x8x64_lrn3_int8_12 15 | cdp_8x8x64_lrn3_int8_2 16 | cdp_8x8x64_lrn3_int8_3 17 | cdp_8x8x64_lrn3_int8_4 18 | cdp_8x8x64_lrn3_int8_5 19 | cdp_8x8x64_lrn3_int8_6 20 | cdp_8x8x64_lrn3_int8_7 21 | cdp_8x8x64_lrn3_int8_8 22 | cdp_8x8x64_lrn3_int8_9 23 | cdp_8x8x64_lrn9_int8 24 | dc_13x15x64_5x3x64x16_int8_0 25 | dc_14x7x49_3x4x49x32_int8_0 26 | dc_1x1x8_1x1x8x1_int8_0 27 | dc_24x33x55_5x5x55x25_int8_0 28 | dc_24x44x14_5x3x14x41_int8_0 29 | dc_32x26x76_6x3x76x16_int8_0 30 | dc_35x22x54_6x8x54x29_int8_0 31 | dc_4x1x8192_1x1x8192x1_int8_0 32 | dc_6x8x192_3x3x192x32_int8_0 33 | dc_8192x1x1_2x3x1x41_int8_0 34 | dc_8x16x128_3x3x128x32_int8 35 | dc_8x8x36_4x4x36x16_dilation_int8_0 36 | img_51x96x4_1x10x4x32_A8B8G8R8_int8_0 37 | img_51x96x4_1x10x4x32_A8R8G8B8_int8_0 38 | img_51x96x4_1x10x4x32_A8Y8U8V8_int8_0 39 | img_51x96x4_1x10x4x32_B8G8R8A8_int8_0 40 | img_51x96x4_1x10x4x32_B8G8R8X8_int8_0 41 | img_51x96x4_1x10x4x32_R8G8B8A8_int8_0 42 | img_51x96x4_1x10x4x32_R8G8B8X8_int8_0 43 | img_51x96x4_1x10x4x32_V8U8Y8A8_int8_0 44 | img_51x96x4_1x10x4x32_X8B8G8R8_int8_0 45 | img_51x96x4_1x10x4x32_X8R8G8B8_int8_0 46 | pdp_12x9x19_8x3_ave_int8_0 47 | pdp_16x6x16_4x2_split_max_int8_0 48 | pdp_1x1x1_3x3_ave_int8_0 49 | pdp_1x3x8_8x8_ave_int8_0 50 | pdp_24x16x1_8x8_ave_int8_0 51 | pdp_28x28x8_2x2_max_int8_0 52 | pdp_5x7x8_4x1_split_max_int8_0 53 | pdp_7x9x10_3x3_int8 54 | pdp_8x8x32_1x1_int8_0 55 | pdp_8x8x32_1x1_int8_1 56 | pdp_8x8x64_2x2_ave_int8_0 57 | pdp_8x8x64_2x2_int8 58 | pdp_8x8x64_2x2_min_int8_0 59 | pdp_8x9x19_3x3_ave_int8_0 60 | pdp_8x9x19_3x3_ave_int8_1 61 | sdp_13x4x29_ew_lut_int8 62 | sdp_1x1x1_pass_through_int8 63 | sdp_1x1x8_pass_through_int8_0 64 | sdp_1x8192x1_pass_through_int8_0 65 | sdp_23x13x42_bs_int8_mem_0 66 | sdp_3x3x32_ew_lo_lin_int8 67 | sdp_3x3x33_bn_int8_mem_0 68 | sdp_3x3x33_bn_int8_reg_0 69 | sdp_3x3x33_bn_int8_reg_1 70 | sdp_3x3x33_bn_int8_reg_2 71 | sdp_3x3x33_bn_int8_reg_3 72 | sdp_3x3x33_bs_bn_int8_0 73 | sdp_3x3x33_bs_bn_int8_1 74 | sdp_3x3x33_bs_int8_reg_0 75 | sdp_3x3x33_bs_int8_reg_1 76 | sdp_3x3x33_ew_int8_reg_0 77 | sdp_3x3x33_ew_le_exp_int8 78 | sdp_3x3x33_ew_le_lin_int8 79 | sdp_4x1x8192_pass_through_int8_0 80 | sdp_4x22x42_bypass_int8 81 | sdp_5x24x18_bs_int8_mem_0 82 | sdp_8192x1x1_pass_through_int8_0 83 | sdp_8x8x32_bypass_int8_0 84 | sdp_8x8x32_bypass_int8_1 85 | sdp_pdp_32x16x32_pass_through_int8_0 86 | -------------------------------------------------------------------------------- /cl_nvdla/verif/regression/nv_small_256_random: -------------------------------------------------------------------------------- 1 | cc_feature_data_full_reuse_rtest_0 2 | cc_feature_data_full_reuse_rtest_1 3 | cc_feature_data_full_reuse_rtest_2 4 | cc_feature_data_full_reuse_rtest_3 5 | cc_feature_data_full_reuse_rtest_4 6 | cc_feature_data_full_reuse_rtest_5 7 | cc_feature_data_full_reuse_rtest_6 8 | cc_feature_data_full_reuse_rtest_7 9 | cc_feature_data_full_reuse_rtest_8 10 | cc_feature_data_full_reuse_rtest_9 11 | cc_feature_rtest_0 12 | cc_feature_rtest_1 13 | cc_feature_rtest_2 14 | cc_feature_rtest_3 15 | cc_feature_rtest_4 16 | cc_feature_rtest_5 17 | cc_feature_rtest_6 18 | cc_feature_rtest_7 19 | cc_feature_rtest_8 20 | cc_feature_rtest_9 21 | cc_feature_weight_full_reuse_rtest_0 22 | cc_feature_weight_full_reuse_rtest_1 23 | cc_feature_weight_full_reuse_rtest_2 24 | cc_feature_weight_full_reuse_rtest_3 25 | cc_feature_weight_full_reuse_rtest_4 26 | cc_feature_weight_full_reuse_rtest_5 27 | cc_feature_weight_full_reuse_rtest_6 28 | cc_feature_weight_full_reuse_rtest_7 29 | cc_feature_weight_full_reuse_rtest_8 30 | cc_feature_weight_full_reuse_rtest_9 31 | cc_image_data_full_reuse_rtest_0 32 | cc_image_data_full_reuse_rtest_1 33 | cc_image_data_full_reuse_rtest_2 34 | cc_image_data_full_reuse_rtest_3 35 | cc_image_data_full_reuse_rtest_4 36 | cc_image_data_full_reuse_rtest_5 37 | cc_image_data_full_reuse_rtest_6 38 | cc_image_data_full_reuse_rtest_7 39 | cc_image_data_full_reuse_rtest_8 40 | cc_image_data_full_reuse_rtest_9 41 | cc_pitch_rtest_0 42 | cc_pitch_rtest_1 43 | cc_pitch_rtest_2 44 | cc_pitch_rtest_3 45 | cc_pitch_rtest_4 46 | cc_pitch_rtest_5 47 | cc_pitch_rtest_6 48 | cc_pitch_rtest_7 49 | cc_pitch_rtest_8 50 | cc_pitch_rtest_9 51 | cc_rtest_0 52 | cc_rtest_1 53 | cc_rtest_2 54 | cc_rtest_3 55 | cc_rtest_4 56 | cc_rtest_5 57 | cc_rtest_6 58 | cc_rtest_7 59 | cc_rtest_8 60 | cc_rtest_9 61 | cc_sdp_pdp_rtest_0 62 | cc_sdp_pdp_rtest_1 63 | cc_sdp_pdp_rtest_2 64 | cc_sdp_pdp_rtest_3 65 | cc_sdp_pdp_rtest_4 66 | cc_sdp_pdp_rtest_5 67 | cc_sdp_pdp_rtest_6 68 | cc_sdp_pdp_rtest_7 69 | cc_sdp_pdp_rtest_8 70 | cc_sdp_pdp_rtest_9 71 | cc_sdprdma_sdp_pdp_rtest_0 72 | cc_sdprdma_sdp_pdp_rtest_1 73 | cc_sdprdma_sdp_pdp_rtest_2 74 | cc_sdprdma_sdp_pdp_rtest_3 75 | cc_sdprdma_sdp_pdp_rtest_4 76 | cc_sdprdma_sdp_pdp_rtest_5 77 | cc_sdprdma_sdp_pdp_rtest_6 78 | cc_sdprdma_sdp_pdp_rtest_7 79 | cc_sdprdma_sdp_pdp_rtest_8 80 | cc_sdprdma_sdp_pdp_rtest_9 81 | cc_sdprdma_sdp_rtest_0 82 | cc_sdprdma_sdp_rtest_1 83 | cc_sdprdma_sdp_rtest_2 84 | cc_sdprdma_sdp_rtest_3 85 | cc_sdprdma_sdp_rtest_4 86 | cc_sdprdma_sdp_rtest_5 87 | cc_sdprdma_sdp_rtest_6 88 | cc_sdprdma_sdp_rtest_7 89 | cc_sdprdma_sdp_rtest_8 90 | cc_sdprdma_sdp_rtest_9 91 | cdp_exp_rtest_0 92 | cdp_exp_rtest_1 93 | cdp_exp_rtest_2 94 | cdp_exp_rtest_3 95 | cdp_exp_rtest_4 96 | cdp_exp_rtest_5 97 | cdp_exp_rtest_6 98 | cdp_exp_rtest_7 99 | cdp_exp_rtest_8 100 | cdp_exp_rtest_9 101 | cdp_lin_rtest_0 102 | cdp_lin_rtest_1 103 | cdp_lin_rtest_2 104 | cdp_lin_rtest_3 105 | cdp_lin_rtest_4 106 | cdp_lin_rtest_5 107 | cdp_lin_rtest_6 108 | cdp_lin_rtest_7 109 | cdp_lin_rtest_8 110 | cdp_lin_rtest_9 111 | cdp_rtest_0 112 | cdp_rtest_1 113 | cdp_rtest_2 114 | cdp_rtest_3 115 | cdp_rtest_4 116 | cdp_rtest_5 117 | cdp_rtest_6 118 | cdp_rtest_7 119 | cdp_rtest_8 120 | cdp_rtest_9 121 | multi_scenario_rtest_0 122 | multi_scenario_rtest_1 123 | multi_scenario_rtest_2 124 | multi_scenario_rtest_3 125 | multi_scenario_rtest_4 126 | multi_scenario_rtest_5 127 | multi_scenario_rtest_6 128 | multi_scenario_rtest_7 129 | multi_scenario_rtest_8 130 | multi_scenario_rtest_9 131 | pdp_non_split_rtest_0 132 | pdp_non_split_rtest_1 133 | pdp_non_split_rtest_2 134 | pdp_non_split_rtest_3 135 | pdp_non_split_rtest_4 136 | pdp_non_split_rtest_5 137 | pdp_non_split_rtest_6 138 | pdp_non_split_rtest_7 139 | pdp_non_split_rtest_8 140 | pdp_non_split_rtest_9 141 | pdp_rtest_0 142 | pdp_rtest_1 143 | pdp_rtest_2 144 | pdp_rtest_3 145 | pdp_rtest_4 146 | pdp_rtest_5 147 | pdp_rtest_6 148 | pdp_rtest_7 149 | pdp_rtest_8 150 | pdp_rtest_9 151 | pdp_split_rtest_0 152 | pdp_split_rtest_1 153 | pdp_split_rtest_2 154 | pdp_split_rtest_3 155 | pdp_split_rtest_4 156 | pdp_split_rtest_5 157 | pdp_split_rtest_6 158 | pdp_split_rtest_7 159 | pdp_split_rtest_8 160 | pdp_split_rtest_9 161 | sdp_bn_rtest_0 162 | sdp_bn_rtest_1 163 | sdp_bn_rtest_2 164 | sdp_bn_rtest_3 165 | sdp_bn_rtest_4 166 | sdp_bn_rtest_5 167 | sdp_bn_rtest_6 168 | sdp_bn_rtest_7 169 | sdp_bn_rtest_8 170 | sdp_bn_rtest_9 171 | sdp_bs_rtest_0 172 | sdp_bs_rtest_1 173 | sdp_bs_rtest_2 174 | sdp_bs_rtest_3 175 | sdp_bs_rtest_4 176 | sdp_bs_rtest_5 177 | sdp_bs_rtest_6 178 | sdp_bs_rtest_7 179 | sdp_bs_rtest_8 180 | sdp_bs_rtest_9 181 | sdp_rtest_0 182 | sdp_rtest_1 183 | sdp_rtest_2 184 | sdp_rtest_3 185 | sdp_rtest_4 186 | sdp_rtest_5 187 | sdp_rtest_6 188 | sdp_rtest_7 189 | sdp_rtest_8 190 | sdp_rtest_9 191 | sdprdma_sdp_pdp_rtest_0 192 | sdprdma_sdp_pdp_rtest_1 193 | sdprdma_sdp_pdp_rtest_2 194 | sdprdma_sdp_pdp_rtest_3 195 | sdprdma_sdp_pdp_rtest_4 196 | sdprdma_sdp_pdp_rtest_5 197 | sdprdma_sdp_pdp_rtest_6 198 | sdprdma_sdp_pdp_rtest_7 199 | sdprdma_sdp_pdp_rtest_8 200 | sdprdma_sdp_pdp_rtest_9 201 | -------------------------------------------------------------------------------- /cl_nvdla/verif/regression/nv_small_256_sanity: -------------------------------------------------------------------------------- 1 | cdp_1x1x1_lrn3_int8_0 2 | cdp_1x1x31_lrn3_int8_0 3 | cdp_33x17x34_lrn5_int8_0 4 | cdp_8x8x32_lrn3_int8_0 5 | cdp_8x8x32_lrn3_int8_1 6 | cdp_8x8x32_lrn3_int8_2 7 | cdp_8x8x32_lrn5_int8_0 8 | cdp_8x8x32_lrn7_int8_0 9 | cdp_8x8x32_lrn9_int8_0 10 | cdp_8x8x64_lrn3_int8_0 11 | cdp_8x8x64_lrn3_int8_1 12 | cdp_8x8x64_lrn3_int8_10 13 | cdp_8x8x64_lrn3_int8_11 14 | cdp_8x8x64_lrn3_int8_12 15 | cdp_8x8x64_lrn3_int8_2 16 | cdp_8x8x64_lrn3_int8_3 17 | cdp_8x8x64_lrn3_int8_4 18 | cdp_8x8x64_lrn3_int8_5 19 | cdp_8x8x64_lrn3_int8_6 20 | cdp_8x8x64_lrn3_int8_7 21 | cdp_8x8x64_lrn3_int8_8 22 | cdp_8x8x64_lrn3_int8_9 23 | cdp_8x8x64_lrn9_int8 24 | dc_13x15x64_5x3x64x16_int8_0 25 | dc_14x7x49_3x4x49x32_int8_0 26 | dc_1x1x8_1x1x8x1_int8_0 27 | dc_24x33x55_5x5x55x25_int8_0 28 | dc_24x44x14_5x3x14x41_int8_0 29 | dc_32x26x76_6x3x76x16_int8_0 30 | dc_35x22x54_6x8x54x29_int8_0 31 | dc_4x1x8192_1x1x8192x1_int8_0 32 | dc_6x8x192_3x3x192x32_int8_0 33 | dc_8192x1x1_2x3x1x41_int8_0 34 | dc_8x16x128_3x3x128x32_int8 35 | dc_8x8x36_4x4x36x16_dilation_int8_0 36 | img_51x96x4_1x10x4x32_A8B8G8R8_int8_0 37 | img_51x96x4_1x10x4x32_A8R8G8B8_int8_0 38 | img_51x96x4_1x10x4x32_A8Y8U8V8_int8_0 39 | img_51x96x4_1x10x4x32_B8G8R8A8_int8_0 40 | img_51x96x4_1x10x4x32_B8G8R8X8_int8_0 41 | img_51x96x4_1x10x4x32_R8G8B8A8_int8_0 42 | img_51x96x4_1x10x4x32_R8G8B8X8_int8_0 43 | img_51x96x4_1x10x4x32_V8U8Y8A8_int8_0 44 | img_51x96x4_1x10x4x32_X8B8G8R8_int8_0 45 | img_51x96x4_1x10x4x32_X8R8G8B8_int8_0 46 | pdp_12x9x19_8x3_ave_int8_0 47 | pdp_16x6x16_4x2_split_max_int8_0 48 | pdp_1x1x1_3x3_ave_int8_0 49 | pdp_1x3x8_8x8_ave_int8_0 50 | pdp_24x16x1_8x8_ave_int8_0 51 | pdp_28x28x8_2x2_max_int8_0 52 | pdp_5x7x8_4x1_split_max_int8_0 53 | pdp_7x9x10_3x3_int8 54 | pdp_8x8x32_1x1_int8_0 55 | pdp_8x8x32_1x1_int8_1 56 | pdp_8x8x64_2x2_ave_int8_0 57 | pdp_8x8x64_2x2_int8 58 | pdp_8x8x64_2x2_min_int8_0 59 | pdp_8x9x19_3x3_ave_int8_0 60 | pdp_8x9x19_3x3_ave_int8_1 61 | sdp_1x1x1_pass_through_int8 62 | sdp_1x1x8_pass_through_int8_0 63 | sdp_1x8192x1_pass_through_int8_0 64 | sdp_23x13x42_bs_int8_mem_0 65 | sdp_3x3x32_ew_lo_lin_int8 66 | sdp_3x3x33_bn_int8_mem_0 67 | sdp_3x3x33_bn_int8_reg_0 68 | sdp_3x3x33_bn_int8_reg_1 69 | sdp_3x3x33_bn_int8_reg_2 70 | sdp_3x3x33_bn_int8_reg_3 71 | sdp_3x3x33_bs_bn_int8_0 72 | sdp_3x3x33_bs_bn_int8_1 73 | sdp_3x3x33_bs_int8_reg_0 74 | sdp_3x3x33_bs_int8_reg_1 75 | sdp_3x3x33_ew_int8_reg_0 76 | sdp_3x3x33_ew_le_exp_int8 77 | sdp_3x3x33_ew_le_lin_int8 78 | sdp_4x1x8192_pass_through_int8_0 79 | sdp_4x22x42_bypass_int8 80 | sdp_5x24x18_bs_int8_mem_0 81 | sdp_8192x1x1_pass_through_int8_0 82 | sdp_8x8x32_bypass_int8_0 83 | sdp_8x8x32_bypass_int8_1 84 | sdp_pdp_32x16x32_pass_through_int8_0 85 | -------------------------------------------------------------------------------- /cl_nvdla/verif/regression/nv_small_random: -------------------------------------------------------------------------------- 1 | cc_feature_data_full_reuse_rtest_0 2 | cc_feature_data_full_reuse_rtest_1 3 | cc_feature_data_full_reuse_rtest_2 4 | cc_feature_data_full_reuse_rtest_3 5 | cc_feature_data_full_reuse_rtest_4 6 | cc_feature_data_full_reuse_rtest_5 7 | cc_feature_data_full_reuse_rtest_6 8 | cc_feature_data_full_reuse_rtest_7 9 | cc_feature_data_full_reuse_rtest_8 10 | cc_feature_data_full_reuse_rtest_9 11 | cc_feature_rtest_0 12 | cc_feature_rtest_1 13 | cc_feature_rtest_2 14 | cc_feature_rtest_3 15 | cc_feature_rtest_4 16 | cc_feature_rtest_5 17 | cc_feature_rtest_6 18 | cc_feature_rtest_7 19 | cc_feature_rtest_8 20 | cc_feature_rtest_9 21 | cc_feature_weight_full_reuse_rtest_0 22 | cc_feature_weight_full_reuse_rtest_1 23 | cc_feature_weight_full_reuse_rtest_2 24 | cc_feature_weight_full_reuse_rtest_3 25 | cc_feature_weight_full_reuse_rtest_4 26 | cc_feature_weight_full_reuse_rtest_5 27 | cc_feature_weight_full_reuse_rtest_6 28 | cc_feature_weight_full_reuse_rtest_7 29 | cc_feature_weight_full_reuse_rtest_8 30 | cc_feature_weight_full_reuse_rtest_9 31 | cc_image_data_full_reuse_rtest_0 32 | cc_image_data_full_reuse_rtest_1 33 | cc_image_data_full_reuse_rtest_2 34 | cc_image_data_full_reuse_rtest_3 35 | cc_image_data_full_reuse_rtest_4 36 | cc_image_data_full_reuse_rtest_5 37 | cc_image_data_full_reuse_rtest_6 38 | cc_image_data_full_reuse_rtest_7 39 | cc_image_data_full_reuse_rtest_8 40 | cc_image_data_full_reuse_rtest_9 41 | cc_pitch_rtest_0 42 | cc_pitch_rtest_1 43 | cc_pitch_rtest_2 44 | cc_pitch_rtest_3 45 | cc_pitch_rtest_4 46 | cc_pitch_rtest_5 47 | cc_pitch_rtest_6 48 | cc_pitch_rtest_7 49 | cc_pitch_rtest_8 50 | cc_pitch_rtest_9 51 | cc_rtest_0 52 | cc_rtest_1 53 | cc_rtest_2 54 | cc_rtest_3 55 | cc_rtest_4 56 | cc_rtest_5 57 | cc_rtest_6 58 | cc_rtest_7 59 | cc_rtest_8 60 | cc_rtest_9 61 | cc_sdp_pdp_rtest_0 62 | cc_sdp_pdp_rtest_1 63 | cc_sdp_pdp_rtest_2 64 | cc_sdp_pdp_rtest_3 65 | cc_sdp_pdp_rtest_4 66 | cc_sdp_pdp_rtest_5 67 | cc_sdp_pdp_rtest_6 68 | cc_sdp_pdp_rtest_7 69 | cc_sdp_pdp_rtest_8 70 | cc_sdp_pdp_rtest_9 71 | cc_sdprdma_sdp_pdp_rtest_0 72 | cc_sdprdma_sdp_pdp_rtest_1 73 | cc_sdprdma_sdp_pdp_rtest_2 74 | cc_sdprdma_sdp_pdp_rtest_3 75 | cc_sdprdma_sdp_pdp_rtest_4 76 | cc_sdprdma_sdp_pdp_rtest_5 77 | cc_sdprdma_sdp_pdp_rtest_6 78 | cc_sdprdma_sdp_pdp_rtest_7 79 | cc_sdprdma_sdp_pdp_rtest_8 80 | cc_sdprdma_sdp_pdp_rtest_9 81 | cc_sdprdma_sdp_rtest_0 82 | cc_sdprdma_sdp_rtest_1 83 | cc_sdprdma_sdp_rtest_2 84 | cc_sdprdma_sdp_rtest_3 85 | cc_sdprdma_sdp_rtest_4 86 | cc_sdprdma_sdp_rtest_5 87 | cc_sdprdma_sdp_rtest_6 88 | cc_sdprdma_sdp_rtest_7 89 | cc_sdprdma_sdp_rtest_8 90 | cc_sdprdma_sdp_rtest_9 91 | cdp_exp_rtest_0 92 | cdp_exp_rtest_1 93 | cdp_exp_rtest_2 94 | cdp_exp_rtest_3 95 | cdp_exp_rtest_4 96 | cdp_exp_rtest_5 97 | cdp_exp_rtest_6 98 | cdp_exp_rtest_7 99 | cdp_exp_rtest_8 100 | cdp_exp_rtest_9 101 | cdp_lin_rtest_0 102 | cdp_lin_rtest_1 103 | cdp_lin_rtest_2 104 | cdp_lin_rtest_3 105 | cdp_lin_rtest_4 106 | cdp_lin_rtest_5 107 | cdp_lin_rtest_6 108 | cdp_lin_rtest_7 109 | cdp_lin_rtest_8 110 | cdp_lin_rtest_9 111 | cdp_rtest_0 112 | cdp_rtest_1 113 | cdp_rtest_2 114 | cdp_rtest_3 115 | cdp_rtest_4 116 | cdp_rtest_5 117 | cdp_rtest_6 118 | cdp_rtest_7 119 | cdp_rtest_8 120 | cdp_rtest_9 121 | multi_scenario_rtest_0 122 | multi_scenario_rtest_1 123 | multi_scenario_rtest_2 124 | multi_scenario_rtest_3 125 | multi_scenario_rtest_4 126 | multi_scenario_rtest_5 127 | multi_scenario_rtest_6 128 | multi_scenario_rtest_7 129 | multi_scenario_rtest_8 130 | multi_scenario_rtest_9 131 | pdp_non_split_rtest_0 132 | pdp_non_split_rtest_1 133 | pdp_non_split_rtest_2 134 | pdp_non_split_rtest_3 135 | pdp_non_split_rtest_4 136 | pdp_non_split_rtest_5 137 | pdp_non_split_rtest_6 138 | pdp_non_split_rtest_7 139 | pdp_non_split_rtest_8 140 | pdp_non_split_rtest_9 141 | pdp_rtest_0 142 | pdp_rtest_1 143 | pdp_rtest_2 144 | pdp_rtest_3 145 | pdp_rtest_4 146 | pdp_rtest_5 147 | pdp_rtest_6 148 | pdp_rtest_7 149 | pdp_rtest_8 150 | pdp_rtest_9 151 | pdp_split_rtest_0 152 | pdp_split_rtest_1 153 | pdp_split_rtest_2 154 | pdp_split_rtest_3 155 | pdp_split_rtest_4 156 | pdp_split_rtest_5 157 | pdp_split_rtest_6 158 | pdp_split_rtest_7 159 | pdp_split_rtest_8 160 | pdp_split_rtest_9 161 | sdp_bn_rtest_0 162 | sdp_bn_rtest_1 163 | sdp_bn_rtest_2 164 | sdp_bn_rtest_3 165 | sdp_bn_rtest_4 166 | sdp_bn_rtest_5 167 | sdp_bn_rtest_6 168 | sdp_bn_rtest_7 169 | sdp_bn_rtest_8 170 | sdp_bn_rtest_9 171 | sdp_bs_rtest_0 172 | sdp_bs_rtest_1 173 | sdp_bs_rtest_2 174 | sdp_bs_rtest_3 175 | sdp_bs_rtest_4 176 | sdp_bs_rtest_5 177 | sdp_bs_rtest_6 178 | sdp_bs_rtest_7 179 | sdp_bs_rtest_8 180 | sdp_bs_rtest_9 181 | sdp_rtest_0 182 | sdp_rtest_1 183 | sdp_rtest_2 184 | sdp_rtest_3 185 | sdp_rtest_4 186 | sdp_rtest_5 187 | sdp_rtest_6 188 | sdp_rtest_7 189 | sdp_rtest_8 190 | sdp_rtest_9 191 | sdprdma_sdp_pdp_rtest_0 192 | sdprdma_sdp_pdp_rtest_1 193 | sdprdma_sdp_pdp_rtest_2 194 | sdprdma_sdp_pdp_rtest_3 195 | sdprdma_sdp_pdp_rtest_4 196 | sdprdma_sdp_pdp_rtest_5 197 | sdprdma_sdp_pdp_rtest_6 198 | sdprdma_sdp_pdp_rtest_7 199 | sdprdma_sdp_pdp_rtest_8 200 | sdprdma_sdp_pdp_rtest_9 201 | -------------------------------------------------------------------------------- /cl_nvdla/verif/regression/nv_small_sanity: -------------------------------------------------------------------------------- 1 | cdp_1x1x1_lrn3_int8_0 2 | cdp_1x1x31_lrn3_int8_0 3 | cdp_33x17x34_lrn5_int8_0 4 | cdp_8x8x32_lrn3_int8_0 5 | cdp_8x8x32_lrn3_int8_1 6 | cdp_8x8x32_lrn3_int8_2 7 | cdp_8x8x32_lrn5_int8_0 8 | cdp_8x8x32_lrn7_int8_0 9 | cdp_8x8x32_lrn9_int8_0 10 | cdp_8x8x64_lrn3_int8_0 11 | cdp_8x8x64_lrn3_int8_1 12 | cdp_8x8x64_lrn3_int8_10 13 | cdp_8x8x64_lrn3_int8_11 14 | cdp_8x8x64_lrn3_int8_12 15 | cdp_8x8x64_lrn3_int8_2 16 | cdp_8x8x64_lrn3_int8_3 17 | cdp_8x8x64_lrn3_int8_4 18 | cdp_8x8x64_lrn3_int8_5 19 | cdp_8x8x64_lrn3_int8_6 20 | cdp_8x8x64_lrn3_int8_7 21 | cdp_8x8x64_lrn3_int8_8 22 | cdp_8x8x64_lrn3_int8_9 23 | cdp_8x8x64_lrn9_int8 24 | dc_13x15x64_5x3x64x16_int8_0 25 | dc_14x7x49_3x4x49x32_int8_0 26 | dc_1x1x8_1x1x8x1_int8_0 27 | dc_24x33x55_5x5x55x25_int8_0 28 | dc_24x44x14_5x3x14x41_int8_0 29 | dc_32x26x76_6x3x76x16_int8_0 30 | dc_32x26x76_6x3x76x270_int8_0 31 | dc_35x22x54_6x8x54x29_int8_0 32 | dc_4x1x8192_1x1x8192x1_int8_0 33 | dc_6x8x192_3x3x192x32_int8_0 34 | dc_8192x1x1_2x3x1x41_int8_0 35 | dc_8x16x128_3x3x128x32_int8 36 | dc_8x8x36_4x4x36x16_dilation_int8_0 37 | img_51x96x4_1x10x4x32_A8B8G8R8_int8_0 38 | img_51x96x4_1x10x4x32_A8R8G8B8_int8_0 39 | img_51x96x4_1x10x4x32_A8Y8U8V8_int8_0 40 | img_51x96x4_1x10x4x32_B8G8R8A8_int8_0 41 | img_51x96x4_1x10x4x32_B8G8R8X8_int8_0 42 | img_51x96x4_1x10x4x32_R8G8B8A8_int8_0 43 | img_51x96x4_1x10x4x32_R8G8B8X8_int8_0 44 | img_51x96x4_1x10x4x32_V8U8Y8A8_int8_0 45 | img_51x96x4_1x10x4x32_X8B8G8R8_int8_0 46 | img_51x96x4_1x10x4x32_X8R8G8B8_int8_0 47 | pdp_12x9x19_8x3_ave_int8_0 48 | pdp_16x6x16_4x2_split_max_int8_0 49 | pdp_1x1x1_3x3_ave_int8_0 50 | pdp_1x3x8_8x8_ave_int8_0 51 | pdp_24x16x1_8x8_ave_int8_0 52 | pdp_28x28x8_2x2_max_int8_0 53 | pdp_5x7x8_4x1_split_max_int8_0 54 | pdp_7x9x10_3x3_int8 55 | pdp_8x8x32_1x1_int8_0 56 | pdp_8x8x32_1x1_int8_1 57 | pdp_8x8x64_2x2_ave_int8_0 58 | pdp_8x8x64_2x2_int8 59 | pdp_8x8x64_2x2_min_int8_0 60 | pdp_8x9x19_3x3_ave_int8_0 61 | pdp_8x9x19_3x3_ave_int8_1 62 | sdp_1x1x1_pass_through_int8 63 | sdp_1x1x8_pass_through_int8_0 64 | sdp_1x8192x1_pass_through_int8_0 65 | sdp_23x13x42_bs_int8_mem_0 66 | sdp_3x3x33_bn_int8_mem_0 67 | sdp_3x3x33_bn_int8_reg_0 68 | sdp_3x3x33_bn_int8_reg_1 69 | sdp_3x3x33_bn_int8_reg_2 70 | sdp_3x3x33_bn_int8_reg_3 71 | sdp_3x3x33_bs_bn_int8_0 72 | sdp_3x3x33_bs_bn_int8_1 73 | sdp_3x3x33_bs_int8_reg_0 74 | sdp_3x3x33_bs_int8_reg_1 75 | sdp_4x1x8192_pass_through_int8_0 76 | sdp_4x22x42_bypass_int8 77 | sdp_5x24x18_bs_int8_mem_0 78 | sdp_8192x1x1_pass_through_int8_0 79 | sdp_8x8x32_bypass_int8_0 80 | sdp_8x8x32_bypass_int8_1 81 | sdp_pdp_32x16x32_pass_through_int8_0 -------------------------------------------------------------------------------- /cl_nvdla/verif/scripts/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | # NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | .PHONY: default 20 | default: all 21 | 22 | export TRACE_TEST ?= 0 23 | 24 | ifeq ($(TRACE_TEST),1) 25 | export TEST ?= trace_test 26 | export C_TEST ?= trace_test 27 | export NVDLA_ENABLE_SIM_MEM ?= "+enable_sim_mem" 28 | else 29 | export TEST ?= test_null 30 | export C_TEST ?= test_null 31 | endif 32 | 33 | export CL_ROOT ?= $(PWD)/../.. 34 | 35 | export CL_COMMON_ROOT = $(CL_ROOT)/../common 36 | 37 | export VP_ROOT = $(PWD)/../../../../.. 38 | 39 | export C_INC_DIR = -I${CL_COMMON_ROOT}/software/include 40 | export C_SRC_DIR = $(CL_ROOT)/software/src 41 | 42 | export TEST_NAME = $(CL_ROOT)/verif/tests/$(TEST).sv 43 | ifeq ($(TRACE_TEST),1) 44 | export C_TEST_NAME = $(CL_ROOT)/software/src/$(C_TEST).c $(CL_ROOT)/software/src/trace_test_impl.c $(CL_COMMON_ROOT)/software/src/cl_common_utils.c $(CL_COMMON_ROOT)/software/src/sh_dpi_tasks.c 45 | else 46 | ifeq ($(COSIM), 1) 47 | export C_TEST_NAME = $(CL_ROOT)/software/src/$(C_TEST).c 48 | else 49 | export C_TEST_NAME = $(CL_ROOT)/software/src/$(C_TEST).c $(CL_COMMON_ROOT)/software/src/cl_common_utils.c $(CL_COMMON_ROOT)/software/src/sh_dpi_tasks.c 50 | endif 51 | endif 52 | 53 | export SIM_ROOT = $(CL_ROOT)/verif/sim 54 | 55 | export NVDLA_TRACE ?= $(CL_ROOT)/software/test_bdma/test_bdma.cfg 56 | 57 | ifeq ($(C_TEST),test_null) 58 | export SIM_DIR = $(SIM_ROOT)/$(TEST) 59 | export RUN_DIR = $(SIM_ROOT)/$(TEST) 60 | else 61 | ifeq ($(C_TEST),trace_test) 62 | export SIM_DIR = $(SIM_ROOT)/$(C_TEST) 63 | export RUN_DIR ?= $(SIM_ROOT)/$(notdir $(NVDLA_TRACE)) 64 | else 65 | export SIM_DIR = $(SIM_ROOT)/$(C_TEST) 66 | export RUN_DIR = $(SIM_ROOT)/$(C_TEST) 67 | endif 68 | endif 69 | 70 | export SCRIPTS_DIR = $(CL_ROOT)/verif/scripts 71 | export XILINX_IP = $(HDK_SHELL_DESIGN_DIR)/ip 72 | export SH_LIB_DIR = $(HDK_SHELL_DESIGN_DIR)/lib 73 | export SH_INF_DIR = $(HDK_SHELL_DESIGN_DIR)/interfaces 74 | 75 | export NVDLA_HW_ROOT ?= $(VP_ROOT)/../hw 76 | export NVDLA_HW_PROJECT ?= nv_small 77 | 78 | ifneq ($(NVDLA_HW_PROJECT),nv_small) 79 | export NVDLA_HW_DEFINES ?= +define+NVDLA_CVSRAM_PRESENT 80 | endif 81 | 82 | export NVDLA_REGISTER_HEADER_DIR ?= $(NVDLA_HW_ROOT)/outdir/$(NVDLA_HW_PROJECT)/spec/manual 83 | 84 | SV_TEST_LIST = 85 | C_TEST_LIST = trace_test.c test_null.c 86 | 87 | ifeq ($(TRACE_TEST),1) 88 | export NVDLA_TRACE_PLAYER_CFLAGS ?= "-g -DDEBUG" 89 | export NVDLA_TRACE_PLAYER_ROOT ?= $(CL_COMMON_ROOT)/trace_player 90 | 91 | include $(NVDLA_TRACE_PLAYER_ROOT)/Makefile.inc 92 | endif 93 | 94 | export SIM_BACKDOOR_MEM ?= 1 95 | ifeq ($(SIM_BACKDOOR_MEM),1) 96 | export NVDLA_HW_DEFINES += +define+SIM_BACKDOOR_MEM 97 | endif 98 | 99 | all: make_sim_dir compile run 100 | 101 | include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.common.inc 102 | -------------------------------------------------------------------------------- /cl_nvdla/verif/scripts/Makefile.vcs: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | # NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | 20 | ################################################################## 21 | ## Makefile For VCS compiles and simulations 22 | ## Step to run : 23 | ## 1. make create_libs VCS=1 -> To generate xilinx compile 24 | ## libraries. This is a one time step 25 | ## 2. make all VCS=1 -> Runs the test 26 | ################################################################## 27 | 28 | ifeq ($(COSIM), 1) 29 | export DPI_FUNCTIONS = set_apb_rd set_apb_wr set_irq_rd set_irq_wr set_ram_rd set_ram_wr set_ev_trigger sv_int_ack sv_printf apb_read_ack ram_read_ack irq_read_ack 30 | compile: $(COMPLIB_DIR) 31 | mkdir -p $(SIM_DIR) 32 | cd ${SIM_DIR} && rm -rf csrc AN.DB simv* *.log DEFAULT.DB DVEfiles/ *.vpd && syscan -export_DPI $(DPI_FUNCTIONS) && syscan -full64 -sysc=230 -CFLAGS "-I$(C_INC_DIR) -I$(CL_COMMON_ROOT)/software/include -std=c++11 -DSV_TEST" $(CL_COMMON_ROOT)/software/src/cosim_top.cpp:cosim_top -l compile.sysc.log 33 | cd ${SIM_DIR} && ln -s -f ../vcs/vcs_complib/synopsys_sim.setup 34 | cd ${SIM_DIR} && rm -rf csrc AN.DB simv* *.log DEFAULT.DB DVEfiles/ *.vpd && syscan -export_DPI $(DPI_FUNCTIONS) && syscan -full64 -sysc=230 -CFLAGS "-I$(C_INC_DIR) -I$(CL_COMMON_ROOT)/software/include -std=c++11 -DSV_TEST" $(CL_COMMON_ROOT)/software/src/cosim_top.cpp:cosim_top -l compile.sysc.log 35 | cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS +define+COSIM_TOP $(DEFINES) $(NVDLA_HW_DEFINES) +lint=TFIPC-L 36 | cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR) -I$(CL_COMMON_ROOT)/software/include -I$(NVDLA_REGISTER_HEADER_DIR) -I$(SIM_DIR) -DSV_TEST -DDEBUG -DCONFIG_LOGLEVEL=4 -std=c++11" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -sysc=230 -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log 37 | else 38 | compile: $(COMPLIB_DIR) 39 | mkdir -p $(SIM_DIR) 40 | cd ${SIM_DIR} && ln -s -f ../vcs/vcs_complib/synopsys_sim.setup 41 | cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -kdb -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFINES) $(NVDLA_HW_DEFINES) +lint=TFIPC-L 42 | ifeq ($(TRACE_TEST), 1) 43 | cd $(NVDLA_TRACE_PLAYER_ROOT)/build && make NVDLA_TRACE_PLAYER_CFLAGS=$(NVDLA_TRACE_PLAYER_CFLAGS) 44 | cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR) -I$(CL_COMMON_ROOT)/software/include -I$(NVDLA_REGISTER_HEADER_DIR) -I$(NVDLA_TRACE_PLAYER_INCLUDES) -I$(SIM_DIR) -DSV_TEST -DDEBUG -DCONFIG_LOGLEVEL=4" -LDFLAGS "-Wl,-rpath=$(NVDLA_TRACE_PLAYER_LIB_DIR) -L$(NVDLA_TRACE_PLAYER_LIB_DIR) -l$(NVDLA_TRACE_PLAYER_LIB)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -kdb -lca -v2005 -l compile.vcs.log 45 | else 46 | cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR) -I$(CL_COMMON_ROOT)/software/include -I$(NVDLA_REGISTER_HEADER_DIR) -I$(SIM_DIR) -DSV_TEST -DDEBUG -DCONFIG_LOGLEVEL=4" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log 47 | endif 48 | endif 49 | 50 | run: 51 | mkdir -p $(RUN_DIR) 52 | ifeq ($(TRACE_TEST), 1) 53 | cd $(RUN_DIR) && $(NVDLA_TRACE_PARSER) -f $(NVDLA_TRACE) 54 | cd $(RUN_DIR) && gcc -fPIC -c $(NVDLA_TRACE_PARSER_COMMAND_SRC) -o $(NVDLA_TRACE_PARSER_COMMAND_OBJ) -I$(NVDLA_REGISTER_HEADER_DIR) -I$(NVDLA_TRACE_PLAYER_INCLUDES) 55 | cd $(RUN_DIR) && gcc -fPIC -shared -o $(NVDLA_TRACE_PARSER_COMMAND_LIB) $(NVDLA_TRACE_PARSER_COMMAND_OBJ) 56 | endif 57 | cd $(RUN_DIR) && $(SIM_DIR)/simv -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd +trace_output_lib=$(NVDLA_TRACE_PARSER_COMMAND_LIB) $(NVDLA_ENABLE_SIM_MEM) 58 | 59 | $(COMPLIB_DIR): 60 | cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl 61 | cd $(SIM_ROOT)/.. && vivado -mode batch -source create_libs.tcl 62 | cd $(SIM_ROOT)/.. && rm -rf create_libs.tcl 63 | -------------------------------------------------------------------------------- /cl_nvdla/verif/scripts/waves.tcl: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | set curr_wave [current_wave_config] 17 | if { [string length $curr_wave] == 0 } { 18 | if { [llength [get_objects]] > 0} { 19 | add_wave / 20 | set_property needs_save false [current_wave_config] 21 | } else { 22 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 23 | } 24 | } 25 | 26 | run 200 us 27 | quit 28 | -------------------------------------------------------------------------------- /cl_nvdla/verif/tests/test_null.sv: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | module test_null(); 17 | 18 | initial begin 19 | int exit_code; 20 | 21 | tb.power_up(); 22 | 23 | // tb.nsec_delay(500); 24 | // tb.poke_stat(.addr(8'h0c), .ddr_idx(0), .data(32'h0000_0000)); 25 | // tb.poke_stat(.addr(8'h0c), .ddr_idx(1), .data(32'h0000_0000)); 26 | // tb.poke_stat(.addr(8'h0c), .ddr_idx(2), .data(32'h0000_0000)); 27 | // 28 | tb.test_main(exit_code); 29 | 30 | #50ns; 31 | 32 | tb.power_down(); 33 | 34 | $finish; 35 | end 36 | 37 | endmodule // test_null 38 | -------------------------------------------------------------------------------- /cl_nvdla/verif/tests/trace_test.sv: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | // Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | // NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | module trace_test(); 20 | 21 | initial begin 22 | int exit_code; 23 | string trace_output_lib; 24 | int enable_sim_mem = 0; 25 | 26 | tb.power_up(); 27 | 28 | // tb.nsec_delay(500); 29 | // tb.poke_stat(.addr(8'h0c), .ddr_idx(0), .data(32'h0000_0000)); 30 | // tb.poke_stat(.addr(8'h0c), .ddr_idx(1), .data(32'h0000_0000)); 31 | // tb.poke_stat(.addr(8'h0c), .ddr_idx(2), .data(32'h0000_0000)); 32 | // 33 | 34 | $value$plusargs("trace_output_lib=%s", trace_output_lib); 35 | 36 | `ifdef SIM_BACKDOOR_MEM 37 | if ($test$plusargs("enable_sim_mem")) 38 | enable_sim_mem = 1; 39 | `endif 40 | 41 | if ($test$plusargs("enable_mem_log")) 42 | tb.enable_backdoor_mem_log(1); 43 | else 44 | tb.enable_backdoor_mem_log(0); 45 | 46 | @(tb.card.fpga.CL.bar1_slv_sync_rst_n === 1'b1); 47 | 48 | #50ns; 49 | 50 | tb.trace_test_main(exit_code, trace_output_lib, enable_sim_mem); 51 | 52 | #50ns; 53 | 54 | tb.power_down(); 55 | 56 | $finish; 57 | end 58 | 59 | endmodule // trace_test 60 | -------------------------------------------------------------------------------- /common/design/transactors/irq/simulate_x_tick.vh: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: simulate_x_tick.vh 10 | 11 | `ifdef _SIMULATE_X_VH_ 12 | `else 13 | `define _SIMULATE_X_VH_ 14 | 15 | // synopsys translate_off 16 | `define SIMULATION_ONLY 17 | //synopsys translate_on 18 | 19 | // useful values 20 | `ifdef SIMULATION_ONLY 21 | `define x_or_0 1'b0 22 | `define x_or_1 1'b1 23 | 24 | `define tick_x_or_0 1'b0 25 | `define tick_x_or_1 1'b1 26 | `else 27 | `define x_or_0 1'b0 28 | `define x_or_1 1'b1 29 | 30 | `define tick_x_or_0 1'b0 31 | `define tick_x_or_1 1'b1 32 | `endif 33 | 34 | // recommended tick defines 35 | `ifdef SIMULATION_ONLY 36 | `define tick_x_or_0 1'b0 37 | `define tick_x_or_1 1'b1 38 | `else 39 | `define tick_x_or_0 1'b0 40 | `define tick_x_or_1 1'b1 41 | `endif 42 | 43 | `endif 44 | -------------------------------------------------------------------------------- /common/design/vlibs/NV_BLKBOX_SINK.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: NV_BLKBOX_SINK.v 10 | 11 | module NV_BLKBOX_SINK ( 12 | A 13 | ); 14 | 15 | input A ; 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /common/design/vlibs/NV_CLK_gate_power.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: NV_CLK_gate_power.v 10 | 11 | module NV_CLK_gate_power (clk, reset_, clk_en, clk_gated); 12 | input clk, reset_, clk_en; 13 | output clk_gated; 14 | 15 | `ifdef VLIB_BYPASS_POWER_CG 16 | assign clk_gated = clk; 17 | `else 18 | 19 | CKLNQD12 p_clkgate (.TE(1'b0), .CP(clk), .E(clk_en), .Q(clk_gated)); 20 | 21 | `endif // VLIB_BYPASS_POWER_CG 22 | 23 | // the gated clk better not be x after reset 24 | // 25 | `ifdef VERILINT 26 | `else 27 | // synopsys translate_off 28 | 29 | reg disable_asserts; initial disable_asserts = $test$plusargs( "disable_nv_clk_gate_asserts" ) != 0; 30 | 31 | nv_assert_no_x #(0, 1, 0, "clk_gated is X after reset" ) 32 | clk_not_x( .clk( clk ), .reset_( reset_ || disable_asserts ), .start_event( 1'b1 ), .test_expr( clk_gated ) ); 33 | 34 | nv_assert_no_x #(0, 1, 0, "clk_en is X after reset" ) 35 | clk_en_not_x( .clk( clk ), .reset_( reset_ || disable_asserts ), .start_event( 1'b1 ), .test_expr( clk_en ) ); 36 | 37 | // synopsys translate_on 38 | `endif 39 | 40 | endmodule // NV_CLK_gate 41 | 42 | -------------------------------------------------------------------------------- /common/design/vlibs/p_SSYNC2DO_C_PP.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: p_SSYNC2DO_C_PP.v 10 | 11 | module p_SSYNC2DO_C_PP ( 12 | clk 13 | ,d 14 | ,clr_ 15 | ,q 16 | ); 17 | 18 | //--------------------------------------- 19 | //IO DECLARATIONS 20 | 21 | input clk ; 22 | input d ; 23 | input clr_ ; 24 | output q ; 25 | 26 | reg q,d0; 27 | 28 | always @(posedge clk or negedge clr_) 29 | begin 30 | if(~clr_) 31 | {q,d0} <= 2'd0; 32 | else 33 | {q,d0} <= {d0,d}; 34 | end 35 | 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /common/design/vlibs/p_SSYNC3DO_C_PPP.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: p_SSYNC3DO_C_PPP.v 10 | 11 | module p_SSYNC3DO_C_PPP ( 12 | clk 13 | ,d 14 | ,clr_ 15 | ,q 16 | ); 17 | 18 | //--------------------------------------- 19 | //IO DECLARATIONS 20 | 21 | input clk ; 22 | input d ; 23 | input clr_ ; 24 | output q ; 25 | 26 | reg q,d1,d0; 27 | 28 | always @(posedge clk or negedge clr_) 29 | begin 30 | if(~clr_) 31 | {q,d1,d0} <= 3'd0; 32 | else 33 | {q,d1,d0} <= {d1,d0,d}; 34 | end 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /common/design/vlibs/sync2d_c_pp.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: sync2d_c_pp.v 10 | 11 | module sync2d_c_pp ( d, clk, clr_, q ); 12 | input d, clk, clr_; 13 | output q; 14 | p_SSYNC2DO_C_PP NV_GENERIC_CELL( .d(d), .clk (clk), .clr_(clr_), .q(q) ); 15 | // synopsys dc_script_begin 16 | // synopsys dc_script_end 17 | //g2c if {[find / -null_ok -subdesign sync2d_c_pp] != {} } { set_attr preserve 1 [find / -subdesign sync2d_c_pp] } 18 | endmodule 19 | -------------------------------------------------------------------------------- /common/design/vlibs/sync3d_c_ppp.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: sync3d_c_ppp.v 10 | 11 | module sync3d_c_ppp ( d, clk, clr_, q ); 12 | input d, clk, clr_; 13 | output q; 14 | p_SSYNC3DO_C_PPP NV_GENERIC_CELL( .d(d), .clk(clk), .clr_(clr_), .q(q) ); 15 | // synopsys dc_script_begin 16 | // synopsys dc_script_end 17 | //g2c if {[find / -null_ok -subdesign sync3d_c_ppp] != {} } { set_attr preserve 1 [find / -subdesign sync3d_c_ppp] } 18 | endmodule 19 | -------------------------------------------------------------------------------- /common/design/xilinx_ip/README.md: -------------------------------------------------------------------------------- 1 | # Xilinux code 2 | 3 | User needs to put all code generated by Xilinux tool here before generate AFI for custom RTL logic. 4 | 5 | More details please refer [here](http://nvdla.org/vp_fpga.html). -------------------------------------------------------------------------------- /common/software/include/cosim_top.h: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: cosim_top.h 10 | 11 | #ifndef _COSIM_TOP_H_ 12 | #define _COSIM_TOP_H_ 13 | 14 | #include 15 | #include "shm_lib/simdb.hpp" 16 | #include "shm_lib/shm_defs.h" 17 | 18 | #ifndef SC_INCLUDE_DYNAMIC_PROCESSES 19 | #define SC_INCLUDE_DYNAMIC_PROCESSES 20 | #endif 21 | #define SIMDB_BLOCK_SIZE 1024 22 | #define SIMDB_BLOCK_COUNT 1024 23 | 24 | using namespace std; 25 | 26 | class cosim_top : public sc_core::sc_module{ 27 | public: 28 | SC_HAS_PROCESS(cosim_top); 29 | cosim_top( sc_core::sc_module_name name = "cosim_top"); 30 | ~cosim_top(); 31 | 32 | private: 33 | uint32_t poll_time_ns; 34 | 35 | simdb *apb_ipc_db; 36 | simdb *irq_ipc_db; 37 | simdb *ram_ipc_db; 38 | 39 | char *apb_ipc_db_nm; 40 | char *irq_ipc_db_nm; 41 | char *ram_ipc_db_nm; 42 | 43 | void apb_ipc_channel(); 44 | void irq_ipc_channel(); 45 | void ram_ipc_channel(); 46 | }; 47 | 48 | #endif 49 | -------------------------------------------------------------------------------- /common/software/include/sh_dpi_tasks.h: -------------------------------------------------------------------------------- 1 | // Amazon FPGA Hardware Development Kit 2 | // 3 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | // 5 | // Licensed under the Amazon Software License (the "License"). You may not use 6 | // this file except in compliance with the License. A copy of the License is 7 | // located at 8 | // 9 | // http://aws.amazon.com/asl/ 10 | // 11 | // or in the "license" file accompanying this file. This file is distributed on 12 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | // implied. See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | 16 | // Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | // NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | 20 | #ifndef SH_DPI_TASKS 21 | #define SH_DPI_TASKS 22 | 23 | #include 24 | #include 25 | 26 | #define SIZE_UINT8 0 27 | #define SIZE_UINT16 1 28 | #define SIZE_UINT32 2 29 | #define SIZE_UINT64 3 30 | 31 | #define CFG_RESET_ADDR (0x14) 32 | 33 | extern void sv_printf(char *msg); 34 | extern void sv_map_host_memory(uint8_t *memory); 35 | 36 | extern void cl_peek_ocl(uint64_t addr, uint32_t *data); 37 | extern void cl_poke_ocl(uint64_t addr, uint32_t data); 38 | extern void cl_peek_bar1(uint64_t addr, uint32_t *data); 39 | extern void cl_poke_bar1(uint64_t addr, uint32_t data); 40 | extern void cl_peek_pcis(uint64_t addr, uint64_t *data, uint32_t size); 41 | extern void cl_poke_pcis(uint64_t addr, uint64_t data, uint32_t size); 42 | extern void sv_int_ack(uint32_t int_num); 43 | 44 | extern void sv_pause(uint32_t x); 45 | 46 | extern void sv_assert(uint32_t x); 47 | 48 | extern void backdoor_mem_write(uint64_t addr, uint64_t data, uint32_t size, uint32_t wstrb); 49 | extern uint64_t backdoor_mem_read(uint64_t addr, uint32_t size); 50 | 51 | void test_main(uint32_t *exit_code); 52 | void trace_test_main(uint32_t *exit_code, const char *trace_output_lib, int enable_sim_mem); 53 | 54 | void cl_int_handler(uint32_t int_num); 55 | 56 | void host_memory_putc(uint64_t addr, uint8_t data); 57 | 58 | //void host_memory_getc(uint64_t addr, uint8_t *data) 59 | uint8_t host_memory_getc(uint64_t addr); 60 | 61 | void log_printf(const char *format, ...); 62 | 63 | void int_handler(uint32_t int_num); 64 | 65 | #define LOW_32b(a) ((uint32_t)((uint64_t)(a) & 0xffffffff)) 66 | #define HIGH_32b(a) ((uint32_t)(((uint64_t)(a)) >> 32L)) 67 | 68 | #endif 69 | -------------------------------------------------------------------------------- /common/software/include/shm_lib/shm_defs.h: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: shm_defs.h 10 | 11 | #ifndef _SHM_DEFS_H__ 12 | #define _SHM_DEFS_H__ 13 | 14 | #include 15 | #include 16 | #define SIMDB_BLOCK_SIZE 1024 17 | #define SIMDB_BLOCK_COUNT 1024 18 | 19 | enum PAYLOAD_TYPE 20 | { 21 | PAYLOAD_TYPE_APB = 0, 22 | PAYLOAD_TYPE_RAM 23 | }; 24 | 25 | struct trans_payload 26 | { 27 | unsigned int data; 28 | unsigned long long addr; 29 | }; 30 | 31 | struct irq_trans_payload 32 | { 33 | unsigned int value; 34 | }; 35 | 36 | #endif -------------------------------------------------------------------------------- /common/software/src/sh_dpi_tasks.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2015-2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"). You may 5 | * not use this file except in compliance with the License. A copy of the 6 | * License is located at 7 | * 8 | * http://aws.amazon.com/apache2.0/ 9 | * 10 | * or in the "license" file accompanying this file. This file is distributed 11 | * on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either 12 | * express or implied. See the License for the specific language governing 13 | * permissions and limitations under the License. 14 | */ 15 | 16 | // Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. 17 | // NVIDIA’s contributions are offered under the Amazon Software License 18 | 19 | 20 | #ifndef VIVADO_SIM 21 | #include "svdpi.h" 22 | #endif 23 | 24 | #include "sh_dpi_tasks.h" 25 | 26 | void host_memory_putc(uint64_t addr, uint8_t data) 27 | { 28 | *(uint8_t *)addr = data; 29 | } 30 | 31 | //void host_memory_getc(uint64_t addr, uint8_t *data) 32 | uint8_t host_memory_getc(uint64_t addr) 33 | { 34 | return *(uint8_t *)addr; 35 | } 36 | 37 | void log_printf(const char *format, ...) 38 | { 39 | static char sv_msg_buffer[256]; 40 | va_list args; 41 | 42 | va_start(args, format); 43 | vsprintf(sv_msg_buffer, format, args); 44 | sv_printf(sv_msg_buffer); 45 | 46 | va_end(args); 47 | } 48 | 49 | void int_handler(uint32_t int_num) 50 | { 51 | // Vivado does not support svGetScopeFromName 52 | #ifndef VIVADO_SIM 53 | svScope scope; 54 | scope = svGetScopeFromName("tb"); 55 | svSetScope(scope); 56 | #endif 57 | 58 | log_printf("Received interrupt %2d", int_num); 59 | sv_int_ack(int_num); 60 | 61 | cl_int_handler(int_num); 62 | 63 | } 64 | -------------------------------------------------------------------------------- /common/trace_player/Makefile.inc: -------------------------------------------------------------------------------- 1 | # ================================================================ 2 | # NVDLA Open Source Project 3 | # 4 | # Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | # NVDLA Open Hardware License; Check \"LICENSE\" which comes with 6 | # this distribution for more information. 7 | # ================================================================ 8 | 9 | export NVDLA_TRACE_PARSER ?= $(NVDLA_TRACE_PLAYER_ROOT)/parser/nvdla_trace_parser.py 10 | export NVDLA_TRACE_PARSER_COMMAND_NAME ?= trace_parser_command 11 | export NVDLA_TRACE_PARSER_COMMAND_SRC ?= $(addsuffix .c, $(NVDLA_TRACE_PARSER_COMMAND_NAME)) 12 | export NVDLA_TRACE_PARSER_COMMAND_OBJ ?= $(addsuffix .o, $(NVDLA_TRACE_PARSER_COMMAND_NAME)) 13 | export NVDLA_TRACE_PARSER_COMMAND_LIB ?= $(addprefix lib, $(addsuffix .so, $(NVDLA_TRACE_PARSER_COMMAND_NAME))) 14 | 15 | export NVDLA_TRACE_PLAYER_INCLUDES ?= $(NVDLA_TRACE_PLAYER_ROOT)/include 16 | export NVDLA_TRACE_PLAYER_SRC_DIR ?= $(NVDLA_TRACE_PLAYER_ROOT)/src 17 | export NVDLA_TRACE_PLAYER_SRCS ?= \ 18 | trace_player_cmd.c \ 19 | trace_player_intr.c \ 20 | trace_player_sync.c \ 21 | trace_player_reg.c \ 22 | trace_player_mem.c \ 23 | trace_player_thread.c \ 24 | 25 | export NVDLA_TRACE_PLAYER_LIB_DIR ?= $(NVDLA_TRACE_PLAYER_ROOT)/build 26 | export NVDLA_TRACE_PLAYER_LIB ?= trace_player_shared 27 | 28 | export NVDLA_TRACE_PLAYER_SRCS_FULLPATH ?= $(addprefix $(NVDLA_TRACE_PLAYER_SRC_DIR)/,${NVDLA_TRACE_PLAYER_SRCS}) 29 | 30 | $(NVDLA_TRACE_PARSER_COMMAND_SRC): 31 | $(NVDLA_TRACE_PARSER) -f $(NVDLA_TRACE) 32 | 33 | $(NVDLA_TRACE_PARSER_COMMAND_LIB): $(NVDLA_TRACE_PARSER_COMMAND_SRC) 34 | $(CC) -fPIC -c $(NVDLA_TRACE_PARSER_COMMAND_SRC) -o $(NVDLA_TRACE_PARSER_COMMAND_OBJ) -I$(NVDLA_TRACE_PLAYER_INCLUDES) -I$(NVDLA_REGISTER_HEADER_DIR) 35 | $(CC) -fPIC -shared -o $(NVDLA_TRACE_PARSER_COMMAND_LIB) $(NVDLA_TRACE_PARSER_COMMAND_OBJ) 36 | 37 | $(NVDLA_TRACE_PLAYER_LIB_DIR)/$(NVDLA_TRACE_PLAYER_LIB): 38 | cd $(NVDLA_TRACE_PLAYER_LIB_DIR) && make clean && make NVDLA_TRACE_PLAYER_CFLAGS=$(NVDLA_TRACE_PLAYER_CFLAGS) CC=$(CC) 39 | -------------------------------------------------------------------------------- /common/trace_player/build/Makefile: -------------------------------------------------------------------------------- 1 | # ================================================================ 2 | # NVDLA Open Source Project 3 | # 4 | # Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | # NVDLA Open Hardware License; Check \"LICENSE\" which comes with 6 | # this distribution for more information. 7 | # ================================================================ 8 | 9 | VPATH = ../src 10 | 11 | INCLUDES = -I../../../common/software/include -I../include 12 | 13 | CC ?= gcc 14 | CFLAGS = -Wall -fPIC $(INCLUDES) $(NVDLA_TRACE_PLAYER_CFLAGS) 15 | LDLIBS = -ldl 16 | 17 | SRC = \ 18 | trace_player.c \ 19 | trace_player_cmd.c \ 20 | trace_player_intr.c \ 21 | trace_player_sync.c \ 22 | trace_player_reg.c \ 23 | trace_player_mem.c \ 24 | trace_player_thread.c \ 25 | 26 | OBJ = $(SRC:.c=.o) 27 | TARGET = libtrace_player_shared.so 28 | 29 | all: $(TARGET) 30 | 31 | $(TARGET): $(OBJ) 32 | $(CC) $(CFLAGS) -shared -o $@ $^ $(LDFLAGS) $(LDLIBS) 33 | 34 | clean: 35 | rm -f *.o $(TARGET) 36 | -------------------------------------------------------------------------------- /common/trace_player/include/trace_player.h: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player.h 10 | 11 | #ifndef TRACE_PLAYER_H 12 | #define TRACE_PLAYER_H 13 | 14 | void trace_player_set_stop_on_error(int val); 15 | void trace_player_set_wait_interval(int val); 16 | void trace_player_set_skip_mem_init(int val); 17 | void trace_player_set_dump_mem_enable(int val); 18 | int trace_player_run(const char *parser_output_lib); 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /common/trace_player/include/trace_player_impl.h: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_impl.h 10 | 11 | #ifndef TRACE_PLAYER_IMPL_H 12 | #define TRACE_PLAYER_IMPL_H 13 | 14 | #include 15 | 16 | extern void reg_write(uint64_t offset, uint32_t val); 17 | extern void reg_read(uint64_t offset, uint32_t *val); 18 | extern void mem_write64(const char *mem_type, uint64_t offset, uint64_t val); 19 | extern void mem_write32(const char *mem_type, uint64_t offset, uint32_t val); 20 | extern void mem_write16(const char *mem_type, uint64_t offset, uint16_t val); 21 | extern void mem_write8(const char *mem_type, uint64_t offset, uint8_t val); 22 | extern void mem_read64(const char *mem_type, uint64_t offset, uint64_t *val); 23 | extern void mem_read32(const char *mem_type, uint64_t offset, uint32_t *val); 24 | extern void mem_read16(const char *mem_type, uint64_t offset, uint16_t *val); 25 | extern void mem_read8(const char *mem_type, uint64_t offset, uint8_t *val); 26 | extern void trace_player_wait(int num); 27 | extern uint32_t trace_player_check_and_clear_pending_intr(void); 28 | 29 | #endif 30 | -------------------------------------------------------------------------------- /common/trace_player/include/trace_player_intr.h: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_intr.h 10 | 11 | #ifndef TRACE_PLAYER_INTR_H 12 | #define TRACE_PLAYER_INTR_H 13 | 14 | #include 15 | 16 | typedef struct { 17 | uint32_t intr_id; 18 | char *sync_id; 19 | } trace_player_intr_t; 20 | 21 | typedef struct trace_player_intr_node { 22 | trace_player_intr_t intr; 23 | struct trace_player_intr_node *next; 24 | } trace_player_intr_node_t; 25 | 26 | void trace_player_push_expect_intr(uint32_t intr_id, const char* sync_id); 27 | int trace_player_intr_check(uint32_t intr_id); 28 | 29 | #endif 30 | -------------------------------------------------------------------------------- /common/trace_player/include/trace_player_mem.h: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_mem.h 10 | 11 | #ifndef TRACE_PLAYER_MEM_H 12 | #define TRACE_PLAYER_MEM_H 13 | 14 | #include 15 | 16 | void trace_player_mem_set_skip_mem_init(int val); 17 | void trace_player_mem_set_dump_mem_enable(int val); 18 | int trace_player_mem_load(const char *mem_type, uint64_t base, const char *file_path); 19 | int trace_player_mem_init_pattern(const char *mem_type, uint64_t base, uint32_t size, const char *pattern); 20 | int trace_player_mem_init_file(const char *mem_type, uint64_t base, const char *file_path); 21 | int trace_player_mem_check_crc(const char *mem_type, uint64_t base, uint32_t size, uint32_t golden_crc); 22 | int trace_player_mem_check_file(const char *mem_type, uint64_t base, uint32_t size, const char *file_path); 23 | 24 | #endif 25 | -------------------------------------------------------------------------------- /common/trace_player/include/trace_player_parser.h: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_parser.h 10 | 11 | #ifndef TRACE_PLAYER_PARSER_H 12 | #define TRACE_PLAYER_PARSER_H 13 | 14 | #include 15 | 16 | extern void trace_player_thread_push_cmd_reg_write(const char* thread_name, uint64_t offset, uint32_t value); 17 | extern void trace_player_thread_push_cmd_reg_read(const char* thread_name, uint64_t offset, const char *sync_id); 18 | extern void trace_player_thread_push_cmd_reg_read_check(const char* thread_name, uint64_t offset, uint32_t golden_val); 19 | extern void trace_player_thread_push_cmd_poll_reg_equal(const char* thread_name, uint64_t offset, uint32_t expect_val); 20 | extern void trace_player_thread_push_cmd_mem_load(const char* mem_type, uint64_t base, const char *file_path); 21 | extern void trace_player_thread_push_cmd_mem_init_pattern(const char* mem_type, uint64_t base, uint32_t size, const char *pattern); 22 | extern void trace_player_thread_push_cmd_mem_init_file(const char* mem_type, uint64_t base, const char *file_path); 23 | extern void trace_player_thread_push_cmd_intr_notify(uint32_t intr_id, const char *sync_id); 24 | extern void trace_player_thread_push_cmd_sync_wait(const char* thread_name, const char *sync_id); 25 | extern void trace_player_thread_push_cmd_sync_notify(const char* thread_name, const char *sync_id); 26 | extern void trace_player_thread_push_cmd_check_crc(const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, uint32_t golden_crc); 27 | extern void trace_player_thread_push_cmd_check_file(const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, const char *file_path); 28 | extern void trace_player_thread_push_cmd_check_nothing(const char *sync_id); 29 | 30 | #endif 31 | -------------------------------------------------------------------------------- /common/trace_player/include/trace_player_reg.h: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_reg.h 10 | 11 | #ifndef TRACE_PLAYER_REG_H_ 12 | #define TRACE_PLAYER_REG_H_ 13 | 14 | #include 15 | 16 | int trace_player_reg_read_check(uint64_t offset, uint32_t golden_val); 17 | int trace_player_reg_poll_reg_equal(uint64_t offset, uint32_t expect_val); 18 | 19 | #endif 20 | -------------------------------------------------------------------------------- /common/trace_player/include/trace_player_sync.h: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_sync.h 10 | 11 | #ifndef TRACE_PLAYER_SYNC_H 12 | #define TRACE_PLAYER_SYNC_H 13 | 14 | typedef struct { 15 | char *sync_id; 16 | int notified; 17 | } trace_player_sync_t; 18 | 19 | typedef struct trace_player_sync_node { 20 | trace_player_sync_t sync; 21 | struct trace_player_sync_node *next; 22 | } trace_player_sync_node_t; 23 | 24 | void trace_player_sync_notify(const char *sync_id); 25 | int trace_player_sync_is_notified(const char *sync_id); 26 | 27 | #endif 28 | -------------------------------------------------------------------------------- /common/trace_player/include/trace_player_thread.h: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_thread.h 10 | 11 | #ifndef TRACE_PLAYER_THREAD_H 12 | #define TRACE_PLAYER_THREAD_H 13 | 14 | #include "trace_player_cmd.h" 15 | 16 | typedef struct { 17 | char *name; 18 | trace_player_cmd_node_t *cmd_head; 19 | } trace_player_thread_t; 20 | 21 | typedef struct trace_player_thread_node { 22 | trace_player_thread_t thread; 23 | struct trace_player_thread_node *next; 24 | } trace_player_thread_node_t; 25 | 26 | trace_player_thread_node_t** trace_player_thread_list_get_head(void); 27 | trace_player_cmd_result_t trace_player_thread_run(trace_player_thread_t *thread); 28 | void trace_player_thread_list_remove_node(trace_player_thread_node_t *rnode); 29 | void trace_player_thread_push_cmd_reg_write(const char* thread_name, uint64_t offset, uint32_t value); 30 | void trace_player_thread_push_cmd_reg_read(const char* thread_name, uint64_t offset, const char *sync_id); 31 | void trace_player_thread_push_cmd_reg_read_check(const char* thread_name, uint64_t offset, uint32_t golden_val); 32 | void trace_player_thread_push_cmd_poll_reg_equal(const char* thread_name, uint64_t offset, uint32_t expect_val); 33 | void trace_player_thread_push_cmd_mem_load(const char* mem_type, uint64_t base, const char *file_path); 34 | void trace_player_thread_push_cmd_mem_init_pattern(const char* mem_type, uint64_t base, uint32_t size, const char *pattern); 35 | void trace_player_thread_push_cmd_mem_init_file(const char* mem_type, uint64_t base, const char *file_path); 36 | void trace_player_thread_push_cmd_intr_notify(uint32_t intr_id, const char *sync_id); 37 | void trace_player_thread_push_cmd_sync_wait(const char* thread_name, const char *sync_id); 38 | void trace_player_thread_push_cmd_sync_notify(const char* thread_name, const char *sync_id); 39 | void trace_player_thread_push_cmd_check_crc(const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, uint32_t golden_crc); 40 | void trace_player_thread_push_cmd_check_file(const char *sync_id, const char* mem_type, uint64_t base, uint32_t size, const char *file_path); 41 | void trace_player_thread_push_cmd_check_nothing(const char *sync_id); 42 | 43 | #endif 44 | -------------------------------------------------------------------------------- /common/trace_player/include/trace_player_utils.h: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_utils.h 10 | 11 | #ifndef TRACE_PLAYER_UTILS_H 12 | #define TRACE_PLAYER_UTILS_H 13 | 14 | #include 15 | 16 | #ifdef DEBUG 17 | #define DEBUG_PRINT(a) printf a 18 | #else 19 | #define DEBUG_PRINT(a) (void)0 20 | #endif 21 | 22 | #endif 23 | -------------------------------------------------------------------------------- /common/trace_player/src/trace_player_intr.c: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_intr.c 10 | 11 | #include 12 | #include 13 | #include "trace_player_utils.h" 14 | #include "trace_player_intr.h" 15 | #include "trace_player_sync.h" 16 | 17 | static trace_player_intr_node_t *head = NULL; 18 | 19 | void trace_player_push_expect_intr(uint32_t intr_id, const char* sync_id) 20 | { 21 | DEBUG_PRINT(("TRACE_PLAYER_INTR: push expect intr, id=0x%x, sync_id=%s\n", intr_id, sync_id)); 22 | trace_player_intr_node_t *new_node; 23 | new_node = malloc(sizeof(trace_player_intr_node_t)); 24 | new_node->intr.intr_id = intr_id; 25 | new_node->intr.sync_id = strdup(sync_id); 26 | new_node->next = NULL; 27 | 28 | if (head == NULL) { 29 | head = new_node; 30 | } else { 31 | trace_player_intr_node_t *current = head; 32 | while (current->next != NULL) { 33 | current = current->next; 34 | } 35 | current->next = new_node; 36 | } 37 | 38 | } 39 | 40 | int trace_player_intr_check(uint32_t intr_id) 41 | { 42 | int rc = 0; 43 | 44 | if (intr_id != 0 && head != NULL) { 45 | while ((intr_id & head->intr.intr_id) == head->intr.intr_id) { 46 | DEBUG_PRINT(("TRACE_PLAYER_INTR: get expected intr id=0x%x\n", head->intr.intr_id)); 47 | /* notify sync_id */ 48 | trace_player_sync_notify(head->intr.sync_id); 49 | /* clear head intr */ 50 | intr_id = intr_id & (~(head->intr.intr_id)); 51 | /* pop intr list */ 52 | trace_player_intr_node_t *next_node = head->next; 53 | free(head->intr.sync_id); 54 | free(head); 55 | head = next_node; 56 | if (head == NULL) 57 | break; 58 | } 59 | } 60 | if (intr_id != 0 && head != NULL) { 61 | trace_player_intr_node_t *p1 = head; 62 | trace_player_intr_node_t *p2 = p1->next; 63 | while (p2 != NULL) { 64 | if ((intr_id & p2->intr.intr_id) == p2->intr.intr_id) { 65 | DEBUG_PRINT(("TRACE_PLAYER_INTR: get expected intr id=0x%x\n", p2->intr.intr_id)); 66 | /* notify sync_id */ 67 | trace_player_sync_notify(p2->intr.sync_id); 68 | /* clear p2 intr */ 69 | intr_id = intr_id & (~(p2->intr.intr_id)); 70 | 71 | p1->next = p2->next; 72 | 73 | free(p2->intr.sync_id); 74 | free(p2); 75 | } else { 76 | p1 = p1->next; 77 | } 78 | p2 = p1->next; 79 | } 80 | } 81 | 82 | if (intr_id != 0) { 83 | DEBUG_PRINT(("TRACE_PLAYER_INTR: WARNING! unexpect intr_id=0x%x\n", intr_id)); 84 | //rc = 1; 85 | } 86 | 87 | return rc; 88 | } 89 | -------------------------------------------------------------------------------- /common/trace_player/src/trace_player_reg.c: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_reg.c 10 | 11 | #include "trace_player_reg.h" 12 | #include "trace_player_utils.h" 13 | #include "trace_player_impl.h" 14 | 15 | int trace_player_reg_read_check(uint64_t offset, uint32_t golden_val) 16 | { 17 | int rc = 0; 18 | uint32_t val; 19 | reg_read(offset, &val); 20 | if (val != golden_val) { 21 | DEBUG_PRINT(("TRACE_PLAYER_REG_READ_CHECK: ERROR! addr=0x%lx, exp=0x%x, act=0x%x\n", offset, golden_val, val)); 22 | rc = 1; 23 | } 24 | return rc; 25 | } 26 | 27 | int trace_player_reg_poll_reg_equal(uint64_t offset, uint32_t expect_val) 28 | { 29 | int rc = 0; 30 | uint32_t val; 31 | reg_read(offset, &val); 32 | if (val != expect_val) { 33 | rc = 1; 34 | } 35 | return rc; 36 | } 37 | -------------------------------------------------------------------------------- /common/trace_player/src/trace_player_sync.c: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_sync.c 10 | 11 | #include 12 | #include 13 | #include "trace_player_utils.h" 14 | #include "trace_player_sync.h" 15 | 16 | static trace_player_sync_node_t *head = NULL; 17 | 18 | static trace_player_sync_node_t* trace_player_sync_find_or_create_node(const char *sync_id) 19 | { 20 | trace_player_sync_node_t *node = head; 21 | trace_player_sync_node_t *prev = NULL; 22 | 23 | while (node != NULL) { 24 | if (strcmp(sync_id, node->sync.sync_id) == 0) { 25 | break; 26 | } 27 | prev = node; 28 | node = node->next; 29 | } 30 | 31 | if (node == NULL) { 32 | node = malloc(sizeof(trace_player_sync_node_t)); 33 | node->sync.sync_id = strdup(sync_id); 34 | node->sync.notified = 0; 35 | node->next = NULL; 36 | if (prev != NULL) { 37 | prev->next = node; 38 | } 39 | if (head == NULL) { 40 | head = node; 41 | } 42 | } 43 | 44 | return node; 45 | } 46 | 47 | void trace_player_sync_notify(const char *sync_id) 48 | { 49 | trace_player_sync_node_t* node = trace_player_sync_find_or_create_node(sync_id); 50 | node->sync.notified = 1; 51 | } 52 | 53 | int trace_player_sync_is_notified(const char *sync_id) 54 | { 55 | trace_player_sync_node_t* node = trace_player_sync_find_or_create_node(sync_id); 56 | return node->sync.notified; 57 | } 58 | -------------------------------------------------------------------------------- /common/trace_player/test/test_trace/test_trace.cfg: -------------------------------------------------------------------------------- 1 | mem_load(pri_mem, 0xC0000000, "test_trace_input.dat"); 2 | reg_write(NVDLA_BDMA.CFG_SRC_ADDR_HIGH_0, 0); 3 | reg_write(NVDLA_BDMA.CFG_SRC_ADDR_LOW_0, 0xC0000000); 4 | reg_write(NVDLA_BDMA.CFG_DST_ADDR_HIGH_0, 0); 5 | reg_write(NVDLA_BDMA.CFG_DST_ADDR_LOW_0 , 0xC0000000); 6 | reg_write(NVDLA_BDMA.CFG_DST_SURF_0, 0x800); 7 | reg_write(NVDLA_BDMA.CFG_DST_LINE_0, 0x100); 8 | reg_write(NVDLA_BDMA.CFG_SRC_SURF_0, 0x800); 9 | reg_write(NVDLA_BDMA.CFG_SRC_LINE_0, 0x100); 10 | reg_write(NVDLA_BDMA.CFG_SURF_REPEAT_0, 0); 11 | reg_write(NVDLA_BDMA.CFG_LINE_REPEAT_0, 7); 12 | reg_write(NVDLA_BDMA.CFG_LINE_0, 7); 13 | reg_write(NVDLA_BDMA.CFG_CMD_0, 3); 14 | reg_write(NVDLA_BDMA.CFG_OP_0, 1); 15 | reg_write(NVDLA_BDMA.CFG_LAUNCH0_0, 1); 16 | intr_notify(BDMA_0, BDMA_0_BDMA_0_interrupt); 17 | check_crc(BDMA_0_BDMA_0_interrupt, pri_mem, 0xC00017C0, 0x800, 0xf1e8ba9e); 18 | check_file(BDMA_0_BDMA_0_interrupt, pri_mem, 0xC00017C0, 0x800, "test_trace_output.dat"); 19 | -------------------------------------------------------------------------------- /common/trace_player/test/trace_player_test.c: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_test.c 10 | 11 | #include "trace_player_utils.h" 12 | #include "trace_player.h" 13 | 14 | int main() 15 | { 16 | int rc = 0; 17 | DEBUG_PRINT(("TEST: START\n")); 18 | rc = trace_player_run("./libtrace_parser_command.so"); 19 | DEBUG_PRINT(("TEST: END, rc=%d\n", rc)); 20 | 21 | return rc; 22 | } 23 | -------------------------------------------------------------------------------- /common/trace_player/test/trace_player_test_impl.c: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: trace_player_test_impl.c 10 | 11 | #include 12 | #include 13 | 14 | void reg_write(uint64_t offset, uint32_t val) 15 | { 16 | printf("REG_WRITE: offset=0x%lx, val=0x%x\n", offset, val); 17 | } 18 | 19 | void reg_read(uint64_t offset, uint32_t *val) 20 | { 21 | printf("REG_READ: offset=0x%lx, val=0x%x\n", offset, 0); 22 | } 23 | 24 | void mem_write64(const char *mem_type, uint64_t offset, uint64_t val) 25 | { 26 | printf("MEM_WRITE64: mem_type=%s, offset=0x%lx, val=0x%lx\n", mem_type, offset, val); 27 | } 28 | 29 | void mem_write32(const char *mem_type, uint64_t offset, uint32_t val) 30 | { 31 | printf("MEM_WRITE32: mem_type=%s, offset=0x%lx, val=0x%x\n", mem_type, offset, val); 32 | } 33 | 34 | void mem_write16(const char *mem_type, uint64_t offset, uint16_t val) 35 | { 36 | printf("MEM_WRITE16: mem_type=%s, offset=0x%lx, val=0x%x\n", mem_type, offset, val); 37 | } 38 | 39 | void mem_write8(const char *mem_type, uint64_t offset, uint8_t val) 40 | { 41 | printf("MEM_WRITE8: mem_type=%s, offset=0x%lx, val=0x%x\n", mem_type, offset, val); 42 | } 43 | 44 | void mem_read64(const char *mem_type, uint64_t offset, uint64_t *val) 45 | { 46 | printf("MEM_read64: mem_type=%s, offset=0x%lx\n", mem_type, offset); 47 | *val = 0; 48 | } 49 | 50 | void mem_read32(const char *mem_type, uint64_t offset, uint32_t *val) 51 | { 52 | printf("MEM_read32: mem_type=%s, offset=0x%lx\n", mem_type, offset); 53 | *val = 0; 54 | } 55 | 56 | void mem_read16(const char *mem_type, uint64_t offset, uint16_t *val) 57 | { 58 | printf("MEM_read16: mem_type=%s, offset=0x%lx\n", mem_type, offset); 59 | *val = 0; 60 | } 61 | 62 | void mem_read8(const char *mem_type, uint64_t offset, uint8_t *val) 63 | { 64 | printf("MEM_read8: mem_type=%s, offset=0x%lx\n", mem_type, offset); 65 | *val = 0; 66 | } 67 | 68 | void trace_player_wait(uint32_t num) 69 | { 70 | printf("WAIT: %d\n", num); 71 | } 72 | 73 | /* fake interrupt generate and handle */ 74 | uint32_t trace_player_check_and_clear_pending_intr(void) 75 | { 76 | uint32_t rc = 0; 77 | static int i = 0; 78 | 79 | if (i++ == 1000) { 80 | i = 0; 81 | rc = 0x1<<6; 82 | printf("NOTIFY_INTR: 0x%x\n", rc); 83 | } 84 | 85 | return rc; 86 | } 87 | --------------------------------------------------------------------------------