├── .gitignore ├── LICENSE ├── Project 1 – Introduction to Xilinx ├── README.md ├── Simulation Waveforms │ └── project1_halfAdder.png ├── half_adder.v └── half_adder_test.v ├── Project 2 – Combinational Logic ├── README.md ├── dec_4_to_16 │ ├── README.md │ ├── Simulation Waveforms │ │ └── project2_416decoder.png │ ├── dec_4_to_16.v │ └── dec_4_to_16_test.v ├── four_bit_look_ahead_adder │ ├── README.md │ ├── Simulation Waveforms │ │ └── project2_four_bit_adder.png │ ├── four_bit_adder_EC.v │ └── four_bit_adder_EC_test.v ├── four_bit_ripple_adder │ ├── README.md │ ├── Simulation Waveforms │ │ └── project2_four_bit_adder.png │ ├── four_bit_adder.v │ └── four_bit_adder_test.v ├── full_adder │ ├── README.md │ ├── Simulation Waveforms │ │ └── project2_full_adder.png │ ├── full_adder.v │ └── full_adder_test.v ├── mux_four_to_one │ ├── README.md │ ├── Simulation Waveforms │ │ └── project2_41_mux.png │ ├── mux_four_to_one.v │ └── mux_four_to_one_test.v ├── priority_encoder │ ├── README.md │ ├── Simulation Waveforms │ │ └── project2_priority_encoder.png │ ├── priority_encoder.v │ └── priority_encoder_test.v └── three_bit_comparator │ ├── README.md │ ├── Simulation Waveforms │ └── project2_comparator.png │ ├── three_bit_comparator.v │ └── three_bit_comparator_test.v ├── Project 3 – Traffic Light Controller ├── Project 3 Presentation.pdf ├── README.md ├── Simulation Waveforms │ ├── project3_test_A.png │ ├── project3_test_B.png │ ├── project3_test_C.png │ ├── project3_test_D.png │ ├── project3_test_E.png │ ├── project3_test_F.png │ ├── project3_test_G.png │ └── project3_test_H.png ├── Traffic_Test_A_eng312_proj3.v ├── Traffic_Test_B_eng312_proj3.v ├── Traffic_Test_C_eng312_proj3.v ├── Traffic_Test_D_eng312_proj3.v ├── Traffic_Test_E_eng312_proj3.v ├── Traffic_Test_F_eng312_proj3.v ├── Traffic_Test_G_eng312_proj3.v ├── Traffic_Test_H_eng312_proj3.v └── Traffic_eng312_proj3.v ├── Project 4 - 64-Bit Adder ├── README.md ├── behavioral_adder_64 │ ├── README.md │ ├── Simulation Waveforms │ │ ├── project4_test_E.png │ │ └── project4_test_F.png │ ├── behavioral_full_adder_64.v │ └── behavioral_full_adder_test.v ├── look_ahead_adder_64 │ ├── README.md │ ├── Simulation Waveforms │ │ ├── project4_test_C.png │ │ └── project4_test_D.png │ ├── look_ahead_adder_64.v │ └── look_ahead_adder_test.v └── ripple_adder_64 │ ├── README.md │ ├── Simulation Waveforms │ ├── project4_test_A.png │ └── project4_test_B.png │ ├── ripple_adder_64.v │ └── ripple_adder_64_test.v └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | .DS_Store 3 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/LICENSE -------------------------------------------------------------------------------- /Project 1 – Introduction to Xilinx/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 1 – Introduction to Xilinx/README.md -------------------------------------------------------------------------------- /Project 1 – Introduction to Xilinx/Simulation Waveforms/project1_halfAdder.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 1 – Introduction to Xilinx/Simulation Waveforms/project1_halfAdder.png -------------------------------------------------------------------------------- /Project 1 – Introduction to Xilinx/half_adder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 1 – Introduction to Xilinx/half_adder.v -------------------------------------------------------------------------------- /Project 1 – Introduction to Xilinx/half_adder_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 1 – Introduction to Xilinx/half_adder_test.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/README.md -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/dec_4_to_16/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/dec_4_to_16/README.md -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/dec_4_to_16/Simulation Waveforms/project2_416decoder.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/dec_4_to_16/Simulation Waveforms/project2_416decoder.png -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/dec_4_to_16/dec_4_to_16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/dec_4_to_16/dec_4_to_16.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/dec_4_to_16/dec_4_to_16_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/dec_4_to_16/dec_4_to_16_test.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/four_bit_look_ahead_adder/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/four_bit_look_ahead_adder/README.md -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/four_bit_look_ahead_adder/Simulation Waveforms/project2_four_bit_adder.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/four_bit_look_ahead_adder/Simulation Waveforms/project2_four_bit_adder.png -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/four_bit_look_ahead_adder/four_bit_adder_EC.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/four_bit_look_ahead_adder/four_bit_adder_EC.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/four_bit_look_ahead_adder/four_bit_adder_EC_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/four_bit_look_ahead_adder/four_bit_adder_EC_test.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/four_bit_ripple_adder/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/four_bit_ripple_adder/README.md -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/four_bit_ripple_adder/Simulation Waveforms/project2_four_bit_adder.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/four_bit_ripple_adder/Simulation Waveforms/project2_four_bit_adder.png -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/four_bit_ripple_adder/four_bit_adder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/four_bit_ripple_adder/four_bit_adder.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/four_bit_ripple_adder/four_bit_adder_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/four_bit_ripple_adder/four_bit_adder_test.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/full_adder/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/full_adder/README.md -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/full_adder/Simulation Waveforms/project2_full_adder.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/full_adder/Simulation Waveforms/project2_full_adder.png -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/full_adder/full_adder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/full_adder/full_adder.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/full_adder/full_adder_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/full_adder/full_adder_test.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/mux_four_to_one/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/mux_four_to_one/README.md -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/mux_four_to_one/Simulation Waveforms/project2_41_mux.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/mux_four_to_one/Simulation Waveforms/project2_41_mux.png -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/mux_four_to_one/mux_four_to_one.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/mux_four_to_one/mux_four_to_one.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/mux_four_to_one/mux_four_to_one_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/mux_four_to_one/mux_four_to_one_test.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/priority_encoder/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/priority_encoder/README.md -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/priority_encoder/Simulation Waveforms/project2_priority_encoder.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/priority_encoder/Simulation Waveforms/project2_priority_encoder.png -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/priority_encoder/priority_encoder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/priority_encoder/priority_encoder.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/priority_encoder/priority_encoder_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/priority_encoder/priority_encoder_test.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/three_bit_comparator/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/three_bit_comparator/README.md -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/three_bit_comparator/Simulation Waveforms/project2_comparator.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/three_bit_comparator/Simulation Waveforms/project2_comparator.png -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/three_bit_comparator/three_bit_comparator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/three_bit_comparator/three_bit_comparator.v -------------------------------------------------------------------------------- /Project 2 – Combinational Logic/three_bit_comparator/three_bit_comparator_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 2 – Combinational Logic/three_bit_comparator/three_bit_comparator_test.v -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Project 3 Presentation.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Project 3 Presentation.pdf -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/README.md -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_A.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_A.png -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_B.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_B.png -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_C.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_C.png -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_D.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_D.png -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_E.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_E.png -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_F.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_F.png -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_G.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_G.png -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_H.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Simulation Waveforms/project3_test_H.png -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Traffic_Test_A_eng312_proj3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Traffic_Test_A_eng312_proj3.v -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Traffic_Test_B_eng312_proj3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Traffic_Test_B_eng312_proj3.v -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Traffic_Test_C_eng312_proj3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Traffic_Test_C_eng312_proj3.v -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Traffic_Test_D_eng312_proj3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Traffic_Test_D_eng312_proj3.v -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Traffic_Test_E_eng312_proj3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Traffic_Test_E_eng312_proj3.v -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Traffic_Test_F_eng312_proj3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Traffic_Test_F_eng312_proj3.v -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Traffic_Test_G_eng312_proj3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Traffic_Test_G_eng312_proj3.v -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Traffic_Test_H_eng312_proj3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Traffic_Test_H_eng312_proj3.v -------------------------------------------------------------------------------- /Project 3 – Traffic Light Controller/Traffic_eng312_proj3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 3 – Traffic Light Controller/Traffic_eng312_proj3.v -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/README.md -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/behavioral_adder_64/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/behavioral_adder_64/README.md -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/behavioral_adder_64/Simulation Waveforms/project4_test_E.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/behavioral_adder_64/Simulation Waveforms/project4_test_E.png -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/behavioral_adder_64/Simulation Waveforms/project4_test_F.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/behavioral_adder_64/Simulation Waveforms/project4_test_F.png -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/behavioral_adder_64/behavioral_full_adder_64.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/behavioral_adder_64/behavioral_full_adder_64.v -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/behavioral_adder_64/behavioral_full_adder_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/behavioral_adder_64/behavioral_full_adder_test.v -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/look_ahead_adder_64/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/look_ahead_adder_64/README.md -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/look_ahead_adder_64/Simulation Waveforms/project4_test_C.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/look_ahead_adder_64/Simulation Waveforms/project4_test_C.png -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/look_ahead_adder_64/Simulation Waveforms/project4_test_D.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/look_ahead_adder_64/Simulation Waveforms/project4_test_D.png -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/look_ahead_adder_64/look_ahead_adder_64.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/look_ahead_adder_64/look_ahead_adder_64.v -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/look_ahead_adder_64/look_ahead_adder_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/look_ahead_adder_64/look_ahead_adder_test.v -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/ripple_adder_64/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/ripple_adder_64/README.md -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/ripple_adder_64/Simulation Waveforms/project4_test_A.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/ripple_adder_64/Simulation Waveforms/project4_test_A.png -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/ripple_adder_64/Simulation Waveforms/project4_test_B.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/ripple_adder_64/Simulation Waveforms/project4_test_B.png -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/ripple_adder_64/ripple_adder_64.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/ripple_adder_64/ripple_adder_64.v -------------------------------------------------------------------------------- /Project 4 - 64-Bit Adder/ripple_adder_64/ripple_adder_64_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/Project 4 - 64-Bit Adder/ripple_adder_64/ripple_adder_64_test.v -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/nxbyte/Verilog-Projects/HEAD/README.md --------------------------------------------------------------------------------