├── .python-version ├── chisellm ├── dataset │ ├── __init__.py │ ├── decompile │ │ ├── __init__.py │ │ ├── templates │ │ │ ├── instruction.j2 │ │ │ ├── cot.j2 │ │ │ └── tutorial.md │ │ └── pipeline.py │ └── completion │ │ ├── __init__.py │ │ ├── templates │ │ ├── generation_prompt.j2 │ │ ├── instruction.j2 │ │ ├── chat_template.j2 │ │ └── cot.j2 │ │ └── pipeline.py ├── utils │ ├── __init__.py │ └── template.py ├── .DS_Store ├── eval │ ├── verilog.j2 │ ├── chisel.scala.j2 │ ├── variation.j2 │ ├── variation-generate.j2 │ ├── s2c.j2 │ ├── d2c.j2 │ └── variation-rating.j2 └── train_config │ ├── ds │ ├── ds_z2_config.json │ ├── ds_z3_config.json │ └── ds_z3_offload_config.json │ ├── ChiseLLM-7B.yaml │ └── ChiseLLM-32B.yaml ├── assets ├── introduction.png └── logo.svg ├── .gitignore ├── pyproject.toml ├── README.md └── uv.lock /.python-version: -------------------------------------------------------------------------------- 1 | 3.13 2 | -------------------------------------------------------------------------------- /chisellm/dataset/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /chisellm/utils/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /chisellm/dataset/decompile/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /chisellm/dataset/completion/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /chisellm/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/observerw/ChiseLLM/HEAD/chisellm/.DS_Store -------------------------------------------------------------------------------- /assets/introduction.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/observerw/ChiseLLM/HEAD/assets/introduction.png -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Python-generated files 2 | __pycache__/ 3 | *.py[oc] 4 | build/ 5 | dist/ 6 | wheels/ 7 | *.egg-info 8 | 9 | # Virtual environments 10 | .venv 11 | 12 | archives/ -------------------------------------------------------------------------------- /pyproject.toml: -------------------------------------------------------------------------------- 1 | [project] 2 | name = "ChiseLLM" 3 | version = "0.1.0" 4 | description = "ChiseLLM Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development" 5 | readme = "README.md" 6 | requires-python = ">=3.13" 7 | dependencies = ["distilabel>=1.5.3", "jinja2>=3.1.6"] 8 | -------------------------------------------------------------------------------- /chisellm/eval/verilog.j2: -------------------------------------------------------------------------------- 1 | {{ spec }} 2 | 3 | # Requirement 4 | 5 | - Your code should be a valid Verilog module. 6 | - The module name and ports should match the specification. 7 | 8 | # Output 9 | 10 | The output code should be in a Markdown code block with an `{result}` identifier, as shown below: 11 | 12 | ```verilog {result} 13 | module TopModule( ... ); 14 | // implement the specification here 15 | endmodule 16 | ``` -------------------------------------------------------------------------------- /chisellm/eval/chisel.scala.j2: -------------------------------------------------------------------------------- 1 | //> using scala "2.13" 2 | //> using dep "org.chipsalliance::chisel:6.7.0" 3 | //> using plugin "org.chipsalliance:::chisel-plugin:6.7.0" 4 | //> using options "-unchecked" "-deprecation" "-language:reflectiveCalls" "-feature" "-Xcheckinit" "-Ywarn-dead-code" "-Ywarn-unused" 5 | 6 | import chisel3._ 7 | import chisel3.util._ 8 | import _root_.circt.stage.ChiselStage 9 | 10 | {{ code }} 11 | 12 | object Main extends App { 13 | val outputPath = args(0) 14 | 15 | ChiselStage.emitSystemVerilog( 16 | {{ top }}(), 17 | firtoolOpts = Array( 18 | "-disable-all-randomization", 19 | "-strip-debug-info", 20 | "-o", outputPath 21 | ) 22 | ) 23 | } 24 | -------------------------------------------------------------------------------- /chisellm/eval/variation.j2: -------------------------------------------------------------------------------- 1 | You are tasked with rating the given content based on the provided criteria. 2 | 3 | - The rating should be a number between 1 and 5, where 1 means the content is not up to the criteria at all, and 5 means it is excellent and meets all the criteria. 4 | - Your rating should be reasonable, objective, and based on the content provided. 5 | - Think carefully about each criterion and how well the content meets it before assigning a rating. 6 | 7 | # Output 8 | 9 | Your output should be a valid JSON object in a Markdown code block. The JSON object should contain: 10 | 11 | ```json 12 | { 13 | "rating": , 14 | "explanation": "" 15 | } 16 | ``` 17 | 18 | # Execution 19 | 20 | Content: 21 | 22 | {{ content }} 23 | 24 | Criteria: 25 | 26 | {{ criteria }} 27 | -------------------------------------------------------------------------------- /chisellm/dataset/completion/templates/generation_prompt.j2: -------------------------------------------------------------------------------- 1 | 2 | 3 | Okay, so the user asked me to implement a chisel module according to the design specification. The user also provided a reference implementation and relevant documentation, which I can use to guide my design process. However, the user mentioned that I shouldn't reference these resources as if they have been given by the user, but to pretend they are my own ideas. How can I achieve that? Oh, I know! When I reference the reference implementation, I can say something like "Let me try these following ideas: ..." followed by some code snippets from the reference implementation;and when I reference the documentation, I can say something like "Let me recall the documentation: ..." followed by the brief content of the document. 4 | 5 | 6 | Let's get started. First let me understand the requirements: -------------------------------------------------------------------------------- /chisellm/dataset/decompile/templates/instruction.j2: -------------------------------------------------------------------------------- 1 | You are tasked with **decompiling the given Verilog code into equivalent Chisel3 code**. Ensure your Chisel code is correct, efficient, and reusable. 2 | 3 | # Output 4 | 5 | your output must include the following content, each within a Markdown code block with id and group identifiers: 6 | 7 | ```scala {optimized} 8 | // The final optimized and refactored version of the Chisel3 code 9 | ``` 10 | 11 | # Requirements 12 | 13 | - Your thinking process should be comprehensive and well-reasoned, avoid repetitive thinking, keep it concise and informative. 14 | - Your thinking process should not only focus on implementing functionality correct code, but also syntactically correct code. That requires you to think about how to properly use Chisel language features. 15 | - Follow the format and instructions provided in the output section. 16 | 17 | # Request 18 | 19 | ```verilog 20 | {{ source }} 21 | ``` 22 | -------------------------------------------------------------------------------- /chisellm/train_config/ds/ds_z2_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "train_batch_size": "auto", 3 | "train_micro_batch_size_per_gpu": "auto", 4 | "gradient_accumulation_steps": "auto", 5 | "gradient_clipping": "auto", 6 | "zero_allow_untested_optimizer": true, 7 | "fp16": { 8 | "enabled": "auto", 9 | "loss_scale": 0, 10 | "loss_scale_window": 1000, 11 | "initial_scale_power": 16, 12 | "hysteresis": 2, 13 | "min_loss_scale": 1 14 | }, 15 | "bf16": { 16 | "enabled": "auto" 17 | }, 18 | "zero_optimization": { 19 | "stage": 2, 20 | "overlap_comm": true, 21 | "contiguous_gradients": true, 22 | "sub_group_size": 1e9, 23 | "reduce_bucket_size": "auto", 24 | "stage3_prefetch_bucket_size": "auto", 25 | "stage3_param_persistence_threshold": "auto", 26 | "stage3_max_live_parameters": 1e9, 27 | "stage3_max_reuse_distance": 1e9, 28 | "stage3_gather_16bit_weights_on_model_save": true 29 | } 30 | } -------------------------------------------------------------------------------- /chisellm/train_config/ds/ds_z3_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "train_batch_size": "auto", 3 | "train_micro_batch_size_per_gpu": "auto", 4 | "gradient_accumulation_steps": "auto", 5 | "gradient_clipping": "auto", 6 | "zero_allow_untested_optimizer": true, 7 | "fp16": { 8 | "enabled": "auto", 9 | "loss_scale": 0, 10 | "loss_scale_window": 1000, 11 | "initial_scale_power": 16, 12 | "hysteresis": 2, 13 | "min_loss_scale": 1 14 | }, 15 | "bf16": { 16 | "enabled": "auto" 17 | }, 18 | "zero_optimization": { 19 | "stage": 3, 20 | "overlap_comm": true, 21 | "contiguous_gradients": true, 22 | "sub_group_size": 1e9, 23 | "reduce_bucket_size": "auto", 24 | "stage3_prefetch_bucket_size": "auto", 25 | "stage3_param_persistence_threshold": "auto", 26 | "stage3_max_live_parameters": 1e9, 27 | "stage3_max_reuse_distance": 1e9, 28 | "stage3_gather_16bit_weights_on_model_save": true 29 | } 30 | } -------------------------------------------------------------------------------- /chisellm/train_config/ChiseLLM-7B.yaml: -------------------------------------------------------------------------------- 1 | ### wandb 2 | report_to: wandb 3 | run_name: ChiseLLM-7B 4 | 5 | ### model 6 | model_name_or_path: models/Qwen/Qwen2.5-Coder-7B-Instruct 7 | 8 | ### method 9 | stage: sft 10 | do_train: true 11 | finetuning_type: full 12 | 13 | ### dataset 14 | dataset_dir: datasets 15 | dataset: ChiseLLM-Completion,ChiseLLM-Decompile 16 | mix_strategy: interleave_under 17 | interleave_probs: 0.3,0.7 18 | template: qwen 19 | cutoff_len: 16384 20 | max_samples: 6000 21 | overwrite_cache: true 22 | preprocessing_num_workers: 48 23 | dataloader_persistent_workers: true 24 | dataloader_pin_memory: true 25 | dataloader_num_workers: 48 26 | 27 | ### output 28 | output_dir: output/ChiseLLM/ChiseLLM-7B 29 | logging_steps: 1 30 | save_steps: 1000 31 | plot_loss: true 32 | 33 | ### train 34 | per_device_train_batch_size: 2 35 | gradient_accumulation_steps: 8 36 | learning_rate: 1.0e-5 37 | num_train_epochs: 3.0 38 | lr_scheduler_type: cosine 39 | warmup_ratio: 0.05 40 | weight_decay: 0.0001 41 | bf16: true 42 | ddp_timeout: 180000000 43 | 44 | # speedup 45 | flash_attn: fa2 46 | enable_liger_kernel: true 47 | 48 | # memory 49 | deepspeed: config/ds/ds_z3_config.json -------------------------------------------------------------------------------- /chisellm/train_config/ds/ds_z3_offload_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "train_batch_size": "auto", 3 | "train_micro_batch_size_per_gpu": "auto", 4 | "gradient_accumulation_steps": "auto", 5 | "gradient_clipping": "auto", 6 | "zero_allow_untested_optimizer": true, 7 | "fp16": { 8 | "enabled": "auto", 9 | "loss_scale": 0, 10 | "loss_scale_window": 1000, 11 | "initial_scale_power": 16, 12 | "hysteresis": 2, 13 | "min_loss_scale": 1 14 | }, 15 | "bf16": { 16 | "enabled": "auto" 17 | }, 18 | "zero_optimization": { 19 | "stage": 3, 20 | "offload_optimizer": { 21 | "device": "cpu", 22 | "pin_memory": true 23 | }, 24 | "offload_param": { 25 | "device": "cpu", 26 | "pin_memory": true 27 | }, 28 | "overlap_comm": false, 29 | "contiguous_gradients": true, 30 | "sub_group_size": 1e9, 31 | "reduce_bucket_size": "auto", 32 | "stage3_prefetch_bucket_size": "auto", 33 | "stage3_param_persistence_threshold": "auto", 34 | "stage3_max_live_parameters": 1e9, 35 | "stage3_max_reuse_distance": 1e9, 36 | "stage3_gather_16bit_weights_on_model_save": true 37 | } 38 | } -------------------------------------------------------------------------------- /chisellm/dataset/completion/templates/instruction.j2: -------------------------------------------------------------------------------- 1 | # Request 2 | 3 | You are tasked with implementing a Chisel3 module according to the design specification provided. The module that needs to be implemented is marked with `// TODO: Implement the module logic here` in the context provided. 4 | 5 | Ensure your Chisel code fully implements the design specification and adheres to best practices. 6 | 7 | # Output 8 | 9 | Your final output should include the following sections: 10 | 11 | - Steps: The detailed steps to implement the functionality, corresponding to the design specification. 12 | - Implementation: Explain how to implement each steps in the previous section with syntactically correct Chisel code.. 13 | - Answer: The complete module implementation in a single code block. 14 | 15 | Every section is mandatory, omit any section will be considered as an incomplete answer. 16 | 17 | # Requirements 18 | 19 | - Your thinking process should be comprehensive and well-reasoned, avoid repetitive thinking, keep it concise and informative. 20 | - Your thinking process should not only focus on implementing functionality correct code, but also syntactically correct code. That requires you to think about how to properly use Chisel language features. 21 | - Follow the format and instructions provided in the output section. 22 | 23 | # Request 24 | 25 | {{ spec }} 26 | -------------------------------------------------------------------------------- /chisellm/train_config/ChiseLLM-32B.yaml: -------------------------------------------------------------------------------- 1 | ### wandb 2 | report_to: wandb 3 | run_name: ChiseLLM-32B 4 | 5 | ### model 6 | model_name_or_path: models/Qwen/Qwen2.5-Coder-32B-Instruct 7 | 8 | ### method 9 | stage: sft 10 | do_train: true 11 | finetuning_type: full 12 | 13 | ### dataset 14 | dataset_dir: datasets 15 | dataset: ChiseLLM-Completion,ChiseLLM-Decompile 16 | mix_strategy: interleave_under 17 | interleave_probs: 0.3,0.7 18 | template: qwen 19 | cutoff_len: 16384 20 | max_samples: 6000 21 | overwrite_cache: true 22 | preprocessing_num_workers: 32 23 | dataloader_persistent_workers: true 24 | dataloader_pin_memory: true 25 | dataloader_num_workers: 32 26 | 27 | ### output 28 | output_dir: output/ChiseLLM/ChiseLLM-32B 29 | logging_steps: 1 30 | save_steps: 1000 31 | plot_loss: true 32 | 33 | ### train 34 | per_device_train_batch_size: 1 35 | gradient_accumulation_steps: 2 36 | learning_rate: 1.0e-5 37 | num_train_epochs: 2.3 38 | lr_scheduler_type: cosine 39 | warmup_ratio: 0.05 40 | weight_decay: 0.0001 41 | bf16: true 42 | ddp_timeout: 180000000 43 | # overwrite_output_dir: true 44 | 45 | # speedup 46 | flash_attn: fa2 47 | 48 | # memory 49 | optim: paged_adamw_8bit 50 | gradient_checkpointing: true 51 | gradient_checkpointing_kwargs: 52 | use_reentrant: false 53 | deepspeed: config/ds/ds_z3_config.json 54 | sequence_parallel_size: 8 55 | sequence_parallel_mode: ulysses -------------------------------------------------------------------------------- /chisellm/utils/template.py: -------------------------------------------------------------------------------- 1 | import importlib.resources as res 2 | from functools import cache 3 | from pathlib import Path 4 | from types import ModuleType 5 | 6 | from jinja2 import BaseLoader, Environment, PackageLoader, Template 7 | 8 | 9 | @cache 10 | def load_template_env(module: ModuleType | None = None) -> Environment: 11 | if not module: 12 | return Environment(loader=BaseLoader()) 13 | 14 | loader = PackageLoader(module.__name__) 15 | return Environment( 16 | loader=loader, 17 | trim_blocks=True, 18 | ) 19 | 20 | 21 | def load_template(module: ModuleType, name: str, **kwargs) -> Template: 22 | """Load template from a module. 23 | 24 | Example: 25 | 26 | ```python 27 | import chisellm_utils.dataset as dataset_module 28 | # load a template named `template.j2` from `chisellm_utils.dataset.templates` directory 29 | template = load_template(dataset_module, "template") 30 | ``` 31 | 32 | Args: 33 | module (ModuleType): A module contains a subdirectory named `templates`. 34 | name (str): Template name without extension. e.g. `template.j2` -> `template` 35 | 36 | Returns: 37 | Template: A jinja2 template object. 38 | """ 39 | return load_template_env(module).get_template(f"{name}.j2") 40 | 41 | 42 | def load_text(module: ModuleType, path: Path) -> str: 43 | with res.as_file(res.files(module)) as module_path: 44 | return (module_path / path).read_text(encoding="utf-8") 45 | 46 | 47 | def load_template_text(module: ModuleType, name: str) -> str: 48 | if not (file_path := Path(name)).suffix: 49 | file_path = file_path.with_suffix(".j2") 50 | 51 | return load_text(module, Path("templates") / file_path) 52 | 53 | 54 | @cache 55 | def create_template(template: str) -> Template: 56 | return load_template_env().from_string(template) 57 | -------------------------------------------------------------------------------- /chisellm/dataset/completion/templates/chat_template.j2: -------------------------------------------------------------------------------- 1 | {%- if messages[0]['role'] == 'system' %} 2 | {{- '<|im_start|>system\n' + messages[0]['content'] + '<|im_end|>\n' }} 3 | {%- endif %} 4 | {%- for message in messages %} 5 | {%- if (message.role == "user") or (message.role == "system" and not loop.first) %} 6 | {{- '<|im_start|>' + message.role + '\n' + message.content + '<|im_end|>' + '\n' }} 7 | {%- elif message.role == "assistant" and not message.tool_calls %} 8 | {%- set content = message.content.split('')[-1].lstrip('\n') %} 9 | {{- '<|im_start|>' + message.role + '\n' + content + '<|im_end|>' + '\n' }} 10 | {%- elif message.role == "assistant" %} 11 | {%- set content = message.content.split('')[-1].lstrip('\n') %} 12 | {{- '<|im_start|>' + message.role }} 13 | {%- if message.content %} 14 | {{- '\n' + content }} 15 | {%- endif %} 16 | {%- for tool_call in message.tool_calls %} 17 | {%- if tool_call.function is defined %} 18 | {%- set tool_call = tool_call.function %} 19 | {%- endif %} 20 | {{- '\n\n{"name": "' }} 21 | {{- tool_call.name }} 22 | {{- '", "arguments": ' }} 23 | {{- tool_call.arguments | tojson }} 24 | {{- '}\n' }} 25 | {%- endfor %} 26 | {{- '<|im_end|>\n' }} 27 | {%- elif message.role == "tool" %} 28 | {%- if (loop.index0 == 0) or (messages[loop.index0 - 1].role != "tool") %} 29 | {{- '<|im_start|>user' }} 30 | {%- endif %} 31 | {{- '\n\n' }} 32 | {{- message.content }} 33 | {{- '\n' }} 34 | {%- if loop.last or (messages[loop.index0 + 1].role != "tool") %} 35 | {{- '<|im_end|>\n' }} 36 | {%- endif %} 37 | {%- endif %} 38 | {%- endfor %} 39 | {%- if add_generation_prompt %} 40 | {{- '<|im_start|>assistant\n' }}{#{ generation_prompt }#} 41 | {%- endif %} 42 | -------------------------------------------------------------------------------- /chisellm/eval/variation-generate.j2: -------------------------------------------------------------------------------- 1 | You are tasked with **decompiling the given Verilog module into equivalent Chisel3 module**. 2 | 3 | On the premise of ensuring syntax correctness and functional equivalence, you need to consider how to optimize and refactor the Chisel module to make a better **variability design**. 4 | 5 | Design variability refers to the adaptability of Chisel module design to changes in context, requirements, or constraints. The higher the variability, the lower the refactoring cost required for the module to adapt to different changes. 6 | 7 | To achieve a high variability design, you need to consider how to reasonably use Chisel language features to make parameterized, abstracted, and modular designs. 8 | 9 | # Requirements 10 | 11 | - All code must use Chisel 3 and Scala 2.13 syntax. 12 | - Module name and ports must strictly follow the specification, even if it will violate the Scala naming convention. 13 | - Code structure requirements: 14 | - All internal signals and modules need meaningful names. 15 | - Add comments to explain key functionality. 16 | - Avoid generating redundant logic. 17 | - Do not define any additional ports or signals (e.g. extra clock or reset signals) not specified in the design specification. 18 | - In Chisel module, unconnected wires are not allowed. Make sure all output IO signals are assigned under all conditions. 19 | - Prioritize correctness over complexity; avoid introducing complex design that could lead to implementation errors. 20 | 21 | # Output Format 22 | 23 | Your output must include a `class {{ top }}` and a `object {{ top }}` that contains a method `apply()` to create an instance of the module. 24 | 25 | - The arguments of `apply()` are class parameters of `class {{ top }}` (if any), not the input ports. 26 | - The parameters of `apply()` must be defined with default values, so that it can be called without any arguments. 27 | 28 | Your output code must be **in a Markdown code block with `{result}` identifier**, as shown below: 29 | 30 | ```scala {result} 31 | // ... other code if needed ... 32 | 33 | class {{ top }}(/* parameters */) extends Module { 34 | // ... module implementation ... 35 | } 36 | 37 | object {{ top }} { 38 | def apply(/* parameters */): {{ top }} = { 39 | new {{ top }}(/* parameters */) 40 | } 41 | } 42 | ``` 43 | 44 | # Request 45 | 46 | Verilog code: 47 | 48 | ```verilog 49 | {{ code }} 50 | ``` 51 | -------------------------------------------------------------------------------- /chisellm/dataset/decompile/pipeline.py: -------------------------------------------------------------------------------- 1 | import logging 2 | from functools import partial 3 | from pathlib import Path 4 | 5 | from distilabel.models import LLM 6 | from distilabel.pipeline import Pipeline 7 | from distilabel.steps import ( 8 | FormatTextGenerationSFT, 9 | KeepColumns, 10 | StepInput, 11 | StepOutput, 12 | step, 13 | ) 14 | from distilabel.steps.tasks import TextGeneration 15 | 16 | import dataset.decompile as decompile_module 17 | from chisellm.utils.template import load_template, load_template_text, load_text 18 | 19 | logger = logging.getLogger(__name__) 20 | 21 | cot_template_text = load_template_text(decompile_module, "cot") 22 | instruction_template = load_template(decompile_module, "instruction") 23 | 24 | tutorial = load_text(decompile_module, Path("templates") / "tutorial.md") 25 | # HACK: replace at prerender stage 26 | cot_template_text = cot_template_text.replace(r"{#{tutorial}#}", tutorial) 27 | 28 | 29 | def cot_generation(): 30 | return partial( 31 | TextGeneration, 32 | template=cot_template_text, 33 | columns=["source"], 34 | ) 35 | 36 | 37 | @step(inputs=["source"], outputs=["instruction"]) 38 | def instruction_formation(input: StepInput) -> StepOutput: 39 | for item in input: 40 | source = item["source"] 41 | item["instruction"] = instruction_template.render(source=source) 42 | 43 | yield input 44 | 45 | 46 | def load( 47 | llm: LLM, 48 | *, 49 | id_column: str = "id", 50 | source_column: str = "source", 51 | input_batch_size: int = 128, 52 | ) -> Pipeline: 53 | with Pipeline("chisellm-decompile") as pipeline: 54 | generate = cot_generation()( 55 | llm=llm, 56 | input_mappings={"source": source_column}, 57 | input_batch_size=input_batch_size, 58 | ) 59 | instruction_format = instruction_formation( 60 | input_mappings={"source": source_column}, 61 | input_batch_size=input_batch_size, 62 | ) 63 | sft_format = FormatTextGenerationSFT( 64 | input_batch_size=input_batch_size, 65 | ) 66 | keep = KeepColumns( 67 | input_mappings={ 68 | "id": id_column, 69 | }, 70 | columns=[ 71 | "id", 72 | "prompt", 73 | "generation", 74 | "prompt_id", 75 | "messages", 76 | ], 77 | input_batch_size=input_batch_size, 78 | ) 79 | 80 | _ = generate >> instruction_format >> sft_format >> keep 81 | 82 | return pipeline 83 | -------------------------------------------------------------------------------- /chisellm/dataset/completion/templates/cot.j2: -------------------------------------------------------------------------------- 1 | You are tasked with implementing a Chisel3 module according to the design specification provided. The module that needs to be implemented is marked with `// TODO: Implement the module logic here` in the context provided. 2 | 3 | Ensure your Chisel code fully implements the design specification and adheres to best practices. 4 | 5 | {%- if doc %} 6 | # Documentation 7 | 8 | Here are some relevant documentation that help you with your code implementation. 9 | 10 | - Refer to the documentation when implementing the code to ensure syntactic/semantic correctness and best practices. 11 | - Refer to the documentation throughout your thinking process. 12 | - Refer to the documentation in the output section to explain the right way to implement the functionality. 13 | - Every Chisel code implementation should be justified with carefully reflections and related documentation content (if necessary). 14 | 15 | ````markdown 16 | {{ doc }} 17 | ```` 18 | {%- endif %} 19 | 20 | # Output 21 | 22 | Your final output should include the following sections: 23 | 24 | - Steps: The detailed steps to implement the functionality, corresponding to the design specification. 25 | - Implementation: Explain how to implement each steps in the previous section with syntactically correct Chisel code. Use the documentation (if provided) to explain the right way to implement it. For example, if you are using a `Mux`, explain how to use it correctly and why. Integrate content from the documentation to explain the right way to use Chisel language features. 26 | - Answer: The complete module implementation in a single code block. 27 | 28 | Every section is mandatory, omit any section will be considered as an incomplete answer. 29 | 30 | # Requirements 31 | 32 | - Your thinking process should be comprehensive and well-reasoned, avoid repetitive thinking, keep it concise and informative. 33 | - Your thinking process should not only focus on implementing functionality correct code, but also syntactically correct code. That requires you to think about how to properly use Chisel language features. 34 | - Follow the format and instructions provided in the output section. 35 | 36 | # Request 37 | 38 | {{ spec }} 39 | 40 | {%- if code %} 41 | --- 42 | 43 | # Answer 44 | 45 | The following code is the correct implementation of the specification. Your final code should be consistent with this implementation. 46 | 47 | - Use the answer to guide your thinking process. 48 | - Use covert references to the answer during the thinking process, such as "I think that in the correct answer, it would be...". 49 | 50 | ```scala 51 | {{ code }} 52 | ``` 53 | {%- endif %} 54 | -------------------------------------------------------------------------------- /chisellm/dataset/completion/pipeline.py: -------------------------------------------------------------------------------- 1 | import logging 2 | from functools import partial 3 | 4 | from distilabel.models import LLM 5 | from distilabel.pipeline import Pipeline 6 | from distilabel.steps import ( 7 | FormatTextGenerationSFT, 8 | KeepColumns, 9 | StepInput, 10 | StepOutput, 11 | step, 12 | ) 13 | from distilabel.steps.tasks import TextGeneration 14 | 15 | import dataset.completion as design_module 16 | from chisellm.utils.template import load_template, load_template_text 17 | 18 | logger = logging.getLogger(__name__) 19 | 20 | cot_template_text = load_template_text(design_module, "cot") 21 | instruction_template = load_template(design_module, "instruction") 22 | 23 | 24 | def cot_generation(mappings: dict[str, str | None] = {}): 25 | input_mappings = {k: v for k, v in mappings.items() if v} 26 | columns = list(input_mappings.keys()) 27 | 28 | return partial( 29 | TextGeneration, 30 | template=cot_template_text, 31 | input_mappings=input_mappings, 32 | columns=columns, 33 | ) 34 | 35 | 36 | @step(inputs=["spec"], outputs=["instruction"]) 37 | def instruction_formation(input: StepInput) -> StepOutput: 38 | for item in input: 39 | spec = item["spec"] 40 | item["instruction"] = instruction_template.render(spec=spec) 41 | 42 | yield input 43 | 44 | 45 | def load( 46 | name: str, 47 | llm: LLM, 48 | *, 49 | id_column: str = "id", 50 | spec_column: str = "spec", 51 | code_column: str | None = None, 52 | doc_column: str | None = None, 53 | input_batch_size: int = 128, 54 | ): 55 | with Pipeline(f"chisellm-design-{name}") as pipeline: 56 | generate = cot_generation( 57 | { 58 | "spec": spec_column, 59 | "code": code_column, 60 | "doc": doc_column, 61 | } 62 | )( 63 | llm=llm, 64 | input_batch_size=input_batch_size, 65 | ) 66 | 67 | instruction_format = instruction_formation( 68 | input_mappings={ 69 | "spec": spec_column, 70 | }, 71 | input_batch_size=input_batch_size, 72 | ) 73 | sft_format = FormatTextGenerationSFT( 74 | input_batch_size=input_batch_size, 75 | ) 76 | keep = KeepColumns( 77 | input_mappings={ 78 | "id": id_column, 79 | }, 80 | columns=[ 81 | "id", 82 | "prompt", 83 | "generation", 84 | "prompt_id", 85 | "messages", 86 | ], 87 | input_batch_size=input_batch_size, 88 | use_cache=False, 89 | ) 90 | 91 | _ = generate >> instruction_format >> sft_format >> keep 92 | 93 | return pipeline 94 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ChiseLLM : Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development 2 | 3 | > This Logo is a joke. Do you get it?🤣 4 | 5 | ![introduction](assets/introduction.png) 6 | 7 | ChiseLLM is **a reasoning model optimized for the Chisel language**, designed to enhance agile hardware design capabilities. 8 | 9 | - [arxiv](https://arxiv.org/abs/2504.19144) 10 | 11 | ## Motivation 12 | 13 | - The demand for Domain-Specific Architecture (DSA) has driven the development of Agile Hardware Development Methodology (AHDM) 14 | - Chisel, as a Hardware Construction Language (HCL), provides high-level abstraction features, making it ideal for HCL-based agile development 15 | - While Large Language Models (LLMs) excel at code generation, they still face challenges with Chisel code generation, particularly regarding syntax correctness and design variability 16 | 17 | ## Highlights 18 | 19 | - **ChiseLLM Solution**: Comprises data processing and transformation, prompt-guided reasoning trace synthesis, and domain-adapted model training 20 | - **High-Quality Datasets**: Constructed from public RTL code resources and guided to adopt structured thinking patterns through prompt enhancement methods 21 | - **Significant Performance Improvements**: 22 | - ChiseLLM-7B and ChiseLLM-32B models improved syntax correctness by 18.85% and 26.32% respectively over base models 23 | - Design variability capability increased by 47.58% compared to baseline reasoning models 24 | 25 | ## Models and Datasets 26 | 27 | - [**ChiseLLM-7B Model**](https://huggingface.co/observerw/ChiseLLM-7B) 28 | - [**ChiseLLM-32B Model**](https://huggingface.co/observerw/ChiseLLM-32B) 29 | - [**ChiseLLM-Completion Dataset**](https://huggingface.co/datasets/observerw/ChiseLLM-Completion) 30 | - [**ChiseLLM-Decompile Dataset**](https://huggingface.co/datasets/observerw/ChiseLLM-Decompile) 31 | 32 | Please check [huggingface collections](https://huggingface.co/collections/observerw/chisellm-v10-67fa72af57953fa80bbccc4e) for more information. 33 | 34 | ## Project Structure 35 | 36 | ``` 37 | chisellm/ 38 | ├── dataset/ # Dataset-related code 39 | │ ├── completion/ # Code completion data processing pipeline 40 | │ │ ├── pipeline.py # distilabel pipeline for completion dataset 41 | │ │ └── templates/ # Code completion prompt templates 42 | │ └── decompile/ # Decompilation data processing pipeline 43 | │ ├── pipeline.py # distilabel pipeline for decompile dataset 44 | │ └── templates/ # Decompilation prompt templates 45 | ├── train_config/ # Training configurations 46 | │ ├── ChiseLLM-7B.yaml # 7B model training config 47 | │ ├── ChiseLLM-32B.yaml # 32B model training config 48 | │ └── ds/ # DeepSpeed configurations 49 | └── utils/ # Utility functions 50 | ``` 51 | ## Citation 52 | 53 | If you are interested in our work, please consider citing this, it would be greatly appreciated! 54 | 55 | ```bibtex 56 | @misc{wang2025chisellmunleashingpowerreasoning, 57 | title={ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development}, 58 | author={Bowei Wang and Jiaran Gao and Yelai Feng and Renzhi Chen and Shanshan Li and Lei Wang}, 59 | year={2025}, 60 | eprint={2504.19144}, 61 | archivePrefix={arXiv}, 62 | primaryClass={cs.AI}, 63 | url={https://arxiv.org/abs/2504.19144}, 64 | } 65 | ``` 66 | -------------------------------------------------------------------------------- /assets/logo.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /chisellm/dataset/decompile/templates/cot.j2: -------------------------------------------------------------------------------- 1 | You are tasked with **decompiling the given Verilog code into equivalent Chisel3 code**. Ensure your Chisel code is correct, efficient, and reusable. 2 | 3 | # Steps 4 | 5 | To make sure the final Chisel code is reusable and efficient, you are required to follow these steps to decompile the Verilog code: 6 | 7 | 1. Analyze the Verilog code, directly mapping it to Chisel code without any optimizations or refactoring. 8 | 2. Write a design specification (referred to as original design specification) of the Verilog code to completely describe its functionality, followed by several **design specification variations** (explained below). 9 | 3. Implement an optimized and refactored version of the Chisel code to **cover all variations of the specification**. 10 | 11 | # Design Specification Variation 12 | 13 | A design specification variation refers to a modified version of the original design specification where specific functional/structural requirements are changed. The purpose of the variation is to model changes in context, requirements or constraints that may occur in the real-world RTL design process. A RTL design with high variability can be adapted to different variations with minimal refactoring effort. 14 | 15 | For now, we only consider the following types of variations: 16 | 17 | - Configurable Variation (`configure`): A modified version where tunable attributes (e.g., data width, cache depth) are extracted as configurable parameters without altering core functionality or interfaces. Modular code refactoring of the original design is often required to support parameterization. 18 | - Structural Variation (`structure`): A modified version that adapts hardware architecture (e.g., pipeline stages, memory organization, FSM encoding schemes), impacting timing/area while preserving functional equivalence. High-level abstraction of the original design is often required to accommodate different implementations of the same behavioral model. 19 | - Functional Variation (`function`): A modified version that alters input-output behavior (e.g., protocol version support, exception handling mechanisms, algorithmic implementation), directly modifying the design's functional requirements. Generalization refactoring of the original design is often required to transforming core functionality that are not directly related to peripheral functionality or input/output behavior into a generalized logic. 20 | 21 | For each original specification, **you are required to provide a `configure` variation and one of the `structure` or `function` variations**. 22 | 23 | - Each variations should be a complete specification that contains all necessary information of the original specification, and can be solitary used to implement a design. 24 | - Variation should be a design specification, not a code implementation. 25 | - Variations should be clear, reasonable, and strictly related to the original design specification. 26 | - The variations should be different from each other and not overlap. 27 | 28 | # Optimization and Refactoring 29 | 30 | The final Chisel code should be an optimized and refactored version of the original version that can cover all variations of the specification. To achieve this, you should select proper Chisel language features to address the variations, e.g. using config case class to provide configurable parameters, using abstract classes to extract common functionality, etc. 31 | 32 | {#{ tutorial }#} 33 | {% include "tutorial.md" ignore missing %} 34 | 35 | # Output 36 | 37 | Your output must include the following content, each within a Markdown code block with id and/or group identifiers (replace `` with the actual type (`structure`/`function`) you select): 38 | 39 | ```scala {decompiled} 40 | // the direct mapping of the Verilog code to Chisel code 41 | ``` 42 | 43 | ```text {specification} 44 | // The original design specification of the Verilog code 45 | ``` 46 | 47 | ```text [variations] {configure} 48 | // The `configure` design specification variation 49 | ``` 50 | 51 | ```text [variations] {} 52 | // The `` design specification variation 53 | ``` 54 | 55 | ```scala {optimized} 56 | // The final optimized and refactored version of the Chisel3 code 57 | ``` 58 | 59 | # Requirements 60 | 61 | - Your thinking process should be comprehensive and well-reasoned, avoid repetitive thinking, keep it concise and informative. 62 | - Your thinking process should not only focus on implementing functionality correct code, but also syntactically correct code. That requires you to think about how to properly use Chisel language features. 63 | - Follow the format and instructions provided in the output section. 64 | 65 | # Extra Attention 66 | 67 | - When directly mapping to Chisel code, keep your thinking process simple, do not overthink. Focus on subsequent variations and optimizations. 68 | - For verilog module with single clock and reset, you can use the implicit clock and reset signal of the Chisel module for convenience. 69 | - For verilog features that are not directly supported in Chisel (e.g. negedge signal), you can use a similar feature or a simple workaround as a substitute, with proper comments explaining the workaround. 70 | 71 | # Request 72 | 73 | ```verilog 74 | {{ source }} 75 | ``` 76 | -------------------------------------------------------------------------------- /chisellm/eval/s2c.j2: -------------------------------------------------------------------------------- 1 | You are tasked with implementing a Chisel3 module according to the design specification provided. 2 | 3 | # Imports 4 | 5 | The following imports are already included, extra import statements are not allowed: 6 | 7 | ```scala 8 | import chisel3._ 9 | import chisel3.util._ 10 | ``` 11 | 12 | # Port Declaration 13 | 14 | You must define module ports using the `val io = FlatIO(new Bundle { /* ports */ })`. Any other ports defination method is not allowed and will be considered as an error. 15 | 16 | The ports you declared must strictly follow the specification, including the name and type. Extra ports or signals (such as extra clock or reset signals) not specified in the design specification will be considered as an error. 17 | 18 | # Module Declaration 19 | 20 | You must define the module and ports with the exact name as specified in the specification. **The module must extend `RawModule`** to avoid implicit clock and reset signal. 21 | 22 | For every sequential module (`RegInit`, `RegNext`, etc.) that requires clock and reset signal, **you must explicitly define their signal using`withClockAndReset`**, for example: 23 | 24 | ```scala 25 | class Comb extends RawModule { 26 | val io = FlatIO(new Bundle { 27 | val in = Input(UInt(8.W)) 28 | val out = Output(UInt(8.W)) 29 | }) 30 | // combinational logic 31 | } 32 | 33 | class Seq extends RawModule { 34 | val io = FlatIO(new Bundle { 35 | val clk = Input(Clock()) 36 | val rst = Input(Bool()) 37 | }) 38 | 39 | // use `withClockAndReset` to specify clock and reset signal for each sequential modules 40 | val reg = withClockAndReset(io.clk, io.rst) { RegInit(0.U) } 41 | } 42 | 43 | class MultiClockSeq extends RawModule { 44 | val io = FlatIO(new Bundle { 45 | val clk_a = Input(Clock()) 46 | val rst_a = Input(Bool()) 47 | 48 | val clk_b = Input(Clock()) 49 | val rst_b = Input(Bool()) 50 | }) 51 | 52 | // register that uses clk_a and rst_a 53 | val reg_a = withClockAndReset(io.clk_a, io.rst_a) { RegInit(0.U) } 54 | // register that uses clk_b and rst_b 55 | val reg_b = withClockAndReset(io.clk_b, io.rst_b) { RegInit(0.U) } 56 | } 57 | ``` 58 | 59 | # Async Reset 60 | 61 | For sequential module that requires an async reset signal, you must provide an async version of the reset signal with `rst.asAsyncReset`, for example: 62 | 63 | ```scala 64 | class Foo extends RawModule { 65 | val io = FlatIO(new Bundle { 66 | val clk = Input(Clock()) 67 | val rst = Input(Bool()) 68 | }) 69 | 70 | // define async reset signal with `.asAsyncReset` 71 | val arst = io.rst.asAsyncReset 72 | 73 | // provide async reset signal to the sequential module instead of the original reset signal 74 | val reg = withClockAndReset(io.clk, io.arst) { RegInit(0.U) } 75 | } 76 | ``` 77 | 78 | # Active-Low Signal 79 | 80 | For sequential module that requires an active-low clock and/or reset signal, you must provide an active-low version of the signal, for example: 81 | 82 | ```scala 83 | class Foo extends RawModule { 84 | val io = FlatIO(new Bundle { 85 | val clk = Input(Clock()) 86 | val rst = Input(Bool()) 87 | }) 88 | 89 | // define active-low clock signal, use `.asBool` then `.asClock` 90 | // ATTENTION: the bracket `()` is mandatory 91 | val clk_n = (!io.clk.asBool).asClock 92 | // define active-low async reset signal, use `.asAsyncReset` 93 | // ATTENTION: the bracket `()` is mandatory 94 | val arst_n = (!io.rst).asAsyncReset 95 | 96 | // provide active-low clock and reset signal to the sequential module instead of the original signals 97 | val reg = withClockAndReset(io.clk_n, io.arst_n) { RegInit(0.U) } 98 | } 99 | ``` 100 | 101 | # Output 102 | 103 | Your output must at least include a `class {{ top }}` that extends `RawModule`, and a `object {{ top }}` that contains a method `apply()` to create an instance of the module. 104 | 105 | - The arguments of `apply()` are class parameters of `class {{ top }}` (if any), not the input ports. 106 | - The parameters of `apply()` must be defined with default values, so that it can be called without any arguments. 107 | 108 | Your output code must be **in a Markdown code block with `{result}` identifier**, as shown below: 109 | 110 | ```scala {result} 111 | // ... other modules if needed... 112 | 113 | class {{ top }} extends RawModule { 114 | // ... your code here... 115 | } 116 | 117 | object {{ top }} { 118 | def apply( /* parameters */ ): {{ top }} = { 119 | new {{ top }}( /* parameters */ ) 120 | } 121 | } 122 | ``` 123 | 124 | # Requirements 125 | 126 | - All code must use Chisel 3 and Scala 2.13 syntax. 127 | - Module name and ports must strictly follow the specification, even if it will violate the Scala naming convention. 128 | - Code structure requirements: 129 | - All internal signals and modules need meaningful names. 130 | - Add comments to explain key functionality. 131 | - Avoid generating redundant logic. 132 | - Do not define any additional ports or signals (e.g. extra clock or reset signals) not specified in the design specification. 133 | - In Chisel module, unconnected wires are not allowed. Make sure all output IO signals are assigned under all conditions. 134 | 135 | # Request 136 | 137 | Design Specification: 138 | 139 | ```text 140 | {{ spec }} 141 | ``` 142 | -------------------------------------------------------------------------------- /chisellm/eval/d2c.j2: -------------------------------------------------------------------------------- 1 | You are tasked with **decompiling the given Verilog code into equivalent Chisel3 code**. You need to analyze the provided Verilog code and directly map it to Chisel code without any optimizations or refactoring. 2 | 3 | # Imports 4 | 5 | The following imports are already included, extra import statements are not allowed: 6 | 7 | ```scala 8 | import chisel3._ 9 | import chisel3.util._ 10 | ``` 11 | 12 | # Port Declaration 13 | 14 | You must define module ports using the `val io = FlatIO(new Bundle { /* ports */ })`. Any other ports defination method is not allowed and will be considered as an error. 15 | 16 | The ports you declared must strictly follow the specification, including the name and type. Extra ports or signals (such as extra clock or reset signals) not specified in the design specification will be considered as an error. 17 | 18 | # Module Declaration 19 | 20 | You must define the module and ports with the exact name as specified in the specification. **The module must extend `RawModule`** to avoid implicit clock and reset signal. 21 | 22 | For every sequential module (`RegInit`, `RegNext`, etc.) that requires clock and reset signal, **you must explicitly define their signal using`withClockAndReset`**, for example: 23 | 24 | ```scala 25 | class Comb extends RawModule { 26 | val io = FlatIO(new Bundle { 27 | val in = Input(UInt(8.W)) 28 | val out = Output(UInt(8.W)) 29 | }) 30 | // combinational logic 31 | } 32 | 33 | class Seq extends RawModule { 34 | val io = FlatIO(new Bundle { 35 | val clk = Input(Clock()) 36 | val rst = Input(Bool()) 37 | }) 38 | 39 | // use `withClockAndReset` to specify clock and reset signal for each sequential modules 40 | val reg = withClockAndReset(io.clk, io.rst) { RegInit(0.U) } 41 | } 42 | 43 | class MultiClockSeq extends RawModule { 44 | val io = FlatIO(new Bundle { 45 | val clk_a = Input(Clock()) 46 | val rst_a = Input(Bool()) 47 | 48 | val clk_b = Input(Clock()) 49 | val rst_b = Input(Bool()) 50 | }) 51 | 52 | // register that uses clk_a and rst_a 53 | val reg_a = withClockAndReset(io.clk_a, io.rst_a) { RegInit(0.U) } 54 | // register that uses clk_b and rst_b 55 | val reg_b = withClockAndReset(io.clk_b, io.rst_b) { RegInit(0.U) } 56 | } 57 | ``` 58 | 59 | # Async Reset 60 | 61 | For sequential module that requires an async reset signal, you must provide an async version of the reset signal with `rst.asAsyncReset`, for example: 62 | 63 | ```scala 64 | class Foo extends RawModule { 65 | val io = FlatIO(new Bundle { 66 | val clk = Input(Clock()) 67 | val rst = Input(Bool()) 68 | }) 69 | 70 | // define async reset signal with `.asAsyncReset` 71 | val arst = io.rst.asAsyncReset 72 | 73 | // provide async reset signal to the sequential module instead of the original reset signal 74 | val reg = withClockAndReset(io.clk, io.arst) { RegInit(0.U) } 75 | } 76 | ``` 77 | 78 | # Active-Low Signal 79 | 80 | For sequential module that requires an active-low clock and/or reset signal, you must provide an active-low version of the signal, for example: 81 | 82 | ```scala 83 | class Foo extends RawModule { 84 | val io = FlatIO(new Bundle { 85 | val clk = Input(Clock()) 86 | val rst = Input(Bool()) 87 | }) 88 | 89 | // define active-low clock signal, use `.asBool` then `.asClock` 90 | // ATTENTION: the bracket `()` is mandatory 91 | val clk_n = (!io.clk.asBool).asClock 92 | // define active-low async reset signal, use `.asAsyncReset` 93 | // ATTENTION: the bracket `()` is mandatory 94 | val arst_n = (!io.rst).asAsyncReset 95 | 96 | // provide active-low clock and reset signal to the sequential module instead of the original signals 97 | val reg = withClockAndReset(io.clk_n, io.arst_n) { RegInit(0.U) } 98 | } 99 | ``` 100 | 101 | # Output 102 | 103 | Your output must at least include a `class {{ top }}` that extends `RawModule`, and a `object {{ top }}` that contains a method `apply()` to create an instance of the module. 104 | 105 | - The arguments of `apply()` are class parameters of `class {{ top }}` (if any), not the input ports. 106 | - The parameters of `apply()` must be defined with default values, so that it can be called without any arguments. 107 | 108 | Your output code must be **in a Markdown code block with `{result}` identifier**, as shown below: 109 | 110 | ```scala {result} 111 | // ... other modules if needed... 112 | 113 | class {{ top }} extends RawModule { 114 | // ... your code here... 115 | } 116 | 117 | object {{ top }} { 118 | def apply( /* parameters */ ): {{ top }} = { 119 | new {{ top }}( /* parameters */ ) 120 | } 121 | } 122 | ``` 123 | 124 | Output that do not follow this output format will be considered invalid. 125 | 126 | # Requirements 127 | 128 | - All code must use Chisel 3 and Scala 2.13 syntax. 129 | - Module name and ports must strictly follow the (System)Verilog code provided, even if it will violate the Scala naming convention. 130 | - Code structure requirements: 131 | - All internal signals and modules need meaningful names. 132 | - Add comments to explain key functionality. 133 | - Avoid generating redundant logic. 134 | - Do not define any additional ports or signals (e.g. extra clock or reset signals) not specified in the problem description. 135 | - In chisel module, unconnected wires are not allowed. Make sure all output IO signals are assigned under all conditions. 136 | 137 | # Request 138 | 139 | You must give a final answer that meets the formatting requirements in strict accordance with the requirements, no extraneous thinking steps are allowed, and **any additional output content will be considered an error and severely penalized**. 140 | 141 | Original Verilog code: 142 | 143 | ```verilog 144 | {{ code }} 145 | ``` -------------------------------------------------------------------------------- /chisellm/dataset/decompile/templates/tutorial.md: -------------------------------------------------------------------------------- 1 | # Tutorial: Chisel Language Features for improving RTL Code Variability 2 | 3 | ## Parameterized and Configurable Modules/Bundles 4 | 5 | Chisel `Module` or `Bundle` is just a Scala class, and you can create parameterized modules/bundles by passing any type of parameters to the constructor. 6 | 7 | Example: Parameterized Adder 8 | 9 | ```scala 10 | // Parameterized adder module with width parameter 11 | class ParamAdder(n: Int) extends Module { 12 | // Define the IO bundle with configurable bit width 13 | val io = IO(new Bundle { 14 | val a = Input(UInt(n.W)) // Input signal with width 'n' 15 | val b = Input(UInt(n.W)) 16 | val c = Output(UInt(n.W)) 17 | }) 18 | 19 | io.c := io.a + io.b 20 | } 21 | 22 | val add8 = Module(new ParamAdder(8)) // 8-bit adder 23 | val add16 = Module(new ParamAdder(16)) // 16-bit adder 24 | ``` 25 | 26 | Or pass a case class to the module constructor as a configuration object. This is useful for encapsulating multiple parameters. 27 | 28 | Example: Case Class for Configuration 29 | 30 | ```scala 31 | // Define a case class to encapsulate configuration parameters 32 | case class Config(txDepth: Int, rxDepth: Int, width: Int) 33 | 34 | class MyModule(config: Config) extends Module { 35 | val io = IO(new Bundle { 36 | val data = Input(UInt(config.width.W)) // Input with configurable width 37 | val result = Output(UInt(config.width.W)) // Output with configurable width 38 | }) 39 | 40 | // Use config parameters in the design 41 | io.result := io.data + config.txDepth.U // Add 'txDepth' to the input data 42 | } 43 | ``` 44 | 45 | ## Lightweight Components with Functions 46 | 47 | Functions in Chisel can be used to create lightweight hardware components, as long as the return type is a Chisel `Data` type. 48 | 49 | Example: Adder Function 50 | 51 | ```scala 52 | // Define a reusable adder function 53 | def adder(x: UInt, y: UInt): UInt = { x + y } 54 | 55 | // Use the adder function to create two adders 56 | val sum1 = adder(a, b) // Adder for inputs 'a' and 'b' 57 | val sum2 = adder(c, d) // Adder for inputs 'c' and 'd' 58 | ``` 59 | 60 | ## Combinational Logic Generation 61 | 62 | Chisel allows you to generate combinational logic dynamically using Scala constructs. This is particularly useful for creating lookup tables or ROMs. 63 | 64 | Example: Square ROM 65 | 66 | ```scala 67 | val table = Wire(Vec(100, UInt(8.W))) // Create a vector of 100 elements, each 8 bits wide 68 | for(i <- 0 until 100) { 69 | // Initialize the table with the square of the index 70 | table(i) := (((i / 10) << 4) + i % 10).U 71 | } 72 | io.output := table(io.address) // Output the value at the given address by simply looking up the table 73 | ``` 74 | 75 | ## Type Parameters 76 | 77 | Chisel supports type parameters, allowing you to create functions/modules that have processing logic regardless of the data type processed. This is useful for creating generic components. 78 | 79 | Example: Multiplexer with Type Parameter 80 | 81 | ```scala 82 | // generic multiplexer 83 | def myMux[T <: Data](sel: Bool, tPath: T, fPath: T): T = { 84 | val ret = WireDefault(fPath) // Default to 'fPath' 85 | when (sel) { ret := tPath } // Select 'tPath' if 'sel' is true 86 | 87 | ret // Return the selected value 88 | } 89 | 90 | // Use the multiplexer with UInt types 91 | val resA = myMux(selA, 5.U, 10.U) // Select between 5 and 10 92 | // Use the multiplexer with Vec types 93 | val resB = myMux(selB, VecInit(1.U, 2.U), VecInit(3.U, 4.U)) // Select between two vectors 94 | ``` 95 | 96 | ## Optional Ports 97 | 98 | Chisel allows you to conditionally generate ports based on configuration parameters. 99 | 100 | Example: Register File with Optional Debug Port 101 | 102 | ```scala 103 | class RegisterFile(debug: Boolean) extends Module { 104 | val io = IO(new Bundle { 105 | // ... other ports omitted 106 | // Optional debug port 107 | val dbgPort = if (debug) Some(Output(Vec(32, UInt(32.W)))) else None 108 | }) 109 | 110 | // If debug is enabled, expose the entire register file 111 | if (debug) { io.dbgPort.get := regfile } 112 | } 113 | ``` 114 | 115 | ## Inheritance 116 | 117 | Chisel modules are Scala classes, so you can use inheritance to factor out common behavior into a base class. 118 | 119 | Example: Base Class for Ticker 120 | 121 | ```scala 122 | // Define an abstract base class for a ticker 123 | // We abstract "ticker" as a module that can output a tick signal at a certain frequency 124 | // So all subclasses of Ticker will have common behavior but different implementations 125 | abstract class Ticker(n: Int) extends Module { 126 | val io = IO(new Bundle { 127 | val tick = Output(Bool())) // Output tick signal 128 | }) 129 | } 130 | 131 | // Define a specific implementation of the ticker 132 | class UpTicker(n: Int) extends Ticker(n) { 133 | val cntReg = RegInit(0.U(8.W)) 134 | cntReg := cntReg + 1.U // Increment the counter 135 | io.tick := cntReg === (n-1).U // Generate a tick when the counter reaches 'n-1' 136 | } 137 | 138 | object Test { 139 | // Use type parameterization to accept any subclass of Ticker 140 | def testTicker[T <: Ticker](ticker: T): Unit = { 141 | // ... 142 | } 143 | } 144 | ``` 145 | 146 | ## Functional Programming 147 | 148 | Chisel supports functional programming, allowing you to create hardware using higher-order functions like `map`, `reduce`, and `reduceTree`. 149 | 150 | Example: Sum of Vector Using Functional Programming 151 | 152 | ```scala 153 | val vec = VecInit(1.U, 2.U, 3.U, 4.U) 154 | // Compute the sum of the vector using a tree of adders 155 | val sum = vec.reduceTree(_ + _) 156 | val min = vec.reduceTree((x, y) => Mux(x < y, x, y)) 157 | ``` 158 | 159 | Example: Arbitration Tree 160 | 161 | ```scala 162 | // Define an arbiter module with a configurable number of inputs 163 | class Arbiter[T <: Data](n: Int, gen: T) extends Module { 164 | val io = IO(new Bundle { 165 | val in = Flipped(Vec(n, new DecoupledIO(gen))) // Input vector of DecoupledIO 166 | val out = new DecoupledIO(gen) // Single output DecoupledIO 167 | }) 168 | 169 | // Use a reduction tree to arbitrate between inputs 170 | io.out <> io.in.reduceTree((a, b) => arbitrateSimp(a, b)) 171 | } 172 | ``` 173 | -------------------------------------------------------------------------------- /chisellm/eval/variation-rating.j2: -------------------------------------------------------------------------------- 1 | You are an experienced hardware engineer who can proficiently use the Chisel language for RTL design and have a deep understanding of Chisel language features. 2 | 3 | Your task is to evaluate the **design variability** of a Chisel module. 4 | 5 | # Concept Explanation 6 | 7 | Design variability refers to a Chisel module's ability to adapt to changes in context, requirements, or constraints. The higher the variability, the lower the refactoring cost needed to adapt the module to different changes. 8 | 9 | Refactoring cost refers to: The amount of refactoring work needed to adapt the module to changes. For example: 10 | - High refactoring cost: If a module has hardcoded pipeline stages, changing the number of stages requires rewriting the datapath. 11 | - Low refactoring cost: If a module uses parameterized stages, variants only need to modify parameter values. 12 | 13 | Based on refactoring cost, a refactoring cost score can be given, ranging from 1-10, where higher scores indicate lower refactoring costs: 14 | - 1-3 points: Need to rewrite core logic/interfaces (e.g., hardcoded structures need complete refactoring) 15 | - 4-6 points: Need medium-scale modifications (e.g., partially parameterized but requires new logic) 16 | - 7-9 points: Only needs parameter adjustments or local adaptations (e.g., fully parameterized design) 17 | - 10 points: Existing design can directly support (e.g., implemented through reserved interfaces/parameters) 18 | 19 | A **design specification variation** is a modified version of the original design specification where certain functional/structural requirements have changed. 20 | - The purpose of variations is to simulate changes in context, requirements, or constraints that may occur during actual RTL design. RTL designs with high variability can adapt to different variants with minimal refactoring work. 21 | 22 | # Example 23 | 24 | Here's an example to illustrate how to perform the evaluation. For simplicity, the example doesn't include design specifications and variations; but in actual evaluation, specifications and variants will be provided. 25 | 26 | Here is an implementation of an adder module: 27 | 28 | ```scala 29 | class Adder extends Module { 30 | val io = IO(new Bundle { 31 | val a = Input(UInt(32.W)) 32 | val b = Input(UInt(32.W)) 33 | val out = Output(UInt(32.W)) 34 | }) 35 | io.out := io.a + io.b 36 | } 37 | ``` 38 | 39 | This implementation doesn't have high variability: 40 | 41 | - To adapt to different data width variant requirements, all input/output ports and logic need to be modified, refactoring cost score is 3. 42 | - To adapt to different types of adders (like adders with carry), the entire module needs to be rewritten, refactoring cost score is 1. 43 | - To adapt to different operations (like subtractor), the module's operation logic needs to be rewritten, refactoring cost score is 4. 44 | - To adapt to different input/output types (like floating-point), both the module's input/output ports and operation logic need to be rewritten, refactoring cost score is 2. 45 | - Considering all evaluation results, the final score is \boxed{3}. 46 | 47 | Here is another implementation: 48 | 49 | ```scala 50 | abstract class BinaryOperation[T <: Data](gen: T) { 51 | def apply(a: T, b: T): T 52 | } 53 | 54 | class Addition[T <: Data](gen: T) extends BinaryOperation(gen) { 55 | def apply(a: T, b: T): T = a + b 56 | } 57 | 58 | class ParametricBinaryOperation[T <: Data]( 59 | width: Int, 60 | gen: => T, 61 | op: BinaryOperation[T] 62 | ) extends Module { 63 | val io = IO(new Bundle { 64 | val a = Input(gen) 65 | val b = Input(gen) 66 | val out = Output(gen) 67 | }) 68 | 69 | io.out := op(io.a, io.b) 70 | } 71 | 72 | class Adder(width: Int) extends ParametricBinaryOperation( 73 | width = width, 74 | gen = UInt(width.W), 75 | op = new Addition(UInt(width.W)) 76 | ) {} 77 | ``` 78 | 79 | This implementation has high variability: 80 | 81 | - To adapt to different data width variant requirements, only parameter values need to be modified, refactoring cost score is 10. 82 | - To adapt to different types of adders (like adders with carry), only need to implement new `BinaryOperation` class, refactoring cost score is 9. 83 | - To adapt to different operations (like subtractor), only need to implement new `BinaryOperation` class, refactoring cost score is 9. 84 | - To adapt to different input/output types (like floating-point), only need to pass different `gen` parameter, refactoring cost score is 10. 85 | - Considering all evaluation results, the final score is \boxed{10}. 86 | 87 | # Evaluation Steps 88 | 89 | You will be provided with a Chisel module code and its corresponding original design specification. To help you perform accurate and consistent evaluations, you will also be provided with several design specification variations. 90 | 91 | Your evaluation process should strictly follow these steps: 92 | 93 | 1. Analyze the module code, identifying important features such as parameterized design, interface abstraction design, and module coupling degree. These features will affect the module's variability and are therefore crucial to your evaluation results. 94 | 2. Understand the requirements of the original design specification and design specification variations. 95 | 3. For each design specification variation, evaluate **the refactoring cost needed to adapt the current module design to that variation** and give a score, following these steps: 96 | 1. Identify affected functionality/structure 97 | 2. Evaluate the scope of required code changes (local/global) 98 | 3. Give a 1-10 score based on refactoring cost level definitions 99 | 4. Synthesize all variation evaluation results to give an integer score from 1 to 10, representing the overall variability of the module design. 100 | 101 | # Output Format 102 | 103 | After comprehensive thinking and analysis, you need to output the final score in the format `\boxed{}`. Note that the score must be an integer between 1 and 10. 104 | 105 | # Important Notes 106 | 107 | - If the module has syntax errors or cannot meet the requirements of the original design specification, a score of 1 should be given directly. 108 | - When evaluating refactoring costs, don't base the evaluation on whether the module currently implements variation requirements, but rather on the changes that would need to be made to implement variant requirements under the current module design: 109 | - If the module happens to meet certain variant requirements (e.g., variant requires 32-bit data width, and module is hardcoded to 32-bit) but doesn't provide parameterized design, it shouldn't receive a high score. 110 | - If the module doesn't directly implement variant requirements but its design structure already considers variant requirement implementation (e.g., variant requires 32-bit data width, and module provides parameterized design), it can receive a high score. 111 | - "Hacking" behaviors should receive low scores. Hacking is defined as: implementing variant requirements through unreasonable means rather than through proper design structures. Such behaviors include but are not limited to: 112 | - Using a boolean parameter to decide whether to enable a specific implementation, or using a switch to decide whether to enable a feature, should not be considered as implementation of variant requirements. This approach doesn't truly consider module design variability, but rather embeds a specific implementation in the module design. This not only increases module design complexity but also reduces maintainability and extensibility. 113 | - Copy-pasting code segments and making minor modifications to support different scenarios. This not only leads to code duplication and redundancy but also reduces module readability and maintainability. Such practices should not be considered as implementation of variant requirements. 114 | - "Over-design" behaviors should also receive low scores. Over-design is defined as: introducing too much parameterization and abstraction levels in module design, leading to increased complexity and difficulty in understanding and maintaining. Such practices include but are not limited to: 115 | - Over-parameterization: introducing unnecessary configuration parameters, leading to increased module design complexity and difficulty in understanding and maintenance. 116 | - Over-abstraction: introducing too many abstraction levels that barely correspond to actual requirement changes that might be encountered. 117 | - Meaningless abstraction: abstracting fundamentally different functionalities into the same interface, where the interface definition has almost no practical significance. 118 | - For parameterized design, the rationality and usability of parameters need to be considered: 119 | - Effective parameterization: parameters should truly control architectural features (like data width, pipeline depth, memory size), and module internal logic should automatically adapt to parameter changes. 120 | - Ineffective parameterization: if parameters are only used as constants (like val DATA_WIDTH = 32), but internal logic doesn't dynamically adjust accordingly (e.g., hardcoded width-related operations still exist), it cannot be considered as high variability. 121 | 122 | # Request 123 | 124 | Chisel module code: 125 | 126 | ```scala 127 | {{ code }} 128 | ``` 129 | 130 | Original design specification: 131 | 132 | ```text 133 | {{ original }} 134 | ``` 135 | 136 | Design specification variations: 137 | 138 | {% for var in variations %} 139 | Variation `{{ var.id }}`: 140 | ```text 141 | {{ var.content }} 142 | ``` 143 | {% endfor %} 144 | -------------------------------------------------------------------------------- /uv.lock: -------------------------------------------------------------------------------- 1 | version = 1 2 | revision = 1 3 | requires-python = ">=3.13" 4 | 5 | [[package]] 6 | name = "aiohappyeyeballs" 7 | version = "2.6.1" 8 | source = { registry = "https://mirrors.tuna.tsinghua.edu.cn/pypi/web/simple" } 9 | sdist = { url = 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