├── dist ├── Assets │ └── mario │ │ └── common │ │ └── .keep ├── Cores │ └── obsidian.MarioBros │ │ ├── audio.json │ │ ├── icon.bin │ │ ├── variants.json │ │ ├── bitstream.rbf_r │ │ ├── video.json │ │ ├── input.json │ │ ├── data.json │ │ ├── core.json │ │ └── interact.json └── Platforms │ ├── _images │ └── mario.bin │ └── mario.json ├── src └── fpga │ ├── output_files │ ├── .gitignore │ ├── ap_core.rbf │ ├── ap_core.sof │ ├── bitstream.rbf_r │ ├── reverse_bits.exe │ ├── run.bat │ └── ap_core.jdi │ ├── core │ ├── mf_pllbase_sim.f │ ├── mf_pllbase_sim │ │ ├── cadence │ │ │ ├── hdl.var │ │ │ └── cds.lib │ │ └── synopsys │ │ │ └── vcsmx │ │ │ └── synopsys_sim.setup │ ├── rtl │ │ ├── t48 │ │ │ ├── README │ │ │ ├── clock_ctrl-c.vhd │ │ │ ├── timer-c.vhd │ │ │ ├── p1-c.vhd │ │ │ ├── p2-c.vhd │ │ │ ├── psw-c.vhd │ │ │ ├── int-c.vhd │ │ │ ├── pmem_ctrl-c.vhd │ │ │ ├── system │ │ │ │ ├── wb_master-c.vhd │ │ │ │ ├── generic_ram_ena-c.vhd │ │ │ │ ├── t48_rom-struct-c.vhd │ │ │ │ ├── t49_rom-struct-c.vhd │ │ │ │ ├── t8039-c.vhd │ │ │ │ ├── t8048-c.vhd │ │ │ │ ├── t8039_notri-c.vhd │ │ │ │ ├── t8048_notri-c.vhd │ │ │ │ ├── t8050_wb-c.vhd │ │ │ │ ├── t48_rom-e.vhd │ │ │ │ ├── t49_rom-e.vhd │ │ │ │ ├── t48_rom-struct-a.vhd │ │ │ │ ├── t49_rom-struct-a.vhd │ │ │ │ └── generic_ram_ena.vhd │ │ │ ├── db_bus-c.vhd │ │ │ ├── bus_mux-c.vhd │ │ │ ├── opc_table-c.vhd │ │ │ ├── alu-c.vhd │ │ │ ├── dmem_ctrl-c.vhd │ │ │ ├── cond_branch-c.vhd │ │ │ ├── t48_tb_pack-p.vhd │ │ │ ├── opc_decoder-c.vhd │ │ │ ├── decoder-c.vhd │ │ │ ├── pmem_ctrl_pack-p.vhd │ │ │ ├── dmem_ctrl_pack-p.vhd │ │ │ ├── cond_branch_pack-p.vhd │ │ │ ├── alu_pack-p.vhd │ │ │ ├── t48_core-c.vhd │ │ │ ├── T48.qip │ │ │ ├── t48_pack-p.vhd │ │ │ ├── syn_ram-e.vhd │ │ │ ├── decoder_pack-p.vhd │ │ │ ├── t48_core_comp_pack-p.vhd │ │ │ ├── bus_mux.vhd │ │ │ ├── p1.vhd │ │ │ └── db_bus.vhd │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ └── pll_0002.v │ │ ├── T80 │ │ │ ├── T80.qip │ │ │ ├── README │ │ │ ├── Z80.vhd │ │ │ ├── T80_Reg.vhd │ │ │ ├── T80sed.vhd │ │ │ └── T80s.vhd │ │ ├── mario_sound_mixer.v │ │ ├── mario_dma.v │ │ ├── dpram.vhd │ │ ├── mario_col_pal.v │ │ ├── mario_sound.v │ │ ├── mario_input.v │ │ ├── mario_logic.v │ │ ├── m58715ip.v │ │ ├── mario_hv_generator.v │ │ ├── mario_sound_analog.v │ │ ├── mario_wav_sound.v │ │ ├── pause.v │ │ ├── mario_sound_digital.v │ │ ├── mario_video.v │ │ ├── dkong3_sub.v │ │ ├── mario_iir_filter.v │ │ └── mario_bram.v │ ├── mf_pllbase.spd │ ├── mf_pllbase │ │ ├── mf_pllbase_0002.qip │ │ └── mf_pllbase_0002.v │ ├── pin_ddio_clk.qip │ ├── pin_ddio_clk.ppf │ ├── mf_pllbase.sip │ ├── core_constraints.sdc │ ├── mf_pllbase.ppf │ ├── sync_fifo.sv │ ├── pin_ddio_clk.v │ ├── mf_pllbase.bsf │ └── sound_i2s.sv │ ├── apf │ ├── build_id.mif │ ├── mf_datatable.qip │ ├── mf_ddio_bidir_12.qip │ ├── apf_constraints.sdc │ ├── apf.qip │ ├── mf_ddio_bidir_12.ppf │ ├── mf_ddio_bidir_12.v │ └── common.v │ ├── .gitignore │ └── ap_core.qpf └── README.md /dist/Assets/mario/common/.keep: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/fpga/output_files/.gitignore: -------------------------------------------------------------------------------- 1 | !*.sof 2 | !*.rbf -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim.f: -------------------------------------------------------------------------------- 1 | mf_pllbase_sim/mf_pllbase.vo 2 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /dist/Cores/obsidian.MarioBros/audio.json: -------------------------------------------------------------------------------- 1 | { 2 | "audio": { 3 | "magic": "APF_VER_1" 4 | } 5 | } -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/obsidian-dot-dev/openFPGA-MarioBros/HEAD/src/fpga/core/rtl/t48/README -------------------------------------------------------------------------------- /dist/Platforms/_images/mario.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/obsidian-dot-dev/openFPGA-MarioBros/HEAD/dist/Platforms/_images/mario.bin -------------------------------------------------------------------------------- /src/fpga/output_files/ap_core.rbf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/obsidian-dot-dev/openFPGA-MarioBros/HEAD/src/fpga/output_files/ap_core.rbf -------------------------------------------------------------------------------- /src/fpga/output_files/ap_core.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/obsidian-dot-dev/openFPGA-MarioBros/HEAD/src/fpga/output_files/ap_core.sof -------------------------------------------------------------------------------- /dist/Cores/obsidian.MarioBros/icon.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/obsidian-dot-dev/openFPGA-MarioBros/HEAD/dist/Cores/obsidian.MarioBros/icon.bin -------------------------------------------------------------------------------- /src/fpga/output_files/bitstream.rbf_r: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/obsidian-dot-dev/openFPGA-MarioBros/HEAD/src/fpga/output_files/bitstream.rbf_r -------------------------------------------------------------------------------- /src/fpga/output_files/reverse_bits.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/obsidian-dot-dev/openFPGA-MarioBros/HEAD/src/fpga/output_files/reverse_bits.exe -------------------------------------------------------------------------------- /dist/Cores/obsidian.MarioBros/variants.json: -------------------------------------------------------------------------------- 1 | { 2 | "variants": { 3 | "magic": "APF_VER_1", 4 | "variant_list": [] 5 | } 6 | } -------------------------------------------------------------------------------- /dist/Cores/obsidian.MarioBros/bitstream.rbf_r: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/obsidian-dot-dev/openFPGA-MarioBros/HEAD/dist/Cores/obsidian.MarioBros/bitstream.rbf_r -------------------------------------------------------------------------------- /dist/Platforms/mario.json: -------------------------------------------------------------------------------- 1 | { 2 | "platform": { 3 | "category": "Arcade", 4 | "name": "Mario Bros", 5 | "year": 1983, 6 | "manufacturer": "Nintendo" 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /src/fpga/output_files/run.bat: -------------------------------------------------------------------------------- 1 | reverse_bits.exe ap_core.rbf bitstream.rbf_r 2 | copy /y bitstream.rbf_r "E:\Cores\obsidian.MarioBros\bitstream.rbf_r" 3 | copy /y bitstream.rbf_r "..\..\..\dist\Cores\obsidian.MarioBros\bitstream.rbf_r" 4 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/fpga/output_files/ap_core.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/fpga/apf/build_id.mif: -------------------------------------------------------------------------------- 1 | -- Build ID Memory Initialization File 2 | -- 3 | 4 | DEPTH = 256; 5 | WIDTH = 32; 6 | ADDRESS_RADIX = HEX; 7 | DATA_RADIX = HEX; 8 | 9 | CONTENT 10 | BEGIN 11 | 12 | 0E0 : 20240302; 13 | 0E1 : 00203204; 14 | 0E2 : e1049728; 15 | 16 | END; 17 | -------------------------------------------------------------------------------- /src/fpga/apf/mf_datatable.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "21.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_datatable.v"] 5 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /dist/Cores/obsidian.MarioBros/video.json: -------------------------------------------------------------------------------- 1 | { 2 | "video": { 3 | "magic": "APF_VER_1", 4 | "scaler_modes": [ 5 | { 6 | "width": 256, 7 | "height": 224, 8 | "aspect_w": 8, 9 | "aspect_h": 7, 10 | "rotation": 0, 11 | "mirror": 0 12 | } 13 | ] 14 | } 15 | } -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase/mf_pllbase_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET OFF -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /src/fpga/apf/mf_ddio_bidir_12.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" 2 | set_global_assignment -name IP_TOOL_VERSION "23.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.ppf"] 6 | -------------------------------------------------------------------------------- /src/fpga/.gitignore: -------------------------------------------------------------------------------- 1 | */db/ 2 | */incremental_db/ 3 | */simulation/ 4 | */greybox_tmp/ 5 | incremental_db/ 6 | db/ 7 | PLLJ_PLLSPE_INFO.txt 8 | c5_pin_model_dump.txt 9 | cr_ie_info.json 10 | *.pin 11 | *.pof 12 | *.ptf.* 13 | *.qar 14 | *.qarlog 15 | *.qws 16 | *.rpt 17 | *.smsg 18 | *.sof 19 | *.sopc_builder 20 | *.summary 21 | *.txt 22 | *.bak 23 | *.cmp 24 | *.done 25 | *.xml 26 | *.sld 27 | *.cdf 28 | 29 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/clock_ctrl-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: clock_ctrl-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 4 | -- 5 | -- The clock control unit. 6 | -- 7 | ------------------------------------------------------------------------------- 8 | 9 | configuration t48_clock_ctrl_rtl_c0 of t48_clock_ctrl is 10 | 11 | for rtl 12 | end for; 13 | 14 | end t48_clock_ctrl_rtl_c0; 15 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/timer-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Timer/Counter unit. 4 | -- 5 | -- $Id: timer-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | configuration t48_timer_rtl_c0 of t48_timer is 12 | 13 | for rtl 14 | end for; 15 | 16 | end t48_timer_rtl_c0; 17 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/p1-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Port 1 unit. 4 | -- Implements the Port 1 logic. 5 | -- 6 | -- $Id: p1-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- All rights reserved 9 | -- 10 | ------------------------------------------------------------------------------- 11 | 12 | configuration t48_p1_rtl_c0 of t48_p1 is 13 | 14 | for rtl 15 | end for; 16 | 17 | end t48_p1_rtl_c0; 18 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/p2-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Port 2 unit. 4 | -- Implements the Port 2 logic. 5 | -- 6 | -- $Id: p2-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- All rights reserved 9 | -- 10 | ------------------------------------------------------------------------------- 11 | 12 | configuration t48_p2_rtl_c0 of t48_p2 is 13 | 14 | for rtl 15 | end for; 16 | 17 | end t48_p2_rtl_c0; 18 | -------------------------------------------------------------------------------- /dist/Cores/obsidian.MarioBros/input.json: -------------------------------------------------------------------------------- 1 | { 2 | "input": { 3 | "magic": "APF_VER_1", 4 | "controllers": [ 5 | { 6 | "type": "default", 7 | "mappings": [ 8 | { 9 | "id": 0, 10 | "name": "Jump", 11 | "key": "pad_btn_a" 12 | } 13 | ] 14 | } 15 | ] 16 | } 17 | } 18 | -------------------------------------------------------------------------------- /src/fpga/core/pin_ddio_clk.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pin_ddio_clk.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pin_ddio_clk_inst.v"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pin_ddio_clk.ppf"] 7 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/psw-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Program Status Word (PSW). 4 | -- Implements the PSW with its special bits. 5 | -- 6 | -- $Id: psw-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- All rights reserved 9 | -- 10 | ------------------------------------------------------------------------------- 11 | 12 | configuration t48_psw_rtl_c0 of t48_psw is 13 | 14 | for rtl 15 | end for; 16 | 17 | end t48_psw_rtl_c0; 18 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/int-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Interrupt Controller. 4 | -- It collects the interrupt sources and notifies the decoder. 5 | -- 6 | -- $Id: int-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- All rights reserved 9 | -- 10 | ------------------------------------------------------------------------------- 11 | 12 | configuration t48_int_rtl_c0 of t48_int is 13 | 14 | for rtl 15 | end for; 16 | 17 | end t48_int_rtl_c0; 18 | -------------------------------------------------------------------------------- /src/fpga/core/pin_ddio_clk.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_VERSION "23.1" 3 | set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_mf_pllbase" -name SPD_FILE [file join $::quartus(sip_path) "mf_pllbase.spd"] 5 | 6 | set_global_assignment -library "lib_mf_pllbase" -name MISC_FILE [file join $::quartus(sip_path) "mf_pllbase_sim/mf_pllbase.vo"] 7 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/pmem_ctrl-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Program Memory control unit. 4 | -- All operations related to the Program Memory are managed here. 5 | -- 6 | -- $Id: pmem_ctrl-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- All rights reserved 9 | -- 10 | ------------------------------------------------------------------------------- 11 | 12 | configuration t48_pmem_ctrl_rtl_c0 of t48_pmem_ctrl is 13 | 14 | for rtl 15 | end for; 16 | 17 | end t48_pmem_ctrl_rtl_c0; 18 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/wb_master-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Wishbone master module. 4 | -- 5 | -- $Id: wb_master-c.vhd,v 1.2 2005/06/11 10:16:05 arniml Exp $ 6 | -- 7 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t48_wb_master_rtl_c0 of t48_wb_master is 14 | 15 | for rtl 16 | end for; 17 | 18 | end t48_wb_master_rtl_c0; 19 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/db_bus-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The BUS unit. 4 | -- Implements the BUS port logic. 5 | -- 6 | -- $Id: db_bus-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t48_db_bus_rtl_c0 of t48_db_bus is 15 | 16 | for rtl 17 | end for; 18 | 19 | end t48_db_bus_rtl_c0; 20 | -------------------------------------------------------------------------------- /src/fpga/core/core_constraints.sdc: -------------------------------------------------------------------------------- 1 | # 2 | # user core constraints 3 | # 4 | # put your clock groups in here as well as any net assignments 5 | # 6 | 7 | set_clock_groups -asynchronous \ 8 | -group { bridge_spiclk } \ 9 | -group { clk_74a } \ 10 | -group { clk_74b } \ 11 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ 12 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ 13 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } 14 | 15 | derive_clock_uncertainty -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/bus_mux-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The T48 Bus Connector. 4 | -- Multiplexes all drivers of the T48 bus. 5 | -- 6 | -- $Id: bus_mux-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t48_bus_mux_rtl_c0 of t48_bus_mux is 15 | 16 | for rtl 17 | end for; 18 | 19 | end t48_bus_mux_rtl_c0; 20 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/opc_table-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Opcode Decoder Table. 4 | -- Decodes the given opcode to instruction mnemonics. 5 | -- Also derives the multicycle information. 6 | -- 7 | -- $Id: opc_table-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t48_opc_table_rtl_c0 of t48_opc_table is 14 | 15 | for rtl 16 | end for; 17 | 18 | end t48_opc_table_rtl_c0; 19 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/generic_ram_ena-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- Parametrizable, generic RAM with enable. 4 | -- 5 | -- $Id: generic_ram_ena-c.vhd,v 1.1.1.1 2006/11/25 22:15:41 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration generic_ram_ena_rtl_c0 of generic_ram_ena is 14 | 15 | for rtl 16 | end for; 17 | 18 | end generic_ram_ena_rtl_c0; 19 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/alu-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Arithmetic Logic Unit (ALU). 4 | -- It contains the ALU core plus the Accumulator and the Temp Reg. 5 | -- 6 | -- $Id: alu-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t48_alu_rtl_c0 of t48_alu is 15 | 16 | for rtl 17 | end for; 18 | 19 | end t48_alu_rtl_c0; 20 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/dmem_ctrl-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Data Memory control unit. 4 | -- All accesses to the Data Memory are managed here. 5 | -- 6 | -- $Id: dmem_ctrl-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t48_dmem_ctrl_rtl_c0 of t48_dmem_ctrl is 15 | 16 | for rtl 17 | end for; 18 | 19 | end t48_dmem_ctrl_rtl_c0; 20 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.ppf: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/fpga/apf/apf_constraints.sdc: -------------------------------------------------------------------------------- 1 | # 2 | # APF constraints 3 | # Do not edit this file. 4 | # 5 | # Add your own constraints in the \core_constraints.sdc in the core directory, which will also be loaded. 6 | 7 | create_clock -name clk_74a -period 13.468 [get_ports clk_74a] 8 | create_clock -name clk_74b -period 13.468 [get_ports clk_74b] 9 | create_clock -name bridge_spiclk -period 13.468 [get_ports bridge_spiclk] 10 | 11 | # autogenerate PLL clock names for use down below 12 | derive_pll_clocks 13 | 14 | 15 | # io constraints go here 16 | # 17 | 18 | 19 | # load in user constraints 20 | read_sdc "core/core_constraints.sdc" -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/cond_branch-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Conditional Branch Logic unit. 4 | -- Decisions whether to take a jump or not are made here. 5 | -- 6 | -- $Id: cond_branch-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t48_cond_branch_rtl_c0 of t48_cond_branch is 15 | 16 | for rtl 17 | end for; 18 | 19 | end t48_cond_branch_rtl_c0; 20 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t48_rom-struct-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8x48 ROM 4 | -- 5 | -- $Id: t48_rom-struct-c.vhd,v 1.1.1.1 2006/11/26 10:07:52 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t48_rom_struct_c0 of t48_rom is 14 | 15 | for struct 16 | 17 | for rom_b: rom_t48 18 | use configuration work.rom_t48_rtl_c0; 19 | end for; 20 | 21 | end for; 22 | 23 | end t48_rom_struct_c0; 24 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t49_rom-struct-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8x49 ROM 4 | -- 5 | -- $Id: t49_rom-struct-c.vhd,v 1.1.1.1 2006/11/26 10:07:52 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t49_rom_struct_c0 of t49_rom is 14 | 15 | for struct 16 | 17 | for rom_b: rom_t49 18 | use configuration work.rom_t49_rtl_c0; 19 | end for; 20 | 21 | end for; 22 | 23 | end t49_rom_struct_c0; 24 | -------------------------------------------------------------------------------- /src/fpga/apf/apf.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "apf_top.v"] 2 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "common.v"] 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_bridge_peripheral.v"] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_pad_controller.v"] 5 | set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) "apf_constraints.sdc"] 6 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.qip"] 7 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_datatable.qip"] 8 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t8039-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8039 Microcontroller System 4 | -- 5 | -- $Id: t8039-c.vhd,v 1.2 2004/12/03 19:43:12 arniml Exp $ 6 | -- 7 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t8039_struct_c0 of t8039 is 14 | 15 | for struct 16 | 17 | for t8039_notri_b : t8039_notri 18 | use configuration work.t8039_notri_struct_c0; 19 | end for; 20 | 21 | end for; 22 | 23 | end t8039_struct_c0; 24 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t8048-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8048 Microcontroller System 4 | -- 5 | -- $Id: t8048-c.vhd,v 1.2 2004/12/01 23:09:47 arniml Exp $ 6 | -- 7 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t8048_struct_c0 of t8048 is 14 | 15 | for struct 16 | 17 | for t8048_notri_b : t8048_notri 18 | use configuration work.t8048_notri_struct_c0; 19 | end for; 20 | 21 | end for; 22 | 23 | end t8048_struct_c0; 24 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/t48_tb_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: t48_tb_pack-p.vhd,v 1.2 2004/04/14 20:53:54 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | library ieee; 12 | use ieee.std_logic_1164.all; 13 | 14 | package t48_tb_pack is 15 | 16 | -- Instruction strobe visibility 17 | signal tb_istrobe_s : std_logic; 18 | 19 | -- Accumulator visibilty 20 | signal tb_accu_s : std_logic_vector(7 downto 0); 21 | 22 | end t48_tb_pack; 23 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/opc_decoder-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Opcode Decoder. 4 | -- Derives instruction mnemonics and multicycle information 5 | -- using the OPC table unit. 6 | -- 7 | -- $Id: opc_decoder-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t48_opc_decoder_rtl_c0 of t48_opc_decoder is 14 | 15 | for rtl 16 | 17 | for opc_table_b: t48_opc_table 18 | use configuration work.t48_opc_table_rtl_c0; 19 | end for; 20 | 21 | end for; 22 | 23 | end t48_opc_decoder_rtl_c0; 24 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | 2 | WORK > DEFAULT 3 | DEFAULT: ./libraries/work/ 4 | work: ./libraries/work/ 5 | altera_ver: ./libraries/altera_ver/ 6 | lpm_ver: ./libraries/lpm_ver/ 7 | sgate_ver: ./libraries/sgate_ver/ 8 | altera_mf_ver: ./libraries/altera_mf_ver/ 9 | altera_lnsim_ver: ./libraries/altera_lnsim_ver/ 10 | cyclonev_ver: ./libraries/cyclonev_ver/ 11 | cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/ 12 | cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/ 13 | LIBRARY_SCAN = TRUE 14 | -------------------------------------------------------------------------------- /dist/Cores/obsidian.MarioBros/data.json: -------------------------------------------------------------------------------- 1 | { 2 | "data": { 3 | "magic": "APF_VER_1", 4 | "data_slots": [ 5 | { 6 | "id": 0, 7 | "name": "ROM", 8 | "required": true, 9 | "parameters": 0, 10 | "filename": "mario.rom", 11 | "address": "0x10000000" 12 | }, 13 | { 14 | "id": 10, 15 | "name": "HISCORE", 16 | "required": false, 17 | "nonvolatile": true, 18 | "parameters": "0x84", 19 | "extensions": ["sav"], 20 | "address": "0x20000000" 21 | } 22 | ] 23 | } 24 | } -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/decoder-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Decoder unit. 4 | -- It decodes the instruction opcodes and executes them. 5 | -- 6 | -- $Id: decoder-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t48_decoder_rtl_c0 of t48_decoder is 15 | 16 | for rtl 17 | 18 | for opc_decoder_b: t48_opc_decoder 19 | use configuration work.t48_opc_decoder_rtl_c0; 20 | end for; 21 | 22 | for int_b: t48_int 23 | use configuration work.t48_int_rtl_c0; 24 | end for; 25 | 26 | end for; 27 | 28 | end t48_decoder_rtl_c0; 29 | -------------------------------------------------------------------------------- /src/fpga/apf/mf_ddio_bidir_12.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t8039_notri-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8039 Microcontroller System 4 | -- 8039 toplevel without tri-states 5 | -- 6 | -- $Id: t8039_notri-c.vhd,v 1.2 2006/06/21 01:02:35 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t8039_notri_struct_c0 of t8039_notri is 15 | 16 | for struct 17 | 18 | for ram_128_b : generic_ram_ena 19 | use configuration work.generic_ram_ena_rtl_c0; 20 | end for; 21 | 22 | for t48_core_b : t48_core 23 | use configuration work.t48_core_struct_c0; 24 | end for; 25 | 26 | end for; 27 | 28 | end t8039_notri_struct_c0; 29 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t8048_notri-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8048 Microcontroller System 4 | -- 5 | -- $Id: t8048_notri-c.vhd,v 1.2 2006/06/21 01:02:16 arniml Exp $ 6 | -- 7 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t8048_notri_struct_c0 of t8048_notri is 14 | 15 | for struct 16 | 17 | for rom_1k_b : t48_rom 18 | use configuration work.t48_rom_lpm_c0; 19 | end for; 20 | 21 | for ram_64_b : generic_ram_ena 22 | use configuration work.generic_ram_ena_rtl_c0; 23 | end for; 24 | 25 | for t48_core_b : t48_core 26 | use configuration work.t48_core_struct_c0; 27 | end for; 28 | 29 | end for; 30 | 31 | end t8048_notri_struct_c0; 32 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t8050_wb-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8048 Microcontroller System 4 | -- 5 | -- $Id: t8050_wb-c.vhd,v 1.2 2005/06/11 10:19:14 arniml Exp $ 6 | -- 7 | -- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t8050_wb_struct_c0 of t8050_wb is 14 | 15 | for struct 16 | 17 | for rom_4k_b : syn_rom 18 | use configuration work.syn_rom_lpm_c0; 19 | end for; 20 | 21 | for ram_256_b : syn_ram 22 | use configuration work.syn_ram_lpm_c0; 23 | end for; 24 | 25 | for wb_master_b : t48_wb_master 26 | use configuration work.t48_wb_master_rtl_c0; 27 | end for; 28 | 29 | for t48_core_b : t48_core 30 | use configuration work.t48_core_struct_c0; 31 | end for; 32 | 33 | end for; 34 | 35 | end t8050_wb_struct_c0; 36 | -------------------------------------------------------------------------------- /dist/Cores/obsidian.MarioBros/core.json: -------------------------------------------------------------------------------- 1 | { 2 | "core": { 3 | "magic": "APF_VER_1", 4 | "metadata": { 5 | "platform_ids": ["mario"], 6 | "shortname": "MarioBros", 7 | "description": "Mario Bros. released in 1983.", 8 | "author": "obsidian", 9 | "url": "https://github.com/obsidian-dot-dev/openFPGA-MarioBros", 10 | "version": "0.9.4", 11 | "date_release": "2024-03-02" 12 | }, 13 | "framework": { 14 | "target_product": "Analogue Pocket", 15 | "version_required": "1.1", 16 | "sleep_supported": false, 17 | "dock": { 18 | "supported": true, 19 | "analog_output": false 20 | }, 21 | "hardware": { 22 | "link_port": false, 23 | "cartridge_adapter": -1 24 | } 25 | }, 26 | "cores": [ 27 | { 28 | "name": "default", 29 | "id": 0, 30 | "filename": "bitstream.rbf_r" 31 | } 32 | ] 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/T80/T80.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) GBse.vhd ] 2 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ] 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ] 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80se.vhd ] 5 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80a.vhd ] 6 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80as.vhd ] 7 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80sed.vhd ] 8 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T8080se.vhd ] 9 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ] 10 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ] 11 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ] 12 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ] 13 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Pack.vhd ] -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_sound_mixer.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | // Mario Bros Arcade 3 | // 4 | // Author: gaz68 (https://github.com/gaz68) June 2020 5 | // 6 | // Sound mixer. 7 | // Mixes the analogue sounds (samples) with the digital 8 | // sound produced by the M58715 chip. 9 | //---------------------------------------------------------------------------- 10 | 11 | module mario_sound_mixer 12 | ( 13 | input I_CLK_48M, 14 | input [15:0]I_SND1,I_SND2,I_SND3,I_SND4, 15 | output signed [15:0]O_SND_DAT 16 | ); 17 | 18 | wire signed [18:0]sound_mix = {{3{I_SND1[15]}}, I_SND1} + 19 | {{3{I_SND2[15]}}, I_SND2} + 20 | {{3{I_SND3[15]}}, I_SND3} + 21 | {{3{I_SND4[15]}}, I_SND4}; 22 | 23 | reg signed [15:0]dac_di; 24 | 25 | always@(posedge I_CLK_48M) 26 | begin 27 | if(sound_mix >= 19'sh07FFF) 28 | dac_di <= 16'sh7FFF; 29 | else if(sound_mix <= -19'sh08000) 30 | dac_di <= -16'sh8000; 31 | else 32 | dac_di <= sound_mix[15:0]; 33 | end 34 | 35 | 36 | assign O_SND_DAT = dac_di; 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/pmem_ctrl_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: pmem_ctrl_pack-p.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | package t48_pmem_ctrl_pack is 12 | 13 | ----------------------------------------------------------------------------- 14 | -- Address Type Identifier 15 | ----------------------------------------------------------------------------- 16 | type pmem_addr_ident_t is (PM_PC, 17 | PM_PAGE, 18 | PM_PAGE3); 19 | 20 | end t48_pmem_ctrl_pack; 21 | 22 | 23 | ------------------------------------------------------------------------------- 24 | -- File History: 25 | -- 26 | -- $Log: pmem_ctrl_pack-p.vhd,v $ 27 | -- Revision 1.2 2005/06/11 10:08:43 arniml 28 | -- introduce prefix 't48_' for all packages, entities and configurations 29 | -- 30 | -- Revision 1.1 2004/03/23 21:31:53 arniml 31 | -- initial check-in 32 | -- 33 | ------------------------------------------------------------------------------- 34 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/dmem_ctrl_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: dmem_ctrl_pack-p.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | package t48_dmem_ctrl_pack is 12 | 13 | ----------------------------------------------------------------------------- 14 | -- Address Type Identifier 15 | ----------------------------------------------------------------------------- 16 | type dmem_addr_ident_t is (DM_PLAIN, 17 | DM_REG, 18 | DM_STACK, 19 | DM_STACK_HIGH); 20 | 21 | end t48_dmem_ctrl_pack; 22 | 23 | 24 | ------------------------------------------------------------------------------- 25 | -- File History: 26 | -- 27 | -- $Log: dmem_ctrl_pack-p.vhd,v $ 28 | -- Revision 1.2 2005/06/11 10:08:43 arniml 29 | -- introduce prefix 't48_' for all packages, entities and configurations 30 | -- 31 | -- Revision 1.1 2004/03/23 21:31:52 arniml 32 | -- initial check-in 33 | -- 34 | ------------------------------------------------------------------------------- 35 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE altera_ver ./libraries/altera_ver/ 13 | DEFINE lpm_ver ./libraries/lpm_ver/ 14 | DEFINE sgate_ver ./libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/ 20 | -------------------------------------------------------------------------------- /src/fpga/ap_core.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2019 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition 22 | # Date created = 21:31:36 January 22, 2020 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "18.1" 27 | DATE = "21:31:36 January 22, 2020" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "ap_core" 32 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/cond_branch_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: cond_branch_pack-p.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | library ieee; 12 | use ieee.std_logic_1164.all; 13 | 14 | package t48_cond_branch_pack is 15 | 16 | ----------------------------------------------------------------------------- 17 | -- The branch conditions. 18 | ----------------------------------------------------------------------------- 19 | type branch_conditions_t is (COND_ON_BIT, COND_Z, 20 | COND_C, 21 | COND_F0, COND_F1, 22 | COND_INT, 23 | COND_T0, COND_T1, 24 | COND_TF); 25 | 26 | subtype comp_value_t is std_logic_vector(2 downto 0); 27 | 28 | end t48_cond_branch_pack; 29 | 30 | 31 | ------------------------------------------------------------------------------- 32 | -- File History: 33 | -- 34 | -- $Log: cond_branch_pack-p.vhd,v $ 35 | -- Revision 1.2 2005/06/11 10:08:43 arniml 36 | -- introduce prefix 't48_' for all packages, entities and configurations 37 | -- 38 | -- Revision 1.1 2004/03/23 21:31:52 arniml 39 | -- initial check-in 40 | -- 41 | ------------------------------------------------------------------------------- 42 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Mario Bros 2 | 3 | Analogue Pocket port of Mario Bros. 4 | 5 | ## Features 6 | 7 | * Dip switches for difficulty, starting lives, and bonuses. 8 | 9 | ## Known Issues 10 | 11 | * High Score saving doesn't work. 12 | * Tate mode isn't supported. 13 | 14 | Note: File bugs for issues you encounter on the Github tracker. Any issues are most likely with my integration, and not with the cores themselves. Please do not engage the original core authors for support requests related to this port. 15 | 16 | ## Releaes Notes 17 | 18 | v0.9.3 19 | * Fixed video sync in dock 20 | 21 | v0.9.2 22 | * Updated version fields 23 | 24 | v0.9.1 25 | * Add coin pulse signal to fix issues with coin input not registering. 26 | 27 | v0.9.0 28 | * Initial Release. 29 | 30 | ## Attribution 31 | 32 | ``` 33 | Arcade: Mario Bros port to MiSTer by [gaz68](https://github.com/gaz68) - June 2020 34 | Original Donkey Kong port to MiSTer by [Sorgelig](https://github.com/sorgelig) - 18 April 2018 35 | ``` 36 | 37 | ### Sources 38 | 39 | [dkong](https://web.archive.org/web/20190330043320/http://www.geocities.jp/kwhr0/hard/fz80.html) Copyright (c) 2003 - 2004 by Katsumi Degawa 40 | [T80](https://opencores.org/projects/t80) Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) All rights reserved 41 | [T48](https://opencores.org/projects/t48) Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) All rights reserved 42 | 43 | - Quartus template and core integration based on the Analogue Pocket port of [Donkey Kong by ericlewis](https://github.com/ericlewis/openFPGA-DonkeyKong) 44 | 45 | ## ROM Instructions 46 | 47 | ROM files are not included, you must use [mra-tools-c](https://github.com/sebdel/mra-tools-c/) to convert to a singular `mario.rom` file, then place the ROM file in `/Assets/mario/common`. 48 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/alu_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: alu_pack-p.vhd,v 1.3 2005/06/11 10:08:43 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | library ieee; 12 | use ieee.std_logic_1164.all; 13 | 14 | use work.t48_pack.word_width_c; 15 | 16 | package t48_alu_pack is 17 | 18 | ----------------------------------------------------------------------------- 19 | -- The ALU operations 20 | ----------------------------------------------------------------------------- 21 | type alu_op_t is (ALU_AND, ALU_OR, ALU_XOR, 22 | ALU_CPL, ALU_CLR, 23 | ALU_RL, ALU_RR, 24 | ALU_SWAP, 25 | ALU_DEC, ALU_INC, 26 | ALU_ADD, 27 | ALU_CONCAT, 28 | ALU_NOP); 29 | 30 | ----------------------------------------------------------------------------- 31 | -- The dedicated ALU arithmetic types. 32 | ----------------------------------------------------------------------------- 33 | subtype alu_operand_t is std_logic_vector(word_width_c downto 0); 34 | 35 | end t48_alu_pack; 36 | 37 | 38 | ------------------------------------------------------------------------------- 39 | -- File History: 40 | -- 41 | -- $Log: alu_pack-p.vhd,v $ 42 | -- Revision 1.3 2005/06/11 10:08:43 arniml 43 | -- introduce prefix 't48_' for all packages, entities and configurations 44 | -- 45 | -- Revision 1.2 2004/04/04 14:18:53 arniml 46 | -- add measures to implement XCHD 47 | -- 48 | -- Revision 1.1 2004/03/23 21:31:52 arniml 49 | -- initial check-in 50 | -- 51 | ------------------------------------------------------------------------------- 52 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/t48_core-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T48 Microcontroller Core 4 | -- 5 | -- $Id: t48_core-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 6 | -- 7 | ------------------------------------------------------------------------------- 8 | 9 | configuration t48_core_struct_c0 of t48_core is 10 | 11 | for struct 12 | 13 | for alu_b : t48_alu 14 | use configuration work.t48_alu_rtl_c0; 15 | end for; 16 | 17 | for bus_mux_b : t48_bus_mux 18 | use configuration work.t48_bus_mux_rtl_c0; 19 | end for; 20 | 21 | for clock_ctrl_b : t48_clock_ctrl 22 | use configuration work.t48_clock_ctrl_rtl_c0; 23 | end for; 24 | 25 | for cond_branch_b : t48_cond_branch 26 | use configuration work.t48_cond_branch_rtl_c0; 27 | end for; 28 | 29 | for use_db_bus 30 | for db_bus_b : t48_db_bus 31 | use configuration work.t48_db_bus_rtl_c0; 32 | end for; 33 | end for; 34 | 35 | for decoder_b : t48_decoder 36 | use configuration work.t48_decoder_rtl_c0; 37 | end for; 38 | 39 | for dmem_ctrl_b : t48_dmem_ctrl 40 | use configuration work.t48_dmem_ctrl_rtl_c0; 41 | end for; 42 | 43 | for use_timer 44 | for timer_b : t48_timer 45 | use configuration work.t48_timer_rtl_c0; 46 | end for; 47 | end for; 48 | 49 | for use_p1 50 | for p1_b : t48_p1 51 | use configuration work.t48_p1_rtl_c0; 52 | end for; 53 | end for; 54 | 55 | for use_p2 56 | for p2_b : t48_p2 57 | use configuration work.t48_p2_rtl_c0; 58 | end for; 59 | end for; 60 | 61 | for pmem_ctrl_b : t48_pmem_ctrl 62 | use configuration work.t48_pmem_ctrl_rtl_c0; 63 | end for; 64 | 65 | for psw_b : t48_psw 66 | use configuration work.t48_psw_rtl_c0; 67 | end for; 68 | 69 | end for; 70 | 71 | end t48_core_struct_c0; 72 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_dma.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | // Mario Bros Arcade 3 | // 4 | // Author: gaz68 (https://github.com/gaz68) June 2020 5 | // 6 | // Simplified sprite DMA. 7 | // To Do: Implement full z80 DMA controller. 8 | // Mario Bros transfers $180 bytes from $6900 to $7000 9 | // when DMA is triggered. 10 | //---------------------------------------------------------------------------- 11 | 12 | module mario_dma 13 | ( 14 | input I_CLK_48M, 15 | input I_CEN_4M, 16 | input I_RSTn, 17 | input I_DMA_TRIG, 18 | input [7:0]I_DMA_DS, 19 | 20 | output [9:0]O_DMA_AS, 21 | output [9:0]O_DMA_AD, 22 | output [7:0]O_DMA_DD, 23 | output O_DMA_CES, 24 | output O_DMA_CED 25 | ); 26 | 27 | parameter dma_cnt_end = 10'h180; 28 | 29 | reg W_DMA_EN = 1'b0; 30 | reg [10:0]W_DMA_CNT; 31 | reg [7:0]W_DMA_DATA; 32 | reg [9:0]DMA_ASr; 33 | reg [9:0]DMA_ADr; 34 | reg [7:0]DMA_DDr; 35 | reg DMA_CESr, DMA_CEDr; 36 | 37 | always @(posedge I_CLK_48M) 38 | begin 39 | if (I_CEN_4M) begin 40 | reg old_trig; 41 | 42 | old_trig <= I_DMA_TRIG; 43 | 44 | if(~old_trig & I_DMA_TRIG) 45 | begin 46 | DMA_ASr <= 10'h100; 47 | DMA_ADr <= 0; 48 | W_DMA_CNT <= 0; 49 | W_DMA_EN <= 1'b1; 50 | DMA_CESr <= 1'b1; 51 | DMA_CEDr <= 1'b1; 52 | end 53 | else if(W_DMA_EN == 1'b1) 54 | begin 55 | case(W_DMA_CNT[1:0]) 56 | 1: DMA_DDr <= I_DMA_DS; 57 | 2: DMA_ASr <= DMA_ASr + 1'd1; 58 | 3: DMA_ADr <= DMA_ADr + 1'd1; 59 | default:; 60 | endcase 61 | W_DMA_CNT <= W_DMA_CNT + 1'd1; 62 | W_DMA_EN <= W_DMA_CNT==dma_cnt_end*4 ? 1'b0 : 1'b1; 63 | end 64 | else 65 | begin 66 | DMA_CESr <= 1'b0; 67 | DMA_CEDr <= 1'b0; 68 | end 69 | end 70 | end 71 | 72 | assign O_DMA_AS = DMA_ASr; 73 | assign O_DMA_AD = DMA_ADr; 74 | assign O_DMA_DD = DMA_DDr; 75 | assign O_DMA_CES = DMA_CESr; 76 | assign O_DMA_CED = DMA_CEDr; 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/T48.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) timer.vhd ] 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_pack-p.vhd ] 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_core_comp_pack-p.vhd ] 5 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_core.vhd ] 6 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_comp_pack-p.vhd ] 7 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) syn_ram-e.vhd ] 8 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) psw.vhd ] 9 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pmem_ctrl_pack-p.vhd ] 10 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pmem_ctrl.vhd ] 11 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) p2.vhd ] 12 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) p1.vhd ] 13 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) opc_table.vhd ] 14 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) opc_decoder.vhd ] 15 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) int.vhd ] 16 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dmem_ctrl_pack-p.vhd ] 17 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dmem_ctrl.vhd ] 18 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) decoder_pack-p.vhd ] 19 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) decoder.vhd ] 20 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) db_bus.vhd ] 21 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cond_branch_pack-p.vhd ] 22 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cond_branch.vhd ] 23 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) clock_ctrl.vhd ] 24 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) bus_mux.vhd ] 25 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) alu_pack-p.vhd ] 26 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) alu.vhd ] 27 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/dpram.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | 4 | LIBRARY altera_mf; 5 | USE altera_mf.altera_mf_components.all; 6 | 7 | entity dpram is 8 | generic ( 9 | addr_width_g : integer := 8; 10 | data_width_g : integer := 8 11 | ); 12 | PORT 13 | ( 14 | address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); 15 | address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); 16 | clock_a : IN STD_LOGIC := '1'; 17 | clock_b : IN STD_LOGIC ; 18 | data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); 19 | data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0'); 20 | enable_a : IN STD_LOGIC := '1'; 21 | enable_b : IN STD_LOGIC := '1'; 22 | wren_a : IN STD_LOGIC := '0'; 23 | wren_b : IN STD_LOGIC := '0'; 24 | q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); 25 | q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) 26 | ); 27 | END dpram; 28 | 29 | 30 | ARCHITECTURE SYN OF dpram IS 31 | BEGIN 32 | altsyncram_component : altsyncram 33 | GENERIC MAP ( 34 | address_reg_b => "CLOCK1", 35 | clock_enable_input_a => "NORMAL", 36 | clock_enable_input_b => "NORMAL", 37 | clock_enable_output_a => "BYPASS", 38 | clock_enable_output_b => "BYPASS", 39 | indata_reg_b => "CLOCK1", 40 | intended_device_family => "Cyclone V", 41 | lpm_type => "altsyncram", 42 | numwords_a => 2**addr_width_g, 43 | numwords_b => 2**addr_width_g, 44 | operation_mode => "BIDIR_DUAL_PORT", 45 | outdata_aclr_a => "NONE", 46 | outdata_aclr_b => "NONE", 47 | outdata_reg_a => "UNREGISTERED", 48 | outdata_reg_b => "UNREGISTERED", 49 | power_up_uninitialized => "FALSE", 50 | read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", 51 | read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", 52 | widthad_a => addr_width_g, 53 | widthad_b => addr_width_g, 54 | width_a => data_width_g, 55 | width_b => data_width_g, 56 | width_byteena_a => 1, 57 | width_byteena_b => 1, 58 | wrcontrol_wraddress_reg_b => "CLOCK1" 59 | ) 60 | PORT MAP ( 61 | address_a => address_a, 62 | address_b => address_b, 63 | clock0 => clock_a, 64 | clock1 => clock_b, 65 | clocken0 => enable_a, 66 | clocken1 => enable_b, 67 | data_a => data_a, 68 | data_b => data_b, 69 | wren_a => wren_a, 70 | wren_b => wren_b, 71 | q_a => q_a, 72 | q_b => q_b 73 | ); 74 | 75 | END SYN; 76 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_col_pal.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | // Mario Bros Arcade 3 | // 4 | // Author: gaz68 (https://github.com/gaz68) June 2020 5 | // 6 | // Colour palette. 7 | // Based on the Donkey Kong version by Katsumi Degawa. 8 | //---------------------------------------------------------------------------- 9 | 10 | module mario_col_pal 11 | ( 12 | input I_CLK_48M, 13 | input I_CEN_24Mn, 14 | input I_CEN_6M, 15 | input [6:0]I_VRAM_D, 16 | input [6:0]I_OBJ_D, 17 | input I_CMPBLKn, 18 | input I_CPAL_SEL, 19 | input I_DLCLK, 20 | input [16:0]I_DLADDR, 21 | input [7:0]I_DLDATA, 22 | input I_DLWR, 23 | 24 | output [2:0]O_R, 25 | output [2:0]O_G, 26 | output [1:0]O_B 27 | ); 28 | 29 | // Link CL2 on the schematics 30 | // Uncut = 0 - Inverted colour palette 31 | // Cut = 1 - Standard colour palette 32 | parameter CL2 = 1'b1; 33 | 34 | //------------------------------------- 35 | // Parts 4U, 5T (74LS157) 36 | // Selects sprites or backgound pixels 37 | // Sprites take priority 38 | //------------------------------------- 39 | 40 | wire [6:0]W_4U5T_Y = (~(I_OBJ_D[0]|I_OBJ_D[1]|I_OBJ_D[2])) ? I_VRAM_D: I_OBJ_D; 41 | 42 | //-------------- 43 | // Parts 6T, 6U 44 | //-------------- 45 | 46 | wire [8:0]W_6TU_D = {I_CPAL_SEL,W_4U5T_Y[6:0],I_CMPBLKn}; 47 | reg [8:0]W_6TU_Q; 48 | wire W_6TU_RST = I_CMPBLKn | W_6TU_Q[0]; 49 | 50 | always@(posedge I_CLK_48M) 51 | begin 52 | if (I_CEN_24Mn) begin 53 | if(W_6TU_RST == 1'b0) 54 | W_6TU_Q <= 9'b0; 55 | else if (I_CEN_6M) 56 | W_6TU_Q <= W_6TU_D; 57 | end 58 | end 59 | 60 | //-------------------------------------------------------------- 61 | // Colour PROM 4P (512 x 8bit) 62 | // The PROM actually contains 2 versions of the colour palette: 63 | // 0 - 255 = Inverted palette 64 | // 256 - 512 = Standard palette 65 | // Link CL2 on the PCB is used for selecting the palette. 66 | //-------------------------------------------------------------- 67 | 68 | wire [8:0]W_PAL_AB = {CL2,W_6TU_Q[8:1]}; 69 | wire [7:0]W_4P_DO; 70 | 71 | CLUT_PROM_512_8 prom4p(I_CLK_48M, W_PAL_AB, W_4P_DO, 72 | I_DLCLK, I_DLADDR, I_DLDATA, I_DLWR); 73 | 74 | assign {O_R, O_G, O_B} = W_4P_DO; // 3R:3G:2B 75 | 76 | endmodule 77 | 78 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/pll/pll_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module pll_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'locked' 14 | output wire locked 15 | ); 16 | 17 | altera_pll #( 18 | .fractional_vco_multiplier("false"), 19 | .reference_clock_frequency("50.0 MHz"), 20 | .operation_mode("direct"), 21 | .number_of_clocks(1), 22 | .output_clock_frequency0("48.000000 MHz"), 23 | .phase_shift0("0 ps"), 24 | .duty_cycle0(50), 25 | .output_clock_frequency1("0 MHz"), 26 | .phase_shift1("0 ps"), 27 | .duty_cycle1(50), 28 | .output_clock_frequency2("0 MHz"), 29 | .phase_shift2("0 ps"), 30 | .duty_cycle2(50), 31 | .output_clock_frequency3("0 MHz"), 32 | .phase_shift3("0 ps"), 33 | .duty_cycle3(50), 34 | .output_clock_frequency4("0 MHz"), 35 | .phase_shift4("0 ps"), 36 | .duty_cycle4(50), 37 | .output_clock_frequency5("0 MHz"), 38 | .phase_shift5("0 ps"), 39 | .duty_cycle5(50), 40 | .output_clock_frequency6("0 MHz"), 41 | .phase_shift6("0 ps"), 42 | .duty_cycle6(50), 43 | .output_clock_frequency7("0 MHz"), 44 | .phase_shift7("0 ps"), 45 | .duty_cycle7(50), 46 | .output_clock_frequency8("0 MHz"), 47 | .phase_shift8("0 ps"), 48 | .duty_cycle8(50), 49 | .output_clock_frequency9("0 MHz"), 50 | .phase_shift9("0 ps"), 51 | .duty_cycle9(50), 52 | .output_clock_frequency10("0 MHz"), 53 | .phase_shift10("0 ps"), 54 | .duty_cycle10(50), 55 | .output_clock_frequency11("0 MHz"), 56 | .phase_shift11("0 ps"), 57 | .duty_cycle11(50), 58 | .output_clock_frequency12("0 MHz"), 59 | .phase_shift12("0 ps"), 60 | .duty_cycle12(50), 61 | .output_clock_frequency13("0 MHz"), 62 | .phase_shift13("0 ps"), 63 | .duty_cycle13(50), 64 | .output_clock_frequency14("0 MHz"), 65 | .phase_shift14("0 ps"), 66 | .duty_cycle14(50), 67 | .output_clock_frequency15("0 MHz"), 68 | .phase_shift15("0 ps"), 69 | .duty_cycle15(50), 70 | .output_clock_frequency16("0 MHz"), 71 | .phase_shift16("0 ps"), 72 | .duty_cycle16(50), 73 | .output_clock_frequency17("0 MHz"), 74 | .phase_shift17("0 ps"), 75 | .duty_cycle17(50), 76 | .pll_type("General"), 77 | .pll_subtype("General") 78 | ) altera_pll_i ( 79 | .rst (rst), 80 | .outclk ({outclk_0}), 81 | .locked (locked), 82 | .fboutclk ( ), 83 | .fbclk (1'b0), 84 | .refclk (refclk) 85 | ); 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_sound.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | // Mario Bros Arcade 3 | // 4 | // Author: gaz68 (https://github.com/gaz68) June 2020 5 | // 6 | // Top level sound module. 7 | //---------------------------------------------------------------------------- 8 | 9 | module mario_sound 10 | ( 11 | input I_CLK_48M, 12 | input I_CEN_12M, 13 | input I_CEN_11M, 14 | input I_RESETn, 15 | input [7:0]I_SND_DATA, 16 | input [9:0]I_SND_CTRL, 17 | input [3:0]I_ANLG_VOL, 18 | input I_DS_FILTER, 19 | input [3:0]I_H_CNT, 20 | input [16:0]I_DLADDR, 21 | input [7:0]I_DLDATA, 22 | input I_DLWR, 23 | 24 | output signed [15:0]O_SND_DAT 25 | ); 26 | 27 | //------------------------------------------------ 28 | // Digital sound 29 | // Background music and some of the sound effects 30 | //------------------------------------------------ 31 | 32 | wire [15:0]W_D_S_DATA; 33 | 34 | mario_sound_digital digital_sound 35 | ( 36 | .I_CLK_48M(I_CLK_48M), 37 | .I_CEN_12M(I_CEN_12M), 38 | .I_CEN_11M(I_CEN_11M), 39 | .I_RST(I_RESETn), 40 | .I_DLADDR(I_DLADDR), 41 | .I_DLDATA(I_DLDATA), 42 | .I_DLWR(I_DLWR), 43 | .I_SND_DATA(I_SND_DATA), 44 | .I_SND_CTRL(I_SND_CTRL[6:0]), 45 | 46 | .O_SND_OUT(W_D_S_DATA) 47 | ); 48 | 49 | //-------------------------------------- 50 | // Analogue Sounds (samples) 51 | // Mario run, Luigi run and skid sounds 52 | //-------------------------------------- 53 | 54 | wire signed [15:0]W_WAVROM_DS[0:2]; 55 | 56 | mario_sound_analog analog_sound 57 | ( 58 | .I_CLK_48M(I_CLK_48M), 59 | .I_RESETn(I_RESETn), 60 | 61 | .I_SND_CTRL(I_SND_CTRL[9:7]), 62 | .I_ANLG_VOL(I_ANLG_VOL), 63 | .I_H_CNT(I_H_CNT), 64 | 65 | .I_DLADDR(I_DLADDR), 66 | .I_DLDATA(I_DLDATA), 67 | .I_DLWR(I_DLWR), 68 | 69 | .O_WAVROM_DS0(W_WAVROM_DS[0]), 70 | .O_WAVROM_DS1(W_WAVROM_DS[1]), 71 | .O_WAVROM_DS2(W_WAVROM_DS[2]) 72 | ); 73 | 74 | //---------------------------------- 75 | // Sound Mixer (Analogue & Digital) 76 | //---------------------------------- 77 | 78 | wire signed [15:0]W_SND_MIX; 79 | 80 | mario_sound_mixer mixer 81 | ( 82 | .I_CLK_48M(I_CLK_48M), 83 | .I_SND1(W_WAVROM_DS[0]), 84 | .I_SND2(W_WAVROM_DS[1]), 85 | .I_SND3(W_WAVROM_DS[2]), 86 | .I_SND4(W_D_S_DATA), 87 | .O_SND_DAT(W_SND_MIX) 88 | ); 89 | 90 | assign O_SND_DAT = W_SND_MIX; 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase/mf_pllbase_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module mf_pllbase_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'outclk1' 14 | output wire outclk_1, 15 | 16 | // interface 'outclk2' 17 | output wire outclk_2, 18 | 19 | // interface 'locked' 20 | output wire locked 21 | ); 22 | 23 | altera_pll #( 24 | .fractional_vco_multiplier("false"), 25 | .reference_clock_frequency("74.25 MHz"), 26 | .operation_mode("direct"), 27 | .number_of_clocks(3), 28 | .output_clock_frequency0("6.000000 MHz"), 29 | .phase_shift0("0 ps"), 30 | .duty_cycle0(50), 31 | .output_clock_frequency1("6.000000 MHz"), 32 | .phase_shift1("41667 ps"), 33 | .duty_cycle1(50), 34 | .output_clock_frequency2("48.000000 MHz"), 35 | .phase_shift2("0 ps"), 36 | .duty_cycle2(50), 37 | .output_clock_frequency3("0 MHz"), 38 | .phase_shift3("0 ps"), 39 | .duty_cycle3(50), 40 | .output_clock_frequency4("0 MHz"), 41 | .phase_shift4("0 ps"), 42 | .duty_cycle4(50), 43 | .output_clock_frequency5("0 MHz"), 44 | .phase_shift5("0 ps"), 45 | .duty_cycle5(50), 46 | .output_clock_frequency6("0 MHz"), 47 | .phase_shift6("0 ps"), 48 | .duty_cycle6(50), 49 | .output_clock_frequency7("0 MHz"), 50 | .phase_shift7("0 ps"), 51 | .duty_cycle7(50), 52 | .output_clock_frequency8("0 MHz"), 53 | .phase_shift8("0 ps"), 54 | .duty_cycle8(50), 55 | .output_clock_frequency9("0 MHz"), 56 | .phase_shift9("0 ps"), 57 | .duty_cycle9(50), 58 | .output_clock_frequency10("0 MHz"), 59 | .phase_shift10("0 ps"), 60 | .duty_cycle10(50), 61 | .output_clock_frequency11("0 MHz"), 62 | .phase_shift11("0 ps"), 63 | .duty_cycle11(50), 64 | .output_clock_frequency12("0 MHz"), 65 | .phase_shift12("0 ps"), 66 | .duty_cycle12(50), 67 | .output_clock_frequency13("0 MHz"), 68 | .phase_shift13("0 ps"), 69 | .duty_cycle13(50), 70 | .output_clock_frequency14("0 MHz"), 71 | .phase_shift14("0 ps"), 72 | .duty_cycle14(50), 73 | .output_clock_frequency15("0 MHz"), 74 | .phase_shift15("0 ps"), 75 | .duty_cycle15(50), 76 | .output_clock_frequency16("0 MHz"), 77 | .phase_shift16("0 ps"), 78 | .duty_cycle16(50), 79 | .output_clock_frequency17("0 MHz"), 80 | .phase_shift17("0 ps"), 81 | .duty_cycle17(50), 82 | .pll_type("General"), 83 | .pll_subtype("General") 84 | ) altera_pll_i ( 85 | .rst (rst), 86 | .outclk ({outclk_2, outclk_1, outclk_0}), 87 | .locked (locked), 88 | .fboutclk ( ), 89 | .fbclk (1'b0), 90 | .refclk (refclk) 91 | ); 92 | endmodule 93 | 94 | -------------------------------------------------------------------------------- /dist/Cores/obsidian.MarioBros/interact.json: -------------------------------------------------------------------------------- 1 | { 2 | "interact": { 3 | "magic": "APF_VER_1", 4 | "variables": [ 5 | { 6 | "name": "Players", 7 | "id": 1, 8 | "type": "list", 9 | "enabled": true, 10 | "persist": true, 11 | "address": "0x80000000", 12 | "writeonly": true, 13 | "defaultval": 0, 14 | "options": [ 15 | { 16 | "value": 0, 17 | "name": "3" 18 | }, 19 | { 20 | "value": 1, 21 | "name": "4" 22 | }, 23 | { 24 | "value": 2, 25 | "name": "5" 26 | }, 27 | { 28 | "value": 3, 29 | "name": "6" 30 | } 31 | ] 32 | }, 33 | { 34 | "name": "Bonus", 35 | "id": 2, 36 | "type": "list", 37 | "enabled": true, 38 | "persist": true, 39 | "address": "0x90000000", 40 | "writeonly": true, 41 | "defaultval": 0, 42 | "options": [ 43 | { 44 | "value": 0, 45 | "name": "10k" 46 | }, 47 | { 48 | "value": 1, 49 | "name": "15k" 50 | }, 51 | { 52 | "value": 2, 53 | "name": "20k" 54 | }, 55 | { 56 | "value": 3, 57 | "name": "25k" 58 | } 59 | ] 60 | }, 61 | { 62 | "name": "Difficulty", 63 | "id": 3, 64 | "type": "list", 65 | "enabled": true, 66 | "persist": true, 67 | "address": "0x10000000", 68 | "writeonly": true, 69 | "defaultval": 0, 70 | "options": [ 71 | { 72 | "value": 0, 73 | "name": "Easy" 74 | }, 75 | { 76 | "value": 2, 77 | "name": "Medium" 78 | }, 79 | { 80 | "value": 1, 81 | "name": "Hard" 82 | }, 83 | { 84 | "value": 3, 85 | "name": "Hardest" 86 | } 87 | ] 88 | } 89 | ], 90 | "messages": [] 91 | } 92 | } -------------------------------------------------------------------------------- /src/fpga/core/rtl/T80/README: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- **** 3 | -- T80(c) core. Attempt to finish all undocumented features and provide 4 | -- accurate timings. 5 | -- 6 | -- Version 351. 7 | -- Merged Gameboy fixes from Bruno Duarte Gouveia (brNX) 8 | -- Passes Blargg's test ROMs 9 | -- 10 | -- Version 350. 11 | -- Copyright (c) 2018 Sorgelig 12 | -- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr 13 | -- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as 14 | -- correct implementation is still unclear. 15 | -- 16 | -- **** 17 | -- T80(b) core. In an effort to merge and maintain bug fixes .... 18 | -- 19 | -- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 20 | -- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle 21 | -- Ver 300 started tidyup. 22 | -- 23 | -- MikeJ March 2005 24 | -- Latest version from www.fpgaarcade.com (original www.opencores.org) 25 | -- 26 | -- **** 27 | -- Z80 compatible microprocessor core 28 | -- 29 | -- Version : 0250 30 | -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) 31 | -- All rights reserved 32 | -- 33 | -- Redistribution and use in source and synthezised forms, with or without 34 | -- modification, are permitted provided that the following conditions are met: 35 | -- 36 | -- Redistributions of source code must retain the above copyright notice, 37 | -- this list of conditions and the following disclaimer. 38 | -- 39 | -- Redistributions in synthesized form must reproduce the above copyright 40 | -- notice, this list of conditions and the following disclaimer in the 41 | -- documentation and/or other materials provided with the distribution. 42 | -- 43 | -- Neither the name of the author nor the names of other contributors may 44 | -- be used to endorse or promote products derived from this software without 45 | -- specific prior written permission. 46 | -- 47 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 48 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 49 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 50 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 51 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 52 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 53 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 54 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 55 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 56 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 57 | -- POSSIBILITY OF SUCH DAMAGE. 58 | -- 59 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/t48_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: t48_pack-p.vhd,v 1.1 2004/03/23 21:31:53 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | library ieee; 12 | use ieee.std_logic_1164.all; 13 | 14 | package t48_pack is 15 | 16 | ----------------------------------------------------------------------------- 17 | -- Global constants 18 | ----------------------------------------------------------------------------- 19 | 20 | -- clock active level 21 | constant clk_active_c : std_logic := '1'; 22 | -- reset active level 23 | constant res_active_c : std_logic := '0'; 24 | -- idle level on internal data bus 25 | constant bus_idle_level_c : std_logic := '1'; 26 | 27 | -- global data word width 28 | constant word_width_c : natural := 8; 29 | 30 | -- data memory address width 31 | constant dmem_addr_width_c : natural := 8; 32 | -- program memory address width 33 | constant pmem_addr_width_c : natural := 12; 34 | 35 | 36 | ----------------------------------------------------------------------------- 37 | -- Global data types 38 | ----------------------------------------------------------------------------- 39 | 40 | -- the global data word width type 41 | subtype word_t is std_logic_vector(word_width_c-1 downto 0); 42 | subtype nibble_t is std_logic_vector(word_width_c/2-1 downto 0); 43 | -- the global data memory address type 44 | subtype dmem_addr_t is std_logic_vector(dmem_addr_width_c-1 downto 0); 45 | -- the global program memory address type 46 | subtype pmem_addr_t is std_logic_vector(pmem_addr_width_c-1 downto 0); 47 | subtype page_t is std_logic_vector(pmem_addr_width_c-1 downto word_width_c); 48 | 49 | -- the machine states 50 | type mstate_t is (MSTATE1, MSTATE2, MSTATE3, MSTATE4, MSTATE5); 51 | 52 | 53 | ----------------------------------------------------------------------------- 54 | -- Global functions 55 | ----------------------------------------------------------------------------- 56 | 57 | function to_stdLogic(input: boolean) return std_logic; 58 | function to_boolean(input: std_logic) return boolean; 59 | 60 | end t48_pack; 61 | 62 | package body t48_pack is 63 | 64 | function to_stdLogic(input: boolean) return std_logic is 65 | begin 66 | if input then 67 | return '1'; 68 | else 69 | return '0'; 70 | end if; 71 | end to_stdLogic; 72 | 73 | function to_boolean(input: std_logic) return boolean is 74 | begin 75 | if input = '1' then 76 | return true; 77 | else 78 | return false; 79 | end if; 80 | end to_boolean; 81 | 82 | end t48_pack; 83 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t48_rom-e.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8x48 ROM 4 | -- 5 | -- $Id: t48_rom-e.vhd,v 1.1.1.1 2006/11/25 22:15:41 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | -- Redistribution and use in source and synthezised forms, with or without 12 | -- modification, are permitted provided that the following conditions are met: 13 | -- 14 | -- Redistributions of source code must retain the above copyright notice, 15 | -- this list of conditions and the following disclaimer. 16 | -- 17 | -- Redistributions in synthesized form must reproduce the above copyright 18 | -- notice, this list of conditions and the following disclaimer in the 19 | -- documentation and/or other materials provided with the distribution. 20 | -- 21 | -- Neither the name of the author nor the names of other contributors may 22 | -- be used to endorse or promote products derived from this software without 23 | -- specific prior written permission. 24 | -- 25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 | -- POSSIBILITY OF SUCH DAMAGE. 36 | -- 37 | -- Please report bugs to the author, but before you do so, please 38 | -- make sure that this is not a derivative work and that 39 | -- you have the latest version of this file. 40 | -- 41 | -- The latest version of this file can be found at: 42 | -- http://www.opencores.org/cvsweb.shtml/t48/ 43 | -- 44 | ------------------------------------------------------------------------------- 45 | 46 | library ieee; 47 | use ieee.std_logic_1164.all; 48 | 49 | entity t48_rom is 50 | 51 | port ( 52 | clk_i : in std_logic; 53 | rom_addr_i : in std_logic_vector(9 downto 0); 54 | rom_data_o : out std_logic_vector(7 downto 0) 55 | ); 56 | 57 | end t48_rom; 58 | 59 | 60 | ------------------------------------------------------------------------------- 61 | -- File History: 62 | -- 63 | -- $Log: t48_rom-e.vhd,v $ 64 | -- Revision 1.1.1.1 2006/11/25 22:15:41 arnim 65 | -- copied from opencores.org repository release 1.0 66 | -- 67 | -- Revision 1.1 2006/06/21 00:59:15 arniml 68 | -- initial check-in 69 | -- 70 | ------------------------------------------------------------------------------- 71 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t49_rom-e.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8x49 ROM 4 | -- 5 | -- $Id: t49_rom-e.vhd,v 1.1.1.1 2006/11/25 22:15:41 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | -- Redistribution and use in source and synthezised forms, with or without 12 | -- modification, are permitted provided that the following conditions are met: 13 | -- 14 | -- Redistributions of source code must retain the above copyright notice, 15 | -- this list of conditions and the following disclaimer. 16 | -- 17 | -- Redistributions in synthesized form must reproduce the above copyright 18 | -- notice, this list of conditions and the following disclaimer in the 19 | -- documentation and/or other materials provided with the distribution. 20 | -- 21 | -- Neither the name of the author nor the names of other contributors may 22 | -- be used to endorse or promote products derived from this software without 23 | -- specific prior written permission. 24 | -- 25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 | -- POSSIBILITY OF SUCH DAMAGE. 36 | -- 37 | -- Please report bugs to the author, but before you do so, please 38 | -- make sure that this is not a derivative work and that 39 | -- you have the latest version of this file. 40 | -- 41 | -- The latest version of this file can be found at: 42 | -- http://www.opencores.org/cvsweb.shtml/t48/ 43 | -- 44 | ------------------------------------------------------------------------------- 45 | 46 | library ieee; 47 | use ieee.std_logic_1164.all; 48 | 49 | entity t49_rom is 50 | 51 | port ( 52 | clk_i : in std_logic; 53 | rom_addr_i : in std_logic_vector(10 downto 0); 54 | rom_data_o : out std_logic_vector( 7 downto 0) 55 | ); 56 | 57 | end t49_rom; 58 | 59 | 60 | ------------------------------------------------------------------------------- 61 | -- File History: 62 | -- 63 | -- $Log: t49_rom-e.vhd,v $ 64 | -- Revision 1.1.1.1 2006/11/25 22:15:41 arnim 65 | -- copied from opencores.org repository release 1.0 66 | -- 67 | -- Revision 1.1 2006/06/21 00:59:15 arniml 68 | -- initial check-in 69 | -- 70 | ------------------------------------------------------------------------------- 71 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_input.v: -------------------------------------------------------------------------------- 1 | //--------------------------------------------------------------------------------- 2 | // Mario Bros Arcade 3 | // 4 | // Author: gaz68 (https://github.com/gaz68) June 2020 5 | // 6 | // Controls and DIP Switches. 7 | //--------------------------------------------------------------------------------- 8 | 9 | //--------------------------------------------------------------------------------- 10 | // CONTROLS 11 | // 12 | // BIT 0 1 2 3 4 5 6 7 13 | //--------------------------------------------------------------------------------- 14 | // SW1(MAIN) RIGHT LEFT - - JUMP 1P START 2P START TEST 15 | // SW2(SUB) RIGHT2 LEFT2 - - JUMP2 COIN - - 16 | //--------------------------------------------------------------------------------- 17 | 18 | //--------------------------------------------------------------------------------- 19 | // DIP SWITCHES 20 | // 21 | // Toggle (DIP1) Settings: 22 | // A B C D E F G H Option 23 | //--------------------------------------------------------------------------------- 24 | // Number of Players per Game 25 | // -------------------------- 26 | // Off Off 3 27 | // On Off 4 28 | // Off On 5 29 | // On On 6 30 | // 31 | // Coin/Credit 32 | // ---------- 33 | // Off Off 1/1 34 | // On Off 2/1 35 | // Off On 1/2 36 | // On On 1/3 37 | // 38 | // Extra Life 39 | // ---------- 40 | // Off Off 20,000 points 41 | // On Off 30,000 points 42 | // Off On 40,000 points 43 | // On On No extra life 44 | // 45 | // Difficulty 46 | // ---------- 47 | // Off Off (1) Easy 48 | // On Off (3) Hard 49 | // Off On (2) Medium 50 | // On On (4) Hardest 51 | // 52 | //--------------------------------------------------------------------------------- 53 | // NOTE: Mario Bros does not have a cocktail mode. 54 | 55 | module mario_inport 56 | ( 57 | input [7:0]I_SW1, 58 | input [7:0]I_SW2, 59 | input [7:0]I_DIPSW, 60 | input I_SW1_OEn, 61 | input I_SW2_OEn, 62 | input I_DIPSW_OEn, 63 | 64 | output [7:0]O_D 65 | ); 66 | 67 | wire [7:0]W_SW1 = I_SW1_OEn ? 8'h00: ~I_SW1; 68 | wire [7:0]W_SW2 = I_SW2_OEn ? 8'h00: ~I_SW2; 69 | 70 | wire [7:0]W_DIPSW = I_DIPSW_OEn ? 8'h00: {I_DIPSW[6],I_DIPSW[7],I_DIPSW[5:0]}; 71 | 72 | assign O_D = W_SW1 | W_SW2 | W_DIPSW; 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/syn_ram-e.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- A synchronous parametrizable RAM. 4 | -- 5 | -- $Id: syn_ram-e.vhd,v 1.1 2004/03/24 21:32:27 arniml Exp $ 6 | -- 7 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | -- Redistribution and use in source and synthezised forms, with or without 12 | -- modification, are permitted provided that the following conditions are met: 13 | -- 14 | -- Redistributions of source code must retain the above copyright notice, 15 | -- this list of conditions and the following disclaimer. 16 | -- 17 | -- Redistributions in synthesized form must reproduce the above copyright 18 | -- notice, this list of conditions and the following disclaimer in the 19 | -- documentation and/or other materials provided with the distribution. 20 | -- 21 | -- Neither the name of the author nor the names of other contributors may 22 | -- be used to endorse or promote products derived from this software without 23 | -- specific prior written permission. 24 | -- 25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 | -- POSSIBILITY OF SUCH DAMAGE. 36 | -- 37 | -- Please report bugs to the author, but before you do so, please 38 | -- make sure that this is not a derivative work and that 39 | -- you have the latest version of this file. 40 | -- 41 | -- The latest version of this file can be found at: 42 | -- http://www.opencores.org/cvsweb.shtml/t48/ 43 | -- 44 | ------------------------------------------------------------------------------- 45 | 46 | library ieee; 47 | use ieee.std_logic_1164.all; 48 | 49 | entity syn_ram is 50 | 51 | generic ( 52 | address_width_g : positive := 8 53 | ); 54 | port ( 55 | clk_i : in std_logic; 56 | res_i : in std_logic; 57 | ram_addr_i : in std_logic_vector(address_width_g-1 downto 0); 58 | ram_data_i : in std_logic_vector(7 downto 0); 59 | ram_we_i : in std_logic; 60 | ram_data_o : out std_logic_vector(7 downto 0) 61 | ); 62 | 63 | end syn_ram; 64 | 65 | 66 | ------------------------------------------------------------------------------- 67 | -- File History: 68 | -- 69 | -- $Log: syn_ram-e.vhd,v $ 70 | -- Revision 1.1 2004/03/24 21:32:27 arniml 71 | -- initial check-in 72 | -- 73 | ------------------------------------------------------------------------------- 74 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_logic.v: -------------------------------------------------------------------------------- 1 | //=============================================================================== 2 | // FPGA DONKEY KONG used LOGIC IP 3 | // 4 | // Version : 1.00 5 | // 6 | // Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved 7 | // 8 | // Important ! 9 | // 10 | // This program is freeware for non-commercial use. 11 | // An author does no guarantee about this program. 12 | // You can use this under your own risk. 13 | // 14 | //================================================================================ 15 | 16 | //================================================ 17 | // 74xx109 18 | // JK FLIP-FLOPS with PRESET & RST 19 | // PRESET NO USE 20 | //================================================ 21 | 22 | module logic_74xx109( 23 | FAST_CLK, 24 | CLK, 25 | RST, 26 | I_J, 27 | I_K, 28 | O_Q 29 | 30 | ); 31 | 32 | input FAST_CLK,CLK,RST; 33 | input I_J,I_K; 34 | output O_Q; 35 | 36 | reg CLK_q; 37 | reg Q; 38 | 39 | assign O_Q = Q; 40 | 41 | always@(posedge FAST_CLK)begin 42 | CLK_q <= CLK; 43 | end 44 | 45 | wire CLK_rise = ~CLK_q & CLK; 46 | 47 | always@(posedge FAST_CLK or negedge RST) 48 | begin 49 | if(RST == 1'b0) Q <= 1'b0; 50 | else if (CLK_rise) begin 51 | case({I_J,I_K}) 52 | 2'b00: Q <= 1'b0; 53 | 2'b01: Q <= Q; 54 | 2'b10: Q <= ~Q; 55 | 2'b11: Q <= 1'b1; 56 | endcase 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | //================================================ 63 | // 74xx138 64 | // 3-to-8 line decoder 65 | //================================================ 66 | 67 | module logic_74xx138( 68 | 69 | I_G1, 70 | I_G2a, 71 | I_G2b, 72 | I_Sel, 73 | O_Q 74 | 75 | ); 76 | 77 | input I_G1,I_G2a,I_G2b; 78 | input [2:0]I_Sel; 79 | output [7:0]O_Q; 80 | 81 | reg [7:0]O_Q; 82 | wire [2:0]I_G = {I_G1,I_G2a,I_G2b}; 83 | always@(I_G or I_Sel or O_Q) 84 | begin 85 | if(I_G == 3'b100 )begin 86 | case(I_Sel) 87 | 3'b000: O_Q = 8'b11111110; 88 | 3'b001: O_Q = 8'b11111101; 89 | 3'b010: O_Q = 8'b11111011; 90 | 3'b011: O_Q = 8'b11110111; 91 | 3'b100: O_Q = 8'b11101111; 92 | 3'b101: O_Q = 8'b11011111; 93 | 3'b110: O_Q = 8'b10111111; 94 | 3'b111: O_Q = 8'b01111111; 95 | endcase 96 | end 97 | else begin 98 | O_Q = 8'b11111111; 99 | end 100 | end 101 | endmodule 102 | 103 | //================================================ 104 | // 74xx139 105 | // 2-to-4 line decoder 106 | //================================================ 107 | 108 | module logic_74xx139( 109 | 110 | I_G, 111 | I_Sel, 112 | O_Q 113 | 114 | ); 115 | 116 | input I_G; 117 | input [1:0]I_Sel; 118 | output [3:0]O_Q; 119 | 120 | reg [3:0]O_Q; 121 | always@(I_G or I_Sel or O_Q) 122 | begin 123 | if(I_G == 1'b0 )begin 124 | case(I_Sel) 125 | 2'b00: O_Q = 4'b1110; 126 | 2'b01: O_Q = 4'b1101; 127 | 2'b10: O_Q = 4'b1011; 128 | 2'b11: O_Q = 4'b0111; 129 | endcase 130 | end 131 | else begin 132 | O_Q = 4'b1111; 133 | end 134 | end 135 | 136 | endmodule 137 | -------------------------------------------------------------------------------- /src/fpga/core/sync_fifo.sv: -------------------------------------------------------------------------------- 1 | // MIT License 2 | 3 | // Copyright (c) 2022 Adam Gastineau 4 | 5 | // Permission is hereby granted, free of charge, to any person obtaining a copy 6 | // of this software and associated documentation files (the "Software"), to deal 7 | // in the Software without restriction, including without limitation the rights 8 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | // copies of the Software, and to permit persons to whom the Software is 10 | // furnished to do so, subject to the following conditions: 11 | 12 | // The above copyright notice and this permission notice shall be included in all 13 | // copies or substantial portions of the Software. 14 | 15 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | // SOFTWARE. 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | // An easily reusable method for synchronizing multiple bits across clock domains 26 | // Uses a shallow depth (4 entries) FIFO, so make sure to empty it quickly 27 | module sync_fifo #( 28 | parameter WIDTH = 2 29 | ) ( 30 | input wire clk_write, 31 | input wire clk_read, 32 | 33 | input wire write_en, 34 | input wire [WIDTH - 1:0] data_in, 35 | output reg [WIDTH - 1:0] data_out = 0 36 | ); 37 | 38 | reg read_req = 0; 39 | wire empty; 40 | 41 | wire [WIDTH - 1:0] fifo_out; 42 | 43 | dcfifo dcfifo_component ( 44 | .data(data_in), 45 | .rdclk(clk_read), 46 | .rdreq(read_req), 47 | .wrclk(clk_write), 48 | .wrreq(write_en), 49 | .q(fifo_out), 50 | .rdempty(empty), 51 | .aclr(), 52 | .eccstatus(), 53 | .rdfull(), 54 | .rdusedw(), 55 | .wrempty(), 56 | .wrfull(), 57 | .wrusedw() 58 | ); 59 | defparam dcfifo_component.intended_device_family = "Cyclone V", dcfifo_component.lpm_numwords = 4, 60 | dcfifo_component.lpm_showahead = "OFF", dcfifo_component.lpm_type = "dcfifo", 61 | dcfifo_component.lpm_width = 32, dcfifo_component.lpm_widthu = 2, 62 | dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 5, 63 | dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON", 64 | dcfifo_component.wrsync_delaypipe = 5; 65 | 66 | reg [1:0] read_state = 0; 67 | 68 | localparam READ_DELAY = 1; 69 | localparam READ_WRITE = 2; 70 | 71 | always @(posedge clk_read) begin 72 | read_req <= 0; 73 | 74 | if (~empty) begin 75 | read_state <= READ_DELAY; 76 | read_req <= 1; 77 | end 78 | 79 | case (read_state) 80 | READ_DELAY: begin 81 | read_state <= READ_WRITE; 82 | end 83 | READ_WRITE: begin 84 | read_state <= 0; 85 | 86 | data_out <= fifo_out; 87 | end 88 | endcase 89 | end 90 | 91 | endmodule 92 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/decoder_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: decoder_pack-p.vhd,v 1.3 2005/06/11 10:08:43 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | package t48_decoder_pack is 12 | 13 | ----------------------------------------------------------------------------- 14 | -- The Mnemonics. 15 | ----------------------------------------------------------------------------- 16 | type mnemonic_t is (MN_ADD, 17 | MN_ADD_A_DATA, 18 | MN_ANL, 19 | MN_ANL_A_DATA, 20 | MN_ANL_EXT, 21 | MN_CALL, 22 | MN_CLR_A, 23 | MN_CLR_C, 24 | MN_CLR_F, 25 | MN_CPL_A, 26 | MN_CPL_C, 27 | MN_CPL_F, 28 | MN_DA, 29 | MN_DEC, 30 | MN_DIS_EN_I, 31 | MN_DIS_EN_TCNTI, 32 | MN_DJNZ, 33 | MN_ENT0_CLK, 34 | MN_IN, 35 | MN_INC, 36 | MN_INS, 37 | MN_JBB, 38 | MN_JC, 39 | MN_JF, 40 | MN_JMP, 41 | MN_JMPP, 42 | MN_JNI, 43 | MN_JT, 44 | MN_JTF, 45 | MN_JZ, 46 | MN_MOV_A_DATA, 47 | MN_MOV_A_PSW, 48 | MN_MOV_A_RR, 49 | MN_MOV_PSW_A, 50 | MN_MOV_RR, 51 | MN_MOV_RR_DATA, 52 | MN_MOV_T, 53 | MN_MOVD_A_PP, 54 | MN_MOVP, 55 | MN_MOVX, 56 | MN_NOP, 57 | MN_ORL, 58 | MN_ORL_A_DATA, 59 | MN_ORL_EXT, 60 | MN_OUTD_PP_A, 61 | MN_OUTL_EXT, 62 | MN_RET, 63 | MN_RL, 64 | MN_RR, 65 | MN_SEL_MB, 66 | MN_SEL_RB, 67 | MN_STOP_TCNT, 68 | MN_STRT, 69 | MN_SWAP, 70 | MN_XCH, 71 | MN_XRL, 72 | MN_XRL_A_DATA); 73 | 74 | end t48_decoder_pack; 75 | 76 | 77 | ------------------------------------------------------------------------------- 78 | -- File History: 79 | -- 80 | -- $Log: decoder_pack-p.vhd,v $ 81 | -- Revision 1.3 2005/06/11 10:08:43 arniml 82 | -- introduce prefix 't48_' for all packages, entities and configurations 83 | -- 84 | -- Revision 1.2 2004/03/28 13:09:53 arniml 85 | -- merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A 86 | -- 87 | -- Revision 1.1 2004/03/23 21:31:52 arniml 88 | -- initial check-in 89 | -- 90 | ------------------------------------------------------------------------------- 91 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t48_rom-struct-a.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8x48 ROM 4 | -- 5 | -- $Id: t48_rom-struct-a.vhd,v 1.1.1.3 2006/11/26 10:07:52 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | -- Redistribution and use in source and synthezised forms, with or without 12 | -- modification, are permitted provided that the following conditions are met: 13 | -- 14 | -- Redistributions of source code must retain the above copyright notice, 15 | -- this list of conditions and the following disclaimer. 16 | -- 17 | -- Redistributions in synthesized form must reproduce the above copyright 18 | -- notice, this list of conditions and the following disclaimer in the 19 | -- documentation and/or other materials provided with the distribution. 20 | -- 21 | -- Neither the name of the author nor the names of other contributors may 22 | -- be used to endorse or promote products derived from this software without 23 | -- specific prior written permission. 24 | -- 25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 | -- POSSIBILITY OF SUCH DAMAGE. 36 | -- 37 | -- Please report bugs to the author, but before you do so, please 38 | -- make sure that this is not a derivative work and that 39 | -- you have the latest version of this file. 40 | -- 41 | -- The latest version of this file can be found at: 42 | -- http://www.opencores.org/cvsweb.shtml/t48/ 43 | -- 44 | ------------------------------------------------------------------------------- 45 | 46 | architecture struct of t48_rom is 47 | 48 | component rom_t48 49 | port( 50 | Clk : in std_logic; 51 | A : in std_logic_vector(9 downto 0); 52 | D : out std_logic_vector(7 downto 0) 53 | ); 54 | end component; 55 | 56 | begin 57 | 58 | rom_b : rom_t48 59 | port map ( 60 | Clk => clk_i, 61 | A => rom_addr_i, 62 | D => rom_data_o 63 | ); 64 | 65 | end struct; 66 | 67 | 68 | ------------------------------------------------------------------------------- 69 | -- File History: 70 | -- 71 | -- $Log: t48_rom-struct-a.vhd,v $ 72 | -- Revision 1.1.1.3 2006/11/26 10:07:52 arnim 73 | -- incremental import for release 1.0 74 | -- 75 | -- Revision 1.3 2006/11/26 12:53:28 arniml 76 | -- fix entity port names 77 | -- 78 | -- Revision 1.2 2006/11/26 11:58:28 arniml 79 | -- fix component name 80 | -- 81 | -- Revision 1.1 2006/06/21 00:59:15 arniml 82 | -- initial check-in 83 | -- 84 | ------------------------------------------------------------------------------- 85 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t49_rom-struct-a.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8x49 ROM 4 | -- 5 | -- $Id: t49_rom-struct-a.vhd,v 1.1.1.3 2006/11/26 10:07:52 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | -- Redistribution and use in source and synthezised forms, with or without 12 | -- modification, are permitted provided that the following conditions are met: 13 | -- 14 | -- Redistributions of source code must retain the above copyright notice, 15 | -- this list of conditions and the following disclaimer. 16 | -- 17 | -- Redistributions in synthesized form must reproduce the above copyright 18 | -- notice, this list of conditions and the following disclaimer in the 19 | -- documentation and/or other materials provided with the distribution. 20 | -- 21 | -- Neither the name of the author nor the names of other contributors may 22 | -- be used to endorse or promote products derived from this software without 23 | -- specific prior written permission. 24 | -- 25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 | -- POSSIBILITY OF SUCH DAMAGE. 36 | -- 37 | -- Please report bugs to the author, but before you do so, please 38 | -- make sure that this is not a derivative work and that 39 | -- you have the latest version of this file. 40 | -- 41 | -- The latest version of this file can be found at: 42 | -- http://www.opencores.org/cvsweb.shtml/t48/ 43 | -- 44 | ------------------------------------------------------------------------------- 45 | 46 | architecture struct of t49_rom is 47 | 48 | component rom_t49 49 | port( 50 | Clk : in std_logic; 51 | A : in std_logic_vector(10 downto 0); 52 | D : out std_logic_vector( 7 downto 0) 53 | ); 54 | end component; 55 | 56 | begin 57 | 58 | rom_b : rom_t49 59 | port map ( 60 | Clk => clk_i, 61 | A => rom_addr_i, 62 | D => rom_data_o 63 | ); 64 | 65 | end struct; 66 | 67 | 68 | ------------------------------------------------------------------------------- 69 | -- File History: 70 | -- 71 | -- $Log: t49_rom-struct-a.vhd,v $ 72 | -- Revision 1.1.1.3 2006/11/26 10:07:52 arnim 73 | -- incremental import for release 1.0 74 | -- 75 | -- Revision 1.3 2006/11/26 12:53:28 arniml 76 | -- fix entity port names 77 | -- 78 | -- Revision 1.2 2006/11/26 11:58:28 arniml 79 | -- fix component name 80 | -- 81 | -- Revision 1.1 2006/06/21 00:59:15 arniml 82 | -- initial check-in 83 | -- 84 | ------------------------------------------------------------------------------- 85 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/m58715ip.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | // Mario Bros Arcade 3 | // 4 | // Author: gaz68 (https://github.com/gaz68) June 2020 5 | // 6 | // M58715 module. 7 | // The M58715 chip produces the digital sounds (music and most 8 | // of the sound effects). It is an 8039 with embedded RAM and ROM. 9 | // The embedded ROM appears to only be used for protection. 10 | // see mario_roms.v for more information. 11 | //---------------------------------------------------------------------------- 12 | 13 | module M58715IP( 14 | 15 | I_CLK, 16 | I_CLK_EN, 17 | I_RSTn, 18 | I_INTn, 19 | I_EA, 20 | O_PSENn, 21 | O_RDn, 22 | O_WRn, 23 | O_ALE, 24 | O_PROGn, 25 | I_T0, 26 | O_T0, 27 | I_T1, 28 | I_DB, 29 | O_DB, 30 | I_P1, 31 | O_P1, 32 | I_P2, 33 | O_P2 34 | ); 35 | 36 | input I_CLK; 37 | input I_CLK_EN; 38 | input I_RSTn; 39 | input I_INTn; 40 | input I_EA; 41 | output O_PSENn; 42 | output O_RDn; 43 | output O_WRn; 44 | output O_ALE; 45 | output O_PROGn; 46 | input I_T0; 47 | output O_T0; 48 | input I_T1; 49 | input [7:0]I_DB; 50 | output [7:0]O_DB; 51 | input [7:0]I_P1; 52 | output [7:0]O_P1; 53 | input [7:0]I_P2; 54 | output [7:0]O_P2; 55 | 56 | wire W_PSENn; 57 | assign O_PSENn = W_PSENn ; 58 | 59 | //---------------------------------- 60 | // M58715 has 128-Byte internal RAM 61 | //---------------------------------- 62 | 63 | wire [7:0]t48_ram_a; 64 | wire t48_ram_we; 65 | wire [7:0]t48_ram_do; 66 | wire [7:0]t48_ram_di; 67 | 68 | ram_128_8 t48_ram 69 | ( 70 | .I_CLK(I_CLK), 71 | .I_ADDR(t48_ram_a[6:0]), 72 | .I_D(t48_ram_di), 73 | .I_CE(1'b1), 74 | .I_WE(t48_ram_we), 75 | .O_D(t48_ram_do) 76 | ); 77 | 78 | //----------------------------------- 79 | // M58715 has 2KB internal ROM 80 | // 81 | // * Using the 8039 hack to bypass 82 | // the internal ROM until the pmem 83 | // interface can be made to work. 84 | // All ROM accesses are external. 85 | //------------------------------------ 86 | 87 | //wire [10:0]t48_int_rom_a; 88 | //wire [7:0]t48_int_rom_do; 89 | // 90 | //SUB_INT_ROM bootrom 91 | //( 92 | // .CLK(I_CLK), 93 | // .AD(t48_int_rom_a), 94 | // .DO(t48_int_rom_do) 95 | //); 96 | 97 | //---------- 98 | // T48 Core 99 | //---------- 100 | 101 | wire xtal3_s; 102 | 103 | t48_core t48_core 104 | ( 105 | .xtal_i(I_CLK), 106 | .xtal_en_i(I_CLK_EN), 107 | .reset_i(I_RSTn), 108 | .t0_i(I_T0), 109 | .t0_o(O_T0), 110 | .t0_dir_o(), 111 | .int_n_i(I_INTn), 112 | //.ea_i(I_EA), 113 | .ea_i(1'b1), // 8039 hack 114 | .rd_n_o(O_RDn), 115 | .psen_n_o(W_PSENn), 116 | .wr_n_o(O_WRn), 117 | .ale_o(O_ALE), 118 | .db_i(I_DB), 119 | .db_o(O_DB), 120 | .db_dir_o(), 121 | .t1_i(I_T1), 122 | .p2_i(I_P2), 123 | .p2_o(O_P2), 124 | .p2_low_imp_o(), 125 | .p1_i(I_P1), 126 | .p1_o(O_P1), 127 | .p1_low_imp_o(), 128 | .prog_n_o(O_PROGn), 129 | .clk_i(I_CLK), 130 | .en_clk_i(xtal3_s), 131 | .xtal3_o(xtal3_s), 132 | .dmem_addr_o(t48_ram_a), 133 | .dmem_we_o(t48_ram_we), 134 | .dmem_data_i(t48_ram_do), 135 | .dmem_data_o(t48_ram_di), 136 | .pmem_addr_o(), // pmem interface not used. 137 | .pmem_data_i(8'h00) 138 | //.pmem_addr_o(t48_int_rom_a), 139 | //.pmem_data_i(t48_int_rom_do) 140 | ); 141 | 142 | endmodule 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/t48_core_comp_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: t48_core_comp_pack-p.vhd,v 1.5 2006/06/21 01:03:28 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | library ieee; 12 | use ieee.std_logic_1164.all; 13 | 14 | package t48_core_comp_pack is 15 | 16 | component t48_core 17 | generic ( 18 | xtal_div_3_g : integer := 1; 19 | register_mnemonic_g : integer := 1; 20 | include_port1_g : integer := 1; 21 | include_port2_g : integer := 1; 22 | include_bus_g : integer := 1; 23 | include_timer_g : integer := 1; 24 | sample_t1_state_g : integer := 4 25 | ); 26 | 27 | port ( 28 | xtal_i : in std_logic; 29 | xtal_en_i : in std_logic; 30 | reset_i : in std_logic; 31 | t0_i : in std_logic; 32 | t0_o : out std_logic; 33 | t0_dir_o : out std_logic; 34 | int_n_i : in std_logic; 35 | ea_i : in std_logic; 36 | rd_n_o : out std_logic; 37 | psen_n_o : out std_logic; 38 | wr_n_o : out std_logic; 39 | ale_o : out std_logic; 40 | db_i : in std_logic_vector( 7 downto 0); 41 | db_o : out std_logic_vector( 7 downto 0); 42 | db_dir_o : out std_logic; 43 | t1_i : in std_logic; 44 | p2_i : in std_logic_vector( 7 downto 0); 45 | p2_o : out std_logic_vector( 7 downto 0); 46 | p2l_low_imp_o : out std_logic; 47 | p2h_low_imp_o : out std_logic; 48 | p1_i : in std_logic_vector( 7 downto 0); 49 | p1_o : out std_logic_vector( 7 downto 0); 50 | p1_low_imp_o : out std_logic; 51 | prog_n_o : out std_logic; 52 | clk_i : in std_logic; 53 | en_clk_i : in std_logic; 54 | xtal3_o : out std_logic; 55 | dmem_addr_o : out std_logic_vector( 7 downto 0); 56 | dmem_we_o : out std_logic; 57 | dmem_data_i : in std_logic_vector( 7 downto 0); 58 | dmem_data_o : out std_logic_vector( 7 downto 0); 59 | pmem_addr_o : out std_logic_vector(11 downto 0); 60 | pmem_data_i : in std_logic_vector( 7 downto 0) 61 | ); 62 | end component; 63 | 64 | component generic_ram_ena 65 | generic ( 66 | addr_width_g : integer := 10; 67 | data_width_g : integer := 8 68 | ); 69 | port ( 70 | clk_i : in std_logic; 71 | a_i : in std_logic_vector(addr_width_g-1 downto 0); 72 | we_i : in std_logic; 73 | ena_i : in std_logic; 74 | d_i : in std_logic_vector(data_width_g-1 downto 0); 75 | d_o : out std_logic_vector(data_width_g-1 downto 0) 76 | ); 77 | end component; 78 | 79 | component t48_rom 80 | port ( 81 | clk_i : in std_logic; 82 | rom_addr_i : in std_logic_vector(9 downto 0); 83 | rom_data_o : out std_logic_vector(7 downto 0) 84 | ); 85 | end component; 86 | 87 | component t49_rom 88 | port ( 89 | clk_i : in std_logic; 90 | rom_addr_i : in std_logic_vector(10 downto 0); 91 | rom_data_o : out std_logic_vector( 7 downto 0) 92 | ); 93 | end component; 94 | 95 | end t48_core_comp_pack; 96 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_hv_generator.v: -------------------------------------------------------------------------------- 1 | //=============================================================================== 2 | // FPGA DONKEY KONG H&V COUNTER 3 | // 4 | // Version : 2.00 5 | // 6 | // Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved 7 | // 8 | // Important ! 9 | // 10 | // This program is freeware for non-commercial use. 11 | // An author does no guarantee about this program. 12 | // You can use this under your own risk. 13 | // 14 | // 2005- 2- 9 some changed. 15 | //================================================================================ 16 | //----------------------------------------------------------------------------------------- 17 | // H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8],H_CNT[9] 18 | // 1/2 H 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H 19 | //----------------------------------------------------------------------------------------- 20 | // V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] 21 | // 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V 22 | //----------------------------------------------------------------------------------------- 23 | // VF_CNT[0],VF_CNT[1],VF_CNT[2],VF_CNT[3],VF_CNT[4],VF_CNT[5],VF_CNT[6],VF_CNT[7] 24 | // 1 VF 2 VF 4 VF 8 VF 16 VF 32 VF 64 VF 128 VF 25 | 26 | 27 | module mario_hv_generator( 28 | input I_CLK, 29 | input I_CEN, 30 | input I_RST_n, 31 | input I_VFLIP, 32 | output [9:0]H_CNT, 33 | output [7:0]V_CNT, 34 | output [7:0]VF_CNT, 35 | output H_BLANKn, 36 | output V_BLANKn, 37 | output C_BLANKn, 38 | output H_SYNCn, 39 | output V_SYNCn, 40 | output VCKn 41 | ); 42 | 43 | parameter H_count = 768; 44 | parameter H_BL_P = 511; 45 | parameter H_BL_W = 767; 46 | parameter V_CL_P = 576; 47 | parameter V_CL_W = 640; 48 | parameter V_BL_P = 239; 49 | parameter V_BL_W = 15; 50 | 51 | reg [9:0]H_CNT_r = 0; 52 | always@(posedge I_CLK) 53 | begin 54 | if (I_CEN) 55 | H_CNT_r <= (H_CNT_r == H_count - 1'd1)? 0 : H_CNT_r + 1'd1 ; 56 | end 57 | 58 | assign H_CNT = H_CNT_r; 59 | 60 | reg H_BLANK = 1'b0; 61 | reg V_CLK = 1'b0; 62 | reg V_CLK_q; 63 | 64 | always@(posedge I_CLK) begin 65 | if (H_CNT == H_BL_P) 66 | H_BLANK <= 1'b1; 67 | else if (H_CNT == H_BL_W) 68 | H_BLANK <= 1'b0; 69 | 70 | if (H_CNT == V_CL_P) 71 | V_CLK <= 1'b1; 72 | else if (H_CNT == V_CL_W) 73 | V_CLK <= 1'b0; 74 | 75 | V_CLK_q <= V_CLK; 76 | end 77 | 78 | assign H_SYNCn = ~V_CLK; 79 | assign H_BLANKn = ~H_BLANK; 80 | 81 | wire V_CLK_EN = ~V_CLK_q & V_CLK; 82 | 83 | 84 | reg [8:0]V_CNT_r; 85 | always@(posedge I_CLK or negedge I_RST_n) 86 | begin 87 | if(I_RST_n == 1'b0) 88 | V_CNT_r <= 0 ; 89 | else if (V_CLK_EN) 90 | V_CNT_r <= (V_CNT_r == 255)? 9'd504 : V_CNT_r + 1'd1; 91 | end 92 | 93 | reg V_BLANK; 94 | always@(posedge I_CLK or negedge I_RST_n) 95 | begin 96 | if(I_RST_n == 1'b0)begin 97 | V_BLANK <= 1'b0; 98 | end 99 | else if (V_CLK_EN) begin 100 | if (V_CNT_r == V_BL_P) 101 | V_BLANK <= 1'b1; 102 | else if (V_CNT_r == V_BL_W) 103 | V_BLANK <= 1'b0; 104 | end 105 | end 106 | 107 | assign V_CNT[7:0] = V_CNT_r[7:0]; 108 | assign V_SYNCn = ~V_CNT_r[8]; 109 | assign V_BLANKn = ~V_BLANK; 110 | assign C_BLANKn = ~(H_BLANK | V_BLANK); 111 | assign VF_CNT[7:0]= V_CNT ^ {8{I_VFLIP}}; 112 | assign VCKn = V_CLK; 113 | 114 | endmodule 115 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_sound_analog.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | // Mario Bros Arcade 3 | // 4 | // Author: gaz68 (https://github.com/gaz68) June 2020 5 | // 6 | // Analogue sounds (samples). 7 | // Mario run, Luigi run and skid sounds. 8 | //---------------------------------------------------------------------------- 9 | 10 | module mario_sound_analog 11 | ( 12 | input I_CLK_48M, 13 | input I_RESETn, 14 | 15 | input [2:0]I_SND_CTRL, 16 | input [3:0]I_ANLG_VOL, 17 | input [3:0]I_H_CNT, 18 | 19 | input [16:0]I_DLADDR, 20 | input [7:0]I_DLDATA, 21 | input I_DLWR, 22 | 23 | output signed [15:0]O_WAVROM_DS0, 24 | output signed [15:0]O_WAVROM_DS1, 25 | output signed [15:0]O_WAVROM_DS2 26 | ); 27 | 28 | //----------------------- 29 | // Extra ROM for samples 30 | //----------------------- 31 | 32 | reg [12:0]WAVROM_ADDR; 33 | wire [15:0]W_WAVROM_DO; 34 | 35 | WAV_ROM wavrom(I_CLK_48M, WAVROM_ADDR, W_WAVROM_DO, 36 | I_CLK_48M, I_DLADDR, I_DLDATA, I_DLWR); 37 | 38 | wire signed [15:0]W_WAVROM_DS[0:3]; 39 | wire [12:0]W_WAVROM_A[0:3]; 40 | 41 | //------------ 42 | // Skid sound 43 | //------------ 44 | mario_wav_sound skid_sound 45 | ( 46 | .I_CLK(I_CLK_48M), 47 | .I_RSTn(I_RESETn), 48 | .I_H_CNT(I_H_CNT[3:0]), 49 | .I_DIV(12'd2176), // 48Mhz / 2176 = 22,050Hz 50 | .I_VOL(I_ANLG_VOL), 51 | .I_DMA_TRIG(~I_SND_CTRL[0]), 52 | .I_DMA_STOP(1'b0), 53 | .I_RETRIG_EN(1'b1), 54 | .I_DMA_CHAN(3'd0), 55 | .I_DMA_ADDR(16'h0000), 56 | .I_DMA_LEN(16'h0800), 57 | .I_DMA_DATA(W_WAVROM_DO), // Sample data from wave ROM. 58 | .O_DMA_ADDR(W_WAVROM_A[0]), // Wave ROM address. 59 | .O_SND(W_WAVROM_DS[0]) 60 | ); 61 | 62 | assign O_WAVROM_DS0 = W_WAVROM_DS[0]; 63 | 64 | //----------------- 65 | // Mario run sound 66 | //----------------- 67 | mario_wav_sound mario_run_sound 68 | ( 69 | .I_CLK(I_CLK_48M), 70 | .I_RSTn(I_RESETn), 71 | .I_H_CNT(I_H_CNT[3:0]), 72 | .I_DIV(12'd2176), 73 | .I_VOL(I_ANLG_VOL), 74 | .I_DMA_TRIG(~I_SND_CTRL[1]), 75 | .I_DMA_STOP(1'b0), 76 | .I_RETRIG_EN(1'b0), 77 | .I_DMA_CHAN(3'd1), 78 | .I_DMA_ADDR(16'h0800), 79 | .I_DMA_LEN(16'h0800), 80 | .I_DMA_DATA(W_WAVROM_DO), 81 | .O_DMA_ADDR(W_WAVROM_A[1]), 82 | .O_SND(W_WAVROM_DS[1]) 83 | ); 84 | 85 | assign O_WAVROM_DS1 = W_WAVROM_DS[1]; 86 | 87 | //----------------- 88 | // Luigi run sound 89 | //----------------- 90 | mario_wav_sound luigi_run_sound 91 | ( 92 | .I_CLK(I_CLK_48M), 93 | .I_RSTn(I_RESETn), 94 | .I_H_CNT(I_H_CNT[3:0]), 95 | .I_DIV(12'd2176), 96 | .I_VOL(I_ANLG_VOL), 97 | .I_DMA_TRIG(~I_SND_CTRL[2]), 98 | .I_DMA_STOP(1'b0), 99 | .I_RETRIG_EN(1'b0), 100 | .I_DMA_CHAN(3'd2), 101 | .I_DMA_ADDR(16'h1000), 102 | .I_DMA_LEN(16'h0800), 103 | .I_DMA_DATA(W_WAVROM_DO), 104 | .O_DMA_ADDR(W_WAVROM_A[2]), 105 | .O_SND(W_WAVROM_DS[2]) 106 | ); 107 | 108 | assign O_WAVROM_DS2 = W_WAVROM_DS[2]; 109 | 110 | //-------------------------------- 111 | // Sample ROM address bus sharing 112 | //-------------------------------- 113 | 114 | always @(posedge I_CLK_48M or negedge I_RESETn) 115 | begin 116 | if(! I_RESETn)begin 117 | 118 | WAVROM_ADDR <= 0; 119 | 120 | end else begin 121 | 122 | case(I_H_CNT[3:0]) 123 | 0: WAVROM_ADDR <= W_WAVROM_A[0]; 124 | 2: WAVROM_ADDR <= W_WAVROM_A[1]; 125 | 4: WAVROM_ADDR <= W_WAVROM_A[2]; 126 | default:; 127 | endcase 128 | 129 | end 130 | end 131 | 132 | endmodule 133 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/generic_ram_ena.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- Parametrizable, generic RAM with enable. 4 | -- 5 | -- $Id: generic_ram_ena.vhd,v 1.1.1.1 2006/11/25 22:15:41 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | -- Redistribution and use in source and synthezised forms, with or without 12 | -- modification, are permitted provided that the following conditions are met: 13 | -- 14 | -- Redistributions of source code must retain the above copyright notice, 15 | -- this list of conditions and the following disclaimer. 16 | -- 17 | -- Redistributions in synthesized form must reproduce the above copyright 18 | -- notice, this list of conditions and the following disclaimer in the 19 | -- documentation and/or other materials provided with the distribution. 20 | -- 21 | -- Neither the name of the author nor the names of other contributors may 22 | -- be used to endorse or promote products derived from this software without 23 | -- specific prior written permission. 24 | -- 25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 | -- POSSIBILITY OF SUCH DAMAGE. 36 | -- 37 | -- Please report bugs to the author, but before you do so, please 38 | -- make sure that this is not a derivative work and that 39 | -- you have the latest version of this file. 40 | -- 41 | -- The latest version of this file can be found at: 42 | -- http://www.opencores.org/cvsweb.shtml/t48/ 43 | -- 44 | ------------------------------------------------------------------------------- 45 | 46 | library ieee; 47 | use ieee.std_logic_1164.all; 48 | 49 | entity generic_ram_ena is 50 | 51 | generic ( 52 | addr_width_g : integer := 10; 53 | data_width_g : integer := 8 54 | ); 55 | port ( 56 | clk_i : in std_logic; 57 | a_i : in std_logic_vector(addr_width_g-1 downto 0); 58 | we_i : in std_logic; 59 | ena_i : in std_logic; 60 | d_i : in std_logic_vector(data_width_g-1 downto 0); 61 | d_o : out std_logic_vector(data_width_g-1 downto 0) 62 | ); 63 | 64 | end generic_ram_ena; 65 | 66 | 67 | library ieee; 68 | use ieee.numeric_std.all; 69 | 70 | architecture rtl of generic_ram_ena is 71 | 72 | type mem_t is array (natural range 0 to 2**addr_width_g-1) of 73 | std_logic_vector(d_i'range); 74 | signal mem_q : mem_t 75 | -- pragma translate_off 76 | := (others => (others => '0')) 77 | -- pragma translate_on 78 | ; 79 | signal a_q : std_logic_vector(a_i'range); 80 | 81 | begin 82 | 83 | mem: process (clk_i) 84 | begin 85 | 86 | if clk_i'event and clk_i = '1' then 87 | if ena_i = '1' then 88 | if we_i = '1' then 89 | mem_q(to_integer(unsigned(a_i))) <= d_i; 90 | end if; 91 | 92 | a_q <= a_i; 93 | end if; 94 | 95 | end if; 96 | end process mem; 97 | 98 | d_o <= mem_q(to_integer(unsigned(a_q))); 99 | 100 | end rtl; 101 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_wav_sound.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | // Mario Bros Arcade 3 | // 4 | // Author: gaz68 (https://github.com/gaz68) June 2020 5 | // 6 | // Sound sample player. 7 | // Up to 8 channels. 16-bit signed samples. 8 | // This version supports re-triggerable samples. 9 | // Workaround for Mario Bros analogue sounds. 10 | // TO DO: Proper synthesis/simulation of analogue sounds. 11 | //---------------------------------------------------------------------------- 12 | 13 | module mario_wav_sound 14 | ( 15 | input I_CLK, 16 | input I_RSTn, 17 | input [3:0]I_H_CNT, 18 | input [11:0]I_DIV, 19 | input [3:0]I_VOL, 20 | input I_DMA_TRIG, 21 | input I_DMA_STOP, 22 | input I_RETRIG_EN, // Allow sample to be retriggered during playback 23 | input [2:0]I_DMA_CHAN, // 8 channels 24 | input [15:0]I_DMA_ADDR, 25 | input [15:0]I_DMA_LEN, 26 | input signed [15:0]I_DMA_DATA, // Data coming back from wave ROM 27 | 28 | output [15:0]O_DMA_ADDR, // Output address to wave ROM 29 | output signed [15:0]O_SND 30 | ); 31 | 32 | reg [15:0]W_DMA_ADDR; 33 | reg signed [23:0]W_DMA_DATA; 34 | reg [15:0]W_DMA_CNT; 35 | reg W_DMA_EN = 1'b0; 36 | reg [11:0]sample; 37 | reg W_DMA_TRIG; 38 | reg signed [15:0]W_SAMPL; 39 | reg signed [8:0]W_VOL; 40 | 41 | always@(posedge I_CLK or negedge I_RSTn) 42 | begin 43 | 44 | if(! I_RSTn)begin 45 | 46 | W_DMA_EN <= 1'b0; 47 | W_DMA_CNT <= 0; 48 | W_DMA_DATA <= 0; 49 | W_DMA_ADDR <= 0; 50 | W_DMA_TRIG <= 0; 51 | W_VOL <= 0; 52 | sample <= 0; 53 | 54 | end else begin 55 | 56 | // Check for DMA trigger and enable DMA. 57 | W_DMA_TRIG <= I_DMA_TRIG; 58 | 59 | if(~W_DMA_TRIG & I_DMA_TRIG) begin 60 | 61 | if (W_DMA_EN==1'b0 || (W_DMA_EN==1'b1 & I_RETRIG_EN)) begin 62 | 63 | W_DMA_ADDR <= I_DMA_ADDR; 64 | W_DMA_CNT <= 0; 65 | W_DMA_EN <= 1'b1; 66 | W_DMA_DATA <= 0; 67 | sample <= 0; 68 | 69 | end 70 | 71 | end else if (W_DMA_EN == 1'b1) begin 72 | 73 | case(I_VOL) 74 | 0: W_VOL <= 9'sd255; // 100% 75 | 1: W_VOL <= 9'sd0; // OFF 76 | 2: W_VOL <= 9'sd26; // 10% 77 | 3: W_VOL <= 9'sd52; // 20% 78 | 4: W_VOL <= 9'sd79; // 30% 79 | 5: W_VOL <= 9'sd104; // 40% 80 | 6: W_VOL <= 9'sd130; // 50% 81 | 7: W_VOL <= 9'sd156; // 60% 82 | 8: W_VOL <= 9'sd182; // 70% 83 | 9: W_VOL <= 9'sd208; // 80% 84 | 10: W_VOL <= 9'sd234; // 90% 85 | default: W_VOL <= 9'sd255; 86 | endcase 87 | 88 | // Prefetch sample. 89 | if (I_H_CNT == {I_DMA_CHAN,1'b1}) begin 90 | W_DMA_DATA <= I_DMA_DATA * W_VOL; 91 | end 92 | 93 | sample <= (sample == I_DIV-1) ? 1'b0 : sample + 1'b1; 94 | 95 | if (sample == I_DIV-1) begin 96 | W_SAMPL <= W_DMA_DATA[23:8]; 97 | W_DMA_ADDR <= W_DMA_ADDR + 1'd1; 98 | W_DMA_CNT <= W_DMA_CNT + 1'd1; 99 | W_DMA_EN <= (W_DMA_CNT==I_DMA_LEN) || I_DMA_STOP ? 1'b0 : 1'b1; 100 | end 101 | 102 | end else begin 103 | 104 | W_DMA_ADDR <= 0; 105 | W_SAMPL <= 0; 106 | 107 | end 108 | 109 | end 110 | 111 | end 112 | 113 | assign O_DMA_ADDR = W_DMA_ADDR; 114 | assign O_SND = W_SAMPL; 115 | 116 | endmodule 117 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/T80/Z80.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.std_logic_1164.all; 3 | library work; 4 | use work.T80_Pack.all; 5 | 6 | entity Z80 is port 7 | ( 8 | clk : in std_logic; 9 | clk_en : in std_logic; 10 | reset : in std_logic; 11 | 12 | addr : out std_logic_vector(15 downto 0); 13 | datai : in std_logic_vector(7 downto 0); 14 | datao : out std_logic_vector(7 downto 0); 15 | 16 | m1 : out std_logic; 17 | mem_rd : out std_logic; 18 | mem_wr : out std_logic; 19 | io_rd : out std_logic; 20 | io_wr : out std_logic; 21 | 22 | wait_n : in std_logic := '1'; 23 | busrq_n : in std_logic := '1'; 24 | intreq : in std_logic := '0'; 25 | intvec : in std_logic_vector(7 downto 0); 26 | intack : out std_logic; 27 | nmi : in std_logic := '0' 28 | ); 29 | end Z80; 30 | 31 | architecture SYN of Z80 is 32 | 33 | component T80se is 34 | generic 35 | ( 36 | Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB 37 | T2Write : integer := 1 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 38 | ); 39 | port 40 | ( 41 | RESET_n : in std_logic; 42 | CLK_n : in std_logic; 43 | CLKEN : in std_logic; 44 | WAIT_n : in std_logic; 45 | INT_n : in std_logic; 46 | NMI_n : in std_logic; 47 | BUSRQ_n : in std_logic; 48 | M1_n : out std_logic; 49 | MREQ_n : out std_logic; 50 | IORQ_n : out std_logic; 51 | RD_n : out std_logic; 52 | WR_n : out std_logic; 53 | RFSH_n : out std_logic; 54 | HALT_n : out std_logic; 55 | BUSAK_n : out std_logic; 56 | A : out std_logic_vector(15 downto 0); 57 | DI : in std_logic_vector(7 downto 0); 58 | DO : out std_logic_vector(7 downto 0) 59 | ); 60 | end component T80se; 61 | 62 | -- Signal Declarations 63 | 64 | signal reset_n : std_logic; 65 | signal int_n : std_logic; 66 | signal nmi_n : std_logic; 67 | 68 | signal z80_m1 : std_logic; 69 | signal z80_memreq : std_logic; 70 | signal z80_ioreq : std_logic; 71 | signal z80_rd : std_logic; 72 | signal z80_wr : std_logic; 73 | signal z80_datai : std_logic_vector(7 downto 0); 74 | 75 | -- derived signals (outputs we need to read) 76 | signal z80_memrd : std_logic; 77 | signal z80_iord : std_logic; 78 | signal fetch : std_logic; 79 | 80 | begin 81 | 82 | -- simple inversions 83 | reset_n <= not reset; 84 | int_n <= not intreq; 85 | nmi_n <= not nmi; 86 | 87 | -- direct-connect (outputs we need to read) 88 | m1 <= z80_m1; 89 | mem_rd <= z80_memrd; 90 | io_rd <= z80_iord; 91 | 92 | -- memory signals 93 | z80_memrd <= z80_memreq nor z80_rd; 94 | mem_wr <= z80_memreq nor z80_wr; 95 | 96 | -- io signals 97 | z80_iord <= z80_ioreq nor z80_rd; 98 | io_wr <= z80_ioreq nor z80_wr; 99 | 100 | -- other signals 101 | fetch <= z80_m1 nor z80_memreq; 102 | intack <= z80_m1 nor z80_ioreq; 103 | 104 | -- data in mux 105 | z80_datai <= intvec when ((z80_memrd or z80_iord) = '0') else 106 | datai; 107 | 108 | Z80_uP : T80se 109 | generic map 110 | ( 111 | Mode => 0 -- Z80 112 | ) 113 | port map 114 | ( 115 | RESET_n => reset_n, 116 | CLK_n => clk, 117 | CLKEN => clk_en, 118 | WAIT_n => wait_n, 119 | INT_n => int_n, 120 | NMI_n => nmi_n, 121 | BUSRQ_n => busrq_n, 122 | M1_n => z80_m1, 123 | MREQ_n => z80_memreq, 124 | IORQ_n => z80_ioreq, 125 | RD_n => z80_rd, 126 | WR_n => z80_wr, 127 | RFSH_n => open, 128 | HALT_n => open, 129 | BUSAK_n => open, 130 | A => addr, 131 | DI => z80_datai, 132 | DO => datao 133 | ); 134 | 135 | end architecture SYN; 136 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/bus_mux.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The T48 Bus Connector. 4 | -- Multiplexes all drivers of the T48 bus. 5 | -- 6 | -- $Id: bus_mux.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | -- Redistribution and use in source and synthezised forms, with or without 13 | -- modification, are permitted provided that the following conditions are met: 14 | -- 15 | -- Redistributions of source code must retain the above copyright notice, 16 | -- this list of conditions and the following disclaimer. 17 | -- 18 | -- Redistributions in synthesized form must reproduce the above copyright 19 | -- notice, this list of conditions and the following disclaimer in the 20 | -- documentation and/or other materials provided with the distribution. 21 | -- 22 | -- Neither the name of the author nor the names of other contributors may 23 | -- be used to endorse or promote products derived from this software without 24 | -- specific prior written permission. 25 | -- 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 | -- POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | -- Please report bugs to the author, but before you do so, please 39 | -- make sure that this is not a derivative work and that 40 | -- you have the latest version of this file. 41 | -- 42 | -- The latest version of this file can be found at: 43 | -- http://www.opencores.org/cvsweb.shtml/t48/ 44 | -- 45 | ------------------------------------------------------------------------------- 46 | 47 | library ieee; 48 | use ieee.std_logic_1164.all; 49 | 50 | use work.t48_pack.word_t; 51 | 52 | entity t48_bus_mux is 53 | 54 | port ( 55 | alu_data_i : in word_t; 56 | bus_data_i : in word_t; 57 | dec_data_i : in word_t; 58 | dm_data_i : in word_t; 59 | pm_data_i : in word_t; 60 | p1_data_i : in word_t; 61 | p2_data_i : in word_t; 62 | psw_data_i : in word_t; 63 | tim_data_i : in word_t; 64 | data_o : out word_t 65 | ); 66 | 67 | end t48_bus_mux; 68 | 69 | 70 | use work.t48_pack.bus_idle_level_c; 71 | 72 | architecture rtl of t48_bus_mux is 73 | 74 | begin 75 | 76 | or_tree: if bus_idle_level_c = '0' generate 77 | data_o <= alu_data_i or 78 | bus_data_i or 79 | dec_data_i or 80 | dm_data_i or 81 | pm_data_i or 82 | p1_data_i or 83 | p2_data_i or 84 | psw_data_i or 85 | tim_data_i; 86 | end generate; 87 | 88 | and_tree: if bus_idle_level_c = '1' generate 89 | data_o <= alu_data_i and 90 | bus_data_i and 91 | dec_data_i and 92 | dm_data_i and 93 | pm_data_i and 94 | p1_data_i and 95 | p2_data_i and 96 | psw_data_i and 97 | tim_data_i; 98 | end generate; 99 | 100 | end rtl; 101 | 102 | 103 | ------------------------------------------------------------------------------- 104 | -- File History: 105 | -- 106 | -- $Log: bus_mux.vhd,v $ 107 | -- Revision 1.2 2005/06/11 10:08:43 arniml 108 | -- introduce prefix 't48_' for all packages, entities and configurations 109 | -- 110 | -- Revision 1.1 2004/03/23 21:31:52 arniml 111 | -- initial check-in 112 | -- 113 | ------------------------------------------------------------------------------- 114 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/pause.v: -------------------------------------------------------------------------------- 1 | //============================================================================ 2 | // Generic pause handling for MiSTer cores. 3 | // 4 | // https://github.com/JimmyStones/Pause_MiSTer 5 | // 6 | // Copyright (c) 2021 Jim Gregory 7 | // 8 | // This program is free software; you can redistribute it and/or modify it 9 | // under the terms of the GNU General Public License as published by the Free 10 | // Software Foundation; either version 3 of the License, or (at your option) 11 | // any later version. 12 | // 13 | // This program is distributed in the hope that it will be useful, but WITHOUT 14 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 | // more details. 17 | // 18 | // You should have received a copy of the GNU General Public License along 19 | // with this program; if not, write to the Free Software Foundation, Inc., 20 | // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21 | //============================================================================ 22 | /* 23 | Features: 24 | - Pause can be triggered by user input, hiscore module or OSD opening (optionally controlled by setting in OSD) 25 | - When paused the RGB outputs will be halved after 10 seconds to reduce burn-in (optionally controlled by setting in OSD) 26 | - Reset signal will cancel user triggered pause 27 | 28 | Version history: 29 | 0001 - 2021-03-15 - First marked release 30 | 0002 - 2021-08-28 - Add optional output of dim_video signal (currently used by Galaga) 31 | ============================================================================ 32 | */ 33 | module pause #( 34 | parameter RW=8, // Width of red channel 35 | parameter GW=8, // Width of green channel 36 | parameter BW=8, // Width of blue channel 37 | parameter CLKSPD = 12 // Main clock speed in MHz 38 | ) 39 | ( 40 | input clk_sys, // Core system clock (should match HPS module) 41 | input reset, // CPU reset signal (active-high) 42 | input user_button, // User pause button signal (active-high) 43 | input pause_request, // Pause requested by other code (active-high) 44 | input [1:0] options, // Pause options from OSD 45 | // [0] = pause in OSD (active-high) 46 | // [1] = dim video (active-high) 47 | input OSD_STATUS, // OSD is open (active-high) 48 | input [(RW-1):0] r, // Red channel 49 | input [(GW-1):0] g, // Green channel 50 | input [(BW-1):0] b, // Blue channel 51 | 52 | output pause_cpu, // Pause signal to CPU (active-high) 53 | `ifdef PAUSE_OUTPUT_DIM 54 | output dim_video, // Dim video requested (active-high) 55 | `endif 56 | output [(RW+GW+BW-1):0] rgb_out // RGB output to arcade_video module 57 | 58 | ); 59 | 60 | // Option constants 61 | localparam pause_in_osd = 1'b0; 62 | localparam dim_video_timer= 1'b1; 63 | 64 | reg pause_toggle = 1'b0; // User paused (active-high) 65 | reg [31:0] pause_timer = 1'b0; // Time since pause 66 | reg [31:0] dim_timeout = (CLKSPD*10000000); // Time until video output dim (10 seconds @ CLKSPD Mhz) 67 | `ifndef PAUSE_OUTPUT_DIM 68 | wire dim_video; // Dim video requested (active-high) 69 | `endif 70 | 71 | assign pause_cpu = (pause_request | pause_toggle | (OSD_STATUS & options[pause_in_osd])) & !reset; 72 | assign dim_video = (pause_timer >= dim_timeout); 73 | 74 | always @(posedge clk_sys) begin 75 | 76 | // Track user pause button down 77 | reg user_button_last; 78 | user_button_last <= user_button; 79 | if(!user_button_last & user_button) pause_toggle <= ~pause_toggle; 80 | 81 | // Clear user pause on reset 82 | if(pause_toggle & reset) pause_toggle <= 0; 83 | 84 | if(pause_cpu & options[dim_video_timer]) 85 | begin 86 | // Track pause duration for video dim 87 | if((pause_timer> 1,g >> 1, b >> 1} : {r,g,b}; 99 | 100 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_sound_digital.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | // Mario Bros Arcade 3 | // 4 | // Author: gaz68 (https://github.com/gaz68) June 2020 5 | // 6 | // Digital sound module. 7 | //---------------------------------------------------------------------------- 8 | 9 | module mario_sound_digital 10 | ( 11 | input I_CLK_48M, 12 | input I_CEN_12M, 13 | input I_CEN_11M, 14 | input I_RST, 15 | input I_DLCLK, 16 | input [16:0]I_DLADDR, 17 | input [7:0]I_DLDATA, 18 | input I_DLWR, 19 | input [7:0]I_SND_DATA, 20 | input [6:0]I_SND_CTRL, 21 | 22 | output signed [15:0]O_SND_DAC, 23 | output signed [15:0]O_SND_OUT 24 | ); 25 | 26 | //---------------- 27 | // Sub CPU M58715 28 | //---------------- 29 | 30 | wire [7:0]M58715_DBI; 31 | wire [7:0]M58715_DBO; 32 | wire [7:0]M58715_PAI; 33 | wire [7:0]M58715_PBI; 34 | wire M58715_ALE; 35 | wire M58715_RDn; 36 | wire M58715_WRn; 37 | wire M58715_PSENn; 38 | 39 | wire [7:0]M58715_PAO = {4'b0000, I_SND_CTRL[6:3]}; 40 | 41 | M58715IP SOUND_CPU 42 | ( 43 | .I_CLK(I_CLK_48M), 44 | .I_CLK_EN(I_CEN_11M), 45 | .I_RSTn(I_RST), 46 | .I_INTn(~I_SND_CTRL[0]), 47 | .I_EA(~M58715_PBI[5]), 48 | .O_PSENn(M58715_PSENn), 49 | .O_RDn(M58715_RDn), 50 | .O_WRn(M58715_WRn), 51 | .O_ALE(M58715_ALE), 52 | .O_PROGn(), 53 | .I_T0(I_SND_CTRL[1]), 54 | .O_T0(), 55 | .I_T1(I_SND_CTRL[2]), 56 | .I_DB(M58715_DBO), 57 | .O_DB(M58715_DBI), 58 | .I_P1(M58715_PAO), 59 | .O_P1(M58715_PAI), 60 | .I_P2(8'h00), 61 | .O_P2(M58715_PBI) 62 | ); 63 | 64 | //-------------------------------------------- 65 | // The Mario Bros schematics show a sound ROM 66 | // labelled as 2732 with the pinout of a 2764. 67 | // A 2732 is used on the real board with the 68 | // option of using a 2764. 69 | // M58715 has 2KB internal ROM. The External 70 | // 4KB ROM is accessed as 2 banks of 2KB. 71 | //-------------------------------------------- 72 | 73 | wire [11:0]S_ROM_A; 74 | reg [7:0]L_ROM_A; 75 | 76 | reg M58715_ALE_q; 77 | wire M58715_ALE_fall = M58715_ALE_q & ~M58715_ALE; 78 | always@(posedge I_CLK_48M) begin 79 | M58715_ALE_q <= M58715_ALE; 80 | end 81 | 82 | always@(posedge I_CLK_48M) begin 83 | if (M58715_ALE_fall) 84 | L_ROM_A <= M58715_DBI; 85 | end 86 | 87 | wire A12 = ~M58715_RDn & ~M58715_PBI[7]; 88 | wire S_ROM_OE = ~A12 & M58715_PSENn; 89 | 90 | assign S_ROM_A = {M58715_PBI[3:0],L_ROM_A[7:0]}; 91 | 92 | 93 | reg S_7J_OC; 94 | always@(posedge I_CLK_48M) begin 95 | if (I_CEN_12M) 96 | S_7J_OC <= ~(~M58715_RDn & M58715_PBI[7]); 97 | end 98 | 99 | wire [7:0]S_PROG_D; 100 | 101 | SUB_EXT_ROM srom5k(I_CLK_48M, S_ROM_A, 1'b0, S_ROM_OE, S_PROG_D, 102 | I_CLK_48M, I_DLADDR, I_DLDATA, I_DLWR); 103 | 104 | // M58715 Data Bus 105 | wire [7:0]M58715_DO = S_7J_OC == 1'b0 ? I_SND_DATA : S_PROG_D; 106 | 107 | reg [7:0]DO; 108 | always@(posedge I_CLK_48M) begin 109 | if (I_CEN_12M) 110 | DO <= M58715_DO; 111 | end 112 | assign M58715_DBO = DO; 113 | 114 | // Sound out 115 | reg [15:0]SND_DAC; 116 | 117 | reg M58715_WRn_q; 118 | wire M58715_WRn_rise = ~M58715_WRn_q & M58715_WRn; 119 | always@(posedge I_CLK_48M) begin 120 | M58715_WRn_q <= M58715_WRn; 121 | end 122 | 123 | always@(posedge I_CLK_48M) begin 124 | if (M58715_WRn_rise) 125 | SND_DAC <= {2{~M58715_DBI[7],M58715_DBI[6:0]}}; // 16-bit signed; 126 | end 127 | 128 | //----------------------------------------------------- 129 | // Sound filter 130 | // Low pass filter. f= 1178.9 Hz @ 48KHz. 131 | //----------------------------------------------------- 132 | 133 | // Reduce volume 134 | wire [15:0]W_SND_IN = {SND_DAC[15],SND_DAC[15:1]} + {{3{SND_DAC[15]}}, SND_DAC[15:3]}; 135 | 136 | wire [15:0]W_FILT_OUT; 137 | 138 | iir_1st_order filter 139 | ( 140 | .clk(I_CLK_48M), 141 | .reset(~I_RST), 142 | .div(12'd1000), // 48Mhz / 1000 = 48KHz 143 | .A2(-18'sd28065), 144 | .B1(18'sd2352), 145 | .B2(18'sd2352), 146 | .in(W_SND_IN), 147 | .out(W_FILT_OUT) 148 | ); 149 | 150 | assign O_SND_OUT = W_FILT_OUT; 151 | 152 | endmodule 153 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_video.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | // Mario Bros Arcade 3 | // 4 | // Author: gaz68 (https://github.com/gaz68) June 2020 5 | // 6 | // Top level video module. 7 | //---------------------------------------------------------------------------- 8 | 9 | module mario_video 10 | ( 11 | input I_CLK_48M, 12 | input I_CEN_24Mp, 13 | input I_CEN_24Mn, 14 | input I_CEN_6M, 15 | input I_CEN_12M, 16 | input I_RESETn, 17 | input [9:0]I_CPU_A, 18 | input [7:0]I_CPU_D, 19 | input I_VRAM_WRn, 20 | input I_VRAM_RDn, 21 | input [7:0]I_2L_Q, 22 | input I_VMOV, 23 | input [9:0]I_H_CNT, 24 | input [7:0]I_VF_CNT, 25 | input I_CBLANKn, 26 | input I_VBLKn, 27 | input I_VCKn, 28 | input [9:0]I_OBJDMA_A, 29 | input [7:0]I_OBJDMA_D, 30 | input I_OBJDMA_CE, 31 | input [16:0]I_DLADDR, 32 | input [7:0]I_DLDATA, 33 | input I_DLWR, 34 | 35 | output [7:0]O_VRAM_DB, 36 | output O_VRAMBUSYn, 37 | output O_FLIP_HV, 38 | output [7:0]O_OBJ_DB, 39 | output [2:0]O_VGA_RED, 40 | output [2:0]O_VGA_GRN, 41 | output [1:0]O_VGA_BLU 42 | ); 43 | 44 | //------------------ 45 | // VRAM 46 | // Background tiles 47 | //------------------ 48 | 49 | wire [3:0]W_VRAM_COL; 50 | wire [1:0]W_VRAM_VID; 51 | wire [7:0]W_VRAM_DB; 52 | wire W_VRAMBUSYn; 53 | wire W_TROMn = I_2L_Q[0]; 54 | 55 | mario_vram vram 56 | ( 57 | .I_CLK_48M(I_CLK_48M), 58 | .I_CEN_24Mp(I_CEN_24Mp), 59 | .I_CEN_24Mn(I_CEN_24Mn), 60 | .I_AB(I_CPU_A), 61 | .I_DB(I_CPU_D), 62 | .I_VRAM_WRn(I_VRAM_WRn), 63 | .I_VRAM_RDn(I_VRAM_RDn), 64 | .I_FLIP(W_FLIP_VRAM), 65 | .I_H_CNT(I_H_CNT), 66 | .I_CMPBLK(I_CBLANKn), 67 | .I_VBLKn(I_VBLKn), 68 | .I_VCKn(I_VCKn), 69 | .I_GFXBANK(W_TROMn), 70 | .I_VMOV(I_VMOV), 71 | .I_DLCLK(I_CLK_48M), 72 | .I_DLADDR(I_DLADDR), 73 | .I_DLDATA(I_DLDATA), 74 | .I_DLWR(I_DLWR), 75 | 76 | .O_DB(W_VRAM_DB), 77 | .O_COL(W_VRAM_COL), 78 | .O_VID(W_VRAM_VID), 79 | .O_VRAMBUSYn(W_VRAMBUSYn) 80 | ); 81 | 82 | wire [6:0]W_VRAM_DAT = {W_VRAM_COL[3:0],1'b0,W_VRAM_VID[1:0]}; 83 | 84 | assign O_VRAM_DB = W_VRAM_DB; 85 | assign O_VRAMBUSYn = W_VRAMBUSYn; 86 | 87 | //------------------- 88 | // Objects / Sprites 89 | //------------------- 90 | 91 | wire [6:0]W_OBJ_DAT; 92 | wire W_FLIP_VRAM; 93 | wire W_FLIP_HV; 94 | wire W_FLIPn = ~I_2L_Q[2]; 95 | wire W_2PSL = I_2L_Q[1]; 96 | wire W_L_CMPBLKn; 97 | wire [7:0]W_OBJ_DB; 98 | 99 | mario_obj sprites 100 | ( 101 | .I_CLK_48M(I_CLK_48M), 102 | .I_CEN_24Mp(I_CEN_24Mp), 103 | .I_CEN_24Mn(I_CEN_24Mn), 104 | .I_CEN_12M(I_CEN_12M), 105 | .I_AB(), // Not used 106 | .I_DB(/*W_2N_DO*/), // Not used 107 | .I_OBJ_WRn(1'b1), // Not used 108 | .I_OBJ_RDn(1'b1), // Not used 109 | .I_OBJ_RQn(1'b1), // Not used 110 | .I_2PSL(W_2PSL), 111 | .I_FLIPn(W_FLIPn), 112 | .I_CMPBLKn(I_CBLANKn), 113 | .I_H_CNT(I_H_CNT), 114 | .I_VF_CNT(I_VF_CNT), 115 | .I_OBJ_DMA_A(I_OBJDMA_A), 116 | .I_OBJ_DMA_D(I_OBJDMA_D), 117 | .I_OBJ_DMA_CE(I_OBJDMA_CE), 118 | .I_DLADDR(I_DLADDR), 119 | .I_DLDATA(I_DLDATA), 120 | .I_DLWR(I_DLWR), 121 | 122 | .O_DB(W_OBJ_DB), // Not used 123 | .O_OBJ_DO(W_OBJ_DAT), 124 | .O_FLIP_VRAM(W_FLIP_VRAM), 125 | .O_FLIP_HV(W_FLIP_HV), 126 | .O_L_CMPBLKn(W_L_CMPBLKn) 127 | ); 128 | 129 | assign O_OBJ_DB = W_OBJ_DB; 130 | assign O_FLIP_HV = W_FLIP_HV; 131 | 132 | //---------------- 133 | // Colour Palette 134 | //---------------- 135 | 136 | wire [2:0]W_R; 137 | wire [2:0]W_G; 138 | wire [1:0]W_B; 139 | 140 | mario_col_pal cpal 141 | ( 142 | .I_CLK_48M(I_CLK_48M), 143 | .I_CEN_24Mn(I_CEN_24Mn), 144 | .I_CEN_6M(I_CEN_6M), 145 | .I_VRAM_D(W_VRAM_DAT), 146 | .I_OBJ_D(W_OBJ_DAT), 147 | .I_CMPBLKn(W_L_CMPBLKn), 148 | .I_CPAL_SEL(I_2L_Q[3]), 149 | .I_DLCLK(I_CLK_48M), 150 | .I_DLADDR(I_DLADDR), 151 | .I_DLDATA(I_DLDATA), 152 | .I_DLWR(I_DLWR), 153 | 154 | .O_R(W_R), 155 | .O_G(W_G), 156 | .O_B(W_B) 157 | ); 158 | 159 | assign O_VGA_RED = W_R; 160 | assign O_VGA_GRN = W_G; 161 | assign O_VGA_BLU = W_B; 162 | 163 | endmodule 164 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/dkong3_sub.v: -------------------------------------------------------------------------------- 1 | 2 | module dkong3_sub 3 | ( 4 | //input I_CLK_24M, 5 | input I_CLK_12M, 6 | input I_SUBCLKx2, 7 | input I_SUB_RESETn, 8 | input I_SUB_NMIn, 9 | input [7:0]I_SUB_DBI, 10 | input I_CPU_CE, 11 | input I_ODD_OR_EVEN, 12 | 13 | //input [16:0]I_DLADDR, 14 | //input [7:0]I_DLDATA, 15 | //input I_DLWR, 16 | 17 | output [15:0]O_SUB_ADDR, 18 | output [7:0]O_SUB_DB0, 19 | output O_SUB_RNW, 20 | //output O_SUB_INP0n, 21 | //output O_SUB_INP1n, 22 | output [15:0]O_SAMPLE 23 | ); 24 | 25 | 26 | //----- 27 | // CPU 28 | //----- 29 | 30 | wire [7:0] from_data_bus; 31 | wire [7:0] cpu_dout; 32 | 33 | wire [15:0] cpu_addr; 34 | wire cpu_rnw; 35 | //wire pause_cpu; 36 | wire nmi; 37 | wire mapper_irq; 38 | wire apu_irq; 39 | 40 | T65 cpu( 41 | .mode (0), // 42 | .BCD_en (0), // 43 | 44 | .res_n (I_SUB_RESETn), // 45 | .clk (I_SUBCLKx2), 46 | .enable (I_CPU_CE), 47 | //.rdy (~pause_cpu), 48 | .rdy (1'b1), 49 | 50 | .IRQ_n (~apu_irq), 51 | .NMI_n (I_SUB_NMIn), // 52 | .R_W_n (cpu_rnw), 53 | 54 | .A (cpu_addr), 55 | .DI (cpu_rnw ? W_CPU_DBUS : cpu_dout), 56 | .DO (cpu_dout) 57 | ); 58 | 59 | assign O_SUB_ADDR = cpu_addr; 60 | assign O_SUB_DB0 = cpu_dout; 61 | assign O_SUB_RNW = cpu_rnw; 62 | 63 | // CPU Data Bus (Data In) 64 | //wire [7:0]W_CPU_DBUS = I_SUB_DBI | APU_DO; // I SUB_DI 65 | 66 | //----- 67 | // ROM 68 | //----- 69 | 70 | //wire [7:0]W_SUB1ROM_DO; 71 | //wire W_SUBROM_OEn = (cpu_addr[15] == 1'b0); 72 | 73 | //SUB1_ROM sub1rom(I_CLK_12M, cpu_addr[12:0], ~I_CPU_CE, W_SUBROM_OEn, W_SUB1ROM_DO, 74 | // I_CLK_24M, I_DLADDR, I_DLDATA, I_DLWR); 75 | 76 | 77 | //----- 78 | // RAM 79 | //----- 80 | 81 | //wire W_SUBRAM_OEn = (cpu_addr[15:14] == 3'b00); 82 | 83 | //reg [7:0]SUB1RAM_DO; 84 | //wire [7:0]W_RAM1_DO; 85 | 86 | //ram_2048_8 U_5K 87 | //( 88 | // .I_CLK(I_CLK_12M), 89 | // .I_ADDR(cpu_addr[10:0]), 90 | // .I_D(cpu_dout), 91 | // .I_CE(~I_CPU_CE), 92 | // .I_WE(~cpu_rnw & (cpu_addr[15:14] == 2'b0)), 93 | // .O_D(W_RAM1_DO) 94 | //); 95 | 96 | wire [7:0]W_CPU_DBUS = (cpu_addr == 16'h4015 & mr_int) ? apu_dout : I_SUB_DBI; 97 | 98 | //always@(posedge I_CLK_12M) 99 | //begin 100 | // SUB1RAM_DO <= (cpu_addr[15:14] == 2'b0 & I_CPU_CE == 1'b1 & cpu_rnw == 1'b1) ? W_RAM1_DO : 0; 101 | // APU_DO <= (inport_cs == 1'b1) ? I_SUB_DI : (apu_cs == 1'b1) ? apu_dout : 0; 102 | //end 103 | 104 | 105 | //----- 106 | // APU 107 | //----- 108 | 109 | wire apu_cs = cpu_addr >= 'h4000 && cpu_addr < 'h4018; 110 | //wire apu_cs2 = cpu_addr >= 'h4000 && cpu_addr < 'h4016; 111 | wire [7:0]apu_dout; 112 | //reg [7:0]APU_DO; 113 | wire [15:0] sample_apu; 114 | 115 | wire mr_int = cpu_rnw; 116 | wire mw_int = !cpu_rnw; 117 | 118 | APU apu( 119 | .MMC5 (1'b0), // 120 | .clk (I_SUBCLKx2), // 121 | .PAL (1'b0), // 122 | .ce (I_CPU_CE), // 123 | .reset (~I_SUB_RESETn), // 124 | .ADDR (cpu_addr[4:0]), // 125 | .DIN (cpu_dout), // 126 | .DOUT (apu_dout), // 127 | .MW (mw_int && apu_cs), // 128 | .MR (mr_int && apu_cs), // 129 | .audio_channels (5'b11111), // not used? 130 | .Sample (sample_apu), // 131 | .DmaReq (/*apu_dma_request*/), 132 | .DmaAck (/*apu_dma_ack*/), 133 | .DmaAddr (/*apu_dma_addr*/), 134 | .DmaData (/*from_data_bus*/), 135 | .odd_or_even (I_ODD_OR_EVEN), // 136 | .IRQ (apu_irq) // 137 | ); 138 | 139 | //assign sample = sample_a; 140 | assign O_SAMPLE = sample_inverted; 141 | //reg [15:0] sample_a; 142 | 143 | //always @* begin 144 | // case (audio_en) 145 | // 0: sample_a = 16'd0; 146 | // 1: sample_a = sample_ext; 147 | // 2: sample_a = sample_inverted; 148 | // 3: sample_a = sample_ext; 149 | // endcase 150 | //end 151 | 152 | wire [15:0] sample_inverted = 16'hFFFF - sample_apu; 153 | //wire [1:0] audio_en = {int_audio, ext_audio}; 154 | //wire [15:0] audio_mappers = (audio_en == 2'd1) ? 16'd0 : sample_inverted; 155 | 156 | 157 | // Input ports are mapped into the APU's range. 158 | //wire inport0_cs = (cpu_addr == 'h4016); 159 | //wire inport1_cs = (cpu_addr == 'h4017); 160 | //wire inport_cs = inport0_cs | inport1_cs; 161 | 162 | //reg inp_strobe; 163 | 164 | //always @(posedge clk) begin 165 | // if (inport1_cs && mw_int) 166 | // inp_strobe <= cpu_dout[0]; 167 | //end 168 | 169 | //assign inport_strobe = inp_strobe; 170 | //assign O_SUB_INP0n = ~(inport0_cs && mr_int); 171 | //assign O_SUB_INP1n = ~(inport1_cs && mr_int); 172 | 173 | endmodule 174 | -------------------------------------------------------------------------------- /src/fpga/core/pin_ddio_clk.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTDDIO_OUT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: ALTDDIO_OUT 5 | 6 | // ============================================================ 7 | // File Name: pin_ddio_clk.v 8 | // Megafunction Name(s): 9 | // ALTDDIO_OUT 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.1.1 Build 646 04/11/2019 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2019 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and any partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details, at 34 | //https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module pin_ddio_clk ( 41 | datain_h, 42 | datain_l, 43 | outclock, 44 | dataout); 45 | 46 | input [0:0] datain_h; 47 | input [0:0] datain_l; 48 | input outclock; 49 | output [0:0] dataout; 50 | 51 | wire [0:0] sub_wire0; 52 | wire [0:0] dataout = sub_wire0[0:0]; 53 | 54 | altddio_out ALTDDIO_OUT_component ( 55 | .datain_h (datain_h), 56 | .datain_l (datain_l), 57 | .outclock (outclock), 58 | .dataout (sub_wire0), 59 | .aclr (1'b0), 60 | .aset (1'b0), 61 | .oe (1'b1), 62 | .oe_out (), 63 | .outclocken (1'b1), 64 | .sclr (1'b0), 65 | .sset (1'b0)); 66 | defparam 67 | ALTDDIO_OUT_component.extend_oe_disable = "OFF", 68 | ALTDDIO_OUT_component.intended_device_family = "Cyclone V", 69 | ALTDDIO_OUT_component.invert_output = "OFF", 70 | ALTDDIO_OUT_component.lpm_hint = "UNUSED", 71 | ALTDDIO_OUT_component.lpm_type = "altddio_out", 72 | ALTDDIO_OUT_component.oe_reg = "UNREGISTERED", 73 | ALTDDIO_OUT_component.power_up_high = "OFF", 74 | ALTDDIO_OUT_component.width = 1; 75 | 76 | 77 | endmodule 78 | 79 | // ============================================================ 80 | // CNX file retrieval info 81 | // ============================================================ 82 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 83 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 84 | // Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" 85 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 86 | // Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" 87 | // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" 88 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" 89 | // Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" 90 | // Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" 91 | // Retrieval info: CONSTANT: WIDTH NUMERIC "1" 92 | // Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]" 93 | // Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0 94 | // Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]" 95 | // Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0 96 | // Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]" 97 | // Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0 98 | // Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" 99 | // Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 100 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.v TRUE FALSE 101 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.qip TRUE FALSE 102 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.bsf FALSE TRUE 103 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk_inst.v TRUE TRUE 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk_bb.v FALSE TRUE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.inc FALSE TRUE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.cmp FALSE TRUE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.ppf TRUE FALSE 108 | // Retrieval info: LIB_FILE: altera_mf 109 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2023 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and any partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details, at 20 | https://fpgasoftware.intel.com/eula. 21 | */ 22 | (header "symbol" (version "1.1")) 23 | (symbol 24 | (rect 0 0 160 224) 25 | (text "mf_pllbase" (rect 48 -1 91 11)(font "Arial" (font_size 10))) 26 | (text "inst" (rect 8 208 20 220)(font "Arial" )) 27 | (port 28 | (pt 0 72) 29 | (input) 30 | (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) 31 | (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8))) 32 | (line (pt 0 72)(pt 48 72)(line_width 1)) 33 | ) 34 | (port 35 | (pt 0 112) 36 | (input) 37 | (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8))) 38 | (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8))) 39 | (line (pt 0 112)(pt 48 112)(line_width 1)) 40 | ) 41 | (port 42 | (pt 160 72) 43 | (output) 44 | (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8))) 45 | (text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8))) 46 | (line (pt 160 72)(pt 112 72)(line_width 1)) 47 | ) 48 | (port 49 | (pt 160 112) 50 | (output) 51 | (text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8))) 52 | (text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8))) 53 | (line (pt 160 112)(pt 112 112)(line_width 1)) 54 | ) 55 | (port 56 | (pt 160 152) 57 | (output) 58 | (text "outclk_2" (rect 0 0 33 12)(font "Arial" (font_size 8))) 59 | (text "outclk_2" (rect 117 141 165 152)(font "Arial" (font_size 8))) 60 | (line (pt 160 152)(pt 112 152)(line_width 1)) 61 | ) 62 | (port 63 | (pt 160 192) 64 | (output) 65 | (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8))) 66 | (text "locked" (rect 127 181 163 192)(font "Arial" (font_size 8))) 67 | (line (pt 160 192)(pt 112 192)(line_width 1)) 68 | ) 69 | (drawing 70 | (text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9))) 71 | (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0))) 72 | (text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9))) 73 | (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0))) 74 | (text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9))) 75 | (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0))) 76 | (text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9))) 77 | (text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0))) 78 | (text "outclk2" (rect 113 123 268 259)(font "Arial" (color 128 0 0)(font_size 9))) 79 | (text "clk" (rect 97 147 212 304)(font "Arial" (color 0 0 0))) 80 | (text "locked" (rect 113 163 262 339)(font "Arial" (color 128 0 0)(font_size 9))) 81 | (text "export" (rect 82 187 200 384)(font "Arial" (color 0 0 0))) 82 | (text " altera_pll " (rect 118 208 308 426)(font "Arial" )) 83 | (line (pt 48 32)(pt 112 32)(line_width 1)) 84 | (line (pt 112 32)(pt 112 208)(line_width 1)) 85 | (line (pt 48 208)(pt 112 208)(line_width 1)) 86 | (line (pt 48 32)(pt 48 208)(line_width 1)) 87 | (line (pt 49 52)(pt 49 76)(line_width 1)) 88 | (line (pt 50 52)(pt 50 76)(line_width 1)) 89 | (line (pt 49 92)(pt 49 116)(line_width 1)) 90 | (line (pt 50 92)(pt 50 116)(line_width 1)) 91 | (line (pt 111 52)(pt 111 76)(line_width 1)) 92 | (line (pt 110 52)(pt 110 76)(line_width 1)) 93 | (line (pt 111 92)(pt 111 116)(line_width 1)) 94 | (line (pt 110 92)(pt 110 116)(line_width 1)) 95 | (line (pt 111 132)(pt 111 156)(line_width 1)) 96 | (line (pt 110 132)(pt 110 156)(line_width 1)) 97 | (line (pt 111 172)(pt 111 196)(line_width 1)) 98 | (line (pt 110 172)(pt 110 196)(line_width 1)) 99 | (line (pt 0 0)(pt 160 0)(line_width 1)) 100 | (line (pt 160 0)(pt 160 224)(line_width 1)) 101 | (line (pt 0 224)(pt 160 224)(line_width 1)) 102 | (line (pt 0 0)(pt 0 224)(line_width 1)) 103 | ) 104 | ) 105 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/T80/T80_Reg.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- **** 3 | -- T80(c) core. Attempt to finish all undocumented features and provide 4 | -- accurate timings. 5 | -- Version 350. 6 | -- Copyright (c) 2018 Sorgelig 7 | -- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr 8 | -- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as 9 | -- correct implementation is still unclear. 10 | -- 11 | -- **** 12 | -- T80(b) core. In an effort to merge and maintain bug fixes .... 13 | -- 14 | -- 15 | -- Ver 300 started tidyup 16 | -- MikeJ March 2005 17 | -- Latest version from www.fpgaarcade.com (original www.opencores.org) 18 | -- 19 | -- **** 20 | -- 21 | -- T80 Registers, technology independent 22 | -- 23 | -- Version : 0244 24 | -- 25 | -- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) 26 | -- 27 | -- All rights reserved 28 | -- 29 | -- Redistribution and use in source and synthezised forms, with or without 30 | -- modification, are permitted provided that the following conditions are met: 31 | -- 32 | -- Redistributions of source code must retain the above copyright notice, 33 | -- this list of conditions and the following disclaimer. 34 | -- 35 | -- Redistributions in synthesized form must reproduce the above copyright 36 | -- notice, this list of conditions and the following disclaimer in the 37 | -- documentation and/or other materials provided with the distribution. 38 | -- 39 | -- Neither the name of the author nor the names of other contributors may 40 | -- be used to endorse or promote products derived from this software without 41 | -- specific prior written permission. 42 | -- 43 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 44 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 45 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 47 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 | -- POSSIBILITY OF SUCH DAMAGE. 54 | -- 55 | -- Please report bugs to the author, but before you do so, please 56 | -- make sure that this is not a derivative work and that 57 | -- you have the latest version of this file. 58 | -- 59 | -- The latest version of this file can be found at: 60 | -- http://www.opencores.org/cvsweb.shtml/t51/ 61 | -- 62 | -- Limitations : 63 | -- 64 | -- File history : 65 | -- 66 | -- 0242 : Initial release 67 | -- 68 | -- 0244 : Changed to single register file 69 | -- 70 | 71 | library IEEE; 72 | use IEEE.std_logic_1164.all; 73 | use IEEE.numeric_std.all; 74 | 75 | entity T80_Reg is 76 | port( 77 | Clk : in std_logic; 78 | CEN : in std_logic; 79 | WEH : in std_logic; 80 | WEL : in std_logic; 81 | AddrA : in std_logic_vector(2 downto 0); 82 | AddrB : in std_logic_vector(2 downto 0); 83 | AddrC : in std_logic_vector(2 downto 0); 84 | DIH : in std_logic_vector(7 downto 0); 85 | DIL : in std_logic_vector(7 downto 0); 86 | DOAH : out std_logic_vector(7 downto 0); 87 | DOAL : out std_logic_vector(7 downto 0); 88 | DOBH : out std_logic_vector(7 downto 0); 89 | DOBL : out std_logic_vector(7 downto 0); 90 | DOCH : out std_logic_vector(7 downto 0); 91 | DOCL : out std_logic_vector(7 downto 0); 92 | DOR : out std_logic_vector(127 downto 0); 93 | DIRSet : in std_logic; 94 | DIR : in std_logic_vector(127 downto 0) 95 | ); 96 | end T80_Reg; 97 | 98 | architecture rtl of T80_Reg is 99 | 100 | type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); 101 | signal RegsH : Register_Image(0 to 7); 102 | signal RegsL : Register_Image(0 to 7); 103 | 104 | begin 105 | 106 | process (Clk) 107 | begin 108 | if rising_edge(Clk) then 109 | if DIRSet = '1' then 110 | RegsL(0) <= DIR( 7 downto 0); 111 | RegsH(0) <= DIR( 15 downto 8); 112 | 113 | RegsL(1) <= DIR( 23 downto 16); 114 | RegsH(1) <= DIR( 31 downto 24); 115 | 116 | RegsL(2) <= DIR( 39 downto 32); 117 | RegsH(2) <= DIR( 47 downto 40); 118 | 119 | RegsL(3) <= DIR( 55 downto 48); 120 | RegsH(3) <= DIR( 63 downto 56); 121 | 122 | RegsL(4) <= DIR( 71 downto 64); 123 | RegsH(4) <= DIR( 79 downto 72); 124 | 125 | RegsL(5) <= DIR( 87 downto 80); 126 | RegsH(5) <= DIR( 95 downto 88); 127 | 128 | RegsL(6) <= DIR(103 downto 96); 129 | RegsH(6) <= DIR(111 downto 104); 130 | 131 | RegsL(7) <= DIR(119 downto 112); 132 | RegsH(7) <= DIR(127 downto 120); 133 | elsif CEN = '1' then 134 | if WEH = '1' then 135 | RegsH(to_integer(unsigned(AddrA))) <= DIH; 136 | end if; 137 | if WEL = '1' then 138 | RegsL(to_integer(unsigned(AddrA))) <= DIL; 139 | end if; 140 | end if; 141 | end if; 142 | end process; 143 | 144 | DOAH <= RegsH(to_integer(unsigned(AddrA))); 145 | DOAL <= RegsL(to_integer(unsigned(AddrA))); 146 | DOBH <= RegsH(to_integer(unsigned(AddrB))); 147 | DOBL <= RegsL(to_integer(unsigned(AddrB))); 148 | DOCH <= RegsH(to_integer(unsigned(AddrC))); 149 | DOCL <= RegsL(to_integer(unsigned(AddrC))); 150 | DOR <= RegsH(7) & RegsL(7) & RegsH(6) & RegsL(6) & RegsH(5) & RegsL(5) & RegsH(4) & RegsL(4) & RegsH(3) & RegsL(3) & RegsH(2) & RegsL(2) & RegsH(1) & RegsL(1) & RegsH(0) & RegsL(0); 151 | 152 | end; 153 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/p1.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Port 1 unit. 4 | -- Implements the Port 1 logic. 5 | -- 6 | -- $Id: p1.vhd,v 1.5 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | -- Redistribution and use in source and synthezised forms, with or without 13 | -- modification, are permitted provided that the following conditions are met: 14 | -- 15 | -- Redistributions of source code must retain the above copyright notice, 16 | -- this list of conditions and the following disclaimer. 17 | -- 18 | -- Redistributions in synthesized form must reproduce the above copyright 19 | -- notice, this list of conditions and the following disclaimer in the 20 | -- documentation and/or other materials provided with the distribution. 21 | -- 22 | -- Neither the name of the author nor the names of other contributors may 23 | -- be used to endorse or promote products derived from this software without 24 | -- specific prior written permission. 25 | -- 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 | -- POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | -- Please report bugs to the author, but before you do so, please 39 | -- make sure that this is not a derivative work and that 40 | -- you have the latest version of this file. 41 | -- 42 | -- The latest version of this file can be found at: 43 | -- http://www.opencores.org/cvsweb.shtml/t48/ 44 | -- 45 | ------------------------------------------------------------------------------- 46 | 47 | library ieee; 48 | use ieee.std_logic_1164.all; 49 | 50 | use work.t48_pack.word_t; 51 | 52 | entity t48_p1 is 53 | 54 | port ( 55 | -- Global Interface ------------------------------------------------------- 56 | clk_i : in std_logic; 57 | res_i : in std_logic; 58 | en_clk_i : in boolean; 59 | -- T48 Bus Interface ------------------------------------------------------ 60 | data_i : in word_t; 61 | data_o : out word_t; 62 | write_p1_i : in boolean; 63 | read_p1_i : in boolean; 64 | read_reg_i : in boolean; 65 | -- Port 1 Interface ------------------------------------------------------- 66 | p1_i : in word_t; 67 | p1_o : out word_t; 68 | p1_low_imp_o : out std_logic 69 | ); 70 | 71 | end t48_p1; 72 | 73 | 74 | use work.t48_pack.clk_active_c; 75 | use work.t48_pack.res_active_c; 76 | use work.t48_pack.bus_idle_level_c; 77 | 78 | architecture rtl of t48_p1 is 79 | 80 | -- the port output register 81 | signal p1_q : word_t; 82 | 83 | -- the low impedance marker 84 | signal low_imp_q : std_logic; 85 | 86 | begin 87 | 88 | ----------------------------------------------------------------------------- 89 | -- Process p1_reg 90 | -- 91 | -- Purpose: 92 | -- Implements the port output register. 93 | -- 94 | p1_reg: process (res_i, clk_i) 95 | begin 96 | if res_i = res_active_c then 97 | p1_q <= (others => '1'); 98 | low_imp_q <= '0'; 99 | 100 | elsif clk_i'event and clk_i = clk_active_c then 101 | if en_clk_i then 102 | 103 | if write_p1_i then 104 | p1_q <= data_i; 105 | low_imp_q <= '1'; 106 | else 107 | low_imp_q <= '0'; 108 | end if; 109 | 110 | end if; 111 | 112 | end if; 113 | 114 | end process p1_reg; 115 | -- 116 | ----------------------------------------------------------------------------- 117 | 118 | 119 | ----------------------------------------------------------------------------- 120 | -- Process p1_data 121 | -- 122 | -- Purpose: 123 | -- Generates the T48 bus data. 124 | -- 125 | p1_data: process (read_p1_i, 126 | p1_i, 127 | read_reg_i, 128 | p1_q) 129 | begin 130 | data_o <= (others => bus_idle_level_c); 131 | 132 | if read_p1_i then 133 | if read_reg_i then 134 | data_o <= p1_q; 135 | else 136 | data_o <= p1_i; 137 | end if; 138 | end if; 139 | 140 | end process p1_data; 141 | -- 142 | ----------------------------------------------------------------------------- 143 | 144 | 145 | ----------------------------------------------------------------------------- 146 | -- Output Mapping. 147 | ----------------------------------------------------------------------------- 148 | p1_o <= p1_q; 149 | p1_low_imp_o <= low_imp_q; 150 | 151 | end rtl; 152 | 153 | 154 | ------------------------------------------------------------------------------- 155 | -- File History: 156 | -- 157 | -- $Log: p1.vhd,v $ 158 | -- Revision 1.5 2005/06/11 10:08:43 arniml 159 | -- introduce prefix 't48_' for all packages, entities and configurations 160 | -- 161 | -- Revision 1.4 2004/07/11 16:51:33 arniml 162 | -- cleanup copyright notice 163 | -- 164 | -- Revision 1.3 2004/05/17 14:37:53 arniml 165 | -- reorder data_o generation 166 | -- 167 | -- Revision 1.2 2004/03/29 19:39:58 arniml 168 | -- rename pX_limp to pX_low_imp 169 | -- 170 | -- Revision 1.1 2004/03/23 21:31:52 arniml 171 | -- initial check-in 172 | -- 173 | ------------------------------------------------------------------------------- 174 | -------------------------------------------------------------------------------- /src/fpga/core/sound_i2s.sv: -------------------------------------------------------------------------------- 1 | // MIT License 2 | 3 | // Copyright (c) 2022 Adam Gastineau 4 | 5 | // Permission is hereby granted, free of charge, to any person obtaining a copy 6 | // of this software and associated documentation files (the "Software"), to deal 7 | // in the Software without restriction, including without limitation the rights 8 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | // copies of the Software, and to permit persons to whom the Software is 10 | // furnished to do so, subject to the following conditions: 11 | 12 | // The above copyright notice and this permission notice shall be included in all 13 | // copies or substantial portions of the Software. 14 | 15 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | // SOFTWARE. 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | // A very simple audio i2s bridge to APF, based on their example code 26 | module sound_i2s #( 27 | parameter CHANNEL_WIDTH = 15, 28 | parameter SIGNED_INPUT = 0 29 | ) ( 30 | input wire clk_74a, 31 | input wire clk_audio, 32 | 33 | // Left and right audio channels. Can be in an arbitrary clock domain 34 | input wire [CHANNEL_WIDTH - 1:0] audio_l, 35 | input wire [CHANNEL_WIDTH - 1:0] audio_r, 36 | 37 | output reg audio_mclk, 38 | output reg audio_lrck, 39 | output reg audio_dac 40 | ); 41 | // 42 | // audio i2s generator 43 | // 44 | 45 | reg audgen_nextsamp; 46 | 47 | // generate MCLK = 12.288mhz with fractional accumulator 48 | reg [21:0] audgen_accum = 0; 49 | parameter [20:0] CYCLE_48KHZ = 21'd122880 * 2; 50 | always @(posedge clk_74a) begin 51 | audgen_accum <= audgen_accum + CYCLE_48KHZ; 52 | if (audgen_accum >= 21'd742500) begin 53 | audio_mclk <= ~audio_mclk; 54 | audgen_accum <= audgen_accum - 21'd742500 + CYCLE_48KHZ; 55 | end 56 | end 57 | 58 | // generate SCLK = 3.072mhz by dividing MCLK by 4 59 | reg [1:0] aud_mclk_divider; 60 | reg prev_audio_mclk; 61 | wire audgen_sclk = aud_mclk_divider[1] /* synthesis keep*/; 62 | 63 | always @(posedge clk_74a) begin 64 | if (audio_mclk && ~prev_audio_mclk) begin 65 | aud_mclk_divider <= aud_mclk_divider + 1'b1; 66 | end 67 | 68 | prev_audio_mclk <= audio_mclk; 69 | end 70 | 71 | // shift out audio data as I2S 72 | // 32 total bits per channel, but only 16 active bits at the start and then 16 dummy bits 73 | // 74 | // synchronize audio samples coming from the core 75 | 76 | localparam CHANNEL_LEFT_HIGH = SIGNED_INPUT ? 16 : 15; 77 | localparam CHANNEL_RIGHT_HIGH = 16 + CHANNEL_LEFT_HIGH; 78 | 79 | // Width of channel with signed component 80 | localparam SIGNED_CHANNEL_WIDTH = SIGNED_INPUT ? CHANNEL_WIDTH : CHANNEL_WIDTH + 1; 81 | 82 | wire [31:0] audgen_sampdata; 83 | 84 | assign audgen_sampdata[CHANNEL_LEFT_HIGH-1:CHANNEL_LEFT_HIGH-CHANNEL_WIDTH] = audio_l; 85 | assign audgen_sampdata[CHANNEL_RIGHT_HIGH-1:CHANNEL_RIGHT_HIGH-CHANNEL_WIDTH] = audio_r; 86 | 87 | generate 88 | if (!SIGNED_INPUT) begin 89 | // If not signed, make sure high bit is 0 90 | assign audgen_sampdata[31] = 0; 91 | assign audgen_sampdata[15] = 0; 92 | end 93 | endgenerate 94 | 95 | generate 96 | if (15 - SIGNED_CHANNEL_WIDTH > 0) begin 97 | assign audgen_sampdata[31-SIGNED_CHANNEL_WIDTH:16] = 0; 98 | assign audgen_sampdata[15-SIGNED_CHANNEL_WIDTH:0] = 0; 99 | end 100 | endgenerate 101 | 102 | sync_fifo #( 103 | .WIDTH(32) 104 | ) sync_fifo ( 105 | .clk_write(clk_audio), 106 | .clk_read (clk_74a), 107 | 108 | .write_en(write_en), 109 | .data_in (audgen_sampdata), 110 | .data_out(audgen_sampdata_s) 111 | ); 112 | 113 | reg write_en = 0; 114 | reg [CHANNEL_WIDTH - 1:0] prev_left; 115 | reg [CHANNEL_WIDTH - 1:0] prev_right; 116 | 117 | // Mark write when necessary 118 | always @(posedge clk_audio) begin 119 | prev_left <= audio_l; 120 | prev_right <= audio_r; 121 | 122 | write_en <= 0; 123 | 124 | if (audio_l != prev_left || audio_r != prev_right) begin 125 | write_en <= 1; 126 | end 127 | end 128 | 129 | wire [31:0] audgen_sampdata_s; 130 | 131 | reg [31:0] audgen_sampshift; 132 | reg [4:0] audio_lrck_cnt; 133 | reg prev_audgen_sclk; 134 | always @(posedge clk_74a) begin 135 | if (prev_audgen_sclk && ~audgen_sclk) begin 136 | // output the next bit 137 | audio_dac <= audgen_sampshift[31]; 138 | 139 | // 48khz * 64 140 | audio_lrck_cnt <= audio_lrck_cnt + 1'b1; 141 | if (audio_lrck_cnt == 31) begin 142 | // switch channels 143 | audio_lrck <= ~audio_lrck; 144 | 145 | // Reload sample shifter 146 | if (~audio_lrck) begin 147 | audgen_sampshift <= audgen_sampdata_s; 148 | end 149 | end else if (audio_lrck_cnt < 16) begin 150 | // only shift for 16 clocks per channel 151 | audgen_sampshift <= {audgen_sampshift[30:0], 1'b0}; 152 | end 153 | end 154 | 155 | prev_audgen_sclk <= audgen_sclk; 156 | end 157 | 158 | initial begin 159 | // Verify parameters 160 | if (CHANNEL_WIDTH > 16) begin 161 | $error("CHANNEL_WIDTH must be <= 16. Received %d", CHANNEL_WIDTH); 162 | end 163 | 164 | if (SIGNED_INPUT != 0 && SIGNED_INPUT != 1) begin 165 | $error("SIGNED_INPUT must be 0 or 1. Received %d", SIGNED_INPUT); 166 | end 167 | 168 | if (CHANNEL_WIDTH == 16 && SIGNED_INPUT == 0) begin 169 | $error("Cannot have CHANNEL_WIDTH of 16 and an unsigned input"); 170 | end 171 | end 172 | endmodule 173 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/db_bus.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The BUS unit. 4 | -- Implements the BUS port logic. 5 | -- 6 | -- $Id: db_bus.vhd,v 1.5 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | -- Redistribution and use in source and synthezised forms, with or without 13 | -- modification, are permitted provided that the following conditions are met: 14 | -- 15 | -- Redistributions of source code must retain the above copyright notice, 16 | -- this list of conditions and the following disclaimer. 17 | -- 18 | -- Redistributions in synthesized form must reproduce the above copyright 19 | -- notice, this list of conditions and the following disclaimer in the 20 | -- documentation and/or other materials provided with the distribution. 21 | -- 22 | -- Neither the name of the author nor the names of other contributors may 23 | -- be used to endorse or promote products derived from this software without 24 | -- specific prior written permission. 25 | -- 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 | -- POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | -- Please report bugs to the author, but before you do so, please 39 | -- make sure that this is not a derivative work and that 40 | -- you have the latest version of this file. 41 | -- 42 | -- The latest version of this file can be found at: 43 | -- http://www.opencores.org/cvsweb.shtml/t48/ 44 | -- 45 | ------------------------------------------------------------------------------- 46 | 47 | library ieee; 48 | use ieee.std_logic_1164.all; 49 | 50 | use work.t48_pack.word_t; 51 | 52 | entity t48_db_bus is 53 | 54 | port ( 55 | -- Global Interface ------------------------------------------------------- 56 | clk_i : in std_logic; 57 | res_i : in std_logic; 58 | en_clk_i : in boolean; 59 | ea_i : in std_logic; 60 | -- T48 Bus Interface ------------------------------------------------------ 61 | data_i : in word_t; 62 | data_o : out word_t; 63 | write_bus_i : in boolean; 64 | read_bus_i : in boolean; 65 | -- BUS Interface ---------------------------------------------------------- 66 | output_pcl_i : in boolean; 67 | bidir_bus_i : in boolean; 68 | pcl_i : in word_t; 69 | db_i : in word_t; 70 | db_o : out word_t; 71 | db_dir_o : out std_logic 72 | ); 73 | 74 | end t48_db_bus; 75 | 76 | 77 | use work.t48_pack.clk_active_c; 78 | use work.t48_pack.res_active_c; 79 | use work.t48_pack.bus_idle_level_c; 80 | use work.t48_pack.to_stdLogic; 81 | 82 | architecture rtl of t48_db_bus is 83 | 84 | -- the BUS output register 85 | signal bus_q : word_t; 86 | 87 | -- BUS direction marker 88 | signal db_dir_q, 89 | db_dir_qq : std_logic; 90 | 91 | begin 92 | 93 | ----------------------------------------------------------------------------- 94 | -- Process bus_regs 95 | -- 96 | -- Purpose: 97 | -- Implements the BUS output register. 98 | -- 99 | bus_regs: process (res_i, clk_i) 100 | begin 101 | if res_i = res_active_c then 102 | bus_q <= (others => '0'); 103 | db_dir_q <= '0'; 104 | db_dir_qq <= '0'; 105 | 106 | elsif clk_i'event and clk_i = clk_active_c then 107 | if en_clk_i then 108 | if write_bus_i then 109 | db_dir_qq <= '1'; 110 | else 111 | -- extend bus direction by one machine cycle 112 | db_dir_qq <= db_dir_q; 113 | end if; 114 | 115 | if write_bus_i then 116 | bus_q <= data_i; 117 | 118 | db_dir_q <= '1'; 119 | 120 | elsif ea_i = '1' or bidir_bus_i then 121 | db_dir_q <= '0'; 122 | 123 | end if; 124 | 125 | end if; 126 | 127 | end if; 128 | 129 | end process bus_regs; 130 | -- 131 | ----------------------------------------------------------------------------- 132 | 133 | 134 | ----------------------------------------------------------------------------- 135 | -- Output Mapping. 136 | ----------------------------------------------------------------------------- 137 | db_o <= pcl_i 138 | when output_pcl_i else 139 | bus_q; 140 | db_dir_o <= db_dir_qq or 141 | to_stdLogic(output_pcl_i); 142 | data_o <= (others => bus_idle_level_c) 143 | when not read_bus_i else 144 | db_i; 145 | 146 | end rtl; 147 | 148 | 149 | ------------------------------------------------------------------------------- 150 | -- File History: 151 | -- 152 | -- $Log: db_bus.vhd,v $ 153 | -- Revision 1.5 2005/06/11 10:08:43 arniml 154 | -- introduce prefix 't48_' for all packages, entities and configurations 155 | -- 156 | -- Revision 1.4 2005/06/09 22:16:26 arniml 157 | -- Implement db_dir_o glitch-safe 158 | -- 159 | -- Revision 1.3 2004/10/25 20:30:18 arniml 160 | -- delay db_dir_o by one machine cycle 161 | -- this fixes the timing relation between BUS data and WR' 162 | -- 163 | -- Revision 1.2 2004/04/04 14:15:45 arniml 164 | -- add dump_compare support 165 | -- 166 | -- Revision 1.1 2004/03/23 21:31:52 arniml 167 | -- initial check-in 168 | -- 169 | ------------------------------------------------------------------------------- 170 | -------------------------------------------------------------------------------- /src/fpga/apf/mf_ddio_bidir_12.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTDDIO_BIDIR% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: ALTDDIO_BIDIR 5 | 6 | // ============================================================ 7 | // File Name: mf_ddio_bidir_12.v 8 | // Megafunction Name(s): 9 | // ALTDDIO_BIDIR 10 | // 11 | // Simulation Library Files(s): 12 | // 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 23.1std.0 Build 991 11/28/2023 SC Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2023 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and any partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details, at 34 | //https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module mf_ddio_bidir_12 ( 41 | datain_h, 42 | datain_l, 43 | inclock, 44 | oe, 45 | outclock, 46 | dataout_h, 47 | dataout_l, 48 | padio); 49 | 50 | input [11:0] datain_h; 51 | input [11:0] datain_l; 52 | input inclock; 53 | input oe; 54 | input outclock; 55 | output [11:0] dataout_h; 56 | output [11:0] dataout_l; 57 | inout [11:0] padio; 58 | 59 | wire [11:0] sub_wire0; 60 | wire [11:0] sub_wire1; 61 | wire [11:0] dataout_h = sub_wire0[11:0]; 62 | wire [11:0] dataout_l = sub_wire1[11:0]; 63 | 64 | altddio_bidir ALTDDIO_BIDIR_component ( 65 | .datain_h (datain_h), 66 | .datain_l (datain_l), 67 | .inclock (inclock), 68 | .oe (oe), 69 | .outclock (outclock), 70 | .padio (padio), 71 | .dataout_h (sub_wire0), 72 | .dataout_l (sub_wire1), 73 | .aclr (1'b0), 74 | .aset (1'b0), 75 | .combout (), 76 | .dqsundelayedout (), 77 | .inclocken (1'b1), 78 | .oe_out (), 79 | .outclocken (1'b1), 80 | .sclr (1'b0), 81 | .sset (1'b0)); 82 | defparam 83 | ALTDDIO_BIDIR_component.extend_oe_disable = "OFF", 84 | ALTDDIO_BIDIR_component.implement_input_in_lcell = "OFF", 85 | ALTDDIO_BIDIR_component.intended_device_family = "Cyclone V", 86 | ALTDDIO_BIDIR_component.invert_output = "OFF", 87 | ALTDDIO_BIDIR_component.lpm_hint = "UNUSED", 88 | ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir", 89 | ALTDDIO_BIDIR_component.oe_reg = "UNREGISTERED", 90 | ALTDDIO_BIDIR_component.power_up_high = "OFF", 91 | ALTDDIO_BIDIR_component.width = 12; 92 | 93 | 94 | endmodule 95 | 96 | // ============================================================ 97 | // CNX file retrieval info 98 | // ============================================================ 99 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 100 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 101 | // Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" 102 | // Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "OFF" 103 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 104 | // Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" 105 | // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" 106 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" 107 | // Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" 108 | // Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" 109 | // Retrieval info: CONSTANT: WIDTH NUMERIC "12" 110 | // Retrieval info: USED_PORT: datain_h 0 0 12 0 INPUT NODEFVAL "datain_h[11..0]" 111 | // Retrieval info: CONNECT: @datain_h 0 0 12 0 datain_h 0 0 12 0 112 | // Retrieval info: USED_PORT: datain_l 0 0 12 0 INPUT NODEFVAL "datain_l[11..0]" 113 | // Retrieval info: CONNECT: @datain_l 0 0 12 0 datain_l 0 0 12 0 114 | // Retrieval info: USED_PORT: dataout_h 0 0 12 0 OUTPUT NODEFVAL "dataout_h[11..0]" 115 | // Retrieval info: CONNECT: dataout_h 0 0 12 0 @dataout_h 0 0 12 0 116 | // Retrieval info: USED_PORT: dataout_l 0 0 12 0 OUTPUT NODEFVAL "dataout_l[11..0]" 117 | // Retrieval info: CONNECT: dataout_l 0 0 12 0 @dataout_l 0 0 12 0 118 | // Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" 119 | // Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 120 | // Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" 121 | // Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 122 | // Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" 123 | // Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 124 | // Retrieval info: USED_PORT: padio 0 0 12 0 BIDIR NODEFVAL "padio[11..0]" 125 | // Retrieval info: CONNECT: padio 0 0 12 0 @padio 0 0 12 0 126 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.v TRUE FALSE 127 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.qip TRUE FALSE 128 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.bsf FALSE TRUE 129 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_inst.v FALSE TRUE 130 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_bb.v FALSE TRUE 131 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.inc FALSE TRUE 132 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.cmp FALSE TRUE 133 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.ppf TRUE FALSE 134 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/T80/T80sed.vhd: -------------------------------------------------------------------------------- 1 | -- **** 2 | -- T80(b) core. In an effort to merge and maintain bug fixes .... 3 | -- 4 | -- 5 | -- Ver 300 started tidyup 6 | -- MikeJ March 2005 7 | -- Latest version from www.fpgaarcade.com (original www.opencores.org) 8 | -- 9 | -- **** 10 | -- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** 11 | -- 12 | -- Z80 compatible microprocessor core, synchronous top level with clock enable 13 | -- Different timing than the original z80 14 | -- Inputs needs to be synchronous and outputs may glitch 15 | -- 16 | -- Version : 0238 17 | -- 18 | -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) 19 | -- 20 | -- All rights reserved 21 | -- 22 | -- Redistribution and use in source and synthezised forms, with or without 23 | -- modification, are permitted provided that the following conditions are met: 24 | -- 25 | -- Redistributions of source code must retain the above copyright notice, 26 | -- this list of conditions and the following disclaimer. 27 | -- 28 | -- Redistributions in synthesized form must reproduce the above copyright 29 | -- notice, this list of conditions and the following disclaimer in the 30 | -- documentation and/or other materials provided with the distribution. 31 | -- 32 | -- Neither the name of the author nor the names of other contributors may 33 | -- be used to endorse or promote products derived from this software without 34 | -- specific prior written permission. 35 | -- 36 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 37 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 38 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 39 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 40 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 41 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 42 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 43 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 44 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 45 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 46 | -- POSSIBILITY OF SUCH DAMAGE. 47 | -- 48 | -- Please report bugs to the author, but before you do so, please 49 | -- make sure that this is not a derivative work and that 50 | -- you have the latest version of this file. 51 | -- 52 | -- The latest version of this file can be found at: 53 | -- http://www.opencores.org/cvsweb.shtml/t80/ 54 | -- 55 | -- Limitations : 56 | -- 57 | -- File history : 58 | -- 59 | -- 0235 : First release 60 | -- 61 | -- 0236 : Added T2Write generic 62 | -- 63 | -- 0237 : Fixed T2Write with wait state 64 | -- 65 | -- 0238 : Updated for T80 interface change 66 | -- 67 | -- 0242 : Updated for T80 interface change 68 | -- 69 | 70 | library IEEE; 71 | use IEEE.std_logic_1164.all; 72 | use IEEE.numeric_std.all; 73 | use work.T80_Pack.all; 74 | 75 | entity T80sed is 76 | port( 77 | RESET_n : in std_logic; 78 | CLK_n : in std_logic; 79 | CLKEN : in std_logic; 80 | WAIT_n : in std_logic; 81 | INT_n : in std_logic; 82 | NMI_n : in std_logic; 83 | BUSRQ_n : in std_logic; 84 | M1_n : out std_logic; 85 | MREQ_n : out std_logic; 86 | IORQ_n : out std_logic; 87 | RD_n : out std_logic; 88 | WR_n : out std_logic; 89 | RFSH_n : out std_logic; 90 | HALT_n : out std_logic; 91 | BUSAK_n : out std_logic; 92 | A : out std_logic_vector(15 downto 0); 93 | DI : in std_logic_vector(7 downto 0); 94 | DO : out std_logic_vector(7 downto 0) 95 | ); 96 | end T80sed; 97 | 98 | architecture rtl of T80sed is 99 | 100 | signal IntCycle_n : std_logic; 101 | signal NoRead : std_logic; 102 | signal Write : std_logic; 103 | signal IORQ : std_logic; 104 | signal DI_Reg : std_logic_vector(7 downto 0); 105 | signal MCycle : std_logic_vector(2 downto 0); 106 | signal TState : std_logic_vector(2 downto 0); 107 | 108 | begin 109 | 110 | u0 : T80 111 | generic map( 112 | Mode => 0, 113 | IOWait => 1) 114 | port map( 115 | CEN => CLKEN, 116 | M1_n => M1_n, 117 | IORQ => IORQ, 118 | NoRead => NoRead, 119 | Write => Write, 120 | RFSH_n => RFSH_n, 121 | HALT_n => HALT_n, 122 | WAIT_n => Wait_n, 123 | INT_n => INT_n, 124 | NMI_n => NMI_n, 125 | RESET_n => RESET_n, 126 | BUSRQ_n => BUSRQ_n, 127 | BUSAK_n => BUSAK_n, 128 | CLK_n => CLK_n, 129 | A => A, 130 | DInst => DI, 131 | DI => DI_Reg, 132 | DO => DO, 133 | MC => MCycle, 134 | TS => TState, 135 | IntCycle_n => IntCycle_n); 136 | 137 | process (RESET_n, CLK_n) 138 | begin 139 | if RESET_n = '0' then 140 | RD_n <= '1'; 141 | WR_n <= '1'; 142 | IORQ_n <= '1'; 143 | MREQ_n <= '1'; 144 | DI_Reg <= "00000000"; 145 | elsif CLK_n'event and CLK_n = '1' then 146 | if CLKEN = '1' then 147 | RD_n <= '1'; 148 | WR_n <= '1'; 149 | IORQ_n <= '1'; 150 | MREQ_n <= '1'; 151 | if MCycle = "001" then 152 | if TState = "001" or (TState = "010" and Wait_n = '0') then 153 | RD_n <= not IntCycle_n; 154 | MREQ_n <= not IntCycle_n; 155 | IORQ_n <= IntCycle_n; 156 | end if; 157 | if TState = "011" then 158 | MREQ_n <= '0'; 159 | end if; 160 | else 161 | if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then 162 | RD_n <= '0'; 163 | IORQ_n <= not IORQ; 164 | MREQ_n <= IORQ; 165 | end if; 166 | if ((TState = "001") or (TState = "010")) and Write = '1' then 167 | WR_n <= '0'; 168 | IORQ_n <= not IORQ; 169 | MREQ_n <= IORQ; 170 | end if; 171 | end if; 172 | if TState = "010" and Wait_n = '1' then 173 | DI_Reg <= DI; 174 | end if; 175 | end if; 176 | end if; 177 | end process; 178 | 179 | end; 180 | -------------------------------------------------------------------------------- /src/fpga/apf/common.v: -------------------------------------------------------------------------------- 1 | // Software License Agreement 2 | 3 | // The software supplied herewith by Analogue Enterprises Limited (the "Company”), 4 | // the Analogue Pocket Framework (“APF”), is provided and licensed to you, the 5 | // Company's customer, solely for use in designing, testing and creating 6 | // applications for use with Company's Products or Services. The software is 7 | // owned by the Company and/or its licensors, and is protected under applicable 8 | // laws, including, but not limited to, U.S. copyright law. All rights are 9 | // reserved. By using the APF code you are agreeing to the terms of the End User 10 | // License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] 11 | // and incorporated herein by reference. To the extent any use of the APF requires 12 | // application of the MIT License or the GNU General Public License and terms of 13 | // this APF Software License Agreement and EULA are inconsistent with such license, 14 | // the applicable terms of the MIT License or the GNU General Public License, as 15 | // applicable, will prevail. 16 | 17 | // THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED 18 | // WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, 19 | // ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR 20 | // NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM 21 | // DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE 22 | // MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, 23 | // THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND 24 | // DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING 25 | // THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR 26 | // ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY 27 | // INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, 28 | // INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR 29 | // INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY 30 | // OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY 31 | // CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, 32 | // WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU 33 | // TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH 34 | // YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE 35 | // FULLEST EXTENT PERMITTED BY APPLICABLE LAW. 36 | // 37 | // 2-stage synchronizer 38 | // 39 | module synch_2 #(parameter WIDTH = 1) ( 40 | input wire [WIDTH-1:0] i, // input signal 41 | output reg [WIDTH-1:0] o, // synchronized output 42 | input wire clk, // clock to synchronize on 43 | output wire rise, // one-cycle rising edge pulse 44 | output wire fall // one-cycle falling edge pulse 45 | ); 46 | 47 | reg [WIDTH-1:0] stage_1; 48 | reg [WIDTH-1:0] stage_2; 49 | reg [WIDTH-1:0] stage_3; 50 | 51 | assign rise = (WIDTH == 1) ? (o & ~stage_2) : 1'b0; 52 | assign fall = (WIDTH == 1) ? (~o & stage_2) : 1'b0; 53 | always @(posedge clk) 54 | {stage_2, o, stage_1} <= {o, stage_1, i}; 55 | 56 | endmodule 57 | 58 | 59 | // 60 | // 3-stage synchronizer 61 | // 62 | module synch_3 #(parameter WIDTH = 1) ( 63 | input wire [WIDTH-1:0] i, // input signal 64 | output reg [WIDTH-1:0] o, // synchronized output 65 | input wire clk, // clock to synchronize on 66 | output wire rise, // one-cycle rising edge pulse 67 | output wire fall // one-cycle falling edge pulse 68 | ); 69 | 70 | reg [WIDTH-1:0] stage_1; 71 | reg [WIDTH-1:0] stage_2; 72 | reg [WIDTH-1:0] stage_3; 73 | 74 | assign rise = (WIDTH == 1) ? (o & ~stage_3) : 1'b0; 75 | assign fall = (WIDTH == 1) ? (~o & stage_3) : 1'b0; 76 | always @(posedge clk) 77 | {stage_3, o, stage_2, stage_1} <= {o, stage_2, stage_1, i}; 78 | 79 | endmodule 80 | 81 | 82 | module bram_block_dp #( 83 | parameter DATA = 32, 84 | parameter ADDR = 7 85 | ) ( 86 | input wire a_clk, 87 | input wire a_wr, 88 | input wire [ADDR-1:0] a_addr, 89 | input wire [DATA-1:0] a_din, 90 | output reg [DATA-1:0] a_dout, 91 | 92 | input wire b_clk, 93 | input wire b_wr, 94 | input wire [ADDR-1:0] b_addr, 95 | input wire [DATA-1:0] b_din, 96 | output reg [DATA-1:0] b_dout 97 | ); 98 | 99 | reg [DATA-1:0] mem [(2**ADDR)-1:0]; 100 | 101 | always @(posedge a_clk) begin 102 | if(a_wr) begin 103 | a_dout <= a_din; 104 | mem[a_addr] <= a_din; 105 | end else 106 | a_dout <= mem[a_addr]; 107 | end 108 | 109 | always @(posedge b_clk) begin 110 | if(b_wr) begin 111 | b_dout <= b_din; 112 | mem[b_addr] <= b_din; 113 | end else 114 | b_dout <= mem[b_addr]; 115 | end 116 | 117 | endmodule 118 | 119 | 120 | module bram_block_dp_nonstd #( 121 | parameter DATA = 32, 122 | parameter ADDR = 7, 123 | parameter DEPTH = 128 124 | ) ( 125 | input wire a_clk, 126 | input wire a_wr, 127 | input wire [ADDR-1:0] a_addr, 128 | input wire [DATA-1:0] a_din, 129 | output reg [DATA-1:0] a_dout, 130 | 131 | input wire b_clk, 132 | input wire b_wr, 133 | input wire [ADDR-1:0] b_addr, 134 | input wire [DATA-1:0] b_din, 135 | output reg [DATA-1:0] b_dout 136 | ); 137 | 138 | reg [DATA-1:0] mem [DEPTH-1:0]; 139 | 140 | always @(posedge a_clk) begin 141 | if(a_wr) begin 142 | a_dout <= a_din; 143 | mem[a_addr] <= a_din; 144 | end else 145 | a_dout <= mem[a_addr]; 146 | end 147 | 148 | always @(posedge b_clk) begin 149 | if(b_wr) begin 150 | b_dout <= b_din; 151 | mem[b_addr] <= b_din; 152 | end else 153 | b_dout <= mem[b_addr]; 154 | end 155 | 156 | endmodule 157 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/T80/T80s.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Z80 compatible microprocessor core, synchronous top level 3 | -- Different timing than the original z80 4 | -- Inputs needs to be synchronous and outputs may glitch 5 | -- 6 | -- Version : 0242 7 | -- 8 | -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | -- Redistribution and use in source and synthezised forms, with or without 13 | -- modification, are permitted provided that the following conditions are met: 14 | -- 15 | -- Redistributions of source code must retain the above copyright notice, 16 | -- this list of conditions and the following disclaimer. 17 | -- 18 | -- Redistributions in synthesized form must reproduce the above copyright 19 | -- notice, this list of conditions and the following disclaimer in the 20 | -- documentation and/or other materials provided with the distribution. 21 | -- 22 | -- Neither the name of the author nor the names of other contributors may 23 | -- be used to endorse or promote products derived from this software without 24 | -- specific prior written permission. 25 | -- 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 | -- POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | -- Please report bugs to the author, but before you do so, please 39 | -- make sure that this is not a derivative work and that 40 | -- you have the latest version of this file. 41 | -- 42 | -- The latest version of this file can be found at: 43 | -- http://www.opencores.org/cvsweb.shtml/t80/ 44 | -- 45 | -- Limitations : 46 | -- 47 | -- File history : 48 | -- 49 | -- 0208 : First complete release 50 | -- 51 | -- 0210 : Fixed read with wait 52 | -- 53 | -- 0211 : Fixed interrupt cycle 54 | -- 55 | -- 0235 : Updated for T80 interface change 56 | -- 57 | -- 0236 : Added T2Write generic 58 | -- 59 | -- 0237 : Fixed T2Write with wait state 60 | -- 61 | -- 0238 : Updated for T80 interface change 62 | -- 63 | -- 0240 : Updated for T80 interface change 64 | -- 65 | -- 0242 : Updated for T80 interface change 66 | -- 67 | 68 | library IEEE; 69 | use IEEE.std_logic_1164.all; 70 | use IEEE.numeric_std.all; 71 | use IEEE.STD_LOGIC_UNSIGNED.all; 72 | use work.T80_Pack.all; 73 | 74 | entity T80s is 75 | generic( 76 | Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB 77 | T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 78 | IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle 79 | ); 80 | port( 81 | RESET_n : in std_logic; 82 | CLK : in std_logic; 83 | CEN : in std_logic := '1'; 84 | WAIT_n : in std_logic := '1'; 85 | INT_n : in std_logic := '1'; 86 | NMI_n : in std_logic := '1'; 87 | BUSRQ_n : in std_logic := '1'; 88 | M1_n : out std_logic; 89 | MREQ_n : out std_logic; 90 | IORQ_n : out std_logic; 91 | RD_n : out std_logic; 92 | WR_n : out std_logic; 93 | RFSH_n : out std_logic; 94 | HALT_n : out std_logic; 95 | BUSAK_n : out std_logic; 96 | OUT0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255 97 | A : out std_logic_vector(15 downto 0); 98 | DI : in std_logic_vector(7 downto 0); 99 | DO : out std_logic_vector(7 downto 0) 100 | ); 101 | end T80s; 102 | 103 | architecture rtl of T80s is 104 | 105 | signal IntCycle_n : std_logic; 106 | signal NoRead : std_logic; 107 | signal Write : std_logic; 108 | signal IORQ : std_logic; 109 | signal DI_Reg : std_logic_vector(7 downto 0); 110 | signal MCycle : std_logic_vector(2 downto 0); 111 | signal TState : std_logic_vector(2 downto 0); 112 | 113 | begin 114 | 115 | u0 : T80 116 | generic map( 117 | Mode => Mode, 118 | IOWait => IOWait) 119 | port map( 120 | CEN => CEN, 121 | M1_n => M1_n, 122 | IORQ => IORQ, 123 | NoRead => NoRead, 124 | Write => Write, 125 | RFSH_n => RFSH_n, 126 | HALT_n => HALT_n, 127 | WAIT_n => Wait_n, 128 | INT_n => INT_n, 129 | NMI_n => NMI_n, 130 | RESET_n => RESET_n, 131 | BUSRQ_n => BUSRQ_n, 132 | BUSAK_n => BUSAK_n, 133 | CLK_n => CLK, 134 | A => A, 135 | DInst => DI, 136 | DI => DI_Reg, 137 | DO => DO, 138 | MC => MCycle, 139 | TS => TState, 140 | OUT0 => OUT0, 141 | IntCycle_n => IntCycle_n 142 | ); 143 | 144 | process (RESET_n, CLK) 145 | begin 146 | if RESET_n = '0' then 147 | RD_n <= '1'; 148 | WR_n <= '1'; 149 | IORQ_n <= '1'; 150 | MREQ_n <= '1'; 151 | DI_Reg <= "00000000"; 152 | elsif rising_edge(CLK) then 153 | if CEN = '1' then 154 | RD_n <= '1'; 155 | WR_n <= '1'; 156 | IORQ_n <= '1'; 157 | MREQ_n <= '1'; 158 | if MCycle = 1 then 159 | if TState = 1 or (TState = 2 and Wait_n = '0') then 160 | RD_n <= not IntCycle_n; 161 | MREQ_n <= not IntCycle_n; 162 | IORQ_n <= IntCycle_n; 163 | end if; 164 | if TState = 3 then 165 | MREQ_n <= '0'; 166 | end if; 167 | else 168 | if (TState = 1 or (TState = 2 and Wait_n = '0')) and NoRead = '0' and Write = '0' then 169 | RD_n <= '0'; 170 | IORQ_n <= not IORQ; 171 | MREQ_n <= IORQ; 172 | end if; 173 | if T2Write = 0 then 174 | if TState = 2 and Write = '1' then 175 | WR_n <= '0'; 176 | IORQ_n <= not IORQ; 177 | MREQ_n <= IORQ; 178 | end if; 179 | else 180 | if (TState = 1 or (TState = 2 and Wait_n = '0')) and Write = '1' then 181 | WR_n <= '0'; 182 | IORQ_n <= not IORQ; 183 | MREQ_n <= IORQ; 184 | end if; 185 | end if; 186 | end if; 187 | if TState = 2 and Wait_n = '1' then 188 | DI_Reg <= DI; 189 | end if; 190 | end if; 191 | end if; 192 | end process; 193 | end; 194 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_iir_filter.v: -------------------------------------------------------------------------------- 1 | /*MIT License 2 | Copyright (c) 2019 Gregory Hogan (Soltan_G42) 3 | Permission is hereby granted, free of charge, to any person obtaining a copy 4 | of this software and associated documentation files (the "Software"), to deal 5 | in the Software without restriction, including without limitation the rights 6 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | copies of the Software, and to permit persons to whom the Software is 8 | furnished to do so, subject to the following conditions: 9 | The above copyright notice and this permission notice shall be included in all 10 | copies or substantial portions of the Software. 11 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 12 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 13 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 14 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 15 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 16 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 17 | SOFTWARE.*/ 18 | 19 | module iir_1st_order 20 | #( 21 | parameter COEFF_WIDTH = 18, 22 | parameter COEFF_SCALE = 15, 23 | parameter DATA_WIDTH = 16, 24 | parameter COUNT_BITS = 11 25 | ) 26 | ( 27 | input clk, 28 | input reset, 29 | input [COUNT_BITS - 1 : 0] div, 30 | input signed [COEFF_WIDTH - 1 : 0] A2, B1, B2, 31 | input signed [DATA_WIDTH - 1 :0] in, 32 | output signed [DATA_WIDTH - 1:0] out 33 | ); 34 | 35 | reg signed [DATA_WIDTH-1:0] x0,x1,y0; 36 | reg signed [DATA_WIDTH + COEFF_WIDTH - 1 : 0] out32; 37 | reg [COUNT_BITS - 1:0] count; 38 | 39 | // Usage: 40 | // Design your 1st order iir low/high-pass with a tool that will give you the 41 | // filter coefficients for the difference equation. Filter coefficients can 42 | // be generated in Octave/matlab/scipy using a command similar to 43 | // [B, A] = butter( 1, 3500/(106528/2), 'low') for a 3500 hz 1st order low-pass 44 | // assuming 106528Hz sample rate. 45 | // 46 | // The Matlab output is: 47 | // B = [0.093863 0.093863] 48 | // A = [1.00000 -0.81227] 49 | // 50 | // Then scale coefficients by multiplying by 2^COEFF_SCALE and round to nearest integer 51 | // 52 | // B = [3076 3076] 53 | // A = [32768 -26616] 54 | // 55 | // Discard A(1) because it is assumed 1.0 before scaling 56 | // 57 | // This leaves you with A2 = -26616 , B1 = 3076 , B2 = 3076 58 | // B1 + B2 - A2 should sum to 2^COEFF_SCALE = 32768 59 | // 60 | // Sample frequency is "clk rate/div": for Genesis this is 53.69mhz/504 = 106528hz 61 | // 62 | // COEFF_WIDTH must be at least COEFF_SCALE+1 and must be large enough to 63 | // handle temporary overflow during this computation: out32 <= (B1*x0 + B2*x1) - A2*y0 64 | 65 | assign out = y0; 66 | 67 | always @ (*) begin 68 | out32 <= (B1*x0 + B2*x1) - A2*y0; //Previous output is y0 not y1 69 | end 70 | 71 | always @ (posedge clk) begin 72 | if(reset) begin 73 | count <= 0; 74 | x0 <= 0; 75 | x1 <= 0; 76 | y0 <= 0; 77 | end 78 | else begin 79 | count <= count + 1'd1; 80 | if (count == div - 1) begin 81 | count <= 0; 82 | y0 <= {out32[DATA_WIDTH + COEFF_WIDTH - 1] , out32[COEFF_SCALE + DATA_WIDTH - 2 : COEFF_SCALE]}; 83 | x1 <= x0; 84 | x0 <= in; 85 | end 86 | end 87 | end 88 | 89 | endmodule //iir_1st_order 90 | 91 | 92 | 93 | module iir_2nd_order 94 | #( 95 | parameter COEFF_WIDTH = 18, 96 | parameter COEFF_SCALE = 14, 97 | parameter DATA_WIDTH = 16, 98 | parameter COUNT_BITS = 10 99 | ) 100 | ( 101 | input clk, 102 | input reset, 103 | input [COUNT_BITS - 1 : 0] div, 104 | input signed [COEFF_WIDTH - 1 : 0] A2, A3, B1, B2, B3, 105 | input signed [DATA_WIDTH - 1 : 0] in, 106 | output [DATA_WIDTH - 1 : 0] out 107 | ); 108 | 109 | reg signed [DATA_WIDTH-1 : 0] x0,x1,x2; 110 | reg signed [DATA_WIDTH-1 : 0] y0,y1; 111 | reg signed [(DATA_WIDTH + COEFF_WIDTH - 1) : 0] out32; 112 | reg [COUNT_BITS : 0] count; 113 | 114 | 115 | // Usage: 116 | // Design your 1st order iir low/high-pass with a tool that will give you the 117 | // filter coefficients for the difference equation. Filter coefficients can 118 | // be generated in Octave/matlab/scipy using a command similar to 119 | // [B, A] = butter( 2, 5000/(48000/2), 'low') for a 5000 hz 2nd order low-pass 120 | // assuming 48000Hz sample rate. 121 | // 122 | // Output is: 123 | // B = [ 0.072231 0.144462 0.072231] 124 | // A = [1.00000 -1.10923 0.39815] 125 | // 126 | // Then scale coefficients by multiplying by 2^COEFF_SCALE and round to nearest integer 127 | // Make sure your coefficients can be stored as a signed number with COEFF_WIDTH bits. 128 | // 129 | // B = [1183 2367 1183] 130 | // A = [16384 -18174 6523] 131 | // 132 | // Discard A(1) because it is assumed 1.0 before scaling 133 | // 134 | // This leaves you with A2 = -18174 , A3 = 6523, B1 = 1183 , B2 = 2367 , B3 = 1183 135 | // B1 + B2 + B3 - A2 - A3 should sum to 2^COEFF_SCALE = 16384 136 | // 137 | // Sample frequency is "clk rate/div" 138 | // 139 | // COEFF_WIDTH must be at least COEFF_SCALE+1 and must be large enough to 140 | // handle temporary overflow during this computation: 141 | // out32 <= (B1*x0 + B2*x1 + B3*x2) - (A2*y0 + A3*y1); 142 | 143 | assign out = y0; 144 | 145 | always @ (*) begin 146 | out32 <= (B1*x0 + B2*x1 + B3*x2) - (A2*y0 + A3*y1); //Previous output is y0 not y1 147 | end 148 | 149 | always @ (posedge clk) begin 150 | if(reset) begin 151 | count <= 0; 152 | x0 <= 0; 153 | x1 <= 0; 154 | x2 <= 0; 155 | y0 <= 0; 156 | y1 <= 0; 157 | end 158 | else begin 159 | count <= count + 1'd1; 160 | if (count == div - 1) begin 161 | count <= 0; 162 | y1 <= y0; 163 | y0 <= {out32[DATA_WIDTH + COEFF_WIDTH - 1] , out32[(DATA_WIDTH + COEFF_SCALE - 2) : COEFF_SCALE]}; 164 | x2 <= x1; 165 | x1 <= x0; 166 | x0 <= in; 167 | end 168 | end 169 | end 170 | 171 | endmodule //iir_2nd_order 172 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mario_bram.v: -------------------------------------------------------------------------------- 1 | //------------------- 2 | // Block RAM modules 3 | //------------------- 4 | 5 | module ram_1024_8_8 6 | ( 7 | input I_CLKA,I_CLKB, 8 | input [9:0]I_ADDRA,I_ADDRB, 9 | input [7:0]I_DA,I_DB, 10 | input I_CEA,I_CEB, 11 | input I_WEA,I_WEB, 12 | output [7:0]O_DA,O_DB 13 | ); 14 | 15 | wire [7:0]W_DOA,W_DOB; 16 | assign O_DA = I_CEA ? W_DOA : 8'h00; 17 | assign O_DB = I_CEB ? W_DOB : 8'h00; 18 | 19 | dpram #(10,8) ram_1024_8_8 20 | ( 21 | .clock_a(I_CLKA), 22 | .address_a(I_ADDRA), 23 | .data_a(I_DA), 24 | .enable_a(I_CEA), 25 | .wren_a(I_WEA), 26 | .q_a(W_DOA), 27 | 28 | .clock_b(I_CLKB), 29 | .address_b(I_ADDRB), 30 | .data_b(I_DB), 31 | .enable_b(I_CEB), 32 | .wren_b(I_WEB), 33 | .q_b(W_DOB) 34 | ); 35 | 36 | endmodule 37 | 38 | ///////////////////////////////////////////////////////////////////// 39 | 40 | module ram_1024_8 41 | ( 42 | input I_CLK, 43 | input [9:0]I_ADDR, 44 | input [7:0]I_D, 45 | input I_CE, 46 | input I_WE, 47 | output [7:0]O_D 48 | ); 49 | 50 | wire [7:0]W_DO; 51 | assign O_D = I_CE ? W_DO : 8'h00; 52 | 53 | dpram #(10,8) ram_1024_8 54 | ( 55 | .clock_a(I_CLK), 56 | .address_a(I_ADDR), 57 | .data_a(I_D), 58 | .wren_a(I_WE), 59 | .enable_a(I_CE), 60 | .q_a(W_DO), 61 | 62 | .clock_b(I_CLK) 63 | ); 64 | 65 | endmodule 66 | 67 | ///////////////////////////////////////////////////////////////////// 68 | 69 | module ram_2N 70 | ( 71 | input I_CLK, 72 | input [7:0]I_ADDR, 73 | input [3:0]I_D, 74 | input I_CE, 75 | input I_WE, 76 | output [3:0]O_D 77 | ); 78 | 79 | dpram #(8,4) ram_256_4 80 | ( 81 | .clock_a(I_CLK), 82 | .address_a(I_ADDR), 83 | .data_a(I_D), 84 | .wren_a(I_WE), 85 | .enable_a(I_CE), 86 | .q_a(O_D), 87 | 88 | .clock_b(I_CLK) 89 | ); 90 | 91 | endmodule 92 | 93 | ///////////////////////////////////////////////////////////////////// 94 | 95 | module ram_256_8 96 | ( 97 | input I_CLKA, 98 | input [7:0]I_ADDRA, 99 | input [7:0]I_DA, 100 | input I_CEA, 101 | input I_WEA, 102 | output [7:0]O_DA 103 | ); 104 | 105 | dpram #(8,8) ram_256_8 106 | ( 107 | .clock_a(I_CLKA), 108 | .address_a(I_ADDRA), 109 | .data_a(I_DA), 110 | .enable_a(I_CEA), 111 | .wren_a(I_WEA), 112 | .q_a(O_DA), 113 | 114 | .clock_b(I_CLKA) 115 | ); 116 | 117 | endmodule 118 | 119 | ///////////////////////////////////////////////////////////////////// 120 | 121 | module ram_64_9 122 | ( 123 | input I_CLKA, 124 | input [5:0]I_ADDRA, 125 | input [8:0]I_DA, 126 | input I_CEA, 127 | input I_WEA, 128 | output [8:0]O_DA 129 | ); 130 | 131 | 132 | dpram #(6,9) ram_64x9 133 | ( 134 | .clock_a(I_CLKA), 135 | .address_a(I_ADDRA), 136 | .data_a(I_DA), 137 | .enable_a(I_CEA), 138 | .wren_a(I_WEA), 139 | .q_a(O_DA), 140 | 141 | .clock_b(I_CLKA) 142 | ); 143 | 144 | endmodule 145 | 146 | ///////////////////////////////////////////////////////////////////// 147 | 148 | module ram_2EF 149 | ( 150 | input I_CLKA,I_CLKB, 151 | input [7:0]I_ADDRA,I_ADDRB, 152 | input [7:0]I_DA,I_DB, 153 | input I_CEA,I_CEB, 154 | input I_WEA,I_WEB, 155 | output [7:0]O_DA,O_DB 156 | ); 157 | 158 | dpram #(9,8) ram_512_8 159 | ( 160 | .clock_a(I_CLKA), 161 | .address_a({1'b0,I_ADDRA}), 162 | .data_a(I_DA), 163 | .enable_a(I_CEA), 164 | .wren_a(I_WEA), 165 | .q_a(O_DA), 166 | 167 | .clock_b(I_CLKB), 168 | .address_b({1'b1,I_ADDRB}), 169 | .data_b(I_DB), 170 | .enable_b(I_CEB), 171 | .wren_b(I_WEB), 172 | .q_b(O_DB) 173 | ); 174 | 175 | endmodule 176 | 177 | ///////////////////////////////////////////////////////////////////// 178 | 179 | module double_scan 180 | ( 181 | input I_CLKA,I_CLKB, 182 | input [8:0]I_ADDRA,I_ADDRB, 183 | input [7:0]I_DA,I_DB, 184 | input I_CEA,I_CEB, 185 | input I_WEA,I_WEB, 186 | output [7:0]O_DA,O_DB 187 | ); 188 | 189 | dpram #(9,8) ram_512_8 190 | ( 191 | .clock_a(I_CLKA), 192 | .address_a(I_ADDRA), 193 | .data_a(I_DA), 194 | .enable_a(I_CEA), 195 | .wren_a(I_WEA), 196 | .q_a(O_DA), 197 | 198 | .clock_b(I_CLKB), 199 | .address_b(I_ADDRB), 200 | .data_b(I_DB), 201 | .enable_b(I_CEB), 202 | .wren_b(I_WEB), 203 | .q_b(O_DB) 204 | ); 205 | 206 | endmodule 207 | 208 | ///////////////////////////////////////////////////////////////////// 209 | 210 | module ram_128_8 211 | ( 212 | input I_CLK, 213 | input [6:0]I_ADDR, 214 | input [7:0]I_D, 215 | input I_CE, 216 | input I_WE, 217 | output [7:0]O_D 218 | ); 219 | 220 | dpram #(7,8) ram_128_8 221 | ( 222 | .clock_a(I_CLK), 223 | .address_a(I_ADDR), 224 | .data_a(I_D), 225 | .wren_a(I_WE), 226 | .enable_a(I_CE), 227 | .q_a(O_D), 228 | 229 | .clock_b(I_CLK) 230 | ); 231 | 232 | endmodule 233 | 234 | ///////////////////////////////////////////////////////////////////// 235 | 236 | module ram_2048_8_8 237 | ( 238 | input I_CLKA,I_CLKB, 239 | input [10:0]I_ADDRA,I_ADDRB, 240 | input [7:0]I_DA,I_DB, 241 | input I_CEA,I_CEB, 242 | input I_OEA,I_OEB, 243 | input I_WEA,I_WEB, 244 | output [7:0]O_DA,O_DB 245 | ); 246 | 247 | wire [7:0]W_DOA,W_DOB; 248 | assign O_DA = I_CEA & I_OEA ? W_DOA : 8'h00; 249 | assign O_DB = I_CEB & I_OEB ? W_DOB : 8'h00; 250 | 251 | dpram #(11,8) ram_2048_8_8 252 | ( 253 | .clock_a(I_CLKA), 254 | .address_a(I_ADDRA), 255 | .data_a(I_DA), 256 | .enable_a(I_CEA), 257 | .wren_a(I_WEA), 258 | .q_a(W_DOA), 259 | 260 | .clock_b(I_CLKB), 261 | .address_b(I_ADDRB), 262 | .data_b(I_DB), 263 | .enable_b(I_CEB), 264 | .wren_b(I_WEB), 265 | .q_b(W_DOB) 266 | ); 267 | 268 | endmodule 269 | 270 | 271 | ///////////////////////////////////////////////////////////////////// 272 | 273 | 274 | module ram_2048_8 275 | ( 276 | input I_CLK, 277 | input [10:0]I_ADDR, 278 | input [7:0]I_D, 279 | input I_CE, 280 | input I_WE, 281 | output [7:0]O_D 282 | ); 283 | 284 | dpram #(11,8) ram_2048_8 285 | ( 286 | .clock_a(I_CLK), 287 | .address_a(I_ADDR), 288 | .data_a(I_D), 289 | .wren_a(I_WE), 290 | .enable_a(I_CE), 291 | .q_a(O_D), 292 | 293 | .clock_b(I_CLK) 294 | ); 295 | 296 | endmodule 297 | 298 | ///////////////////////////////////////////////////////////////////// 299 | 300 | module ram_4096_8 301 | ( 302 | input I_CLK, 303 | input [11:0]I_ADDR, 304 | input [7:0]I_D, 305 | input I_CE, 306 | input I_WE, 307 | output [7:0]O_D 308 | ); 309 | 310 | 311 | dpram #(12,8) ram_4096_8 312 | ( 313 | .clock_a(I_CLK), 314 | .address_a(I_ADDR), 315 | .data_a(I_D), 316 | .wren_a(I_WE), 317 | .enable_a(I_CE), 318 | .q_a(O_D), 319 | 320 | .clock_b(I_CLK) 321 | ); 322 | 323 | endmodule 324 | 325 | --------------------------------------------------------------------------------