├── LICENSE ├── README.md ├── TODO ├── docs └── instructionSetArchitecture.ods ├── img ├── cpuSchematic.png ├── fib.gif ├── fib.jpg ├── hiWorld.gif ├── hiWorld.jpeg ├── hiWorld.mov └── topLevelSchematic.png └── src ├── .gitignore ├── assembler ├── .gitignore ├── Makefile └── main.cpp ├── computer ├── .gitignore ├── Computer8Bit.cache │ └── wt │ │ └── webtalk_pa.xml ├── Computer8Bit.hw │ └── hw_1 │ │ └── hw.xml ├── Computer8Bit.ip_user_files │ └── README.txt ├── Computer8Bit.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_10.xml │ │ ├── vrs_config_11.xml │ │ ├── vrs_config_12.xml │ │ ├── vrs_config_13.xml │ │ ├── vrs_config_14.xml │ │ ├── vrs_config_15.xml │ │ ├── vrs_config_16.xml │ │ ├── vrs_config_17.xml │ │ ├── vrs_config_18.xml │ │ ├── vrs_config_19.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_20.xml │ │ ├── vrs_config_21.xml │ │ ├── vrs_config_22.xml │ │ ├── vrs_config_23.xml │ │ ├── vrs_config_24.xml │ │ ├── vrs_config_25.xml │ │ ├── vrs_config_26.xml │ │ ├── vrs_config_27.xml │ │ ├── vrs_config_28.xml │ │ ├── vrs_config_29.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_4.xml │ │ ├── vrs_config_5.xml │ │ ├── vrs_config_6.xml │ │ ├── vrs_config_7.xml │ │ ├── vrs_config_8.xml │ │ └── vrs_config_9.xml │ ├── impl_1 │ │ ├── Computer.tcl │ │ ├── Computer.vdi │ │ ├── Computer_bus_skew_routed.pb │ │ ├── Computer_bus_skew_routed.rpt │ │ ├── Computer_clock_utilization_routed.rpt │ │ ├── Computer_control_sets_placed.rpt │ │ ├── Computer_drc_opted.pb │ │ ├── Computer_drc_opted.rpt │ │ ├── Computer_drc_routed.pb │ │ ├── Computer_drc_routed.rpt │ │ ├── Computer_io_placed.rpt │ │ ├── Computer_methodology_drc_routed.pb │ │ ├── Computer_methodology_drc_routed.rpt │ │ ├── Computer_opt.dcp │ │ ├── Computer_physopt.dcp │ │ ├── Computer_placed.dcp │ │ ├── Computer_power_routed.rpt │ │ ├── Computer_power_summary_routed.pb │ │ ├── Computer_route_status.pb │ │ ├── Computer_route_status.rpt │ │ ├── Computer_routed.dcp │ │ ├── Computer_timing_summary_routed.pb │ │ ├── Computer_timing_summary_routed.rpt │ │ ├── Computer_utilization_placed.pb │ │ ├── Computer_utilization_placed.rpt │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── phys_opt_design.pb │ │ ├── place_design.pb │ │ ├── route_design.pb │ │ ├── usage_statistics_webtalk.xml │ │ ├── vivado.jou │ │ ├── vivado.pb │ │ ├── vivado_57835.backup.jou │ │ └── write_bitstream.pb │ └── synth_1 │ │ ├── .Xil │ │ └── Computer_propImpl.xdc │ │ ├── Computer.dcp │ │ ├── Computer.tcl │ │ ├── Computer.vds │ │ ├── Computer_utilization_synth.pb │ │ ├── Computer_utilization_synth.rpt │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── vivado.jou │ │ └── vivado.pb ├── Computer8Bit.sim │ └── sim_1 │ │ └── behav │ │ └── xsim │ │ ├── Computer_tb.tcl │ │ ├── Computer_tb_vhdl.prj │ │ ├── Register_tb.tcl │ │ ├── Register_tb_vhdl.prj │ │ ├── webtalk.jou │ │ ├── webtalk_12826.backup.jou │ │ ├── webtalk_13209.backup.jou │ │ ├── webtalk_1750373.backup.jou │ │ ├── webtalk_1751994.backup.jou │ │ ├── webtalk_26033.backup.jou │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── Computer_tb_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ └── xsim_1.c │ │ │ ├── webtalk │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ └── xsim.mem │ │ └── Register_tb_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ └── xsim_1.c │ │ │ ├── webtalk │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ └── xsim_webtalk.tcl │ │ │ └── xsim.mem │ │ └── xvhdl.pb ├── Computer8Bit.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── computer_xdc.xdc │ ├── sim_1 │ │ └── new │ │ │ ├── Computer_tb.vhd │ │ │ └── Register_tb.vhd │ └── sources_1 │ │ └── new │ │ ├── ALU.vhd │ │ ├── CPU.vhd │ │ ├── Computer.vhd │ │ ├── ControlUnit.vhd │ │ ├── HexToSseg.vhd │ │ ├── IO.vhd │ │ ├── IndexRegister.vhd │ │ ├── ModMCounter.vhd │ │ ├── PIPORegister.vhd │ │ ├── ProgramCounter.vhd │ │ ├── RAM.vhd │ │ ├── ROM.vhd │ │ ├── RegisterBank.vhd │ │ ├── SixteenBitDisplay.vhd │ │ ├── SixteenToFourMux.vhd │ │ └── StackPointer.vhd ├── Computer8Bit.xpr ├── Computer_tb_behav.wcfg ├── Computer_tb_behav1.wcfg └── Computer_tb_behav2.wcfg ├── prog.bin └── programs ├── add.asm ├── fullTest.asm ├── helloWorld.asm ├── mul.asm └── printFib.asm /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 Kent Odde 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /TODO: -------------------------------------------------------------------------------- 1 | Clean up control unit, create modules 2 | Implement division in ALU 3 | Implement binary literals in assembler 4 | Implement address offset in ldw and stw 5 | Implement possibility for variables in assembler 6 | Clean up assembler 7 | 8 | -------------------------------------------------------------------------------- /docs/instructionSetArchitecture.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/docs/instructionSetArchitecture.ods -------------------------------------------------------------------------------- /img/cpuSchematic.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/img/cpuSchematic.png -------------------------------------------------------------------------------- /img/fib.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/img/fib.gif -------------------------------------------------------------------------------- /img/fib.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/img/fib.jpg -------------------------------------------------------------------------------- /img/hiWorld.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/img/hiWorld.gif -------------------------------------------------------------------------------- /img/hiWorld.jpeg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/img/hiWorld.jpeg -------------------------------------------------------------------------------- /img/hiWorld.mov: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/img/hiWorld.mov -------------------------------------------------------------------------------- /img/topLevelSchematic.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/img/topLevelSchematic.png -------------------------------------------------------------------------------- /src/.gitignore: -------------------------------------------------------------------------------- 1 | prog.bin 2 | -------------------------------------------------------------------------------- /src/assembler/.gitignore: -------------------------------------------------------------------------------- 1 | assembler 2 | *.o 3 | -------------------------------------------------------------------------------- /src/assembler/Makefile: -------------------------------------------------------------------------------- 1 | 2 | PROG = assembler 3 | 4 | CC = g++ 5 | CXXFLAGS = -Wall -Wextra -std=c++17 6 | CPPFLAGS = #-I /usr/include -L /usr/lib 7 | SRC = $(wildcard *.cpp) 8 | OBJ = $(SRC:.cpp=.o) 9 | LDFLAGS = 10 | 11 | all: build run 12 | 13 | run: 14 | ./$(PROG) "fullTest.asm" "128" 15 | 16 | build: $(PROG) 17 | 18 | $(PROG): $(OBJ) 19 | $(CC) $(CXXFLAGS) -o $@ $(OBJ) $(CPPFLAGS) $(LDFLAGS) 20 | 21 | clean: 22 | rm -f *stackdump $(PROG) $(OBJ) 23 | -------------------------------------------------------------------------------- /src/computer/.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################################### 2 | ## This is an example .gitignore file for Vivado, please treat it as an example as 3 | ## it might not be complete. In addition, XAPP 1165 should be followed. 4 | ######################################################################################################### 5 | ######### 6 | #Exclude all 7 | ######### 8 | * 9 | !*/ 10 | !.gitignore 11 | ########################################################################### 12 | ## VIVADO 13 | ########################################################################### 14 | ######### 15 | #Source files: 16 | ######### 17 | #Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. 18 | !*.vhd 19 | !*.v 20 | !*.bd 21 | !*.edif 22 | ######### 23 | #IP files 24 | ######### 25 | #.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products 26 | #.xci + .dcp: implementation possible but not re-synthesis 27 | #*.xci(www.spiritconsortium.org) 28 | !*.xci 29 | #*.dcp(checkpoint files) 30 | !*.dcp 31 | !*.vds 32 | !*.pb 33 | #All bd comments and layout coordinates are stored within .ui 34 | !*.ui 35 | !*.ooc 36 | ######### 37 | #System Generator 38 | ######### 39 | !*.mdl 40 | !*.slx 41 | !*.bxml 42 | ######### 43 | #Simulation logic analyzer 44 | ######### 45 | !*.wcfg 46 | !*.coe 47 | ######### 48 | #MIG 49 | ######### 50 | !*.prj 51 | !*.mem 52 | ######### 53 | #Project files 54 | ######### 55 | #XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) 56 | #Do NOT ignore *.xpr files 57 | !*.xpr 58 | #Include *.xml files for 2013.4 or earlier version 59 | !*.xml 60 | ######### 61 | #Constraint files 62 | ######### 63 | #Do NOT ignore *.xdc files 64 | !*.xdc 65 | ######### 66 | #TCL - files 67 | ######### 68 | !*.tcl 69 | ######### 70 | #Journal - files 71 | ######### 72 | !*.jou 73 | ######### 74 | #Reports 75 | ######### 76 | !*.rpt 77 | !*.txt 78 | !*.vdi 79 | ######### 80 | #C-files 81 | ######### 82 | !*.c 83 | !*.h 84 | !*.elf 85 | !*.bmm 86 | !*.xmp 87 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.hw/hw_1/hw.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_10.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_11.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_12.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_13.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_14.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_15.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_16.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_17.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_18.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_19.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_2.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_20.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_21.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_22.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_23.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_24.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_25.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_26.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_27.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_28.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_29.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_3.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_4.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_5.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_6.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_7.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_8.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/.jobs/vrs_config_9.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_bus_skew_routed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/Computer_bus_skew_routed.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_bus_skew_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 2 | --------------------------------------------------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 4 | | Date : Sun Jan 10 14:14:30 2021 5 | | Host : kent-ThinkPad-T580 running 64-bit Ubuntu 20.04.1 LTS 6 | | Command : report_bus_skew -warn_on_violation -file Computer_bus_skew_routed.rpt -pb Computer_bus_skew_routed.pb -rpx Computer_bus_skew_routed.rpx 7 | | Design : Computer 8 | | Device : 7a35t-cpg236 9 | | Speed File : -1 PRODUCTION 1.23 2018-06-13 10 | --------------------------------------------------------------------------------------------------------------------------------------------------------- 11 | 12 | Bus Skew Report 13 | 14 | No bus skew constraints 15 | 16 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_control_sets_placed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 4 | | Date : Sun Jan 10 14:14:14 2021 5 | | Host : kent-ThinkPad-T580 running 64-bit Ubuntu 20.04.1 LTS 6 | | Command : report_control_sets -verbose -file Computer_control_sets_placed.rpt 7 | | Design : Computer 8 | | Device : xc7a35t 9 | ------------------------------------------------------------------------------------- 10 | 11 | Control Set Information 12 | 13 | Table of Contents 14 | ----------------- 15 | 1. Summary 16 | 2. Histogram 17 | 3. Flip-Flop Distribution 18 | 4. Detailed Control Set Information 19 | 20 | 1. Summary 21 | ---------- 22 | 23 | +----------------------------------------------------------+-------+ 24 | | Status | Count | 25 | +----------------------------------------------------------+-------+ 26 | | Total control sets | 20 | 27 | | Minimum number of control sets | 20 | 28 | | Addition due to synthesis replication | 0 | 29 | | Addition due to physical synthesis replication | 0 | 30 | | Unused register locations in slices containing registers | 36 | 31 | +----------------------------------------------------------+-------+ 32 | * Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers 33 | ** Run report_qor_suggestions for automated merging and remapping suggestions 34 | 35 | 36 | 2. Histogram 37 | ------------ 38 | 39 | +--------------------+-------+ 40 | | Fanout | Count | 41 | +--------------------+-------+ 42 | | Total control sets | 20 | 43 | | >= 0 to < 4 | 2 | 44 | | >= 4 to < 6 | 3 | 45 | | >= 6 to < 8 | 0 | 46 | | >= 8 to < 10 | 10 | 47 | | >= 10 to < 12 | 0 | 48 | | >= 12 to < 14 | 0 | 49 | | >= 14 to < 16 | 0 | 50 | | >= 16 | 5 | 51 | +--------------------+-------+ 52 | * Control sets can be remapped at either synth_design or opt_design 53 | 54 | 55 | 3. Flip-Flop Distribution 56 | ------------------------- 57 | 58 | +--------------+-----------------------+------------------------+-----------------+--------------+ 59 | | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | 60 | +--------------+-----------------------+------------------------+-----------------+--------------+ 61 | | No | No | No | 25 | 9 | 62 | | No | No | Yes | 31 | 9 | 63 | | No | Yes | No | 0 | 0 | 64 | | Yes | No | No | 17 | 5 | 65 | | Yes | No | Yes | 115 | 45 | 66 | | Yes | Yes | No | 0 | 0 | 67 | +--------------+-----------------------+------------------------+-----------------+--------------+ 68 | 69 | 70 | 4. Detailed Control Set Information 71 | ----------------------------------- 72 | 73 | +---------------------------------------------+---------------------------------------------------+------------------+------------------+----------------+--------------+ 74 | | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | 75 | +---------------------------------------------+---------------------------------------------------+------------------+------------------+----------------+--------------+ 76 | | processor/registers/reg_op/reg_reg[3]_4 | | | 1 | 1 | 1.00 | 77 | | ~modMillionCounter/r_reg_reg[0]_0_BUFG | processor/registers/reg_mem/E[0] | rst_IBUF | 1 | 3 | 3.00 | 78 | | clk_IBUF_BUFG | sseg/d_reg | rst_IBUF | 1 | 4 | 4.00 | 79 | | modMillionCounter/r_reg_reg[0]_0_BUFG | | rst_IBUF | 2 | 4 | 2.00 | 80 | | ~modMillionCounter/r_reg_reg[0]_0_BUFG | processor/cu/E[0] | rst_IBUF | 1 | 4 | 4.00 | 81 | | ~modMillionCounter/r_reg_reg[0]_0_BUFG | processor/cu/reg_reg[3][0] | rst_IBUF | 4 | 8 | 2.00 | 82 | | ~modMillionCounter/r_reg_reg[0]_0_BUFG | processor/cu/reg_reg[1][0] | rst_IBUF | 4 | 8 | 2.00 | 83 | | ~modMillionCounter/r_reg_reg[0]_0_BUFG | processor/cu/FSM_sequential_state_reg_reg[0]_6[0] | rst_IBUF | 3 | 8 | 2.67 | 84 | | ~modMillionCounter/r_reg_reg[0]_0_BUFG | processor/cu/FSM_sequential_state_reg_reg[0]_5[0] | rst_IBUF | 2 | 8 | 4.00 | 85 | | ~modMillionCounter/r_reg_reg[0]_0_BUFG | processor/cu/FSM_sequential_state_reg_reg[0]_7[0] | rst_IBUF | 2 | 8 | 4.00 | 86 | | ~modMillionCounter/r_reg_reg[0]_0_BUFG | processor/cu/FSM_sequential_state_reg_reg[0]_3[0] | rst_IBUF | 4 | 8 | 2.00 | 87 | | ~modMillionCounter/r_reg_reg[0]_0_BUFG | processor/cu/FSM_sequential_state_reg_reg[0]_2[0] | rst_IBUF | 5 | 8 | 1.60 | 88 | | ~modMillionCounter/r_reg_reg[0]_0_BUFG | processor/cu/FSM_sequential_state_reg_reg[0]_1[0] | rst_IBUF | 4 | 8 | 2.00 | 89 | | ~modMillionCounter/r_reg_reg[0]_0_BUFG | processor/registers/reg_mem/reg_reg[4]_0[0] | rst_IBUF | 3 | 8 | 2.67 | 90 | | processor/registers/reg_op/reg_reg[3]_5[0] | | | 3 | 8 | 2.67 | 91 | | ~modMillionCounter/r_reg_reg[0]_0_BUFG | processor/cu/cpu_rw | | 4 | 16 | 4.00 | 92 | | processor/registers/reg_op/reg_reg[0]_1[0] | | | 5 | 16 | 3.20 | 93 | | clk_IBUF_BUFG | sseg/sel | | 5 | 17 | 3.40 | 94 | | clk_IBUF_BUFG | | rst_IBUF | 7 | 27 | 3.86 | 95 | | modMillionCounter/r_reg_reg[0]_0_BUFG | processor/registers/reg_op/reg_reg[2]_0[0] | rst_IBUF | 11 | 32 | 2.91 | 96 | +---------------------------------------------+---------------------------------------------------+------------------+------------------+----------------+--------------+ 97 | 98 | 99 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_drc_opted.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/Computer_drc_opted.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_drc_opted.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 2 | --------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 4 | | Date : Sun Jan 10 14:14:10 2021 5 | | Host : kent-ThinkPad-T580 running 64-bit Ubuntu 20.04.1 LTS 6 | | Command : report_drc -file Computer_drc_opted.rpt -pb Computer_drc_opted.pb -rpx Computer_drc_opted.rpx 7 | | Design : Computer 8 | | Device : xc7a35tcpg236-1 9 | | Speed File : -1 10 | | Design State : Synthesized 11 | --------------------------------------------------------------------------------------------------------------- 12 | 13 | Report DRC 14 | 15 | Table of Contents 16 | ----------------- 17 | 1. REPORT SUMMARY 18 | 2. REPORT DETAILS 19 | 20 | 1. REPORT SUMMARY 21 | ----------------- 22 | Netlist: netlist 23 | Floorplan: design_1 24 | Design limits: 25 | Ruledeck: default 26 | Max violations: 27 | Violations found: 1 28 | +----------+----------+-----------------------------------------------------+------------+ 29 | | Rule | Severity | Description | Violations | 30 | +----------+----------+-----------------------------------------------------+------------+ 31 | | CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | 32 | +----------+----------+-----------------------------------------------------+------------+ 33 | 34 | 2. REPORT DETAILS 35 | ----------------- 36 | CFGBVS-1#1 Warning 37 | Missing CFGBVS and CONFIG_VOLTAGE Design Properties 38 | Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: 39 | 40 | set_property CFGBVS value1 [current_design] 41 | #where value1 is either VCCO or GND 42 | 43 | set_property CONFIG_VOLTAGE value2 [current_design] 44 | #where value2 is the voltage provided to configuration bank 0 45 | 46 | Refer to the device configuration user guide for more information. 47 | Related violations: 48 | 49 | 50 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_drc_routed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/Computer_drc_routed.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_drc_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 4 | | Date : Sun Jan 10 14:14:28 2021 5 | | Host : kent-ThinkPad-T580 running 64-bit Ubuntu 20.04.1 LTS 6 | | Command : report_drc -file Computer_drc_routed.rpt -pb Computer_drc_routed.pb -rpx Computer_drc_routed.rpx 7 | | Design : Computer 8 | | Device : xc7a35tcpg236-1 9 | | Speed File : -1 10 | | Design State : Fully Routed 11 | ------------------------------------------------------------------------------------------------------------------ 12 | 13 | Report DRC 14 | 15 | Table of Contents 16 | ----------------- 17 | 1. REPORT SUMMARY 18 | 2. REPORT DETAILS 19 | 20 | 1. REPORT SUMMARY 21 | ----------------- 22 | Netlist: netlist 23 | Floorplan: design_1 24 | Design limits: 25 | Ruledeck: default 26 | Max violations: 27 | Violations found: 4 28 | +----------+----------+-----------------------------------------------------+------------+ 29 | | Rule | Severity | Description | Violations | 30 | +----------+----------+-----------------------------------------------------+------------+ 31 | | CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | 32 | | PDRC-153 | Warning | Gated clock check | 3 | 33 | +----------+----------+-----------------------------------------------------+------------+ 34 | 35 | 2. REPORT DETAILS 36 | ----------------- 37 | CFGBVS-1#1 Warning 38 | Missing CFGBVS and CONFIG_VOLTAGE Design Properties 39 | Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: 40 | 41 | set_property CFGBVS value1 [current_design] 42 | #where value1 is either VCCO or GND 43 | 44 | set_property CONFIG_VOLTAGE value2 [current_design] 45 | #where value2 is the voltage provided to configuration bank 0 46 | 47 | Refer to the device configuration user guide for more information. 48 | Related violations: 49 | 50 | PDRC-153#1 Warning 51 | Gated clock check 52 | Net processor/registers/reg_op/reg_reg[0]_1[0] is a gated clock net sourced by a combinational pin processor/registers/reg_op/mul_temp_reg[15]_i_1/O, cell processor/registers/reg_op/mul_temp_reg[15]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. 53 | Related violations: 54 | 55 | PDRC-153#2 Warning 56 | Gated clock check 57 | Net processor/registers/reg_op/reg_reg[3]_4 is a gated clock net sourced by a combinational pin processor/registers/reg_op/logical_bool_reg_i_2/O, cell processor/registers/reg_op/logical_bool_reg_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. 58 | Related violations: 59 | 60 | PDRC-153#3 Warning 61 | Gated clock check 62 | Net processor/registers/reg_op/reg_reg[3]_5[0] is a gated clock net sourced by a combinational pin processor/registers/reg_op/temp_reg[7]_i_2/O, cell processor/registers/reg_op/temp_reg[7]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. 63 | Related violations: 64 | 65 | 66 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_methodology_drc_routed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/Computer_methodology_drc_routed.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_opt.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/Computer_opt.dcp -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_physopt.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/Computer_physopt.dcp -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_placed.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/Computer_placed.dcp -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_power_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 2 | ---------------------------------------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 4 | | Date : Sun Jan 10 14:14:29 2021 5 | | Host : kent-ThinkPad-T580 running 64-bit Ubuntu 20.04.1 LTS 6 | | Command : report_power -file Computer_power_routed.rpt -pb Computer_power_summary_routed.pb -rpx Computer_power_routed.rpx 7 | | Design : Computer 8 | | Device : xc7a35tcpg236-1 9 | | Design State : routed 10 | | Grade : commercial 11 | | Process : typical 12 | | Characterization : Production 13 | ---------------------------------------------------------------------------------------------------------------------------------------------- 14 | 15 | Power Report 16 | 17 | Table of Contents 18 | ----------------- 19 | 1. Summary 20 | 1.1 On-Chip Components 21 | 1.2 Power Supply Summary 22 | 1.3 Confidence Level 23 | 2. Settings 24 | 2.1 Environment 25 | 2.2 Clock Constraints 26 | 3. Detailed Reports 27 | 3.1 By Hierarchy 28 | 29 | 1. Summary 30 | ---------- 31 | 32 | +--------------------------+--------------+ 33 | | Total On-Chip Power (W) | 0.075 | 34 | | Design Power Budget (W) | Unspecified* | 35 | | Power Budget Margin (W) | NA | 36 | | Dynamic (W) | 0.004 | 37 | | Device Static (W) | 0.072 | 38 | | Effective TJA (C/W) | 5.0 | 39 | | Max Ambient (C) | 84.6 | 40 | | Junction Temperature (C) | 25.4 | 41 | | Confidence Level | Low | 42 | | Setting File | --- | 43 | | Simulation Activity File | --- | 44 | | Design Nets Matched | NA | 45 | +--------------------------+--------------+ 46 | * Specify Design Power Budget using, set_operating_conditions -design_power_budget 47 | 48 | 49 | 1.1 On-Chip Components 50 | ---------------------- 51 | 52 | +--------------------------+-----------+----------+-----------+-----------------+ 53 | | On-Chip | Power (W) | Used | Available | Utilization (%) | 54 | +--------------------------+-----------+----------+-----------+-----------------+ 55 | | Clocks | <0.001 | 3 | --- | --- | 56 | | Slice Logic | <0.001 | 802 | --- | --- | 57 | | LUT as Logic | <0.001 | 422 | 20800 | 2.03 | 58 | | CARRY4 | <0.001 | 37 | 8150 | 0.45 | 59 | | Register | <0.001 | 188 | 41600 | 0.45 | 60 | | LUT as Distributed RAM | <0.001 | 16 | 9600 | 0.17 | 61 | | F7/F8 Muxes | <0.001 | 16 | 32600 | 0.05 | 62 | | BUFG | <0.001 | 1 | 32 | 3.13 | 63 | | Others | 0.000 | 13 | --- | --- | 64 | | Signals | <0.001 | 687 | --- | --- | 65 | | I/O | 0.001 | 25 | 106 | 23.58 | 66 | | Static Power | 0.072 | | | | 67 | | Total | 0.075 | | | | 68 | +--------------------------+-----------+----------+-----------+-----------------+ 69 | 70 | 71 | 1.2 Power Supply Summary 72 | ------------------------ 73 | 74 | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ 75 | | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | 76 | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ 77 | | Vccint | 1.000 | 0.012 | 0.002 | 0.010 | NA | Unspecified | NA | 78 | | Vccaux | 1.800 | 0.013 | 0.000 | 0.013 | NA | Unspecified | NA | 79 | | Vcco33 | 3.300 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA | 80 | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 81 | | Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 82 | | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 83 | | Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 84 | | Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 85 | | Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 86 | | Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 87 | | MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 88 | | MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 89 | | Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | 90 | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ 91 | 92 | 93 | 1.3 Confidence Level 94 | -------------------- 95 | 96 | +-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ 97 | | User Input Data | Confidence | Details | Action | 98 | +-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ 99 | | Design implementation state | High | Design is routed | | 100 | | Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | 101 | | I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | 102 | | Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | 103 | | Device models | High | Device models are Production | | 104 | | | | | | 105 | | Overall confidence level | Low | | | 106 | +-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ 107 | 108 | 109 | 2. Settings 110 | ----------- 111 | 112 | 2.1 Environment 113 | --------------- 114 | 115 | +-----------------------+--------------------------+ 116 | | Ambient Temp (C) | 25.0 | 117 | | ThetaJA (C/W) | 5.0 | 118 | | Airflow (LFM) | 250 | 119 | | Heat Sink | medium (Medium Profile) | 120 | | ThetaSA (C/W) | 4.6 | 121 | | Board Selection | medium (10"x10") | 122 | | # of Board Layers | 12to15 (12 to 15 Layers) | 123 | | Board Temperature (C) | 25.0 | 124 | +-----------------------+--------------------------+ 125 | 126 | 127 | 2.2 Clock Constraints 128 | --------------------- 129 | 130 | +-------------+--------+-----------------+ 131 | | Clock | Domain | Constraint (ns) | 132 | +-------------+--------+-----------------+ 133 | | sys_clk_pin | clk | 10.0 | 134 | +-------------+--------+-----------------+ 135 | 136 | 137 | 3. Detailed Reports 138 | ------------------- 139 | 140 | 3.1 By Hierarchy 141 | ---------------- 142 | 143 | +-------------+-----------+ 144 | | Name | Power (W) | 145 | +-------------+-----------+ 146 | | Computer | 0.004 | 147 | | processor | 0.001 | 148 | +-------------+-----------+ 149 | 150 | 151 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_power_summary_routed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/Computer_power_summary_routed.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_route_status.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/Computer_route_status.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_route_status.rpt: -------------------------------------------------------------------------------- 1 | Design Route Status 2 | : # nets : 3 | ------------------------------------------- : ----------- : 4 | # of logical nets.......................... : 938 : 5 | # of nets not needing routing.......... : 247 : 6 | # of internally routed nets........ : 247 : 7 | # of routable nets..................... : 691 : 8 | # of fully routed nets............. : 691 : 9 | # of nets with routing errors.......... : 0 : 10 | ------------------------------------------- : ----------- : 11 | 12 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_routed.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/Computer_routed.dcp -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_timing_summary_routed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/Computer_timing_summary_routed.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/Computer_utilization_placed.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/Computer_utilization_placed.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/gen_run.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 194 | 195 | 196 | 197 | 198 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/htr.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado(TM) 3 | # htr.txt: a Vivado-generated description of how-to-repeat the 4 | # the basic steps of a run. Note that runme.bat/sh needs 5 | # to be invoked for Vivado to track run status. 6 | # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | vivado -log Computer.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Computer.tcl -notrace 10 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/init_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/init_design.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/opt_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/opt_design.pb -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/route_design.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Sun Jan 10 14:13:44 2021 6 | # Process ID: 63345 7 | # Current directory: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.runs/impl_1 8 | # Command line: vivado -log Computer.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Computer.tcl -notrace 9 | # Log file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.runs/impl_1/Computer.vdi 10 | # Journal file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.runs/impl_1/vivado.jou 11 | #----------------------------------------------------------- 12 | source Computer.tcl -notrace 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/vivado.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/vivado_57835.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Sun Jan 10 14:10:12 2021 6 | # Process ID: 57835 7 | # Current directory: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.runs/impl_1 8 | # Command line: vivado -log Computer.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Computer.tcl -notrace 9 | # Log file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.runs/impl_1/Computer.vdi 10 | # Journal file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.runs/impl_1/vivado.jou 11 | #----------------------------------------------------------- 12 | source Computer.tcl -notrace 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/impl_1/write_bitstream.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/impl_1/write_bitstream.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/synth_1/.Xil/Computer_propImpl.xdc: -------------------------------------------------------------------------------- 1 | set_property SRC_FILE_INFO {cfile:/home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/constrs_1/new/computer_xdc.xdc rfile:../../../Computer8Bit.srcs/constrs_1/new/computer_xdc.xdc id:1} [current_design] 2 | set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] 3 | set_property PACKAGE_PIN W5 [get_ports clk] 4 | set_property src_info {type:XDC file:1 line:82 export:INPUT save:INPUT read:READ} [current_design] 5 | set_property PACKAGE_PIN W7 [get_ports {seg[0]}] 6 | set_property src_info {type:XDC file:1 line:84 export:INPUT save:INPUT read:READ} [current_design] 7 | set_property PACKAGE_PIN W6 [get_ports {seg[1]}] 8 | set_property src_info {type:XDC file:1 line:86 export:INPUT save:INPUT read:READ} [current_design] 9 | set_property PACKAGE_PIN U8 [get_ports {seg[2]}] 10 | set_property src_info {type:XDC file:1 line:88 export:INPUT save:INPUT read:READ} [current_design] 11 | set_property PACKAGE_PIN V8 [get_ports {seg[3]}] 12 | set_property src_info {type:XDC file:1 line:90 export:INPUT save:INPUT read:READ} [current_design] 13 | set_property PACKAGE_PIN U5 [get_ports {seg[4]}] 14 | set_property src_info {type:XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design] 15 | set_property PACKAGE_PIN V5 [get_ports {seg[5]}] 16 | set_property src_info {type:XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design] 17 | set_property PACKAGE_PIN U7 [get_ports {seg[6]}] 18 | set_property src_info {type:XDC file:1 line:97 export:INPUT save:INPUT read:READ} [current_design] 19 | set_property PACKAGE_PIN V7 [get_ports {seg[7]}] 20 | set_property src_info {type:XDC file:1 line:100 export:INPUT save:INPUT read:READ} [current_design] 21 | set_property PACKAGE_PIN U2 [get_ports {an[0]}] 22 | set_property src_info {type:XDC file:1 line:102 export:INPUT save:INPUT read:READ} [current_design] 23 | set_property PACKAGE_PIN U4 [get_ports {an[1]}] 24 | set_property src_info {type:XDC file:1 line:104 export:INPUT save:INPUT read:READ} [current_design] 25 | set_property PACKAGE_PIN V4 [get_ports {an[2]}] 26 | set_property src_info {type:XDC file:1 line:106 export:INPUT save:INPUT read:READ} [current_design] 27 | set_property PACKAGE_PIN W4 [get_ports {an[3]}] 28 | set_property src_info {type:XDC file:1 line:111 export:INPUT save:INPUT read:READ} [current_design] 29 | set_property PACKAGE_PIN U18 [get_ports rst] 30 | set_property src_info {type:XDC file:1 line:154 export:INPUT save:INPUT read:READ} [current_design] 31 | set_property PACKAGE_PIN A14 [get_ports {JB[0]}] 32 | set_property src_info {type:XDC file:1 line:157 export:INPUT save:INPUT read:READ} [current_design] 33 | set_property PACKAGE_PIN A16 [get_ports {JB[1]}] 34 | set_property src_info {type:XDC file:1 line:160 export:INPUT save:INPUT read:READ} [current_design] 35 | set_property PACKAGE_PIN B15 [get_ports {JB[2]}] 36 | set_property src_info {type:XDC file:1 line:163 export:INPUT save:INPUT read:READ} [current_design] 37 | set_property PACKAGE_PIN B16 [get_ports {JB[3]}] 38 | set_property src_info {type:XDC file:1 line:166 export:INPUT save:INPUT read:READ} [current_design] 39 | set_property PACKAGE_PIN A15 [get_ports {JB[4]}] 40 | set_property src_info {type:XDC file:1 line:169 export:INPUT save:INPUT read:READ} [current_design] 41 | set_property PACKAGE_PIN A17 [get_ports {JB[5]}] 42 | set_property src_info {type:XDC file:1 line:172 export:INPUT save:INPUT read:READ} [current_design] 43 | set_property PACKAGE_PIN C15 [get_ports {JB[6]}] 44 | set_property src_info {type:XDC file:1 line:175 export:INPUT save:INPUT read:READ} [current_design] 45 | set_property PACKAGE_PIN C16 [get_ports {JB[7]}] 46 | set_property src_info {type:XDC file:1 line:182 export:INPUT save:INPUT read:READ} [current_design] 47 | set_property PACKAGE_PIN K17 [get_ports lcd_rs] 48 | set_property src_info {type:XDC file:1 line:185 export:INPUT save:INPUT read:READ} [current_design] 49 | set_property PACKAGE_PIN M18 [get_ports lcd_rw] 50 | set_property src_info {type:XDC file:1 line:188 export:INPUT save:INPUT read:READ} [current_design] 51 | set_property PACKAGE_PIN N17 [get_ports lcd_en] 52 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/synth_1/Computer.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/synth_1/Computer.dcp -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/synth_1/Computer.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Synthesis run script generated by Vivado 3 | # 4 | 5 | set TIME_start [clock seconds] 6 | namespace eval ::optrace { 7 | variable script "/home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.runs/synth_1/Computer.tcl" 8 | variable category "vivado_synth" 9 | } 10 | 11 | # Try to connect to running dispatch if we haven't done so already. 12 | # This code assumes that the Tcl interpreter is not using threads, 13 | # since the ::dispatch::connected variable isn't mutex protected. 14 | if {![info exists ::dispatch::connected]} { 15 | namespace eval ::dispatch { 16 | variable connected false 17 | if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { 18 | set result "true" 19 | if {[catch { 20 | if {[lsearch -exact [package names] DispatchTcl] < 0} { 21 | set result [load librdi_cd_clienttcl[info sharedlibextension]] 22 | } 23 | if {$result eq "false"} { 24 | puts "WARNING: Could not load dispatch client library" 25 | } 26 | set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] 27 | if { $connect_id eq "" } { 28 | puts "WARNING: Could not initialize dispatch client" 29 | } else { 30 | puts "INFO: Dispatch client connection id - $connect_id" 31 | set connected true 32 | } 33 | } catch_res]} { 34 | puts "WARNING: failed to connect to dispatch server - $catch_res" 35 | } 36 | } 37 | } 38 | } 39 | if {$::dispatch::connected} { 40 | # Remove the dummy proc if it exists. 41 | if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { 42 | rename ::OPTRACE "" 43 | } 44 | proc ::OPTRACE { task action {tags {} } } { 45 | ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category 46 | } 47 | # dispatch is generic. We specifically want to attach logging. 48 | ::vitis_log::connect_client 49 | } else { 50 | # Add dummy proc if it doesn't exist. 51 | if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { 52 | proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { 53 | # Do nothing 54 | } 55 | } 56 | } 57 | 58 | proc create_report { reportName command } { 59 | set status "." 60 | append status $reportName ".fail" 61 | if { [file exists $status] } { 62 | eval file delete [glob $status] 63 | } 64 | send_msg_id runtcl-4 info "Executing : $command" 65 | set retval [eval catch { $command } msg] 66 | if { $retval != 0 } { 67 | set fp [open $status w] 68 | close $fp 69 | send_msg_id runtcl-5 warning "$msg" 70 | } 71 | } 72 | OPTRACE "synth_1" START { ROLLUP_AUTO } 73 | set_param chipscope.maxJobs 2 74 | set_param xicom.use_bs_reader 1 75 | set_param synth.incrementalSynthesisCache ./.Xil/Vivado-13915-kent-ThinkPad-T580/incrSyn 76 | set_msg_config -id {Synth 8-256} -limit 10000 77 | set_msg_config -id {Synth 8-638} -limit 10000 78 | OPTRACE "Creating in-memory project" START { } 79 | create_project -in_memory -part xc7a35tcpg236-1 80 | 81 | set_param project.singleFileAddWarning.threshold 0 82 | set_param project.compositeFile.enableAutoGeneration 0 83 | set_param synth.vivado.isSynthRun true 84 | set_property webtalk.parent_dir /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.cache/wt [current_project] 85 | set_property parent.project_path /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.xpr [current_project] 86 | set_property default_lib xil_defaultlib [current_project] 87 | set_property target_language VHDL [current_project] 88 | set_property board_part digilentinc.com:basys3:part0:1.1 [current_project] 89 | set_property ip_output_repo /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.cache/ip [current_project] 90 | set_property ip_cache_permissions {read write} [current_project] 91 | OPTRACE "Creating in-memory project" END { } 92 | OPTRACE "Adding files" START { } 93 | read_vhdl -library xil_defaultlib { 94 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/ALU.vhd 95 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/CPU.vhd 96 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/ControlUnit.vhd 97 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/HexToSseg.vhd 98 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/IndexRegister.vhd 99 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/ModMCounter.vhd 100 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/PIPORegister.vhd 101 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/ProgramCounter.vhd 102 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/RAM.vhd 103 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/ROM.vhd 104 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/RegisterBank.vhd 105 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/SixteenBitDisplay.vhd 106 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/SixteenToFourMux.vhd 107 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/StackPointer.vhd 108 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/Computer.vhd 109 | /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/sources_1/new/IO.vhd 110 | } 111 | OPTRACE "Adding files" END { } 112 | # Mark all dcp files as not used in implementation to prevent them from being 113 | # stitched into the results of this synthesis run. Any black boxes in the 114 | # design are intentionally left as such for best results. Dcp files will be 115 | # stitched into the design at a later time, either when this synthesis run is 116 | # opened, or when it is stitched into a dependent implementation run. 117 | foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { 118 | set_property used_in_implementation false $dcp 119 | } 120 | read_xdc /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/constrs_1/new/computer_xdc.xdc 121 | set_property used_in_implementation false [get_files /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.srcs/constrs_1/new/computer_xdc.xdc] 122 | 123 | set_param ips.enableIPCacheLiteLoad 1 124 | close [open __synthesis_is_running__ w] 125 | 126 | OPTRACE "synth_design" START { } 127 | synth_design -top Computer -part xc7a35tcpg236-1 128 | OPTRACE "synth_design" END { } 129 | if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { 130 | send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" 131 | } 132 | 133 | 134 | OPTRACE "write_checkpoint" START { CHECKPOINT } 135 | # disable binary constraint mode for synth run checkpoints 136 | set_param constraints.enableBinaryConstraints false 137 | write_checkpoint -force -noxdef Computer.dcp 138 | OPTRACE "write_checkpoint" END { } 139 | OPTRACE "synth reports" START { REPORT } 140 | create_report "synth_1_synth_report_utilization_0" "report_utilization -file Computer_utilization_synth.rpt -pb Computer_utilization_synth.pb" 141 | OPTRACE "synth reports" END { } 142 | file delete __synthesis_is_running__ 143 | close [open __synthesis_is_complete__ w] 144 | OPTRACE "synth_1" END { } 145 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/synth_1/Computer_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/synth_1/Computer_utilization_synth.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/synth_1/Computer_utilization_synth.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 2 | ----------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 4 | | Date : Sun Jan 10 14:13:40 2021 5 | | Host : kent-ThinkPad-T580 running 64-bit Ubuntu 20.04.1 LTS 6 | | Command : report_utilization -file Computer_utilization_synth.rpt -pb Computer_utilization_synth.pb 7 | | Design : Computer 8 | | Device : 7a35tcpg236-1 9 | | Design State : Synthesized 10 | ----------------------------------------------------------------------------------------------------------- 11 | 12 | Utilization Design Information 13 | 14 | Table of Contents 15 | ----------------- 16 | 1. Slice Logic 17 | 1.1 Summary of Registers by Type 18 | 2. Memory 19 | 3. DSP 20 | 4. IO and GT Specific 21 | 5. Clocking 22 | 6. Specific Feature 23 | 7. Primitives 24 | 8. Black Boxes 25 | 9. Instantiated Netlists 26 | 27 | 1. Slice Logic 28 | -------------- 29 | 30 | +----------------------------+------+-------+-----------+-------+ 31 | | Site Type | Used | Fixed | Available | Util% | 32 | +----------------------------+------+-------+-----------+-------+ 33 | | Slice LUTs* | 462 | 0 | 20800 | 2.22 | 34 | | LUT as Logic | 446 | 0 | 20800 | 2.14 | 35 | | LUT as Memory | 16 | 0 | 9600 | 0.17 | 36 | | LUT as Distributed RAM | 16 | 0 | | | 37 | | LUT as Shift Register | 0 | 0 | | | 38 | | Slice Registers | 196 | 0 | 41600 | 0.47 | 39 | | Register as Flip Flop | 171 | 0 | 41600 | 0.41 | 40 | | Register as Latch | 25 | 0 | 41600 | 0.06 | 41 | | F7 Muxes | 16 | 0 | 16300 | 0.10 | 42 | | F8 Muxes | 0 | 0 | 8150 | 0.00 | 43 | +----------------------------+------+-------+-----------+-------+ 44 | * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. 45 | 46 | 47 | 1.1 Summary of Registers by Type 48 | -------------------------------- 49 | 50 | +-------+--------------+-------------+--------------+ 51 | | Total | Clock Enable | Synchronous | Asynchronous | 52 | +-------+--------------+-------------+--------------+ 53 | | 0 | _ | - | - | 54 | | 0 | _ | - | Set | 55 | | 0 | _ | - | Reset | 56 | | 0 | _ | Set | - | 57 | | 0 | _ | Reset | - | 58 | | 0 | Yes | - | - | 59 | | 1 | Yes | - | Set | 60 | | 178 | Yes | - | Reset | 61 | | 0 | Yes | Set | - | 62 | | 17 | Yes | Reset | - | 63 | +-------+--------------+-------------+--------------+ 64 | 65 | 66 | 2. Memory 67 | --------- 68 | 69 | +----------------+------+-------+-----------+-------+ 70 | | Site Type | Used | Fixed | Available | Util% | 71 | +----------------+------+-------+-----------+-------+ 72 | | Block RAM Tile | 0 | 0 | 50 | 0.00 | 73 | | RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | 74 | | RAMB18 | 0 | 0 | 100 | 0.00 | 75 | +----------------+------+-------+-----------+-------+ 76 | * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 77 | 78 | 79 | 3. DSP 80 | ------ 81 | 82 | +-----------+------+-------+-----------+-------+ 83 | | Site Type | Used | Fixed | Available | Util% | 84 | +-----------+------+-------+-----------+-------+ 85 | | DSPs | 0 | 0 | 90 | 0.00 | 86 | +-----------+------+-------+-----------+-------+ 87 | 88 | 89 | 4. IO and GT Specific 90 | --------------------- 91 | 92 | +-----------------------------+------+-------+-----------+-------+ 93 | | Site Type | Used | Fixed | Available | Util% | 94 | +-----------------------------+------+-------+-----------+-------+ 95 | | Bonded IOB | 25 | 0 | 106 | 23.58 | 96 | | Bonded IPADs | 0 | 0 | 10 | 0.00 | 97 | | Bonded OPADs | 0 | 0 | 4 | 0.00 | 98 | | PHY_CONTROL | 0 | 0 | 5 | 0.00 | 99 | | PHASER_REF | 0 | 0 | 5 | 0.00 | 100 | | OUT_FIFO | 0 | 0 | 20 | 0.00 | 101 | | IN_FIFO | 0 | 0 | 20 | 0.00 | 102 | | IDELAYCTRL | 0 | 0 | 5 | 0.00 | 103 | | IBUFDS | 0 | 0 | 104 | 0.00 | 104 | | GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | 105 | | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | 106 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | 107 | | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | 108 | | IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | 109 | | ILOGIC | 0 | 0 | 106 | 0.00 | 110 | | OLOGIC | 0 | 0 | 106 | 0.00 | 111 | +-----------------------------+------+-------+-----------+-------+ 112 | 113 | 114 | 5. Clocking 115 | ----------- 116 | 117 | +------------+------+-------+-----------+-------+ 118 | | Site Type | Used | Fixed | Available | Util% | 119 | +------------+------+-------+-----------+-------+ 120 | | BUFGCTRL | 1 | 0 | 32 | 3.13 | 121 | | BUFIO | 0 | 0 | 20 | 0.00 | 122 | | MMCME2_ADV | 0 | 0 | 5 | 0.00 | 123 | | PLLE2_ADV | 0 | 0 | 5 | 0.00 | 124 | | BUFMRCE | 0 | 0 | 10 | 0.00 | 125 | | BUFHCE | 0 | 0 | 72 | 0.00 | 126 | | BUFR | 0 | 0 | 20 | 0.00 | 127 | +------------+------+-------+-----------+-------+ 128 | 129 | 130 | 6. Specific Feature 131 | ------------------- 132 | 133 | +-------------+------+-------+-----------+-------+ 134 | | Site Type | Used | Fixed | Available | Util% | 135 | +-------------+------+-------+-----------+-------+ 136 | | BSCANE2 | 0 | 0 | 4 | 0.00 | 137 | | CAPTUREE2 | 0 | 0 | 1 | 0.00 | 138 | | DNA_PORT | 0 | 0 | 1 | 0.00 | 139 | | EFUSE_USR | 0 | 0 | 1 | 0.00 | 140 | | FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | 141 | | ICAPE2 | 0 | 0 | 2 | 0.00 | 142 | | PCIE_2_1 | 0 | 0 | 1 | 0.00 | 143 | | STARTUPE2 | 0 | 0 | 1 | 0.00 | 144 | | XADC | 0 | 0 | 1 | 0.00 | 145 | +-------------+------+-------+-----------+-------+ 146 | 147 | 148 | 7. Primitives 149 | ------------- 150 | 151 | +----------+------+---------------------+ 152 | | Ref Name | Used | Functional Category | 153 | +----------+------+---------------------+ 154 | | LUT6 | 248 | LUT | 155 | | FDCE | 153 | Flop & Latch | 156 | | LUT4 | 103 | LUT | 157 | | LUT2 | 80 | LUT | 158 | | LUT5 | 64 | LUT | 159 | | LUT3 | 48 | LUT | 160 | | CARRY4 | 37 | CarryLogic | 161 | | LDCE | 25 | Flop & Latch | 162 | | OBUF | 23 | IO | 163 | | FDRE | 17 | Flop & Latch | 164 | | RAMS64E | 16 | Distributed Memory | 165 | | MUXF7 | 16 | MuxFx | 166 | | LUT1 | 5 | LUT | 167 | | IBUF | 2 | IO | 168 | | FDPE | 1 | Flop & Latch | 169 | | BUFG | 1 | Clock | 170 | +----------+------+---------------------+ 171 | 172 | 173 | 8. Black Boxes 174 | -------------- 175 | 176 | +----------+------+ 177 | | Ref Name | Used | 178 | +----------+------+ 179 | 180 | 181 | 9. Instantiated Netlists 182 | ------------------------ 183 | 184 | +----------+------+ 185 | | Ref Name | Used | 186 | +----------+------+ 187 | 188 | 189 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/synth_1/gen_run.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 128 | 129 | 130 | 131 | 132 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado(TM) 3 | # htr.txt: a Vivado-generated description of how-to-repeat the 4 | # the basic steps of a run. Note that runme.bat/sh needs 5 | # to be invoked for Vivado to track run status. 6 | # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | vivado -log Computer.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Computer.tcl 10 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Sun Jan 10 14:12:58 2021 6 | # Process ID: 63171 7 | # Current directory: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.runs/synth_1 8 | # Command line: vivado -log Computer.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Computer.tcl 9 | # Log file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.runs/synth_1/Computer.vds 10 | # Journal file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.runs/synth_1/vivado.jou 11 | #----------------------------------------------------------- 12 | source Computer.tcl -notrace 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.runs/synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.runs/synth_1/vivado.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/Computer_tb.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/Computer_tb_vhdl.prj: -------------------------------------------------------------------------------- 1 | # compile vhdl design source files 2 | vhdl xil_defaultlib \ 3 | "../../../../Computer8Bit.srcs/sources_1/new/ALU.vhd" \ 4 | "../../../../Computer8Bit.srcs/sources_1/new/CPU.vhd" \ 5 | "../../../../Computer8Bit.srcs/sources_1/new/ControlUnit.vhd" \ 6 | "../../../../Computer8Bit.srcs/sources_1/new/HexToSseg.vhd" \ 7 | "../../../../Computer8Bit.srcs/sources_1/new/IndexRegister.vhd" \ 8 | "../../../../Computer8Bit.srcs/sources_1/new/ModMCounter.vhd" \ 9 | "../../../../Computer8Bit.srcs/sources_1/new/PIPORegister.vhd" \ 10 | "../../../../Computer8Bit.srcs/sources_1/new/ProgramCounter.vhd" \ 11 | "../../../../Computer8Bit.srcs/sources_1/new/RAM.vhd" \ 12 | "../../../../Computer8Bit.srcs/sources_1/new/ROM.vhd" \ 13 | "../../../../Computer8Bit.srcs/sources_1/new/RegisterBank.vhd" \ 14 | "../../../../Computer8Bit.srcs/sources_1/new/SixteenBitDisplay.vhd" \ 15 | "../../../../Computer8Bit.srcs/sources_1/new/SixteenToFourMux.vhd" \ 16 | "../../../../Computer8Bit.srcs/sources_1/new/StackPointer.vhd" \ 17 | "../../../../Computer8Bit.srcs/sources_1/new/Computer.vhd" \ 18 | "../../../../Computer8Bit.srcs/sources_1/new/IO.vhd" \ 19 | "../../../../Computer8Bit.srcs/sim_1/new/Computer_tb.vhd" \ 20 | "../../../../Computer8Bit.srcs/sim_1/new/Register_tb.vhd" \ 21 | 22 | # Do not sort compile order 23 | nosort 24 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/Register_tb.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/Register_tb_vhdl.prj: -------------------------------------------------------------------------------- 1 | # compile vhdl design source files 2 | vhdl xil_defaultlib \ 3 | "../../../../Computer8Bit.srcs/sources_1/new/PIPORegister.vhd" \ 4 | "../../../../Computer8Bit.srcs/sim_1/new/Register_tb.vhd" \ 5 | 6 | # Do not sort compile order 7 | nosort 8 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Sun Jan 10 13:11:47 2021 6 | # Process ID: 27851 7 | # Current directory: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim 8 | # Command line: wbtcv -mode batch -source /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.jou 11 | #----------------------------------------------------------- 12 | source /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk_12826.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Sat Jan 9 13:03:23 2021 6 | # Process ID: 12826 7 | # Current directory: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim 8 | # Command line: wbtcv -mode batch -source /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.jou 11 | #----------------------------------------------------------- 12 | source /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk_13209.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Sat Jan 9 13:04:07 2021 6 | # Process ID: 13209 7 | # Current directory: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim 8 | # Command line: wbtcv -mode batch -source /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.jou 11 | #----------------------------------------------------------- 12 | source /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk_1750373.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Thu Jan 7 08:56:18 2021 6 | # Process ID: 1750373 7 | # Current directory: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim 8 | # Command line: wbtcv -mode batch -source /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.jou 11 | #----------------------------------------------------------- 12 | source /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk_1751994.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Thu Jan 7 09:08:53 2021 6 | # Process ID: 1751994 7 | # Current directory: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim 8 | # Command line: wbtcv -mode batch -source /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.jou 11 | #----------------------------------------------------------- 12 | source /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk_26033.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Sun Jan 10 13:07:21 2021 6 | # Process ID: 26033 7 | # Current directory: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim 8 | # Command line: wbtcv -mode batch -source /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/webtalk.jou 11 | #----------------------------------------------------------- 12 | source /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "093bea831d884684b7367d1f133b0d45" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "Computer_tb_behav" "xil_defaultlib.Computer_tb" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/obj/xsim_1.c: -------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /**********************************************************************/ 12 | 13 | #if defined(_WIN32) 14 | #include "stdio.h" 15 | #define IKI_DLLESPEC __declspec(dllimport) 16 | #else 17 | #define IKI_DLLESPEC 18 | #endif 19 | #include "iki.h" 20 | #include 21 | #include 22 | #ifdef __GNUC__ 23 | #include 24 | #else 25 | #include 26 | #define alloca _alloca 27 | #endif 28 | /**********************************************************************/ 29 | /* ____ ____ */ 30 | /* / /\/ / */ 31 | /* /___/ \ / */ 32 | /* \ \ \/ */ 33 | /* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ 34 | /* / / All Right Reserved. */ 35 | /* /---/ /\ */ 36 | /* \ \ / \ */ 37 | /* \___\/\___\ */ 38 | /**********************************************************************/ 39 | 40 | #if defined(_WIN32) 41 | #include "stdio.h" 42 | #define IKI_DLLESPEC __declspec(dllimport) 43 | #else 44 | #define IKI_DLLESPEC 45 | #endif 46 | #include "iki.h" 47 | #include 48 | #include 49 | #ifdef __GNUC__ 50 | #include 51 | #else 52 | #include 53 | #define alloca _alloca 54 | #endif 55 | typedef void (*funcp)(char *, char *); 56 | extern int main(int, char**); 57 | IKI_DLLESPEC extern void execute_164(char*, char *); 58 | IKI_DLLESPEC extern void execute_165(char*, char *); 59 | IKI_DLLESPEC extern void execute_27(char*, char *); 60 | IKI_DLLESPEC extern void execute_28(char*, char *); 61 | IKI_DLLESPEC extern void execute_29(char*, char *); 62 | IKI_DLLESPEC extern void execute_30(char*, char *); 63 | IKI_DLLESPEC extern void execute_31(char*, char *); 64 | IKI_DLLESPEC extern void execute_32(char*, char *); 65 | IKI_DLLESPEC extern void execute_33(char*, char *); 66 | IKI_DLLESPEC extern void execute_34(char*, char *); 67 | IKI_DLLESPEC extern void execute_35(char*, char *); 68 | IKI_DLLESPEC extern void execute_36(char*, char *); 69 | IKI_DLLESPEC extern void execute_159(char*, char *); 70 | IKI_DLLESPEC extern void execute_68(char*, char *); 71 | IKI_DLLESPEC extern void execute_69(char*, char *); 72 | IKI_DLLESPEC extern void execute_71(char*, char *); 73 | IKI_DLLESPEC extern void execute_72(char*, char *); 74 | IKI_DLLESPEC extern void execute_73(char*, char *); 75 | IKI_DLLESPEC extern void execute_75(char*, char *); 76 | IKI_DLLESPEC extern void execute_76(char*, char *); 77 | IKI_DLLESPEC extern void execute_77(char*, char *); 78 | IKI_DLLESPEC extern void execute_79(char*, char *); 79 | IKI_DLLESPEC extern void execute_80(char*, char *); 80 | IKI_DLLESPEC extern void execute_81(char*, char *); 81 | IKI_DLLESPEC extern void execute_82(char*, char *); 82 | IKI_DLLESPEC extern void execute_116(char*, char *); 83 | IKI_DLLESPEC extern void execute_117(char*, char *); 84 | IKI_DLLESPEC extern void execute_118(char*, char *); 85 | IKI_DLLESPEC extern void execute_119(char*, char *); 86 | IKI_DLLESPEC extern void execute_120(char*, char *); 87 | IKI_DLLESPEC extern void execute_121(char*, char *); 88 | IKI_DLLESPEC extern void execute_122(char*, char *); 89 | IKI_DLLESPEC extern void execute_123(char*, char *); 90 | IKI_DLLESPEC extern void execute_124(char*, char *); 91 | IKI_DLLESPEC extern void execute_125(char*, char *); 92 | IKI_DLLESPEC extern void execute_126(char*, char *); 93 | IKI_DLLESPEC extern void execute_127(char*, char *); 94 | IKI_DLLESPEC extern void execute_128(char*, char *); 95 | IKI_DLLESPEC extern void execute_129(char*, char *); 96 | IKI_DLLESPEC extern void execute_85(char*, char *); 97 | IKI_DLLESPEC extern void execute_86(char*, char *); 98 | IKI_DLLESPEC extern void execute_87(char*, char *); 99 | IKI_DLLESPEC extern void execute_89(char*, char *); 100 | IKI_DLLESPEC extern void execute_90(char*, char *); 101 | IKI_DLLESPEC extern void execute_91(char*, char *); 102 | IKI_DLLESPEC extern void execute_93(char*, char *); 103 | IKI_DLLESPEC extern void execute_94(char*, char *); 104 | IKI_DLLESPEC extern void execute_95(char*, char *); 105 | IKI_DLLESPEC extern void execute_133(char*, char *); 106 | IKI_DLLESPEC extern void execute_134(char*, char *); 107 | IKI_DLLESPEC extern void execute_135(char*, char *); 108 | IKI_DLLESPEC extern void execute_136(char*, char *); 109 | IKI_DLLESPEC extern void execute_137(char*, char *); 110 | IKI_DLLESPEC extern void execute_138(char*, char *); 111 | IKI_DLLESPEC extern void execute_142(char*, char *); 112 | IKI_DLLESPEC extern void execute_144(char*, char *); 113 | IKI_DLLESPEC extern void execute_145(char*, char *); 114 | IKI_DLLESPEC extern void execute_147(char*, char *); 115 | IKI_DLLESPEC extern void execute_148(char*, char *); 116 | IKI_DLLESPEC extern void execute_150(char*, char *); 117 | IKI_DLLESPEC extern void execute_152(char*, char *); 118 | IKI_DLLESPEC extern void execute_153(char*, char *); 119 | IKI_DLLESPEC extern void execute_155(char*, char *); 120 | IKI_DLLESPEC extern void execute_156(char*, char *); 121 | IKI_DLLESPEC extern void execute_157(char*, char *); 122 | IKI_DLLESPEC extern void execute_158(char*, char *); 123 | IKI_DLLESPEC extern void execute_161(char*, char *); 124 | IKI_DLLESPEC extern void execute_162(char*, char *); 125 | IKI_DLLESPEC extern void execute_163(char*, char *); 126 | IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); 127 | IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); 128 | IKI_DLLESPEC extern void transaction_19(char*, char*, unsigned, unsigned, unsigned); 129 | funcp funcTab[72] = {(funcp)execute_164, (funcp)execute_165, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_159, (funcp)execute_68, (funcp)execute_69, (funcp)execute_71, (funcp)execute_72, (funcp)execute_73, (funcp)execute_75, (funcp)execute_76, (funcp)execute_77, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_116, (funcp)execute_117, (funcp)execute_118, (funcp)execute_119, (funcp)execute_120, (funcp)execute_121, (funcp)execute_122, (funcp)execute_123, (funcp)execute_124, (funcp)execute_125, (funcp)execute_126, (funcp)execute_127, (funcp)execute_128, (funcp)execute_129, (funcp)execute_85, (funcp)execute_86, (funcp)execute_87, (funcp)execute_89, (funcp)execute_90, (funcp)execute_91, (funcp)execute_93, (funcp)execute_94, (funcp)execute_95, (funcp)execute_133, (funcp)execute_134, (funcp)execute_135, (funcp)execute_136, (funcp)execute_137, (funcp)execute_138, (funcp)execute_142, (funcp)execute_144, (funcp)execute_145, (funcp)execute_147, (funcp)execute_148, (funcp)execute_150, (funcp)execute_152, (funcp)execute_153, (funcp)execute_155, (funcp)execute_156, (funcp)execute_157, (funcp)execute_158, (funcp)execute_161, (funcp)execute_162, (funcp)execute_163, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_19}; 130 | const int NumRelocateId= 72; 131 | 132 | void relocate(char *dp) 133 | { 134 | iki_relocate(dp, "xsim.dir/Computer_tb_behav/xsim.reloc", (void **)funcTab, 72); 135 | iki_vhdl_file_variable_register(dp + 28288); 136 | iki_vhdl_file_variable_register(dp + 28344); 137 | 138 | 139 | /*Populate the transaction function pointer field in the whole net structure */ 140 | } 141 | 142 | void sensitize(char *dp) 143 | { 144 | iki_sensitize(dp, "xsim.dir/Computer_tb_behav/xsim.reloc"); 145 | } 146 | 147 | void simulate(char *dp) 148 | { 149 | iki_schedule_processes_at_time_zero(dp, "xsim.dir/Computer_tb_behav/xsim.reloc"); 150 | // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net 151 | iki_execute_processes(); 152 | 153 | // Schedule resolution functions for the multiply driven Verilog nets that have strength 154 | // Schedule transaction functions for the singly driven Verilog nets that have strength 155 | 156 | } 157 | #include "iki_bridge.h" 158 | void relocate(char *); 159 | 160 | void sensitize(char *); 161 | 162 | void simulate(char *); 163 | 164 | extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); 165 | extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; 166 | extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; 167 | 168 | int main(int argc, char **argv) 169 | { 170 | iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; 171 | iki_set_sv_type_file_path_name("xsim.dir/Computer_tb_behav/xsim.svtype"); 172 | iki_set_crvs_dump_file_path_name("xsim.dir/Computer_tb_behav/xsim.crvsdump"); 173 | void* design_handle = iki_create_design("xsim.dir/Computer_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); 174 | iki_set_rc_trial_count(100); 175 | (void) design_handle; 176 | return iki_simulate_design(); 177 | } 178 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/usage_statistics_ext_xsim.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 |
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54 | 55 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/xsim_webtalk.tcl: -------------------------------------------------------------------------------- 1 | webtalk_init -webtalk_dir /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/ 2 | webtalk_register_client -client project 3 | webtalk_add_data -client project -key date_generated -value "Sun Jan 10 14:20:33 2021" -context "software_version_and_target_device" 4 | webtalk_add_data -client project -key product_version -value "XSIM v2020.2 (64-bit)" -context "software_version_and_target_device" 5 | webtalk_add_data -client project -key build_version -value "3064766" -context "software_version_and_target_device" 6 | webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" 7 | webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" 8 | webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" 9 | webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" 10 | webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" 11 | webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" 12 | webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" 13 | webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" 14 | webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" 15 | webtalk_add_data -client project -key random_id -value "c504ae24-7c68-4174-ac1a-c3bf683363a6" -context "software_version_and_target_device" 16 | webtalk_add_data -client project -key project_id -value "093bea831d884684b7367d1f133b0d45" -context "software_version_and_target_device" 17 | webtalk_add_data -client project -key project_iteration -value "295" -context "software_version_and_target_device" 18 | webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" 19 | webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.1 LTS" -context "user_environment" 20 | webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-8250U CPU @ 1.60GHz" -context "user_environment" 21 | webtalk_add_data -client project -key cpu_speed -value "3086.953 MHz" -context "user_environment" 22 | webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" 23 | webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" 24 | webtalk_register_client -client xsim 25 | webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" 26 | webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" 27 | webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" 28 | webtalk_add_data -client xsim -key iteration -value "10" -context "xsim\\usage" 29 | webtalk_add_data -client xsim -key Simulation_Time -value "0.85_sec" -context "xsim\\usage" 30 | webtalk_add_data -client xsim -key Simulation_Memory -value "123628_KB" -context "xsim\\usage" 31 | webtalk_transmit -clientid 1930767920 -regid "" -xml /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/kent/source/vhdl/Computer8Bit/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" 32 | webtalk_terminate 33 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/xsim.mem: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Computer_tb_behav/xsim.mem -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Register_tb_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "093bea831d884684b7367d1f133b0d45" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "Register_tb_behav" "xil_defaultlib.Register_tb" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Register_tb_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Register_tb_behav/obj/xsim_1.c: -------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /**********************************************************************/ 12 | 13 | #if defined(_WIN32) 14 | #include "stdio.h" 15 | #define IKI_DLLESPEC __declspec(dllimport) 16 | #else 17 | #define IKI_DLLESPEC 18 | #endif 19 | #include "iki.h" 20 | #include 21 | #include 22 | #ifdef __GNUC__ 23 | #include 24 | #else 25 | #include 26 | #define alloca _alloca 27 | #endif 28 | /**********************************************************************/ 29 | /* ____ ____ */ 30 | /* / /\/ / */ 31 | /* /___/ \ / */ 32 | /* \ \ \/ */ 33 | /* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ 34 | /* / / All Right Reserved. */ 35 | /* /---/ /\ */ 36 | /* \ \ / \ */ 37 | /* \___\/\___\ */ 38 | /**********************************************************************/ 39 | 40 | #if defined(_WIN32) 41 | #include "stdio.h" 42 | #define IKI_DLLESPEC __declspec(dllimport) 43 | #else 44 | #define IKI_DLLESPEC 45 | #endif 46 | #include "iki.h" 47 | #include 48 | #include 49 | #ifdef __GNUC__ 50 | #include 51 | #else 52 | #include 53 | #define alloca _alloca 54 | #endif 55 | typedef void (*funcp)(char *, char *); 56 | extern int main(int, char**); 57 | IKI_DLLESPEC extern void execute_12(char*, char *); 58 | IKI_DLLESPEC extern void execute_13(char*, char *); 59 | IKI_DLLESPEC extern void execute_9(char*, char *); 60 | IKI_DLLESPEC extern void execute_10(char*, char *); 61 | IKI_DLLESPEC extern void execute_11(char*, char *); 62 | IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); 63 | IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); 64 | funcp funcTab[7] = {(funcp)execute_12, (funcp)execute_13, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; 65 | const int NumRelocateId= 7; 66 | 67 | void relocate(char *dp) 68 | { 69 | iki_relocate(dp, "xsim.dir/Register_tb_behav/xsim.reloc", (void **)funcTab, 7); 70 | iki_vhdl_file_variable_register(dp + 3600); 71 | iki_vhdl_file_variable_register(dp + 3656); 72 | 73 | 74 | /*Populate the transaction function pointer field in the whole net structure */ 75 | } 76 | 77 | void sensitize(char *dp) 78 | { 79 | iki_sensitize(dp, "xsim.dir/Register_tb_behav/xsim.reloc"); 80 | } 81 | 82 | void simulate(char *dp) 83 | { 84 | iki_schedule_processes_at_time_zero(dp, "xsim.dir/Register_tb_behav/xsim.reloc"); 85 | // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net 86 | iki_execute_processes(); 87 | 88 | // Schedule resolution functions for the multiply driven Verilog nets that have strength 89 | // Schedule transaction functions for the singly driven Verilog nets that have strength 90 | 91 | } 92 | #include "iki_bridge.h" 93 | void relocate(char *); 94 | 95 | void sensitize(char *); 96 | 97 | void simulate(char *); 98 | 99 | extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); 100 | extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; 101 | extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; 102 | 103 | int main(int argc, char **argv) 104 | { 105 | iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; 106 | iki_set_sv_type_file_path_name("xsim.dir/Register_tb_behav/xsim.svtype"); 107 | iki_set_crvs_dump_file_path_name("xsim.dir/Register_tb_behav/xsim.crvsdump"); 108 | void* design_handle = iki_create_design("xsim.dir/Register_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); 109 | iki_set_rc_trial_count(100); 110 | (void) design_handle; 111 | return iki_simulate_design(); 112 | } 113 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Register_tb_behav/webtalk/usage_statistics_ext_xsim.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 |
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43 | 44 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Register_tb_behav/webtalk/xsim_webtalk.tcl: -------------------------------------------------------------------------------- 1 | webtalk_init -webtalk_dir /home/kent/source/vhdl/Computer8Bit/src/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Register_tb_behav/webtalk/ 2 | webtalk_register_client -client project 3 | webtalk_add_data -client project -key date_generated -value "Mon Dec 21 16:35:55 2020" -context "software_version_and_target_device" 4 | webtalk_add_data -client project -key product_version -value "XSIM v2020.2 (64-bit)" -context "software_version_and_target_device" 5 | webtalk_add_data -client project -key build_version -value "3064766" -context "software_version_and_target_device" 6 | webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" 7 | webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" 8 | webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" 9 | webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" 10 | webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" 11 | webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" 12 | webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" 13 | webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" 14 | webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" 15 | webtalk_add_data -client project -key random_id -value "c504ae24-7c68-4174-ac1a-c3bf683363a6" -context "software_version_and_target_device" 16 | webtalk_add_data -client project -key project_id -value "093bea831d884684b7367d1f133b0d45" -context "software_version_and_target_device" 17 | webtalk_add_data -client project -key project_iteration -value "29" -context "software_version_and_target_device" 18 | webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" 19 | webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.1 LTS" -context "user_environment" 20 | webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-8250U CPU @ 1.60GHz" -context "user_environment" 21 | webtalk_add_data -client project -key cpu_speed -value "3069.624 MHz" -context "user_environment" 22 | webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" 23 | webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" 24 | webtalk_register_client -client xsim 25 | webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" 26 | webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" 27 | webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" 28 | webtalk_add_data -client xsim -key iteration -value "2" -context "xsim\\usage" 29 | webtalk_add_data -client xsim -key Simulation_Time -value "0.08_sec" -context "xsim\\usage" 30 | webtalk_add_data -client xsim -key Simulation_Memory -value "115296_KB" -context "xsim\\usage" 31 | webtalk_transmit -clientid 374147158 -regid "" -xml /home/kent/source/vhdl/Computer8Bit/src/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Register_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/kent/source/vhdl/Computer8Bit/src/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Register_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/kent/source/vhdl/Computer8Bit/src/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Register_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" 32 | webtalk_terminate 33 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Register_tb_behav/xsim.mem: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oddek/8-bit-Computer/775f850e23f1f9b92c459904e54e676aa97de8c6/src/computer/Computer8Bit.sim/sim_1/behav/xsim/xsim.dir/Register_tb_behav/xsim.mem -------------------------------------------------------------------------------- /src/computer/Computer8Bit.sim/sim_1/behav/xsim/xvhdl.pb: -------------------------------------------------------------------------------- 1 | 2 |  3 | 4 | End Record -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sim_1/new/Computer_tb.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 12/21/2020 10:40:36 AM 6 | -- Design Name: 7 | -- Module Name: Computer_tb - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity Computer_tb is 35 | -- Port ( ); 36 | end Computer_tb; 37 | 38 | architecture Behavioral of Computer_tb is 39 | 40 | signal clk, rst : STD_LOGIC; 41 | constant clk_period : time := 10 ps; 42 | signal seg : STD_LOGIC_VECTOR(7 downto 0); 43 | signal an : STD_LOGIC_VECTOR(3 downto 0); 44 | signal JB : STD_LOGIC_VECTOR(7 downto 0); 45 | signal lcd_rs, lcd_rw, lcd_en : STD_LOGIC; 46 | 47 | Component Computer 48 | Port ( clk : in STD_LOGIC; 49 | rst : in STD_LOGIC; 50 | seg : out STD_LOGIC_VECTOR(7 downto 0); 51 | an : out STD_LOGIC_VECTOR(3 downto 0); 52 | JB : out STD_LOGIC_VECTOR(7 downto 0); 53 | lcd_rs, lcd_rw, lcd_en : out STD_LOGIC); 54 | end Component; 55 | 56 | begin 57 | UUT: Computer 58 | port map 59 | ( 60 | clk => clk, 61 | rst => rst, 62 | seg => seg, 63 | an => an, 64 | JB => JB, 65 | lcd_rs => lcd_rs, 66 | lcd_rw => lcd_rw, 67 | lcd_en => lcd_en 68 | ); 69 | 70 | 71 | process 72 | begin 73 | clk <= '0'; 74 | wait for clk_period/2; 75 | clk <= '1'; 76 | wait for clk_period/2; 77 | end process; 78 | 79 | process 80 | begin 81 | rst <= '1'; 82 | wait for clk_period*1; 83 | rst <= '0'; 84 | wait for clk_period*100; 85 | wait; 86 | end process; 87 | 88 | end Behavioral; 89 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sim_1/new/Register_tb.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 12/21/2020 03:40:15 PM 6 | -- Design Name: 7 | -- Module Name: Register_tb - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity Register_tb is 35 | -- Port ( ); 36 | end Register_tb; 37 | 38 | architecture Behavioral of Register_tb is 39 | 40 | signal clk, rst, en, load : STD_LOGIC; 41 | constant clk_period : time := 10 ps; 42 | signal q : STD_LOGIC_VECTOR(7 downto 0); 43 | signal dataBus : STD_LOGIC_VECTOR(7 downto 0); 44 | 45 | 46 | Component PIPORegister 47 | Generic(data_width : integer := 8); 48 | Port ( clk : in STD_LOGIC; 49 | rst : in STD_LOGIC; 50 | en : in STD_LOGIC; 51 | load : in STD_LOGIC; 52 | q : out STD_LOGIC_VECTOR (data_width-1 downto 0); 53 | dataBus : inout STD_LOGIC_VECTOR (data_width-1 downto 0)); 54 | end Component; 55 | 56 | begin 57 | UUT: PIPORegister 58 | port map 59 | ( 60 | clk => clk, 61 | rst => rst, 62 | en => en, 63 | load => load, 64 | q => q, 65 | dataBus => dataBus 66 | ); 67 | 68 | 69 | process 70 | begin 71 | clk <= '0'; 72 | wait for clk_period/2; 73 | clk <= '1'; 74 | wait for clk_period/2; 75 | end process; 76 | 77 | process 78 | begin 79 | rst <= '1'; 80 | en <= '0'; 81 | load <= '0'; 82 | 83 | wait for clk_period*4; 84 | rst <= '0'; 85 | wait for clk_period*2; 86 | dataBus <= x"11"; 87 | wait for clk_period/2; 88 | dataBus <= x"FF"; 89 | load <= '1'; 90 | wait for clk_period/2; 91 | load <= '0'; 92 | wait for clk_period*100; 93 | wait; 94 | end process; 95 | 96 | end Behavioral; 97 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/ALU.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 12/18/2020 11:14:44 AM 6 | -- Design Name: 7 | -- Module Name: ALU - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 25 | use IEEE.NUMERIC_STD.ALL; 26 | 27 | 28 | entity ALU is 29 | Generic(code_width : integer := 5; 30 | data_width : integer := 8); 31 | Port ( opcode : in STD_LOGIC_VECTOR (code_width-1 downto 0); 32 | en : STD_LOGIC; 33 | x : in STD_LOGIC_VECTOR (data_width-1 downto 0); 34 | y : in STD_LOGIC_VECTOR (data_width-1 downto 0); 35 | logical_bool : out STD_LOGIC; 36 | Z : out STD_LOGIC_VECTOR (data_width-1 downto 0)); 37 | end ALU; 38 | 39 | architecture Behavioral of ALU is 40 | 41 | signal temp : STD_LOGIC_VECTOR(data_width-1 downto 0); 42 | signal mul_temp : STD_LOGIC_VECTOR((data_width * 2) - 1 downto 0) := (others => '0'); 43 | 44 | signal x_signed : signed(x'Range); 45 | signal y_signed : signed(y'Range); 46 | signal x_unsigned : unsigned(x'Range); 47 | signal y_unsigned : unsigned(y'Range); 48 | 49 | constant alu_nop : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#00#, 5)); 50 | constant alu_add : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#01#, 5)); 51 | constant alu_addu : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#02#, 5)); 52 | constant alu_sub : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#03#, 5)); 53 | constant alu_subu : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#04#, 5)); 54 | constant alu_equ : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#05#, 5)); 55 | constant alu_eqg : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#06#, 5)); 56 | constant alu_gre : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#07#, 5)); 57 | constant alu_and : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#08#, 5)); 58 | constant alu_or : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#09#, 5)); 59 | constant alu_notx : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#0A#, 5)); 60 | constant alu_noty : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#0B#, 5)); 61 | constant alu_xor : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#0C#, 5)); 62 | constant alu_xnor : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#0D#, 5)); 63 | constant alu_sxl : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#0E#, 5)); 64 | constant alu_sxr : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#0F#, 5)); 65 | constant alu_syl : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#10#, 5)); 66 | constant alu_syr : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#11#, 5)); 67 | constant alu_mull : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#12#, 5)); 68 | constant alu_mulu : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#13#, 5)); 69 | constant alu_divq : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#14#, 5)); 70 | constant alu_divr : STD_LOGIC_VECTOR(4 downto 0) := std_logic_vector(to_unsigned(16#15#, 5)); 71 | 72 | begin 73 | --Todo: Bytt ut verdier med variabler i case 74 | 75 | x_signed <= signed(x); 76 | y_signed <= signed(y); 77 | x_unsigned <= unsigned(x); 78 | y_unsigned <= unsigned(y); 79 | 80 | process(opcode, x, y, x_signed, y_signed, x_unsigned, y_unsigned, mul_temp) 81 | begin 82 | 83 | case opcode is 84 | --Noop 85 | when "00000" => 86 | null; 87 | --Add signed 88 | when "00001" => 89 | temp <= std_logic_vector(x_signed + y_signed); 90 | --Add unsigned 91 | when "00010" => 92 | temp <= std_logic_vector(x_unsigned + y_unsigned); 93 | --Sub signed 94 | when "00011" => 95 | temp <= std_logic_vector(x_signed - y_signed); 96 | --Sub unsigned 97 | when "00100" => 98 | temp <= std_logic_vector(x_unsigned - y_unsigned); 99 | -- Equals 100 | when "00101" => 101 | if(x_signed = y_signed) then 102 | logical_bool <= '1'; 103 | temp <= (others => '1'); 104 | else 105 | logical_bool <= '0'; 106 | temp <= (others => '0'); 107 | end if; 108 | --Greater or equal 109 | when "00110" => 110 | if(x_signed >= y_signed) then 111 | logical_bool <= '1'; 112 | temp <= (others => '1'); 113 | else 114 | logical_bool <= '0'; 115 | temp <= (others => '0'); 116 | end if; 117 | --Greater than 118 | when "00111" => 119 | if(x_signed > y_signed) then 120 | logical_bool <= '1'; 121 | temp <= (others => '1'); 122 | else 123 | temp <= (others => '0'); 124 | logical_bool <= '0'; 125 | end if; 126 | -- AND 127 | when "01000" => 128 | temp <= x and y; 129 | -- OR 130 | when "01001" => 131 | temp <= x or y; 132 | --NOT X 133 | when "01010" => 134 | temp <= not x; 135 | --NOT Y 136 | when "01011" => 137 | temp <= not y; 138 | -- XOR 139 | when "01100" => 140 | temp <= x xor y; 141 | -- XNOR 142 | when "01101" => 143 | temp <= x xnor y; 144 | -- SXL (shift X reg left) 145 | when "01110" => 146 | temp <= x(6 downto 0) & '0'; 147 | -- SXR (shift X reg right) 148 | when "01111" => 149 | temp <= '0' & x(7 downto 1); 150 | -- SYL (shift Y reg left) 151 | when "10000" => 152 | temp <= y(6 downto 0) & '0'; 153 | 154 | --SYR (shift Y reg right) 155 | when "10001" => 156 | temp <= '0' & y(7 downto 1); 157 | 158 | -- MULL (Multiply, return lower bits) 159 | when "10010" => 160 | mul_temp <= std_logic_vector(x_signed * y_signed); 161 | temp <= mul_temp(7 downto 0); 162 | -- MULU (Multiply, return upper bits) 163 | when "10011" => 164 | mul_temp <= std_logic_vector(x_signed * y_signed); 165 | temp <= mul_temp(15 downto 8); 166 | -- DIVQ, (Divide, return Quotient) 167 | when "10100" => 168 | --TO BE IMPLEMENTED 169 | temp <= (others => '0'); 170 | -- DIVR (Divide, return remainder) 171 | when "10101" => 172 | --TO BE IMPLEMENTED 173 | temp <= (others => '0'); 174 | when others => 175 | end case; 176 | end process; 177 | 178 | Z <= temp when en = '1' else 179 | (others => 'Z'); 180 | 181 | end Behavioral; 182 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/CPU.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.NUMERIC_STD.ALL; 5 | 6 | entity CPU is 7 | Port ( clk : in STD_LOGIC; 8 | rst : in STD_LOGIC; 9 | rw : out STD_LOGIC; 10 | mem_en : out STD_LOGIC; 11 | addr : out STD_LOGIC_VECTOR (7 downto 0); 12 | dataBus : inout STD_LOGIC_VECTOR (7 downto 0)); 13 | end CPU; 14 | 15 | architecture Behavioral of CPU is 16 | 17 | 18 | Component ControlUnit 19 | Port ( clk : in STD_LOGIC; 20 | rst : in STD_LOGIC; 21 | alu_boolean : in STD_LOGIC; 22 | instr : in STD_LOGIC_VECTOR(7 downto 0); 23 | instr2 : in STD_LOGIC_VECTOR(7 downto 0); 24 | alu_opcode : out STD_LOGIC_VECTOR(4 downto 0); 25 | alu_out : out STD_LOGIC; 26 | pc_load : out STD_LOGIC; 27 | pc_inc : out STD_LOGIC; 28 | pc_out : out STD_LOGIC; 29 | ip_load : out STD_LOGIC; 30 | ip_inc : out STD_LOGIC; 31 | ip_out : out STD_LOGIC; 32 | sp_inc : out STD_LOGIC; 33 | sp_dec : out STD_LOGIC; 34 | sp_out : out STD_LOGIC; 35 | reg_load : out STD_LOGIC_VECTOR(2 downto 0); 36 | reg_out : out STD_LOGIC_VECTOR(2 downto 0); 37 | mem_load : out STD_LOGIC; 38 | mem_out : out STD_LOGIC); 39 | end Component; 40 | 41 | --Program counter signals 42 | signal pc_inc : STD_LOGIC; 43 | signal pc_load : STD_LOGIC; 44 | signal pc_en : STD_LOGIC; 45 | 46 | Component ProgramCounter 47 | generic(N : integer := 8; 48 | M : integer := 256); 49 | Port ( rst : in STD_LOGIC; 50 | clk : in STD_LOGIC; 51 | inc : in STD_LOGIC; 52 | en : in STD_LOGIC; 53 | load : in STD_LOGIC; 54 | dataBus : inout STD_LOGIC_VECTOR (N-1 downto 0)); 55 | end Component; 56 | 57 | --Index Register signals 58 | signal ip_inc : STD_LOGIC; 59 | signal ip_load : STD_LOGIC; 60 | signal ip_en : STD_LOGIC; 61 | 62 | Component IndexRegister 63 | generic(N : integer := 8; 64 | M : integer := 256); 65 | Port ( rst : in STD_LOGIC; 66 | clk : in STD_LOGIC; 67 | en : in STD_LOGIC; 68 | inc : in STD_LOGIC; 69 | load : in STD_LOGIC; 70 | dataBus : inout STD_LOGIC_VECTOR (N-1 downto 0)); 71 | end Component; 72 | 73 | --StackPointer signals: 74 | signal sp_inc, sp_dec, sp_en : STD_LOGIC; 75 | 76 | Component StackPointer 77 | generic(N : integer := 4; 78 | M : integer := 16); 79 | Port ( clk : in STD_LOGIC; 80 | rst : in STD_LOGIC; 81 | en : in STD_LOGIC; 82 | inc : in STD_LOGIC; 83 | dec : in STD_LOGIC; 84 | q : out STD_LOGIC_VECTOR (7 downto 0)); 85 | end Component; 86 | 87 | --RegisterBank signals 88 | signal reg_out : STD_LOGIC_VECTOR(2 downto 0); 89 | signal reg_load : STD_LOGIC_VECTOR(2 downto 0); 90 | signal reg2AluX, reg2AluY, instr2CU, instr2CU2 : STD_LOGIC_VECTOR(7 downto 0); 91 | 92 | Component RegisterBank 93 | Generic( addr_width : integer := 3; 94 | data_width : integer := 8); 95 | Port ( clk : in STD_LOGIC; 96 | rst : in STD_LOGIC; 97 | reg_out : in STD_LOGIC_VECTOR(addr_width-1 downto 0); 98 | reg_load : in STD_LOGIC_VECTOR(addr_width-1 downto 0); 99 | mem_addr : out STD_LOGIC_VECTOR(7 downto 0); 100 | instr2CU : out STD_LOGIC_VECTOR(7 downto 0); 101 | instr2CU2 : out STD_LOGIC_VECTOR(7 downto 0); 102 | aluBusX : out STD_LOGIC_VECTOR(data_width-1 downto 0); 103 | aluBusY : out STD_LOGIC_VECTOR(data_width-1 downto 0); 104 | dataBus : inout STD_LOGIC_VECTOR (data_width-1 downto 0)); 105 | end Component; 106 | 107 | --ALU signals 108 | signal alu_opcode : STD_LOGIC_VECTOR(4 downto 0); 109 | signal alu_en : STD_LOGIC; 110 | signal alu_boolean : STD_LOGIC; 111 | 112 | Component ALU 113 | Generic(code_width : integer := 5; 114 | data_width : integer := 8); 115 | Port ( opcode : in STD_LOGIC_VECTOR (code_width-1 downto 0); 116 | en : STD_LOGIC; 117 | x : in STD_LOGIC_VECTOR (data_width-1 downto 0); 118 | y : in STD_LOGIC_VECTOR (data_width-1 downto 0); 119 | logical_bool : out STD_LOGIC; 120 | Z : out STD_LOGIC_VECTOR (data_width-1 downto 0)); 121 | end Component; 122 | 123 | 124 | begin 125 | --Instantiation CONTROLUNIT 126 | cu : ControlUnit 127 | port map 128 | ( 129 | clk => clk, 130 | rst => rst, 131 | instr => instr2CU, 132 | instr2 => instr2CU2, 133 | alu_opcode => alu_opcode, 134 | alu_boolean => alu_boolean, 135 | alu_out => alu_en, 136 | mem_load => rw, 137 | mem_out => mem_en, 138 | pc_load => pc_load, 139 | pc_inc => pc_inc, 140 | pc_out => pc_en, 141 | ip_load => ip_load, 142 | ip_inc => ip_inc, 143 | ip_out => ip_en, 144 | reg_load => reg_load, 145 | reg_out => reg_out, 146 | sp_out => sp_en, 147 | sp_inc => sp_inc, 148 | sp_dec => sp_dec 149 | ); 150 | 151 | --Instantiation PROGRAMCOUNTER 152 | pc : ProgramCounter 153 | port map 154 | ( 155 | rst => rst, 156 | clk => clk, 157 | en => pc_en, 158 | inc => pc_inc, 159 | load => pc_load, 160 | dataBus => dataBus 161 | ); 162 | 163 | --Instantiation IndexRegister 164 | ip : IndexRegister 165 | port map 166 | ( 167 | rst => rst, 168 | clk => clk, 169 | en => ip_en, 170 | inc => ip_inc, 171 | load => ip_load, 172 | dataBus => dataBus 173 | ); 174 | 175 | --Instantiation StackPointer 176 | sp : StackPointer 177 | port map 178 | ( 179 | clk => clk, 180 | rst => rst, 181 | en => sp_en, 182 | inc => sp_inc, 183 | dec => sp_dec, 184 | q => dataBus 185 | ); 186 | 187 | --Instantiation REGISTERBANK 188 | registers : RegisterBank 189 | port map 190 | ( 191 | clk => clk, 192 | rst => rst, 193 | reg_out => reg_out, 194 | reg_load => reg_load, 195 | mem_addr => addr, 196 | instr2CU => instr2CU, 197 | instr2CU2 => instr2CU2, 198 | aluBusX => reg2AluX, 199 | aluBusY => reg2AluY, dataBus => dataBus 200 | ); 201 | 202 | --Instantiation ALU 203 | aluInst : ALU 204 | port map 205 | ( 206 | opcode => alu_opcode, 207 | en => alu_en, 208 | x => reg2AluX, 209 | y => reg2AluY, 210 | logical_bool => alu_boolean, 211 | Z => dataBus 212 | ); 213 | 214 | end Behavioral; 215 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/Computer.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | 5 | entity Computer is 6 | Port ( clk : in STD_LOGIC; 7 | rst : in STD_LOGIC; 8 | seg : out STD_LOGIC_VECTOR(7 downto 0); 9 | an : out STD_LOGIC_VECTOR(3 downto 0); 10 | JB : out STD_LOGIC_VECTOR(7 downto 0); 11 | lcd_rs, lcd_rw, lcd_en : out STD_LOGIC); 12 | end Computer; 13 | 14 | architecture Behavioral of Computer is 15 | 16 | 17 | 18 | --Internal signals 19 | signal mem_en : STD_LOGIC; 20 | signal cpu_rw : STD_LOGIC; 21 | signal dataBus : STD_LOGIC_VECTOR(7 downto 0); 22 | signal addrBus : STD_LOGIC_VECTOR(7 downto 0); 23 | 24 | signal romEnable : STD_LOGIC; 25 | signal ramEnable : STD_LOGIC; 26 | 27 | --Stuf for IO/LCD screen 28 | signal load_io_a, load_io_b : STD_LOGIC; 29 | signal lcd_a, lcd_b : STD_LOGIC_VECTOR(7 downto 0); 30 | 31 | --Seven segments display on Basys3 32 | signal hexDisp : STD_LOGIC_VECTOR(15 downto 0); 33 | 34 | --Slower clock for all of the components 35 | signal global_clk : STD_LOGIC; 36 | 37 | Component CPU 38 | Port ( clk : in STD_LOGIC; 39 | rst : in STD_LOGIC; 40 | rw : out STD_LOGIC; 41 | mem_en : out STD_LOGIC; 42 | addr : out STD_LOGIC_VECTOR (7 downto 0); 43 | dataBus : inout STD_LOGIC_VECTOR (7 downto 0)); 44 | end Component; 45 | 46 | Component ROM 47 | Generic(AddrSize : Integer := 7; 48 | DataSize : Integer := 8); 49 | Port ( addr : in STD_LOGIC_VECTOR (AddrSize-1 downto 0); 50 | en : in STD_LOGIC; 51 | dataOut : out STD_LOGIC_VECTOR (Datasize-1 downto 0)); 52 | end Component; 53 | 54 | Component RAM 55 | Generic( AddrSize : Integer := 7; 56 | DataSize : Integer := 8); 57 | Port ( clk : in STD_LOGIC; 58 | load : in STD_LOGIC; 59 | en : in STD_LOGIC; 60 | addr : in STD_LOGIC_VECTOR (AddrSize-1 downto 0); 61 | dataBus : inout STD_LOGIC_VECTOR (DataSize-1 downto 0)); 62 | end Component; 63 | 64 | --Sevensegments display on basys3 65 | Component SixteenBitDisplay 66 | Port ( sw : in STD_LOGIC_VECTOR (15 downto 0); 67 | clk : in STD_LOGIC; 68 | rst : in STD_LOGIC; 69 | seg : out STD_LOGIC_VECTOR (7 downto 0); 70 | an : out STD_LOGIC_VECTOR(3 downto 0)); 71 | end Component; 72 | 73 | --Counter for slowing down clock, set to a million down below 74 | Component ModMCounter 75 | Generic(N : integer := 7; 76 | M : Integer := 100); 77 | Port ( clk : in STD_LOGIC; 78 | rst : in STD_LOGIC; 79 | q : out STD_LOGIC_VECTOR(N-1 downto 0); 80 | max_tick : out STD_LOGIC); 81 | 82 | end Component; 83 | 84 | --IO registers 85 | Component IO 86 | Port ( clk : in STD_LOGIC; 87 | rst : in STD_LOGIC; 88 | en_load : in STD_LOGIC; 89 | load_a : in STD_LOGIC; 90 | load_b : in STD_LOGIC; 91 | dataBus : in STD_LOGIC_VECTOR(7 downto 0); 92 | Z_a : out STD_LOGIC_VECTOR(7 downto 0); 93 | Z_b : out STD_LOGIC_VECTOR(7 downto 0)); 94 | end Component; 95 | 96 | begin 97 | 98 | --Rom is enabled when mem_en is high and were in the lower address space 99 | romEnable <= '1' when (mem_en = '1' and addrBus(7) = '0') else 100 | '0'; 101 | 102 | --Ram is enabled when mem_en is high and were in the upper address space 103 | ramEnable <= '1' when (mem_en = '1' and addrBus(7) = '1') else 104 | '0'; 105 | 106 | --Display address bus and data bus on seven segment display 107 | hexDisp(15 downto 8) <= addrBus(7 downto 0); 108 | hexDisp(7 downto 0) <= dataBus(7 downto 0); 109 | 110 | --Io is currently setup to only work as output, to interface with an lcd display: 111 | load_io_a <= '1' when addrBus = "11111111" else 112 | '0'; 113 | load_io_b <= '1' when addrBus = "11111110" else 114 | '0'; 115 | JB <= lcd_b; 116 | lcd_rs <= lcd_a(5); 117 | lcd_rw <= lcd_a(6); 118 | lcd_en <= lcd_a(7); 119 | 120 | 121 | 122 | processor : CPU 123 | port map 124 | ( 125 | clk => global_clk, 126 | rst => rst, 127 | rw => cpu_rw, 128 | mem_en => mem_en, 129 | addr => addrBus, 130 | dataBus => dataBus 131 | ); 132 | 133 | readOnlyMem : ROM 134 | port map 135 | ( 136 | addr => addrBus(6 downto 0), 137 | en => romEnable, 138 | dataOut => dataBus 139 | ); 140 | 141 | 142 | 143 | writeMem : RAM 144 | port map 145 | ( 146 | clk => global_clk, 147 | load => cpu_rw, 148 | en => ramEnable, 149 | addr => addrBus(6 downto 0), 150 | dataBus => dataBus 151 | ); 152 | 153 | 154 | 155 | sseg: SixteenBitDisplay 156 | port map 157 | ( 158 | sw => hexDisp, 159 | clk => clk, 160 | rst => rst, 161 | seg => seg, 162 | an => an 163 | ); 164 | 165 | 166 | modMillionCounter : ModMCounter 167 | generic map 168 | ( 169 | N => 27, 170 | M => 1000000 171 | ) 172 | port map 173 | ( 174 | clk => clk, 175 | rst => rst, 176 | q => open, 177 | max_tick => global_clk --set as open for simulation, as we don't want a slow clock in that case 178 | ); 179 | --Uncomment for simulation 180 | --global_clk <= clk; 181 | 182 | io_reg : IO 183 | port map 184 | ( 185 | clk => global_clk, 186 | rst => rst, 187 | en_load => cpu_rw, 188 | load_a => load_io_a, 189 | load_b => load_io_b, 190 | dataBus => dataBus, 191 | Z_a => lcd_a, 192 | Z_b => lcd_b 193 | ); 194 | 195 | end Behavioral; 196 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/HexToSseg.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | 5 | entity HexToSseg is 6 | Port ( hex : in STD_LOGIC_VECTOR (3 downto 0); 7 | seg : out STD_LOGIC_VECTOR (7 downto 0)); 8 | end HexToSseg; 9 | 10 | architecture Behavioral of HexToSseg is 11 | 12 | begin 13 | 14 | seg(7) <= '1'; 15 | 16 | process(hex) 17 | begin 18 | case hex is 19 | when "0000" => -- 0 20 | seg(6 downto 0) <= "1000000"; 21 | when "0001" => -- 1 22 | seg(6 downto 0) <= "1111001"; 23 | when "0010" => -- 2 24 | seg(6 downto 0) <= "0100100"; 25 | when "0011" => -- 3 26 | seg(6 downto 0) <= "0110000"; 27 | when "0100" => --4 28 | seg(6 downto 0) <= "0011001"; 29 | when "0101" => --5 30 | seg(6 downto 0) <= "0010010"; 31 | when "0110" => -- 6 32 | seg(6 downto 0) <= "0000010"; 33 | when "0111" => -- 7 34 | seg(6 downto 0) <= "1111000"; 35 | when "1000" => -- 8 36 | seg(6 downto 0) <= "0000000"; 37 | when "1001" => -- 9 38 | seg(6 downto 0) <= "0010000"; 39 | when "1010" => -- 10 | A 40 | seg(6 downto 0) <= "0001000"; 41 | when "1011" => -- 11|B 42 | seg(6 downto 0) <= "0000011"; 43 | when "1100" => -- 12 |C 44 | seg(6 downto 0) <= "1000110"; 45 | when "1101" => -- 13 |D 46 | seg(6 downto 0) <= "0100001"; 47 | when "1110" => -- 14 |E 48 | seg(6 downto 0) <= "0000110"; 49 | when others => -- 15 | F 50 | seg(6 downto 0) <= "0001110"; 51 | end case; 52 | 53 | end process; 54 | end Behavioral; 55 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/IO.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | 5 | entity IO is 6 | Port ( clk : in STD_LOGIC; 7 | rst : in STD_LOGIC; 8 | en_load : in STD_LOGIC; 9 | load_a : in STD_LOGIC; 10 | load_b : in STD_LOGIC; 11 | dataBus : in STD_LOGIC_VECTOR(7 downto 0); 12 | Z_a : out STD_LOGIC_VECTOR(7 downto 0); 13 | Z_b : out STD_LOGIC_VECTOR(7 downto 0)); 14 | end IO; 15 | 16 | --Two registers for IO 17 | architecture Behavioral of IO is 18 | 19 | signal reg_a : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 20 | signal reg_b : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 21 | begin 22 | 23 | process(clk, rst, en_load, load_a, load_b, dataBus) 24 | begin 25 | if(rst = '1') then 26 | reg_a <= (others => '0'); 27 | reg_b <= (others => '0'); 28 | elsif(rising_edge(clk)) then 29 | if(en_load = '1') then 30 | if(load_a = '1') then 31 | reg_a <= dataBus; 32 | elsif(load_b = '1') then 33 | reg_b <= dataBus; 34 | end if; 35 | end if; 36 | end if; 37 | end process; 38 | 39 | Z_a <= reg_a; 40 | Z_b <= reg_b; 41 | 42 | end Behavioral; 43 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/IndexRegister.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.NUMERIC_STD.ALL; 5 | 6 | entity IndexRegister is 7 | generic(N : integer := 8; 8 | M : integer := 256); 9 | Port ( rst : in STD_LOGIC; 10 | clk : in STD_LOGIC; 11 | en : in STD_LOGIC; 12 | inc : in STD_LOGIC; 13 | load : in STD_LOGIC; 14 | dataBus : inout STD_LOGIC_VECTOR (N-1 downto 0)); 15 | end IndexRegister; 16 | 17 | architecture Behavioral of IndexRegister is 18 | 19 | signal r_reg, r_next : unsigned(N-1 downto 0) := (others => '0'); 20 | 21 | begin 22 | process(rst, clk, en, dataBus, load) 23 | begin 24 | if(rst = '1') then 25 | r_reg <= (others => '0'); 26 | elsif(rising_edge(clk)) then 27 | if(inc = '1') then 28 | r_reg <= r_next; 29 | elsif(load = '1') then 30 | r_reg <= unsigned(dataBus); 31 | end if; 32 | end if; 33 | end process; 34 | 35 | --Next state logic 36 | r_next <= (others => '0') when r_reg = M-1 else 37 | r_reg + 1; 38 | 39 | dataBus <= STD_LOGIC_VECTOR(r_reg) when en = '1' else 40 | (others => 'Z'); 41 | 42 | end Behavioral; 43 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/ModMCounter.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.NUMERIC_STD.ALL; 5 | 6 | entity ModMCounter is 7 | Generic(N : integer := 7; 8 | M : Integer := 100); 9 | Port ( clk : in STD_LOGIC; 10 | rst : in STD_LOGIC; 11 | q : out STD_LOGIC_VECTOR(N-1 downto 0); 12 | max_tick : out STD_LOGIC); 13 | 14 | end ModMCounter; 15 | 16 | architecture Behavioral of ModMCounter is 17 | 18 | signal r_reg, r_next : unsigned(N-1 downto 0) := (others=> '0'); 19 | begin 20 | 21 | process(rst, clk) 22 | begin 23 | if rst = '1' then 24 | r_reg <= (others => '0'); 25 | elsif rising_edge(clk) then 26 | r_reg <= r_next; 27 | end if; 28 | end process; 29 | 30 | r_next <= (others => '0') when r_reg = M-1 else 31 | r_reg + 1; 32 | 33 | q <= std_logic_vector(r_reg); 34 | max_tick <= '1' when r_reg = M-1 else 35 | '0'; 36 | 37 | 38 | end Behavioral; 39 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/PIPORegister.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | 5 | entity PIPORegister is 6 | Generic(data_width : integer := 8); 7 | Port ( clk : in STD_LOGIC; 8 | rst : in STD_LOGIC; 9 | en : in STD_LOGIC; 10 | load : in STD_LOGIC; 11 | q : out STD_LOGIC_VECTOR (data_width-1 downto 0); 12 | dataBus : inout STD_LOGIC_VECTOR (data_width-1 downto 0)); 13 | end PIPORegister; 14 | 15 | architecture Behavioral of PIPORegister is 16 | 17 | signal reg : STD_LOGIC_VECTOR(data_width-1 downto 0) := (others => '0'); 18 | 19 | begin 20 | 21 | process(clk, rst, en, load, dataBus, reg) 22 | begin 23 | -- dataBus <= (others => 'Z'); 24 | if(rst = '1') then 25 | reg <= (others => '0'); 26 | elsif(rising_edge(clk)) then 27 | if(load = '1') then 28 | reg <= dataBus; 29 | end if; 30 | end if; 31 | end process; 32 | 33 | --Output on dataBus only when enabled 34 | dataBus <= reg when en = '1' else (others => 'Z'); 35 | 36 | --Always output on q 37 | q <= reg; 38 | 39 | end Behavioral; 40 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/ProgramCounter.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.NUMERIC_STD.ALL; 5 | 6 | entity ProgramCounter is 7 | generic(N : integer := 8; 8 | M : integer := 128); 9 | Port ( rst : in STD_LOGIC; 10 | clk : in STD_LOGIC; 11 | en : in STD_LOGIC; 12 | inc : in STD_LOGIC; 13 | load : in STD_LOGIC; 14 | dataBus : inout STD_LOGIC_VECTOR (N-1 downto 0)); 15 | end ProgramCounter; 16 | 17 | architecture Behavioral of ProgramCounter is 18 | 19 | signal r_reg, r_next : unsigned(N-1 downto 0) := (others => '0'); 20 | 21 | begin 22 | process(rst, clk, en, dataBus, load) 23 | begin 24 | if(rst = '1') then 25 | r_reg <= (others => '0'); 26 | elsif(rising_edge(clk)) then 27 | if(inc = '1') then 28 | r_reg <= r_next; 29 | elsif(load = '1') then 30 | r_reg <= unsigned(dataBus); 31 | end if; 32 | end if; 33 | end process; 34 | 35 | --Next state logic 36 | r_next <= (others => '0') when r_reg = M-1 else 37 | r_reg + 1; 38 | 39 | --Output logic 40 | dataBus <= STD_LOGIC_VECTOR(r_reg) when en = '1' else 41 | (others => 'Z'); 42 | 43 | end Behavioral; 44 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/RAM.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.NUMERIC_STD.ALL; 5 | 6 | entity RAM is 7 | Generic( AddrSize : Integer := 7; 8 | DataSize : Integer := 8); 9 | Port ( clk : in STD_LOGIC; 10 | load : in STD_LOGIC; 11 | en : in STD_LOGIC; 12 | addr : in STD_LOGIC_VECTOR (AddrSize-1 downto 0); 13 | dataBus : inout STD_LOGIC_VECTOR (DataSize-1 downto 0)); 14 | end RAM; 15 | 16 | architecture Behavioral of RAM is 17 | type memory_type is array(0 to (2**AddrSize)-1) of std_logic_vector(DataSize-1 downto 0); 18 | signal memory : memory_type := (others => (others => '1')); 19 | begin 20 | process(clk, load, addr, memory, dataBus) 21 | begin 22 | if(rising_edge(clk)) then 23 | if(load = '1') then 24 | memory(to_integer(unsigned(addr))) <= dataBus; 25 | end if; 26 | end if; 27 | end process; 28 | 29 | dataBus <= memory(to_integer(unsigned(addr))) when (en = '1') else 30 | (others => 'Z'); 31 | end Behavioral; 32 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/ROM.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | use IEEE.STD_LOGIC_TEXTIO.ALL; 6 | use STD.TEXTIO.ALL; 7 | 8 | entity ROM is 9 | Generic(AddrSize : Integer := 7; 10 | DataSize : Integer := 8); 11 | Port ( addr : in STD_LOGIC_VECTOR (AddrSize-1 downto 0); 12 | en : in STD_LOGIC; 13 | dataOut : out STD_LOGIC_VECTOR (Datasize-1 downto 0)); 14 | end ROM; 15 | 16 | --Rom is filled with contents of file prog.bin 17 | --File has to be 128 lines of binary, with a newline for each byte 18 | architecture Behavioral of ROM is 19 | 20 | type memory_type is array(0 to (2**AddrSize)-1) of std_logic_vector(DataSize-1 downto 0); 21 | 22 | impure function getFile(fileName : string) return memory_type is 23 | file fileHandle : TEXT open READ_MODE is FileName; 24 | variable currentLine : LINE; 25 | variable tempWord : STD_LOGIC_VECTOR(DataSize - 1 downto 0); 26 | variable result : memory_type := (others => (others => '0')); 27 | variable lineNumber : integer := 0; 28 | begin 29 | while not endFile(fileHandle) loop 30 | readline(fileHandle, currentLine); 31 | read(currentLine, tempWord); 32 | result(lineNumber) := tempWord; 33 | lineNumber := lineNumber + 1; 34 | end loop; 35 | return result; 36 | end function; 37 | 38 | signal memory : memory_type := getFile("../../../../prog.bin"); 39 | 40 | begin 41 | dataOut <= memory(to_integer(unsigned(addr))) when en = '1' else 42 | (others => 'Z'); 43 | end Behavioral; 44 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/RegisterBank.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.NUMERIC_STD.ALL; 5 | 6 | 7 | entity RegisterBank is 8 | Generic( addr_width : integer := 3; 9 | data_width : integer := 8); 10 | Port ( clk : in STD_LOGIC; 11 | rst : in STD_LOGIC; 12 | reg_out : in STD_LOGIC_VECTOR(addr_width-1 downto 0); 13 | reg_load : in STD_LOGIC_VECTOR(addr_width-1 downto 0); 14 | mem_addr : out STD_LOGIC_VECTOR(7 downto 0); 15 | instr2CU : out STD_LOGIC_VECTOR(7 downto 0); 16 | instr2CU2 : out STD_LOGIC_VECTOR(7 downto 0); 17 | aluBusX : out STD_LOGIC_VECTOR(data_width-1 downto 0); 18 | aluBusY : out STD_LOGIC_VECTOR(data_width-1 downto 0); 19 | dataBus : inout STD_LOGIC_VECTOR (data_width-1 downto 0)); 20 | end RegisterBank; 21 | 22 | architecture Behavioral of RegisterBank is 23 | 24 | Component PIPORegister 25 | Generic(data_width : integer := 8); 26 | Port ( clk : in STD_LOGIC; 27 | rst : in STD_LOGIC; 28 | en : in STD_LOGIC; 29 | load : in STD_LOGIC; 30 | q : out STD_LOGIC_VECTOR (data_width-1 downto 0); 31 | dataBus : inout STD_LOGIC_VECTOR (data_width-1 downto 0)); 32 | end Component; 33 | 34 | --Choosing which register to put on the bus, in any given time 35 | --value 000 unables all of them 36 | signal en_instr1, en_instr2, en_x, en_y, en_mem, en_hi, en_lo : STD_LOGIC; 37 | signal load_instr1, load_instr2, load_x, load_y, load_mem, load_hi, load_lo : STD_LOGIC; 38 | 39 | constant REG_NOOP_ADDR : STD_LOGIC_VECTOR(2 downto 0) := STD_LOGIC_VECTOR(to_unsigned(0, 3)); 40 | constant REG_INSTR1_ADDR : STD_LOGIC_VECTOR(2 downto 0) := STD_LOGIC_VECTOR(to_unsigned(1, 3)); 41 | constant REG_INSTR2_ADDR : STD_LOGIC_VECTOR(2 downto 0) := STD_LOGIC_VECTOR(to_unsigned(2, 3)); 42 | constant REG_X_ADDR : STD_LOGIC_VECTOR(2 downto 0) := STD_LOGIC_VECTOR(to_unsigned(3, 3)); 43 | constant REG_Y_ADDR : STD_LOGIC_VECTOR(2 downto 0) := STD_LOGIC_VECTOR(to_unsigned(4, 3)); 44 | constant REG_MEM_ADDR : STD_LOGIC_VECTOR(2 downto 0) := STD_LOGIC_VECTOR(to_unsigned(5, 3)); 45 | constant REG_HI_ADDR : STD_LOGIC_VECTOR(2 downto 0) := STD_LOGIC_VECTOR(to_unsigned(6, 3)); 46 | constant REG_LO_ADDR : STD_LOGIC_VECTOR(2 downto 0) := STD_LOGIC_VECTOR(to_unsigned(7, 3)); 47 | begin 48 | 49 | --instruction register 1, OPCODE argument, shares bus with register argument 50 | reg_op : PIPORegister 51 | generic map(data_width => 5) 52 | port map(clk => clk, rst => rst, en => en_instr1, load => load_instr1, q => instr2CU(7 downto 3), dataBus => dataBus(7 downto 3)); 53 | 54 | --instruction register 1, REGISTER argument, shares bus with opcode argument 55 | reg_instr_reg : PIPORegister 56 | generic map(data_width => 3) 57 | port map(clk => clk, rst => rst, en => en_instr1, load => load_instr1, q => instr2CU(2 downto 0), dataBus => dataBus(2 downto 0)); 58 | 59 | --instruction register 2, ADDRESS argument 60 | reg_instr_addr : PIPORegister 61 | generic map(data_width => 8) 62 | port map(clk => clk, rst => rst, en => en_instr2, load => load_instr2, q => instr2CU2, dataBus => dataBus); 63 | 64 | --X register 65 | reg_x : PIPORegister 66 | port map(clk => clk, rst => rst, en => en_x, load => load_x, q => aluBusX, dataBus => dataBus); 67 | 68 | --Y register 69 | reg_y : PIPORegister 70 | port map(clk => clk, rst => rst, en => en_y, load => load_y, q => aluBusY, dataBus => dataBus); 71 | 72 | --MemoryAddress register 73 | reg_mem : PIPORegister 74 | generic map(data_width => 8) 75 | port map(clk => clk, rst => rst, en => en_mem, load => load_mem, q => mem_addr, dataBus => dataBus); 76 | 77 | --HI register 78 | reg_hi : PIPORegister 79 | generic map(data_width => 8) 80 | port map(clk => clk, rst => rst, en => en_hi, load => load_hi, q => open, dataBus => dataBus); 81 | 82 | --LO register 83 | reg_lo : PIPORegister 84 | generic map(data_width => 8) 85 | port map(clk => clk, rst => rst, en => en_lo, load => load_lo, q => open, dataBus => dataBus); 86 | 87 | 88 | --Logic for enabling either loading or output from the correct register 89 | en_instr1 <= '1' when reg_out = REG_INSTR1_ADDR else 90 | '0'; 91 | load_instr1 <= '1' when reg_load = REG_INSTR1_ADDR else 92 | '0'; 93 | 94 | en_instr2 <= '1' when reg_out = REG_INSTR2_ADDR else 95 | '0'; 96 | load_instr2 <= '1' when reg_load = REG_INSTR2_ADDR else 97 | '0'; 98 | 99 | en_x <= '1' when reg_out = REG_X_ADDR else 100 | '0'; 101 | load_x <= '1' when reg_load = REG_X_ADDR else 102 | '0'; 103 | 104 | en_y <= '1' when reg_out = REG_Y_ADDR else 105 | '0'; 106 | load_y <= '1' when reg_load = REG_Y_ADDR else 107 | '0'; 108 | en_mem <= '1' when reg_out = REG_MEM_ADDR else 109 | '0'; 110 | load_mem <= '1' when reg_load = REG_MEM_ADDR else 111 | '0'; 112 | en_hi <= '1' when reg_out = REG_HI_ADDR else 113 | '0'; 114 | load_hi <= '1' when reg_load = REG_HI_ADDR else 115 | '0'; 116 | en_lo <= '1' when reg_out = REG_LO_ADDR else 117 | '0'; 118 | load_lo <= '1' when reg_load = REG_LO_ADDR else 119 | '0'; 120 | end Behavioral; 121 | 122 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/SixteenBitDisplay.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | 5 | 6 | entity SixteenBitDisplay is 7 | Port ( sw : in STD_LOGIC_VECTOR (15 downto 0); 8 | clk : in STD_LOGIC; 9 | rst : in STD_LOGIC; 10 | seg : out STD_LOGIC_VECTOR (7 downto 0); 11 | an : out STD_LOGIC_VECTOR(3 downto 0)); 12 | end SixteenBitDisplay; 13 | 14 | architecture Behavioral of SixteenBitDisplay is 15 | 16 | Component HexToSseg 17 | Port ( hex : in STD_LOGIC_VECTOR (3 downto 0); 18 | seg : out STD_LOGIC_VECTOR (7 downto 0)); 19 | end Component; 20 | 21 | Component SixteenToFourMux 22 | Port ( x : in STD_LOGIC_VECTOR (15 downto 0); 23 | sel : in STD_LOGIC_VECTOR (1 downto 0); 24 | y : out STD_LOGIC_VECTOR (3 downto 0)); 25 | end Component; 26 | 27 | signal sel : STD_LOGIC_VECTOR(1 downto 0); 28 | signal output : STD_LOGIC_VECTOR(3 downto 0); 29 | type states is (d0, d1, d2, d3); 30 | signal d_reg, d_next : states := d0; 31 | signal counter : integer range 0 to 100000 := 0; 32 | 33 | begin 34 | process(clk, rst) 35 | begin 36 | if(rst = '1') then 37 | d_reg <= d0; 38 | elsif(rising_edge(clk)) then 39 | if(counter = 0) then 40 | d_reg <= d_next; 41 | end if; 42 | counter <= counter + 1; 43 | end if; 44 | end process; 45 | 46 | process(d_reg) 47 | begin 48 | case d_reg is 49 | when d0 => 50 | sel <= "00"; 51 | an <= "1110"; 52 | d_next <= d1; 53 | when d1 => 54 | sel <= "01"; 55 | an <= "1101"; 56 | d_next <= d2; 57 | when d2 => 58 | sel <= "10"; 59 | an <= "1011"; 60 | d_next <= d3; 61 | when d3 => 62 | sel <= "11"; 63 | an <= "0111"; 64 | d_next <= d0; 65 | end case; 66 | end process; 67 | 68 | mux : SixteenToFourMux 69 | port map(x => sw, sel => sel, y => output); 70 | 71 | hexToSsegComp : HexToSseg 72 | port map(hex => output, seg => seg); 73 | 74 | end Behavioral; 75 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/SixteenToFourMux.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | 5 | entity SixteenToFourMux is 6 | Port ( x : in STD_LOGIC_VECTOR (15 downto 0); 7 | sel : in STD_LOGIC_VECTOR (1 downto 0); 8 | y : out STD_LOGIC_VECTOR (3 downto 0)); 9 | end SixteenToFourMux; 10 | 11 | architecture Behavioral of SixteenToFourMux is 12 | 13 | begin 14 | y <= x(3 downto 0) when sel = "00" else 15 | x(7 downto 4) when sel = "01" else 16 | x(11 downto 8) when sel = "10" else 17 | x(15 downto 12); 18 | end Behavioral; 19 | -------------------------------------------------------------------------------- /src/computer/Computer8Bit.srcs/sources_1/new/StackPointer.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | 5 | use IEEE.NUMERIC_STD.ALL; 6 | 7 | 8 | entity StackPointer is 9 | generic(N : integer := 4; 10 | M : integer := 16); 11 | Port ( clk : in STD_LOGIC; 12 | rst : in STD_LOGIC; 13 | en : in STD_LOGIC; 14 | inc : in STD_LOGIC; 15 | dec : in STD_LOGIC; 16 | q : out STD_LOGIC_VECTOR (7 downto 0)); 17 | end StackPointer; 18 | 19 | architecture Behavioral of StackPointer is 20 | 21 | signal r_reg, r_next, r_prev : unsigned(N-1 downto 0) := (others => '0'); 22 | 23 | begin 24 | 25 | process(rst, clk) 26 | begin 27 | if(rst = '1') then 28 | r_reg <= (others => '0'); 29 | elsif(rising_edge(clk)) then 30 | if(inc = '1') then 31 | r_reg <= r_next; 32 | elsif(dec = '1') then 33 | r_reg <= r_prev; 34 | end if; 35 | end if; 36 | end process; 37 | 38 | 39 | --Next state logic 40 | r_next <= (others => '0') when r_reg = M-1 else 41 | r_reg + 1; 42 | 43 | r_prev <= (others => '1') when r_reg = 0 else 44 | r_reg - 1; 45 | 46 | q <= "1000" & STD_LOGIC_VECTOR(r_reg) when en = '1' else 47 | (others => 'Z'); 48 | 49 | end Behavioral; 50 | -------------------------------------------------------------------------------- /src/computer/Computer_tb_behav.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | clk 24 | clk 25 | 26 | 27 | rst 28 | rst 29 | 30 | 31 | y 32 | y 33 | 34 | 35 | clk_period 36 | clk_period 37 | 38 | 39 | dataBus[7:0] 40 | dataBus[7:0] 41 | 42 | 43 | addrBus[7:0] 44 | addrBus[7:0] 45 | 46 | 47 | romEnable 48 | romEnable 49 | 50 | 51 | mem_en 52 | mem_en 53 | 54 | 55 | state_reg 56 | state_reg 57 | 58 | 59 | q[7:0] 60 | q[7:0] 61 | 62 | 63 | load 64 | load 65 | 66 | 67 | reg_load[2:0] 68 | reg_load[2:0] 69 | 70 | 71 | q[7:0] 72 | q[7:0] 73 | 74 | 75 | r_reg[7:0] 76 | r_reg[7:0] 77 | 78 | 79 | dataBus[7:0] 80 | dataBus[7:0] 81 | 82 | 83 | reg_load[2:0] 84 | reg_load[2:0] 85 | 86 | 87 | reg_load[2:0] 88 | reg_load[2:0] 89 | 90 | 91 | load_mem 92 | load_mem 93 | 94 | 95 | reg[7:0] 96 | reg[7:0] 97 | 98 | 99 | en 100 | en 101 | 102 | 103 | dataOut[7:0] 104 | dataOut[7:0] 105 | 106 | 107 | dataOut[7:0] 108 | dataOut[7:0] 109 | 110 | 111 | addr[6:0] 112 | addr[6:0] 113 | 114 | 115 | en 116 | en 117 | 118 | 119 | romEnable 120 | romEnable 121 | 122 | 123 | ramEnable 124 | ramEnable 125 | 126 | 127 | mem_en 128 | mem_en 129 | 130 | 131 | addrBus[7:0] 132 | addrBus[7:0] 133 | 134 | 135 | mem_en 136 | mem_en 137 | 138 | 139 | mem_out 140 | mem_out 141 | 142 | 143 | pc_out 144 | pc_out 145 | 146 | 147 | en 148 | en 149 | 150 | 151 | load_mem 152 | load_mem 153 | 154 | 155 | load 156 | load 157 | 158 | 159 | reg[7:0] 160 | reg[7:0] 161 | 162 | 163 | 164 | dataOut[7:0] 165 | dataOut[7:0] 166 | 167 | 168 | 169 | en 170 | en 171 | 172 | 173 | -------------------------------------------------------------------------------- /src/computer/Computer_tb_behav1.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | clk 30 | clk 31 | 32 | 33 | rst 34 | rst 35 | 36 | 37 | clk_period 38 | clk_period 39 | 40 | 41 | FullPathName 42 | r_reg[7:0] 43 | r_reg[7:0] 44 | 45 | 46 | dataBus[7:0] 47 | dataBus[7:0] 48 | 49 | 50 | 51 | addrBus[7:0] 52 | addrBus[7:0] 53 | 54 | 55 | romEnable 56 | romEnable 57 | 58 | 59 | ramEnable 60 | ramEnable 61 | 62 | 63 | mem_en 64 | mem_en 65 | 66 | 67 | cpu_rw 68 | cpu_rw 69 | 70 | 71 | load 72 | load 73 | 74 | 75 | clk 76 | clk 77 | 78 | 79 | memory[0:127][7:0] 80 | memory[0:127][7:0] 81 | 82 | 83 | state_reg 84 | state_reg 85 | 86 | 87 | instruction_stage 88 | instruction_stage 89 | 90 | 91 | pc_load 92 | pc_load 93 | 94 | 95 | reg_out[2:0] 96 | reg_out[2:0] 97 | 98 | 99 | x[7:0] 100 | x[7:0] 101 | 102 | 103 | y[7:0] 104 | y[7:0] 105 | 106 | 107 | Z[7:0] 108 | Z[7:0] 109 | 110 | 111 | mul_temp[15:0] 112 | mul_temp[15:0] 113 | 114 | 115 | temp[7:0] 116 | temp[7:0] 117 | 118 | 119 | reg[7:0] 120 | reg[7:0] 121 | 122 | 123 | reg[7:0] 124 | reg[7:0] 125 | 126 | 127 | reg_out[2:0] 128 | reg_out[2:0] 129 | 130 | 131 | reg_load[2:0] 132 | reg_load[2:0] 133 | 134 | 135 | instr2[7:0] 136 | instr2[7:0] 137 | 138 | 139 | max_tick 140 | max_tick 141 | 142 | 143 | sw[15:0] 144 | sw[15:0] 145 | 146 | 147 | an[3:0] 148 | an[3:0] 149 | 150 | 151 | 152 | seg[7:0] 153 | seg[7:0] 154 | 155 | 156 | -------------------------------------------------------------------------------- /src/computer/Computer_tb_behav2.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | clk 24 | clk 25 | 26 | 27 | rst 28 | rst 29 | 30 | 31 | seg[7:0] 32 | seg[7:0] 33 | 34 | 35 | an[3:0] 36 | an[3:0] 37 | 38 | 39 | JB[7:0] 40 | JB[7:0] 41 | 42 | 43 | lcd_rs 44 | lcd_rs 45 | 46 | 47 | lcd_rw 48 | lcd_rw 49 | 50 | 51 | lcd_en 52 | lcd_en 53 | 54 | 55 | clk_period 56 | clk_period 57 | 58 | 59 | dataBus[7:0] 60 | dataBus[7:0] 61 | 62 | 63 | addrBus[7:0] 64 | addrBus[7:0] 65 | 66 | 67 | state_reg 68 | state_reg 69 | 70 | 71 | instr[7:0] 72 | instr[7:0] 73 | 74 | 75 | 76 | instr2[7:0] 77 | instr2[7:0] 78 | 79 | 80 | reg[7:0] 81 | reg[7:0] 82 | 83 | 84 | reg[7:0] 85 | reg[7:0] 86 | 87 | 88 | load_a 89 | load_a 90 | 91 | 92 | load_b 93 | load_b 94 | 95 | 96 | reg_a[7:0] 97 | reg_a[7:0] 98 | 99 | 100 | reg_b[7:0] 101 | reg_b[7:0] 102 | 103 | 104 | Z_a[7:0] 105 | Z_a[7:0] 106 | 107 | 108 | Z_b[7:0] 109 | Z_b[7:0] 110 | 111 | 112 | r_reg[7:0] 113 | r_reg[7:0] 114 | 115 | 116 | Z[7:0] 117 | Z[7:0] 118 | 119 | 120 | en 121 | en 122 | 123 | 124 | -------------------------------------------------------------------------------- /src/prog.bin: -------------------------------------------------------------------------------- 1 | 00000000 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00000000 24 | 00000000 25 | 00000000 26 | 00000000 27 | 00000000 28 | 00000000 29 | 00000000 30 | 00000000 31 | 00000000 32 | 00000000 33 | 00000000 34 | 00000000 35 | 00000000 36 | 00000000 37 | 00000000 38 | 00000000 39 | 00000000 40 | 00000000 41 | 00000000 42 | 00000000 43 | 00000000 44 | 00000000 45 | 00000000 46 | 00000000 47 | 00000000 48 | 00000000 49 | 00000000 50 | 00000000 51 | 00000000 52 | 00000000 53 | 00000000 54 | 00000000 55 | 00000000 56 | 00000000 57 | 00000000 58 | 00000000 59 | 00000000 60 | 00000000 61 | 00000000 62 | 00000000 63 | 00000000 64 | 00000000 65 | 00000000 66 | 00000000 67 | 00000000 68 | 00000000 69 | 00000000 70 | 00000000 71 | 00000000 72 | 00000000 73 | 00000000 74 | 00000000 75 | 00000000 76 | 00000000 77 | 00000000 78 | 00000000 79 | 00000000 80 | 00000000 81 | 00000000 82 | 00000000 83 | 00000000 84 | 00000000 85 | 00000000 86 | 00000000 87 | 00000000 88 | 00000000 89 | 00000000 90 | 00000000 91 | 00000000 92 | 00000000 93 | 00000000 94 | 00000000 95 | 00000000 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00000000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00000000 129 | -------------------------------------------------------------------------------- /src/programs/add.asm: -------------------------------------------------------------------------------- 1 | .org #$02 ; place following code at address 0x02 2 | ldw xr inta ; load contents of address 001E into register X 3 | ldw yr intb ; load contents of address 001F into register Y 4 | add xr ; add contents of x and y register. Place result in x register 5 | stw xr #$F0 ; store the contents of x register at address 0xF0 6 | loop: 7 | nop ; do nothing 8 | jmp loop ; jump to label 'loop' 9 | 10 | 11 | .org #$1E ; place following code at address 0x1E 12 | inta: 13 | .word #05 ; place literal 0x5 at this address 14 | intb: 15 | .word 15 ; place literal 15 at this address 16 | -------------------------------------------------------------------------------- /src/programs/fullTest.asm: -------------------------------------------------------------------------------- 1 | ;.org #$0002 ; place all this code at address 0006 2 | ldw xr intx ; load address 001E into register X 3 | ldw yr inty ; load address 001F into register Y 4 | addu xr 5 | subu yr 6 | and xr ; add x and y reg and put in x 7 | or yr ; 8 | not yr 9 | xor yr 10 | xnor yr 11 | sll yr 12 | srl xr 13 | mul 14 | div 15 | inl #FF 16 | ini #1 17 | stw xr #$F0 ; 18 | ldi xr #FF ; place value FF into X reg 19 | ldi yr 99 ; place 99 in decimal into y reg 20 | subu xr ; substitute 21 | beq func ; jump to function 22 | bgt func 23 | bge func 24 | loop: 25 | nop 26 | mov xr yr 27 | jmp loop 28 | 29 | 30 | .org #$004E 31 | intx: 32 | .word #05 ; place 5 in address 33 | inty: 34 | .word 15 ; place 15 in address 35 | char: 36 | .word 'L' ; place letter L in address 37 | 38 | 39 | func: 40 | psh xr 41 | ldw xr intx 42 | pul xr 43 | ret 44 | -------------------------------------------------------------------------------- /src/programs/helloWorld.asm: -------------------------------------------------------------------------------- 1 | 2 | ; set cursor stuff: 3 | 4 | ldi xr #0E ; Display on, cursor on, blink off : 00001110 5 | stw xr #FE ; store to port B 6 | 7 | ldi xr #0 ; clear RS/RW/E bits 8 | stw xr #FF ; store to port A 9 | 10 | ldw xr enable ; enable write to lcd 11 | stw xr #FF ; store to port A 12 | 13 | ldi xr #0 ; clear RS/RW/E bits 14 | stw xr #FF ; store to port A 15 | 16 | 17 | ; entry mode set 18 | 19 | ldi xr #06 ; Increment and shift curosr, don't shift display, 00000110 20 | stw xr #FE ; store to port B 21 | 22 | ldi xr #0 ; clear RS/RW/E bits 23 | stw xr #FF ; store to port A 24 | 25 | ldw xr enable ; enable write to lcd 26 | stw xr #FF ; store to port A 27 | 28 | ldi xr #0 ; clear RS/RW/E bits 29 | stw xr #FF ; store to port A 30 | 31 | ; write Hello,world to lcd 32 | ldw xr charH ; 33 | stw xr #FE ; store to port B 34 | jmp writeChar 35 | 36 | ldw xr chari ; 37 | stw xr #FE ; store to port B 38 | jmp writeChar 39 | 40 | ldw xr char, ; 41 | stw xr #FE ; store to port B 42 | jmp writeChar 43 | 44 | ldw xr charW ; 45 | stw xr #FE ; store to port B 46 | jmp writeChar 47 | 48 | ldw xr charo ; 49 | stw xr #FE ; store to port B 50 | jmp writeChar 51 | 52 | ldw xr charr ; 53 | stw xr #FE ; store to port B 54 | jmp writeChar 55 | 56 | ldw xr charl ; 57 | stw xr #FE ; store to port B 58 | jmp writeChar 59 | 60 | ldw xr chard 61 | stw xr #FE ; store to port B 62 | jmp writeChar 63 | 64 | ldw xr char! 65 | stw xr #FE ; store to port B 66 | jmp writeChar 67 | 68 | loop: 69 | jmp loop 70 | 71 | writeChar: 72 | ldw xr rs ; set register select 73 | stw xr #FF ; store to port A 74 | ldw xr enrs ; enable write to lcd 75 | stw xr #FF ; store to port A 76 | 77 | ldw xr rs ; clear RS/RW/E bits 78 | stw xr #FF ; store to port A 79 | 80 | ret 81 | 82 | 83 | 84 | 85 | .org #$70 ; place following code at address 0x1E 86 | porta: 87 | .word #FF ; place literal 0x5 at this address 88 | portb: 89 | .word #FE ; place literal 15 at this address 90 | enable: 91 | .word #80 ; store 10000000 92 | rw: 93 | .word #40 ; store 01000000 94 | rs: 95 | .word #20 ; store 00100000 96 | enrs: 97 | .word #A0 98 | charH: 99 | .word 'H' 100 | chari: 101 | .word 'i' 102 | charl: 103 | .word 'l' 104 | char,: 105 | .word ',' 106 | charW: 107 | .word 'W' 108 | charo: 109 | .word 'o' 110 | charr: 111 | .word 'r' 112 | chard: 113 | .word 'd' 114 | char!: 115 | .word '!' 116 | -------------------------------------------------------------------------------- /src/programs/mul.asm: -------------------------------------------------------------------------------- 1 | .org #$02 ; place following code at address 0x02 2 | ldw xr inta ; load contents of address 001E into register X 3 | ldw yr intb ; load contents of address 001F into register Y 4 | mul ; multiplies x and y. Places result in hi and lo reg. 5 | stw hi #$F0 ; store upper bits of result at address 0xF0 6 | stw lo #$F1 ; store lower bits of result at address 0xF1 7 | loop: 8 | nop ; do nothing 9 | jmp loop ; jump to label 'loop' 10 | 11 | 12 | .org #$1E ; place following code at address 0x1E 13 | inta: 14 | .word #05 ; place literal 0x5 at this address 15 | intb: 16 | .word 15 ; place literal 15 at this address 17 | -------------------------------------------------------------------------------- /src/programs/printFib.asm: -------------------------------------------------------------------------------- 1 | ; set cursor stuff: 2 | ldi xr #0E ; Display on, cursor on, blink off : 00001110 3 | jmp writeSet 4 | 5 | ; entry mode set 6 | ldi xr #06 ; Increment and shift curosr, don't shift display, 00000110 7 | jmp writeSet 8 | 9 | ; write fib 10 | ldi xr 'F' ; print F 11 | jmp writeChar 12 | ldi xr 'i' ; print i 13 | jmp writeChar 14 | ldi xr 'b' ; print b 15 | jmp writeChar 16 | 17 | ; load initial values and print them 18 | ldi xr #0 ; load 0 19 | stw xr #90 ; store in addr1 20 | ldw yr ascii 21 | addu xr ; add ascii offset 22 | jmp writeChar ; print 0 23 | 24 | ldw xr sep ; load and print comma 25 | jmp writeChar 26 | 27 | ldi xr #1 ; load 1 28 | stw xr #91 29 | ldw yr ascii 30 | addu xr ; add ascii offset 31 | jmp writeChar ; print 1 32 | 33 | ldw xr sep ; load and print comma 34 | jmp writeChar 35 | 36 | fib: 37 | ldw xr #$90 ; load values, add and store result 38 | ldw yr #$91 39 | stw yr #$90 40 | addu xr 41 | stw xr #$91 42 | 43 | ldi yr #9 ; Check if val is bigger than 9, if so exit 44 | bgt loop 45 | 46 | ldw yr ascii ; Add ascii offset 47 | addu xr 48 | 49 | jmp writeChar 50 | 51 | ldw xr sep ; load and print comma 52 | jmp writeChar 53 | 54 | jmp fib 55 | 56 | writeSet: 57 | stw xr #FE ; store to port B 58 | ldi xr #0 ; clear RS/RW/E bits 59 | stw xr #FF ; store to port A 60 | ldw xr enable ; enable write to lcd 61 | stw xr #FF ; store to port A 62 | ldi xr #0 ; clear RS/RW/E bits 63 | stw xr #FF ; store to port A 64 | 65 | ret 66 | 67 | 68 | writeChar: 69 | stw xr #FE ; store to port B 70 | ldw xr rs ; set register select 71 | stw xr #FF ; store to port A 72 | ldw xr enrs ; enable write to lcd 73 | stw xr #FF ; store to port A 74 | ldw xr rs ; clear RS/RW/E bits 75 | stw xr #FF ; store to port A 76 | 77 | ret 78 | 79 | 80 | loop: 81 | jmp writeSet ; 82 | jmp loop ; loop forever 83 | 84 | 85 | .org #$78 ; place following code at address 0x1E 86 | porta: 87 | .word #FF ; place literal 0x5 at this address 88 | portb: 89 | .word #FE ; place literal 15 at this address 90 | enable: 91 | .word #80 ; store 10000000 92 | rw: 93 | .word #40 ; store 01000000 94 | rs: 95 | .word #20 ; store 00100000 96 | enrs: 97 | .word #A0 98 | ascii: 99 | .word #30 ; 100 | sep: 101 | .word ',' 102 | --------------------------------------------------------------------------------