├── LICENSE ├── README.md ├── corescore.core ├── corescore.png ├── corescore.svg ├── data ├── agilex5_dk-a5e065bb32aes1.tcl ├── alhambra_II.pcf ├── arty_a7.xdc ├── chameleon96 │ ├── CV_96.v │ ├── HPS.sv │ ├── chain1.cdf │ ├── chameleon96.sdc │ └── pinmap.tcl ├── cisco-hwic-3g-cdma.sdc ├── cisco-hwic-3g-cdma.tcl ├── cmod_a7.xdc ├── colorlight_5a75b.lpf ├── cyc1000.sdc ├── cyc1000.tcl ├── de0_nano.sdc ├── de0_nano.tcl ├── de10_nano.sdc ├── de10_nano.tcl ├── de5_net.sdc ├── de5_net.tcl ├── deca.sdc ├── deca.tcl ├── ebaz4205.xdc ├── ep2c5t144_devboard.sdc ├── ep2c5t144_devboard.tcl ├── fpc_iii.lpf ├── genesys2.xdc ├── go_board.pcf ├── haps_dx7.xdc ├── hpc_k7.xdc ├── hpc_ku.xdc ├── hx8k.pcf ├── icebreaker.pcf ├── icestick.pcf ├── icesugar.pcf ├── intel_a10gx_devkit.sdc ├── intel_a10gx_devkit.tcl ├── intel_agilex7.sdc ├── intel_agilex7.tcl ├── intel_cyc10lp_devkit.sdc ├── intel_cyc10lp_devkit.tcl ├── intel_dk-dev-agf014ea.tcl ├── intel_dk-si-agi027fb.tcl ├── intel_dk-si-agi040fes.tcl ├── intel_max10_devkit.sdc ├── intel_max10_devkit.tcl ├── intel_s10gx_devkit.sdc ├── intel_s10gx_devkit.tcl ├── intel_s10gx_pll.ip ├── kc705.xdc ├── libero-post-instructions.txt ├── marble.xdc ├── max1000.sdc ├── max1000.tcl ├── nexys_a7.xdc ├── nexys_video.xdc ├── polarfire_eval.pdc ├── sockit.sdc ├── sockit.tcl ├── thunderfjord.tcl ├── tinyfpga_bx.pcf ├── tinyfpga_bx.py ├── ulx3s.lpf ├── upduino2.pcf ├── vcu118.xdc ├── vcu128.xdc ├── vivado_waive.tcl ├── vu19p.xdc ├── xyloni.isf └── zcu106.xdc ├── rtl ├── arty_a7_clock_gen.v ├── axis2wb.v ├── base.v ├── chameleon96_clock_gen.v ├── cisco_hwic_3g_cdma_clock_gen.v ├── cmod_a7_clock_gen.v ├── corescore_alhambra_II.v ├── corescore_arty_a7.v ├── corescore_chameleon96.v ├── corescore_cisco_hwic_3g_cdma.v ├── corescore_cmod_a7.v ├── corescore_colorlight.v ├── corescore_colorlight_clock_gen.v ├── corescore_cyc1000.v ├── corescore_de0_nano.v ├── corescore_de10_nano.v ├── corescore_de5_net.v ├── corescore_deca.v ├── corescore_ebaz4205.v ├── corescore_ep2c5t144_devboard.v ├── corescore_fpc_iii.v ├── corescore_fpc_iii_clock_gen.v ├── corescore_generic.v ├── corescore_genesys2.v ├── corescore_go_board.v ├── corescore_haps_dx7.v ├── corescore_haps_dx7_clock_gen.v ├── corescore_hpc_k7.v ├── corescore_hpc_ku.v ├── corescore_hx8k.v ├── corescore_icebreaker.v ├── corescore_icestick.v ├── corescore_icesugar.v ├── corescore_intel_a10gx_devkit.v ├── corescore_intel_agilex7.v ├── corescore_intel_cyc10lp_devkit.v ├── corescore_intel_max10_devkit.v ├── corescore_intel_s10gx_devkit.v ├── corescore_kc705.v ├── corescore_kc705_clock_gen.v ├── corescore_marble.v ├── corescore_max1000.v ├── corescore_nexys_a7.v ├── corescore_nexys_video.v ├── corescore_polarfire.v ├── corescore_polarfire_eval_clock_gen.v ├── corescore_sockit.v ├── corescore_storeypeak.v ├── corescore_tinyfpga_bx.v ├── corescore_ulx3s.v ├── corescore_ulx3s_clock_gen.v ├── corescore_upduino2.v ├── corescore_vcu118.v ├── corescore_vcu118_clock_gen.v ├── corescore_vcu128.v ├── corescore_vcu128_clock_gen.v ├── corescore_vu19p.v ├── corescore_vu19p_clock_gen.v ├── corescore_xyloni.v ├── corescore_zcu106.v ├── corescore_zcu106_clock_gen.v ├── cyc1000_clock_gen.v ├── de0_nano_clock_gen.v ├── de5_net_clock_gen.v ├── ebaz4205_clock_gen.v ├── ecppll.v ├── emitter.v ├── emitter_mux.v ├── emitter_uart.v ├── ep2c5t144_devboard_clock_gen.v ├── genesys2_clock_gen.v ├── hpc_k7_clock_gen.v ├── hpc_ku_clock_gen.v ├── intel_a10gx_devkit_clock_gen.v ├── intel_cyc10lp_devkit_clock_gen.v ├── intel_max10_devkit_clock_gen.v ├── max1000_clock_gen.v ├── nexys_a7_clock_gen.v ├── nexys_video_clock_gen.v ├── storeypeak_clock_gen.v └── wb2axis.v ├── sw ├── .gitignore ├── Makefile ├── corecount.py ├── corescorecore_gen.py ├── emitter.S ├── emitter.hex ├── link.ld ├── makehex.py ├── requirements.txt └── verilogwriter.py └── tb └── corescore_tb.cpp /LICENSE: -------------------------------------------------------------------------------- 1 | 2 | Apache License 3 | Version 2.0, January 2004 4 | http://www.apache.org/licenses/ 5 | 6 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 7 | 8 | 1. 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It tests how many [SERV](https://github.com/olofk/serv) cores that can be put into a particular FPGA. 6 | 7 | Some more background about CoreScore can be found in the [SERV introduction video](https://diode.zone/videos/watch/0230a518-e207-4cf6-b5e2-69cc09411013). 8 | 9 | Check out the [CoreScore World Ranking](https://corescore.store/)! 10 | 11 | ## Quick start 12 | 13 | 1. Install [FuseSoC](https://github.com/olofk/fusesoc) 14 | 15 | pip install fusesoc 16 | 17 | 2. Set up a workspace directory and get the FuseSoC base library 18 | 19 | mkdir workspace 20 | cd workspace 21 | fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores 22 | 23 | 3. Add CoreScore as a library in your workspace 24 | 25 | fusesoc library add corescore https://github.com/olofk/corescore 26 | 27 | 4. Check available corescore targets 28 | 29 | fusesoc core show corescore 30 | 31 | 5. Build one of the supported targets (cyc1000 is one of the currently supported cores) 32 | 33 | fusesoc run --target=cyc1000 corescore 34 | 35 | 6. If the board is connected it will be automatically programmed. Otherwise connect it and run `fusesoc run --run --target=cyc1000 corescore` to program without rebuilding 36 | 37 | 7. Run the corecount utility (Might need to adjust for the correct UART port) 38 | 39 | python3 fusesoc_libraries/corescore/sw/corecount.py /dev/ttyUSB0 40 | -------------------------------------------------------------------------------- /corescore.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/corescore/8e048f41d2ac7e393bcc32449de317e452aa7df6/corescore.png -------------------------------------------------------------------------------- /data/agilex5_dk-a5e065bb32aes1.tcl: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VERILOG_CU_MODE MFCU 2 | set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA" 3 | * 4 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 5 | set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)" 6 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 7 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 8 | 9 | set_global_assignment -name GENERATE_COMPRESSED_SOF ON 10 | set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF 11 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8" 12 | set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF 13 | set_global_assignment -name USE_CONF_DONE SDM_IO12 14 | set_global_assignment -name USE_HPS_COLD_RESET SDM_IO7 15 | set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ 16 | set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL 17 | 18 | set_global_assignment -name ERROR_ON_WARNINGS_PARSING_SDC_ON_RTL_CONSTRAINTS ON 19 | set_global_assignment -name ERROR_ON_WARNINGS_LOADING_SDC_ON_RTL_CONSTRAINTS ON 20 | set_global_assignment -name RTL_SDC_FILE src/corescore_0/data/intel_agilex7.sdc 21 | 22 | # Clock 23 | set_location_assignment PIN_D8 -to i_clk -comment IOBANK_6C 24 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk -entity veerwolf_agilex 25 | 26 | # Reset PB SW11 HPS_COLD_RESETn Bank 5B 3.3V 27 | set_location_assignment PIN_BM109 -to i_rstn -comment IOBANK_5B 28 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rstn -entity veerwolf_agilex 29 | -------------------------------------------------------------------------------- /data/alhambra_II.pcf: -------------------------------------------------------------------------------- 1 | set_io i_clk 49 2 | set_io o_uart_tx 61 3 | set_io locked_led 45 4 | -------------------------------------------------------------------------------- /data/arty_a7.xdc: -------------------------------------------------------------------------------- 1 | # Clock signal 2 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports i_clk ]; 3 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk ]; 4 | 5 | # USB-UART Interface 6 | set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx ]; 7 | 8 | # LEDs 9 | set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports q ]; -------------------------------------------------------------------------------- /data/chameleon96/CV_96.v: -------------------------------------------------------------------------------- 1 | 2 | module CV_96 ( 3 | output q, 4 | output uart_txd 5 | ); 6 | 7 | wire clk; 8 | 9 | HPS u0( 10 | .h2f_user0_clk( clk) //hps_0_h2f_user0_clock.clk 11 | ); 12 | 13 | 14 | corescore_chameleon96 u1 ( 15 | .i_clk ( clk ), 16 | .i_rst_n ( 1'b1), 17 | .q ( q ), 18 | .uart_txd( uart_txd ) 19 | ); 20 | 21 | 22 | endmodule 23 | 24 | 25 | 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /data/chameleon96/HPS.sv: -------------------------------------------------------------------------------- 1 | 2 | module HPS( 3 | output wire [1 - 1 : 0 ] h2f_rst_n 4 | ,output wire [1 - 1 : 0 ] h2f_user0_clk 5 | ); 6 | 7 | 8 | cyclonev_hps_interface_clocks_resets clocks_resets( 9 | .f2h_pending_rst_ack({ 10 | 1'b1 // 0:0 11 | }) 12 | ,.f2h_warm_rst_req_n({ 13 | 1'b1 // 0:0 14 | }) 15 | ,.f2h_dbg_rst_req_n({ 16 | 1'b1 // 0:0 17 | }) 18 | ,.h2f_rst_n({ 19 | h2f_rst_n[0:0] // 0:0 20 | }) 21 | ,.f2h_cold_rst_req_n({ 22 | 1'b1 // 0:0 23 | }) 24 | ,.h2f_user0_clk({ 25 | h2f_user0_clk[0:0] // 0:0 26 | }) 27 | ); 28 | 29 | 30 | cyclonev_hps_interface_dbg_apb debug_apb( 31 | .DBG_APB_DISABLE({ 32 | 1'b0 // 0:0 33 | }) 34 | ,.P_CLK_EN({ 35 | 1'b0 // 0:0 36 | }) 37 | ); 38 | 39 | 40 | cyclonev_hps_interface_tpiu_trace tpiu( 41 | .traceclk_ctl({ 42 | 1'b1 // 0:0 43 | }) 44 | ); 45 | 46 | 47 | cyclonev_hps_interface_boot_from_fpga boot_from_fpga( 48 | .boot_from_fpga_ready({ 49 | 1'b0 // 0:0 50 | }) 51 | ,.boot_from_fpga_on_failure({ 52 | 1'b0 // 0:0 53 | }) 54 | ,.bsel_en({ 55 | 1'b0 // 0:0 56 | }) 57 | ,.csel_en({ 58 | 1'b0 // 0:0 59 | }) 60 | ,.csel({ 61 | 2'b01 // 1:0 62 | }) 63 | ,.bsel({ 64 | 3'b001 // 2:0 65 | }) 66 | ); 67 | 68 | 69 | cyclonev_hps_interface_fpga2hps fpga2hps( 70 | .port_size_config({ 71 | 2'b11 // 1:0 72 | }) 73 | ); 74 | 75 | 76 | cyclonev_hps_interface_hps2fpga hps2fpga( 77 | .port_size_config({ 78 | 2'b11 // 1:0 79 | }) 80 | ); 81 | 82 | 83 | cyclonev_hps_interface_fpga2sdram f2sdram( 84 | .cfg_cport_rfifo_map({ 85 | 18'b000000000000000000 // 17:0 86 | }) 87 | ,.cfg_axi_mm_select({ 88 | 6'b000000 // 5:0 89 | }) 90 | ,.cfg_wfifo_cport_map({ 91 | 16'b0000000000000000 // 15:0 92 | }) 93 | ,.cfg_cport_type({ 94 | 12'b000000000000 // 11:0 95 | }) 96 | ,.cfg_rfifo_cport_map({ 97 | 16'b0000000000000000 // 15:0 98 | }) 99 | ,.cfg_port_width({ 100 | 12'b000000000000 // 11:0 101 | }) 102 | ,.cfg_cport_wfifo_map({ 103 | 18'b000000000000000000 // 17:0 104 | }) 105 | ); 106 | 107 | endmodule 108 | 109 | -------------------------------------------------------------------------------- /data/chameleon96/chain1.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Ign) 7 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 8 | P ActionCode(Cfg) 9 | Device PartName(5CSEBA6U19) Path("/home/jordi/bin/fusesoc/build/fusesoc_utils_blinky_1.1/chameleon96-quartus/") File("fusesoc_utils_blinky_1_1.sof") MfrSpec(OpMask(1)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /data/chameleon96/chameleon96.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (100 Mhz) 2 | create_clock -name "clk" -period 10.000ns [get_pins -compatibility_mode u0|clocks_resets|h2f_user0_clk] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/chameleon96/pinmap.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Clock / Reset 3 | # 4 | # set_location_assignment PIN_xxxx -to i_clk 5 | # No direct clock. Using internal HPS clock 6 | 7 | # 8 | # GPIO 9 | # 10 | # LED Y19 Yellow WIFI, Y20 Blue Bluetooth 11 | set_location_assignment PIN_Y19 -to q 12 | set_instance_assignment -name IO_STANDARD "2.5 V" -to q 13 | 14 | # FPGA_1V8_HPS_EXP_UART1_TXD_PIN_W14 Pin 5 Low speed connector (WHITE C96 USB/serial cable) Pin 1 GND 15 | set_location_assignment PIN_W14 -to uart_txd 16 | set_instance_assignment -name IO_STANDARD "1.8 V" -to uart_txd 17 | 18 | # No reset button wired to FPGA 19 | # set_location_assignment PIN_xxx -to i_rst_n 20 | 21 | -------------------------------------------------------------------------------- /data/cisco-hwic-3g-cdma.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (25 Mhz) 2 | create_clock -name "clk" -period 40.000 [get_ports {clk25}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/cisco-hwic-3g-cdma.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_L2 -to clk25 2 | set_location_assignment PIN_AA19 -to led0 3 | set_location_assignment PIN_N6 -to uart_drv_ena_ 4 | set_location_assignment PIN_P6 -to uart_drv_sd_ 5 | set_location_assignment PIN_D6 -to uart_txd 6 | set_location_assignment PIN_F4 -to uart_rxd 7 | set_location_assignment PIN_G6 -to uart_rts 8 | set_location_assignment PIN_H6 -to uart_cts 9 | 10 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" 11 | set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "cisco_hwic_3g_cdma_clock_gen:clock_gen|r[9]" 12 | 13 | -------------------------------------------------------------------------------- /data/cmod_a7.xdc: -------------------------------------------------------------------------------- 1 | # Clock signal 2 | set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports i_clk ]; 3 | create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports i_clk ]; 4 | 5 | # USB-UART Interface 6 | set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx ]; 7 | 8 | # LEDs 9 | set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports q ]; 10 | -------------------------------------------------------------------------------- /data/colorlight_5a75b.lpf: -------------------------------------------------------------------------------- 1 | LOCATE COMP "i_clk" SITE "P6"; 2 | IOBUF PORT "i_clk" PULLMODE=NONE IO_TYPE=LVCMOS33; 3 | FREQUENCY PORT "i_clk" 25.000 MHZ; 4 | 5 | LOCATE COMP "btn0" SITE "M13"; # BTN_PWRn (inverted logic) 6 | IOBUF PORT "btn0" PULLMODE=UP IO_TYPE=LVCMOS33; 7 | 8 | LOCATE COMP "o_uart_tx" SITE "M11"; # FPGA transmits to ftdi (J5) 9 | IOBUF PORT "o_uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 10 | -------------------------------------------------------------------------------- /data/cyc1000.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (12 Mhz) 2 | create_clock -name "clk" -period 83.333ns [get_ports {i_clk}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/cyc1000.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_M2 -to i_clk 2 | set_location_assignment PIN_M6 -to q 3 | set_location_assignment PIN_T7 -to o_uart_tx 4 | -------------------------------------------------------------------------------- /data/de0_nano.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (50 Mhz) 2 | create_clock -name "clk" -period 20.000ns [get_ports {i_clk}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/de0_nano.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_R8 -to i_clk 2 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk 3 | 4 | set_location_assignment PIN_A15 -to q 5 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q 6 | 7 | set_location_assignment PIN_D11 -to o_uart_tx 8 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to o_uart_tx 9 | 10 | set_location_assignment PIN_J15 -to i_rst_n 11 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_rst_n 12 | -------------------------------------------------------------------------------- /data/de10_nano.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (50 Mhz) 2 | create_clock -name "clk" -period 20.000ns [get_ports {i_clk}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/de10_nano.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_V11 -to i_clk 2 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk 3 | 4 | set_location_assignment PIN_W15 -to q 5 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q 6 | 7 | # GPIO0 Pin 1 8 | set_location_assignment PIN_Y15 -to uart_txd 9 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_txd 10 | 11 | #KEY[0] 12 | set_location_assignment PIN_AH17 -to i_rst_n 13 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_rst_n 14 | -------------------------------------------------------------------------------- /data/de5_net.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (50 Mhz) 2 | create_clock -name "clk" -period 20.000ns [get_ports {i_clk}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/de5_net.tcl: -------------------------------------------------------------------------------- 1 | # OSC_50_B3B - 50 MHz system clock 2 | set_instance_assignment -name IO_STANDARD "2.5 V" -to i_clk 3 | set_location_assignment PIN_AW35 -to i_clk 4 | 5 | # LED_BRACKET[0] 6 | set_location_assignment PIN_AH15 -to o_led_n 7 | set_instance_assignment -name IO_STANDARD "2.5 V" -to o_led_n 8 | set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to o_led_n 9 | set_instance_assignment -name SLEW_RATE 1 -to o_led_n ; # fast 10 | 11 | # CPU_RESET_n 12 | set_instance_assignment -name IO_STANDARD "2.5 V" -to i_rst_n 13 | set_location_assignment PIN_BC37 -to i_rst_n 14 | 15 | # 7-Segement decimal points 16 | set_instance_assignment -name IO_STANDARD "1.5 V" -to o_hex0_dp_n 17 | set_instance_assignment -name IO_STANDARD "1.5 V" -to o_hex1_dp_n 18 | set_location_assignment PIN_P8 -to o_hex0_dp_n 19 | set_location_assignment PIN_E9 -to o_hex1_dp_n 20 | set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to o_hex0_dp_n 21 | set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to o_hex1_dp_n 22 | set_instance_assignment -name SLEW_RATE 1 -to o_hex0_dp_n ; # fast 23 | set_instance_assignment -name SLEW_RATE 1 -to o_hex1_dp_n ; # fast 24 | 25 | # RS422 26 | set_instance_assignment -name IO_STANDARD "2.5 V" -to o_rs422_de ; # RS422_DE 27 | set_instance_assignment -name IO_STANDARD "2.5 V" -to o_uart_txd ; # RS422_DOUT 28 | set_instance_assignment -name IO_STANDARD "2.5 V" -to o_rs422_re_n ; # RS422_RE_n 29 | set_instance_assignment -name IO_STANDARD "2.5 V" -to o_rs422_te ; # RS422_TE 30 | set_location_assignment PIN_AG14 -to o_rs422_de ; # RS422_DE 31 | set_location_assignment PIN_AE17 -to o_uart_txd ; # RS422_DOUT 32 | set_location_assignment PIN_AF17 -to o_rs422_re_n ; # RS422_RE_n 33 | set_location_assignment PIN_AF16 -to o_rs422_te ; # RS422_TE 34 | set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to o_rs422_de 35 | set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to o_uart_txd 36 | set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to o_rs422_re_n 37 | set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to o_rs422_te 38 | set_instance_assignment -name SLEW_RATE 1 -to o_rs422_de ; # fast 39 | set_instance_assignment -name SLEW_RATE 1 -to o_uart_txd ; # fast 40 | set_instance_assignment -name SLEW_RATE 1 -to o_rs422_re_n ; # fast 41 | set_instance_assignment -name SLEW_RATE 1 -to o_rs422_te ; # fast 42 | 43 | -------------------------------------------------------------------------------- /data/deca.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (50 Mhz) 2 | create_clock -name "clk" -period 20.000ns [get_ports {i_clk}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/deca.tcl: -------------------------------------------------------------------------------- 1 | #MAX10_CLK2_50 3.3V 2 | set_location_assignment PIN_P11 -to i_clk 3 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk 4 | 5 | #LED[0] 6 | set_location_assignment PIN_C7 -to q 7 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q 8 | 9 | #P8 3 GPIO0_D0 (P8 1 GND) 10 | set_location_assignment PIN_W18 -to uart_txd 11 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_txd 12 | 13 | #KEY[0] 14 | set_location_assignment PIN_H21 -to i_rst_n 15 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_rst_n 16 | 17 | # Configuration mode that allows Memory Initialisation 18 | set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" 19 | 20 | -------------------------------------------------------------------------------- /data/ebaz4205.xdc: -------------------------------------------------------------------------------- 1 | ## 33.333 MHz Clock signal 2 | set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports i_clk]; 3 | create_clock -add -name sys_clk_pin -period 30.00 -waveform {0 5} [get_ports i_clk]; 4 | 5 | ## UART on DATA1_8 pin 6 | set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx]; 7 | -------------------------------------------------------------------------------- /data/ep2c5t144_devboard.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (50 Mhz) 2 | create_clock -name "clk" -period 20.000 [get_ports {clk50}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/ep2c5t144_devboard.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_17 -to clk50 2 | set_location_assignment PIN_3 -to led0 3 | set_location_assignment PIN_30 -to uart_txd 4 | 5 | -------------------------------------------------------------------------------- /data/fpc_iii.lpf: -------------------------------------------------------------------------------- 1 | LOCATE COMP "i_clk" SITE "P3"; 2 | IOBUF PORT "i_clk" IO_TYPE=LVCMOS33; 3 | FREQUENCY PORT "i_clk" 25 MHZ; 4 | 5 | LOCATE COMP "o_uart_tx" SITE "M1"; 6 | IOBUF PORT "o_uart_tx" IO_TYPE=LVCMOS33; 7 | -------------------------------------------------------------------------------- /data/genesys2.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports i_clk_n]; 2 | set_property -dict {PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports i_clk_p]; 3 | create_clock -add -name sys_clk_pin -period 5.00 [get_nets i_clk]; 4 | 5 | set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx]; 6 | -------------------------------------------------------------------------------- /data/go_board.pcf: -------------------------------------------------------------------------------- 1 | # 25 MHz clock input 2 | set_io i_clk 15 3 | 4 | # Onboard LEDs 1-4 5 | set_io o_led1 56 6 | set_io o_led2 57 7 | set_io o_led3 59 8 | set_io o_led4 60 9 | 10 | set_io o_uart_tx 74 11 | set_io o_pmod1 65 12 | -------------------------------------------------------------------------------- /data/haps_dx7.xdc: -------------------------------------------------------------------------------- 1 | ## Clock signal 2 | set_property -dict { PACKAGE_PIN AP26 IOSTANDARD LVCMOS15 } [get_ports i_clk_in]; 3 | create_clock -add -name sys_clk_pin -period 7.5001875 [get_nets i_clk]; # 133.33 MHz 4 | 5 | ## Clock enable 6 | set_property -dict { PACKAGE_PIN AM26 IOSTANDARD LVCMOS15 } [get_ports o_clk_en]; 7 | 8 | ## LED 9 | set_property -dict { PACKAGE_PIN A36 IOSTANDARD LVCMOS18 } [get_ports q]; 10 | 11 | ## UART 12 | set_property -dict { PACKAGE_PIN A35 IOSTANDARD LVCMOS18 } [get_ports o_uart_tx] 13 | 14 | set_property RAM_STYLE block [get_cells corescorecore/core_*/serving/ram/mem_reg] 15 | -------------------------------------------------------------------------------- /data/hpc_k7.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33 } [get_ports i_clk]; 2 | set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx] 3 | 4 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk]; 5 | -------------------------------------------------------------------------------- /data/hpc_ku.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict { PACKAGE_PIN D23 IOSTANDARD LVCMOS18 } [get_ports i_clk]; 2 | set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx] 3 | 4 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk]; 5 | -------------------------------------------------------------------------------- /data/hx8k.pcf: -------------------------------------------------------------------------------- 1 | set_io i_clk J3 2 | set_io o_uart_tx B12 3 | -------------------------------------------------------------------------------- /data/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | set_io i_clk 35 2 | set_io o_uart_tx 9 -------------------------------------------------------------------------------- /data/icestick.pcf: -------------------------------------------------------------------------------- 1 | set_io i_clk 21 2 | set_io o_uart_tx 8 3 | -------------------------------------------------------------------------------- /data/icesugar.pcf: -------------------------------------------------------------------------------- 1 | set_io g 41 2 | set_io b 39 3 | set_io r 40 4 | set_io o_uart_tx 6 5 | -------------------------------------------------------------------------------- /data/intel_a10gx_devkit.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (50 Mhz) 2 | create_clock -name "clk" -period 20.000 [get_ports {clk50}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/intel_a10gx_devkit.tcl: -------------------------------------------------------------------------------- 1 | # Base Clock 2 | set_location_assignment PIN_AU33 -to clk50 3 | 4 | # CPU_RESETn (S4 - From Schematic) 5 | set_location_assignment PIN_BD27 -to rstn 6 | 7 | -------------------------------------------------------------------------------- /data/intel_agilex7.sdc: -------------------------------------------------------------------------------- 1 | # input clock (100 Mhz) 2 | create_clock -name "clk100MHz" -period 10.0 [get_ports {i_clk}] 3 | # main system clock (16 Mhz) 4 | create_generated_clock -name "clk16MHz" -multiply_by 8 -divide_by 50 -source [get_ports {i_clk}] [get_nets {clk}] 5 | -------------------------------------------------------------------------------- /data/intel_agilex7.tcl: -------------------------------------------------------------------------------- 1 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 2 | 3 | set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to * -entity serv_state 4 | set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to * -entity serv_alu 5 | set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA" 6 | 7 | set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to i_clk -entity corescore_intel_agilex7 8 | set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to i_clk -entity corescore_intel_agilex7 9 | 10 | set_global_assignment -name ERROR_ON_WARNINGS_PARSING_SDC_ON_RTL_CONSTRAINTS ON 11 | set_global_assignment -name ERROR_ON_WARNINGS_LOADING_SDC_ON_RTL_CONSTRAINTS ON 12 | set_global_assignment -name RTL_SDC_FILE src/corescore_0/data/intel_agilex7.sdc 13 | 14 | -------------------------------------------------------------------------------- /data/intel_cyc10lp_devkit.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (25 Mhz) 2 | create_clock -name "clk" -period 20.000 [get_ports {clk50}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/intel_cyc10lp_devkit.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_E1 -to clk50 2 | 3 | # PMOD_D0 pin 4 | set_location_assignment PIN_D16 -to uart_txd 5 | 6 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk50 7 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart_txd 8 | 9 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" 10 | set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE WITH ERAM" 11 | 12 | set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1 13 | set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2 14 | set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3 15 | set_global_assignment -name IOBANK_VCCIO 1.8V -section_id 4 16 | set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 5 17 | set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 6 18 | set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7 19 | set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8 20 | 21 | -------------------------------------------------------------------------------- /data/intel_dk-dev-agf014ea.tcl: -------------------------------------------------------------------------------- 1 | # Base Clock 100 MHz 2 | set_location_assignment PIN_CU24 -to i_clk 3 | set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to i_clk -entity corescore_intel_agilex7 4 | 5 | # CPU_RESETn 6 | set_location_assignment PIN_A24 -to i_rstn 7 | set_instance_assignment -name IO_STANDARD "1.2 V" -to i_rstn -entity corescore_intel_agilex7 8 | 9 | # Build assignments 10 | set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to * -entity serv_state 11 | set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to * -entity serv_alu 12 | set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA" 13 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 14 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 15 | 16 | # SDM assignments 17 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" 18 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON 19 | set_global_assignment -name GENERATE_PR_RBF_FILE ON 20 | set_global_assignment -name ENABLE_ED_CRC_CHECK ON 21 | set_global_assignment -name MINIMUM_SEU_INTERVAL 0 22 | set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE ED8401 23 | set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 47 24 | set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 25 | set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 26 | set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ 27 | set_global_assignment -name USE_PWRMGT_SCL SDM_IO14 28 | set_global_assignment -name USE_PWRMGT_SDA SDM_IO11 29 | set_global_assignment -name USE_CONF_DONE SDM_IO16 30 | 31 | # SDC on RTL assignments 32 | set_global_assignment -name ERROR_ON_WARNINGS_PARSING_SDC_ON_RTL_CONSTRAINTS ON 33 | set_global_assignment -name ERROR_ON_WARNINGS_LOADING_SDC_ON_RTL_CONSTRAINTS ON 34 | set_global_assignment -name RTL_SDC_FILE src/corescore_0/data/intel_agilex7.sdc 35 | 36 | -------------------------------------------------------------------------------- /data/intel_dk-si-agi027fb.tcl: -------------------------------------------------------------------------------- 1 | # Base Clock 100 MHz 2 | set_location_assignment PIN_CM29 -to i_clk 3 | set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to i_clk 4 | 5 | # CPU_RESETn 6 | set_location_assignment PIN_AB53 -to i_rstn 7 | 8 | # Build assignments 9 | set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to * -entity serv_state 10 | set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to * -entity serv_alu 11 | set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA" 12 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 13 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 14 | 15 | # SDM assignments 16 | set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 17 | set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 18 | set_global_assignment -name USE_CONF_DONE SDM_IO16 19 | set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE ED8401 20 | set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 62 21 | set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" 22 | set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13" 23 | set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_115MHZ_IOSC 24 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" 25 | 26 | set_global_assignment -name ERROR_ON_WARNINGS_PARSING_SDC_ON_RTL_CONSTRAINTS ON 27 | set_global_assignment -name ERROR_ON_WARNINGS_LOADING_SDC_ON_RTL_CONSTRAINTS ON 28 | set_global_assignment -name RTL_SDC_FILE src/corescore_0/data/intel_agilex7.sdc 29 | 30 | -------------------------------------------------------------------------------- /data/intel_dk-si-agi040fes.tcl: -------------------------------------------------------------------------------- 1 | # Base Clock CLK_FPGA_100M 2 | set_location_assignment PIN_DM22 -to i_clk 3 | set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to i_clk -entity corescore_intel_agilex7 4 | 5 | # CPU_RESETn 6 | set_location_assignment PIN_G33 -to i_rstn 7 | 8 | # Build assignments 9 | set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to * -entity serv_state 10 | set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to * -entity serv_alu 11 | set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA" 12 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 13 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 14 | 15 | # SDM assignments 16 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8" 17 | set_global_assignment -name DEVICE_IO_STANDARD_ALL "1.2 V" 18 | set_global_assignment -name USE_CONFIGURATION_DEVICE OFF 19 | set_global_assignment -name GENERATE_PR_RBF_FILE ON 20 | set_global_assignment -name ENABLE_ED_CRC_CHECK ON 21 | set_global_assignment -name MINIMUM_SEU_INTERVAL 0 22 | set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888 23 | set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 62 24 | set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 25 | set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 26 | set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ 27 | set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 28 | set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 29 | set_global_assignment -name USE_CONF_DONE SDM_IO16 30 | set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ 31 | set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON 32 | set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" 33 | set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12" 34 | 35 | # SDC on RTL assignments 36 | set_global_assignment -name ERROR_ON_WARNINGS_PARSING_SDC_ON_RTL_CONSTRAINTS ON 37 | set_global_assignment -name ERROR_ON_WARNINGS_LOADING_SDC_ON_RTL_CONSTRAINTS ON 38 | set_global_assignment -name RTL_SDC_FILE src/corescore_0/data/intel_agilex7.sdc 39 | 40 | -------------------------------------------------------------------------------- /data/intel_max10_devkit.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (25 Mhz) 2 | create_clock -name "clk" -period 20.000 [get_ports {clk50}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/intel_max10_devkit.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_M9 -to clk50 2 | set_location_assignment PIN_T20 -to led0 3 | set_location_assignment PIN_W18 -to uart_txd 4 | set_location_assignment PIN_Y19 -to uart_rxd 5 | 6 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" 7 | set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE WITH ERAM" 8 | 9 | set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 1A 10 | set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 1B 11 | set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 2 12 | set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 3 13 | set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 4 14 | set_global_assignment -name IOBANK_VCCIO 1.5V -section_id 5 15 | set_global_assignment -name IOBANK_VCCIO 1.5V -section_id 6 16 | set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7 17 | set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8 18 | 19 | set_instance_assignment -name IO_STANDARD "1.5 V" -to led0 20 | -------------------------------------------------------------------------------- /data/intel_s10gx_devkit.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (50 Mhz) 2 | create_clock -name "clk" -period 20.000 [get_ports {clk50}] 3 | 4 | -------------------------------------------------------------------------------- /data/intel_s10gx_devkit.tcl: -------------------------------------------------------------------------------- 1 | # Base Clock CLK_FPGA_50M 2 | set_location_assignment PIN_BH33 -to clk50 3 | 4 | # CPU_RESETn (S4 - From Schematic) 5 | set_location_assignment PIN_A20 -to rstn 6 | 7 | set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to * -entity serv_state 8 | set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to * -entity serv_alu 9 | set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA" 10 | 11 | set_global_assignment -name USE_PWRMGT_SCL SDM_IO14 12 | set_global_assignment -name USE_PWRMGT_SDA SDM_IO11 13 | set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" 14 | set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" 15 | set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTM4677 16 | set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 4F 17 | set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 18 | set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 19 | set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 20 | set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00 21 | set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00 22 | set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00 23 | set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00 24 | set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON 25 | set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "AUTO DISCOVERY" 26 | set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS 27 | 28 | set_global_assignment -name USE_CONF_DONE SDM_IO16 29 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" 30 | set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_115MHZ_IOSC 31 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 32 | 33 | -------------------------------------------------------------------------------- /data/kc705.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports i_clk_p]; 2 | set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports i_clk_n]; 3 | create_clock -add -name sys_clk_pin -period 5 [get_nets i_clk]; 4 | 5 | set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS25 } [get_ports q]; 6 | set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS25 } [get_ports o_uart_tx] 7 | 8 | set_property RAM_STYLE block [get_cells corescorecore/core_*/serving/ram/mem_reg] 9 | -------------------------------------------------------------------------------- /data/libero-post-instructions.txt: -------------------------------------------------------------------------------- 1 | ========================= 2 | Libero build instructions 3 | ========================= 4 | 5 | After "Generate FPGA Array Data" task, open "Configure Design Initialization Data and Memories" tool. 6 | 7 | Click the "Fabric RAMs" tab and select "Initialize all clients from SPI-Flash" in the dropdown named "Initialize all clients from". 8 | 9 | Click "Apply". 10 | 11 | Select "Design Initialization" tab and set the dropdown "SPI Clock divider value" to "6 (13.33)". 12 | 13 | Click Apply 14 | -------------------------------------------------------------------------------- /data/marble.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict {PACKAGE_PIN AC9 IOSTANDARD DIFF_SSTL15 } [get_ports i_clk_p]; 2 | set_property -dict {PACKAGE_PIN AD9 IOSTANDARD DIFF_SSTL15 } [get_ports i_clk_n]; 3 | 4 | set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25 } [get_ports o_uart_tx] 5 | set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS25 } [get_ports i_uart_rx] 6 | 7 | # Alternative UART output on PMODA:0 8 | set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS25 } [get_ports o_uart_tx2] 9 | 10 | create_clock -add -name sys_clk_pin -period 8 [get_ports i_clk_p]; 11 | -------------------------------------------------------------------------------- /data/max1000.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (12 Mhz) 2 | create_clock -name "clk" -period 83.333ns [get_ports {CLK12M}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/max1000.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_H6 -to CLK12M 2 | set_location_assignment PIN_A8 -to q 3 | set_location_assignment PIN_A4 -to i_uart_rx 4 | set_location_assignment PIN_B4 -to o_uart_tx 5 | 6 | set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE WITH ERAM" 7 | 8 | -------------------------------------------------------------------------------- /data/nexys_a7.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports i_clk]; 2 | set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx] 3 | 4 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk]; 5 | -------------------------------------------------------------------------------- /data/nexys_video.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33 } [get_ports i_clk]; 2 | set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports o_uart_tx]; 3 | 4 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk]; 5 | -------------------------------------------------------------------------------- /data/polarfire_eval.pdc: -------------------------------------------------------------------------------- 1 | set_io -port_name {i_clk} -pin_name E25 -io_std LVCMOS18 -fixed true 2 | set_io -port_name {resetbtn} -pin_name K22 -io_std LVCMOS18 -fixed true 3 | set_io -port_name {q} -pin_name F22 -io_std LVCMOS18 -fixed true 4 | set_io -port_name {h} -pin_name B26 -io_std LVCMOS18 -fixed true 5 | set_io -port_name {o_uart_tx} -pin_name G17 -io_std LVCMOS18 -fixed true 6 | -------------------------------------------------------------------------------- /data/sockit.sdc: -------------------------------------------------------------------------------- 1 | # Main system clock (50 Mhz) 2 | create_clock -name "clk" -period 20.000ns [get_ports {i_clk}] 3 | 4 | # Automatically constrain PLL and other generated clocks 5 | derive_pll_clocks -create_base_clocks 6 | 7 | # Automatically calculate clock uncertainty to jitter and other effects. 8 | derive_clock_uncertainty 9 | -------------------------------------------------------------------------------- /data/sockit.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_AF14 -to i_clk 2 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk 3 | 4 | set_location_assignment PIN_AF10 -to q 5 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q 6 | 7 | set_location_assignment PIN_F14 -to uart_txd 8 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_txd 9 | 10 | set_location_assignment PIN_AE9 -to i_rst_n 11 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_rst_n 12 | -------------------------------------------------------------------------------- /data/thunderfjord.tcl: -------------------------------------------------------------------------------- 1 | # Base Clock CLK_FPGA_100M 2 | #100Mhz clk 3 | set_location_assignment PIN_AB57 -to i_clk 4 | set_location_assignment PIN_AC56 -to "i_clk(n)" 5 | set_instance_assignment -name IO_STANDARD "1.2V TRUE DIFFERENTIAL SIGNALING" -to i_clk 6 | set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to i_clk 7 | 8 | # CPU_RESETn 9 | set_location_assignment PIN_E38 -to i_rstn 10 | 11 | # Build assignments 12 | set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to * -entity serv_state 13 | set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to * -entity serv_alu 14 | set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA" 15 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 16 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 17 | 18 | # SDM assignments 19 | # Assembler Assignments 20 | # ===================== 21 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8" 22 | set_global_assignment -name PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE 3C 23 | set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" 24 | set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12" 25 | 26 | # Setup VID operation: 27 | set_global_assignment -name VID_OPERATION_MODE "PMBUS SLAVE" 28 | 29 | set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 30 | set_global_assignment -name USE_PWRMGT_SDA SDM_IO16 31 | set_global_assignment -name USE_PWRMGT_ALERT SDM_IO9 32 | set_global_assignment -name USE_INIT_DONE SDM_IO5 33 | set_global_assignment -name USE_CONF_DONE SDM_IO12 34 | set_global_assignment -name USE_HPS_COLD_RESET SDM_IO7 35 | set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ 36 | 37 | set_global_assignment -name FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD ON 38 | set_global_assignment -name ALLOW_RAM_RETIMING ON 39 | 40 | 41 | # SDC on RTL assignments 42 | set_global_assignment -name ERROR_ON_WARNINGS_PARSING_SDC_ON_RTL_CONSTRAINTS ON 43 | set_global_assignment -name ERROR_ON_WARNINGS_LOADING_SDC_ON_RTL_CONSTRAINTS ON 44 | set_global_assignment -name RTL_SDC_FILE src/corescore_0/data/intel_agilex7.sdc 45 | 46 | -------------------------------------------------------------------------------- /data/tinyfpga_bx.pcf: -------------------------------------------------------------------------------- 1 | set_io i_clk B2 2 | set_io pin_usb_p B4 3 | set_io pin_usb_n A4 4 | set_io pin_pu A3 5 | -------------------------------------------------------------------------------- /data/tinyfpga_bx.py: -------------------------------------------------------------------------------- 1 | ctx.addClock("i_clk", 16) 2 | ctx.addClock("clk", 48) 3 | -------------------------------------------------------------------------------- /data/ulx3s.lpf: -------------------------------------------------------------------------------- 1 | LOCATE COMP "i_clk" SITE "G2"; 2 | IOBUF PORT "i_clk" PULLMODE=NONE IO_TYPE=LVCMOS33; 3 | FREQUENCY PORT "i_clk" 25.000 MHZ; 4 | LOCATE COMP "q" SITE "B2"; 5 | IOBUF PORT "q" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 6 | 7 | LOCATE COMP "btn0" SITE "D6"; # BTN_PWRn (inverted logic) 8 | IOBUF PORT "btn0" PULLMODE=UP IO_TYPE=LVCMOS33; 9 | 10 | LOCATE COMP "wifi_gpio0" SITE "L2"; 11 | IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 12 | 13 | LOCATE COMP "o_uart_tx" SITE "L4"; # FPGA transmits to ftdi 14 | IOBUF PORT "o_uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 15 | -------------------------------------------------------------------------------- /data/upduino2.pcf: -------------------------------------------------------------------------------- 1 | set_io g 39 2 | set_io b 40 3 | set_io r 41 4 | set_io o_uart_tx 14 -------------------------------------------------------------------------------- /data/vcu118.xdc: -------------------------------------------------------------------------------- 1 | ## Clock signal 2 | set_property -dict { PACKAGE_PIN AY24 IOSTANDARD LVDS } [get_ports i_clk_p]; 3 | set_property -dict { PACKAGE_PIN AY23 IOSTANDARD LVDS } [get_ports i_clk_n]; 4 | create_clock -add -name sys_clk_pin -period 8 [get_nets i_clk]; 5 | 6 | ## LED 7 | set_property -dict { PACKAGE_PIN AT32 IOSTANDARD LVCMOS12 } [get_ports q]; 8 | set_property -dict { PACKAGE_PIN BB21 IOSTANDARD LVCMOS12 } [get_ports o_uart_tx] 9 | 10 | set_property RAM_STYLE block [get_cells corescorecore/core_*/serving/ram/mem_reg] 11 | -------------------------------------------------------------------------------- /data/vcu128.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN BK3 [get_ports "QDR4_CLK_100MHZ_N"] ; 2 | set_property IOSTANDARD DIFF_SSTL12 [get_ports "QDR4_CLK_100MHZ_N"] ; 3 | set_property PACKAGE_PIN BJ4 [get_ports "QDR4_CLK_100MHZ_P"] ; 4 | set_property IOSTANDARD DIFF_SSTL12 [get_ports "QDR4_CLK_100MHZ_P"] ; 5 | 6 | create_clock -add -name sys_clk_pin -period 10 [get_nets i_clk]; 7 | 8 | set_property PACKAGE_PIN BH24 [get_ports "GPIO_LED_0_LS"] ; 9 | set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_0_LS"] ; 10 | 11 | set_property PACKAGE_PIN BJ28 [get_ports "UART1_TXD"] ; 12 | set_property IOSTANDARD LVCMOS18 [get_ports "UART1_TXD"] ; 13 | 14 | set_property RAM_STYLE block [get_cells corescorecore/core_*/serving/ram/mem_reg] 15 | -------------------------------------------------------------------------------- /data/vivado_waive.tcl: -------------------------------------------------------------------------------- 1 | #Waive warnings 2 | set_msg_config -id "Synth 8-2507" -string "priority_encoder" -suppress 3 | set_msg_config -id "Synth 8-6014" -string "axis_arb_mux tkeep_reg" -suppress 4 | set_msg_config -id "Synth 8-6014" -string "axis_arb_mux tid_reg" -suppress 5 | set_msg_config -id "Synth 8-6014" -string "axis_arb_mux tdest_reg" -suppress 6 | set_msg_config -id "Synth 8-6014" -string "axis_arb_mux tuser_reg" -suppress 7 | set_msg_config -id "Synth 8-3331" -string "axis_arb_mux s_axis_tid" -suppress 8 | set_msg_config -id "Synth 8-3331" -string "axis_arb_mux s_axis_tkeep" -suppress 9 | -------------------------------------------------------------------------------- /data/vu19p.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN BW60 [get_ports "CLK_100MHZ_N"] ; 2 | set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "CLK_100MHZ_N"] ; 3 | set_property PACKAGE_PIN BV60 [get_ports "CLK_100MHZ_P"] ; 4 | set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "CLK_100MHZ_P"] ; 5 | 6 | create_clock -add -name sys_clk_pin -period 10 [get_nets i_clk]; 7 | 8 | set_property PACKAGE_PIN M21 [get_ports "UART_TXD"] ; 9 | set_property IOSTANDARD LVCMOS18 [get_ports "UART_TXD"] ; 10 | 11 | set_property RAM_STYLE block [get_cells corescorecore/core_*/serving/ram/mem_reg] 12 | -------------------------------------------------------------------------------- /data/xyloni.isf: -------------------------------------------------------------------------------- 1 | # Efinity Interface Configuration 2 | # Version: 2023.1.150 3 | # Date: 2023-10-06 23:12 4 | # 5 | # Copyright (C) 2017 - 2023 Efinix Inc. All rights reserved. 6 | # 7 | # Device: T8F81 8 | # Package: 81-ball FBGA (final) 9 | # Project: xyloni 10 | # Configuration mode: active (x1) 11 | # Timing Model: C2 (final) 12 | 13 | 14 | # Device setting 15 | design.set_device_property("1A","VOLTAGE","3.3","IOBANK") 16 | design.set_device_property("1B","VOLTAGE","3.3","IOBANK") 17 | design.set_device_property("1C","VOLTAGE","1.1","IOBANK") 18 | design.set_device_property("2A","VOLTAGE","3.3","IOBANK") 19 | design.set_device_property("2B","VOLTAGE","3.3","IOBANK") 20 | 21 | # Create instance 22 | design.create_pll_input_clock_gpio("PLL_IN") 23 | design.create_output_gpio("o_uart_tx") 24 | design.create_output_gpio("q") 25 | design.create_block("pll_inst1","PLL") 26 | 27 | # Set property, non-defaults 28 | design.set_property("o_uart_tx","OUT_REG","REG") 29 | design.set_property("o_uart_tx","OUT_CLK_PIN","i_clk") 30 | design.set_property("pll_inst1","CLKOUT0_EN","1","PLL") 31 | design.set_property("pll_inst1","CLKOUT1_EN","0","PLL") 32 | design.set_property("pll_inst1","CLKOUT2_EN","0","PLL") 33 | design.set_property("pll_inst1","CLKOUT0_DIV","8","PLL") 34 | design.set_property("pll_inst1","CLKOUT0_PIN","i_clk","PLL") 35 | design.set_property("pll_inst1","LOCKED_PIN","i_pll_locked","PLL") 36 | design.set_property("pll_inst1","M","16","PLL") 37 | design.set_property("pll_inst1","N","1","PLL") 38 | design.set_property("pll_inst1","O","4","PLL") 39 | design.set_property("pll_inst1","REFCLK_FREQ","33.33","PLL") 40 | design.set_property("pll_inst1","RSTN_PIN","","PLL") 41 | 42 | # Set resource assignment 43 | design.assign_pkg_pin("PLL_IN","C3") 44 | design.assign_pkg_pin("o_uart_tx","F3") 45 | design.assign_pkg_pin("q","B3") 46 | design.assign_resource("pll_inst1","PLL_0","PLL") 47 | -------------------------------------------------------------------------------- /data/zcu106.xdc: -------------------------------------------------------------------------------- 1 | ## Clock signal 2 | set_property -dict { PACKAGE_PIN H9 IOSTANDARD LVDS } [get_ports i_clk_p]; 3 | set_property -dict { PACKAGE_PIN G9 IOSTANDARD LVDS } [get_ports i_clk_n]; 4 | create_clock -add -name sys_clk_pin -period 8 [get_nets i_clk]; 5 | 6 | ## LED 7 | set_property -dict { PACKAGE_PIN AL11 IOSTANDARD LVCMOS12 } [get_ports q]; 8 | set_property -dict { PACKAGE_PIN AL17 IOSTANDARD LVCMOS12 } [get_ports o_uart_tx] 9 | 10 | set_property RAM_STYLE block [get_cells corescorecore/core_1*/serving/ram/mem_reg] 11 | set_property RAM_STYLE block [get_cells corescorecore/core_2*/serving/ram/mem_reg] 12 | set_property RAM_STYLE block [get_cells corescorecore/core_3*/serving/ram/mem_reg] 13 | set_property RAM_STYLE block [get_cells corescorecore/core_4*/serving/ram/mem_reg] 14 | set_property RAM_STYLE block [get_cells corescorecore/core_5*/serving/ram/mem_reg] 15 | #555 16 | set_property RAM_STYLE block [get_cells corescorecore/core_60*/serving/ram/mem_reg] 17 | #555+11 = 566 18 | set_property RAM_STYLE block [get_cells corescorecore/core_61*/serving/ram/mem_reg] 19 | #566+11 = 577 20 | set_property RAM_STYLE block [get_cells corescorecore/core_62*/serving/ram/mem_reg] 21 | #566+11 = 588 22 | set_property RAM_STYLE block [get_cells corescorecore/core_63*/serving/ram/mem_reg] 23 | #566+11 = 599 24 | set_property RAM_STYLE block [get_cells corescorecore/core_64*/serving/ram/mem_reg] 25 | #566+11 = 610 26 | set_property RAM_STYLE block [get_cells corescorecore/core_65*/serving/ram/mem_reg] 27 | #566+11 = 621 28 | set_property RAM_STYLE block [get_cells corescorecore/core_666/serving/ram/mem_reg] 29 | set_property RAM_STYLE block [get_cells corescorecore/core_667/serving/ram/mem_reg] 30 | -------------------------------------------------------------------------------- /rtl/arty_a7_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module arty_a7_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | PLLE2_BASE 12 | #(.BANDWIDTH("OPTIMIZED"), 13 | .CLKFBOUT_MULT(16), 14 | .CLKIN1_PERIOD(10.0), //100MHz 15 | .CLKOUT0_DIVIDE(100), 16 | .DIVCLK_DIVIDE(1), 17 | .STARTUP_WAIT("FALSE")) 18 | PLLE2_BASE_inst 19 | (.CLKOUT0(o_clk), 20 | .CLKOUT1(), 21 | .CLKOUT2(), 22 | .CLKOUT3(), 23 | .CLKOUT4(), 24 | .CLKOUT5(), 25 | .CLKFBOUT(clkfb), 26 | .LOCKED(locked), 27 | .CLKIN1(i_clk), 28 | .PWRDWN(1'b0), 29 | .RST(1'b0), 30 | .CLKFBIN(clkfb)); 31 | 32 | always @(posedge o_clk) begin 33 | locked_r <= locked; 34 | o_rst <= !locked_r; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /rtl/axis2wb.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module axis2wb 3 | ( 4 | input wire i_clk, 5 | input wire i_rst, 6 | input wire [0:0] i_wb_sel, 7 | input wire i_wb_stb, 8 | output wire [9:0] o_wb_rdt, 9 | output reg o_wb_ack, 10 | input wire [7:0] i_tdata, 11 | input wire i_tlast, 12 | input wire i_tvalid, 13 | output wire o_tready); 14 | 15 | always @(posedge i_clk) begin 16 | o_wb_ack <= i_wb_stb & !o_wb_ack; 17 | if (i_rst) 18 | o_wb_ack <= 1'b0; 19 | end 20 | 21 | assign o_tready = i_wb_sel[0] & o_wb_ack; 22 | assign o_wb_rdt = {i_tvalid, i_tlast, i_tdata}; 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /rtl/base.v: -------------------------------------------------------------------------------- 1 | module base 2 | (input wire i_clk, 3 | input wire i_rst, 4 | output wire [7:0] o_tdata, 5 | output wire o_tlast, 6 | output wire o_tvalid, 7 | input wire i_tready); 8 | 9 | parameter memfile = ""; 10 | parameter memsize = 8192; 11 | 12 | wire [31:0] wb_dat; 13 | wire wb_we; 14 | wire wb_stb; 15 | wire wb_ack; 16 | 17 | wb2axis w2s 18 | (.i_clk (i_clk), 19 | .i_rst (i_rst), 20 | .i_wb_dat (wb_dat[8:0]), 21 | .i_wb_we (wb_we), 22 | .i_wb_stb (wb_stb), 23 | .o_wb_ack (wb_ack), 24 | .o_tdata (o_tdata), 25 | .o_tlast (o_tlast), 26 | .o_tvalid (o_tvalid), 27 | .i_tready (i_tready)); 28 | 29 | serving 30 | #(.memfile (memfile), 31 | .memsize (memsize), 32 | .WITH_CSR (0)) 33 | serving 34 | (.i_clk (i_clk), 35 | .i_rst (i_rst), 36 | .i_timer_irq (1'b0), 37 | 38 | .o_wb_adr (), 39 | .o_wb_dat (wb_dat), 40 | .o_wb_sel (), 41 | .o_wb_we (wb_we), 42 | .o_wb_stb (wb_stb), 43 | .i_wb_rdt (32'd0), 44 | .i_wb_ack (wb_ack)); 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /rtl/chameleon96_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module de0_nano_clock_gen 3 | (input wire i_clk, 4 | input wire i_rst, 5 | output wire o_clk, 6 | output wire o_rst); 7 | 8 | wire locked; 9 | reg [9:0] r; 10 | 11 | assign o_rst = r[9]; 12 | 13 | always @(posedge o_clk) 14 | if (locked) 15 | r <= {r[8:0],1'b0}; 16 | else 17 | r <= 10'b1111111111; 18 | 19 | wire [5:0] clk; 20 | 21 | assign o_clk = clk[0]; 22 | 23 | altpll 24 | #(.operation_mode ("NORMAL"), 25 | .clk0_divide_by (25), 26 | .clk0_multiply_by (4), 27 | .inclk0_input_frequency (10000)) 28 | pll 29 | (.areset (i_rst), 30 | .inclk ({1'b0, i_clk}), 31 | .clk (clk), 32 | .locked (locked)); 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /rtl/cisco_hwic_3g_cdma_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module cisco_hwic_3g_cdma_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output wire o_rst); 6 | 7 | wire locked; 8 | reg [9:0] r; 9 | 10 | assign o_rst = r[9]; 11 | 12 | always @(posedge o_clk) 13 | if (locked) 14 | r <= {r[8:0],1'b0}; 15 | else 16 | r <= 10'b1111111111; 17 | 18 | altpll altpll_component ( 19 | .inclk (i_clk), 20 | .clk (o_clk), 21 | .locked (locked), 22 | .activeclock (), 23 | .areset (1'b0), 24 | .clkbad (), 25 | .clkena ({6{1'b1}}), 26 | .clkloss (), 27 | .clkswitch (1'b0), 28 | .configupdate (1'b0), 29 | .enable0 (), 30 | .enable1 (), 31 | .extclk (), 32 | .extclkena ({4{1'b1}}), 33 | .fbin (1'b1), 34 | .fbmimicbidir (), 35 | .fbout (), 36 | .fref (), 37 | .icdrclk (), 38 | .pfdena (1'b1), 39 | .phasecounterselect ({4{1'b1}}), 40 | .phasedone (), 41 | .phasestep (1'b1), 42 | .phaseupdown (1'b1), 43 | .pllena (1'b1), 44 | .scanaclr (1'b0), 45 | .scanclk (1'b0), 46 | .scanclkena (1'b1), 47 | .scandata (1'b0), 48 | .scandataout (), 49 | .scandone (), 50 | .scanread (1'b0), 51 | .scanwrite (1'b0), 52 | .sclkout0 (), 53 | .sclkout1 (), 54 | .vcooverrange (), 55 | .vcounderrange ()); 56 | defparam 57 | altpll_component.clk0_divide_by = 25, 58 | altpll_component.clk0_duty_cycle = 50, 59 | altpll_component.clk0_multiply_by = 16, 60 | altpll_component.clk0_phase_shift = "0", 61 | altpll_component.compensate_clock = "CLK0", 62 | altpll_component.gate_lock_signal = "NO", 63 | altpll_component.inclk0_input_frequency = 40000, 64 | altpll_component.intended_device_family = "Cyclone II", 65 | altpll_component.invalid_lock_multiplier = 5, 66 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=main_pll", 67 | altpll_component.lpm_type = "altpll", 68 | altpll_component.operation_mode = "NORMAL", 69 | altpll_component.port_activeclock = "PORT_UNUSED", 70 | altpll_component.port_areset = "PORT_UNUSED", 71 | altpll_component.port_clkbad0 = "PORT_UNUSED", 72 | altpll_component.port_clkbad1 = "PORT_UNUSED", 73 | altpll_component.port_clkloss = "PORT_UNUSED", 74 | altpll_component.port_clkswitch = "PORT_UNUSED", 75 | altpll_component.port_configupdate = "PORT_UNUSED", 76 | altpll_component.port_fbin = "PORT_UNUSED", 77 | altpll_component.port_inclk0 = "PORT_USED", 78 | altpll_component.port_inclk1 = "PORT_UNUSED", 79 | altpll_component.port_locked = "PORT_USED", 80 | altpll_component.port_pfdena = "PORT_UNUSED", 81 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 82 | altpll_component.port_phasedone = "PORT_UNUSED", 83 | altpll_component.port_phasestep = "PORT_UNUSED", 84 | altpll_component.port_phaseupdown = "PORT_UNUSED", 85 | altpll_component.port_pllena = "PORT_UNUSED", 86 | altpll_component.port_scanaclr = "PORT_UNUSED", 87 | altpll_component.port_scanclk = "PORT_UNUSED", 88 | altpll_component.port_scanclkena = "PORT_UNUSED", 89 | altpll_component.port_scandata = "PORT_UNUSED", 90 | altpll_component.port_scandataout = "PORT_UNUSED", 91 | altpll_component.port_scandone = "PORT_UNUSED", 92 | altpll_component.port_scanread = "PORT_UNUSED", 93 | altpll_component.port_scanwrite = "PORT_UNUSED", 94 | altpll_component.port_clk0 = "PORT_USED", 95 | altpll_component.port_clk1 = "PORT_UNUSED", 96 | altpll_component.port_clk2 = "PORT_UNUSED", 97 | altpll_component.port_clk3 = "PORT_UNUSED", 98 | altpll_component.port_clk4 = "PORT_UNUSED", 99 | altpll_component.port_clk5 = "PORT_UNUSED", 100 | altpll_component.port_clkena0 = "PORT_UNUSED", 101 | altpll_component.port_clkena1 = "PORT_UNUSED", 102 | altpll_component.port_clkena2 = "PORT_UNUSED", 103 | altpll_component.port_clkena3 = "PORT_UNUSED", 104 | altpll_component.port_clkena4 = "PORT_UNUSED", 105 | altpll_component.port_clkena5 = "PORT_UNUSED", 106 | altpll_component.port_extclk0 = "PORT_UNUSED", 107 | altpll_component.port_extclk1 = "PORT_UNUSED", 108 | altpll_component.port_extclk2 = "PORT_UNUSED", 109 | altpll_component.port_extclk3 = "PORT_UNUSED", 110 | altpll_component.valid_lock_multiplier = 1; 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /rtl/cmod_a7_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module cmod_a7_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | MMCME2_ADV #( 12 | .BANDWIDTH("OPTIMIZED"), 13 | .CLKFBOUT_MULT_F(64), 14 | .CLKIN1_PERIOD(83.33), // 12 MHz (not possible with PLLE2_BASE) 15 | .CLKOUT0_DIVIDE_F(48), 16 | .CLKOUT0_PHASE(1'd0), 17 | .DIVCLK_DIVIDE(1'd1), 18 | .REF_JITTER1(0.01) 19 | ) MMCME2_ADV ( 20 | .CLKFBIN(clkfb), 21 | .CLKIN1(i_clk), 22 | .PWRDWN(0), 23 | .RST(1'b0), 24 | .CLKFBOUT(clkfb), 25 | .CLKOUT0(o_clk), 26 | .LOCKED(locked) 27 | ); 28 | 29 | always @(posedge o_clk) begin 30 | locked_r <= locked; 31 | o_rst <= !locked_r; 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /rtl/corescore_alhambra_II.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_alhambra_II 3 | ( 4 | input i_clk, 5 | output wire locked_led, 6 | output wire o_uart_tx); 7 | 8 | wire clk; 9 | wire locked; 10 | 11 | //Mirror locked PLL to LED 12 | assign locked_led = locked; 13 | 14 | //Create a 16MHz clock from 12MHz using PLL 15 | pll pll48 16 | (.clock_in (i_clk), 17 | .clock_out (clk), 18 | .locked (locked)); 19 | 20 | reg rst = 1'b1; 21 | 22 | always @(posedge clk) 23 | rst <= !locked; 24 | 25 | parameter memfile_emitter = "emitter.hex"; 26 | 27 | wire [7:0] tdata; 28 | wire tlast; 29 | wire tvalid; 30 | wire tready; 31 | 32 | corescorecore corescorecore 33 | (.i_clk (clk), 34 | .i_rst (rst), 35 | .o_tdata (tdata), 36 | .o_tlast (tlast), 37 | .o_tvalid (tvalid), 38 | .i_tready (tready)); 39 | 40 | emitter #(.memfile (memfile_emitter)) emitter 41 | (.i_clk (clk), 42 | .i_rst (rst), 43 | .i_tdata (tdata), 44 | .i_tlast (tlast), 45 | .i_tvalid (tvalid), 46 | .o_tready (tready), 47 | .o_uart_tx (o_uart_tx)); 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /rtl/corescore_arty_a7.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_arty_a7 3 | ( 4 | input wire i_clk, 5 | output wire q, 6 | output wire o_uart_tx); 7 | 8 | wire clk; 9 | wire rst; 10 | 11 | //Mirror UART output to LED 12 | assign q = o_uart_tx; 13 | 14 | arty_a7_clock_gen clock_gen 15 | (.i_clk (i_clk), 16 | .o_clk (clk), 17 | .o_rst (rst)); 18 | 19 | wire [7:0] tdata; 20 | wire tlast; 21 | wire tvalid; 22 | wire tready; 23 | 24 | corescorecore corescorecore 25 | (.i_clk (clk), 26 | .i_rst (rst), 27 | .o_tdata (tdata), 28 | .o_tlast (tlast), 29 | .o_tvalid (tvalid), 30 | .i_tready (tready)); 31 | 32 | emitter_uart emitter 33 | (.i_clk (clk), 34 | .i_rst (rst), 35 | .i_tdata (tdata), 36 | .i_tvalid (tvalid), 37 | .o_tready (tready), 38 | .o_uart_tx (o_uart_tx)); 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /rtl/corescore_chameleon96.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_chameleon96 3 | ( 4 | input wire i_clk, 5 | input wire i_rst_n, 6 | output wire q, 7 | output wire uart_txd); 8 | 9 | wire clk; 10 | wire rst; 11 | 12 | //Mirror UART output to LED 13 | assign q = uart_txd; 14 | 15 | de0_nano_clock_gen clock_gen 16 | (.i_clk (i_clk), 17 | .i_rst (!i_rst_n), 18 | .o_clk (clk), 19 | .o_rst (rst)); 20 | 21 | parameter memfile_emitter = "emitter.hex"; 22 | 23 | wire [7:0] tdata; 24 | wire tlast; 25 | wire tvalid; 26 | wire tready; 27 | 28 | corescorecore corescorecore 29 | (.i_clk (clk), 30 | .i_rst (rst), 31 | .o_tdata (tdata), 32 | .o_tlast (tlast), 33 | .o_tvalid (tvalid), 34 | .i_tready (tready)); 35 | 36 | emitter #(.memfile (memfile_emitter)) emitter 37 | (.i_clk (clk), 38 | .i_rst (rst), 39 | .i_tdata (tdata), 40 | .i_tlast (tlast), 41 | .i_tvalid (tvalid), 42 | .o_tready (tready), 43 | .o_uart_tx (uart_txd)); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /rtl/corescore_cisco_hwic_3g_cdma.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_cisco_hwic_3g_cdma 3 | ( 4 | input wire clk25, 5 | output wire led0, 6 | output wire uart_txd, 7 | output wire uart_drv_ena_, 8 | output wire uart_drv_sd_); 9 | 10 | wire clk; 11 | wire rst; 12 | 13 | //Mirror UART output to LED 14 | assign led0 = uart_txd; 15 | assign uart_drv_ena_ = 1'b0; // ADM3222 EN_: Set 0 to enable RX 16 | assign uart_drv_sd_ = 1'b1; // ADM3222 SD_: Set 1 to enabel TX 17 | 18 | cisco_hwic_3g_cdma_clock_gen clock_gen 19 | (.i_clk (clk25), 20 | .o_clk (clk), 21 | .o_rst (rst)); 22 | 23 | parameter memfile_emitter = "emitter.hex"; 24 | 25 | wire [7:0] tdata; 26 | wire tlast; 27 | wire tvalid; 28 | wire tready; 29 | 30 | corescorecore corescorecore 31 | (.i_clk (clk), 32 | .i_rst (rst), 33 | .o_tdata (tdata), 34 | .o_tlast (tlast), 35 | .o_tvalid (tvalid), 36 | .i_tready (tready)); 37 | 38 | emitter #(.memfile (memfile_emitter)) emitter 39 | (.i_clk (clk), 40 | .i_rst (rst), 41 | .i_tdata (tdata), 42 | .i_tlast (tlast), 43 | .i_tvalid (tvalid), 44 | .o_tready (tready), 45 | .o_uart_tx (uart_txd)); 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /rtl/corescore_cmod_a7.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_cmod_a7 3 | ( 4 | input wire i_clk, 5 | output wire q, 6 | output wire o_uart_tx); 7 | 8 | wire clk; 9 | wire rst; 10 | 11 | //Mirror UART output to LED 12 | assign q = o_uart_tx; 13 | 14 | cmod_a7_clock_gen clock_gen 15 | (.i_clk (i_clk), 16 | .o_clk (clk), 17 | .o_rst (rst)); 18 | 19 | parameter memfile_emitter = "emitter.hex"; 20 | 21 | wire [7:0] tdata; 22 | wire tlast; 23 | wire tvalid; 24 | wire tready; 25 | 26 | corescorecore corescorecore 27 | (.i_clk (clk), 28 | .i_rst (rst), 29 | .o_tdata (tdata), 30 | .o_tlast (tlast), 31 | .o_tvalid (tvalid), 32 | .i_tready (tready)); 33 | 34 | emitter #(.memfile (memfile_emitter)) emitter 35 | (.i_clk (clk), 36 | .i_rst (rst), 37 | .i_tdata (tdata), 38 | .i_tlast (tlast), 39 | .i_tvalid (tvalid), 40 | .o_tready (tready), 41 | .o_uart_tx (o_uart_tx)); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /rtl/corescore_colorlight.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_colorlight 3 | (input wire i_clk, 4 | input wire btn0, 5 | output wire o_uart_tx); 6 | 7 | wire clk; 8 | wire rst; 9 | 10 | 11 | corescore_colorlight_clock_gen clock_gen 12 | (.i_clk (i_clk), 13 | .i_rst (!btn0), 14 | .o_clk (clk), 15 | .o_rst (rst)); 16 | 17 | parameter memfile_emitter = "emitter.hex"; 18 | 19 | wire [7:0] tdata; 20 | wire tlast; 21 | wire tvalid; 22 | wire tready; 23 | 24 | corescorecore corescorecore 25 | (.i_clk (clk), 26 | .i_rst (rst), 27 | .o_tdata (tdata), 28 | .o_tlast (tlast), 29 | .o_tvalid (tvalid), 30 | .i_tready (tready)); 31 | 32 | emitter #(.memfile (memfile_emitter)) emitter 33 | (.i_clk (clk), 34 | .i_rst (rst), 35 | .i_tdata (tdata), 36 | .i_tlast (tlast), 37 | .i_tvalid (tvalid), 38 | .o_tready (tready), 39 | .o_uart_tx (o_uart_tx)); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /rtl/corescore_colorlight_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_colorlight_clock_gen 3 | ( 4 | input i_clk, 5 | input i_rst, 6 | output o_clk, 7 | output o_rst); 8 | 9 | wire locked; 10 | 11 | reg [1:0] rst_reg; 12 | always @(posedge o_clk) 13 | if (i_rst) 14 | rst_reg <= 2'b11; 15 | else 16 | rst_reg <= {!locked, rst_reg[1]}; 17 | 18 | assign o_rst = rst_reg[0]; 19 | 20 | pll pll 21 | (.clki (i_clk), 22 | .clko (o_clk), 23 | .locked (locked)); 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /rtl/corescore_cyc1000.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_cyc1000 3 | ( 4 | input wire i_clk, 5 | output wire q, 6 | output wire o_uart_tx); 7 | 8 | wire clk; 9 | wire rst; 10 | 11 | //Mirror UART output to LED 12 | assign q = o_uart_tx; 13 | 14 | cyc1000_clock_gen clock_gen 15 | (.i_clk (i_clk), 16 | .o_clk (clk), 17 | .o_rst (rst)); 18 | 19 | parameter memfile_emitter = "emitter.hex"; 20 | 21 | wire [7:0] tdata; 22 | wire tlast; 23 | wire tvalid; 24 | wire tready; 25 | 26 | corescorecore corescorecore 27 | (.i_clk (clk), 28 | .i_rst (rst), 29 | .o_tdata (tdata), 30 | .o_tlast (tlast), 31 | .o_tvalid (tvalid), 32 | .i_tready (tready)); 33 | 34 | emitter #(.memfile (memfile_emitter)) emitter 35 | (.i_clk (clk), 36 | .i_rst (rst), 37 | .i_tdata (tdata), 38 | .i_tlast (tlast), 39 | .i_tvalid (tvalid), 40 | .o_tready (tready), 41 | .o_uart_tx (o_uart_tx)); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /rtl/corescore_de0_nano.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_de0_nano 3 | ( 4 | input wire i_clk, 5 | input wire i_rst_n, 6 | output wire q, 7 | output wire o_uart_tx); 8 | 9 | wire clk; 10 | wire rst; 11 | 12 | //Mirror UART output to LED 13 | assign q = o_uart_tx; 14 | 15 | de0_nano_clock_gen clock_gen 16 | (.i_clk (i_clk), 17 | .i_rst (!i_rst_n), 18 | .o_clk (clk), 19 | .o_rst (rst)); 20 | 21 | parameter memfile_emitter = "emitter.hex"; 22 | 23 | wire [7:0] tdata; 24 | wire tlast; 25 | wire tvalid; 26 | wire tready; 27 | 28 | corescorecore corescorecore 29 | (.i_clk (clk), 30 | .i_rst (rst), 31 | .o_tdata (tdata), 32 | .o_tlast (tlast), 33 | .o_tvalid (tvalid), 34 | .i_tready (tready)); 35 | 36 | emitter #(.memfile (memfile_emitter)) emitter 37 | (.i_clk (clk), 38 | .i_rst (rst), 39 | .i_tdata (tdata), 40 | .i_tlast (tlast), 41 | .i_tvalid (tvalid), 42 | .o_tready (tready), 43 | .o_uart_tx (o_uart_tx)); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /rtl/corescore_de10_nano.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_de10_nano 3 | ( 4 | input wire i_clk, 5 | input wire i_rst_n, 6 | output wire q, 7 | output wire uart_txd); 8 | 9 | wire clk; 10 | wire rst; 11 | 12 | //Mirror UART output to LED 13 | assign q = uart_txd; 14 | 15 | de0_nano_clock_gen clock_gen 16 | (.i_clk (i_clk), 17 | .i_rst (!i_rst_n), 18 | .o_clk (clk), 19 | .o_rst (rst)); 20 | 21 | parameter memfile_emitter = "emitter.hex"; 22 | 23 | wire [7:0] tdata; 24 | wire tlast; 25 | wire tvalid; 26 | wire tready; 27 | 28 | corescorecore corescorecore 29 | (.i_clk (clk), 30 | .i_rst (rst), 31 | .o_tdata (tdata), 32 | .o_tlast (tlast), 33 | .o_tvalid (tvalid), 34 | .i_tready (tready)); 35 | 36 | emitter #(.memfile (memfile_emitter)) emitter 37 | (.i_clk (clk), 38 | .i_rst (rst), 39 | .i_tdata (tdata), 40 | .i_tlast (tlast), 41 | .i_tvalid (tvalid), 42 | .o_tready (tready), 43 | .o_uart_tx (uart_txd)); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /rtl/corescore_de5_net.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_de5_net ( 3 | input wire i_clk, 4 | input wire i_rst_n, 5 | output wire o_led_n, 6 | output wire o_hex0_dp_n, 7 | output wire o_hex1_dp_n, 8 | output wire o_uart_txd, 9 | output wire o_rs422_de, 10 | output wire o_rs422_re_n, 11 | output wire o_rs422_te 12 | ); 13 | 14 | wire clk; 15 | wire rst; 16 | 17 | // Mirror UART output to LED and decimal point on 7-seg 18 | assign o_led_n = ~o_uart_txd; 19 | assign o_hex0_dp_n = o_uart_txd; 20 | assign o_hex1_dp_n = ~o_uart_txd; 21 | 22 | de5_net_clock_gen clock_gen 23 | (.i_clk (i_clk), 24 | .i_rst (!i_rst_n), 25 | .o_clk (clk), 26 | .o_rst (rst)); 27 | 28 | parameter memfile_emitter = "emitter.hex"; 29 | 30 | wire [7:0] tdata; 31 | wire tlast; 32 | wire tvalid; 33 | wire tready; 34 | 35 | corescorecore corescorecore 36 | (.i_clk (clk), 37 | .i_rst (rst), 38 | .o_tdata (tdata), 39 | .o_tlast (tlast), 40 | .o_tvalid (tvalid), 41 | .i_tready (tready)); 42 | 43 | emitter #(.memfile (memfile_emitter)) emitter 44 | (.i_clk (clk), 45 | .i_rst (rst), 46 | .i_tdata (tdata), 47 | .i_tlast (tlast), 48 | .i_tvalid (tvalid), 49 | .o_tready (tready), 50 | .o_uart_tx (o_uart_txd)); 51 | 52 | assign o_rs422_de = 1'b1; // Driver enable 53 | assign o_rs422_re_n = 1'b1; // Receiver disabled 54 | assign o_rs422_te = 1'b0; // Disable RS-485 termination 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /rtl/corescore_deca.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_deca 3 | ( 4 | input wire i_clk, 5 | input wire i_rst_n, 6 | output wire q, 7 | output wire uart_txd); 8 | 9 | wire clk; 10 | wire rst; 11 | 12 | //Mirror UART output to LED 13 | assign q = uart_txd; 14 | 15 | de0_nano_clock_gen clock_gen 16 | (.i_clk (i_clk), 17 | .i_rst (!i_rst_n), 18 | .o_clk (clk), 19 | .o_rst (rst)); 20 | 21 | parameter memfile_emitter = "emitter.hex"; 22 | 23 | wire [7:0] tdata; 24 | wire tlast; 25 | wire tvalid; 26 | wire tready; 27 | 28 | corescorecore corescorecore 29 | (.i_clk (clk), 30 | .i_rst (rst), 31 | .o_tdata (tdata), 32 | .o_tlast (tlast), 33 | .o_tvalid (tvalid), 34 | .i_tready (tready)); 35 | 36 | emitter #(.memfile (memfile_emitter)) emitter 37 | (.i_clk (clk), 38 | .i_rst (rst), 39 | .i_tdata (tdata), 40 | .i_tlast (tlast), 41 | .i_tvalid (tvalid), 42 | .o_tready (tready), 43 | .o_uart_tx (uart_txd)); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /rtl/corescore_ebaz4205.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_ebaz4205 3 | ( 4 | input wire i_clk, 5 | output wire o_uart_tx); 6 | 7 | wire clk; 8 | wire rst; 9 | 10 | ebaz4205_clock_gen clock_gen 11 | (.i_clk (i_clk), 12 | .o_clk (clk), 13 | .o_rst (rst)); 14 | 15 | parameter memfile_emitter = "emitter.hex"; 16 | 17 | wire [7:0] tdata; 18 | wire tlast; 19 | wire tvalid; 20 | wire tready; 21 | 22 | corescorecore corescorecore 23 | (.i_clk (clk), 24 | .i_rst (rst), 25 | .o_tdata (tdata), 26 | .o_tlast (tlast), 27 | .o_tvalid (tvalid), 28 | .i_tready (tready)); 29 | 30 | emitter #(.memfile (memfile_emitter)) emitter 31 | (.i_clk (clk), 32 | .i_rst (rst), 33 | .i_tdata (tdata), 34 | .i_tlast (tlast), 35 | .i_tvalid (tvalid), 36 | .o_tready (tready), 37 | .o_uart_tx (o_uart_tx)); 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /rtl/corescore_ep2c5t144_devboard.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_ep2c5t144_devboard 3 | ( 4 | input wire clk50, 5 | output wire led0, 6 | output wire uart_txd); 7 | 8 | wire clk; 9 | wire rst; 10 | 11 | //Mirror UART output to LED 12 | assign led0 = uart_txd; 13 | 14 | ep2c5t144_clock_gen clock_gen 15 | (.i_clk (clk50), 16 | .o_clk (clk), 17 | .o_rst (rst)); 18 | 19 | parameter memfile_emitter = "emitter.hex"; 20 | 21 | wire [7:0] tdata; 22 | wire tlast; 23 | wire tvalid; 24 | wire tready; 25 | 26 | corescorecore corescorecore 27 | (.i_clk (clk), 28 | .i_rst (rst), 29 | .o_tdata (tdata), 30 | .o_tlast (tlast), 31 | .o_tvalid (tvalid), 32 | .i_tready (tready)); 33 | 34 | emitter #(.memfile (memfile_emitter)) emitter 35 | (.i_clk (clk), 36 | .i_rst (rst), 37 | .i_tdata (tdata), 38 | .i_tlast (tlast), 39 | .i_tvalid (tvalid), 40 | .o_tready (tready), 41 | .o_uart_tx (uart_txd)); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /rtl/corescore_fpc_iii.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_fpc_iii( input i_clk, output o_uart_tx ); 3 | wire clk; 4 | wire rst; 5 | 6 | corescore_fpc_iii_clock_gen clock_gen( .i_clk( i_clk ), .o_clk( clk ), 7 | .o_rst( rst ) ); 8 | 9 | parameter memfile_emitter = "emitter.hex"; 10 | 11 | wire [7:0] tdata; 12 | wire tlast; 13 | wire tvalid; 14 | wire tready; 15 | 16 | corescorecore corescorecore 17 | (.i_clk (clk), 18 | .i_rst (rst), 19 | .o_tdata (tdata), 20 | .o_tlast (tlast), 21 | .o_tvalid (tvalid), 22 | .i_tready (tready)); 23 | 24 | emitter #(.memfile (memfile_emitter)) emitter 25 | (.i_clk (clk), 26 | .i_rst (rst), 27 | .i_tdata (tdata), 28 | .i_tlast (tlast), 29 | .i_tvalid (tvalid), 30 | .o_tready (tready), 31 | .o_uart_tx (o_uart_tx)); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /rtl/corescore_fpc_iii_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_fpc_iii_clock_gen( input i_clk, output o_clk, output o_rst ); 3 | 4 | wire locked; 5 | 6 | reg[ 1:0 ] rst_reg; 7 | always @( posedge o_clk ) 8 | rst_reg <= { !locked, rst_reg[ 1 ] }; 9 | 10 | assign o_rst = rst_reg[ 0 ]; 11 | 12 | pll pll( .clki( i_clk ), .clko( o_clk ), .locked( locked ) ); 13 | endmodule 14 | -------------------------------------------------------------------------------- /rtl/corescore_generic.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_generic 3 | ( 4 | input wire i_clk, 5 | input wire i_rst, 6 | output wire o_uart_tx); 7 | 8 | parameter memfile_emitter = "emitter.hex"; 9 | 10 | wire [7:0] tdata; 11 | wire tlast; 12 | wire tvalid; 13 | wire tready; 14 | 15 | corescorecore corescorecore 16 | (.i_clk (i_clk), 17 | .i_rst (i_rst), 18 | .o_tdata (tdata), 19 | .o_tlast (tlast), 20 | .o_tvalid (tvalid), 21 | .i_tready (tready)); 22 | 23 | emitter #(.memfile (memfile_emitter)) emitter 24 | (.i_clk (i_clk), 25 | .i_rst (i_rst), 26 | .i_tdata (tdata), 27 | .i_tlast (tlast), 28 | .i_tvalid (tvalid), 29 | .o_tready (tready), 30 | .o_uart_tx (o_uart_tx)); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /rtl/corescore_genesys2.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_genesys2 3 | ( 4 | input wire i_clk_p, 5 | input wire i_clk_n, 6 | output wire o_uart_tx); 7 | 8 | wire i_clk; 9 | wire clk; 10 | wire rst; 11 | 12 | IBUFDS ibufds 13 | (.I (i_clk_p), 14 | .IB (i_clk_n), 15 | .O (i_clk)); 16 | 17 | genesys2_clock_gen 18 | clock_gen 19 | (.i_clk (i_clk), 20 | .o_clk (clk), 21 | .o_rst (rst)); 22 | 23 | parameter memfile_emitter = "emitter.hex"; 24 | 25 | wire [7:0] tdata; 26 | wire tlast; 27 | wire tvalid; 28 | wire tready; 29 | 30 | corescorecore corescorecore 31 | (.i_clk (clk), 32 | .i_rst (rst), 33 | .o_tdata (tdata), 34 | .o_tlast (tlast), 35 | .o_tvalid (tvalid), 36 | .i_tready (tready)); 37 | 38 | emitter #(.memfile (memfile_emitter)) emitter 39 | (.i_clk (clk), 40 | .i_rst (rst), 41 | .i_tdata (tdata), 42 | .i_tlast (tlast), 43 | .i_tvalid (tvalid), 44 | .o_tready (tready), 45 | .o_uart_tx (o_uart_tx)); 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /rtl/corescore_go_board.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_go_board 3 | ( 4 | input wire i_clk, 5 | output wire o_uart_tx, 6 | output wire o_led1, 7 | output wire o_led2 = 0, 8 | output wire o_led3 = 0, 9 | output wire o_led4 = 0, 10 | output wire o_pmod1); 11 | 12 | // Mirror UART output to LED1 and PMOD1 13 | assign o_led1 = !o_uart_tx; 14 | assign o_pmod1 = o_uart_tx; 15 | 16 | // Assert reset for 64 clock cycles. Use the 7th bit as the reset signal. 17 | reg [6:0] rst_count; 18 | wire rst_r = !rst_count[6]; 19 | 20 | always @(posedge i_clk) begin 21 | if (rst_r == 1) begin 22 | rst_count <= rst_count + 1; 23 | end 24 | end 25 | 26 | wire [7:0] tdata; 27 | wire tvalid; 28 | wire tready; 29 | 30 | corescorecore corescorecore 31 | (.i_clk (i_clk), 32 | .i_rst (rst_r), 33 | .o_tdata (tdata), 34 | .o_tlast (), 35 | .o_tvalid (tvalid), 36 | .i_tready (tready)); 37 | 38 | emitter_uart #(.clk_freq_hz (25_000_000)) emitter 39 | (.i_clk (i_clk), 40 | .i_rst (rst_r), 41 | .i_tdata (tdata), 42 | .i_tvalid (tvalid), 43 | .o_tready (tready), 44 | .o_uart_tx (o_uart_tx)); 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /rtl/corescore_haps_dx7.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_haps_dx7 3 | ( 4 | input wire i_clk_in, 5 | output wire o_clk_en, 6 | output wire q, 7 | output wire o_uart_tx); 8 | 9 | wire i_clk; 10 | wire clk; 11 | wire rst; 12 | 13 | //Enable clock input 14 | assign o_clk_en = 1'b1; 15 | 16 | //Mirror UART output to LED 17 | assign q = o_uart_tx; 18 | 19 | IBUF ibuf 20 | (.I (i_clk_in), 21 | .O (i_clk)); 22 | 23 | corescore_haps_dx7_clock_gen 24 | clock_gen 25 | (.i_clk (i_clk), 26 | .o_clk (clk), 27 | .o_rst (rst)); 28 | 29 | parameter memfile_emitter = "emitter.hex"; 30 | 31 | wire [7:0] tdata; 32 | wire tlast; 33 | wire tvalid; 34 | wire tready; 35 | 36 | corescorecore corescorecore 37 | (.i_clk (clk), 38 | .i_rst (rst), 39 | .o_tdata (tdata), 40 | .o_tlast (tlast), 41 | .o_tvalid (tvalid), 42 | .i_tready (tready)); 43 | 44 | emitter #(.memfile (memfile_emitter)) emitter 45 | (.i_clk (clk), 46 | .i_rst (rst), 47 | .i_tdata (tdata), 48 | .i_tlast (tlast), 49 | .i_tvalid (tvalid), 50 | .o_tready (tready), 51 | .o_uart_tx (o_uart_tx)); 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /rtl/corescore_haps_dx7_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_haps_dx7_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output wire o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | reg rst = 1'b1; 11 | 12 | assign o_rst = rst; 13 | 14 | MMCME2_ADV 15 | #(.DIVCLK_DIVIDE (5), 16 | .CLKFBOUT_MULT_F (30.000), 17 | .CLKOUT0_DIVIDE_F (50.0), 18 | .CLKIN1_PERIOD (7.5001875), //133.33 MHz 19 | .STARTUP_WAIT ("FALSE")) 20 | mmcm 21 | (.CLKFBOUT (clkfb), 22 | .CLKFBOUTB (), 23 | .CLKOUT0 (o_clk), 24 | .CLKOUT0B (), 25 | .CLKOUT1 (), 26 | .CLKOUT1B (), 27 | .CLKOUT2 (), 28 | .CLKOUT2B (), 29 | .CLKOUT3 (), 30 | .CLKOUT3B (), 31 | .CLKOUT4 (), 32 | .CLKOUT5 (), 33 | .CLKIN1 (i_clk), 34 | .CLKIN2 (1'b0), 35 | .CLKINSEL (1'b1), 36 | .LOCKED (locked), 37 | .PWRDWN (1'b0), 38 | .RST (1'b0), 39 | .CLKFBIN (clkfb)); 40 | 41 | always @(posedge o_clk) begin 42 | locked_r <= locked; 43 | if (locked_r) begin 44 | rst <= 1'b0; 45 | end else begin 46 | rst <= rst; 47 | end 48 | end 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /rtl/corescore_hpc_k7.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_hpc_k7 3 | ( 4 | input wire i_clk, 5 | output wire o_uart_tx); 6 | 7 | wire clk; 8 | wire rst; 9 | 10 | hpc_k7_clock_gen clock_gen 11 | (.i_clk (i_clk), 12 | .o_clk (clk), 13 | .o_rst (rst)); 14 | 15 | parameter memfile_emitter = "emitter.hex"; 16 | 17 | wire [7:0] tdata; 18 | wire tlast; 19 | wire tvalid; 20 | wire tready; 21 | 22 | corescorecore corescorecore 23 | (.i_clk (clk), 24 | .i_rst (rst), 25 | .o_tdata (tdata), 26 | .o_tlast (tlast), 27 | .o_tvalid (tvalid), 28 | .i_tready (tready)); 29 | 30 | emitter #(.memfile (memfile_emitter)) emitter 31 | (.i_clk (clk), 32 | .i_rst (rst), 33 | .i_tdata (tdata), 34 | .i_tlast (tlast), 35 | .i_tvalid (tvalid), 36 | .o_tready (tready), 37 | .o_uart_tx (o_uart_tx)); 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /rtl/corescore_hpc_ku.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_hpc_ku 3 | ( 4 | input wire i_clk, 5 | output wire o_uart_tx); 6 | 7 | wire clk; 8 | wire rst; 9 | 10 | hpc_ku_clock_gen clock_gen 11 | (.i_clk (i_clk), 12 | .o_clk (clk), 13 | .o_rst (rst)); 14 | 15 | parameter memfile_emitter = "emitter.hex"; 16 | 17 | wire [7:0] tdata; 18 | wire tlast; 19 | wire tvalid; 20 | wire tready; 21 | 22 | corescorecore corescorecore 23 | (.i_clk (clk), 24 | .i_rst (rst), 25 | .o_tdata (tdata), 26 | .o_tlast (tlast), 27 | .o_tvalid (tvalid), 28 | .i_tready (tready)); 29 | 30 | emitter #(.memfile (memfile_emitter)) emitter 31 | (.i_clk (clk), 32 | .i_rst (rst), 33 | .i_tdata (tdata), 34 | .i_tlast (tlast), 35 | .i_tvalid (tvalid), 36 | .o_tready (tready), 37 | .o_uart_tx (o_uart_tx)); 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /rtl/corescore_hx8k.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_hx8k 3 | ( 4 | input i_clk, 5 | output wire o_uart_tx); 6 | 7 | wire clk; 8 | wire locked; 9 | 10 | //Create a 16MHz clock from 12MHz using PLL 11 | pll pll12 12 | (.clock_in (i_clk), 13 | .clock_out (clk), 14 | .locked (locked)); 15 | 16 | reg rst = 1'b1; 17 | 18 | always @(posedge clk) 19 | rst <= !locked; 20 | 21 | parameter memfile_emitter = "emitter.hex"; 22 | 23 | wire [7:0] tdata; 24 | wire tlast; 25 | wire tvalid; 26 | wire tready; 27 | 28 | corescorecore corescorecore 29 | (.i_clk (clk), 30 | .i_rst (rst), 31 | .o_tdata (tdata), 32 | .o_tlast (tlast), 33 | .o_tvalid (tvalid), 34 | .i_tready (tready)); 35 | 36 | emitter #(.memfile (memfile_emitter)) emitter 37 | (.i_clk (clk), 38 | .i_rst (rst), 39 | .i_tdata (tdata), 40 | .i_tlast (tlast), 41 | .i_tvalid (tvalid), 42 | .o_tready (tready), 43 | .o_uart_tx (o_uart_tx)); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /rtl/corescore_icebreaker.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_icebreaker 3 | ( 4 | input i_clk, 5 | output wire o_uart_tx); 6 | 7 | wire clk; 8 | wire locked; 9 | 10 | //Create a 16MHz clock from 12MHz using PLL 11 | SB_PLL40_PAD 12 | #( 13 | .FEEDBACK_PATH("SIMPLE"), 14 | .DIVR(4'b0000), 15 | .DIVF(7'b1010100), 16 | .DIVQ(3'b110), 17 | .FILTER_RANGE(3'b001)) 18 | pll 19 | (.LOCK(locked), 20 | .RESETB(1'b1), 21 | .BYPASS(1'b0), 22 | .PACKAGEPIN(i_clk), 23 | .PLLOUTCORE(clk)); 24 | 25 | reg rst = 1'b1; 26 | 27 | always @(posedge clk) 28 | rst <= !locked; 29 | 30 | parameter memfile_emitter = "emitter.hex"; 31 | 32 | wire [7:0] tdata; 33 | wire tlast; 34 | wire tvalid; 35 | wire tready; 36 | 37 | corescorecore corescorecore 38 | (.i_clk (clk), 39 | .i_rst (rst), 40 | .o_tdata (tdata), 41 | .o_tlast (tlast), 42 | .o_tvalid (tvalid), 43 | .i_tready (tready)); 44 | 45 | emitter #(.memfile (memfile_emitter)) emitter 46 | (.i_clk (clk), 47 | .i_rst (rst), 48 | .i_tdata (tdata), 49 | .i_tlast (tlast), 50 | .i_tvalid (tvalid), 51 | .o_tready (tready), 52 | .o_uart_tx (o_uart_tx)); 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /rtl/corescore_icestick.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_icestick 3 | ( 4 | input i_clk, 5 | output wire o_uart_tx); 6 | 7 | wire clk; 8 | wire locked; 9 | 10 | //Create a 16MHz clock from 12MHz using PLL 11 | pll pll12 12 | (.clock_in (i_clk), 13 | .clock_out (clk), 14 | .locked (locked)); 15 | 16 | reg rst = 1'b1; 17 | 18 | always @(posedge clk) 19 | rst <= !locked; 20 | 21 | parameter memfile_emitter = "emitter.hex"; 22 | 23 | wire [7:0] tdata; 24 | wire tlast; 25 | wire tvalid; 26 | wire tready; 27 | 28 | corescorecore corescorecore 29 | (.i_clk (clk), 30 | .i_rst (rst), 31 | .o_tdata (tdata), 32 | .o_tlast (tlast), 33 | .o_tvalid (tvalid), 34 | .i_tready (tready)); 35 | 36 | emitter_uart emitter 37 | (.i_clk (clk), 38 | .i_rst (rst), 39 | .i_tdata (tdata), 40 | .i_tvalid (tvalid), 41 | .o_tready (tready), 42 | .o_uart_tx (o_uart_tx)); 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /rtl/corescore_icesugar.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_icesugar 3 | ( 4 | output wire g, 5 | output wire b, 6 | output wire r, 7 | output wire o_uart_tx); 8 | 9 | wire clk48; 10 | wire clk; 11 | wire locked; 12 | 13 | 14 | SB_HFOSC inthosc 15 | ( 16 | .CLKHFPU(1'b1), 17 | .CLKHFEN(1'b1), 18 | .CLKHF(clk48)); 19 | 20 | SB_PLL40_CORE 21 | #( 22 | .FEEDBACK_PATH("SIMPLE"), 23 | .DIVR(4'b0010), 24 | .DIVF(7'b0111111), 25 | .DIVQ(3'b110), 26 | .FILTER_RANGE(3'b001)) 27 | pll 28 | (.LOCK(locked), 29 | .RESETB(1'b1), 30 | .BYPASS(1'b0), 31 | .REFERENCECLK(clk48), 32 | .PLLOUTCORE(clk)); 33 | 34 | SB_RGBA_DRV 35 | #( 36 | .CURRENT_MODE ("0b1"), 37 | .RGB0_CURRENT ("0b000111"), 38 | .RGB1_CURRENT ("0b000111"), 39 | .RGB2_CURRENT ("0b000111")) 40 | RGBA_DRIVER 41 | ( 42 | .CURREN(1'b1), 43 | .RGBLEDEN(1'b1), 44 | .RGB0PWM(o_uart_tx), 45 | .RGB1PWM(o_uart_tx), 46 | .RGB2PWM(o_uart_tx), 47 | .RGB0(g), 48 | .RGB1(b), 49 | .RGB2(r)); 50 | 51 | reg rst = 1'b1; 52 | 53 | always @(posedge clk) 54 | rst <= !locked; 55 | 56 | parameter memfile_emitter = "emitter.hex"; 57 | 58 | wire [7:0] tdata; 59 | wire tlast; 60 | wire tvalid; 61 | wire tready; 62 | 63 | corescorecore corescorecore 64 | (.i_clk (clk), 65 | .i_rst (rst), 66 | .o_tdata (tdata), 67 | .o_tlast (tlast), 68 | .o_tvalid (tvalid), 69 | .i_tready (tready)); 70 | 71 | emitter #(.memfile (memfile_emitter)) emitter 72 | (.i_clk (clk), 73 | .i_rst (rst), 74 | .i_tdata (tdata), 75 | .i_tlast (tlast), 76 | .i_tvalid (tvalid), 77 | .o_tready (tready), 78 | .o_uart_tx (o_uart_tx)); 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /rtl/corescore_intel_a10gx_devkit.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module corescore_intel_a10gx_devkit 4 | ( 5 | input wire rstn, 6 | input wire clk50 7 | ); 8 | 9 | wire clk; 10 | wire rst; 11 | wire [7:0] tdata; 12 | wire tlast; 13 | wire tvalid; 14 | reg tready; 15 | reg [7:0] r_dat; 16 | wire r_ena; 17 | 18 | // ================================================================ 19 | // Generate 16MHz from 50MHz board Clock 20 | // ================================================================ 21 | intel_a10gx_devkit_clock_gen clock_gen 22 | ( 23 | .i_rst (~rstn), 24 | .i_clk (clk50), 25 | .o_clk (clk), 26 | .o_rst (rst) 27 | ); 28 | 29 | // ================================================================ 30 | // CPU Magic Inside 31 | // ================================================================ 32 | corescorecore corescorecore 33 | ( 34 | .i_clk (clk), 35 | .i_rst (rst), 36 | .o_tdata (tdata), 37 | .o_tlast (tlast), 38 | .o_tvalid (tvalid), 39 | .i_tready (tready) 40 | ); 41 | 42 | // ================================================================ 43 | // Pipeline response as UART expects 1 clk delay after r_ena goes active 44 | // before you can push characters into it. 45 | // ================================================================ 46 | always @(posedge clk) begin 47 | if (tvalid & r_ena) begin 48 | tready <= 1'b1; 49 | r_dat <= tdata; 50 | end else begin 51 | tready <= 1'b0; 52 | end 53 | end 54 | 55 | // ================================================================ 56 | // Instantiate the internal JTAG-UART interface as the GX Devkit has no UART pins. 57 | // 58 | // NOTE - UART will stall indefinety when its tx-fifo is full, 59 | // so you must run nios-terminal.exe to allow things to flow 60 | // ================================================================ 61 | alt_jtag_atlantic #( 62 | .INSTANCE_ID(0), 63 | .LOG2_RXFIFO_DEPTH(6), 64 | .LOG2_TXFIFO_DEPTH(6), 65 | .SLD_AUTO_INSTANCE_INDEX("YES") 66 | ) i_uart ( 67 | .clk (clk), 68 | .rst_n (~rst), 69 | .r_dat (r_dat), 70 | .r_ena (r_ena), 71 | .r_val (tready), 72 | // Not interested in RX 73 | .t_dat (), 74 | .t_dav (1'b1), 75 | .t_ena (), 76 | .t_pause() 77 | ); 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /rtl/corescore_intel_agilex7.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module corescore_intel_agilex7 4 | ( 5 | // input wire rstn, 6 | input wire i_clk, 7 | input wire i_rstn 8 | ); 9 | 10 | wire clk; 11 | wire rst; 12 | wire [7:0] tdata; 13 | wire tlast; 14 | wire tvalid; 15 | reg tready; 16 | reg [7:0] r_dat; 17 | wire r_ena; 18 | wire ninit_done; 19 | wire locked; 20 | 21 | reg rst_reg1; 22 | reg rst_reg2; 23 | 24 | assign rst = rst_reg2; 25 | 26 | // ================================================================ 27 | // CPU Magic Inside 28 | // ================================================================ 29 | corescorecore corescorecore 30 | ( 31 | .i_clk (clk), 32 | .i_rst (rst), 33 | .o_tdata (tdata), 34 | .o_tlast (tlast), 35 | .o_tvalid (tvalid), 36 | .i_tready (tready) 37 | ); 38 | 39 | // ================================================================ 40 | // Synchronize Reset 41 | // ================================================================ 42 | always @(posedge clk) begin 43 | if (!locked || !i_rstn) begin 44 | rst_reg1 <= 1'b1; 45 | rst_reg2 <= 1'b1; 46 | end else begin 47 | rst_reg1 <= 1'b0; 48 | rst_reg2 <= rst_reg1; 49 | end 50 | end 51 | 52 | // ================================================================ 53 | // Agilex Reset Release 54 | // ================================================================ 55 | altera_agilex_config_reset_release_endpoint config_reset_release_endpoint( 56 | .conf_reset(ninit_done) 57 | ); 58 | 59 | // ================================================================ 60 | // Basic Intel Parameterizable Macro for IOPLL 61 | // ================================================================ 62 | ipm_iopll_basic #( 63 | .REFERENCE_CLOCK_FREQUENCY ("100.0 MHz"), 64 | .N_CNT (1), 65 | .M_CNT (8), 66 | .C0_CNT (50), 67 | .C1_CNT (1), 68 | .C2_CNT (1), 69 | .C3_CNT (1), 70 | .C4_CNT (1), 71 | .C5_CNT (1), 72 | .C6_CNT (1) 73 | ) core_pll ( 74 | .refclk (i_clk), //input, width = 1 75 | .reset (ninit_done), //input, width = 1 76 | .outclk0 (clk), //output, width = 1 77 | .outclk1 (), //output, width = 1 78 | .outclk2 (), //output, width = 1 79 | .outclk3 (), //output, width = 1 80 | .outclk4 (), //output, width = 1 81 | .outclk5 (), //output, width = 1 82 | .outclk6 (), //output, width = 1 83 | .locked (locked) //output, width = 1 84 | ); 85 | 86 | // ================================================================ 87 | // Pipeline response as UART expects 1 clk delay after r_ena goes active 88 | // before you can push characters into it. 89 | // ================================================================ 90 | always @(posedge clk) begin 91 | if (tvalid & r_ena) begin 92 | tready <= 1'b1; 93 | r_dat <= tdata; 94 | end else begin 95 | tready <= 1'b0; 96 | end 97 | end 98 | 99 | // ================================================================ 100 | // Instantiate the internal JTAG-UART interface as the GX Devkit has no UART pins. 101 | // 102 | // NOTE - UART will stall indefinety when its tx-fifo is full, 103 | // so you must run nios-terminal.exe to allow things to flow 104 | // ================================================================ 105 | alt_jtag_atlantic #( 106 | .INSTANCE_ID(0), 107 | .LOG2_RXFIFO_DEPTH(6), 108 | .LOG2_TXFIFO_DEPTH(6), 109 | .SLD_AUTO_INSTANCE_INDEX("YES") 110 | ) i_uart ( 111 | .clk (clk), 112 | .rst_n (~rst), 113 | .r_dat (r_dat), 114 | .r_ena (r_ena), 115 | .r_val (tready), 116 | // Not interested in RX 117 | .t_dat (), 118 | .t_dav (1'b1), 119 | .t_ena (), 120 | .t_pause() 121 | ); 122 | 123 | endmodule 124 | -------------------------------------------------------------------------------- /rtl/corescore_intel_cyc10lp_devkit.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_intel_cyc10lp_devkit 3 | ( 4 | input wire clk50, 5 | output wire uart_txd); 6 | 7 | wire clk; 8 | wire rst; 9 | 10 | intel_cyc10lp_devkit_clock_gen clock_gen 11 | (.i_clk (clk50), 12 | .o_clk (clk), 13 | .o_rst (rst)); 14 | 15 | parameter memfile_emitter = "emitter.hex"; 16 | 17 | wire [7:0] tdata; 18 | wire tlast; 19 | wire tvalid; 20 | wire tready; 21 | 22 | corescorecore corescorecore 23 | (.i_clk (clk), 24 | .i_rst (rst), 25 | .o_tdata (tdata), 26 | .o_tlast (tlast), 27 | .o_tvalid (tvalid), 28 | .i_tready (tready)); 29 | 30 | emitter #(.memfile (memfile_emitter)) emitter 31 | (.i_clk (clk), 32 | .i_rst (rst), 33 | .i_tdata (tdata), 34 | .i_tlast (tlast), 35 | .i_tvalid (tvalid), 36 | .o_tready (tready), 37 | .o_uart_tx (uart_txd)); 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /rtl/corescore_intel_max10_devkit.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_intel_max10_devkit 3 | ( 4 | input wire clk50, 5 | output wire led0, 6 | output wire uart_txd); 7 | 8 | wire clk; 9 | wire rst; 10 | 11 | //Mirror UART output to LED 12 | assign led0 = uart_txd; 13 | 14 | intel_max10_devkit_clock_gen clock_gen 15 | (.i_clk (clk50), 16 | .o_clk (clk), 17 | .o_rst (rst)); 18 | 19 | parameter memfile_emitter = "emitter.hex"; 20 | 21 | wire [7:0] tdata; 22 | wire tlast; 23 | wire tvalid; 24 | wire tready; 25 | 26 | corescorecore corescorecore 27 | (.i_clk (clk), 28 | .i_rst (rst), 29 | .o_tdata (tdata), 30 | .o_tlast (tlast), 31 | .o_tvalid (tvalid), 32 | .i_tready (tready)); 33 | 34 | emitter #(.memfile (memfile_emitter)) emitter 35 | (.i_clk (clk), 36 | .i_rst (rst), 37 | .i_tdata (tdata), 38 | .i_tlast (tlast), 39 | .i_tvalid (tvalid), 40 | .o_tready (tready), 41 | .o_uart_tx (uart_txd)); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /rtl/corescore_intel_s10gx_devkit.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module corescore_intel_s10gx_devkit 4 | ( 5 | input wire rstn, 6 | input wire clk50 7 | ); 8 | 9 | wire clk; 10 | wire rst; 11 | wire [7:0] tdata; 12 | wire tlast; 13 | wire tvalid; 14 | reg tready; 15 | reg [7:0] r_dat; 16 | wire r_ena; 17 | wire locked; 18 | 19 | // ================================================================ 20 | // Generate 16MHz from 50MHz board Clock 21 | // ================================================================ 22 | intel_s10gx_pll clock_gen 23 | ( 24 | .rst (~rstn), 25 | .refclk (clk50), 26 | .outclk_0 (clk), 27 | .locked (locked) 28 | ); 29 | 30 | assign rst = ~locked; 31 | 32 | // ================================================================ 33 | // CPU Magic Inside 34 | // ================================================================ 35 | corescorecore corescorecore 36 | ( 37 | .i_clk (clk), 38 | .i_rst (rst), 39 | .o_tdata (tdata), 40 | .o_tlast (tlast), 41 | .o_tvalid (tvalid), 42 | .i_tready (tready) 43 | ); 44 | 45 | // ================================================================ 46 | // Pipeline response as UART expects 1 clk delay after r_ena goes active 47 | // before you can push characters into it. 48 | // ================================================================ 49 | always @(posedge clk) begin 50 | if (tvalid & r_ena) begin 51 | tready <= 1'b1; 52 | r_dat <= tdata; 53 | end else begin 54 | tready <= 1'b0; 55 | end 56 | end 57 | 58 | // ================================================================ 59 | // Instantiate the internal JTAG-UART interface as the GX Devkit has no UART pins. 60 | // 61 | // NOTE - UART will stall indefinety when its tx-fifo is full, 62 | // so you must run nios-terminal.exe to allow things to flow 63 | // ================================================================ 64 | alt_jtag_atlantic #( 65 | .INSTANCE_ID(0), 66 | .LOG2_RXFIFO_DEPTH(6), 67 | .LOG2_TXFIFO_DEPTH(6), 68 | .SLD_AUTO_INSTANCE_INDEX("YES") 69 | ) i_uart ( 70 | .clk (clk), 71 | .rst_n (~rst), 72 | .r_dat (r_dat), 73 | .r_ena (r_ena), 74 | .r_val (tready), 75 | // Not interested in RX 76 | .t_dat (), 77 | .t_dav (1'b1), 78 | .t_ena (), 79 | .t_pause() 80 | ); 81 | 82 | endmodule 83 | -------------------------------------------------------------------------------- /rtl/corescore_kc705.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_kc705 3 | ( 4 | input wire i_clk_p, 5 | input wire i_clk_n, 6 | output wire q, 7 | output wire o_uart_tx); 8 | 9 | wire i_clk; 10 | wire clk; 11 | wire rst; 12 | 13 | //Mirror UART output to LED 14 | assign q = o_uart_tx; 15 | 16 | IBUFDS ibufds 17 | (.I (i_clk_p), 18 | .IB (i_clk_n), 19 | .O (i_clk)); 20 | 21 | corescore_kc705_clock_gen 22 | clock_gen 23 | (.i_clk (i_clk), 24 | .o_clk (clk), 25 | .o_rst (rst)); 26 | 27 | parameter memfile_emitter = "emitter.hex"; 28 | 29 | wire [7:0] tdata; 30 | wire tlast; 31 | wire tvalid; 32 | wire tready; 33 | 34 | corescorecore corescorecore 35 | (.i_clk (clk), 36 | .i_rst (rst), 37 | .o_tdata (tdata), 38 | .o_tlast (tlast), 39 | .o_tvalid (tvalid), 40 | .i_tready (tready)); 41 | 42 | emitter #(.memfile (memfile_emitter)) emitter 43 | (.i_clk (clk), 44 | .i_rst (rst), 45 | .i_tdata (tdata), 46 | .i_tlast (tlast), 47 | .i_tvalid (tvalid), 48 | .o_tready (tready), 49 | .o_uart_tx (o_uart_tx)); 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /rtl/corescore_kc705_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_kc705_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | PLLE2_BASE 12 | #(.BANDWIDTH("OPTIMIZED"), 13 | .CLKFBOUT_MULT(8), 14 | .CLKIN1_PERIOD(5.0), //200MHz 15 | .CLKOUT0_DIVIDE(100), 16 | .DIVCLK_DIVIDE(1), 17 | .STARTUP_WAIT("FALSE")) 18 | PLLE2_BASE_inst 19 | (.CLKOUT0(o_clk), // 16MHz 20 | .CLKOUT1(), 21 | .CLKOUT2(), 22 | .CLKOUT3(), 23 | .CLKOUT4(), 24 | .CLKOUT5(), 25 | .CLKFBOUT(clkfb), 26 | .LOCKED(locked), 27 | .CLKIN1(i_clk), 28 | .PWRDWN(1'b0), 29 | .RST(1'b0), 30 | .CLKFBIN(clkfb)); 31 | 32 | always @(posedge o_clk) begin 33 | locked_r <= locked; 34 | o_rst <= !locked_r; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /rtl/corescore_marble.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_marble ( 3 | input wire i_clk_p, 4 | input wire i_clk_n, 5 | output wire o_uart_tx, 6 | output wire o_uart_tx2, 7 | input wire i_uart_rx 8 | ); 9 | 10 | assign o_uart_tx2 = o_uart_tx; 11 | 12 | wire main_crg_clkin, main_crg_clkout0; 13 | IBUFDS IBUFDS( 14 | .I(i_clk_p), 15 | .IB(i_clk_n), 16 | .O(main_crg_clkin) 17 | ); 18 | 19 | // Create a 100 MHz clock using MMCME 20 | // baudrate = 57600 * 100 / 16 = 360000 baud / s 21 | wire builder_mmcm_fb; 22 | wire locked; 23 | MMCME2_ADV #( 24 | .BANDWIDTH("OPTIMIZED"), 25 | .CLKFBOUT_MULT_F(11), 26 | .CLKIN1_PERIOD(8.0), 27 | .CLKOUT0_DIVIDE_F(13.75), 28 | .CLKOUT0_PHASE(1'd0), 29 | .DIVCLK_DIVIDE(1'd1), 30 | .REF_JITTER1(0.01) 31 | ) MMCME2_ADV ( 32 | .CLKFBIN(builder_mmcm_fb), 33 | .CLKIN1(main_crg_clkin), 34 | .PWRDWN(0), 35 | .RST(), 36 | .CLKFBOUT(builder_mmcm_fb), 37 | .CLKOUT0(main_crg_clkout0), 38 | .LOCKED(locked) 39 | ); 40 | 41 | wire clk; 42 | reg rst = 1; 43 | reg locked_r = 0; 44 | 45 | BUFG BUFG( 46 | .I(main_crg_clkout0), 47 | .O(clk) 48 | ); 49 | 50 | always @(posedge clk) begin 51 | locked_r <= locked; 52 | rst <= !locked_r; 53 | end 54 | 55 | parameter memfile_emitter = "emitter.hex"; 56 | 57 | wire [7:0] tdata; 58 | wire tlast; 59 | wire tvalid; 60 | wire tready; 61 | 62 | corescorecore corescorecore 63 | (.i_clk (clk), 64 | .i_rst (rst), 65 | .o_tdata (tdata), 66 | .o_tlast (tlast), 67 | .o_tvalid (tvalid), 68 | .i_tready (tready)); 69 | 70 | emitter #(.memfile (memfile_emitter)) emitter 71 | (.i_clk (clk), 72 | .i_rst (rst), 73 | .i_tdata (tdata), 74 | .i_tlast (tlast), 75 | .i_tvalid (tvalid), 76 | .o_tready (tready), 77 | .o_uart_tx (o_uart_tx)); 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /rtl/corescore_max1000.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_max1000 3 | ( 4 | input wire CLK12M, 5 | output wire q, 6 | output wire o_uart_tx); 7 | 8 | wire clk; 9 | wire rst; 10 | 11 | //Mirror UART output to LED 12 | assign q = o_uart_tx; 13 | 14 | max1000_clock_gen clock_gen 15 | (.i_clk (CLK12M), 16 | .o_clk (clk), 17 | .o_rst (rst)); 18 | 19 | parameter memfile_emitter = "emitter.hex"; 20 | 21 | wire [7:0] tdata; 22 | wire tlast; 23 | wire tvalid; 24 | wire tready; 25 | 26 | corescorecore corescorecore 27 | (.i_clk (clk), 28 | .i_rst (rst), 29 | .o_tdata (tdata), 30 | .o_tlast (tlast), 31 | .o_tvalid (tvalid), 32 | .i_tready (tready)); 33 | 34 | emitter #(.memfile (memfile_emitter)) emitter 35 | (.i_clk (clk), 36 | .i_rst (rst), 37 | .i_tdata (tdata), 38 | .i_tlast (tlast), 39 | .i_tvalid (tvalid), 40 | .o_tready (tready), 41 | .o_uart_tx (o_uart_tx)); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /rtl/corescore_nexys_a7.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_nexys_a7 3 | ( 4 | input wire i_clk, 5 | output wire o_uart_tx); 6 | 7 | wire clk; 8 | wire rst; 9 | 10 | nexys_a7_clock_gen clock_gen 11 | (.i_clk (i_clk), 12 | .o_clk (clk), 13 | .o_rst (rst)); 14 | 15 | parameter memfile_emitter = "emitter.hex"; 16 | 17 | wire [7:0] tdata; 18 | wire tlast; 19 | wire tvalid; 20 | wire tready; 21 | 22 | corescorecore corescorecore 23 | (.i_clk (clk), 24 | .i_rst (rst), 25 | .o_tdata (tdata), 26 | .o_tlast (tlast), 27 | .o_tvalid (tvalid), 28 | .i_tready (tready)); 29 | 30 | emitter #(.memfile (memfile_emitter)) emitter 31 | (.i_clk (clk), 32 | .i_rst (rst), 33 | .i_tdata (tdata), 34 | .i_tlast (tlast), 35 | .i_tvalid (tvalid), 36 | .o_tready (tready), 37 | .o_uart_tx (o_uart_tx)); 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /rtl/corescore_nexys_video.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_nexys_video 3 | ( 4 | input wire i_clk, 5 | output wire o_uart_tx); 6 | 7 | wire clk; 8 | wire rst; 9 | 10 | nexys_video_clock_gen clock_gen 11 | (.i_clk (i_clk), 12 | .o_clk (clk), 13 | .o_rst (rst)); 14 | 15 | parameter memfile_emitter = "emitter.hex"; 16 | 17 | wire [7:0] tdata; 18 | wire tlast; 19 | wire tvalid; 20 | wire tready; 21 | 22 | corescorecore corescorecore 23 | (.i_clk (clk), 24 | .i_rst (rst), 25 | .o_tdata (tdata), 26 | .o_tlast (tlast), 27 | .o_tvalid (tvalid), 28 | .i_tready (tready)); 29 | 30 | emitter #(.memfile (memfile_emitter)) emitter 31 | (.i_clk (clk), 32 | .i_rst (rst), 33 | .i_tdata (tdata), 34 | .i_tlast (tlast), 35 | .i_tvalid (tvalid), 36 | .o_tready (tready), 37 | .o_uart_tx (o_uart_tx)); 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /rtl/corescore_polarfire.v: -------------------------------------------------------------------------------- 1 | module corescore_polarfire 2 | ( 3 | input wire i_clk, 4 | input wire resetbtn, 5 | output wire q, 6 | output reg h, 7 | output wire o_uart_tx); 8 | 9 | wire clk; 10 | wire rst; 11 | 12 | //Mirror UART output to LED 13 | assign q = o_uart_tx; 14 | 15 | assign rst = ~resetbtn; 16 | 17 | PF_CCC_C0_PF_CCC_C0_0_PF_CCC clock_gen 18 | (.REF_CLK_0 (i_clk), 19 | .OUT0_FABCLK_0 (clk)); 20 | 21 | parameter memfile_emitter = "emitter.hex"; 22 | 23 | wire [7:0] tdata; 24 | wire tlast; 25 | wire tvalid; 26 | wire tready; 27 | 28 | corescorecore corescorecore 29 | (.i_clk (clk), 30 | .i_rst (rst), 31 | .o_tdata (tdata), 32 | .o_tlast (tlast), 33 | .o_tvalid (tvalid), 34 | .i_tready (tready)); 35 | 36 | emitter #(.memfile (memfile_emitter)) emitter 37 | (.i_clk (clk), 38 | .i_rst (rst), 39 | .i_tdata (tdata), 40 | .i_tlast (tlast), 41 | .i_tvalid (tvalid), 42 | .o_tready (tready), 43 | .o_uart_tx (o_uart_tx)); 44 | 45 | 46 | // Heartbeat led 47 | reg [$clog2(16000000)-1:0] count = 0; 48 | always @(posedge clk) begin 49 | if (rst) begin 50 | count <= 0; 51 | h <= 0; 52 | end else 53 | count <= count + 1; 54 | if (count == 16000000-1) begin 55 | h <= !h; 56 | count <= 0; 57 | end 58 | end 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /rtl/corescore_polarfire_eval_clock_gen.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/100 ps 2 | // Version: v12.5 12.900.10.16 3 | 4 | 5 | module PF_CCC_C0_PF_CCC_C0_0_PF_CCC( 6 | OUT0_FABCLK_0, 7 | PLL_LOCK_0, 8 | REF_CLK_0, 9 | ); 10 | output OUT0_FABCLK_0; 11 | output PLL_LOCK_0; 12 | input REF_CLK_0; 13 | 14 | wire gnd_net, vcc_net, pll_inst_0_clkint_0; 15 | 16 | CLKINT clkint_0 (.A(pll_inst_0_clkint_0), .Y(OUT0_FABCLK_0)); 17 | PLL #( .VCOFREQUENCY(4992), .DELAY_LINE_SIMULATION_MODE(""), .DATA_RATE(0.0) 18 | , .FORMAL_NAME(""), .INTERFACE_NAME(""), .INTERFACE_LEVEL(3'b0) 19 | , .SOFTRESET(1'b0), .SOFT_POWERDOWN_N(1'b1), .RFDIV_EN(1'b1), .OUT0_DIV_EN(1'b1) 20 | , .OUT1_DIV_EN(1'b0), .OUT2_DIV_EN(1'b0), .OUT3_DIV_EN(1'b0), .SOFT_REF_CLK_SEL(1'b0) 21 | , .RESET_ON_LOCK(1'b1), .BYPASS_CLK_SEL(4'b0), .BYPASS_GO_EN_N(1'b1) 22 | , .BYPASS_PLL(4'b0), .BYPASS_OUT_DIVIDER(4'b0), .FF_REQUIRES_LOCK(1'b0) 23 | , .FSE_N(1'b0), .FB_CLK_SEL_0(2'b00), .FB_CLK_SEL_1(1'b0), .RFDIV(6'b011001) 24 | , .FRAC_EN(1'b0), .FRAC_DAC_EN(1'b0), .DIV0_RST_DELAY(3'b000) 25 | , .DIV0_VAL(7'b1001110), .DIV1_RST_DELAY(3'b0), .DIV1_VAL(7'b1) 26 | , .DIV2_RST_DELAY(3'b0), .DIV2_VAL(7'b1), .DIV3_RST_DELAY(3'b0) 27 | , .DIV3_VAL(7'b1), .DIV3_CLK_SEL(1'b0), .BW_INT_CTRL(2'b0), .BW_PROP_CTRL(2'b01) 28 | , .IREF_EN(1'b1), .IREF_TOGGLE(1'b0), .LOCK_CNT(4'b1000), .DESKEW_CAL_CNT(3'b110) 29 | , .DESKEW_CAL_EN(1'b1), .DESKEW_CAL_BYPASS(1'b0), .SYNC_REF_DIV_EN(1'b0) 30 | , .SYNC_REF_DIV_EN_2(1'b0), .OUT0_PHASE_SEL(3'b000), .OUT1_PHASE_SEL(3'b0) 31 | , .OUT2_PHASE_SEL(3'b0), .OUT3_PHASE_SEL(3'b0), .SOFT_LOAD_PHASE_N(1'b1) 32 | , .SSM_DIV_VAL(6'b1), .FB_FRAC_VAL(24'b0), .SSM_SPREAD_MODE(1'b0) 33 | , .SSM_MODULATION(5'b00101), .FB_INT_VAL(12'b100111000000), .SSM_EN_N(1'b1) 34 | , .SSM_EXT_WAVE_EN(2'b0), .SSM_EXT_WAVE_MAX_ADDR(8'b0), .SSM_RANDOM_EN(1'b0) 35 | , .SSM_RANDOM_PATTERN_SEL(3'b0), .CDMUX0_SEL(2'b0), .CDMUX1_SEL(1'b1) 36 | , .CDMUX2_SEL(1'b0), .CDELAY0_SEL(8'b0), .CDELAY0_EN(1'b0), .DRI_EN(1'b1) 37 | ) pll_inst_0 (.LOCK(PLL_LOCK_0), .SSCG_WAVE_TABLE_ADDR({nc0, 38 | nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .DELAY_LINE_OUT_OF_RANGE() 39 | , .POWERDOWN_N(vcc_net), .OUT0_EN(vcc_net), .OUT1_EN(gnd_net), 40 | .OUT2_EN(gnd_net), .OUT3_EN(gnd_net), .REF_CLK_SEL(gnd_net), 41 | .BYPASS_EN_N(vcc_net), .LOAD_PHASE_N(vcc_net), 42 | .SSCG_WAVE_TABLE({gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, 43 | gnd_net, gnd_net, gnd_net}), .PHASE_DIRECTION(gnd_net), 44 | .PHASE_ROTATE(gnd_net), .PHASE_OUT0_SEL(gnd_net), 45 | .PHASE_OUT1_SEL(gnd_net), .PHASE_OUT2_SEL(gnd_net), 46 | .PHASE_OUT3_SEL(gnd_net), .DELAY_LINE_MOVE(gnd_net), 47 | .DELAY_LINE_DIRECTION(gnd_net), .DELAY_LINE_WIDE(gnd_net), 48 | .DELAY_LINE_LOAD(vcc_net), .REFCLK_SYNC_EN(gnd_net), 49 | .REF_CLK_0(REF_CLK_0), .REF_CLK_1(gnd_net), .FB_CLK(gnd_net), 50 | .OUT0(pll_inst_0_clkint_0), .OUT1(), .OUT2(), .OUT3(), 51 | .DRI_CLK(gnd_net), .DRI_CTRL({gnd_net, gnd_net, gnd_net, 52 | gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, 53 | gnd_net}), .DRI_WDATA({gnd_net, gnd_net, gnd_net, gnd_net, 54 | gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, 55 | gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, 56 | gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, 57 | gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, 58 | gnd_net}), .DRI_ARST_N(vcc_net), .DRI_RDATA({nc8, nc9, nc10, 59 | nc11, nc12, nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20, 60 | nc21, nc22, nc23, nc24, nc25, nc26, nc27, nc28, nc29, nc30, 61 | nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40}), 62 | .DRI_INTERRUPT()); 63 | VCC vcc_inst (.Y(vcc_net)); 64 | GND gnd_inst (.Y(gnd_net)); 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /rtl/corescore_sockit.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_sockit 3 | ( 4 | input wire i_clk, 5 | input wire i_rst_n, 6 | output wire q, 7 | output wire uart_txd); 8 | 9 | wire clk; 10 | wire rst; 11 | 12 | //Mirror UART output to LED 13 | assign q = uart_txd; 14 | 15 | de0_nano_clock_gen clock_gen 16 | (.i_clk (i_clk), 17 | .i_rst (!i_rst_n), 18 | .o_clk (clk), 19 | .o_rst (rst)); 20 | 21 | parameter memfile_emitter = "emitter.hex"; 22 | 23 | wire [7:0] tdata; 24 | wire tlast; 25 | wire tvalid; 26 | wire tready; 27 | 28 | corescorecore corescorecore 29 | (.i_clk (clk), 30 | .i_rst (rst), 31 | .o_tdata (tdata), 32 | .o_tlast (tlast), 33 | .o_tvalid (tvalid), 34 | .i_tready (tready)); 35 | 36 | emitter #(.memfile (memfile_emitter)) emitter 37 | (.i_clk (clk), 38 | .i_rst (rst), 39 | .i_tdata (tdata), 40 | .i_tlast (tlast), 41 | .i_tvalid (tvalid), 42 | .o_tready (tready), 43 | .o_uart_tx (uart_txd)); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /rtl/corescore_storeypeak.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_storeypeak 3 | ( 4 | input wire i_clk, 5 | output wire q, 6 | output wire o_uart_tx); 7 | 8 | wire clk; 9 | wire rst; 10 | 11 | //Mirror UART output to LED 12 | assign q = ~o_uart_tx; 13 | 14 | storeypeak_clock_gen clock_gen 15 | (.i_clk (i_clk), 16 | .o_clk (clk), 17 | .o_rst (rst)); 18 | 19 | parameter memfile_emitter = "emitter.hex"; 20 | 21 | wire [7:0] tdata; 22 | wire tlast; 23 | wire tvalid; 24 | wire tready; 25 | 26 | corescorecore corescorecore 27 | (.i_clk (clk), 28 | .i_rst (rst), 29 | .o_tdata (tdata), 30 | .o_tlast (tlast), 31 | .o_tvalid (tvalid), 32 | .i_tready (tready)); 33 | 34 | emitter #(.memfile (memfile_emitter)) emitter 35 | (.i_clk (clk), 36 | .i_rst (rst), 37 | .i_tdata (tdata), 38 | .i_tlast (tlast), 39 | .i_tvalid (tvalid), 40 | .o_tready (tready), 41 | .o_uart_tx (o_uart_tx)); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /rtl/corescore_tinyfpga_bx.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_tinyfpga_bx 3 | (input wire i_clk, 4 | inout wire pin_usb_p, 5 | inout wire pin_usb_n, 6 | output wire pin_pu); 7 | 8 | wire clk; 9 | wire clk_locked; 10 | 11 | // USB Host Detect Pull Up 12 | assign pin_pu = 1'b1; 13 | 14 | pll pll48 15 | (.clock_in (i_clk), 16 | .clock_out (clk), 17 | .locked (clk_locked)); 18 | 19 | // Generate reset signal 20 | reg [5:0] reset_cnt = 0; 21 | wire reset = ~reset_cnt[5]; 22 | always @(posedge clk) 23 | if ( clk_locked ) 24 | reset_cnt <= reset_cnt + reset; 25 | 26 | reg rst; 27 | reg rst_r; 28 | 29 | always @(posedge i_clk) begin 30 | rst_r <= reset; 31 | rst <= rst_r; 32 | end 33 | wire [7:0] tdata; 34 | wire tvalid; 35 | wire tready; 36 | 37 | wire [7:0] usb_tdata; 38 | wire usb_tvalid; 39 | wire usb_tready; 40 | 41 | corescorecore corescorecore 42 | (.i_clk (i_clk), 43 | .i_rst (rst), 44 | .o_tdata (tdata), 45 | .o_tlast (), 46 | .o_tvalid (tvalid), 47 | .i_tready (tready)); 48 | 49 | axis_async_fifo 50 | #( 51 | .DEPTH(4), 52 | .DATA_WIDTH(8), 53 | .KEEP_ENABLE(0), 54 | .KEEP_WIDTH(0), 55 | .LAST_ENABLE(0), 56 | .ID_ENABLE(0), 57 | .ID_WIDTH(0), 58 | .DEST_ENABLE(0), 59 | .DEST_WIDTH(0), 60 | .USER_ENABLE(0), 61 | .USER_WIDTH(0), 62 | .FRAME_FIFO(0), 63 | .USER_BAD_FRAME_VALUE(0), 64 | .USER_BAD_FRAME_MASK(0), 65 | .DROP_BAD_FRAME(0), 66 | .DROP_WHEN_FULL(0)) 67 | UUT 68 | (// Common reset 69 | .async_rst (rst), 70 | // AXI input 71 | .s_clk(i_clk), 72 | .s_axis_tdata(tdata), 73 | .s_axis_tkeep(), 74 | .s_axis_tvalid(tvalid), 75 | .s_axis_tready(tready), 76 | .s_axis_tlast(), 77 | .s_axis_tid(), 78 | .s_axis_tdest(), 79 | .s_axis_tuser(), 80 | // AXI output 81 | .m_clk(clk), 82 | .m_axis_tdata (usb_tdata), 83 | .m_axis_tkeep (), 84 | .m_axis_tvalid (usb_tvalid), 85 | .m_axis_tready (usb_tready), 86 | .m_axis_tlast (), 87 | .m_axis_tid (), 88 | .m_axis_tdest (), 89 | .m_axis_tuser (), 90 | // Status 91 | .s_status_overflow (), 92 | .s_status_bad_frame (), 93 | .s_status_good_frame (), 94 | .m_status_overflow (), 95 | .m_status_bad_frame (), 96 | .m_status_good_frame ()); 97 | 98 | wire usb_p_tx; 99 | wire usb_n_tx; 100 | wire usb_p_rx; 101 | wire usb_n_rx; 102 | wire usb_tx_en; 103 | 104 | usb_uart_core uart 105 | ( 106 | .clk_48mhz (clk), 107 | .reset (reset), 108 | // pins - these must be connected properly to the outside world. See below. 109 | .usb_p_tx (usb_p_tx), 110 | .usb_n_tx (usb_n_tx), 111 | .usb_p_rx (usb_p_rx), 112 | .usb_n_rx (usb_n_rx), 113 | .usb_tx_en (usb_tx_en), 114 | // uart pipeline in 115 | .uart_in_data (usb_tdata), 116 | .uart_in_valid (usb_tvalid), 117 | .uart_in_ready (usb_tready), 118 | // uart pipeline out 119 | .uart_out_data (), 120 | .uart_out_valid (/*tvalid*/), 121 | .uart_out_ready (tready), 122 | .debug ()); 123 | 124 | wire usb_p_in; 125 | wire usb_n_in; 126 | 127 | assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_in; 128 | assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_in; 129 | 130 | SB_IO 131 | #(.PIN_TYPE(6'b 1010_01), // PIN_OUTPUT_TRISTATE - PIN_INPUT 132 | .PULLUP(1'b 0)) 133 | iobuf_usbp 134 | (.PACKAGE_PIN (pin_usb_p), 135 | .OUTPUT_ENABLE (usb_tx_en), 136 | .D_OUT_0 (usb_p_tx), 137 | .D_IN_0 (usb_p_in)); 138 | 139 | SB_IO #( 140 | .PIN_TYPE(6'b 1010_01), // PIN_OUTPUT_TRISTATE - PIN_INPUT 141 | .PULLUP(1'b 0) 142 | ) iobuf_usbn ( 143 | .PACKAGE_PIN(pin_usb_n), 144 | .OUTPUT_ENABLE(usb_tx_en), 145 | .D_OUT_0(usb_n_tx), 146 | .D_IN_0(usb_n_in) 147 | ); 148 | 149 | endmodule 150 | -------------------------------------------------------------------------------- /rtl/corescore_ulx3s.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_ulx3s 3 | (input wire i_clk, 4 | input wire btn0, 5 | output wire wifi_gpio0, 6 | output wire o_uart_tx, 7 | output wire q); 8 | 9 | wire clk; 10 | wire rst; 11 | 12 | assign q = o_uart_tx; 13 | assign wifi_gpio0 = btn0; 14 | 15 | corescore_ulx3s_clock_gen clock_gen 16 | (.i_clk (i_clk), 17 | .i_rst (!btn0), 18 | .o_clk (clk), 19 | .o_rst (rst)); 20 | 21 | parameter memfile_emitter = "emitter.hex"; 22 | 23 | wire [7:0] tdata; 24 | wire tlast; 25 | wire tvalid; 26 | wire tready; 27 | 28 | corescorecore corescorecore 29 | (.i_clk (clk), 30 | .i_rst (rst), 31 | .o_tdata (tdata), 32 | .o_tlast (tlast), 33 | .o_tvalid (tvalid), 34 | .i_tready (tready)); 35 | 36 | emitter #(.memfile (memfile_emitter)) emitter 37 | (.i_clk (clk), 38 | .i_rst (rst), 39 | .i_tdata (tdata), 40 | .i_tlast (tlast), 41 | .i_tvalid (tvalid), 42 | .o_tready (tready), 43 | .o_uart_tx (o_uart_tx)); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /rtl/corescore_ulx3s_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_ulx3s_clock_gen 3 | ( 4 | input i_clk, 5 | input i_rst, 6 | output o_clk, 7 | output o_rst); 8 | 9 | wire locked; 10 | 11 | reg [1:0] rst_reg; 12 | always @(posedge o_clk) 13 | if (i_rst) 14 | rst_reg <= 2'b11; 15 | else 16 | rst_reg <= {!locked, rst_reg[1]}; 17 | 18 | assign o_rst = rst_reg[0]; 19 | 20 | pll pll 21 | (.clki (i_clk), 22 | .clko (o_clk), 23 | .locked (locked)); 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /rtl/corescore_upduino2.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_upduino2 3 | ( 4 | output wire g, 5 | output wire b, 6 | output wire r, 7 | output wire o_uart_tx); 8 | 9 | wire clk48; 10 | wire clk; 11 | wire locked; 12 | 13 | 14 | SB_HFOSC inthosc 15 | ( 16 | .CLKHFPU(1'b1), 17 | .CLKHFEN(1'b1), 18 | .CLKHF(clk48)); 19 | 20 | SB_PLL40_CORE 21 | #( 22 | .FEEDBACK_PATH("SIMPLE"), 23 | .DIVR(4'b0010), 24 | .DIVF(7'b0111111), 25 | .DIVQ(3'b110), 26 | .FILTER_RANGE(3'b001)) 27 | pll 28 | (.LOCK(locked), 29 | .RESETB(1'b1), 30 | .BYPASS(1'b0), 31 | .REFERENCECLK(clk48), 32 | .PLLOUTCORE(clk)); 33 | 34 | SB_RGBA_DRV 35 | #( 36 | .CURRENT_MODE ("0b1"), 37 | .RGB0_CURRENT ("0b000111"), 38 | .RGB1_CURRENT ("0b000111"), 39 | .RGB2_CURRENT ("0b000111")) 40 | RGBA_DRIVER 41 | ( 42 | .CURREN(1'b1), 43 | .RGBLEDEN(1'b1), 44 | .RGB0PWM(o_uart_tx), 45 | .RGB1PWM(o_uart_tx), 46 | .RGB2PWM(o_uart_tx), 47 | .RGB0(g), 48 | .RGB1(b), 49 | .RGB2(r)); 50 | 51 | reg rst = 1'b1; 52 | 53 | always @(posedge clk) 54 | rst <= !locked; 55 | 56 | parameter memfile_emitter = "emitter.hex"; 57 | 58 | wire [7:0] tdata; 59 | wire tlast; 60 | wire tvalid; 61 | wire tready; 62 | 63 | corescorecore corescorecore 64 | (.i_clk (clk), 65 | .i_rst (rst), 66 | .o_tdata (tdata), 67 | .o_tlast (tlast), 68 | .o_tvalid (tvalid), 69 | .i_tready (tready)); 70 | 71 | emitter #(.memfile (memfile_emitter)) emitter 72 | (.i_clk (clk), 73 | .i_rst (rst), 74 | .i_tdata (tdata), 75 | .i_tlast (tlast), 76 | .i_tvalid (tvalid), 77 | .o_tready (tready), 78 | .o_uart_tx (o_uart_tx)); 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /rtl/corescore_vcu118.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_vcu118 3 | ( 4 | input wire i_clk_p, 5 | input wire i_clk_n, 6 | output wire q, 7 | output wire o_uart_tx); 8 | 9 | wire i_clk; 10 | wire clk; 11 | wire rst; 12 | 13 | //Mirror UART output to LED 14 | assign q = o_uart_tx; 15 | 16 | IBUFDS ibufds 17 | (.I (i_clk_p), 18 | .IB (i_clk_n), 19 | .O (i_clk)); 20 | 21 | corescore_vcu118_clock_gen 22 | clock_gen 23 | (.i_clk (i_clk), 24 | .o_clk (clk), 25 | .o_rst (rst)); 26 | 27 | parameter memfile_emitter = "emitter.hex"; 28 | 29 | wire [7:0] tdata; 30 | wire tlast; 31 | wire tvalid; 32 | wire tready; 33 | 34 | corescorecore corescorecore 35 | (.i_clk (clk), 36 | .i_rst (rst), 37 | .o_tdata (tdata), 38 | .o_tlast (tlast), 39 | .o_tvalid (tvalid), 40 | .i_tready (tready)); 41 | 42 | emitter #(.memfile (memfile_emitter)) emitter 43 | (.i_clk (clk), 44 | .i_rst (rst), 45 | .i_tdata (tdata), 46 | .i_tlast (tlast), 47 | .i_tvalid (tvalid), 48 | .o_tready (tready), 49 | .o_uart_tx (o_uart_tx)); 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /rtl/corescore_vcu118_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_vcu118_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | MMCME4_ADV 12 | #(.DIVCLK_DIVIDE (5), 13 | .CLKFBOUT_MULT_F (48.000), 14 | .CLKOUT0_DIVIDE_F (75.0), 15 | .CLKIN1_PERIOD (8.0), //125MHz 16 | .STARTUP_WAIT ("FALSE")) 17 | mmcm 18 | (.CLKFBOUT (clkfb), 19 | .CLKFBOUTB (), 20 | .CLKOUT0 (o_clk), 21 | .CLKOUT0B (), 22 | .CLKOUT1 (), 23 | .CLKOUT1B (), 24 | .CLKOUT2 (), 25 | .CLKOUT2B (), 26 | .CLKOUT3 (), 27 | .CLKOUT3B (), 28 | .CLKOUT4 (), 29 | .CLKOUT5 (), 30 | .CLKOUT6 (), 31 | .CLKIN1 (i_clk), 32 | .CLKIN2 (1'b0), 33 | .CLKINSEL (1'b1), 34 | .LOCKED (locked), 35 | .PWRDWN (1'b0), 36 | .RST (1'b0), 37 | .CLKFBIN (clkfb)); 38 | 39 | always @(posedge o_clk) begin 40 | locked_r <= locked; 41 | o_rst <= !locked_r; 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /rtl/corescore_vcu128.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_vcu128 3 | ( 4 | input wire QDR4_CLK_100MHZ_P, 5 | input wire QDR4_CLK_100MHZ_N, 6 | output wire GPIO_LED_0_LS, 7 | output wire UART1_TXD); 8 | 9 | wire i_clk; 10 | wire clk; 11 | wire rst; 12 | 13 | //Mirror UART output to LED 14 | assign GPIO_LED_0_LS = UART1_TXD; 15 | 16 | IBUFGDS ibufds( 17 | .I (QDR4_CLK_100MHZ_P), 18 | .IB(QDR4_CLK_100MHZ_N), 19 | .O (i_clk)); 20 | 21 | corescore_vcu128_clock_gen 22 | clock_gen 23 | (.i_clk (i_clk), 24 | .o_clk (clk), 25 | .o_rst (rst)); 26 | 27 | parameter memfile_emitter = "emitter.hex"; 28 | 29 | wire [7:0] tdata; 30 | wire tlast; 31 | wire tvalid; 32 | wire tready; 33 | 34 | corescorecore corescorecore 35 | (.i_clk (clk), 36 | .i_rst (rst), 37 | .o_tdata (tdata), 38 | .o_tlast (tlast), 39 | .o_tvalid (tvalid), 40 | .i_tready (tready)); 41 | 42 | emitter #(.memfile (memfile_emitter)) emitter 43 | (.i_clk (clk), 44 | .i_rst (rst), 45 | .i_tdata (tdata), 46 | .i_tlast (tlast), 47 | .i_tvalid (tvalid), 48 | .o_tready (tready), 49 | .o_uart_tx (UART1_TXD)); 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /rtl/corescore_vcu128_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_vcu128_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | MMCME4_ADV 12 | #(.DIVCLK_DIVIDE (4), 13 | .CLKFBOUT_MULT_F (32.000), 14 | .CLKOUT0_DIVIDE_F (50.0), 15 | .CLKIN1_PERIOD (10.0), //100MHz 16 | .STARTUP_WAIT ("FALSE")) 17 | mmcm 18 | (.CLKFBOUT (clkfb), 19 | .CLKFBOUTB (), 20 | .CLKOUT0 (o_clk), // 16MHz 21 | .CLKOUT0B (), 22 | .CLKOUT1 (), 23 | .CLKOUT1B (), 24 | .CLKOUT2 (), 25 | .CLKOUT2B (), 26 | .CLKOUT3 (), 27 | .CLKOUT3B (), 28 | .CLKOUT4 (), 29 | .CLKOUT5 (), 30 | .CLKOUT6 (), 31 | .CLKIN1 (i_clk), 32 | .CLKIN2 (1'b0), 33 | .CLKINSEL (1'b1), 34 | .LOCKED (locked), 35 | .PWRDWN (1'b0), 36 | .RST (1'b0), 37 | .CLKFBIN (clkfb)); 38 | 39 | always @(posedge o_clk) begin 40 | locked_r <= locked; 41 | o_rst <= !locked_r; 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /rtl/corescore_vu19p.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_vu19p 3 | ( 4 | input wire CLK_100MHZ_P, 5 | input wire CLK_100MHZ_N, 6 | output wire UART_TXD); 7 | 8 | wire i_clk; 9 | wire clk; 10 | wire rst; 11 | 12 | IBUFGDS ibufds( 13 | .I (CLK_100MHZ_P), 14 | .IB(CLK_100MHZ_N), 15 | .O (i_clk)); 16 | 17 | corescore_vu19p_clock_gen 18 | clock_gen 19 | (.i_clk (i_clk), 20 | .o_clk (clk), 21 | .o_rst (rst)); 22 | 23 | parameter memfile_emitter = "emitter.hex"; 24 | 25 | wire [7:0] tdata; 26 | wire tlast; 27 | wire tvalid; 28 | wire tready; 29 | 30 | corescorecore corescorecore 31 | (.i_clk (clk), 32 | .i_rst (rst), 33 | .o_tdata (tdata), 34 | .o_tlast (tlast), 35 | .o_tvalid (tvalid), 36 | .i_tready (tready)); 37 | 38 | emitter #(.memfile (memfile_emitter)) emitter 39 | (.i_clk (clk), 40 | .i_rst (rst), 41 | .i_tdata (tdata), 42 | .i_tlast (tlast), 43 | .i_tvalid (tvalid), 44 | .o_tready (tready), 45 | .o_uart_tx (UART_TXD)); 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /rtl/corescore_vu19p_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_vu19p_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | MMCME4_ADV 12 | #(.DIVCLK_DIVIDE (4), 13 | .CLKFBOUT_MULT_F (32.000), 14 | .CLKOUT0_DIVIDE_F (50.0), 15 | .CLKIN1_PERIOD (10.0), //100MHz 16 | .STARTUP_WAIT ("FALSE")) 17 | mmcm 18 | (.CLKFBOUT (clkfb), 19 | .CLKFBOUTB (), 20 | .CLKOUT0 (o_clk), // 16MHz 21 | .CLKOUT0B (), 22 | .CLKOUT1 (), 23 | .CLKOUT1B (), 24 | .CLKOUT2 (), 25 | .CLKOUT2B (), 26 | .CLKOUT3 (), 27 | .CLKOUT3B (), 28 | .CLKOUT4 (), 29 | .CLKOUT5 (), 30 | .CLKOUT6 (), 31 | .CLKIN1 (i_clk), 32 | .CLKIN2 (1'b0), 33 | .CLKINSEL (1'b1), 34 | .LOCKED (locked), 35 | .PWRDWN (1'b0), 36 | .RST (1'b0), 37 | .CLKFBIN (clkfb)); 38 | 39 | always @(posedge o_clk) begin 40 | locked_r <= locked; 41 | o_rst <= !locked_r; 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /rtl/corescore_xyloni.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_xyloni 3 | ( 4 | input wire i_clk, 5 | input wire i_pll_locked, 6 | output wire q, 7 | output wire o_uart_tx); 8 | 9 | wire [7:0] tdata; 10 | wire tlast; 11 | wire tvalid; 12 | wire tready; 13 | 14 | reg pll_locked_r; 15 | reg rst; 16 | 17 | assign q = o_uart_tx; 18 | 19 | always @(posedge i_clk) begin 20 | pll_locked_r <= i_pll_locked; 21 | rst <= ~pll_locked_r; 22 | end 23 | 24 | corescorecore corescorecore 25 | (.i_clk (i_clk), 26 | .i_rst (rst), 27 | .o_tdata (tdata), 28 | .o_tlast (tlast), 29 | .o_tvalid (tvalid), 30 | .i_tready (tready)); 31 | 32 | emitter_uart emitter 33 | (.i_clk (i_clk), 34 | .i_rst (rst), 35 | .i_tdata (tdata), 36 | .i_tvalid (tvalid), 37 | .o_tready (tready), 38 | .o_uart_tx (o_uart_tx)); 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /rtl/corescore_zcu106.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_zcu106 3 | ( 4 | input wire i_clk_p, 5 | input wire i_clk_n, 6 | output wire q, 7 | output wire o_uart_tx); 8 | 9 | wire i_clk; 10 | wire clk; 11 | wire rst; 12 | 13 | //Mirror UART output to LED 14 | assign q = o_uart_tx; 15 | 16 | IBUFDS ibufds 17 | (.I (i_clk_p), 18 | .IB (i_clk_n), 19 | .O (i_clk)); 20 | 21 | corescore_zcu106_clock_gen 22 | clock_gen 23 | (.i_clk (i_clk), 24 | .o_clk (clk), 25 | .o_rst (rst)); 26 | 27 | parameter memfile_emitter = "emitter.hex"; 28 | 29 | wire [7:0] tdata; 30 | wire tlast; 31 | wire tvalid; 32 | wire tready; 33 | 34 | corescorecore corescorecore 35 | (.i_clk (clk), 36 | .i_rst (rst), 37 | .o_tdata (tdata), 38 | .o_tlast (tlast), 39 | .o_tvalid (tvalid), 40 | .i_tready (tready)); 41 | 42 | emitter #(.memfile (memfile_emitter)) emitter 43 | (.i_clk (clk), 44 | .i_rst (rst), 45 | .i_tdata (tdata), 46 | .i_tlast (tlast), 47 | .i_tvalid (tvalid), 48 | .o_tready (tready), 49 | .o_uart_tx (o_uart_tx)); 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /rtl/corescore_zcu106_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module corescore_zcu106_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | MMCME4_ADV 12 | #(.DIVCLK_DIVIDE (5), 13 | .CLKFBOUT_MULT_F (48.000), 14 | .CLKOUT0_DIVIDE_F (75.0), 15 | .CLKIN1_PERIOD (8.0), //125MHz 16 | .STARTUP_WAIT ("FALSE")) 17 | mmcm 18 | (.CLKFBOUT (clkfb), 19 | .CLKFBOUTB (), 20 | .CLKOUT0 (o_clk), 21 | .CLKOUT0B (), 22 | .CLKOUT1 (), 23 | .CLKOUT1B (), 24 | .CLKOUT2 (), 25 | .CLKOUT2B (), 26 | .CLKOUT3 (), 27 | .CLKOUT3B (), 28 | .CLKOUT4 (), 29 | .CLKOUT5 (), 30 | .CLKOUT6 (), 31 | .CLKIN1 (i_clk), 32 | .CLKIN2 (1'b0), 33 | .CLKINSEL (1'b1), 34 | .LOCKED (locked), 35 | .PWRDWN (1'b0), 36 | .RST (1'b0), 37 | .CLKFBIN (clkfb)); 38 | 39 | always @(posedge o_clk) begin 40 | locked_r <= locked; 41 | o_rst <= !locked_r; 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /rtl/cyc1000_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module cyc1000_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output wire o_rst); 6 | 7 | wire [4:0] clk; 8 | 9 | wire clk_fb; 10 | 11 | wire locked; 12 | reg [9:0] r; 13 | 14 | assign o_clk = clk[0]; 15 | 16 | assign o_rst = r[9]; 17 | 18 | always @(posedge o_clk) 19 | if (locked) 20 | r <= {r[8:0],1'b0}; 21 | else 22 | r <= 10'b1111111111; 23 | 24 | cyclone10lp_pll 25 | #(.bandwidth_type ("auto"), 26 | .clk0_divide_by (6), 27 | .clk0_duty_cycle (50), 28 | .clk0_multiply_by (8), 29 | .clk0_phase_shift ("0"), 30 | .compensate_clock ("clk0"), 31 | .inclk0_input_frequency (83333), 32 | .operation_mode ("normal"), 33 | .pll_type ("auto"), 34 | .lpm_type ("cyclone10lp_pll")) 35 | pll 36 | (.activeclock(), 37 | .areset(1'b0), 38 | .clk(clk), 39 | .clkbad(), 40 | .fbin(clk_fb), 41 | .fbout(clk_fb), 42 | .inclk(i_clk), 43 | .locked(locked), 44 | .phasedone(), 45 | .scandataout(), 46 | .scandone(), 47 | .vcooverrange(), 48 | .vcounderrange()); 49 | endmodule 50 | -------------------------------------------------------------------------------- /rtl/de0_nano_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module de0_nano_clock_gen 3 | (input wire i_clk, 4 | input wire i_rst, 5 | output wire o_clk, 6 | output wire o_rst); 7 | 8 | wire locked; 9 | reg [9:0] r; 10 | 11 | assign o_rst = r[9]; 12 | 13 | always @(posedge o_clk) 14 | if (locked) 15 | r <= {r[8:0],1'b0}; 16 | else 17 | r <= 10'b1111111111; 18 | 19 | wire [5:0] clk; 20 | 21 | assign o_clk = clk[0]; 22 | 23 | altpll 24 | #(.operation_mode ("NORMAL"), 25 | .clk0_divide_by (25), 26 | .clk0_multiply_by (8), 27 | .inclk0_input_frequency (20000)) 28 | pll 29 | (.areset (i_rst), 30 | .inclk ({1'b0, i_clk}), 31 | .clk (clk), 32 | .locked (locked)); 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /rtl/de5_net_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module de5_net_clock_gen ( 3 | input wire i_clk, 4 | input wire i_rst, 5 | output wire o_clk, 6 | output wire o_rst 7 | ); 8 | 9 | wire locked; 10 | reg [9:0] r; 11 | 12 | assign o_rst = r[9]; 13 | 14 | always @(posedge o_clk) begin 15 | if (locked) 16 | r <= {r[8:0], 1'b0}; 17 | else 18 | r <= 10'b1111111111; 19 | end 20 | 21 | wire clk; 22 | assign o_clk = clk; 23 | 24 | altera_pll #( 25 | .reference_clock_frequency("50.0 MHz"), 26 | .operation_mode("direct"), 27 | .output_clock_frequency0("16.000000 MHz") 28 | ) altera_pll_i ( 29 | .rst(i_rst), 30 | .outclk({clk}), 31 | .locked(locked), 32 | .fboutclk(), 33 | .fbclk(1'b0), 34 | .refclk(i_clk) 35 | ); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /rtl/ebaz4205_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module ebaz4205_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | PLLE2_BASE 12 | #(.BANDWIDTH("OPTIMIZED"), 13 | .CLKFBOUT_MULT(48), 14 | .CLKIN1_PERIOD(30.000300003), // 33.333 MHz 15 | .CLKOUT0_DIVIDE(100), 16 | .DIVCLK_DIVIDE(1), 17 | .STARTUP_WAIT("FALSE")) 18 | PLLE2_BASE_inst 19 | (.CLKOUT0(o_clk), 20 | .CLKOUT1(), 21 | .CLKOUT2(), 22 | .CLKOUT3(), 23 | .CLKOUT4(), 24 | .CLKOUT5(), 25 | .CLKFBOUT(clkfb), 26 | .LOCKED(locked), 27 | .CLKIN1(i_clk), 28 | .PWRDWN(1'b0), 29 | .RST(1'b0), 30 | .CLKFBIN(clkfb)); 31 | 32 | always @(posedge o_clk) begin 33 | locked_r <= locked; 34 | o_rst <= !locked_r; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /rtl/ecppll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(18), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(36), 19 | .CLKFB_DIV(2), 20 | .CLKI_DIV(3), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /rtl/emitter.v: -------------------------------------------------------------------------------- 1 | module emitter 2 | (input wire i_clk, 3 | input wire i_rst, 4 | input wire [7:0] i_tdata, 5 | input wire i_tlast, 6 | input wire i_tvalid, 7 | output wire o_tready, 8 | output wire o_uart_tx); 9 | 10 | parameter memfile = ""; 11 | parameter memsize = 256; 12 | parameter sim = 0; 13 | 14 | wire [31:0] wb_ibus_adr; 15 | wire wb_ibus_cyc; 16 | wire [31:0] wb_ibus_rdt; 17 | wire wb_ibus_ack; 18 | 19 | wire [31:0] wb_dbus_adr; 20 | wire [31:0] wb_dbus_dat; 21 | wire [3:0] wb_dbus_sel; 22 | wire wb_dbus_we; 23 | wire wb_dbus_cyc; 24 | wire [31:0] wb_dbus_rdt; 25 | wire wb_dbus_ack; 26 | 27 | wire [31:0] wb_dmem_adr; 28 | wire [31:0] wb_dmem_dat; 29 | wire [3:0] wb_dmem_sel; 30 | wire wb_dmem_we; 31 | wire wb_dmem_cyc; 32 | wire [31:0] wb_dmem_rdt; 33 | wire wb_dmem_ack; 34 | 35 | wire [31:0] wb_mem_adr; 36 | wire [31:0] wb_mem_dat; 37 | wire [3:0] wb_mem_sel; 38 | wire wb_mem_we; 39 | wire wb_mem_cyc; 40 | wire [31:0] wb_mem_rdt; 41 | wire wb_mem_ack; 42 | 43 | wire wb_gpio_dat; 44 | wire wb_gpio_cyc; 45 | // wire wb_gpio_rdt; 46 | 47 | wire [0:0] wb_fifo_sel; 48 | wire wb_fifo_stb; 49 | wire [9:0] wb_fifo_rdt; 50 | wire wb_fifo_ack; 51 | 52 | servant_arbiter arbiter 53 | (.i_wb_cpu_dbus_adr (wb_dmem_adr), 54 | .i_wb_cpu_dbus_dat (wb_dmem_dat), 55 | .i_wb_cpu_dbus_sel (wb_dmem_sel), 56 | .i_wb_cpu_dbus_we (wb_dmem_we ), 57 | .i_wb_cpu_dbus_cyc (wb_dmem_cyc), 58 | .o_wb_cpu_dbus_rdt (wb_dmem_rdt), 59 | .o_wb_cpu_dbus_ack (wb_dmem_ack), 60 | 61 | .i_wb_cpu_ibus_adr (wb_ibus_adr), 62 | .i_wb_cpu_ibus_cyc (wb_ibus_cyc), 63 | .o_wb_cpu_ibus_rdt (wb_ibus_rdt), 64 | .o_wb_cpu_ibus_ack (wb_ibus_ack), 65 | 66 | .o_wb_cpu_adr (wb_mem_adr), 67 | .o_wb_cpu_dat (wb_mem_dat), 68 | .o_wb_cpu_sel (wb_mem_sel), 69 | .o_wb_cpu_we (wb_mem_we ), 70 | .o_wb_cpu_cyc (wb_mem_cyc), 71 | .i_wb_cpu_rdt (wb_mem_rdt), 72 | .i_wb_cpu_ack (wb_mem_ack)); 73 | 74 | emitter_mux #(sim) dmux 75 | ( 76 | .i_clk (i_clk), 77 | .i_rst (i_rst), 78 | .i_wb_cpu_adr (wb_dbus_adr), 79 | .i_wb_cpu_dat (wb_dbus_dat), 80 | .i_wb_cpu_sel (wb_dbus_sel), 81 | .i_wb_cpu_we (wb_dbus_we), 82 | .i_wb_cpu_cyc (wb_dbus_cyc), 83 | .o_wb_cpu_rdt (wb_dbus_rdt), 84 | .o_wb_cpu_ack (wb_dbus_ack), 85 | 86 | .o_wb_mem_adr (wb_dmem_adr), 87 | .o_wb_mem_dat (wb_dmem_dat), 88 | .o_wb_mem_sel (wb_dmem_sel), 89 | .o_wb_mem_we (wb_dmem_we), 90 | .o_wb_mem_cyc (wb_dmem_cyc), 91 | .i_wb_mem_rdt (wb_dmem_rdt), 92 | 93 | .o_wb_gpio_dat (wb_gpio_dat), 94 | .o_wb_gpio_cyc (wb_gpio_cyc), 95 | // .i_wb_gpio_rdt (wb_gpio_rdt), 96 | 97 | .o_wb_timer_dat (), 98 | .o_wb_timer_we (), 99 | .o_wb_timer_cyc (), 100 | .i_wb_timer_rdt (32'd0), 101 | 102 | .o_wb_fifo_sel (wb_fifo_sel), 103 | .o_wb_fifo_stb (wb_fifo_stb), 104 | .i_wb_fifo_rdt (wb_fifo_rdt), 105 | .i_wb_fifo_ack (wb_fifo_ack)); 106 | 107 | servant_ram 108 | #(.memfile (memfile), 109 | .RESET_STRATEGY ("MINI"), 110 | .depth (memsize)) 111 | ram 112 | (// Wishbone interface 113 | .i_wb_clk (i_clk), 114 | .i_wb_rst (i_rst), 115 | .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]), 116 | .i_wb_cyc (wb_mem_cyc), 117 | .i_wb_we (wb_mem_we) , 118 | .i_wb_sel (wb_mem_sel), 119 | .i_wb_dat (wb_mem_dat), 120 | .o_wb_rdt (wb_mem_rdt), 121 | .o_wb_ack (wb_mem_ack)); 122 | 123 | servant_gpio gpio 124 | (.i_wb_clk (i_clk), 125 | .i_wb_dat (wb_gpio_dat), 126 | .i_wb_we (1'b1), 127 | .i_wb_cyc (wb_gpio_cyc), 128 | .o_wb_rdt (), 129 | .o_gpio (o_uart_tx)); 130 | 131 | axis2wb s2w 132 | (.i_clk (i_clk), 133 | .i_rst (i_rst), 134 | .i_wb_sel (wb_fifo_sel), 135 | .i_wb_stb (wb_fifo_stb), 136 | .o_wb_rdt (wb_fifo_rdt), 137 | .o_wb_ack (wb_fifo_ack), 138 | .i_tdata (i_tdata), 139 | .i_tlast (i_tlast), 140 | .i_tvalid (i_tvalid), 141 | .o_tready (o_tready)); 142 | 143 | serv_rf_top 144 | #(.RESET_PC (32'h0000_0000), 145 | .WITH_CSR (0)) 146 | cpu 147 | ( 148 | .clk (i_clk), 149 | .i_rst (i_rst), 150 | .i_timer_irq (1'b0), 151 | `ifdef RISCV_FORMAL 152 | .rvfi_valid (), 153 | .rvfi_order (), 154 | .rvfi_insn (), 155 | .rvfi_trap (), 156 | .rvfi_halt (), 157 | .rvfi_intr (), 158 | .rvfi_mode (), 159 | .rvfi_ixl (), 160 | .rvfi_rs1_addr (), 161 | .rvfi_rs2_addr (), 162 | .rvfi_rs1_rdata (), 163 | .rvfi_rs2_rdata (), 164 | .rvfi_rd_addr (), 165 | .rvfi_rd_wdata (), 166 | .rvfi_pc_rdata (), 167 | .rvfi_pc_wdata (), 168 | .rvfi_mem_addr (), 169 | .rvfi_mem_rmask (), 170 | .rvfi_mem_wmask (), 171 | .rvfi_mem_rdata (), 172 | .rvfi_mem_wdata (), 173 | `endif 174 | 175 | .o_ibus_adr (wb_ibus_adr), 176 | .o_ibus_cyc (wb_ibus_cyc), 177 | .i_ibus_rdt (wb_ibus_rdt), 178 | .i_ibus_ack (wb_ibus_ack), 179 | 180 | .o_dbus_adr (wb_dbus_adr), 181 | .o_dbus_dat (wb_dbus_dat), 182 | .o_dbus_sel (wb_dbus_sel), 183 | .o_dbus_we (wb_dbus_we), 184 | .o_dbus_cyc (wb_dbus_cyc), 185 | .i_dbus_rdt (wb_dbus_rdt), 186 | .i_dbus_ack (wb_dbus_ack)); 187 | 188 | endmodule 189 | -------------------------------------------------------------------------------- /rtl/emitter_mux.v: -------------------------------------------------------------------------------- 1 | /* 2 | mem = 00 3 | gpio = 01 4 | timer = 10 5 | FIFO = 11 6 | */ 7 | module emitter_mux 8 | ( 9 | input wire i_clk, 10 | input wire i_rst, 11 | input wire [31:0] i_wb_cpu_adr, 12 | input wire [31:0] i_wb_cpu_dat, 13 | input wire [3:0] i_wb_cpu_sel, 14 | input wire i_wb_cpu_we, 15 | input wire i_wb_cpu_cyc, 16 | output wire [31:0] o_wb_cpu_rdt, 17 | output wire o_wb_cpu_ack, 18 | //RW 19 | output wire [31:0] o_wb_mem_adr, 20 | output wire [31:0] o_wb_mem_dat, 21 | output wire [3:0] o_wb_mem_sel, 22 | output wire o_wb_mem_we, 23 | output wire o_wb_mem_cyc, 24 | input wire [31:0] i_wb_mem_rdt, 25 | //W 26 | output wire o_wb_gpio_dat, 27 | output wire o_wb_gpio_cyc, 28 | //RW 29 | output wire [31:0] o_wb_timer_dat, 30 | output wire o_wb_timer_we, 31 | output wire o_wb_timer_cyc, 32 | input wire [31:0] i_wb_timer_rdt, 33 | //R 34 | output wire [0:0] o_wb_fifo_sel, 35 | output wire o_wb_fifo_stb, 36 | input wire [9:0] i_wb_fifo_rdt, 37 | input wire i_wb_fifo_ack); 38 | 39 | parameter sim = 0; 40 | 41 | reg ack; 42 | 43 | wire [1:0] s = i_wb_cpu_adr[31:30]; 44 | 45 | assign o_wb_cpu_rdt = !s[1] ? i_wb_mem_rdt : 46 | s[0] ? {22'd0, i_wb_fifo_rdt} : 47 | i_wb_timer_rdt; 48 | assign o_wb_cpu_ack = (s == 2'b11) ? i_wb_fifo_ack : ack; 49 | 50 | always @(posedge i_clk) begin 51 | ack <= 1'b0; 52 | if (i_wb_cpu_cyc & (s != 2'b11) & !ack) 53 | ack <= 1'b1; 54 | if (i_rst) 55 | ack <= 1'b0; 56 | end 57 | 58 | assign o_wb_mem_adr = i_wb_cpu_adr; 59 | assign o_wb_mem_dat = i_wb_cpu_dat; 60 | assign o_wb_mem_sel = i_wb_cpu_sel; 61 | assign o_wb_mem_we = i_wb_cpu_we; 62 | assign o_wb_mem_cyc = i_wb_cpu_cyc & (s == 2'b00); 63 | 64 | assign o_wb_gpio_dat = i_wb_cpu_dat[0]; 65 | assign o_wb_gpio_cyc = i_wb_cpu_cyc & (s == 2'b01); 66 | 67 | assign o_wb_timer_dat = i_wb_cpu_dat; 68 | assign o_wb_timer_we = i_wb_cpu_we; 69 | assign o_wb_timer_cyc = i_wb_cpu_cyc & (s == 2'b10); 70 | 71 | assign o_wb_fifo_sel = i_wb_cpu_sel[0]; 72 | assign o_wb_fifo_stb = i_wb_cpu_cyc & (s == 2'b11); 73 | 74 | generate 75 | if (sim) begin 76 | wire halt_en = (i_wb_cpu_adr[31:28] == 4'h9) & i_wb_cpu_cyc & o_wb_cpu_ack; 77 | 78 | always @(posedge i_clk) 79 | if(halt_en) begin 80 | $display("Finito"); 81 | $finish; 82 | end 83 | end 84 | endgenerate 85 | endmodule 86 | -------------------------------------------------------------------------------- /rtl/emitter_uart.v: -------------------------------------------------------------------------------- 1 | /* 2 | * emitter_uart.v : Simple UA(R)T used as emitter in CoreScore 3 | * 4 | * SPDX-FileCopyrightText: 2023 Olof Kindgren 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | 8 | module emitter_uart 9 | #(parameter clk_freq_hz = 16_000_000, 10 | parameter baud_rate = 57600) 11 | (input wire i_clk, 12 | input wire i_rst, 13 | input wire [7:0] i_tdata, 14 | input wire i_tvalid, 15 | output reg o_tready, 16 | output wire o_uart_tx); 17 | 18 | localparam START_VALUE = clk_freq_hz/baud_rate; 19 | 20 | localparam WIDTH = $clog2(START_VALUE); 21 | 22 | reg [WIDTH:0] cnt; 23 | 24 | reg [9:0] data; 25 | 26 | assign o_uart_tx = data[0] | !(|data); 27 | 28 | always @(posedge i_clk) begin 29 | if (cnt[WIDTH] & !(|data)) 30 | o_tready <= 1'b1; 31 | else if (i_tvalid & o_tready) 32 | o_tready <= 1'b0; 33 | 34 | if (o_tready | cnt[WIDTH]) 35 | cnt <= {1'b0,START_VALUE[WIDTH-1:0]}; 36 | else 37 | cnt <= cnt-1; 38 | 39 | if (cnt[WIDTH]) 40 | data <= {1'b0, data[9:1]}; 41 | else if (i_tvalid & o_tready) 42 | data <= {1'b1, i_tdata, 1'b0}; 43 | end 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /rtl/ep2c5t144_devboard_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module ep2c5t144_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output wire o_rst); 6 | 7 | wire locked; 8 | reg [9:0] r; 9 | 10 | assign o_rst = r[9]; 11 | 12 | always @(posedge o_clk) 13 | if (locked) 14 | r <= {r[8:0],1'b0}; 15 | else 16 | r <= 10'b1111111111; 17 | 18 | altpll altpll_component ( 19 | .inclk (i_clk), 20 | .clk (o_clk), 21 | .locked (locked), 22 | .activeclock (), 23 | .areset (1'b0), 24 | .clkbad (), 25 | .clkena ({6{1'b1}}), 26 | .clkloss (), 27 | .clkswitch (1'b0), 28 | .configupdate (1'b0), 29 | .enable0 (), 30 | .enable1 (), 31 | .extclk (), 32 | .extclkena ({4{1'b1}}), 33 | .fbin (1'b1), 34 | .fbmimicbidir (), 35 | .fbout (), 36 | .fref (), 37 | .icdrclk (), 38 | .pfdena (1'b1), 39 | .phasecounterselect ({4{1'b1}}), 40 | .phasedone (), 41 | .phasestep (1'b1), 42 | .phaseupdown (1'b1), 43 | .pllena (1'b1), 44 | .scanaclr (1'b0), 45 | .scanclk (1'b0), 46 | .scanclkena (1'b1), 47 | .scandata (1'b0), 48 | .scandataout (), 49 | .scandone (), 50 | .scanread (1'b0), 51 | .scanwrite (1'b0), 52 | .sclkout0 (), 53 | .sclkout1 (), 54 | .vcooverrange (), 55 | .vcounderrange ()); 56 | defparam 57 | altpll_component.clk0_divide_by = 50, 58 | altpll_component.clk0_duty_cycle = 50, 59 | altpll_component.clk0_multiply_by = 16, 60 | altpll_component.clk0_phase_shift = "0", 61 | altpll_component.compensate_clock = "CLK0", 62 | altpll_component.gate_lock_signal = "NO", 63 | altpll_component.inclk0_input_frequency = 20000, 64 | altpll_component.intended_device_family = "Cyclone II", 65 | altpll_component.invalid_lock_multiplier = 5, 66 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=main_pll", 67 | altpll_component.lpm_type = "altpll", 68 | altpll_component.operation_mode = "NORMAL", 69 | altpll_component.port_activeclock = "PORT_UNUSED", 70 | altpll_component.port_areset = "PORT_UNUSED", 71 | altpll_component.port_clkbad0 = "PORT_UNUSED", 72 | altpll_component.port_clkbad1 = "PORT_UNUSED", 73 | altpll_component.port_clkloss = "PORT_UNUSED", 74 | altpll_component.port_clkswitch = "PORT_UNUSED", 75 | altpll_component.port_configupdate = "PORT_UNUSED", 76 | altpll_component.port_fbin = "PORT_UNUSED", 77 | altpll_component.port_inclk0 = "PORT_USED", 78 | altpll_component.port_inclk1 = "PORT_UNUSED", 79 | altpll_component.port_locked = "PORT_USED", 80 | altpll_component.port_pfdena = "PORT_UNUSED", 81 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 82 | altpll_component.port_phasedone = "PORT_UNUSED", 83 | altpll_component.port_phasestep = "PORT_UNUSED", 84 | altpll_component.port_phaseupdown = "PORT_UNUSED", 85 | altpll_component.port_pllena = "PORT_UNUSED", 86 | altpll_component.port_scanaclr = "PORT_UNUSED", 87 | altpll_component.port_scanclk = "PORT_UNUSED", 88 | altpll_component.port_scanclkena = "PORT_UNUSED", 89 | altpll_component.port_scandata = "PORT_UNUSED", 90 | altpll_component.port_scandataout = "PORT_UNUSED", 91 | altpll_component.port_scandone = "PORT_UNUSED", 92 | altpll_component.port_scanread = "PORT_UNUSED", 93 | altpll_component.port_scanwrite = "PORT_UNUSED", 94 | altpll_component.port_clk0 = "PORT_USED", 95 | altpll_component.port_clk1 = "PORT_UNUSED", 96 | altpll_component.port_clk2 = "PORT_UNUSED", 97 | altpll_component.port_clk3 = "PORT_UNUSED", 98 | altpll_component.port_clk4 = "PORT_UNUSED", 99 | altpll_component.port_clk5 = "PORT_UNUSED", 100 | altpll_component.port_clkena0 = "PORT_UNUSED", 101 | altpll_component.port_clkena1 = "PORT_UNUSED", 102 | altpll_component.port_clkena2 = "PORT_UNUSED", 103 | altpll_component.port_clkena3 = "PORT_UNUSED", 104 | altpll_component.port_clkena4 = "PORT_UNUSED", 105 | altpll_component.port_clkena5 = "PORT_UNUSED", 106 | altpll_component.port_extclk0 = "PORT_UNUSED", 107 | altpll_component.port_extclk1 = "PORT_UNUSED", 108 | altpll_component.port_extclk2 = "PORT_UNUSED", 109 | altpll_component.port_extclk3 = "PORT_UNUSED", 110 | altpll_component.valid_lock_multiplier = 1; 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /rtl/genesys2_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module genesys2_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | PLLE2_BASE 12 | #(.BANDWIDTH("OPTIMIZED"), 13 | .CLKFBOUT_MULT(4), 14 | .CLKIN1_PERIOD(5.0), //200MHz 15 | .CLKOUT0_DIVIDE(50), 16 | .DIVCLK_DIVIDE(1), 17 | .STARTUP_WAIT("FALSE")) 18 | PLLE2_BASE_inst 19 | (.CLKOUT0(o_clk), 20 | .CLKOUT1(), 21 | .CLKOUT2(), 22 | .CLKOUT3(), 23 | .CLKOUT4(), 24 | .CLKOUT5(), 25 | .CLKFBOUT(clkfb), 26 | .LOCKED(locked), 27 | .CLKIN1(i_clk), 28 | .PWRDWN(1'b0), 29 | .RST(1'b0), 30 | .CLKFBIN(clkfb)); 31 | 32 | always @(posedge o_clk) begin 33 | locked_r <= locked; 34 | o_rst <= !locked_r; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /rtl/hpc_k7_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module hpc_k7_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | PLLE2_BASE 12 | #(.BANDWIDTH("OPTIMIZED"), 13 | .CLKFBOUT_MULT(16), 14 | .CLKIN1_PERIOD(10.0), //100MHz 15 | .CLKOUT0_DIVIDE(12.5), 16 | .DIVCLK_DIVIDE(1), 17 | .STARTUP_WAIT("FALSE")) 18 | PLLE2_BASE_inst 19 | (.CLKOUT0(o_clk), 20 | .CLKOUT1(), 21 | .CLKOUT2(), 22 | .CLKOUT3(), 23 | .CLKOUT4(), 24 | .CLKOUT5(), 25 | .CLKFBOUT(clkfb), 26 | .LOCKED(locked), 27 | .CLKIN1(i_clk), 28 | .PWRDWN(1'b0), 29 | .RST(1'b0), 30 | .CLKFBIN(clkfb)); 31 | 32 | always @(posedge o_clk) begin 33 | locked_r <= locked; 34 | o_rst <= !locked_r; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /rtl/hpc_ku_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module hpc_ku_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | PLLE2_BASE 12 | #(.BANDWIDTH("OPTIMIZED"), 13 | .CLKFBOUT_MULT(16), 14 | .CLKIN1_PERIOD(10.0), //100MHz 15 | .CLKOUT0_DIVIDE(12.5), 16 | .DIVCLK_DIVIDE(1), 17 | .STARTUP_WAIT("FALSE")) 18 | PLLE2_BASE_inst 19 | (.CLKOUT0(o_clk), 20 | .CLKOUT1(), 21 | .CLKOUT2(), 22 | .CLKOUT3(), 23 | .CLKOUT4(), 24 | .CLKOUT5(), 25 | .CLKFBOUT(clkfb), 26 | .LOCKED(locked), 27 | .CLKIN1(i_clk), 28 | .PWRDWN(1'b0), 29 | .RST(1'b0), 30 | .CLKFBIN(clkfb)); 31 | 32 | always @(posedge o_clk) begin 33 | locked_r <= locked; 34 | o_rst <= !locked_r; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /rtl/intel_a10gx_devkit_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | // 50MHz Board clock to 16MHz SERV Clock 4 | module intel_a10gx_devkit_clock_gen 5 | ( 6 | input wire i_rst, 7 | input wire i_clk, 8 | 9 | output wire o_clk, 10 | output wire o_rst); 11 | 12 | wire locked; 13 | wire [7:0] unused_wires; 14 | 15 | assign o_rst = ~locked; 16 | 17 | altera_iopll #( 18 | .c_cnt_bypass_en0("false"), 19 | .c_cnt_bypass_en1("true"), 20 | .c_cnt_bypass_en2("true"), 21 | .c_cnt_bypass_en3("true"), 22 | .c_cnt_bypass_en4("true"), 23 | .c_cnt_bypass_en5("true"), 24 | .c_cnt_bypass_en6("true"), 25 | .c_cnt_bypass_en7("true"), 26 | .c_cnt_bypass_en8("true"), 27 | .c_cnt_hi_div0(25), 28 | .c_cnt_hi_div1(256), 29 | .c_cnt_hi_div2(256), 30 | .c_cnt_hi_div3(256), 31 | .c_cnt_hi_div4(256), 32 | .c_cnt_hi_div5(256), 33 | .c_cnt_hi_div6(256), 34 | .c_cnt_hi_div7(256), 35 | .c_cnt_hi_div8(256), 36 | .c_cnt_in_src0("c_m_cnt_in_src_ph_mux_clk"), 37 | .c_cnt_in_src1("c_m_cnt_in_src_ph_mux_clk"), 38 | .c_cnt_in_src2("c_m_cnt_in_src_ph_mux_clk"), 39 | .c_cnt_in_src3("c_m_cnt_in_src_ph_mux_clk"), 40 | .c_cnt_in_src4("c_m_cnt_in_src_ph_mux_clk"), 41 | .c_cnt_in_src5("c_m_cnt_in_src_ph_mux_clk"), 42 | .c_cnt_in_src6("c_m_cnt_in_src_ph_mux_clk"), 43 | .c_cnt_in_src7("c_m_cnt_in_src_ph_mux_clk"), 44 | .c_cnt_in_src8("c_m_cnt_in_src_ph_mux_clk"), 45 | .c_cnt_lo_div0(25), 46 | .c_cnt_lo_div1(256), 47 | .c_cnt_lo_div2(256), 48 | .c_cnt_lo_div3(256), 49 | .c_cnt_lo_div4(256), 50 | .c_cnt_lo_div5(256), 51 | .c_cnt_lo_div6(256), 52 | .c_cnt_lo_div7(256), 53 | .c_cnt_lo_div8(256), 54 | .c_cnt_odd_div_duty_en0("false"), 55 | .c_cnt_odd_div_duty_en1("false"), 56 | .c_cnt_odd_div_duty_en2("false"), 57 | .c_cnt_odd_div_duty_en3("false"), 58 | .c_cnt_odd_div_duty_en4("false"), 59 | .c_cnt_odd_div_duty_en5("false"), 60 | .c_cnt_odd_div_duty_en6("false"), 61 | .c_cnt_odd_div_duty_en7("false"), 62 | .c_cnt_odd_div_duty_en8("false"), 63 | .c_cnt_ph_mux_prst0(0), 64 | .c_cnt_ph_mux_prst1(0), 65 | .c_cnt_ph_mux_prst2(0), 66 | .c_cnt_ph_mux_prst3(0), 67 | .c_cnt_ph_mux_prst4(0), 68 | .c_cnt_ph_mux_prst5(0), 69 | .c_cnt_ph_mux_prst6(0), 70 | .c_cnt_ph_mux_prst7(0), 71 | .c_cnt_ph_mux_prst8(0), 72 | .c_cnt_prst0(1), 73 | .c_cnt_prst1(1), 74 | .c_cnt_prst2(1), 75 | .c_cnt_prst3(1), 76 | .c_cnt_prst4(1), 77 | .c_cnt_prst5(1), 78 | .c_cnt_prst6(1), 79 | .c_cnt_prst7(1), 80 | .c_cnt_prst8(1), 81 | .clock_name_0("outclk0"), 82 | .clock_name_1(""), 83 | .clock_name_2(""), 84 | .clock_name_3(""), 85 | .clock_name_4(""), 86 | .clock_name_5(""), 87 | .clock_name_6(""), 88 | .clock_name_7(""), 89 | .clock_name_8(""), 90 | .clock_name_global_0("false"), 91 | .clock_name_global_1("false"), 92 | .clock_name_global_2("false"), 93 | .clock_name_global_3("false"), 94 | .clock_name_global_4("false"), 95 | .clock_name_global_5("false"), 96 | .clock_name_global_6("false"), 97 | .clock_name_global_7("false"), 98 | .clock_name_global_8("false"), 99 | .duty_cycle0(50), 100 | .duty_cycle1(50), 101 | .duty_cycle2(50), 102 | .duty_cycle3(50), 103 | .duty_cycle4(50), 104 | .duty_cycle5(50), 105 | .duty_cycle6(50), 106 | .duty_cycle7(50), 107 | .duty_cycle8(50), 108 | .m_cnt_bypass_en("false"), 109 | .m_cnt_hi_div(8), 110 | .m_cnt_lo_div(8), 111 | .m_cnt_odd_div_duty_en("false"), 112 | .n_cnt_bypass_en("true"), 113 | .n_cnt_hi_div(256), 114 | .n_cnt_lo_div(256), 115 | .n_cnt_odd_div_duty_en("false"), 116 | .number_of_clocks(1), 117 | .operation_mode("direct"), 118 | .output_clock_frequency0("16.0 MHz"), 119 | .output_clock_frequency1("0 ps"), 120 | .output_clock_frequency2("0 ps"), 121 | .output_clock_frequency3("0 ps"), 122 | .output_clock_frequency4("0 ps"), 123 | .output_clock_frequency5("0 ps"), 124 | .output_clock_frequency6("0 ps"), 125 | .output_clock_frequency7("0 ps"), 126 | .output_clock_frequency8("0 ps"), 127 | .phase_shift0("0 ps"), 128 | .phase_shift1("0 ps"), 129 | .phase_shift2("0 ps"), 130 | .phase_shift3("0 ps"), 131 | .phase_shift4("0 ps"), 132 | .phase_shift5("0 ps"), 133 | .phase_shift6("0 ps"), 134 | .phase_shift7("0 ps"), 135 | .phase_shift8("0 ps"), 136 | .pll_bw_sel("Low"), 137 | .pll_bwctrl("pll_bw_res_setting3"), 138 | .pll_cp_current("pll_cp_setting10"), 139 | .pll_extclk_0_cnt_src("pll_extclk_cnt_src_vss"), 140 | .pll_extclk_1_cnt_src("pll_extclk_cnt_src_vss"), 141 | .pll_fbclk_mux_1("pll_fbclk_mux_1_glb"), 142 | .pll_fbclk_mux_2("pll_fbclk_mux_2_m_cnt"), 143 | .pll_m_cnt_in_src("c_m_cnt_in_src_ph_mux_clk"), 144 | .pll_output_clk_frequency("800.0 MHz"), 145 | .pll_slf_rst("true"), 146 | .pll_subtype("General"), 147 | .pll_type("Arria 10"), 148 | .prot_mode("BASIC"), 149 | .reference_clock_frequency("50.0 MHz") 150 | ) altera_iopll_i ( 151 | .refclk1 (1'b0), 152 | .rst (i_rst), 153 | .fbclk (1'b0), 154 | .fboutclk ( ), 155 | .zdbfbclk ( ), 156 | .locked (locked), 157 | .loaden ( ), 158 | .phase_done ( ), 159 | .reconfig_to_pll (64'b0), 160 | .refclk (i_clk), 161 | .scanclk (1'b0), 162 | .phout ( ), 163 | .num_phase_shifts (3'b0), 164 | .cntsel (5'b0), 165 | .clkbad ( ), 166 | .extclk_out ( ), 167 | .lvds_clk ( ), 168 | .outclk ({o_clk}), 169 | .phase_en (1'b0), 170 | .extswitch (1'b0), 171 | .cascade_out ( ), 172 | .activeclk ( ), 173 | .adjpllin (1'b0), 174 | .updn (1'b0), 175 | .reconfig_from_pll ( ) 176 | ); 177 | 178 | endmodule 179 | -------------------------------------------------------------------------------- /rtl/intel_cyc10lp_devkit_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module intel_cyc10lp_devkit_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output wire o_rst); 6 | 7 | wire locked; 8 | reg [9:0] r; 9 | 10 | assign o_rst = r[9]; 11 | 12 | always @(posedge o_clk) 13 | if (locked) 14 | r <= {r[8:0],1'b0}; 15 | else 16 | r <= 10'b1111111111; 17 | 18 | altpll altpll_component ( 19 | .inclk (i_clk), 20 | .clk (o_clk), 21 | .locked (locked), 22 | .activeclock (), 23 | .areset (1'b0), 24 | .clkbad (), 25 | .clkena ({6{1'b1}}), 26 | .clkloss (), 27 | .clkswitch (1'b0), 28 | .configupdate (1'b0), 29 | .enable0 (), 30 | .enable1 (), 31 | .extclk (), 32 | .extclkena ({4{1'b1}}), 33 | .fbin (1'b1), 34 | .fbmimicbidir (), 35 | .fbout (), 36 | .fref (), 37 | .icdrclk (), 38 | .pfdena (1'b1), 39 | .phasecounterselect ({4{1'b1}}), 40 | .phasedone (), 41 | .phasestep (1'b1), 42 | .phaseupdown (1'b1), 43 | .pllena (1'b1), 44 | .scanaclr (1'b0), 45 | .scanclk (1'b0), 46 | .scanclkena (1'b1), 47 | .scandata (1'b0), 48 | .scandataout (), 49 | .scandone (), 50 | .scanread (1'b0), 51 | .scanwrite (1'b0), 52 | .sclkout0 (), 53 | .sclkout1 (), 54 | .vcooverrange (), 55 | .vcounderrange ()); 56 | defparam 57 | altpll_component.bandwidth_type = "AUTO", 58 | altpll_component.clk0_divide_by = 25, 59 | altpll_component.clk0_duty_cycle = 50, 60 | altpll_component.clk0_multiply_by = 8, 61 | altpll_component.clk0_phase_shift = "0", 62 | altpll_component.compensate_clock = "CLK0", 63 | altpll_component.inclk0_input_frequency = 20000, 64 | altpll_component.intended_device_family = "Cyclone 10 LP", 65 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", 66 | altpll_component.lpm_type = "altpll", 67 | altpll_component.operation_mode = "NORMAL", 68 | altpll_component.pll_type = "AUTO", 69 | altpll_component.port_activeclock = "PORT_UNUSED", 70 | altpll_component.port_areset = "PORT_UNUSED", 71 | altpll_component.port_clkbad0 = "PORT_UNUSED", 72 | altpll_component.port_clkbad1 = "PORT_UNUSED", 73 | altpll_component.port_clkloss = "PORT_UNUSED", 74 | altpll_component.port_clkswitch = "PORT_UNUSED", 75 | altpll_component.port_configupdate = "PORT_UNUSED", 76 | altpll_component.port_fbin = "PORT_UNUSED", 77 | altpll_component.port_inclk0 = "PORT_USED", 78 | altpll_component.port_inclk1 = "PORT_UNUSED", 79 | altpll_component.port_locked = "PORT_USED", 80 | altpll_component.port_pfdena = "PORT_UNUSED", 81 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 82 | altpll_component.port_phasedone = "PORT_UNUSED", 83 | altpll_component.port_phasestep = "PORT_UNUSED", 84 | altpll_component.port_phaseupdown = "PORT_UNUSED", 85 | altpll_component.port_pllena = "PORT_UNUSED", 86 | altpll_component.port_scanaclr = "PORT_UNUSED", 87 | altpll_component.port_scanclk = "PORT_UNUSED", 88 | altpll_component.port_scanclkena = "PORT_UNUSED", 89 | altpll_component.port_scandata = "PORT_UNUSED", 90 | altpll_component.port_scandataout = "PORT_UNUSED", 91 | altpll_component.port_scandone = "PORT_UNUSED", 92 | altpll_component.port_scanread = "PORT_UNUSED", 93 | altpll_component.port_scanwrite = "PORT_UNUSED", 94 | altpll_component.port_clk0 = "PORT_USED", 95 | altpll_component.port_clk1 = "PORT_UNUSED", 96 | altpll_component.port_clk2 = "PORT_UNUSED", 97 | altpll_component.port_clk3 = "PORT_UNUSED", 98 | altpll_component.port_clk4 = "PORT_UNUSED", 99 | altpll_component.port_clk5 = "PORT_UNUSED", 100 | altpll_component.port_clkena0 = "PORT_UNUSED", 101 | altpll_component.port_clkena1 = "PORT_UNUSED", 102 | altpll_component.port_clkena2 = "PORT_UNUSED", 103 | altpll_component.port_clkena3 = "PORT_UNUSED", 104 | altpll_component.port_clkena4 = "PORT_UNUSED", 105 | altpll_component.port_clkena5 = "PORT_UNUSED", 106 | altpll_component.port_extclk0 = "PORT_UNUSED", 107 | altpll_component.port_extclk1 = "PORT_UNUSED", 108 | altpll_component.port_extclk2 = "PORT_UNUSED", 109 | altpll_component.port_extclk3 = "PORT_UNUSED", 110 | altpll_component.self_reset_on_loss_lock = "OFF", 111 | altpll_component.width_clock = 5; 112 | 113 | endmodule 114 | -------------------------------------------------------------------------------- /rtl/intel_max10_devkit_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module intel_max10_devkit_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output wire o_rst); 6 | 7 | wire locked; 8 | reg [9:0] r; 9 | 10 | assign o_rst = r[9]; 11 | 12 | always @(posedge o_clk) 13 | if (locked) 14 | r <= {r[8:0],1'b0}; 15 | else 16 | r <= 10'b1111111111; 17 | 18 | altpll altpll_component ( 19 | .inclk (i_clk), 20 | .clk (o_clk), 21 | .locked (locked), 22 | .activeclock (), 23 | .areset (1'b0), 24 | .clkbad (), 25 | .clkena ({6{1'b1}}), 26 | .clkloss (), 27 | .clkswitch (1'b0), 28 | .configupdate (1'b0), 29 | .enable0 (), 30 | .enable1 (), 31 | .extclk (), 32 | .extclkena ({4{1'b1}}), 33 | .fbin (1'b1), 34 | .fbmimicbidir (), 35 | .fbout (), 36 | .fref (), 37 | .icdrclk (), 38 | .pfdena (1'b1), 39 | .phasecounterselect ({4{1'b1}}), 40 | .phasedone (), 41 | .phasestep (1'b1), 42 | .phaseupdown (1'b1), 43 | .pllena (1'b1), 44 | .scanaclr (1'b0), 45 | .scanclk (1'b0), 46 | .scanclkena (1'b1), 47 | .scandata (1'b0), 48 | .scandataout (), 49 | .scandone (), 50 | .scanread (1'b0), 51 | .scanwrite (1'b0), 52 | .sclkout0 (), 53 | .sclkout1 (), 54 | .vcooverrange (), 55 | .vcounderrange ()); 56 | defparam 57 | altpll_component.bandwidth_type = "AUTO", 58 | altpll_component.clk0_divide_by = 25, 59 | altpll_component.clk0_duty_cycle = 50, 60 | altpll_component.clk0_multiply_by = 8, 61 | altpll_component.clk0_phase_shift = "0", 62 | altpll_component.compensate_clock = "CLK0", 63 | altpll_component.inclk0_input_frequency = 20000, 64 | altpll_component.intended_device_family = "MAX 10", 65 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", 66 | altpll_component.lpm_type = "altpll", 67 | altpll_component.operation_mode = "NORMAL", 68 | altpll_component.pll_type = "AUTO", 69 | altpll_component.port_activeclock = "PORT_UNUSED", 70 | altpll_component.port_areset = "PORT_UNUSED", 71 | altpll_component.port_clkbad0 = "PORT_UNUSED", 72 | altpll_component.port_clkbad1 = "PORT_UNUSED", 73 | altpll_component.port_clkloss = "PORT_UNUSED", 74 | altpll_component.port_clkswitch = "PORT_UNUSED", 75 | altpll_component.port_configupdate = "PORT_UNUSED", 76 | altpll_component.port_fbin = "PORT_UNUSED", 77 | altpll_component.port_inclk0 = "PORT_USED", 78 | altpll_component.port_inclk1 = "PORT_UNUSED", 79 | altpll_component.port_locked = "PORT_USED", 80 | altpll_component.port_pfdena = "PORT_UNUSED", 81 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 82 | altpll_component.port_phasedone = "PORT_UNUSED", 83 | altpll_component.port_phasestep = "PORT_UNUSED", 84 | altpll_component.port_phaseupdown = "PORT_UNUSED", 85 | altpll_component.port_pllena = "PORT_UNUSED", 86 | altpll_component.port_scanaclr = "PORT_UNUSED", 87 | altpll_component.port_scanclk = "PORT_UNUSED", 88 | altpll_component.port_scanclkena = "PORT_UNUSED", 89 | altpll_component.port_scandata = "PORT_UNUSED", 90 | altpll_component.port_scandataout = "PORT_UNUSED", 91 | altpll_component.port_scandone = "PORT_UNUSED", 92 | altpll_component.port_scanread = "PORT_UNUSED", 93 | altpll_component.port_scanwrite = "PORT_UNUSED", 94 | altpll_component.port_clk0 = "PORT_USED", 95 | altpll_component.port_clk1 = "PORT_UNUSED", 96 | altpll_component.port_clk2 = "PORT_UNUSED", 97 | altpll_component.port_clk3 = "PORT_UNUSED", 98 | altpll_component.port_clk4 = "PORT_UNUSED", 99 | altpll_component.port_clk5 = "PORT_UNUSED", 100 | altpll_component.port_clkena0 = "PORT_UNUSED", 101 | altpll_component.port_clkena1 = "PORT_UNUSED", 102 | altpll_component.port_clkena2 = "PORT_UNUSED", 103 | altpll_component.port_clkena3 = "PORT_UNUSED", 104 | altpll_component.port_clkena4 = "PORT_UNUSED", 105 | altpll_component.port_clkena5 = "PORT_UNUSED", 106 | altpll_component.port_extclk0 = "PORT_UNUSED", 107 | altpll_component.port_extclk1 = "PORT_UNUSED", 108 | altpll_component.port_extclk2 = "PORT_UNUSED", 109 | altpll_component.port_extclk3 = "PORT_UNUSED", 110 | altpll_component.self_reset_on_loss_lock = "OFF", 111 | altpll_component.width_clock = 5; 112 | 113 | endmodule 114 | -------------------------------------------------------------------------------- /rtl/max1000_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module max1000_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output wire o_rst); 6 | 7 | wire locked; 8 | reg [9:0] r; 9 | 10 | assign o_rst = r[9]; 11 | 12 | always @(posedge o_clk) 13 | if (locked) 14 | r <= {r[8:0],1'b0}; 15 | else 16 | r <= 10'b1111111111; 17 | 18 | altpll altpll_component ( 19 | .inclk (i_clk), 20 | .clk (o_clk), 21 | .locked (locked), 22 | .activeclock (), 23 | .areset (1'b0), 24 | .clkbad (), 25 | .clkena ({6{1'b1}}), 26 | .clkloss (), 27 | .clkswitch (1'b0), 28 | .configupdate (1'b0), 29 | .enable0 (), 30 | .enable1 (), 31 | .extclk (), 32 | .extclkena ({4{1'b1}}), 33 | .fbin (1'b1), 34 | .fbmimicbidir (), 35 | .fbout (), 36 | .fref (), 37 | .icdrclk (), 38 | .pfdena (1'b1), 39 | .phasecounterselect ({4{1'b1}}), 40 | .phasedone (), 41 | .phasestep (1'b1), 42 | .phaseupdown (1'b1), 43 | .pllena (1'b1), 44 | .scanaclr (1'b0), 45 | .scanclk (1'b0), 46 | .scanclkena (1'b1), 47 | .scandata (1'b0), 48 | .scandataout (), 49 | .scandone (), 50 | .scanread (1'b0), 51 | .scanwrite (1'b0), 52 | .sclkout0 (), 53 | .sclkout1 (), 54 | .vcooverrange (), 55 | .vcounderrange ()); 56 | defparam 57 | altpll_component.bandwidth_type = "AUTO", 58 | altpll_component.clk0_divide_by = 3, 59 | altpll_component.clk0_duty_cycle = 50, 60 | altpll_component.clk0_multiply_by = 4, 61 | altpll_component.clk0_phase_shift = "0", 62 | altpll_component.compensate_clock = "CLK0", 63 | altpll_component.inclk0_input_frequency = 83333, 64 | altpll_component.intended_device_family = "MAX 10", 65 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", 66 | altpll_component.lpm_type = "altpll", 67 | altpll_component.operation_mode = "NORMAL", 68 | altpll_component.pll_type = "AUTO", 69 | altpll_component.port_activeclock = "PORT_UNUSED", 70 | altpll_component.port_areset = "PORT_UNUSED", 71 | altpll_component.port_clkbad0 = "PORT_UNUSED", 72 | altpll_component.port_clkbad1 = "PORT_UNUSED", 73 | altpll_component.port_clkloss = "PORT_UNUSED", 74 | altpll_component.port_clkswitch = "PORT_UNUSED", 75 | altpll_component.port_configupdate = "PORT_UNUSED", 76 | altpll_component.port_fbin = "PORT_UNUSED", 77 | altpll_component.port_inclk0 = "PORT_USED", 78 | altpll_component.port_inclk1 = "PORT_UNUSED", 79 | altpll_component.port_locked = "PORT_USED", 80 | altpll_component.port_pfdena = "PORT_UNUSED", 81 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 82 | altpll_component.port_phasedone = "PORT_UNUSED", 83 | altpll_component.port_phasestep = "PORT_UNUSED", 84 | altpll_component.port_phaseupdown = "PORT_UNUSED", 85 | altpll_component.port_pllena = "PORT_UNUSED", 86 | altpll_component.port_scanaclr = "PORT_UNUSED", 87 | altpll_component.port_scanclk = "PORT_UNUSED", 88 | altpll_component.port_scanclkena = "PORT_UNUSED", 89 | altpll_component.port_scandata = "PORT_UNUSED", 90 | altpll_component.port_scandataout = "PORT_UNUSED", 91 | altpll_component.port_scandone = "PORT_UNUSED", 92 | altpll_component.port_scanread = "PORT_UNUSED", 93 | altpll_component.port_scanwrite = "PORT_UNUSED", 94 | altpll_component.port_clk0 = "PORT_USED", 95 | altpll_component.port_clk1 = "PORT_UNUSED", 96 | altpll_component.port_clk2 = "PORT_UNUSED", 97 | altpll_component.port_clk3 = "PORT_UNUSED", 98 | altpll_component.port_clk4 = "PORT_UNUSED", 99 | altpll_component.port_clk5 = "PORT_UNUSED", 100 | altpll_component.port_clkena0 = "PORT_UNUSED", 101 | altpll_component.port_clkena1 = "PORT_UNUSED", 102 | altpll_component.port_clkena2 = "PORT_UNUSED", 103 | altpll_component.port_clkena3 = "PORT_UNUSED", 104 | altpll_component.port_clkena4 = "PORT_UNUSED", 105 | altpll_component.port_clkena5 = "PORT_UNUSED", 106 | altpll_component.port_extclk0 = "PORT_UNUSED", 107 | altpll_component.port_extclk1 = "PORT_UNUSED", 108 | altpll_component.port_extclk2 = "PORT_UNUSED", 109 | altpll_component.port_extclk3 = "PORT_UNUSED", 110 | altpll_component.self_reset_on_loss_lock = "OFF", 111 | altpll_component.width_clock = 5; 112 | 113 | endmodule 114 | -------------------------------------------------------------------------------- /rtl/nexys_a7_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module nexys_a7_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | PLLE2_BASE 12 | #(.BANDWIDTH("OPTIMIZED"), 13 | .CLKFBOUT_MULT(16), 14 | .CLKIN1_PERIOD(10.0), //100MHz 15 | .CLKOUT0_DIVIDE(100), 16 | .DIVCLK_DIVIDE(1), 17 | .STARTUP_WAIT("FALSE")) 18 | PLLE2_BASE_inst 19 | (.CLKOUT0(o_clk), 20 | .CLKOUT1(), 21 | .CLKOUT2(), 22 | .CLKOUT3(), 23 | .CLKOUT4(), 24 | .CLKOUT5(), 25 | .CLKFBOUT(clkfb), 26 | .LOCKED(locked), 27 | .CLKIN1(i_clk), 28 | .PWRDWN(1'b0), 29 | .RST(1'b0), 30 | .CLKFBIN(clkfb)); 31 | 32 | always @(posedge o_clk) begin 33 | locked_r <= locked; 34 | o_rst <= !locked_r; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /rtl/nexys_video_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module nexys_video_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | wire clkfb; 8 | wire locked; 9 | reg locked_r; 10 | 11 | PLLE2_BASE 12 | #(.BANDWIDTH("OPTIMIZED"), 13 | .CLKFBOUT_MULT(16), 14 | .CLKIN1_PERIOD(10.0), //100MHz 15 | .CLKOUT0_DIVIDE(100), 16 | .DIVCLK_DIVIDE(1), 17 | .STARTUP_WAIT("FALSE")) 18 | PLLE2_BASE_inst 19 | (.CLKOUT0(o_clk), 20 | .CLKOUT1(), 21 | .CLKOUT2(), 22 | .CLKOUT3(), 23 | .CLKOUT4(), 24 | .CLKOUT5(), 25 | .CLKFBOUT(clkfb), 26 | .LOCKED(locked), 27 | .CLKIN1(i_clk), 28 | .PWRDWN(1'b0), 29 | .RST(1'b0), 30 | .CLKFBIN(clkfb)); 31 | 32 | always @(posedge o_clk) begin 33 | locked_r <= locked; 34 | o_rst <= !locked_r; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /rtl/storeypeak_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module storeypeak_clock_gen 3 | (input wire i_clk, 4 | output wire o_clk, 5 | output wire o_rst); 6 | 7 | 8 | wire clk_fb; 9 | 10 | wire locked; 11 | reg [9:0] r; 12 | 13 | 14 | assign o_rst = r[9]; 15 | 16 | always @(posedge o_clk) 17 | if (locked) 18 | r <= {r[8:0],1'b0}; 19 | else 20 | r <= 10'b1111111111; 21 | 22 | 23 | altera_pll #( 24 | .fractional_vco_multiplier("false"), 25 | .reference_clock_frequency("125.0 MHz"), 26 | .operation_mode("direct"), 27 | .number_of_clocks(1), 28 | .output_clock_frequency0("16.000000 MHz"), 29 | .phase_shift0("0 ps"), 30 | .duty_cycle0(50), 31 | .output_clock_frequency1("0 MHz"), 32 | .phase_shift1("0 ps"), 33 | .duty_cycle1(50), 34 | .output_clock_frequency2("0 MHz"), 35 | .phase_shift2("0 ps"), 36 | .duty_cycle2(50), 37 | .output_clock_frequency3("0 MHz"), 38 | .phase_shift3("0 ps"), 39 | .duty_cycle3(50), 40 | .output_clock_frequency4("0 MHz"), 41 | .phase_shift4("0 ps"), 42 | .duty_cycle4(50), 43 | .output_clock_frequency5("0 MHz"), 44 | .phase_shift5("0 ps"), 45 | .duty_cycle5(50), 46 | .output_clock_frequency6("0 MHz"), 47 | .phase_shift6("0 ps"), 48 | .duty_cycle6(50), 49 | .output_clock_frequency7("0 MHz"), 50 | .phase_shift7("0 ps"), 51 | .duty_cycle7(50), 52 | .output_clock_frequency8("0 MHz"), 53 | .phase_shift8("0 ps"), 54 | .duty_cycle8(50), 55 | .output_clock_frequency9("0 MHz"), 56 | .phase_shift9("0 ps"), 57 | .duty_cycle9(50), 58 | .output_clock_frequency10("0 MHz"), 59 | .phase_shift10("0 ps"), 60 | .duty_cycle10(50), 61 | .output_clock_frequency11("0 MHz"), 62 | .phase_shift11("0 ps"), 63 | .duty_cycle11(50), 64 | .output_clock_frequency12("0 MHz"), 65 | .phase_shift12("0 ps"), 66 | .duty_cycle12(50), 67 | .output_clock_frequency13("0 MHz"), 68 | .phase_shift13("0 ps"), 69 | .duty_cycle13(50), 70 | .output_clock_frequency14("0 MHz"), 71 | .phase_shift14("0 ps"), 72 | .duty_cycle14(50), 73 | .output_clock_frequency15("0 MHz"), 74 | .phase_shift15("0 ps"), 75 | .duty_cycle15(50), 76 | .output_clock_frequency16("0 MHz"), 77 | .phase_shift16("0 ps"), 78 | .duty_cycle16(50), 79 | .output_clock_frequency17("0 MHz"), 80 | .phase_shift17("0 ps"), 81 | .duty_cycle17(50), 82 | .pll_type("General"), 83 | .pll_subtype("General") 84 | ) altera_pll_i ( 85 | .rst (1'b0), 86 | .outclk ({o_clk}), 87 | .locked (locked), 88 | .fboutclk ( ), 89 | .fbclk (1'b0), 90 | .refclk (i_clk) 91 | ); 92 | 93 | endmodule 94 | -------------------------------------------------------------------------------- /rtl/wb2axis.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module wb2axis 3 | ( 4 | input wire i_clk, 5 | input wire i_rst, 6 | input wire [8:0] i_wb_dat, 7 | input wire i_wb_we, 8 | input wire i_wb_stb, 9 | output reg o_wb_ack, 10 | output wire [7:0] o_tdata, 11 | output wire o_tlast, 12 | output wire o_tvalid, 13 | input wire i_tready); 14 | 15 | always @(posedge i_clk) begin 16 | o_wb_ack <= i_wb_stb & i_tready & !o_wb_ack; 17 | if (i_rst) 18 | o_wb_ack <= 1'b0; 19 | end 20 | 21 | assign o_tvalid = i_wb_stb & i_wb_we & !o_wb_ack; 22 | assign o_tdata = i_wb_dat[7:0]; 23 | assign o_tlast = i_wb_dat[8]; 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /sw/.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__/ 2 | -------------------------------------------------------------------------------- /sw/Makefile: -------------------------------------------------------------------------------- 1 | TOOLCHAIN_PREFIX ?= riscv64-unknown-elf- 2 | 3 | %.elf: %.S 4 | $(TOOLCHAIN_PREFIX)gcc -nostartfiles -march=rv32i -mabi=ilp32 -Tlink.ld -o$@ $< 5 | %.hex: %.bin 6 | python3 makehex.py $< 2048 > $@ 7 | %.bin: %.elf 8 | $(TOOLCHAIN_PREFIX)objcopy -O binary $< $@ 9 | clean: 10 | rm -f *.elf *.bin *.hex 11 | -------------------------------------------------------------------------------- /sw/corecount.py: -------------------------------------------------------------------------------- 1 | import curses 2 | import serial 3 | import sys 4 | import msgpack 5 | 6 | COREY = r''' 7 | /---------\ 8 | | Hi! | 9 | |I'm Corey|---------\ 10 | \---------- | 11 | | O" O" | 12 | | _________ | 13 | | \_______/ | 14 | \___________------------\ 15 | |Let's count| 16 | | cores! | 17 | \-----------/ 18 | ''' 19 | 20 | 21 | def main(stdscr): 22 | dev = sys.argv[1] if len(sys.argv) > 1 else '/dev/ttyUSB0' 23 | 24 | stdscr = curses.initscr() 25 | curses.curs_set(0) 26 | y = 0 27 | for l in COREY.split('\n'): 28 | try: 29 | stdscr.addstr(y, 0, l) 30 | except curses.error: 31 | pass 32 | y += 1 33 | stdscr.box(0, 0) 34 | stdscr.refresh() 35 | win = curses.newwin(curses.LINES//2-2, curses.COLS-2, curses.LINES//2+1, 1) 36 | win.scrollok(True) 37 | win.addstr(1, 10, '') 38 | win.refresh() 39 | 40 | found_cores = [] 41 | with serial.Serial(dev, 57600) as ser: 42 | unpacker = msgpack.Unpacker(raw=False) 43 | while(True): 44 | buf = ser.read() 45 | unpacker.feed(buf) 46 | for o in unpacker: 47 | if type(o) == str: 48 | (y, x) = win.getyx() 49 | win.addstr(curses.LINES//2-3, 6, o[0:-1]) 50 | win.refresh() 51 | n = int(o[5:10]) 52 | if not (n in found_cores): 53 | found_cores.append(n) 54 | stdscr.addstr( 55 | 10, 35, "Found {} cores".format(len(found_cores))) 56 | stdscr.refresh() 57 | 58 | 59 | curses.wrapper(main) 60 | -------------------------------------------------------------------------------- /sw/corescorecore_gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | from fusesoc.capi2.generator import Generator 3 | import os 4 | import shutil 5 | import subprocess 6 | 7 | from verilogwriter import Instance, ModulePort, Parameter, Port, VerilogWriter, Wire 8 | 9 | #HEX_TEMPLATE implements the following program 10 | #/* 11 | #* Read a string and send as packet to emitter 12 | #* 13 | #* 14 | #*/ 15 | ##define AXIS_ADDR 0xC0000000 16 | # 17 | # /* 18 | # a0 = String address 19 | # a1 = Emitter FIFO address 20 | # t0 = Character to write 21 | # */ 22 | # 23 | #.globl _start 24 | #_start: 25 | # nop 26 | # /* Load string address to a0 */ 27 | # la a0, str 28 | # 29 | # /* Load axis address to a1 */ 30 | # li a1, AXIS_ADDR 31 | # 32 | # /* Write MSGPack string header (0b101xxxxx + len) */ 33 | # li t0, 0xa0+23 34 | # 35 | #next: /* Write to FIFO */ 36 | # sb t0, 0(a1) 37 | # 38 | # /* Read byte from str */ 39 | # lb t0, 0(a0) 40 | # 41 | # /* Load next address */ 42 | # addi a0, a0, 1 43 | # 44 | # /* Check if this was last byte in packet */ 45 | # bnez t0, next 46 | # 47 | # /* Write packet end to FIFO */ 48 | # ori t0, t0, 0x100 49 | # sh t0, 0(a1) 50 | # 51 | # li t0, 10000 52 | #loop: addi t0, t0, -1 53 | # bnez t0, loop 54 | # j _start 55 | # 56 | #str: 57 | # .string "Core XXXXX says hello\n" 58 | 59 | HEX_TEMPLATE = '''@0000 60 | 13 00 00 00 61 | 17 05 00 00 62 | 13 05 c5 03 63 | b7 05 00 c0 64 | 93 02 70 0b 65 | 23 80 55 00 66 | 83 02 05 00 67 | 13 05 15 00 68 | e3 9a 02 fe 69 | 93 e2 02 10 70 | 23 90 55 00 71 | b7 22 00 00 72 | 93 82 02 71 73 | 93 82 f2 ff 74 | e3 9e 02 fe 75 | 6f f0 5f fc 76 | 43 6F 72 65 77 | 20 {} {} {} 78 | {} {} 20 73 79 | 61 79 73 20 80 | 68 65 6C 6C 81 | 6F 0A 00 00 82 | ''' 83 | 84 | 85 | class CoreScoreCoreGenerator(Generator): 86 | def run(self): 87 | files = [{'corescorecore.v': {'file_type': 'verilogSource'}}] 88 | count = self.config.get('count') 89 | 90 | for idx in range(count): 91 | name = 'core_{}'.format(idx) 92 | memfile = name+'.hex' 93 | 94 | # Create hex file 95 | with open(memfile, 'w') as f: 96 | _s = '{:05}'.format(idx) 97 | f.write(HEX_TEMPLATE.format(hex(ord(_s[0]))[2:], 98 | hex(ord(_s[1]))[2:], 99 | hex(ord(_s[2]))[2:], 100 | hex(ord(_s[3]))[2:], 101 | hex(ord(_s[4]))[2:])) 102 | files.append({memfile: {'file_type': 'user', 'copyto': memfile}}) 103 | 104 | self.gen_corescorecore(count) 105 | self.add_files(files) 106 | 107 | def gen_corescorecore(self, count): 108 | corescorecore = VerilogWriter('corescorecore') 109 | 110 | corescorecore.add(ModulePort('i_clk', 'input')) 111 | corescorecore.add(ModulePort('i_rst', 'input')) 112 | corescorecore.add(ModulePort('o_tdata', 'output', 8)) 113 | corescorecore.add(ModulePort('o_tlast', 'output')) 114 | corescorecore.add(ModulePort('o_tvalid', 'output')) 115 | corescorecore.add(ModulePort('i_tready', 'input')) 116 | 117 | corescorecore.add(Wire('tdata', count*8)) 118 | corescorecore.add(Wire('tlast', count)) 119 | corescorecore.add(Wire('tvalid', count)) 120 | corescorecore.add(Wire('tready', count)) 121 | 122 | for idx in range(count): 123 | base_ports = [ 124 | Port('i_clk', 'i_clk'), 125 | Port('i_rst', 'i_rst'), 126 | Port('o_tdata', 'tdata[{}:{}]'.format(idx*8+7, idx*8)), 127 | Port('o_tlast', 'tlast[{}]'.format(idx)), 128 | Port('o_tvalid', 'tvalid[{}]'.format(idx)), 129 | Port('i_tready', 'tready[{}]'.format(idx)), 130 | ] 131 | corescorecore.add(Instance('base', 'core_'+str(idx), 132 | [Parameter('memfile', '"core_{}.hex"'.format(idx)), 133 | Parameter('memsize', '256')], 134 | base_ports)) 135 | 136 | arbports = [ 137 | Port('clk', 'i_clk'), 138 | Port('rst', 'i_rst'), 139 | Port("s_axis_tdata".format(idx), "tdata"), 140 | Port("s_axis_tkeep".format(idx), "{}'d0".format(count)), 141 | Port("s_axis_tvalid".format(idx), 'tvalid'), 142 | Port("s_axis_tready".format(idx), 'tready'), 143 | Port("s_axis_tlast".format(idx), 'tlast'), 144 | Port("s_axis_tid".format(idx), "{}'d0".format(count*8)), 145 | Port("s_axis_tdest".format(idx), "{}'d0".format(count*8)), 146 | Port("s_axis_tuser".format(idx), "{}'d0".format(count)), 147 | Port('m_axis_tdata ', 'o_tdata'), 148 | Port('m_axis_tkeep ', ''), 149 | Port('m_axis_tvalid', 'o_tvalid'), 150 | Port('m_axis_tready', 'i_tready'), 151 | Port('m_axis_tlast ', 'o_tlast'), 152 | Port('m_axis_tid ', ''), 153 | Port('m_axis_tdest ', ''), 154 | Port('m_axis_tuser ', ''), 155 | ] 156 | arbparams = [ 157 | Parameter('S_COUNT', count), 158 | Parameter('DATA_WIDTH', 8), 159 | Parameter('KEEP_ENABLE', 0), 160 | Parameter('KEEP_WIDTH', 1), 161 | Parameter('ID_ENABLE', 0), 162 | Parameter('ID_WIDTH', 8), 163 | Parameter('DEST_ENABLE', 0), 164 | Parameter('DEST_WIDTH', 8), 165 | Parameter('USER_ENABLE', 0), 166 | Parameter('USER_WIDTH', 1), 167 | Parameter('ARB_TYPE', '"ROUND_ROBIN"'), 168 | Parameter('LSB_PRIORITY', '"HIGH"'), 169 | ] 170 | 171 | corescorecore.add( 172 | Instance('axis_arb_mux', 'axis_mux', arbparams, arbports)) 173 | corescorecore.write('corescorecore.v') 174 | 175 | 176 | g = CoreScoreCoreGenerator() 177 | g.run() 178 | g.write() 179 | -------------------------------------------------------------------------------- /sw/emitter.S: -------------------------------------------------------------------------------- 1 | /* 2 | * Read packet from base and bitbang on UART 3 | * 4 | */ 5 | #define GPIO_ADDR 0x40000000 6 | #define AXIS_ADDR 0xC0000000 7 | #define HALT_ADDR 0x90000000 8 | 9 | /* 10 | a0 = Console address 11 | a1 = FIFO address 12 | t0 = Character to write 13 | */ 14 | 15 | .globl _start 16 | _start: 17 | /* Load gpio address to a0 */ 18 | li a0, GPIO_ADDR 19 | 20 | /* Set GPIO high initially */ 21 | addi t0, zero, 1 22 | sb t0, 0(a0) 23 | 24 | /* Load axis address to a0 */ 25 | li a1, AXIS_ADDR 26 | 27 | /* Check for valid data */ 28 | next: lb t1, 1(a1) 29 | andi t2, t1, 2 30 | beqz t2, next 31 | 32 | /* Read byte from axis */ 33 | lbu t0, 0(a1) 34 | 35 | /* Bitbanged UART loop */ 36 | ori t0, t0, 0x100 37 | slli t0, t0, 1 38 | 1: sb t0, 0(a0) 39 | srli t0, t0, 1 40 | nop 41 | nop 42 | bnez t0, 1b 43 | 44 | j next 45 | -------------------------------------------------------------------------------- /sw/emitter.hex: -------------------------------------------------------------------------------- 1 | 40000537 2 | 00100293 3 | 00550023 4 | c00005b7 5 | 00158303 6 | 00237393 7 | fe038ce3 8 | 0005c283 9 | 1002e293 10 | 00129293 11 | 00550023 12 | 0012d293 13 | 00000013 14 | 00000013 15 | fe0298e3 16 | fd5ff06f 17 | 0013f393 18 | fc0396e3 19 | 900005b7 20 | 0005a023 21 | 56524553 22 | 7375462b 23 | 436f5365 24 | 636f7220 25 | 000a736b 26 | -------------------------------------------------------------------------------- /sw/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | . = 0; 7 | .text : { *(.text) } 8 | .data : { *(.data) } 9 | .bss : { *(.bss) } 10 | } 11 | -------------------------------------------------------------------------------- /sw/makehex.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # 3 | # This is free and unencumbered software released into the public domain. 4 | # 5 | # Anyone is free to copy, modify, publish, use, compile, sell, or 6 | # distribute this software, either in source code form or as a compiled 7 | # binary, for any purpose, commercial or non-commercial, and by any 8 | # means. 9 | 10 | from sys import argv 11 | 12 | binfile = argv[1] 13 | nwords = int(argv[2]) 14 | 15 | with open(binfile, "rb") as f: 16 | bindata = f.read() 17 | 18 | assert len(bindata) < 4*nwords 19 | assert len(bindata) % 4 == 0 20 | 21 | for i in range(nwords): 22 | if i < len(bindata) // 4: 23 | w = bindata[4*i: 4*i+4] 24 | print("%02x%02x%02x%02x" % (w[3], w[2], w[1], w[0])) 25 | else: 26 | print("0") 27 | -------------------------------------------------------------------------------- /sw/requirements.txt: -------------------------------------------------------------------------------- 1 | msgpack 2 | -------------------------------------------------------------------------------- /sw/verilogwriter.py: -------------------------------------------------------------------------------- 1 | class Signal(object): 2 | def __init__(self, name, width=0, low=0, asc=False, vec=0): 3 | self.name = name 4 | self.width = width 5 | self.low = low 6 | self.asc = asc 7 | 8 | def range(self): 9 | if self.width > 0: 10 | l = self.width+self.low-1 11 | r = self.low 12 | if self.asc: 13 | return '['+str(r)+':'+str(l)+']' 14 | else: 15 | return '['+str(l)+':'+str(r)+']' 16 | return '' 17 | 18 | 19 | class Wire(Signal): 20 | def write(self, width): 21 | return 'wire{range} {name};\n'.format(range=self.range().rjust(width), name=self.name) 22 | 23 | 24 | class Parameter: 25 | def __init__(self, name, value): 26 | self.name = name 27 | self.value = value 28 | 29 | 30 | class Port: 31 | def __init__(self, name, value): 32 | self.name = name 33 | self.value = value 34 | 35 | 36 | class ModulePort(Signal): 37 | def __init__(self, name, dir, width=0, low=0, asc=False): 38 | super(ModulePort, self).__init__(name, width, low, asc) 39 | self.dir = dir 40 | 41 | def write(self, range_width=0): 42 | return '{dir} wire {range} {name}'.format(dir=self.dir.ljust(6), range=self.range().rjust(range_width), name=self.name) 43 | 44 | 45 | class Instance: 46 | def __init__(self, module, name, parameters, ports): 47 | self.module = module 48 | self.name = name 49 | self.parameters = parameters 50 | self.ports = ports 51 | 52 | def write(self): 53 | s = self.module 54 | if self.parameters: 55 | max_len = max([len(p.name) for p in self.parameters]) 56 | s += '\n #(' 57 | s += ',\n '.join(['.' + p.name.ljust(max_len) + 58 | ' (' + str(p.value) + ')' for p in self.parameters]) 59 | s += ')\n' 60 | s += ' ' + self.name 61 | 62 | if self.ports: 63 | s += '\n (' 64 | max_len = max([len(p.name) for p in self.ports]) 65 | s += ',\n '.join(['.' + p.name.ljust(max_len) + 66 | ' (' + str(p.value) + ')' for p in self.ports]) 67 | s += ')' 68 | s += ';\n' 69 | return s 70 | 71 | 72 | class VerilogWriter: 73 | raw = "" 74 | 75 | def __init__(self, name): 76 | self.name = name 77 | self.instances = [] 78 | self.ports = [] 79 | self.wires = [] 80 | 81 | def add(self, obj): 82 | if isinstance(obj, Instance): 83 | self.instances += [obj] 84 | elif isinstance(obj, ModulePort): 85 | self.ports += [obj] 86 | elif isinstance(obj, Wire): 87 | self.wires += [obj] 88 | else: 89 | raise Exception("Invalid type!" + str(obj)) 90 | 91 | def write(self, file=None): 92 | s = ("// THIS FILE IS AUTOGENERATED BY corescorecore_gen\n" 93 | "// ANY MANUAL CHANGES WILL BE LOST\n") 94 | if self.ports: 95 | s += "`default_nettype none\n" 96 | s += "module {name}\n".format(name=self.name) 97 | max_len = max([len(p.range()) for p in self.ports]) 98 | s += ' (' 99 | s += ',\n '.join([p.write(max_len) for p in self.ports]) 100 | s += ')' 101 | s += ';\n\n' 102 | if self.wires: 103 | max_len = max([len(w.range()) for w in self.wires]) 104 | for w in self.wires: 105 | s += w.write(max_len + 1) 106 | s += '\n' 107 | s += self.raw 108 | for i in self.instances: 109 | s += i.write() 110 | s += '\n' 111 | if self.ports: 112 | s += 'endmodule\n' 113 | if file is None: 114 | return s 115 | else: 116 | f = open(file, 'w') 117 | f.write(s) 118 | -------------------------------------------------------------------------------- /tb/corescore_tb.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "verilated_vcd_c.h" 5 | #include "Vcorescore_generic.h" 6 | 7 | #include 8 | 9 | using namespace std; 10 | 11 | static bool done; 12 | 13 | vluint64_t main_time = 0; // Current simulation time 14 | // This is a 64-bit integer to reduce wrap over issues and 15 | // allow modulus. You can also use a double, if you wish. 16 | 17 | ofstream file ("msgpack.bin", ios::out|ios::binary); 18 | 19 | double sc_time_stamp () { // Called by $time in Verilog 20 | return main_time; // converts to double, to match 21 | // what SystemC does 22 | } 23 | 24 | void INThandler(int signal) 25 | { 26 | printf("\nCaught ctrl-c\n"); 27 | done = true; 28 | } 29 | 30 | typedef struct { 31 | uint8_t state; 32 | char ch; 33 | uint32_t baud_t; 34 | vluint64_t last_update; 35 | } uart_context_t; 36 | 37 | void uart_init(uart_context_t *context, uint32_t baud_rate) { 38 | context->baud_t = 1000*1000*1000/baud_rate; 39 | context->state = 0; 40 | } 41 | 42 | void do_uart(uart_context_t *context, bool rx) { 43 | if (context->state == 0) { 44 | if (rx) 45 | context->state++; 46 | } 47 | else if (context->state == 1) { 48 | if (!rx) { 49 | context->last_update = main_time + context->baud_t/2; 50 | context->state++; 51 | } 52 | } 53 | else if(context->state == 2) { 54 | if (main_time > context->last_update) { 55 | context->last_update += context->baud_t; 56 | context->ch = 0; 57 | context->state++; 58 | } 59 | } 60 | else if (context->state < 11) { 61 | if (main_time > context->last_update) { 62 | context->last_update += context->baud_t; 63 | context->ch |= rx << (context->state-3); 64 | context->state++; 65 | } 66 | } 67 | else { 68 | if (main_time > context->last_update) { 69 | context->last_update += context->baud_t; 70 | file.write (&context->ch, 1); 71 | putchar(context->ch); 72 | context->state=1; 73 | } 74 | } 75 | } 76 | 77 | 78 | int main(int argc, char **argv, char **env) 79 | { 80 | Verilated::commandArgs(argc, argv); 81 | Vcorescore_generic* top = new Vcorescore_generic; 82 | 83 | VerilatedVcdC * tfp = 0; 84 | const char *vcd = Verilated::commandArgsPlusMatch("vcd="); 85 | if (vcd[0]) { 86 | Verilated::traceEverOn(true); 87 | tfp = new VerilatedVcdC; 88 | top->trace (tfp, 99); 89 | tfp->open ("trace.vcd"); 90 | } 91 | 92 | 93 | uart_context_t uart_context; 94 | int baud_rate = 0; 95 | const char *arg = Verilated::commandArgsPlusMatch("uart_baudrate="); 96 | if (arg[0]) { 97 | baud_rate = atoi(arg+15); 98 | if (baud_rate) { 99 | uart_init(&uart_context, baud_rate); 100 | } 101 | } 102 | 103 | vluint64_t timeout = 0; 104 | const char *arg_timeout = Verilated::commandArgsPlusMatch("timeout="); 105 | if (arg_timeout[0]) 106 | timeout = atoi(arg_timeout+9); 107 | 108 | signal(SIGINT, INThandler); 109 | 110 | top->i_clk = 1; 111 | bool q = top->o_uart_tx; 112 | 113 | while (!(done || Verilated::gotFinish())) { 114 | top->i_rst = main_time < 100; 115 | top->eval(); 116 | if (tfp) 117 | tfp->dump(main_time); 118 | if (baud_rate) do_uart(&uart_context, top->o_uart_tx); 119 | 120 | if (timeout && (main_time >= timeout)) { 121 | printf("Timeout: Exiting at time %lu\n", main_time); 122 | done = true; 123 | } 124 | 125 | top->i_clk = !top->i_clk; 126 | main_time+=31.25; 127 | 128 | } 129 | if (tfp) 130 | tfp->close(); 131 | if (file.is_open()) 132 | file.close(); 133 | exit(0); 134 | } 135 | --------------------------------------------------------------------------------