├── .github └── workflows │ └── ci.yml ├── .gitignore ├── .pre-commit-config.yaml ├── .readthedocs.yml ├── LICENSE ├── NEWS ├── README.rst ├── dev-requirements.txt ├── doc ├── Makefile ├── conf.py ├── dev │ ├── extend.rst │ ├── index.rst │ ├── setup.rst │ └── tests.rst ├── edalize.rst ├── edam │ ├── api.rst │ ├── efinity.gv │ ├── f4pga.gv │ ├── generic.gv │ ├── gls.gv │ ├── gowin.gv │ ├── icestorm.gv │ ├── lint.gv │ ├── sim.gv │ ├── vivado.gv │ └── vpr.gv ├── genindex.rst ├── index.rst ├── make.bat ├── py-modindex.rst ├── ref │ ├── flow.py │ └── migrations.rst ├── requirements.txt └── user │ ├── build.rst │ ├── build_runners.rst │ ├── configure.rst │ ├── index.rst │ └── run.rst ├── edalize ├── apicula.py ├── ascentlint.py ├── build_runners │ └── make.py ├── design_compiler.py ├── diamond.py ├── edatool.py ├── flows │ ├── edaflow.py │ ├── efinity.py │ ├── f4pga.py │ ├── generic.py │ ├── gls.py │ ├── gowin.py │ ├── icestorm.py │ ├── lint.py │ ├── sim.py │ ├── vivado.py │ └── vpr.py ├── gatemate.py ├── genus.py ├── ghdl.py ├── icarus.py ├── icestorm.py ├── ise.py ├── ise_reporting.py ├── isim.py ├── libero.py ├── mistral.py ├── modelsim.py ├── morty.py ├── nextpnr.py ├── openfpga.py ├── openlane.py ├── openroad.py ├── oxide.py ├── quartus.py ├── quartus_reporting.py ├── questaformal.py ├── radiant.py ├── reporting.py ├── rivierapro.py ├── sandpipersaas.py ├── slang.py ├── spyglass.py ├── symbiflow.py ├── symbiyosys.py ├── templates │ ├── ascentlint │ │ ├── Makefile.j2 │ │ └── run-ascentlint.tcl.j2 │ ├── design_compiler │ │ ├── design-compiler-makefile.j2 │ │ ├── design-compiler-project.tcl.j2 │ │ └── design-compiler-read-sources.tcl.j2 │ ├── genus │ │ ├── genus-makefile.j2 │ │ ├── genus-project.tcl.j2 │ │ └── genus-read-sources.tcl.j2 │ ├── ghdl │ │ └── Makefile.j2 │ ├── libero │ │ ├── libero-project.tcl.j2 │ │ ├── libero-run.tcl.j2 │ │ └── libero-syn-user.tcl.j2 │ ├── openfpga │ │ └── task_simulation.conf.j2 │ ├── openlane │ │ ├── openlane-makefile.j2 │ │ └── openlane-script-tcl.j2 │ ├── quartus │ │ ├── quartus-pro-makefile.j2 │ │ ├── quartus-project.tcl.j2 │ │ └── quartus-std-makefile.j2 │ ├── spyglass │ │ ├── Makefile.j2 │ │ ├── spyglass-project.prj.j2 │ │ └── spyglass-run-goal.tcl.j2 │ ├── vcs │ │ └── Makefile.j2 │ ├── vivado │ │ ├── vivado-program.tcl.j2 │ │ ├── vivado-project.tcl.j2 │ │ ├── vivado-run.tcl.j2 │ │ └── vivado-synth.tcl.j2 │ ├── vunit │ │ └── run.py.j2 │ └── yosys │ │ ├── edalize_yosys_procs.tcl.j2 │ │ └── yosys-script-tcl.j2 ├── tools │ ├── edatool.py │ ├── efinity.py │ ├── ghdl.py │ ├── gowin.py │ ├── icarus.py │ ├── icepack.py │ ├── icetime.py │ ├── nextpnr.py │ ├── sandpipersaas.py │ ├── surelog.py │ ├── sv2v.py │ ├── templates │ │ ├── efinity │ │ │ ├── isf_to_xml.py │ │ │ └── newproj_tmpl.xml.j2 │ │ ├── gowin │ │ │ └── gowin-project.tcl.j2 │ │ ├── vivado │ │ │ ├── vivado-netlist.tcl.j2 │ │ │ ├── vivado-program.tcl.j2 │ │ │ ├── vivado-project.tcl.j2 │ │ │ ├── vivado-run.tcl.j2 │ │ │ └── vivado-synth.tcl.j2 │ │ └── yosys │ │ │ ├── edalize_yosys_procs.tcl.j2 │ │ │ └── yosys-script-tcl.j2 │ ├── vcs.py │ ├── verilator.py │ ├── vivado.py │ ├── vpr.py │ └── yosys.py ├── trellis.py ├── utils.py ├── vcs.py ├── veribleformat.py ├── veriblelint.py ├── verilator.py ├── vivado.py ├── vivado_reporting.py ├── vunit.py ├── vunit_hooks.py ├── xcelium.py ├── xsim.py └── yosys.py ├── pyproject.toml ├── scripts └── el_docker ├── tests ├── README.rst ├── __init__.py ├── edalize_common.py ├── edalize_flow_common.py ├── edalize_tool_common.py ├── flows │ ├── gls │ │ ├── Makefile │ │ ├── design.scr │ │ ├── edalize_yosys_procs.tcl │ │ └── edalize_yosys_template.tcl │ ├── lint │ │ ├── Makefile │ │ └── design.vc │ └── sim │ │ ├── Makefile │ │ ├── design.scr │ │ └── with_cocotb │ │ ├── Makefile │ │ └── design.vc ├── mock_commands │ ├── arachne-pnr │ ├── ascentlint │ ├── diamondc │ ├── ecppack │ ├── flow.tcl │ ├── ghdl │ ├── gowin_pack │ ├── icepack │ ├── ip-generate │ ├── iverilog │ ├── iverilog-vpi │ ├── morty │ ├── nextpnr-ecp5 │ ├── nextpnr-gowin │ ├── nextpnr-ice40 │ ├── nextpnr-mistral │ ├── nextpnr-nexus │ ├── p_r │ ├── prjoxide │ ├── qsys-generate │ ├── quartus_asm │ ├── quartus_dse │ ├── quartus_fit │ ├── quartus_map │ ├── quartus_pgm │ ├── quartus_sh │ ├── quartus_sta │ ├── quartus_syn │ ├── qverify │ ├── radiantc │ ├── sby │ ├── sg_shell │ ├── slang │ ├── vcs │ ├── verible-verilog-format │ ├── verible-verilog-lint │ ├── vivado │ ├── vsim │ ├── vvp │ ├── xcelium │ │ ├── tools │ │ │ └── bin │ │ │ │ └── xrun │ │ └── xmroot │ ├── xelab │ ├── xsim │ ├── xtclsh │ └── yosys ├── test_apicula.py ├── test_apicula │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ ├── edalize_yosys_template.tcl │ ├── gowin_pack.cmd │ ├── minimal │ │ ├── Makefile │ │ ├── edalize_yosys_procs.tcl │ │ ├── edalize_yosys_template.tcl │ │ ├── gowin_pack.cmd │ │ ├── nextpnr-gowin.cmd │ │ └── yosys.cmd │ ├── nextpnr-gowin.cmd │ └── yosys.cmd ├── test_ascentlint.py ├── test_ascentlint │ └── defaults │ │ ├── Makefile │ │ ├── ascentlint.cmd │ │ ├── run-ascentlint.tcl │ │ └── sources.f ├── test_diamond.py ├── test_diamond │ ├── diamondc.cmd │ ├── minimal │ │ ├── diamondc.cmd │ │ ├── test_diamond_minimal_0.tcl │ │ └── test_diamond_minimal_0_run.tcl │ ├── test_diamond_0.tcl │ └── test_diamond_0_run.tcl ├── test_edam.py ├── test_edam │ └── exit_1_script ├── test_flow_gls.py ├── test_flow_lint.py ├── test_flow_sim.py ├── test_gatemate.py ├── test_gatemate │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ ├── edalize_yosys_template.tcl │ ├── minimal │ │ ├── Makefile │ │ ├── edalize_yosys_procs.tcl │ │ ├── edalize_yosys_template.tcl │ │ ├── p_r.cmd │ │ └── yosys.cmd │ ├── p_r.cmd │ └── yosys.cmd ├── test_ghdl.py ├── test_ghdl │ ├── test01 │ │ ├── Makefile │ │ ├── analyze.cmd │ │ └── elab-run.cmd │ ├── test02 │ │ ├── Makefile │ │ ├── analyze.cmd │ │ └── elab-run.cmd │ ├── test03 │ │ ├── Makefile │ │ ├── analyze.cmd │ │ └── elab-run.cmd │ └── test04 │ │ ├── Makefile │ │ ├── analyze.cmd │ │ └── elab-run.cmd ├── test_icarus.py ├── test_icarus │ ├── Makefile │ ├── iverilog-vpi.cmd │ ├── iverilog.cmd │ ├── minimal │ │ ├── Makefile │ │ ├── iverilog.cmd │ │ ├── test_icarus_minimal_0.scr │ │ └── vvp.cmd │ ├── test_icarus_0.scr │ ├── timescale.v │ └── vvp.cmd ├── test_icestorm.py ├── test_icestorm │ ├── Makefile │ ├── arachne-pnr.cmd │ ├── edalize_yosys_procs.tcl │ ├── edalize_yosys_template.tcl │ ├── icepack.cmd │ ├── minimal │ │ ├── Makefile │ │ ├── arachne-pnr.cmd │ │ ├── edalize_yosys_procs.tcl │ │ ├── edalize_yosys_template.tcl │ │ ├── icepack.cmd │ │ ├── nextpnr-ice40.cmd │ │ └── yosys.cmd │ ├── nextpnr-ice40.cmd │ ├── nextpnr │ │ ├── Makefile │ │ ├── edalize_yosys_procs.tcl │ │ ├── edalize_yosys_template.tcl │ │ ├── icepack.cmd │ │ ├── nextpnr-ice40.cmd │ │ └── yosys.cmd │ └── yosys.cmd ├── test_ise.py ├── test_ise │ ├── Makefile │ ├── config.mk │ ├── test_ise_0.tcl │ ├── test_ise_0_run.tcl │ └── xtclsh.cmd ├── test_isim.py ├── test_isim │ ├── Makefile │ ├── config.mk │ ├── run.cmd │ ├── run_test_isim_0.tcl │ ├── test_isim_0 │ └── test_isim_0.prj ├── test_libero.py ├── test_libero │ ├── libero-test-all-project.tcl │ ├── libero-test-all-run.tcl │ ├── libero-test-all-syn-user.tcl │ ├── libero-test-project.tcl │ ├── libero-test-run.tcl │ └── libero-test-syn-user.tcl ├── test_mistral.py ├── test_mistral │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ ├── edalize_yosys_template.tcl │ ├── minimal │ │ ├── Makefile │ │ ├── edalize_yosys_procs.tcl │ │ ├── edalize_yosys_template.tcl │ │ ├── nextpnr-mistral.cmd │ │ └── yosys.cmd │ ├── nextpnr-mistral.cmd │ └── yosys.cmd ├── test_modelsim.py ├── test_modelsim │ ├── Makefile │ ├── common_compilation │ │ ├── Makefile │ │ ├── edalize_build_rtl.tcl │ │ ├── edalize_main.tcl │ │ ├── vsim.cmd │ │ └── vsim2.cmd │ ├── edalize_build_rtl.tcl │ ├── edalize_main.tcl │ ├── vsim.cmd │ └── vsim2.cmd ├── test_morty.py ├── test_morty │ └── morty.cmd ├── test_openfpga.py ├── test_openfpga │ └── config │ │ └── task.conf ├── test_openlane.py ├── test_openlane │ ├── Makefile │ ├── config.tcl │ └── flow.tcl.cmd ├── test_oxide.py ├── test_oxide │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ ├── edalize_yosys_template.tcl │ ├── minimal │ │ ├── Makefile │ │ ├── edalize_yosys_procs.tcl │ │ ├── edalize_yosys_template.tcl │ │ ├── nextpnr-nexus.cmd │ │ ├── prjoxide.cmd │ │ └── yosys.cmd │ ├── nextpnr-nexus.cmd │ ├── prjoxide.cmd │ └── yosys.cmd ├── test_plugin.py ├── test_plugin │ └── edalize │ │ ├── flows │ │ └── customexternalflow.py │ │ ├── testplugin.py │ │ └── tools │ │ └── customtool.py ├── test_quartus.py ├── test_quartus │ ├── Pro │ │ ├── Makefile │ │ ├── qsys-generate.cmd │ │ ├── quartus_asm.cmd │ │ ├── quartus_dse.cmd │ │ ├── quartus_fit.cmd │ │ ├── quartus_sh.cmd │ │ ├── quartus_sta.cmd │ │ ├── quartus_syn.cmd │ │ └── test_quartus_0.tcl │ └── Standard │ │ ├── Makefile │ │ ├── ip-generate.cmd │ │ ├── quartus_asm.cmd │ │ ├── quartus_dse.cmd │ │ ├── quartus_fit.cmd │ │ ├── quartus_map.cmd │ │ ├── quartus_sh.cmd │ │ ├── quartus_sta.cmd │ │ └── test_quartus_0.tcl ├── test_questa_formal.py ├── test_questaformal │ ├── Makefile │ ├── edalize_build_rtl.tcl │ ├── edalize_main.tcl │ ├── qverify.cmd │ └── qverify2.cmd ├── test_radiant.py ├── test_radiant │ ├── minimal │ │ ├── radiantc.cmd │ │ ├── test_radiant_minimal_0.tcl │ │ └── test_radiant_minimal_0_run.tcl │ ├── radiantc.cmd │ ├── test_radiant_0.tcl │ └── test_radiant_0_run.tcl ├── test_reporting.py.disabled ├── test_reporting │ └── data │ │ ├── linux-on-litex-vexriscv │ │ ├── arty_a7 │ │ │ ├── top_timing.rpt │ │ │ └── top_utilization_place.rpt │ │ ├── de10nano │ │ │ ├── top.fit.rpt │ │ │ └── top.sta.rpt │ │ └── pipistrello │ │ │ ├── top.twr │ │ │ └── top_map.mrp │ │ └── picorv32 │ │ ├── README.md │ │ ├── ise-spartan6 │ │ ├── top.twr │ │ └── top_map.mrp │ │ ├── quartus-cyclone10 │ │ ├── picorv32_wrap_0_1.fit.rpt │ │ └── picorv32_wrap_0_1.sta.rpt │ │ ├── quartus-cyclone4 │ │ ├── picorv32_wrap_0_1.fit.rpt │ │ └── picorv32_wrap_0_1.sta.rpt │ │ ├── vivado-artix7 │ │ └── impl │ │ │ ├── top_timing_summary_routed.rpt │ │ │ └── top_utilization_placed.rpt │ │ └── vivado-kintex_usp │ │ └── impl │ │ ├── top_timing_summary_routed.rpt │ │ └── top_utilization_placed.rpt ├── test_rivierapro.py ├── test_rivierapro │ ├── edalize_build_rtl.tcl │ ├── edalize_build_vpi.tcl │ ├── edalize_launch.tcl │ ├── edalize_main.tcl │ ├── edalize_run.tcl │ ├── vsim.cmd │ └── vsim2.cmd ├── test_slang.py ├── test_slang │ ├── lint │ │ └── slang.cmd │ ├── preprocess │ │ └── slang.cmd │ └── slang_options │ │ └── slang.cmd ├── test_spyglass.py ├── test_spyglass │ ├── defaults │ │ ├── Makefile │ │ ├── spyglass-run-design_read.tcl │ │ ├── spyglass-run-lint_lint_rtl.tcl │ │ ├── spyglass-run-some_othergoal.tcl │ │ ├── spyglass.cmd │ │ └── test_spyglass_0.prj │ └── tooloptions │ │ ├── Makefile │ │ ├── spyglass-run-design_read.tcl │ │ ├── spyglass-run-lint_lint_rtl.tcl │ │ ├── spyglass-run-some_othergoal.tcl │ │ ├── spyglass.cmd │ │ └── test_spyglass_0.prj ├── test_symbiflow.py ├── test_symbiflow │ ├── nextpnr │ │ ├── fpga_interchange │ │ │ ├── Makefile │ │ │ ├── edalize_yosys_procs.tcl │ │ │ └── edalize_yosys_template.tcl │ │ └── xilinx │ │ │ ├── Makefile │ │ │ ├── edalize_yosys_procs.tcl │ │ │ └── edalize_yosys_template.tcl │ └── vtr │ │ └── Makefile ├── test_symbiyosys.py ├── test_symbiyosys │ ├── config.sby.j2 │ ├── files.txt │ ├── incdirs.txt │ ├── sby.cmd │ └── test.sby ├── test_tool_efinity.py ├── test_tool_gowin.py ├── test_tool_icarus.py ├── test_tool_icepack.py ├── test_tool_vcs.py ├── test_tool_verilator.py ├── test_tool_vivado.py ├── test_tool_yosys.py ├── test_trellis.py ├── test_trellis │ ├── Makefile │ ├── ecppack.cmd │ ├── edalize_yosys_procs.tcl │ ├── edalize_yosys_template.tcl │ ├── minimal │ │ ├── Makefile │ │ ├── ecppack.cmd │ │ ├── edalize_yosys_procs.tcl │ │ ├── edalize_yosys_template.tcl │ │ ├── nextpnr-ecp5.cmd │ │ └── yosys.cmd │ ├── nextpnr-ecp5.cmd │ └── yosys.cmd ├── test_vcs.py ├── test_vcs │ ├── minimal │ │ ├── Makefile │ │ ├── run.cmd │ │ ├── test_vcs_minimal_0.scr │ │ └── vcs.cmd │ ├── no_tool_options │ │ ├── Makefile │ │ ├── run.cmd │ │ ├── test_vcs_0.scr │ │ └── vcs.cmd │ └── tool_options │ │ ├── Makefile │ │ ├── run.cmd │ │ ├── test_vcs_tool_options_0.scr │ │ └── vcs.cmd ├── test_veribleformat.py ├── test_veribleformat │ └── default │ │ └── verible-verilog-format.cmd ├── test_veriblelint.py ├── test_veriblelint │ └── lint │ │ └── verible-verilog-lint.cmd ├── test_verilator.py ├── test_verilator │ ├── Makefile │ ├── Vtop_module │ ├── binary │ │ ├── config.mk │ │ └── test_verilator_0.vc │ ├── cc │ │ ├── config.mk │ │ └── test_verilator_0.vc │ ├── dpi-hdr-only │ │ ├── config.mk │ │ └── test_verilator_0.vc │ ├── lint-only │ │ ├── config.mk │ │ └── test_verilator_0.vc │ ├── preprocess-only │ │ ├── config.mk │ │ └── test_verilator_0.vc │ ├── run.cmd │ ├── sc │ │ ├── config.mk │ │ └── test_verilator_0.vc │ └── xml-only │ │ ├── config.mk │ │ └── test_verilator_0.vc ├── test_vivado.py ├── test_vivado │ ├── Makefile │ ├── board_file │ │ ├── Makefile │ │ ├── test_vivado_0.tcl │ │ ├── test_vivado_0_pgm.tcl │ │ ├── test_vivado_0_run.tcl │ │ ├── test_vivado_0_synth.tcl │ │ ├── test_vivado_minimal_0.tcl │ │ ├── test_vivado_minimal_0_pgm.tcl │ │ ├── test_vivado_minimal_0_run.tcl │ │ ├── test_vivado_minimal_0_synth.tcl │ │ └── vivado.cmd │ ├── edif_netlist │ │ ├── Makefile │ │ ├── test_vivado_0.tcl │ │ ├── test_vivado_0_pgm.tcl │ │ ├── test_vivado_0_run.tcl │ │ ├── test_vivado_0_synth.tcl │ │ └── vivado.cmd │ ├── edif_netlist_no_link_design │ │ ├── Makefile │ │ ├── test_vivado_0.tcl │ │ ├── test_vivado_0_pgm.tcl │ │ ├── test_vivado_0_run.tcl │ │ ├── test_vivado_0_synth.tcl │ │ └── vivado.cmd │ ├── minimal │ │ ├── Makefile │ │ ├── test_vivado_minimal_0.tcl │ │ ├── test_vivado_minimal_0_pgm.tcl │ │ ├── test_vivado_minimal_0_run.tcl │ │ ├── test_vivado_minimal_0_synth.tcl │ │ └── vivado.cmd │ ├── test_vivado_0.tcl │ ├── test_vivado_0_pgm.tcl │ ├── test_vivado_0_run.tcl │ ├── test_vivado_0_synth.tcl │ ├── vivado.cmd │ └── yosys │ │ ├── Makefile │ │ ├── edalize_yosys_procs.tcl │ │ ├── edalize_yosys_template.tcl │ │ ├── test_vivado_yosys_0.tcl │ │ ├── test_vivado_yosys_0_pgm.tcl │ │ ├── test_vivado_yosys_0_run.tcl │ │ ├── vivado.cmd │ │ └── yosys.cmd ├── test_vpr.py ├── test_vpr │ └── vpr │ │ └── Makefile ├── test_vunit.py ├── test_vunit │ ├── minimal │ │ └── tb_minimal.vhd │ ├── run.py │ └── vunit_mock │ │ └── vunit │ │ ├── __init__.py │ │ ├── ui.py │ │ └── vhdl_standard.py ├── test_xcelium.py ├── test_xcelium │ ├── Makefile │ ├── edalize_build_rtl.f │ ├── edalize_main.f │ └── xrun.cmd ├── test_xsim.py ├── test_xsim │ ├── Makefile │ ├── config.mk │ ├── mfc │ │ ├── Makefile │ │ ├── config.mk │ │ ├── test_xsim_0.prj │ │ ├── xelab.cmd │ │ └── xsim.cmd │ ├── test_xsim_0.prj │ ├── xelab.cmd │ └── xsim.cmd ├── test_yosys.py ├── test_yosys │ ├── custom_output_name │ │ └── Makefile │ └── default_output_name │ │ └── Makefile └── tools │ ├── efinity │ ├── Makefile │ └── design.xml │ ├── gowin │ ├── edalize_gowin_template.tcl │ └── minimal │ │ └── edalize_gowin_template.tcl │ ├── icarus │ ├── Makefile │ ├── design.scr │ └── multitop │ │ ├── Makefile │ │ └── design.scr │ ├── icepack │ └── Makefile │ ├── vcs │ ├── 2stage_basic │ │ ├── Makefile │ │ ├── parameters.txt │ │ ├── synopsys_sim.setup │ │ └── vcs.f │ ├── 2stage_minimal │ │ ├── Makefile │ │ ├── parameters.txt │ │ ├── synopsys_sim.setup │ │ └── vcs.f │ ├── basic │ │ ├── Makefile │ │ ├── libx.f │ │ ├── parameters.txt │ │ ├── synopsys_sim.setup │ │ ├── vcs.f │ │ ├── work.f │ │ ├── work_1.f │ │ └── work_2.f │ └── minimal │ │ ├── Makefile │ │ ├── libx.f │ │ ├── parameters.txt │ │ ├── synopsys_sim.setup │ │ ├── vcs.f │ │ ├── work.f │ │ ├── work_1.f │ │ └── work_2.f │ ├── verilator │ ├── Makefile │ ├── design.vc │ └── minimal │ │ ├── Makefile │ │ └── design.vc │ ├── vivado │ ├── Makefile │ ├── design.tcl │ ├── design_netlist.tcl │ ├── design_pgm.tcl │ ├── design_run.tcl │ ├── design_synth.tcl │ └── tags │ │ ├── Makefile │ │ ├── design.tcl │ │ ├── design_netlist.tcl │ │ ├── design_pgm.tcl │ │ ├── design_run.tcl │ │ └── design_synth.tcl │ └── yosys │ ├── ecp5-blif │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl │ ├── ecp5-edif │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl │ ├── ecp5-json │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl │ ├── ecp5-verilog │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl │ ├── ice40-blif │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl │ ├── ice40-edif │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl │ ├── ice40-json │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl │ ├── ice40-verilog │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl │ ├── minimal │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl │ ├── template │ ├── Makefile │ └── edalize_yosys_procs.tcl │ ├── xilinx-blif │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl │ ├── xilinx-edif │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl │ ├── xilinx-json │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl │ └── xilinx-verilog │ ├── Makefile │ ├── edalize_yosys_procs.tcl │ └── edalize_yosys_template.tcl └── tox.ini /.gitignore: -------------------------------------------------------------------------------- 1 | doc/_build/ 2 | *.egg-info/ 3 | __pycache__ 4 | /.eggs 5 | /.tox 6 | .vscode/ 7 | build/ 8 | dist/ 9 | venv/ 10 | .project 11 | .pydevproject 12 | /.pytest_cache/ 13 | 14 | # auto-generated by setuptools_scm during the build 15 | edalize/version.py 16 | -------------------------------------------------------------------------------- /.pre-commit-config.yaml: -------------------------------------------------------------------------------- 1 | # Configuration for pre-commit (https://pre-commit.com/), a tool to run 2 | # formatters, linters, and other productivity tools before a commit. 3 | repos: 4 | - repo: https://github.com/psf/black 5 | rev: "22.3.0" 6 | hooks: 7 | - id: black 8 | -------------------------------------------------------------------------------- /.readthedocs.yml: -------------------------------------------------------------------------------- 1 | # .readthedocs.yml 2 | # Read the Docs configuration file 3 | # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details 4 | 5 | # Required 6 | version: 2 7 | 8 | sphinx: 9 | configuration: doc/conf.py 10 | 11 | python: 12 | install: 13 | - requirements: doc/requirements.txt 14 | 15 | build: 16 | os: "ubuntu-22.04" 17 | tools: 18 | python: "3.11" 19 | apt_packages: 20 | - graphviz 21 | -------------------------------------------------------------------------------- /dev-requirements.txt: -------------------------------------------------------------------------------- 1 | pre-commit>=2.9.0 2 | tox 3 | -------------------------------------------------------------------------------- /doc/Makefile: -------------------------------------------------------------------------------- 1 | # Minimal makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line. 5 | SPHINXOPTS = 6 | SPHINXBUILD = sphinx-build 7 | SOURCEDIR = . 8 | BUILDDIR = _build 9 | 10 | # Put it first so that "make" without argument is like "make help". 11 | help: 12 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 13 | 14 | .PHONY: help Makefile 15 | 16 | # Catch-all target: route all unknown targets to Sphinx using the new 17 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 18 | %: Makefile 19 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 20 | -------------------------------------------------------------------------------- /doc/dev/index.rst: -------------------------------------------------------------------------------- 1 | .. _dg: 2 | 3 | ####################### 4 | Edalize Developer Guide 5 | ####################### 6 | 7 | This Developer Guide is for users who intend to work on Edalize itself and explains how to set up Edalize in development mode, run tests and how to add new features. 8 | 9 | .. toctree:: 10 | :maxdepth: 2 11 | :caption: Inside this Developer Guide 12 | :hidden: 13 | 14 | setup 15 | tests 16 | extend 17 | -------------------------------------------------------------------------------- /doc/dev/tests.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Workaround for https://github.com/sphinx-doc/sphinx/issues/701 3 | 4 | .. include:: ../../tests/README.rst 5 | -------------------------------------------------------------------------------- /doc/edam/efinity.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | "$project.bit" [shape=box,style=filled] 3 | frontends -> efinity; 4 | efinity -> "$project.bit"; 5 | } -------------------------------------------------------------------------------- /doc/edam/f4pga.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | yosyseblif [label="yosys\noutput_format=eblif"] 3 | yosysjson [label="yosys\noutput_format=json"] 4 | "$project.bit" [shape=box,style=filled] 5 | 6 | frontends -> yosysjson[label="pnr==nextpnr "]; 7 | frontends -> yosyseblif[label="pnr==vpr "]; 8 | yosysjson -> nextpnr; 9 | yosyseblif -> vpr; 10 | vpr -> genfasm; 11 | genfasm -> xcfasm; 12 | xcfasm -> "$project.bit"; 13 | } -------------------------------------------------------------------------------- /doc/edam/generic.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | "?" [shape=box,style=filled] 3 | frontends -> "$tool"; 4 | "$tool" -> "?"; 5 | } -------------------------------------------------------------------------------- /doc/edam/gls.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | "model" [shape=box,style=filled,label="Simulation model"] 3 | frontends -> "$synth"; 4 | "$synth" -> "$sim"; 5 | "$sim" -> "model"; 6 | } -------------------------------------------------------------------------------- /doc/edam/gowin.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | "$project.fs" [shape=box,style=filled] 3 | frontends -> gowin; 4 | gowin -> "$project.fs"; 5 | } -------------------------------------------------------------------------------- /doc/edam/icestorm.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | "$project.bit" [shape=box,style=filled] 3 | "$project.json" [shape=box,style=filled] 4 | yosys [label="yosys\narch=ice40\noutput_format=json"] 5 | nextpnr [label="nextpnr\narch=ice40"] 6 | 7 | frontends -> yosys; 8 | yosys -> nextpnr; 9 | yosys -> "$project.json" [label="pnr==none"]; 10 | nextpnr -> icetime; 11 | nextpnr -> icebox_stat; 12 | nextpnr -> icepack; 13 | icepack -> "$project.bit"; 14 | } -------------------------------------------------------------------------------- /doc/edam/lint.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | frontends -> "$tool"; 3 | } -------------------------------------------------------------------------------- /doc/edam/sim.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | "model" [shape=box,style=filled,label="Simulation model"] 3 | frontends -> "$tool"; 4 | "$tool" -> "model"; 5 | } -------------------------------------------------------------------------------- /doc/edam/vivado.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | yosys [label="yosys\narch=xilinx\noutput_format=edif"] 3 | vpnr [label="vivado\nsynth=none"] 4 | "$project.bit" [shape=box,style=filled] 5 | "$project.v" [shape=box,style=filled] 6 | frontends -> yosys[label="synth==yosys "]; 7 | frontends -> "vivado"[label="synth!=yosys"]; 8 | yosys -> "vpnr"; 9 | vivado -> "$project.v"[label="pnr==none"]; 10 | vivado -> "$project.bit"[label="pnr!=none"]; 11 | "vpnr" -> "$project.bit"; 12 | } -------------------------------------------------------------------------------- /doc/edam/vpr.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | yosysblif [label="yosys\noutput_format=blif"] 3 | "$project.analysis" [shape=box,style=filled] 4 | 5 | frontends -> yosysblif; 6 | yosysblif -> vpr; 7 | vpr -> "$project.analysis"; 8 | } -------------------------------------------------------------------------------- /doc/genindex.rst: -------------------------------------------------------------------------------- 1 | .. # This file is a placeholder and will be replaced 2 | 3 | Index 4 | ##### 5 | -------------------------------------------------------------------------------- /doc/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | pushd %~dp0 4 | 5 | REM Command file for Sphinx documentation 6 | 7 | if "%SPHINXBUILD%" == "" ( 8 | set SPHINXBUILD=sphinx-build 9 | ) 10 | set SOURCEDIR=. 11 | set BUILDDIR=_build 12 | 13 | if "%1" == "" goto help 14 | 15 | %SPHINXBUILD% >NUL 2>NUL 16 | if errorlevel 9009 ( 17 | echo. 18 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 19 | echo.installed, then set the SPHINXBUILD environment variable to point 20 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 21 | echo.may add the Sphinx directory to PATH. 22 | echo. 23 | echo.If you don't have Sphinx installed, grab it from 24 | echo.http://sphinx-doc.org/ 25 | exit /b 1 26 | ) 27 | 28 | %SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% 29 | goto end 30 | 31 | :help 32 | %SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% 33 | 34 | :end 35 | popd 36 | -------------------------------------------------------------------------------- /doc/py-modindex.rst: -------------------------------------------------------------------------------- 1 | .. # This file is a placeholder and will be replaced 2 | 3 | Search Page 4 | ########### 5 | -------------------------------------------------------------------------------- /doc/requirements.txt: -------------------------------------------------------------------------------- 1 | Sphinx>=3.0 2 | vunit_hdl 3 | sphinx_rtd_theme 4 | sphinx-autodoc-typehints 5 | -------------------------------------------------------------------------------- /doc/user/build.rst: -------------------------------------------------------------------------------- 1 | Build 2 | ===== 3 | 4 | .. todo:: 5 | 6 | Document the build stage 7 | -------------------------------------------------------------------------------- /doc/user/configure.rst: -------------------------------------------------------------------------------- 1 | Configure 2 | ========= 3 | 4 | .. todo:: 5 | 6 | Document the configure stage 7 | -------------------------------------------------------------------------------- /doc/user/index.rst: -------------------------------------------------------------------------------- 1 | .. _ug: 2 | 3 | ################## 4 | Edalize User Guide 5 | ################## 6 | 7 | The Edalize User Guide will guide you through how to use Edalize to set up and configure EDA flows and use them in your project. 8 | 9 | The Edalize flow is divided into three stages called `configure`, `build` and `run`. The three chapters will be looking at these stages in detail. 10 | 11 | .. include:: configure.rst 12 | .. include:: build.rst 13 | .. include:: run.rst 14 | 15 | .. include:: build_runners.rst 16 | -------------------------------------------------------------------------------- /doc/user/run.rst: -------------------------------------------------------------------------------- 1 | Run 2 | === 3 | 4 | .. todo:: 5 | 6 | Document the run stage 7 | -------------------------------------------------------------------------------- /edalize/flows/efinity.py: -------------------------------------------------------------------------------- 1 | # Copyright edalize contributors 2 | # Licensed under the 2-Clause BSD License, see LICENSE for details. 3 | # SPDX-License-Identifier: BSD-2-Clause 4 | 5 | from edalize.flows.generic import Generic 6 | 7 | 8 | class Efinity(Generic): 9 | """Efinix Efinity FPGA toolchain""" 10 | 11 | argtypes = ["generic", "vlogdefine", "vlogparam"] 12 | 13 | @classmethod 14 | def get_flow_options(cls): 15 | return {k: v for k, v in cls.FLOW_OPTIONS.items() if k != "tool"} 16 | 17 | @classmethod 18 | def get_tool_options(cls, flow_options): 19 | flow = flow_options.get("frontends", []).copy() + ["efinity"] 20 | 21 | return cls.get_filtered_tool_options(flow, cls.FLOW_DEFINED_TOOL_OPTIONS) 22 | 23 | def configure_flow(self, flow_options): 24 | self.flow_options["tool"] = "efinity" 25 | return super().configure_flow(flow_options) 26 | -------------------------------------------------------------------------------- /edalize/flows/gowin.py: -------------------------------------------------------------------------------- 1 | # Copyright edalize contributors 2 | # Licensed under the 2-Clause BSD License, see LICENSE for details. 3 | # SPDX-License-Identifier: BSD-2-Clause 4 | 5 | from edalize.flows.generic import Generic 6 | 7 | 8 | class Gowin(Generic): 9 | """Official Gowin FPGA toolchain""" 10 | 11 | argtypes = [] 12 | 13 | @classmethod 14 | def get_flow_options(cls): 15 | return {k: v for k, v in cls.FLOW_OPTIONS.items() if k != "tool"} 16 | 17 | @classmethod 18 | def get_tool_options(cls, flow_options): 19 | flow = flow_options.get("frontends", []).copy() + ["gowin"] 20 | 21 | return cls.get_filtered_tool_options(flow, cls.FLOW_DEFINED_TOOL_OPTIONS) 22 | 23 | def configure_flow(self, flow_options): 24 | self.flow_options["tool"] = "gowin" 25 | return super().configure_flow(flow_options) 26 | -------------------------------------------------------------------------------- /edalize/flows/lint.py: -------------------------------------------------------------------------------- 1 | # Copyright edalize contributors 2 | # Licensed under the 2-Clause BSD License, see LICENSE for details. 3 | # SPDX-License-Identifier: BSD-2-Clause 4 | 5 | from edalize.flows.generic import Generic 6 | 7 | 8 | class Lint(Generic): 9 | """Run a linter tool on the design""" 10 | 11 | argtypes = ["vlogdefine", "vlogparam"] 12 | 13 | FLOW_DEFINED_TOOL_OPTIONS = { 14 | "verilator": {"mode": "lint-only", "exe": "false", "make_options": []}, 15 | # verible, spyglass, ascentlint, slang... 16 | } 17 | -------------------------------------------------------------------------------- /edalize/flows/vpr.py: -------------------------------------------------------------------------------- 1 | # Copyright edalize contributors 2 | # Licensed under the 2-Clause BSD License, see LICENSE for details. 3 | # SPDX-License-Identifier: BSD-2-Clause 4 | 5 | import os.path 6 | 7 | from edalize.flows.edaflow import Edaflow, FlowGraph 8 | 9 | 10 | class Vpr(Edaflow): 11 | """VPR is an open source academic CAD tool designed for the exploration of new FPGA architectures and CAD algorithms, at the packing, placement and routing phases of the CAD flow""" 12 | 13 | argtypes = ["vlogdefine", "vlogparam"] 14 | 15 | def configure_flow(self, flow_options): 16 | 17 | flow = { 18 | "yosys": {"ftdo": {"output_format": "blif"}}, 19 | "vpr": {"deps": ["yosys"]}, 20 | } 21 | return FlowGraph.fromdict(flow) 22 | 23 | def build_tool_graph(self): 24 | return super().build_tool_graph() 25 | 26 | def configure_tools(self, nodes): 27 | super().configure_tools(nodes) 28 | name = self.edam["name"] 29 | self.commands.set_default_target(name + ".analysis") 30 | -------------------------------------------------------------------------------- /edalize/templates/ascentlint/Makefile.j2: -------------------------------------------------------------------------------- 1 | # This file is generated by edalize. 2 | 3 | NAME := {{ name }} 4 | 5 | ASCENTLINT_OPTIONS ?= {{ ascentlint_options }} 6 | all: report-violations 7 | 8 | ascentlint.log: run-ascentlint.tcl sources.f 9 | ascentlint -i run-ascentlint.tcl -log ascentlint.log $(ASCENTLINT_OPTIONS) 10 | 11 | report-violations: ascentlint.log 12 | @(egrep -q "(Found [0-9]+ info lint violations|No lint violations found)" \ 13 | ascentlint.log && echo "***PASSED***") || \ 14 | (echo "***ERROR*** Lint run found new errors or warnings." \ 15 | "Please check ascentlint.rpt" && exit 1) 16 | -------------------------------------------------------------------------------- /edalize/templates/ascentlint/run-ascentlint.tcl.j2: -------------------------------------------------------------------------------- 1 | # This file is generated by edalize. 2 | 3 | {% for waiver_file in waiver_files %} 4 | source {{ waiver_file.name }} 5 | {% endfor %} 6 | 7 | {% for tcl_source_file in tcl_source_files %} 8 | source {{ tcl_source_file.name }} 9 | {% endfor %} 10 | 11 | analyze -f sources.f 12 | elaborate {% if vlogparam -%} 13 | -params { {% for k, v in vlogparam.items() %}{ {{ k }} {{ v|param_value_str(str_quote_style = '"') }} } {% endfor -%} } 14 | {%- endif%} {{ toplevel }} 15 | report_policy -skip_empty_summary_status -compat -output ascentlint.rpt NEW 16 | exit 17 | -------------------------------------------------------------------------------- /edalize/templates/design_compiler/design-compiler-makefile.j2: -------------------------------------------------------------------------------- 1 | SHELL=/bin/bash 2 | NAME := {{ name }} 3 | {% if report_dir -%} 4 | REPORT_DIR := {{ report_dir }} 5 | {% else %} 6 | REPORT_DIR := "./" 7 | {%- endif %} 8 | 9 | 10 | all: 11 | mkdir -p ${REPORT_DIR} 12 | dc_shell-t -f ${NAME}.tcl |& tee ${REPORT_DIR}/synth.log -------------------------------------------------------------------------------- /edalize/templates/design_compiler/design-compiler-read-sources.tcl.j2: -------------------------------------------------------------------------------- 1 | # Auto-generated project tcl file to read all sources 2 | 3 | {% if incdirs -%} 4 | set search_path [concat [list {{ incdirs|join(' ') }}] $search_path] 5 | {%- endif %} 6 | 7 | {% for src_file in src_files if src_file|src_file_filter%} 8 | {{ src_file|src_file_filter }} 9 | {% endfor %} 10 | -------------------------------------------------------------------------------- /edalize/templates/genus/genus-makefile.j2: -------------------------------------------------------------------------------- 1 | SHELL=/bin/bash 2 | NAME := {{ name }} 3 | {% if report_dir -%} 4 | REPORT_DIR := {{ report_dir }} 5 | {% else %} 6 | REPORT_DIR := "./" 7 | {%- endif %} 8 | 9 | 10 | all: 11 | mkdir -p ${REPORT_DIR} 12 | genus -files ${NAME}.tcl -log ${REPORT_DIR}/synth.log -------------------------------------------------------------------------------- /edalize/templates/genus/genus-read-sources.tcl.j2: -------------------------------------------------------------------------------- 1 | # Auto-generated project tcl file to read all sources 2 | 3 | {% if incdirs -%} 4 | set_db init_hdl_search_path [list {{ incdirs|join(' ') }}] 5 | {%- endif %} 6 | 7 | {% for src_file in src_files if src_file|src_file_filter%} 8 | {{ src_file|src_file_filter }} 9 | {% endfor %} 10 | -------------------------------------------------------------------------------- /edalize/templates/ghdl/Makefile.j2: -------------------------------------------------------------------------------- 1 | # Auto generated by Edalize 2 | STD = {{ std }} 3 | TOPLEVEL = {{ toplevel }} 4 | TOPLEVEL_LIBS = {{ top_libraries }} 5 | ANALYZE_OPTIONS = {{ analyze_options }} 6 | RUN_OPTIONS = {{ run_options }} 7 | 8 | VHDL_SOURCES = {{ vhdl_sources }} 9 | 10 | all: work-obj{{ standard }}.cf 11 | 12 | run: $(TOPLEVEL) 13 | $(EDALIZE_LAUNCHER) ghdl -r $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) $(RUN_OPTIONS) $(EXTRA_OPTIONS) 14 | 15 | $(TOPLEVEL): $(VHDL_SOURCES) work-obj{{ standard }}.cf 16 | $(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) 17 | 18 | $(TOPLEVEL).v: $(VHDL_SOURCES) work-obj{{ standard }}.cf 19 | $(EDALIZE_LAUNCHER) ghdl --synth --out=verilog $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) 20 | 21 | make_libraries_directories: 22 | @echo "Creating libraries directories" 23 | {{ make_libraries_directories }} 24 | work-obj{{ standard }}.cf: make_libraries_directories 25 | {{ ghdlimport }} 26 | -------------------------------------------------------------------------------- /edalize/templates/libero/libero-run.tcl.j2: -------------------------------------------------------------------------------- 1 | # This file is generated by Edalize. 2 | # Microsemi Tcl Script 3 | # Libero 4 | 5 | source {{op}}{{name}}-project.tcl{{cl}} 6 | 7 | run_tool -name {SYNTHESIZE} 8 | run_tool -name {PLACEROUTE} 9 | run_tool -name {GENERATEPROGRAMMINGDATA} 10 | 11 | puts "To program the FPGA and SPI-Flash, run the 'Run PROGRAM Action' and 'Run PROGRAM_SPI_IMAGE Action' tools in the Design Flow menu." 12 | puts "If required, adjust the memory allocation and initialization before generating the bitstream and programming." 13 | puts "----------------- Finished building project -----------------------------" 14 | -------------------------------------------------------------------------------- /edalize/templates/libero/libero-syn-user.tcl.j2: -------------------------------------------------------------------------------- 1 | # This file is generated by Edalize. 2 | # Synplify Tcl Script 3 | # Libero 4 | 5 | {% if vlogparam -%}{%- for k,v in vlogparam.items() %} 6 | set_option -hdl_param -set {{k}}={{v}} 7 | {% endfor -%}{%- endif %} 8 | {% if vlogdefine -%}{%- for k,v in vlogdefine.items() %} 9 | set_option -hdl_define -set {{k}}={{v}} 10 | {% endfor -%}{%- endif %} 11 | {% if generic -%} 12 | set_option -hdl_param -set { 13 | {%- for k, v in generic.items() %}{{ k }}={{ v|generic_value_str(bool_is_str = True) }} {% endfor -%} 14 | } 15 | {%- endif %} 16 | 17 | {% if incdirs -%}{%- for dir in incdirs %} 18 | set_option -include_path {{op}}../../{{dir}}{{cl}} 19 | {% endfor -%}{%- endif %} 20 | -------------------------------------------------------------------------------- /edalize/templates/openfpga/task_simulation.conf.j2: -------------------------------------------------------------------------------- 1 | # Generated by EDAlize 2 | 3 | [GENERAL] 4 | run_engine = openfpga_shell 5 | power_tech_file = {{ power_tech_file }} 6 | power_analysis = true 7 | spice_output = false 8 | verilog_output = true 9 | timeout_each_job = 1*60 10 | fpga_flow = yosys_vpr 11 | arch_variable_file = {{ arch_variable_file }} 12 | 13 | [OpenFPGA_SHELL] 14 | openfpga_shell_template = {{ openfpga_shell_template }} 15 | openfpga_arch_file = {{ openfpga_arch_file }} 16 | openfpga_sim_setting_file = {{ openfpga_sim_setting_file }} 17 | external_fabric_key_file = {{ external_fabric_key_file }} 18 | openfpga_vpr_device_layout = {{ vpr_device_layout }} 19 | openfpga_vpr_route_chan_width = {{ vpr_route_chan_width }} 20 | 21 | [ARCHITECTURES] 22 | arch0 = {{ vpr_arch_file }} 23 | 24 | [BENCHMARKS] 25 | bench0 = {{ tb_verilog_file }} 26 | 27 | [SYNTHESIS_PARAM] 28 | bench0_top = {{ tb_top_entity }} 29 | 30 | [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] 31 | -------------------------------------------------------------------------------- /edalize/templates/openlane/openlane-makefile.j2: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: config.tcl 4 | $(EDALIZE_LAUNCHER) flow.tcl -tag {{top}} -save -save_path . -design . 5 | 6 | clean: 7 | rm -rf runs 8 | -------------------------------------------------------------------------------- /edalize/templates/openlane/openlane-script-tcl.j2: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | set ::env(DESIGN_NAME) {{top}} 4 | 5 | set ::env(VERILOG_FILES) [list {{file_table}}] 6 | set ::env(SYNTH_DEFINES) [list{{defines}}] 7 | 8 | {{tcl}} 9 | -------------------------------------------------------------------------------- /edalize/templates/spyglass/Makefile.j2: -------------------------------------------------------------------------------- 1 | NAME := {{ name }} 2 | 3 | run-goals: {% for goal in sanitized_goals %}run-goal-{{ goal }} {% endfor %} 4 | 5 | {% for goal in sanitized_goals %} 6 | run-goal-{{ goal }}: 7 | sg_shell -enable_pass_exit_codes -tcl spyglass-run-{{ goal }}.tcl 8 | 9 | {% endfor -%} 10 | 11 | run-gui: 12 | spyglass -project $(NAME).prj 13 | -------------------------------------------------------------------------------- /edalize/templates/spyglass/spyglass-run-goal.tcl.j2: -------------------------------------------------------------------------------- 1 | open_project {{ name }}.prj 2 | 3 | current_goal {{ goal }} 4 | 5 | # Parameters which are not used/defined in a given goal/methodology raise 6 | # a WARNING, which fails the lint process. That's a bit over the top, we hence 7 | # disable this warning. 8 | waive -rule {checkCMD_unknown} 9 | 10 | set rc [run_goal] 11 | close_project -force 12 | 13 | set errorCode [lindex $rc 0] 14 | set errorMsg [lindex $rc 1] 15 | if { $errorCode } { 16 | puts stderr "SpyGlass run failed: $errorMsg ($errorCode)" 17 | } 18 | 19 | # requires sg_shell to be called with -enable_pass_exit_codes, otherwise 20 | # all non-fatal exit codes are mapped to 0 21 | exit $errorCode 22 | -------------------------------------------------------------------------------- /edalize/templates/vcs/Makefile.j2: -------------------------------------------------------------------------------- 1 | all: {{ name }} 2 | 3 | {{ name }}: {{ name }}.scr 4 | $(EDALIZE_LAUNCHER) vcs -full64 -top {{ toplevel }} -f {{ name }}.scr -o $@ {% for option in vcs_options %} {{ option }}{% endfor %} 5 | 6 | run: {{ name }} 7 | ./{{ name }} -l vcs.log {% for plusarg in plusargs %} {{ plusarg }} {% endfor %}{% for option in run_options %} {{ option }}{% endfor %} 8 | 9 | clean: 10 | $(RM) {{ name }} 11 | -------------------------------------------------------------------------------- /edalize/templates/vivado/vivado-synth.tcl.j2: -------------------------------------------------------------------------------- 1 | launch_runs synth_1{{ jobs }} 2 | wait_on_run synth_1 3 | exit [regexp -nocase -- {synth_design (error|failed)} [get_property STATUS [get_runs synth_1]] match] 4 | -------------------------------------------------------------------------------- /edalize/templates/yosys/edalize_yosys_procs.tcl.j2: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | {{ file_table }} 3 | } 4 | 5 | proc set_defines {} { 6 | {% if verilog_defines -%} 7 | set defines {{ verilog_defines }} 8 | 9 | foreach d ${defines} { 10 | set key [lindex $d 0] 11 | set val [lindex $d 1] 12 | verilog_defines "-D$key=$val" 13 | } 14 | {%- endif %} 15 | } 16 | 17 | proc set_incdirs {} { 18 | {% if incdirs -%} 19 | verilog_defaults -add {{ incdirs }} 20 | {%- endif %} 21 | } 22 | 23 | proc set_params {} { 24 | {% if verilog_params -%} 25 | {{ verilog_params }} 26 | {%- endif %} 27 | } 28 | 29 | proc synth {top} { 30 | {{ synth_command }} {{ synth_options }} -top $top 31 | } 32 | 33 | set top {{ top }} 34 | set name {{ name }} 35 | -------------------------------------------------------------------------------- /edalize/templates/yosys/yosys-script-tcl.j2: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | {{ write_command }} {{ output_opts -}} {{ output_name }} 17 | -------------------------------------------------------------------------------- /edalize/tools/templates/efinity/isf_to_xml.py: -------------------------------------------------------------------------------- 1 | import os 2 | import sys 3 | 4 | sys.path.append(os.getenv("EFXPT_HOME") + "/bin") 5 | 6 | from api_service.design import DesignAPI 7 | import api_service.excp.design_excp as APIExcp 8 | 9 | design = DesignAPI(False) 10 | 11 | name = sys.argv[1] 12 | part = sys.argv[2] 13 | workdir = "." 14 | isf_file = sys.argv[3] 15 | design.create(name, part, workdir) 16 | design.import_design(isf_file) 17 | design.generate(enable_bitstream=False) 18 | design.save_as(name + ".peri.xml") 19 | -------------------------------------------------------------------------------- /edalize/tools/templates/gowin/gowin-project.tcl.j2: -------------------------------------------------------------------------------- 1 | set_device {{ tool_options.part }} {{ "--device_version " + tool_options.part_version if tool_options.part_version else "" }} 2 | 3 | 4 | {% for src_file in file_table %} 5 | {{ src_file }} 6 | {% endfor %} 7 | 8 | set_option -top_module {{ toplevel }} 9 | {{ "set_option -vhdl_std vhd2008" if has_vhdl2008 else "" }} 10 | {{ "set_option -verilog_std sysv2017" if has_systemVerilog else "" }} 11 | 12 | {% for option in tool_options.gowin_options %} 13 | set_option {{ option }} 14 | {% endfor %} 15 | 16 | 17 | {{ "run syn" if tool_options.synth == "gowin" else "" }} 18 | {{ "run pnr" if tool_options.pnr == "gowin" else "" }} -------------------------------------------------------------------------------- /edalize/tools/templates/vivado/vivado-netlist.tcl.j2: -------------------------------------------------------------------------------- 1 | open_run synth_1 2 | write_edif [current_project].edn 3 | write_verilog [current_project].v 4 | -------------------------------------------------------------------------------- /edalize/tools/templates/vivado/vivado-synth.tcl.j2: -------------------------------------------------------------------------------- 1 | set outdated [get_property NEEDS_REFRESH [get_runs synth_1]] 2 | set progress [get_property PROGRESS [get_runs synth_1]] 3 | 4 | if {$outdated || $progress != "100%"} { 5 | reset_runs synth_1 6 | launch_runs synth_1{{ jobs }} 7 | wait_on_run synth_1 8 | } 9 | #exit [regexp -nocase -- {synth_design (error|failed)} [get_property STATUS [get_runs synth_1]] match] 10 | -------------------------------------------------------------------------------- /edalize/tools/templates/yosys/edalize_yosys_procs.tcl.j2: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | {% if plugins -%} 3 | {{ plugins }} 4 | {%- endif %} 5 | } 6 | 7 | proc read_files {} { 8 | {{ file_table }} 9 | } 10 | 11 | proc set_defines {} { 12 | {% if verilog_defines -%} 13 | set defines {{ verilog_defines }} 14 | 15 | foreach d ${defines} { 16 | set key [lindex $d 0] 17 | set val [lindex $d 1] 18 | verilog_defines "-D$key=$val" 19 | } 20 | {%- endif %} 21 | } 22 | 23 | proc set_incdirs {} { 24 | {% if incdirs -%} 25 | verilog_defaults -add {{ incdirs }} 26 | {%- endif %} 27 | } 28 | 29 | proc set_params {} { 30 | {% if verilog_params -%} 31 | {{ verilog_params }} 32 | {%- endif %} 33 | } 34 | 35 | proc synth {top} { 36 | {{ synth_command }} {{ synth_options }} -top $top 37 | } 38 | 39 | set top {{ top }} 40 | set name {{ name }} 41 | -------------------------------------------------------------------------------- /edalize/tools/templates/yosys/yosys-script-tcl.j2: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | {{ write_command }} {{ output_opts -}} $name.{{ output_format }} 19 | -------------------------------------------------------------------------------- /tests/__init__.py: -------------------------------------------------------------------------------- 1 | import pytest 2 | 3 | pytest.register_assert_rewrite("tests.edalize_common") 4 | -------------------------------------------------------------------------------- /tests/flows/gls/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: post_build 4 | 5 | pre_build: 6 | 7 | design.v: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv | pre_build 8 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 9 | 10 | design: design.v design.scr 11 | $(EDALIZE_LAUNCHER) iverilog -stop_module -c design.scr -o design 12 | 13 | run: design 14 | $(EDALIZE_LAUNCHER) vvp -n -M. design -fst $(EXTRA_OPTIONS) 15 | 16 | post_build: design 17 | 18 | pre_run: 19 | 20 | run: pre_run 21 | 22 | post_run: run 23 | -------------------------------------------------------------------------------- /tests/flows/gls/design.scr: -------------------------------------------------------------------------------- 1 | +define+vlogdefine_bool=1 2 | +define+vlogdefine_int=42 3 | +define+vlogdefine_str=hello 4 | +parameter+top_module.vlogparam_bool=1 5 | +parameter+top_module.vlogparam_int=42 6 | +parameter+top_module.vlogparam_str="hello" 7 | design.v 8 | -------------------------------------------------------------------------------- /tests/flows/gls/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 None 27 | chparam -set vlogparam_int 42 None 28 | chparam -set vlogparam_str {"hello"} None} 29 | 30 | proc synth {top} { 31 | synth_ice40 -top $top 32 | } 33 | 34 | set top None 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/flows/gls/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_verilog $name.v 19 | -------------------------------------------------------------------------------- /tests/flows/lint/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: post_build 4 | 5 | pre_build: 6 | 7 | Vtop_module.mk: design.vc sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv | pre_build 8 | $(EDALIZE_LAUNCHER) verilator -f design.vc 9 | 10 | post_build: Vtop_module.mk 11 | 12 | pre_run: 13 | 14 | run: pre_run 15 | 16 | post_run: run 17 | -------------------------------------------------------------------------------- /tests/flows/lint/design.vc: -------------------------------------------------------------------------------- 1 | --Mdir . 2 | --lint-only 3 | +incdir+. 4 | -CFLAGS -I. 5 | sv_file.sv 6 | vlog_file.v 7 | vlog_with_define.v 8 | vlog05_file.v 9 | another_sv_file.sv 10 | --top-module top_module 11 | 12 | c_file.c 13 | cpp_file.cpp 14 | -Gvlogparam_bool=1 15 | -Gvlogparam_int=42 16 | -Gvlogparam_str=\"hello\" 17 | -Dvlogdefine_bool=1 18 | -Dvlogdefine_int=42 19 | -Dvlogdefine_str=hello 20 | -------------------------------------------------------------------------------- /tests/flows/sim/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: post_build 4 | 5 | pre_build: 6 | 7 | design: sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv design.scr | pre_build 8 | $(EDALIZE_LAUNCHER) iverilog -stop_module -c design.scr -o design 9 | 10 | run: design 11 | $(EDALIZE_LAUNCHER) vvp -n -M. design -fst $(EXTRA_OPTIONS) 12 | 13 | post_build: design 14 | 15 | pre_run: 16 | 17 | run: pre_run 18 | 19 | post_run: run 20 | -------------------------------------------------------------------------------- /tests/flows/sim/design.scr: -------------------------------------------------------------------------------- 1 | +define+vlogdefine_bool=1 2 | +define+vlogdefine_int=42 3 | +define+vlogdefine_str=hello 4 | +parameter+top_module.vlogparam_bool=1 5 | +parameter+top_module.vlogparam_int=42 6 | +parameter+top_module.vlogparam_str="hello" 7 | +incdir+. 8 | sv_file.sv 9 | vlog_file.v 10 | vlog_with_define.v 11 | vlog05_file.v 12 | another_sv_file.sv 13 | -------------------------------------------------------------------------------- /tests/flows/sim/with_cocotb/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: post_build 4 | 5 | pre_build: 6 | 7 | Vtop.mk: design.vc sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv | pre_build 8 | $(EDALIZE_LAUNCHER) verilator -f design.vc `cocotb-config --share`/lib/verilator/verilator.cpp 9 | 10 | Vtop: Vtop.mk c_file.c cpp_file.cpp | pre_build 11 | $(EDALIZE_LAUNCHER) make -f Vtop.mk 12 | 13 | post_build: Vtop 14 | 15 | pre_run: 16 | 17 | run: pre_run 18 | 19 | post_run: run 20 | -------------------------------------------------------------------------------- /tests/flows/sim/with_cocotb/design.vc: -------------------------------------------------------------------------------- 1 | --Mdir . 2 | --cc 3 | --vpi 4 | --public-flat-rw --prefix Vtop 5 | -LDFLAGS "-Wl,-rpath,`cocotb-config --lib-dir` -L`cocotb-config --lib-dir` -lcocotbvpi_verilator" 6 | +incdir+. 7 | -CFLAGS -I. 8 | sv_file.sv 9 | vlog_file.v 10 | vlog_with_define.v 11 | vlog05_file.v 12 | another_sv_file.sv 13 | --top-module top_module 14 | 15 | --exe 16 | c_file.c 17 | cpp_file.cpp 18 | -Gvlogparam_bool=1 19 | -Gvlogparam_int=42 20 | -Gvlogparam_str=\"hello\" 21 | -Dvlogdefine_bool=1 22 | -Dvlogdefine_int=42 23 | -Dvlogdefine_str=hello 24 | -------------------------------------------------------------------------------- /tests/mock_commands/arachne-pnr: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | is_argvalue = False 6 | for arg in sys.argv[1:]: 7 | if not (is_argvalue or arg[0] == "-"): 8 | input_file = arg 9 | is_argvalue = arg[0] == "-" 10 | 11 | output_file = input_file[0:-4] + "txt" 12 | with open(output_file, "a"): 13 | os.utime(output_file, None) 14 | 15 | with open("arachne-pnr.cmd", "w") as f: 16 | f.write(" ".join(sys.argv[1:]) + "\n") 17 | -------------------------------------------------------------------------------- /tests/mock_commands/ascentlint: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import sys 3 | 4 | with open("ascentlint.cmd", "w") as f: 5 | f.write(" ".join(sys.argv[1:]) + "\n") 6 | 7 | with open("ascentlint.log", "w") as f: 8 | f.write("No lint violations found\n") 9 | -------------------------------------------------------------------------------- /tests/mock_commands/diamondc: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("diamondc.cmd", "a") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/ecppack: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | output_file = sys.argv[2] 6 | with open(output_file, "a"): 7 | # set the access and modified times to the current time 8 | os.utime(output_file, None) 9 | 10 | with open("ecppack.cmd", "w") as f: 11 | f.write(" ".join(sys.argv[1:]) + "\n") 12 | -------------------------------------------------------------------------------- /tests/mock_commands/flow.tcl: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | echo "$@" > flow.tcl.cmd 3 | -------------------------------------------------------------------------------- /tests/mock_commands/ghdl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | cmd_file = "analyze.cmd" if sys.argv[1] == "-i" else "elab-run.cmd" 6 | 7 | with open(cmd_file, "a") as f: 8 | f.write(" ".join(sys.argv[1:]) + "\n") 9 | 10 | if sys.argv[1] == "-i": 11 | for arg in sys.argv: 12 | if arg.startswith("--std"): 13 | std = arg.split("=")[1] 14 | output_file = "work-obj" + std + ".cf" 15 | with open(output_file, "a"): 16 | # set the access and modified times to the current time 17 | os.utime(output_file, None) 18 | -------------------------------------------------------------------------------- /tests/mock_commands/gowin_pack: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | output_file = sys.argv[sys.argv.index("-o") + 1] 6 | with open(output_file, "a"): 7 | # set the access and modified times to the current time 8 | os.utime(output_file, None) 9 | 10 | with open("gowin_pack.cmd", "w") as f: 11 | f.write(" ".join(sys.argv[1:]) + "\n") 12 | -------------------------------------------------------------------------------- /tests/mock_commands/icepack: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | output_file = sys.argv[2] 6 | with open(output_file, "a"): 7 | # set the access and modified times to the current time 8 | os.utime(output_file, None) 9 | 10 | with open("icepack.cmd", "w") as f: 11 | f.write(" ".join(sys.argv[1:]) + "\n") 12 | -------------------------------------------------------------------------------- /tests/mock_commands/ip-generate: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("ip-generate.cmd", "w") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/iverilog: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | grab_input = False 6 | for arg in sys.argv: 7 | if grab_input: 8 | output_file = arg 9 | grab_input = arg == "-o" 10 | 11 | with open(output_file, "a"): 12 | os.utime(output_file, None) 13 | 14 | with open("iverilog.cmd", "w") as f: 15 | f.write(" ".join(sys.argv[1:]) + "\n") 16 | -------------------------------------------------------------------------------- /tests/mock_commands/iverilog-vpi: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | for arg in sys.argv: 6 | if arg.startswith("--name="): 7 | output_file = arg[7:] + ".vpi" 8 | 9 | with open(output_file, "a"): 10 | os.utime(output_file, None) 11 | 12 | with open("iverilog-vpi.cmd", "a") as f: 13 | f.write(" ".join(sys.argv[1:]) + "\n") 14 | -------------------------------------------------------------------------------- /tests/mock_commands/morty: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | echo "$@" > morty.cmd 3 | -------------------------------------------------------------------------------- /tests/mock_commands/nextpnr-ecp5: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | output_file = sys.argv[sys.argv.index("--textcfg") + 1] 6 | 7 | with open(output_file, "a"): 8 | os.utime(output_file, None) 9 | 10 | with open("nextpnr-ecp5.cmd", "w") as f: 11 | f.write(" ".join(sys.argv[1:]) + "\n") 12 | -------------------------------------------------------------------------------- /tests/mock_commands/nextpnr-gowin: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | output_file = sys.argv[sys.argv.index("--write") + 1] 6 | 7 | with open(output_file, "a"): 8 | os.utime(output_file, None) 9 | 10 | with open("nextpnr-gowin.cmd", "w") as f: 11 | f.write(" ".join(sys.argv[1:]) + "\n") 12 | -------------------------------------------------------------------------------- /tests/mock_commands/nextpnr-ice40: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | output_file = sys.argv[sys.argv.index("--asc") + 1] 6 | 7 | with open(output_file, "a"): 8 | os.utime(output_file, None) 9 | 10 | with open("nextpnr-ice40.cmd", "w") as f: 11 | f.write(" ".join(sys.argv[1:]) + "\n") 12 | -------------------------------------------------------------------------------- /tests/mock_commands/nextpnr-mistral: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | output_file = sys.argv[sys.argv.index("--rbf") + 1] 6 | 7 | with open(output_file, "a"): 8 | os.utime(output_file, None) 9 | 10 | with open("nextpnr-mistral.cmd", "w") as f: 11 | f.write(" ".join(sys.argv[1:]) + "\n") 12 | -------------------------------------------------------------------------------- /tests/mock_commands/nextpnr-nexus: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | output_file = sys.argv[sys.argv.index("--fasm") + 1] 6 | 7 | with open(output_file, "a"): 8 | os.utime(output_file, None) 9 | 10 | with open("nextpnr-nexus.cmd", "w") as f: 11 | f.write(" ".join(sys.argv[1:]) + "\n") 12 | -------------------------------------------------------------------------------- /tests/mock_commands/p_r: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | output_file = sys.argv[sys.argv.index("-o") + 1] 6 | with open(output_file, "a"): 7 | # set the access and modified times to the current time 8 | os.utime(output_file, None) 9 | 10 | with open("p_r.cmd", "w") as f: 11 | f.write(" ".join(sys.argv[1:]) + "\n") 12 | -------------------------------------------------------------------------------- /tests/mock_commands/prjoxide: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | output_file = sys.argv[3] 6 | with open(output_file, "a"): 7 | # set the access and modified times to the current time 8 | os.utime(output_file, None) 9 | 10 | with open("prjoxide.cmd", "w") as f: 11 | f.write(" ".join(sys.argv[1:]) + "\n") 12 | -------------------------------------------------------------------------------- /tests/mock_commands/qsys-generate: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("qsys-generate.cmd", "w") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/quartus_asm: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("quartus_asm.cmd", "w") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/quartus_dse: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("quartus_dse.cmd", "w") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/quartus_fit: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("quartus_fit.cmd", "w") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/quartus_map: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("quartus_map.cmd", "w") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/quartus_pgm: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | echo "$@" > run.cmd 3 | -------------------------------------------------------------------------------- /tests/mock_commands/quartus_sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | # Emulate the behaviour of --version to help with testing. 6 | if len(sys.argv) > 1 and sys.argv[1] == "--version": 7 | # Check the test specific environment variable to determine whether to 8 | # present Quartus Pro or Quartus Std information 9 | if os.getenv("FUSESOC_QUARTUS_EDITION", "Standard") == "Pro": 10 | print("Version 17.1.2 Build 304 01/31/2018 SJ Pro Edition") 11 | else: 12 | print("Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition") 13 | sys.exit(0) 14 | 15 | with open("quartus_sh.cmd", "w") as f: 16 | f.write(" ".join(sys.argv[1:]) + "\n") 17 | -------------------------------------------------------------------------------- /tests/mock_commands/quartus_sta: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("quartus_sta.cmd", "w") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/quartus_syn: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("quartus_syn.cmd", "w") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/qverify: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("qverify.cmd", "w") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/radiantc: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("radiantc.cmd", "a") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/sby: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import sys 3 | 4 | with open("sby.cmd", "a") as f: 5 | f.write(" ".join(sys.argv[1:]) + "\n") 6 | -------------------------------------------------------------------------------- /tests/mock_commands/sg_shell: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("spyglass.cmd", "a") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/slang: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("slang.cmd", "w") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/vcs: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | # output_file is the argument to the option `-o` 6 | output_file = sys.argv[sys.argv.index("-o") + 1] 7 | 8 | # output_file, when executed, will record the arguments it has been called with 9 | # in a file `run.cmd` 10 | with open(output_file, "w") as f: 11 | s = """#!/usr/bin/env python3 12 | import sys 13 | with open('run.cmd', 'w') as f: 14 | f.write(' '.join(sys.argv[1:]) + '\\n') 15 | """ 16 | f.write(s) 17 | 18 | # make file executable 19 | os.chmod(output_file, 0o755) 20 | 21 | # write out the arguments this mock has been called with to `vcs.cmd` 22 | with open("vcs.cmd", "w") as f: 23 | f.write(" ".join(sys.argv[1:]) + "\n") 24 | -------------------------------------------------------------------------------- /tests/mock_commands/verible-verilog-format: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import sys 3 | 4 | with open("verible-verilog-format.cmd", "a") as f: 5 | f.write(" ".join(sys.argv[1:]) + "\n") 6 | -------------------------------------------------------------------------------- /tests/mock_commands/verible-verilog-lint: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import sys 3 | 4 | with open("verible-verilog-lint.cmd", "a") as f: 5 | f.write(" ".join(sys.argv[1:]) + "\n") 6 | -------------------------------------------------------------------------------- /tests/mock_commands/vivado: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("vivado.cmd", "a") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/vsim: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | with open("vsim.cmd", "w") as f: 6 | f.write(" ".join(sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/vvp: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | echo "$@" > vvp.cmd 3 | -------------------------------------------------------------------------------- /tests/mock_commands/xcelium/tools/bin/xrun: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import sys 3 | import shlex 4 | 5 | with open("xrun.cmd", "w") as f: 6 | f.write(" ".join(shlex.quote(arg) for arg in sys.argv[1:]) + "\n") 7 | -------------------------------------------------------------------------------- /tests/mock_commands/xcelium/xmroot: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import pathlib 3 | 4 | print(pathlib.Path(__file__).resolve().parent) 5 | -------------------------------------------------------------------------------- /tests/mock_commands/xelab: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | echo "$@" > xelab.cmd 3 | -------------------------------------------------------------------------------- /tests/mock_commands/xsim: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | echo "$@" > xsim.cmd 3 | -------------------------------------------------------------------------------- /tests/mock_commands/xtclsh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | # Pretend xtclsh is called to create the .xise file 6 | if len(sys.argv) == 2: 7 | output_file = sys.argv[1][0:-3] + "xise" 8 | with open(output_file, "a"): 9 | os.utime(output_file, None) 10 | 11 | with open("xtclsh.cmd", "a") as f: 12 | f.write(" ".join(sys.argv[1:]) + "\n") 13 | -------------------------------------------------------------------------------- /tests/mock_commands/yosys: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import sys 4 | 5 | grab_input = False 6 | for arg in sys.argv: 7 | if grab_input: 8 | input_file = arg.replace(" ", "_") 9 | grab_input = arg == "-p" 10 | 11 | output_file = input_file[0:-3] + "blif" 12 | with open(output_file, "a"): 13 | os.utime(output_file, None) 14 | 15 | output_file = input_file[0:-3] + "json" 16 | with open(output_file, "a"): 17 | os.utime(output_file, None) 18 | 19 | with open("yosys.cmd", "w") as f: 20 | f.write(" ".join(sys.argv[1:]) + "\n") 21 | -------------------------------------------------------------------------------- /tests/test_apicula/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: test_apicula_0.fs 4 | 5 | test_apicula_0.json: edalize_yosys_template.tcl 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | 8 | test_apicula_0.pack: test_apicula_0.json 9 | $(EDALIZE_LAUNCHER) nextpnr-gowin -l next.log --device GW1N-LV1QN48C6/I5 a few nextpnr_options --json test_apicula_0.json --write test_apicula_0.pack 10 | 11 | build-gui: test_apicula_0.json 12 | $(EDALIZE_LAUNCHER) nextpnr-gowin -l next.log --device GW1N-LV1QN48C6/I5 a few nextpnr_options --json test_apicula_0.json --write test_apicula_0.pack --gui 13 | 14 | test_apicula_0.fs: test_apicula_0.pack 15 | $(EDALIZE_LAUNCHER) gowin_pack -d GW1N-LV1QN48C6/I5 -o test_apicula_0.fs test_apicula_0.pack 16 | -------------------------------------------------------------------------------- /tests/test_apicula/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | read_verilog -sv {sv_file.sv} 3 | source {tcl_file.tcl} 4 | read_verilog {vlog_file.v} 5 | read_verilog {vlog_with_define.v} 6 | read_verilog {vlog05_file.v} 7 | read_verilog -sv {another_sv_file.sv} 8 | } 9 | 10 | proc set_defines {} { 11 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 12 | 13 | foreach d ${defines} { 14 | set key [lindex $d 0] 15 | set val [lindex $d 1] 16 | verilog_defines "-D$key=$val" 17 | }} 18 | 19 | proc set_incdirs {} { 20 | verilog_defaults -add -I.} 21 | 22 | proc set_params {} { 23 | chparam -set vlogparam_bool 1 top_module 24 | chparam -set vlogparam_int 42 top_module 25 | chparam -set vlogparam_str {"hello"} top_module} 26 | 27 | proc synth {top} { 28 | synth_gowin -json test_apicula_0.json some yosys_synth_options -top $top 29 | } 30 | 31 | set top top_module 32 | set name test_apicula_0 33 | -------------------------------------------------------------------------------- /tests/test_apicula/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | write_json test_apicula_0.json 17 | -------------------------------------------------------------------------------- /tests/test_apicula/gowin_pack.cmd: -------------------------------------------------------------------------------- 1 | -d GW1N-LV1QN48C6/I5 -o test_apicula_0.fs test_apicula_0.pack 2 | -------------------------------------------------------------------------------- /tests/test_apicula/minimal/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: test_apicula_0.fs 4 | 5 | test_apicula_0.json: edalize_yosys_template.tcl 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | 8 | test_apicula_0.pack: test_apicula_0.json 9 | $(EDALIZE_LAUNCHER) nextpnr-gowin -l next.log --device GW1N-LV1QN48C6/I5 --json test_apicula_0.json --write test_apicula_0.pack 10 | 11 | build-gui: test_apicula_0.json 12 | $(EDALIZE_LAUNCHER) nextpnr-gowin -l next.log --device GW1N-LV1QN48C6/I5 --json test_apicula_0.json --write test_apicula_0.pack --gui 13 | 14 | test_apicula_0.fs: test_apicula_0.pack 15 | $(EDALIZE_LAUNCHER) gowin_pack -d GW1N-LV1QN48C6/I5 -o test_apicula_0.fs test_apicula_0.pack 16 | -------------------------------------------------------------------------------- /tests/test_apicula/minimal/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | 3 | } 4 | 5 | proc set_defines {} { 6 | set defines {} 7 | 8 | foreach d ${defines} { 9 | set key [lindex $d 0] 10 | set val [lindex $d 1] 11 | verilog_defines "-D$key=$val" 12 | }} 13 | 14 | proc set_incdirs {} { 15 | } 16 | 17 | proc set_params {} { 18 | } 19 | 20 | proc synth {top} { 21 | synth_gowin -json test_apicula_0.json -top $top 22 | } 23 | 24 | set top top_module 25 | set name test_apicula_0 26 | -------------------------------------------------------------------------------- /tests/test_apicula/minimal/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | write_json test_apicula_0.json 17 | -------------------------------------------------------------------------------- /tests/test_apicula/minimal/gowin_pack.cmd: -------------------------------------------------------------------------------- 1 | -d GW1N-LV1QN48C6/I5 -o test_apicula_0.fs test_apicula_0.pack 2 | -------------------------------------------------------------------------------- /tests/test_apicula/minimal/nextpnr-gowin.cmd: -------------------------------------------------------------------------------- 1 | -l next.log --device GW1N-LV1QN48C6/I5 --json test_apicula_0.json --write test_apicula_0.pack 2 | -------------------------------------------------------------------------------- /tests/test_apicula/minimal/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_apicula/nextpnr-gowin.cmd: -------------------------------------------------------------------------------- 1 | -l next.log --device GW1N-LV1QN48C6/I5 a few nextpnr_options --json test_apicula_0.json --write test_apicula_0.pack 2 | -------------------------------------------------------------------------------- /tests/test_apicula/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_ascentlint.py: -------------------------------------------------------------------------------- 1 | from .edalize_common import make_edalize_test 2 | 3 | 4 | def test_ascentlint_defaults(make_edalize_test): 5 | """Test the default configuration of Ascent Lint""" 6 | tf = make_edalize_test( 7 | "ascentlint", 8 | test_name="test_ascentlint", 9 | param_types=["vlogdefine", "vlogparam"], 10 | ref_dir="defaults", 11 | ) 12 | 13 | tf.backend.configure() 14 | 15 | tf.compare_files(["Makefile", "run-ascentlint.tcl", "sources.f"]) 16 | 17 | tf.backend.build() 18 | 19 | tf.compare_files(["ascentlint.cmd"]) 20 | -------------------------------------------------------------------------------- /tests/test_ascentlint/defaults/Makefile: -------------------------------------------------------------------------------- 1 | # This file is generated by edalize. 2 | 3 | NAME := test_ascentlint 4 | 5 | ASCENTLINT_OPTIONS ?= 6 | all: report-violations 7 | 8 | ascentlint.log: run-ascentlint.tcl sources.f 9 | ascentlint -i run-ascentlint.tcl -log ascentlint.log $(ASCENTLINT_OPTIONS) 10 | 11 | report-violations: ascentlint.log 12 | @(egrep -q "(Found [0-9]+ info lint violations|No lint violations found)" \ 13 | ascentlint.log && echo "***PASSED***") || \ 14 | (echo "***ERROR*** Lint run found new errors or warnings." \ 15 | "Please check ascentlint.rpt" && exit 1) 16 | -------------------------------------------------------------------------------- /tests/test_ascentlint/defaults/ascentlint.cmd: -------------------------------------------------------------------------------- 1 | -i run-ascentlint.tcl -log ascentlint.log 2 | -------------------------------------------------------------------------------- /tests/test_ascentlint/defaults/run-ascentlint.tcl: -------------------------------------------------------------------------------- 1 | # This file is generated by edalize. 2 | 3 | source waiver_file.waiver 4 | 5 | source tcl_file.tcl 6 | 7 | analyze -f sources.f 8 | elaborate -params { { vlogparam_bool 1 } { vlogparam_int 42 } { vlogparam_str "hello" } } top_module 9 | report_policy -skip_empty_summary_status -compat -output ascentlint.rpt NEW 10 | exit 11 | -------------------------------------------------------------------------------- /tests/test_ascentlint/defaults/sources.f: -------------------------------------------------------------------------------- 1 | +define+vlogdefine_bool=1 2 | +define+vlogdefine_int=42 3 | +define+vlogdefine_str=hello 4 | +incdir+. 5 | sv_file.sv 6 | vlog_file.v 7 | vlog_with_define.v 8 | vlog05_file.v 9 | another_sv_file.sv 10 | -------------------------------------------------------------------------------- /tests/test_diamond/diamondc.cmd: -------------------------------------------------------------------------------- 1 | test_diamond_0.tcl 2 | test_diamond_0_run.tcl 3 | -------------------------------------------------------------------------------- /tests/test_diamond/minimal/diamondc.cmd: -------------------------------------------------------------------------------- 1 | test_diamond_minimal_0.tcl 2 | test_diamond_minimal_0_run.tcl 3 | -------------------------------------------------------------------------------- /tests/test_diamond/minimal/test_diamond_minimal_0.tcl: -------------------------------------------------------------------------------- 1 | #Generated by Edalize 2 | prj_project new -name test_diamond_minimal_0 -dev LFE5U-85F-6BG381C -synthesis synplify 3 | prj_impl option top [] 4 | 5 | prj_project save 6 | exit 7 | -------------------------------------------------------------------------------- /tests/test_diamond/minimal/test_diamond_minimal_0_run.tcl: -------------------------------------------------------------------------------- 1 | #Generated by Edalize 2 | prj_project open test_diamond_minimal_0.ldf 3 | prj_run Synthesis 4 | prj_run Export -task Bitgen 5 | prj_project save 6 | prj_project close 7 | -------------------------------------------------------------------------------- /tests/test_diamond/test_diamond_0.tcl: -------------------------------------------------------------------------------- 1 | #Generated by Edalize 2 | prj_project new -name test_diamond_0 -dev LFE5U-85F-6BG381C -lpf lpf_file.lpf -synthesis synplify 3 | prj_impl option top top_module 4 | prj_strgy set_value -strategy Strategy1 syn_vhdl2008=True 5 | prj_impl option {include path} {.} 6 | prj_impl option HDL_PARAM {generic_bool=1;generic_int=42;generic_str="hello"} 7 | prj_impl option HDL_PARAM {vlogparam_bool=1;vlogparam_int=42;vlogparam_str="hello"} 8 | prj_impl option VERILOG_DIRECTIVES {vlogdefine_bool=True;vlogdefine_int=42;vlogdefine_str=hello} 9 | prj_src add -format SDC sdc_file 10 | prj_src add -format Verilog sv_file.sv 11 | source tcl_file.tcl 12 | prj_src add -format Verilog vlog_file.v 13 | prj_src add -format Verilog vlog_with_define.v 14 | prj_src add -format Verilog vlog05_file.v 15 | prj_src add -format VHDL vhdl_file.vhd 16 | prj_src add -format VHDL -work libx vhdl_lfile 17 | prj_src add -format VHDL vhdl2008_file 18 | prj_src add -format Verilog another_sv_file.sv 19 | prj_project save 20 | exit 21 | -------------------------------------------------------------------------------- /tests/test_diamond/test_diamond_0_run.tcl: -------------------------------------------------------------------------------- 1 | #Generated by Edalize 2 | prj_project open test_diamond_0.ldf 3 | prj_run Synthesis 4 | prj_run Export -task Bitgen 5 | prj_project save 6 | prj_project close 7 | -------------------------------------------------------------------------------- /tests/test_edam/exit_1_script: -------------------------------------------------------------------------------- 1 | exit 1 2 | -------------------------------------------------------------------------------- /tests/test_flow_gls.py: -------------------------------------------------------------------------------- 1 | from .edalize_flow_common import flow_fixture 2 | 3 | 4 | def test_gls(flow_fixture): 5 | flow_options = {"synth": "yosys", "sim": "icarus", "arch": "ice40"} 6 | ff = flow_fixture("gls", flow_options=flow_options) 7 | 8 | ff.flow.configure() 9 | ff.compare_config_files( 10 | [ 11 | "design.scr", 12 | "edalize_yosys_procs.tcl", 13 | "edalize_yosys_template.tcl", 14 | "Makefile", 15 | ] 16 | ) 17 | -------------------------------------------------------------------------------- /tests/test_flow_lint.py: -------------------------------------------------------------------------------- 1 | from .edalize_flow_common import flow_fixture 2 | 3 | 4 | def test_lint(flow_fixture): 5 | flow_options = {"tool": "verilator"} 6 | ff = flow_fixture("lint", flow_options=flow_options) 7 | 8 | ff.flow.configure() 9 | ff.compare_config_files( 10 | [ 11 | "design.vc", 12 | "Makefile", 13 | ] 14 | ) 15 | -------------------------------------------------------------------------------- /tests/test_flow_sim.py: -------------------------------------------------------------------------------- 1 | import pytest 2 | from .edalize_flow_common import flow_fixture 3 | 4 | 5 | def test_sim_no_tool(flow_fixture): 6 | flow_options = {} 7 | with pytest.raises(RuntimeError) as e: 8 | ff = flow_fixture("sim", flow_options=flow_options) 9 | assert "Flow 'sim' requires flow option 'tool' to be set" in str(e.value) 10 | 11 | 12 | def test_sim(flow_fixture): 13 | flow_options = {"tool": "icarus"} 14 | ff = flow_fixture("sim", flow_options=flow_options) 15 | 16 | ff.flow.configure() 17 | ff.compare_config_files( 18 | [ 19 | "design.scr", 20 | "Makefile", 21 | ] 22 | ) 23 | 24 | 25 | def test_sim_cocotb(flow_fixture): 26 | flow_options = {"tool": "verilator", "cocotb_module": "some_cocotb_module"} 27 | ff = flow_fixture("sim", flow_options=flow_options, ref_subdir="with_cocotb") 28 | 29 | ff.flow.configure() 30 | ff.compare_config_files( 31 | [ 32 | "design.vc", 33 | "Makefile", 34 | ] 35 | ) 36 | -------------------------------------------------------------------------------- /tests/test_gatemate/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | P_R := $(shell which p_r) 4 | 5 | 6 | all: test_gatemate_0_00.cfg.bit 7 | 8 | test_gatemate_0_synth.v: edalize_yosys_template.tcl 9 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 10 | 11 | test_gatemate_0_00.cfg.bit: test_gatemate_0_synth.v 12 | $(EDALIZE_LAUNCHER) $(P_R) -A 1 -i test_gatemate_0_synth.v -o test_gatemate_0 -lib ccag some p_r_synth_options > p_r.log 13 | -------------------------------------------------------------------------------- /tests/test_gatemate/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | read_verilog -sv {sv_file.sv} 3 | source {tcl_file.tcl} 4 | read_verilog {vlog_file.v} 5 | read_verilog {vlog_with_define.v} 6 | read_verilog {vlog05_file.v} 7 | read_verilog -sv {another_sv_file.sv} 8 | } 9 | 10 | proc set_defines {} { 11 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello} {CCGM 1}} 12 | 13 | foreach d ${defines} { 14 | set key [lindex $d 0] 15 | set val [lindex $d 1] 16 | verilog_defines "-D$key=$val" 17 | }} 18 | 19 | proc set_incdirs {} { 20 | verilog_defaults -add -I.} 21 | 22 | proc set_params {} { 23 | chparam -set vlogparam_bool 1 top_module 24 | chparam -set vlogparam_int 42 top_module 25 | chparam -set vlogparam_str {"hello"} top_module} 26 | 27 | proc synth {top} { 28 | synth_gatemate some yosys_synth_options -top $top 29 | } 30 | 31 | set top top_module 32 | set name test_gatemate_0 33 | -------------------------------------------------------------------------------- /tests/test_gatemate/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | write_verilog test_gatemate_0_synth.v 17 | -------------------------------------------------------------------------------- /tests/test_gatemate/minimal/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | P_R := $(shell which p_r) 4 | 5 | 6 | all: test_gatemate_0_00.cfg.bit 7 | 8 | test_gatemate_0_synth.v: edalize_yosys_template.tcl 9 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 10 | 11 | test_gatemate_0_00.cfg.bit: test_gatemate_0_synth.v 12 | $(EDALIZE_LAUNCHER) $(P_R) -A 1 -i test_gatemate_0_synth.v -o test_gatemate_0 -lib ccag > p_r.log 13 | -------------------------------------------------------------------------------- /tests/test_gatemate/minimal/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | 3 | } 4 | 5 | proc set_defines {} { 6 | set defines {{CCGM 1}} 7 | 8 | foreach d ${defines} { 9 | set key [lindex $d 0] 10 | set val [lindex $d 1] 11 | verilog_defines "-D$key=$val" 12 | }} 13 | 14 | proc set_incdirs {} { 15 | } 16 | 17 | proc set_params {} { 18 | } 19 | 20 | proc synth {top} { 21 | synth_gatemate -top $top 22 | } 23 | 24 | set top top_module 25 | set name test_gatemate_0 26 | -------------------------------------------------------------------------------- /tests/test_gatemate/minimal/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | write_verilog test_gatemate_0_synth.v 17 | -------------------------------------------------------------------------------- /tests/test_gatemate/minimal/p_r.cmd: -------------------------------------------------------------------------------- 1 | -A 1 -i test_gatemate_0_synth.v -o test_gatemate_0 -lib ccag 2 | -------------------------------------------------------------------------------- /tests/test_gatemate/minimal/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_gatemate/p_r.cmd: -------------------------------------------------------------------------------- 1 | -A 1 -i test_gatemate_0_synth.v -o test_gatemate_0 -lib ccag some p_r_synth_options 2 | -------------------------------------------------------------------------------- /tests/test_gatemate/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_ghdl/test01/analyze.cmd: -------------------------------------------------------------------------------- 1 | -i --std=08 some analyze_options -P./libx vhdl_file.vhd vhdl2008_file 2 | -i --std=08 some analyze_options -P./libx --work=libx --workdir=./libx vhdl_lfile 3 | -------------------------------------------------------------------------------- /tests/test_ghdl/test01/elab-run.cmd: -------------------------------------------------------------------------------- 1 | -m --std=08 some analyze_options -P./libx top_module 2 | -r --std=08 some analyze_options -P./libx top_module a few run_options -ggeneric_bool=true -ggeneric_int=42 -ggeneric_str=hello 3 | -------------------------------------------------------------------------------- /tests/test_ghdl/test02/analyze.cmd: -------------------------------------------------------------------------------- 1 | -i --std=93c some analyze_options -P./libx vhdl_file.vhd 2 | -i --std=93c some analyze_options -P./libx --work=libx --workdir=./libx vhdl_lfile 3 | -------------------------------------------------------------------------------- /tests/test_ghdl/test02/elab-run.cmd: -------------------------------------------------------------------------------- 1 | -m --std=93c some analyze_options -P./libx top_module 2 | -r --std=93c some analyze_options -P./libx top_module a few run_options -ggeneric_bool=true -ggeneric_int=42 -ggeneric_str=hello 3 | -------------------------------------------------------------------------------- /tests/test_ghdl/test03/analyze.cmd: -------------------------------------------------------------------------------- 1 | -i --std=08 --ieee=synopsys -P./libx vhdl_file.vhd 2 | -i --std=08 --ieee=synopsys -P./libx --work=libx --workdir=./libx vhdl_lfile 3 | -------------------------------------------------------------------------------- /tests/test_ghdl/test03/elab-run.cmd: -------------------------------------------------------------------------------- 1 | -m --std=08 --ieee=synopsys -P./libx top_module 2 | -r --std=08 --ieee=synopsys -P./libx top_module a few run_options -ggeneric_bool=true -ggeneric_int=42 -ggeneric_str=hello 3 | -------------------------------------------------------------------------------- /tests/test_ghdl/test04/analyze.cmd: -------------------------------------------------------------------------------- 1 | -i --std=08 some analyze_options -P./libx --work=libx --workdir=./libx vhdl_lfile 2 | -i --std=08 some analyze_options -P./libx vhdl_file.vhd vhdl2008_file 3 | -------------------------------------------------------------------------------- /tests/test_ghdl/test04/elab-run.cmd: -------------------------------------------------------------------------------- 1 | -m --std=08 some analyze_options -P./libx --work=libx --workdir=./libx vhdl_lfile 2 | -r --std=08 some analyze_options -P./libx --work=libx --workdir=./libx vhdl_lfile a few run_options -ggeneric_bool=true -ggeneric_int=42 -ggeneric_str=hello 3 | -------------------------------------------------------------------------------- /tests/test_icarus/iverilog-vpi.cmd: -------------------------------------------------------------------------------- 1 | --name=vpi1 -lsome_lib -Isrc/vpi_1/ src/vpi_1/f1 src/vpi_1/f3 2 | --name=vpi2 src/vpi_2/f4 3 | -------------------------------------------------------------------------------- /tests/test_icarus/iverilog.cmd: -------------------------------------------------------------------------------- 1 | -stop_module -c test_icarus_0.scr -o test_icarus_0 some iverilog_options 2 | -------------------------------------------------------------------------------- /tests/test_icarus/minimal/Makefile: -------------------------------------------------------------------------------- 1 | TARGET := test_icarus_minimal_0 2 | TOPLEVEL := -stop 3 | IVERILOG_OPTIONS := 4 | VVP_OPTIONS := 5 | 6 | all: $(VPI_MODULES) $(TARGET) 7 | 8 | $(TARGET): 9 | iverilog $(TOPLEVEL) -c $(TARGET).scr -o $@ $(IVERILOG_OPTIONS) 10 | 11 | run: $(VPI_MODULES) $(TARGET) 12 | vvp -n -M. -l icarus.log $(patsubst %.vpi,-m%,$(VPI_MODULES)) $(VVP_OPTIONS) $(TARGET) -fst $(EXTRA_OPTIONS) 13 | 14 | clean: 15 | $(RM) $(VPI_MODULES) $(TARGET) 16 | -------------------------------------------------------------------------------- /tests/test_icarus/minimal/iverilog.cmd: -------------------------------------------------------------------------------- 1 | -stop -c test_icarus_minimal_0.scr -o test_icarus_minimal_0 2 | -------------------------------------------------------------------------------- /tests/test_icarus/minimal/test_icarus_minimal_0.scr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/edalize/1eedb7f726d1899465da30363763ea8c93d074af/tests/test_icarus/minimal/test_icarus_minimal_0.scr -------------------------------------------------------------------------------- /tests/test_icarus/minimal/vvp.cmd: -------------------------------------------------------------------------------- 1 | -M. -l icarus.log test_icarus_minimal_0 -fst -------------------------------------------------------------------------------- /tests/test_icarus/test_icarus_0.scr: -------------------------------------------------------------------------------- 1 | +define+vlogdefine_bool=1 2 | +define+vlogdefine_int=42 3 | +define+vlogdefine_str=hello 4 | +parameter+top_module.vlogparam_bool=1 5 | +parameter+top_module.vlogparam_int=42 6 | +parameter+top_module.vlogparam_str="hello" 7 | +incdir+. 8 | timescale.v 9 | sv_file.sv 10 | vlog_file.v 11 | vlog_with_define.v 12 | vlog05_file.v 13 | another_sv_file.sv 14 | -------------------------------------------------------------------------------- /tests/test_icarus/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | -------------------------------------------------------------------------------- /tests/test_icarus/vvp.cmd: -------------------------------------------------------------------------------- 1 | -M. -l icarus.log -mvpi1 -mvpi2 test_icarus_0 -fst +plusarg_bool=1 +plusarg_int=42 +plusarg_str=hello -------------------------------------------------------------------------------- /tests/test_icestorm/arachne-pnr.cmd: -------------------------------------------------------------------------------- 1 | a few arachne_pnr_options -q -p pcf_file.pcf test_icestorm_0.blif -o test_icestorm_0_arachne.asc 2 | -------------------------------------------------------------------------------- /tests/test_icestorm/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_ice40 some yosys_synth_options -top $top 32 | } 33 | 34 | set top top_module 35 | set name test_icestorm_0 36 | -------------------------------------------------------------------------------- /tests/test_icestorm/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_json $name.json 19 | -------------------------------------------------------------------------------- /tests/test_icestorm/icepack.cmd: -------------------------------------------------------------------------------- 1 | test_icestorm_0.asc test_icestorm_0.bin 2 | -------------------------------------------------------------------------------- /tests/test_icestorm/minimal/arachne-pnr.cmd: -------------------------------------------------------------------------------- 1 | -q -p pcf_file.pcf test_icestorm_0.blif -o test_icestorm_0_arachne.asc 2 | -------------------------------------------------------------------------------- /tests/test_icestorm/minimal/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | 6 | } 7 | 8 | proc set_defines {} { 9 | set defines {} 10 | 11 | foreach d ${defines} { 12 | set key [lindex $d 0] 13 | set val [lindex $d 1] 14 | verilog_defines "-D$key=$val" 15 | }} 16 | 17 | proc set_incdirs {} { 18 | } 19 | 20 | proc set_params {} { 21 | } 22 | 23 | proc synth {top} { 24 | synth_ice40 some yosys_synth_options -top $top 25 | } 26 | 27 | set top top_module 28 | set name test_icestorm_0 29 | -------------------------------------------------------------------------------- /tests/test_icestorm/minimal/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_json $name.json 19 | -------------------------------------------------------------------------------- /tests/test_icestorm/minimal/icepack.cmd: -------------------------------------------------------------------------------- 1 | test_icestorm_0.asc test_icestorm_0.bin 2 | -------------------------------------------------------------------------------- /tests/test_icestorm/minimal/nextpnr-ice40.cmd: -------------------------------------------------------------------------------- 1 | -l next.log --pcf pcf_file.pcf --json test_icestorm_0.json --asc test_icestorm_0.asc 2 | -------------------------------------------------------------------------------- /tests/test_icestorm/minimal/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_icestorm/nextpnr-ice40.cmd: -------------------------------------------------------------------------------- 1 | -l next.log --pcf pcf_file.pcf --json test_icestorm_0.json --asc test_icestorm_0.asc 2 | -------------------------------------------------------------------------------- /tests/test_icestorm/nextpnr/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_ice40 some yosys_synth_options some yosys_synth_options -top $top 32 | } 33 | 34 | set top top_module 35 | set name test_icestorm_0 36 | -------------------------------------------------------------------------------- /tests/test_icestorm/nextpnr/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_json $name.json 19 | -------------------------------------------------------------------------------- /tests/test_icestorm/nextpnr/icepack.cmd: -------------------------------------------------------------------------------- 1 | several icepack_options test_icestorm_0.asc test_icestorm_0.bin 2 | -------------------------------------------------------------------------------- /tests/test_icestorm/nextpnr/nextpnr-ice40.cmd: -------------------------------------------------------------------------------- 1 | -l next.log multiple nextpnr_options --pcf pcf_file.pcf --json test_icestorm_0.json --asc test_icestorm_0.asc 2 | -------------------------------------------------------------------------------- /tests/test_icestorm/nextpnr/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_icestorm/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_ise/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | include config.mk 3 | 4 | all: $(TOPLEVEL).bit 5 | 6 | $(TOPLEVEL).bit: $(NAME)_run.tcl $(NAME).xise 7 | $(EDALIZE_LAUNCHER) xtclsh $^ 8 | 9 | $(NAME).xise: $(NAME).tcl 10 | $(EDALIZE_LAUNCHER) xtclsh $< 11 | -------------------------------------------------------------------------------- /tests/test_ise/config.mk: -------------------------------------------------------------------------------- 1 | NAME := test_ise_0 2 | TOPLEVEL := top_module 3 | -------------------------------------------------------------------------------- /tests/test_ise/test_ise_0_run.tcl: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | project open $::argv 3 | process run "Generate Programming File" 4 | -------------------------------------------------------------------------------- /tests/test_ise/xtclsh.cmd: -------------------------------------------------------------------------------- 1 | test_ise_0.tcl 2 | test_ise_0_run.tcl test_ise_0.xise 3 | -------------------------------------------------------------------------------- /tests/test_isim.py: -------------------------------------------------------------------------------- 1 | from .edalize_common import make_edalize_test 2 | 3 | 4 | def test_isim(make_edalize_test): 5 | tool_options = { 6 | "fuse_options": ["some", "fuse_options"], 7 | "isim_options": ["a", "few", "isim_options"], 8 | } 9 | tf = make_edalize_test("isim", tool_options=tool_options) 10 | 11 | tf.backend.configure() 12 | 13 | tf.compare_files( 14 | ["config.mk", "Makefile", "run_test_isim_0.tcl", "test_isim_0.prj"] 15 | ) 16 | 17 | tf.copy_to_work_root("test_isim_0") 18 | 19 | tf.backend.run() 20 | 21 | tf.compare_files(["run.cmd"]) 22 | -------------------------------------------------------------------------------- /tests/test_isim/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | include config.mk 3 | 4 | all: $(TARGET) 5 | 6 | $(TARGET): 7 | fuse $(TOPLEVEL) -prj $(TARGET).prj -o $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(VLOG_PARAMS) $(FUSE_OPTIONS) 8 | 9 | run: $(TARGET) 10 | ./$(TARGET) -tclbatch run_$(TARGET).tcl $(ISIM_OPTIONS) $(EXTRA_OPTIONS) 11 | 12 | run-gui: $(TARGET) 13 | ./$(TARGET) -gui $(ISIM_OPTIONS) $(EXTRA_OPTIONS) 14 | -------------------------------------------------------------------------------- /tests/test_isim/config.mk: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | TARGET = test_isim_0 3 | TOPLEVEL = top_module 4 | 5 | VLOG_DEFINES = --define vlogdefine_bool=1 --define vlogdefine_int=42 --define vlogdefine_str=hello 6 | VLOG_INCLUDES = -i . 7 | VLOG_PARAMS = --generic_top vlogparam_bool=1 --generic_top vlogparam_int=42 --generic_top vlogparam_str=hello 8 | 9 | FUSE_OPTIONS = some fuse_options 10 | ISIM_OPTIONS = a few isim_options 11 | 12 | EXTRA_OPTIONS ?= -testplusarg plusarg_bool=1 -testplusarg plusarg_int=42 -testplusarg plusarg_str=hello 13 | -------------------------------------------------------------------------------- /tests/test_isim/run.cmd: -------------------------------------------------------------------------------- 1 | -tclbatch run_test_isim_0.tcl a few isim_options -testplusarg plusarg_bool=1 -testplusarg plusarg_int=42 -testplusarg plusarg_str=hello 2 | -------------------------------------------------------------------------------- /tests/test_isim/run_test_isim_0.tcl: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | wave log -r / 3 | run all 4 | quit 5 | -------------------------------------------------------------------------------- /tests/test_isim/test_isim_0: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | echo "$@" > run.cmd 3 | -------------------------------------------------------------------------------- /tests/test_isim/test_isim_0.prj: -------------------------------------------------------------------------------- 1 | sv work sv_file.sv 2 | verilog work vlog_file.v 3 | verilog work vlog_with_define.v 4 | sv work vlog05_file.v 5 | vhdl work vhdl_file.vhd 6 | vhdl work libx vhdl_lfile 7 | vhdl work vhdl2008_file 8 | sv work another_sv_file.sv 9 | -------------------------------------------------------------------------------- /tests/test_libero/libero-test-all-run.tcl: -------------------------------------------------------------------------------- 1 | # This file is generated by Edalize. 2 | # Microsemi Tcl Script 3 | # Libero 4 | 5 | source {libero-test-all-project.tcl} 6 | 7 | run_tool -name {SYNTHESIZE} 8 | run_tool -name {PLACEROUTE} 9 | run_tool -name {GENERATEPROGRAMMINGDATA} 10 | 11 | puts "To program the FPGA and SPI-Flash, run the 'Run PROGRAM Action' and 'Run PROGRAM_SPI_IMAGE Action' tools in the Design Flow menu." 12 | puts "If required, adjust the memory allocation and initialization before generating the bitstream and programming." 13 | puts "----------------- Finished building project -----------------------------" 14 | -------------------------------------------------------------------------------- /tests/test_libero/libero-test-all-syn-user.tcl: -------------------------------------------------------------------------------- 1 | # This file is generated by Edalize. 2 | # Synplify Tcl Script 3 | # Libero 4 | 5 | set_option -hdl_param -set vlogparam_bool=True 6 | set_option -hdl_param -set vlogparam_int=42 7 | set_option -hdl_param -set vlogparam_str=hello 8 | set_option -hdl_define -set vlogdefine_bool=True 9 | set_option -hdl_define -set vlogdefine_int=42 10 | set_option -hdl_define -set vlogdefine_str=hello 11 | 12 | set_option -include_path {../../.} 13 | -------------------------------------------------------------------------------- /tests/test_libero/libero-test-run.tcl: -------------------------------------------------------------------------------- 1 | # This file is generated by Edalize. 2 | # Microsemi Tcl Script 3 | # Libero 4 | 5 | source {libero-test-project.tcl} 6 | 7 | run_tool -name {SYNTHESIZE} 8 | run_tool -name {PLACEROUTE} 9 | run_tool -name {GENERATEPROGRAMMINGDATA} 10 | 11 | puts "To program the FPGA and SPI-Flash, run the 'Run PROGRAM Action' and 'Run PROGRAM_SPI_IMAGE Action' tools in the Design Flow menu." 12 | puts "If required, adjust the memory allocation and initialization before generating the bitstream and programming." 13 | puts "----------------- Finished building project -----------------------------" 14 | -------------------------------------------------------------------------------- /tests/test_libero/libero-test-syn-user.tcl: -------------------------------------------------------------------------------- 1 | # This file is generated by Edalize. 2 | # Synplify Tcl Script 3 | # Libero 4 | 5 | set_option -hdl_param -set vlogparam_bool=True 6 | set_option -hdl_param -set vlogparam_int=42 7 | set_option -hdl_param -set vlogparam_str=hello 8 | set_option -hdl_define -set vlogdefine_bool=True 9 | set_option -hdl_define -set vlogdefine_int=42 10 | set_option -hdl_define -set vlogdefine_str=hello 11 | 12 | set_option -include_path {../../.} 13 | -------------------------------------------------------------------------------- /tests/test_mistral/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: test_mistral_0.rbf 4 | 5 | test_mistral_0.json: edalize_yosys_template.tcl 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | 8 | test_mistral_0.rbf: test_mistral_0.json 9 | $(EDALIZE_LAUNCHER) nextpnr-mistral -l next.log --device 5CSEBA6U23I7 a few nextpnr_options --qsf qsf_constraint_file.qsf --json test_mistral_0.json --rbf test_mistral_0.rbf 10 | 11 | build-gui: test_mistral_0.json 12 | $(EDALIZE_LAUNCHER) nextpnr-mistral -l next.log --device 5CSEBA6U23I7 a few nextpnr_options --qsf qsf_constraint_file.qsf --json test_mistral_0.json --rbf test_mistral_0.rbf --gui 13 | -------------------------------------------------------------------------------- /tests/test_mistral/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | read_verilog -sv {sv_file.sv} 3 | source {tcl_file.tcl} 4 | read_verilog {vlog_file.v} 5 | read_verilog {vlog_with_define.v} 6 | read_verilog {vlog05_file.v} 7 | read_verilog -sv {another_sv_file.sv} 8 | } 9 | 10 | proc set_defines {} { 11 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 12 | 13 | foreach d ${defines} { 14 | set key [lindex $d 0] 15 | set val [lindex $d 1] 16 | verilog_defines "-D$key=$val" 17 | }} 18 | 19 | proc set_incdirs {} { 20 | verilog_defaults -add -I.} 21 | 22 | proc set_params {} { 23 | chparam -set vlogparam_bool 1 top_module 24 | chparam -set vlogparam_int 42 top_module 25 | chparam -set vlogparam_str {"hello"} top_module} 26 | 27 | proc synth {top} { 28 | synth_intel_alm some yosys_synth_options -top $top 29 | } 30 | 31 | set top top_module 32 | set name test_mistral_0 33 | -------------------------------------------------------------------------------- /tests/test_mistral/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | write_json test_mistral_0.json 17 | -------------------------------------------------------------------------------- /tests/test_mistral/minimal/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: test_mistral_0.rbf 4 | 5 | test_mistral_0.json: edalize_yosys_template.tcl 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | 8 | test_mistral_0.rbf: test_mistral_0.json 9 | $(EDALIZE_LAUNCHER) nextpnr-mistral -l next.log --device 5CSEBA6U23I7 --json test_mistral_0.json --rbf test_mistral_0.rbf 10 | 11 | build-gui: test_mistral_0.json 12 | $(EDALIZE_LAUNCHER) nextpnr-mistral -l next.log --device 5CSEBA6U23I7 --json test_mistral_0.json --rbf test_mistral_0.rbf --gui 13 | -------------------------------------------------------------------------------- /tests/test_mistral/minimal/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | 3 | } 4 | 5 | proc set_defines {} { 6 | set defines {} 7 | 8 | foreach d ${defines} { 9 | set key [lindex $d 0] 10 | set val [lindex $d 1] 11 | verilog_defines "-D$key=$val" 12 | }} 13 | 14 | proc set_incdirs {} { 15 | } 16 | 17 | proc set_params {} { 18 | } 19 | 20 | proc synth {top} { 21 | synth_intel_alm -top $top 22 | } 23 | 24 | set top top_module 25 | set name test_mistral_0 26 | -------------------------------------------------------------------------------- /tests/test_mistral/minimal/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | write_json test_mistral_0.json 17 | -------------------------------------------------------------------------------- /tests/test_mistral/minimal/nextpnr-mistral.cmd: -------------------------------------------------------------------------------- 1 | -l next.log --device 5CSEBA6U23I7 --json test_mistral_0.json --rbf test_mistral_0.rbf 2 | -------------------------------------------------------------------------------- /tests/test_mistral/minimal/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_mistral/nextpnr-mistral.cmd: -------------------------------------------------------------------------------- 1 | -l next.log --device 5CSEBA6U23I7 a few nextpnr_options --qsf qsf_constraint_file.qsf --json test_mistral_0.json --rbf test_mistral_0.rbf 2 | -------------------------------------------------------------------------------- /tests/test_mistral/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_modelsim/common_compilation/edalize_build_rtl.tcl: -------------------------------------------------------------------------------- 1 | vlib work 2 | vcom various vcom_options -quiet -work work vhdl_file.vhd 3 | vlib libx 4 | vcom various vcom_options -quiet -work libx vhdl_lfile 5 | vcom -2008 various vcom_options -quiet -work work vhdl2008_file 6 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello -sv +incdir+. -quiet -work work -mfcu sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v another_sv_file.sv -------------------------------------------------------------------------------- /tests/test_modelsim/common_compilation/edalize_main.tcl: -------------------------------------------------------------------------------- 1 | onerror { quit -code 1; } 2 | do edalize_build_rtl.tcl 3 | do tcl_file.tcl 4 | -------------------------------------------------------------------------------- /tests/test_modelsim/common_compilation/vsim.cmd: -------------------------------------------------------------------------------- 1 | -c -do do edalize_main.tcl; exit 2 | -------------------------------------------------------------------------------- /tests/test_modelsim/common_compilation/vsim2.cmd: -------------------------------------------------------------------------------- 1 | -c a few vsim_options -gvlogparam_bool=1 -gvlogparam_int=42 -gvlogparam_str=hello +plusarg_bool=1 +plusarg_int=42 +plusarg_str=hello -do run -all; quit -code [expr [coverage attribute -name TESTSTATUS -concise] >= 2 ? [coverage attribute -name TESTSTATUS -concise] : 0]; exit top_module 2 | -------------------------------------------------------------------------------- /tests/test_modelsim/edalize_build_rtl.tcl: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello -sv +incdir+. -quiet -work work sv_file.sv 3 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. -quiet -work work vlog_file.v 4 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. -quiet -work work vlog_with_define.v 5 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. -quiet -work work vlog05_file.v 6 | vcom various vcom_options -quiet -work work vhdl_file.vhd 7 | vlib libx 8 | vcom various vcom_options -quiet -work libx vhdl_lfile 9 | vcom -2008 various vcom_options -quiet -work work vhdl2008_file 10 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello -sv +incdir+. -quiet -work work another_sv_file.sv 11 | -------------------------------------------------------------------------------- /tests/test_modelsim/edalize_main.tcl: -------------------------------------------------------------------------------- 1 | onerror { quit -code 1; } 2 | do edalize_build_rtl.tcl 3 | do tcl_file.tcl 4 | -------------------------------------------------------------------------------- /tests/test_modelsim/vsim.cmd: -------------------------------------------------------------------------------- 1 | -c -do do edalize_main.tcl; exit 2 | -------------------------------------------------------------------------------- /tests/test_modelsim/vsim2.cmd: -------------------------------------------------------------------------------- 1 | -c a few vsim_options -gvlogparam_bool=1 -gvlogparam_int=42 -gvlogparam_str=hello +plusarg_bool=1 +plusarg_int=42 +plusarg_str=hello -do run -all; quit -code [expr [coverage attribute -name TESTSTATUS -concise] >= 2 ? [coverage attribute -name TESTSTATUS -concise] : 0]; exit top_module 2 | -------------------------------------------------------------------------------- /tests/test_morty.py: -------------------------------------------------------------------------------- 1 | from .edalize_common import make_edalize_test 2 | import os 3 | 4 | 5 | def test_morty(make_edalize_test): 6 | tool_options = {"morty_options": ["--prefix", "blub"]} 7 | paramtypes = ["vlogdefine"] 8 | 9 | tf = make_edalize_test("morty", tool_options=tool_options, param_types=paramtypes) 10 | 11 | tf.backend.build() 12 | tf.compare_files(["morty.cmd"]) 13 | -------------------------------------------------------------------------------- /tests/test_morty/morty.cmd: -------------------------------------------------------------------------------- 1 | -I . -D vlogdefine_bool=1 -D vlogdefine_int=42 -D vlogdefine_str=hello sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v another_sv_file.sv --prefix blub 2 | -------------------------------------------------------------------------------- /tests/test_openfpga.py: -------------------------------------------------------------------------------- 1 | import os 2 | from .edalize_common import make_edalize_test, tests_dir 3 | 4 | 5 | def test_openfpga(make_edalize_test): 6 | # Standard tool options 7 | tool_options = { 8 | "arch": "sofa-qlhd", 9 | "task_options": ["--debug"], 10 | } 11 | # Fake environment variables 12 | os.environ["OPENFPGA_PATH"] = "${{OPENFPGA_PATH}}" 13 | os.environ["SOFA_PATH"] = "${{SOFA_PATH}}" 14 | 15 | tf = make_edalize_test( 16 | tool_name="openfpga", 17 | test_name="test_openfpga_0", 18 | tool_options=tool_options, 19 | ) 20 | 21 | tf.backend.configure() 22 | 23 | tf.compare_files(["config/task.conf"]) 24 | -------------------------------------------------------------------------------- /tests/test_openlane.py: -------------------------------------------------------------------------------- 1 | from .edalize_common import make_edalize_test 2 | import os 3 | 4 | 5 | def test_openlane(make_edalize_test): 6 | tool_options = {} 7 | paramtypes = ["vlogdefine"] 8 | 9 | tf = make_edalize_test( 10 | "openlane", tool_options=tool_options, param_types=paramtypes 11 | ) 12 | 13 | tf.backend.configure() 14 | tf.backend.build() 15 | tf.compare_files(["config.tcl", "Makefile", "flow.tcl.cmd"]) 16 | -------------------------------------------------------------------------------- /tests/test_openlane/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: config.tcl 4 | $(EDALIZE_LAUNCHER) flow.tcl -tag top_module -save -save_path . -design . 5 | 6 | clean: 7 | rm -rf runs 8 | -------------------------------------------------------------------------------- /tests/test_openlane/config.tcl: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | set ::env(DESIGN_NAME) top_module 4 | 5 | set ::env(VERILOG_FILES) [list sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v another_sv_file.sv] 6 | set ::env(SYNTH_DEFINES) [list vlogdefine_bool=1 vlogdefine_int=42 vlogdefine_str=hello] 7 | 8 | source tcl_file.tcl 9 | -------------------------------------------------------------------------------- /tests/test_openlane/flow.tcl.cmd: -------------------------------------------------------------------------------- 1 | -tag top_module -save -save_path . -design . 2 | -------------------------------------------------------------------------------- /tests/test_oxide/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: test_oxide_0.bit 4 | 5 | test_oxide_0.json: edalize_yosys_template.tcl 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | 8 | test_oxide_0.fasm: test_oxide_0.json 9 | $(EDALIZE_LAUNCHER) nextpnr-nexus -l next.log --device LIFCL-40-9BG400CES a few nextpnr_options --pdc pdc_constraint_file.pdc --json test_oxide_0.json --fasm test_oxide_0.fasm 10 | 11 | build-gui: test_oxide_0.json 12 | $(EDALIZE_LAUNCHER) nextpnr-nexus -l next.log --device LIFCL-40-9BG400CES a few nextpnr_options --pdc pdc_constraint_file.pdc --json test_oxide_0.json --fasm test_oxide_0.fasm --gui 13 | 14 | test_oxide_0.bit: test_oxide_0.fasm 15 | $(EDALIZE_LAUNCHER) prjoxide pack test_oxide_0.fasm test_oxide_0.bit 16 | -------------------------------------------------------------------------------- /tests/test_oxide/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | read_verilog -sv {sv_file.sv} 3 | source {tcl_file.tcl} 4 | read_verilog {vlog_file.v} 5 | read_verilog {vlog_with_define.v} 6 | read_verilog {vlog05_file.v} 7 | read_verilog -sv {another_sv_file.sv} 8 | } 9 | 10 | proc set_defines {} { 11 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 12 | 13 | foreach d ${defines} { 14 | set key [lindex $d 0] 15 | set val [lindex $d 1] 16 | verilog_defines "-D$key=$val" 17 | }} 18 | 19 | proc set_incdirs {} { 20 | verilog_defaults -add -I.} 21 | 22 | proc set_params {} { 23 | chparam -set vlogparam_bool 1 top_module 24 | chparam -set vlogparam_int 42 top_module 25 | chparam -set vlogparam_str {"hello"} top_module} 26 | 27 | proc synth {top} { 28 | synth_nexus some yosys_synth_options -top $top 29 | } 30 | 31 | set top top_module 32 | set name test_oxide_0 33 | -------------------------------------------------------------------------------- /tests/test_oxide/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | write_json test_oxide_0.json 17 | -------------------------------------------------------------------------------- /tests/test_oxide/minimal/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: test_oxide_0.bit 4 | 5 | test_oxide_0.json: edalize_yosys_template.tcl 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | 8 | test_oxide_0.fasm: test_oxide_0.json 9 | $(EDALIZE_LAUNCHER) nextpnr-nexus -l next.log --device LIFCL-40-9BG400CES --json test_oxide_0.json --fasm test_oxide_0.fasm 10 | 11 | build-gui: test_oxide_0.json 12 | $(EDALIZE_LAUNCHER) nextpnr-nexus -l next.log --device LIFCL-40-9BG400CES --json test_oxide_0.json --fasm test_oxide_0.fasm --gui 13 | 14 | test_oxide_0.bit: test_oxide_0.fasm 15 | $(EDALIZE_LAUNCHER) prjoxide pack test_oxide_0.fasm test_oxide_0.bit 16 | -------------------------------------------------------------------------------- /tests/test_oxide/minimal/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | 3 | } 4 | 5 | proc set_defines {} { 6 | set defines {} 7 | 8 | foreach d ${defines} { 9 | set key [lindex $d 0] 10 | set val [lindex $d 1] 11 | verilog_defines "-D$key=$val" 12 | }} 13 | 14 | proc set_incdirs {} { 15 | } 16 | 17 | proc set_params {} { 18 | } 19 | 20 | proc synth {top} { 21 | synth_nexus -top $top 22 | } 23 | 24 | set top top_module 25 | set name test_oxide_0 26 | -------------------------------------------------------------------------------- /tests/test_oxide/minimal/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | write_json test_oxide_0.json 17 | -------------------------------------------------------------------------------- /tests/test_oxide/minimal/nextpnr-nexus.cmd: -------------------------------------------------------------------------------- 1 | -l next.log --device LIFCL-40-9BG400CES --json test_oxide_0.json --fasm test_oxide_0.fasm 2 | -------------------------------------------------------------------------------- /tests/test_oxide/minimal/prjoxide.cmd: -------------------------------------------------------------------------------- 1 | pack test_oxide_0.fasm test_oxide_0.bit 2 | -------------------------------------------------------------------------------- /tests/test_oxide/minimal/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_oxide/nextpnr-nexus.cmd: -------------------------------------------------------------------------------- 1 | -l next.log --device LIFCL-40-9BG400CES a few nextpnr_options --pdc pdc_constraint_file.pdc --json test_oxide_0.json --fasm test_oxide_0.fasm 2 | -------------------------------------------------------------------------------- /tests/test_oxide/prjoxide.cmd: -------------------------------------------------------------------------------- 1 | pack test_oxide_0.fasm test_oxide_0.bit 2 | -------------------------------------------------------------------------------- /tests/test_oxide/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_plugin/edalize/flows/customexternalflow.py: -------------------------------------------------------------------------------- 1 | from edalize.flows.edaflow import Edaflow 2 | 3 | 4 | class Customexternalflow(Edaflow): 5 | 6 | argtypes = ["plusarg", "vlogdefine", "vlogparam"] 7 | 8 | FLOW_OPTIONS = {} 9 | 10 | def configure(self): 11 | print("Configuring custom flow") 12 | 13 | def build(self): 14 | print("Building with custom flow") 15 | 16 | def run(self, args): 17 | print("Running custom flow") 18 | -------------------------------------------------------------------------------- /tests/test_quartus/Pro/Makefile: -------------------------------------------------------------------------------- 1 | # Auto generated by Edalize 2 | NAME := test_quartus_0 3 | OPTIONS := some quartus_options 4 | DSE_OPTIONS := some dse_options 5 | 6 | all: sta 7 | 8 | project: $(NAME).tcl 9 | $(EDALIZE_LAUNCHER) quartus_sh $(OPTIONS) -t $(NAME).tcl 10 | 11 | qsys: project 12 | qsys-generate qsys_file --synthesis=VERILOG --family="Cyclone V" --part=5CSXFC6D6F31C8ES --quartus-project=$(NAME) 13 | 14 | syn: qsys 15 | $(EDALIZE_LAUNCHER) quartus_syn $(OPTIONS) $(NAME) 16 | 17 | fit: syn 18 | $(EDALIZE_LAUNCHER) quartus_fit $(OPTIONS) $(NAME) 19 | 20 | asm: fit 21 | $(EDALIZE_LAUNCHER) quartus_asm $(OPTIONS) $(NAME) 22 | 23 | sta: asm 24 | $(EDALIZE_LAUNCHER) quartus_sta $(OPTIONS) $(NAME) 25 | 26 | dse: syn 27 | $(EDALIZE_LAUNCHER) quartus_dse $(NAME) $(DSE_OPTIONS) 28 | 29 | clean: 30 | $(EDALIZE_LAUNCHER) rm -rf *.* qdb tmp-clearbox 31 | 32 | .PHONY: all project qsys syn fit asm sta dse clean 33 | -------------------------------------------------------------------------------- /tests/test_quartus/Pro/qsys-generate.cmd: -------------------------------------------------------------------------------- 1 | qsys_file --synthesis=VERILOG --family=Cyclone V --part=5CSXFC6D6F31C8ES --quartus-project=test_quartus_0 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Pro/quartus_asm.cmd: -------------------------------------------------------------------------------- 1 | some quartus_options test_quartus_0 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Pro/quartus_dse.cmd: -------------------------------------------------------------------------------- 1 | test_quartus_0 some dse_options 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Pro/quartus_fit.cmd: -------------------------------------------------------------------------------- 1 | some quartus_options test_quartus_0 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Pro/quartus_sh.cmd: -------------------------------------------------------------------------------- 1 | some quartus_options -t test_quartus_0.tcl 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Pro/quartus_sta.cmd: -------------------------------------------------------------------------------- 1 | some quartus_options test_quartus_0 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Pro/quartus_syn.cmd: -------------------------------------------------------------------------------- 1 | some quartus_options test_quartus_0 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Standard/ip-generate.cmd: -------------------------------------------------------------------------------- 1 | --project-directory=. --output-directory=qsys/qsys_file/synthesis --file-set=QUARTUS_SYNTH --report-file=sopcinfo:qsys/qsys_file/qsys_file.sopcinfo --report-file=html:qsys/qsys_file/qsys_file.html --report-file=qip:qsys/qsys_file/qsys_file.qip --report-file=cmp:qsys/qsys_file/qsys_file.cmp --report-file=svd --system-info=DEVICE_FAMILY=Cyclone V --system-info=DEVICE=5CSXFC6D6F31C8ES --component-file=./qsys_file.qsys --language=VERILOG 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Standard/quartus_asm.cmd: -------------------------------------------------------------------------------- 1 | some quartus_options test_quartus_0 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Standard/quartus_dse.cmd: -------------------------------------------------------------------------------- 1 | test_quartus_0 some dse_options 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Standard/quartus_fit.cmd: -------------------------------------------------------------------------------- 1 | some quartus_options test_quartus_0 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Standard/quartus_map.cmd: -------------------------------------------------------------------------------- 1 | some quartus_options test_quartus_0 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Standard/quartus_sh.cmd: -------------------------------------------------------------------------------- 1 | some quartus_options -t test_quartus_0.tcl 2 | -------------------------------------------------------------------------------- /tests/test_quartus/Standard/quartus_sta.cmd: -------------------------------------------------------------------------------- 1 | some quartus_options test_quartus_0 2 | -------------------------------------------------------------------------------- /tests/test_questaformal/Makefile: -------------------------------------------------------------------------------- 1 | #Generated by Edalize 2 | 3 | QVERIFY ?= qverify 4 | 5 | QVERIFY_OPTIONS ?= a few qverify_options 6 | 7 | all: work 8 | 9 | run: work 10 | $(QVERIFY) $(QVERIFY_OPTIONS) -do "do edalize_autocheck.tcl; exit" 11 | 12 | run-gui: work 13 | $(QVERIFY) -gui 14 | 15 | work: 16 | $(QVERIFY) -c -do "do edalize_main.tcl; exit" 17 | 18 | clean: 19 | -------------------------------------------------------------------------------- /tests/test_questaformal/edalize_build_rtl.tcl: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello -sv +incdir+. -quiet -work work sv_file.sv 3 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. -quiet -work work vlog_file.v 4 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. -quiet -work work vlog_with_define.v 5 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. -quiet -work work vlog05_file.v 6 | vcom various vcom_options -quiet -work work vhdl_file.vhd 7 | vlib libx 8 | vcom various vcom_options -quiet -work libx vhdl_lfile 9 | vcom -2008 various vcom_options -quiet -work work vhdl2008_file 10 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello -sv +incdir+. -quiet -work work another_sv_file.sv 11 | -------------------------------------------------------------------------------- /tests/test_questaformal/edalize_main.tcl: -------------------------------------------------------------------------------- 1 | onerror { quit -code 1; } 2 | do edalize_build_rtl.tcl 3 | do tcl_file.tcl 4 | -------------------------------------------------------------------------------- /tests/test_questaformal/qverify.cmd: -------------------------------------------------------------------------------- 1 | -c -do do edalize_main.tcl; exit 2 | -------------------------------------------------------------------------------- /tests/test_questaformal/qverify2.cmd: -------------------------------------------------------------------------------- 1 | a few qverify_options -do do edalize_autocheck.tcl; exit 2 | -------------------------------------------------------------------------------- /tests/test_radiant/minimal/radiantc.cmd: -------------------------------------------------------------------------------- 1 | test_radiant_minimal_0.tcl 2 | test_radiant_minimal_0_run.tcl 3 | -------------------------------------------------------------------------------- /tests/test_radiant/minimal/test_radiant_minimal_0.tcl: -------------------------------------------------------------------------------- 1 | #Generated by Edalize 2 | prj_create -name test_radiant_minimal_0 -impl "impl" -dev LIFCL-40-9BG400C 3 | prj_set_impl_opt top [] 4 | prj_save 5 | prj_close 6 | -------------------------------------------------------------------------------- /tests/test_radiant/minimal/test_radiant_minimal_0_run.tcl: -------------------------------------------------------------------------------- 1 | #Generated by Edalize 2 | prj_open test_radiant_minimal_0.rdf 3 | prj_run Synthesis -impl impl -forceOne 4 | prj_run Map -impl impl 5 | prj_run PAR -impl impl 6 | prj_run Export -impl impl -task Bitgen 7 | prj_save 8 | prj_close 9 | -------------------------------------------------------------------------------- /tests/test_radiant/radiantc.cmd: -------------------------------------------------------------------------------- 1 | test_radiant_0.tcl 2 | test_radiant_0_run.tcl 3 | -------------------------------------------------------------------------------- /tests/test_radiant/test_radiant_0.tcl: -------------------------------------------------------------------------------- 1 | #Generated by Edalize 2 | prj_create -name test_radiant_0 -impl "impl" -dev LIFCL-40-9BG400C 3 | prj_set_impl_opt top top_module 4 | prj_set_impl_opt {include path} {.} 5 | prj_set_impl_opt HDL_PARAM {generic_bool=True;generic_int=42;generic_str=hello} 6 | prj_set_impl_opt HDL_PARAM {vlogparam_bool=1;vlogparam_int=42;vlogparam_str="hello"} 7 | prj_set_impl_opt VERILOG_DIRECTIVES {vlogdefine_bool=True;vlogdefine_int=42;vlogdefine_str=hello} 8 | prj_add_source sdc_file -work work 9 | prj_add_source sv_file.sv -work work 10 | source tcl_file.tcl 11 | prj_add_source vlog_file.v -work work 12 | prj_add_source vlog_with_define.v -work work 13 | prj_add_source vlog05_file.v -work work 14 | prj_add_source vhdl_file.vhd -work work 15 | prj_add_source vhdl_lfile -work libx 16 | prj_add_source vhdl2008_file -work work 17 | prj_add_source another_sv_file.sv -work work 18 | prj_add_source pdc_constraint_file.pdc -work work 19 | prj_save 20 | prj_close 21 | -------------------------------------------------------------------------------- /tests/test_radiant/test_radiant_0_run.tcl: -------------------------------------------------------------------------------- 1 | #Generated by Edalize 2 | prj_open test_radiant_0.rdf 3 | prj_run Synthesis -impl impl -forceOne 4 | prj_run Map -impl impl 5 | prj_run PAR -impl impl 6 | prj_run Export -impl impl -task Bitgen 7 | prj_save 8 | prj_close 9 | -------------------------------------------------------------------------------- /tests/test_reporting/data/linux-on-litex-vexriscv/de10nano/top.fit.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/edalize/1eedb7f726d1899465da30363763ea8c93d074af/tests/test_reporting/data/linux-on-litex-vexriscv/de10nano/top.fit.rpt -------------------------------------------------------------------------------- /tests/test_reporting/data/picorv32/README.md: -------------------------------------------------------------------------------- 1 | Reports from untested builds of the [PicoRV32 RISCV 2 | CPU](https://github.com/cliffordwolf/picorv32) for several tools and devices. 3 | 4 | A wrapper of some form is needed since this design uses far more pins than 5 | provided by these devices. The Quartus builds used `VIRTUAL_PIN` constraints 6 | from the [virtual_pins 7 | generator](https://github.com/fusesoc/fusesoc-generators). The Xilinx builds 8 | used the wrapped version of the core from the [SymbiFlow FPGA tool performance 9 | profiling project](https://github.com/SymbiFlow/fpga-tool-perf/). 10 | 11 | There are [reported problems with ISE synthesis and this 12 | design](https://github.com/cliffordwolf/picorv32/issues/38) so this run is 13 | potentially suspect, but produced the right report files. 14 | 15 | -------------------------------------------------------------------------------- /tests/test_reporting/data/picorv32/quartus-cyclone10/picorv32_wrap_0_1.fit.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/edalize/1eedb7f726d1899465da30363763ea8c93d074af/tests/test_reporting/data/picorv32/quartus-cyclone10/picorv32_wrap_0_1.fit.rpt -------------------------------------------------------------------------------- /tests/test_reporting/data/picorv32/quartus-cyclone4/picorv32_wrap_0_1.fit.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/edalize/1eedb7f726d1899465da30363763ea8c93d074af/tests/test_reporting/data/picorv32/quartus-cyclone4/picorv32_wrap_0_1.fit.rpt -------------------------------------------------------------------------------- /tests/test_rivierapro/edalize_build_rtl.tcl: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlog some vlog_options -sv +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. -quiet -work work sv_file.sv 3 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. -quiet -work work vlog_file.v 4 | vlog some vlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. -quiet -work work vlog_with_define.v 5 | vlog some vlog_options -v2k5 +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. -quiet -work work vlog05_file.v 6 | vcom -quiet -work work vhdl_file.vhd 7 | vlib libx 8 | vcom -quiet -work libx vhdl_lfile 9 | vcom -2008 -quiet -work work vhdl2008_file 10 | vlog some vlog_options -sv +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. -quiet -work work another_sv_file.sv 11 | -------------------------------------------------------------------------------- /tests/test_rivierapro/edalize_build_vpi.tcl: -------------------------------------------------------------------------------- 1 | ccomp -pli -o elf-loader_0.so -lelf -std=c99 ../../../cores/elf-loader/elf-loader.c ../../../cores/elf-loader/vpi_wrapper.c 2 | -------------------------------------------------------------------------------- /tests/test_rivierapro/edalize_launch.tcl: -------------------------------------------------------------------------------- 1 | vsim a few vsim_options top_module +plusarg_bool=1 +plusarg_int=42 +plusarg_str=hello -gvlogparam_bool=1 -gvlogparam_int=42 -gvlogparam_str=hello 2 | -------------------------------------------------------------------------------- /tests/test_rivierapro/edalize_main.tcl: -------------------------------------------------------------------------------- 1 | do edalize_build_rtl.tcl 2 | do tcl_file.tcl 3 | -------------------------------------------------------------------------------- /tests/test_rivierapro/edalize_run.tcl: -------------------------------------------------------------------------------- 1 | do edalize_launch.tcl 2 | run -all 3 | exit 4 | -------------------------------------------------------------------------------- /tests/test_rivierapro/vsim.cmd: -------------------------------------------------------------------------------- 1 | -c -do do edalize_main.tcl; exit 2 | -------------------------------------------------------------------------------- /tests/test_rivierapro/vsim2.cmd: -------------------------------------------------------------------------------- 1 | -c -quiet -do edalize_run.tcl 2 | -------------------------------------------------------------------------------- /tests/test_slang/lint/slang.cmd: -------------------------------------------------------------------------------- 1 | -D vlogdefine_bool=1 -D vlogdefine_int=42 -D vlogdefine_str=hello -G vlogparam_bool=1 -G vlogparam_int=42 -G vlogparam_str=hello -I . sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v another_sv_file.sv --lint-only --top top_module 2 | -------------------------------------------------------------------------------- /tests/test_slang/preprocess/slang.cmd: -------------------------------------------------------------------------------- 1 | -D vlogdefine_bool=1 -D vlogdefine_int=42 -D vlogdefine_str=hello -G vlogparam_bool=1 -G vlogparam_int=42 -G vlogparam_str=hello -I . sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v another_sv_file.sv --preprocess --top top_module 2 | -------------------------------------------------------------------------------- /tests/test_slang/slang_options/slang.cmd: -------------------------------------------------------------------------------- 1 | -D vlogdefine_bool=1 -D vlogdefine_int=42 -D vlogdefine_str=hello -G vlogparam_bool=1 -G vlogparam_int=42 -G vlogparam_str=hello -I . sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v another_sv_file.sv -v -d -c -e --top top_module 2 | -------------------------------------------------------------------------------- /tests/test_spyglass/defaults/Makefile: -------------------------------------------------------------------------------- 1 | NAME := test_spyglass_0 2 | 3 | run-goals: run-goal-design_read run-goal-lint_lint_rtl 4 | run-goal-design_read: 5 | sg_shell -enable_pass_exit_codes -tcl spyglass-run-design_read.tcl 6 | 7 | run-goal-lint_lint_rtl: 8 | sg_shell -enable_pass_exit_codes -tcl spyglass-run-lint_lint_rtl.tcl 9 | 10 | run-gui: 11 | spyglass -project $(NAME).prj 12 | -------------------------------------------------------------------------------- /tests/test_spyglass/defaults/spyglass-run-design_read.tcl: -------------------------------------------------------------------------------- 1 | open_project test_spyglass_0.prj 2 | 3 | current_goal Design_Read 4 | 5 | # Parameters which are not used/defined in a given goal/methodology raise 6 | # a WARNING, which fails the lint process. That's a bit over the top, we hence 7 | # disable this warning. 8 | waive -rule {checkCMD_unknown} 9 | 10 | set rc [run_goal] 11 | close_project -force 12 | 13 | set errorCode [lindex $rc 0] 14 | set errorMsg [lindex $rc 1] 15 | if { $errorCode } { 16 | puts stderr "SpyGlass run failed: $errorMsg ($errorCode)" 17 | } 18 | 19 | # requires sg_shell to be called with -enable_pass_exit_codes, otherwise 20 | # all non-fatal exit codes are mapped to 0 21 | exit $errorCode 22 | -------------------------------------------------------------------------------- /tests/test_spyglass/defaults/spyglass-run-lint_lint_rtl.tcl: -------------------------------------------------------------------------------- 1 | open_project test_spyglass_0.prj 2 | 3 | current_goal lint/lint_rtl 4 | 5 | # Parameters which are not used/defined in a given goal/methodology raise 6 | # a WARNING, which fails the lint process. That's a bit over the top, we hence 7 | # disable this warning. 8 | waive -rule {checkCMD_unknown} 9 | 10 | set rc [run_goal] 11 | close_project -force 12 | 13 | set errorCode [lindex $rc 0] 14 | set errorMsg [lindex $rc 1] 15 | if { $errorCode } { 16 | puts stderr "SpyGlass run failed: $errorMsg ($errorCode)" 17 | } 18 | 19 | # requires sg_shell to be called with -enable_pass_exit_codes, otherwise 20 | # all non-fatal exit codes are mapped to 0 21 | exit $errorCode 22 | -------------------------------------------------------------------------------- /tests/test_spyglass/defaults/spyglass-run-some_othergoal.tcl: -------------------------------------------------------------------------------- 1 | open_project test_spyglass_0.prj 2 | 3 | current_goal some/othergoal 4 | 5 | # Parameters which are not used/defined in a given goal/methodology raise 6 | # a WARNING, which fails the lint process. That's a bit over the top, we hence 7 | # disable this warning. 8 | waive -rule {checkCMD_unknown} 9 | 10 | set rc [run_goal] 11 | close_project -force 12 | 13 | set errorCode [lindex $rc 0] 14 | set errorMsg [lindex $rc 1] 15 | if { $errorCode } { 16 | puts stderr "SpyGlass run failed: $errorMsg ($errorCode)" 17 | } 18 | 19 | # requires sg_shell to be called with -enable_pass_exit_codes, otherwise 20 | # all non-fatal exit codes are mapped to 0 21 | exit $errorCode -------------------------------------------------------------------------------- /tests/test_spyglass/defaults/spyglass.cmd: -------------------------------------------------------------------------------- 1 | -enable_pass_exit_codes -tcl spyglass-run-design_read.tcl 2 | -enable_pass_exit_codes -tcl spyglass-run-lint_lint_rtl.tcl 3 | -------------------------------------------------------------------------------- /tests/test_spyglass/tooloptions/Makefile: -------------------------------------------------------------------------------- 1 | NAME := test_spyglass_0 2 | 3 | run-goals: run-goal-design_read run-goal-lint_lint_rtl run-goal-some_othergoal 4 | run-goal-design_read: 5 | sg_shell -enable_pass_exit_codes -tcl spyglass-run-design_read.tcl 6 | 7 | run-goal-lint_lint_rtl: 8 | sg_shell -enable_pass_exit_codes -tcl spyglass-run-lint_lint_rtl.tcl 9 | 10 | run-goal-some_othergoal: 11 | sg_shell -enable_pass_exit_codes -tcl spyglass-run-some_othergoal.tcl 12 | 13 | run-gui: 14 | spyglass -project $(NAME).prj 15 | -------------------------------------------------------------------------------- /tests/test_spyglass/tooloptions/spyglass-run-design_read.tcl: -------------------------------------------------------------------------------- 1 | open_project test_spyglass_0.prj 2 | 3 | current_goal Design_Read 4 | 5 | # Parameters which are not used/defined in a given goal/methodology raise 6 | # a WARNING, which fails the lint process. That's a bit over the top, we hence 7 | # disable this warning. 8 | waive -rule {checkCMD_unknown} 9 | 10 | set rc [run_goal] 11 | close_project -force 12 | 13 | set errorCode [lindex $rc 0] 14 | set errorMsg [lindex $rc 1] 15 | if { $errorCode } { 16 | puts stderr "SpyGlass run failed: $errorMsg ($errorCode)" 17 | } 18 | 19 | # requires sg_shell to be called with -enable_pass_exit_codes, otherwise 20 | # all non-fatal exit codes are mapped to 0 21 | exit $errorCode 22 | -------------------------------------------------------------------------------- /tests/test_spyglass/tooloptions/spyglass-run-lint_lint_rtl.tcl: -------------------------------------------------------------------------------- 1 | open_project test_spyglass_0.prj 2 | 3 | current_goal lint/lint_rtl 4 | 5 | # Parameters which are not used/defined in a given goal/methodology raise 6 | # a WARNING, which fails the lint process. That's a bit over the top, we hence 7 | # disable this warning. 8 | waive -rule {checkCMD_unknown} 9 | 10 | set rc [run_goal] 11 | close_project -force 12 | 13 | set errorCode [lindex $rc 0] 14 | set errorMsg [lindex $rc 1] 15 | if { $errorCode } { 16 | puts stderr "SpyGlass run failed: $errorMsg ($errorCode)" 17 | } 18 | 19 | # requires sg_shell to be called with -enable_pass_exit_codes, otherwise 20 | # all non-fatal exit codes are mapped to 0 21 | exit $errorCode 22 | -------------------------------------------------------------------------------- /tests/test_spyglass/tooloptions/spyglass-run-some_othergoal.tcl: -------------------------------------------------------------------------------- 1 | open_project test_spyglass_0.prj 2 | 3 | current_goal some/othergoal 4 | 5 | # Parameters which are not used/defined in a given goal/methodology raise 6 | # a WARNING, which fails the lint process. That's a bit over the top, we hence 7 | # disable this warning. 8 | waive -rule {checkCMD_unknown} 9 | 10 | set rc [run_goal] 11 | close_project -force 12 | 13 | set errorCode [lindex $rc 0] 14 | set errorMsg [lindex $rc 1] 15 | if { $errorCode } { 16 | puts stderr "SpyGlass run failed: $errorMsg ($errorCode)" 17 | } 18 | 19 | # requires sg_shell to be called with -enable_pass_exit_codes, otherwise 20 | # all non-fatal exit codes are mapped to 0 21 | exit $errorCode 22 | -------------------------------------------------------------------------------- /tests/test_spyglass/tooloptions/spyglass.cmd: -------------------------------------------------------------------------------- 1 | -enable_pass_exit_codes -tcl spyglass-run-design_read.tcl 2 | -enable_pass_exit_codes -tcl spyglass-run-lint_lint_rtl.tcl 3 | -enable_pass_exit_codes -tcl spyglass-run-some_othergoal.tcl 4 | -------------------------------------------------------------------------------- /tests/test_symbiflow/nextpnr/fpga_interchange/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | 3 | } 4 | 5 | proc set_defines {} { 6 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 7 | 8 | foreach d ${defines} { 9 | set key [lindex $d 0] 10 | set val [lindex $d 1] 11 | verilog_defines "-D$key=$val" 12 | }} 13 | 14 | proc set_incdirs {} { 15 | } 16 | 17 | proc set_params {} { 18 | chparam -set vlogparam_bool 1 top_module 19 | chparam -set vlogparam_int 42 top_module 20 | chparam -set vlogparam_str {"hello"} top_module} 21 | 22 | proc synth {top} { 23 | synth_xilinx -top $top 24 | } 25 | 26 | set top top_module 27 | set name test_symbiflow_nextpnr_fpga_interchange_0 28 | -------------------------------------------------------------------------------- /tests/test_symbiflow/nextpnr/fpga_interchange/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | write_json test_symbiflow_nextpnr_fpga_interchange_0.json 17 | -------------------------------------------------------------------------------- /tests/test_symbiflow/nextpnr/xilinx/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: test_symbiflow_nextpnr_xilinx_0.bit 4 | 5 | test_symbiflow_nextpnr_xilinx_0.json: edalize_yosys_template.tcl 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | 8 | test_symbiflow_nextpnr_xilinx_0.fasm: test_symbiflow_nextpnr_xilinx_0.json 9 | $(EDALIZE_LAUNCHER) nextpnr-xilinx --chipdb chipdb.bin --xdc top.xdc --json test_symbiflow_nextpnr_xilinx_0.json --write test_symbiflow_nextpnr_xilinx_0.routed.json --fasm test_symbiflow_nextpnr_xilinx_0.fasm --log nextpnr.log --fake_option 1000 10 | 11 | test_symbiflow_nextpnr_xilinx_0.bit: test_symbiflow_nextpnr_xilinx_0.fasm 12 | $(EDALIZE_LAUNCHER) symbiflow_write_bitstream -d artix7 -f test_symbiflow_nextpnr_xilinx_0.fasm -p xc7a35tcsg324-1csg324-1 -b test_symbiflow_nextpnr_xilinx_0.bit 13 | -------------------------------------------------------------------------------- /tests/test_symbiflow/nextpnr/xilinx/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | 3 | } 4 | 5 | proc set_defines {} { 6 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 7 | 8 | foreach d ${defines} { 9 | set key [lindex $d 0] 10 | set val [lindex $d 1] 11 | verilog_defines "-D$key=$val" 12 | }} 13 | 14 | proc set_incdirs {} { 15 | } 16 | 17 | proc set_params {} { 18 | chparam -set vlogparam_bool 1 top_module 19 | chparam -set vlogparam_int 42 top_module 20 | chparam -set vlogparam_str {"hello"} top_module} 21 | 22 | proc synth {top} { 23 | synth_xilinx -top $top 24 | } 25 | 26 | set top top_module 27 | set name test_symbiflow_nextpnr_xilinx_0 28 | -------------------------------------------------------------------------------- /tests/test_symbiflow/nextpnr/xilinx/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | write_json test_symbiflow_nextpnr_xilinx_0.json 17 | -------------------------------------------------------------------------------- /tests/test_symbiyosys/config.sby.j2: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prove pf 3 | cover cv 4 | 5 | [options] 6 | pf: mode prove 7 | pf: depth 3 8 | 9 | cv: mode cover 10 | cv: depth 32 11 | 12 | [engines] 13 | smtbmc boolector 14 | 15 | [script] 16 | {{"-sv"|gen_reads}} 17 | 18 | prep -top {{top_level}} 19 | 20 | [files] 21 | {{files}} 22 | -------------------------------------------------------------------------------- /tests/test_symbiyosys/files.txt: -------------------------------------------------------------------------------- 1 | sv_file.sv 2 | vlog_file.v 3 | vlog_with_define.v 4 | vlog05_file.v 5 | another_sv_file.sv 6 | -------------------------------------------------------------------------------- /tests/test_symbiyosys/incdirs.txt: -------------------------------------------------------------------------------- 1 | . 2 | -------------------------------------------------------------------------------- /tests/test_symbiyosys/sby.cmd: -------------------------------------------------------------------------------- 1 | -d build test.sby task0 task1 2 | -------------------------------------------------------------------------------- /tests/test_symbiyosys/test.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prove pf 3 | cover cv 4 | 5 | [options] 6 | pf: mode prove 7 | pf: depth 3 8 | 9 | cv: mode cover 10 | cv: depth 32 11 | 12 | [engines] 13 | smtbmc boolector 14 | 15 | [script] 16 | read -sv -Dvlogdefine_bool=1 -Dvlogdefine_int=42 -Dvlogdefine_str=hello -I. sv_file.sv 17 | read -sv -Dvlogdefine_bool=1 -Dvlogdefine_int=42 -Dvlogdefine_str=hello -I. vlog_file.v 18 | read -sv -Dvlogdefine_bool=1 -Dvlogdefine_int=42 -Dvlogdefine_str=hello -I. vlog_with_define.v 19 | read -sv -Dvlogdefine_bool=1 -Dvlogdefine_int=42 -Dvlogdefine_str=hello -I. vlog05_file.v 20 | read -sv -Dvlogdefine_bool=1 -Dvlogdefine_int=42 -Dvlogdefine_str=hello -I. another_sv_file.sv 21 | chparam -set vlogparam_bool 1 -set vlogparam_int 42 -set vlogparam_str "hello" top_module 22 | 23 | prep -top top_module 24 | 25 | [files] 26 | sv_file.sv 27 | vlog_file.v 28 | vlog_with_define.v 29 | vlog05_file.v 30 | another_sv_file.sv 31 | -------------------------------------------------------------------------------- /tests/test_tool_efinity.py: -------------------------------------------------------------------------------- 1 | from .edalize_tool_common import tool_fixture 2 | 3 | 4 | def test_tool_efinity(tool_fixture): 5 | import os 6 | 7 | tool_options = {"family": "Trion", "part": "T8F81", "timing": "C2"} 8 | 9 | orig_env = os.environ.copy() 10 | os.environ["EFINITY_HOME"] = "path/to/efinity/intallation" 11 | tf = tool_fixture("efinity", tool_options=tool_options) 12 | os.environ = orig_env 13 | 14 | name = "design" 15 | 16 | tf.tool.configure() 17 | tf.compare_config_files( 18 | [ 19 | name + ".xml", 20 | ] 21 | ) 22 | 23 | 24 | def test_tool_efinity_no_env(tool_fixture): 25 | import pytest 26 | 27 | with pytest.raises(RuntimeError) as e: 28 | tf = tool_fixture("efinity") 29 | assert "The environment variable EFINITY_HOME is not set" in str(e.value) 30 | -------------------------------------------------------------------------------- /tests/test_tool_gowin.py: -------------------------------------------------------------------------------- 1 | from .edalize_tool_common import tool_fixture 2 | 3 | 4 | def test_tool_gowin(tool_fixture): 5 | 6 | tool_options = { 7 | "part": "dummy_part", 8 | "gowin_options": ["some", "gowin", "options"], 9 | } 10 | 11 | tf = tool_fixture( 12 | "gowin", tool_options=tool_options, paramtypes=[], has_makefile=False 13 | ) 14 | 15 | tf.tool.configure() 16 | tf.compare_config_files(["edalize_gowin_template.tcl"]) 17 | 18 | 19 | def test_tool_gowin_minimal(tool_fixture): 20 | tool_options = {"part": "dummy_part"} 21 | tf = tool_fixture( 22 | "gowin", 23 | tool_options=tool_options, 24 | ref_subdir="minimal", 25 | paramtypes=[], 26 | has_makefile=False, 27 | ) 28 | 29 | tf.tool.configure() 30 | tf.compare_config_files(["edalize_gowin_template.tcl"]) 31 | -------------------------------------------------------------------------------- /tests/test_tool_icarus.py: -------------------------------------------------------------------------------- 1 | from .edalize_tool_common import tool_fixture 2 | 3 | 4 | def test_tool_icarus(tool_fixture): 5 | tool_name = "icarus" 6 | 7 | tool_options = { 8 | "timescale": "1ns/1ps", 9 | "iverilog_options": ["a", "few", "iverilog", "options"], 10 | "vvp_options": ["some", "vvp", "options"], 11 | } 12 | tf = tool_fixture(tool_name, tool_options=tool_options) 13 | 14 | tf.tool.configure() 15 | tf.compare_config_files(["design.scr"]) 16 | 17 | tf.tool.run() 18 | 19 | 20 | def test_tool_icarus_multiple_tops(tool_fixture): 21 | tf = tool_fixture( 22 | "icarus", toplevel=" ".join(["top1", "top2"]), ref_subdir="multitop" 23 | ) 24 | 25 | tf.tool.configure() 26 | tf.compare_config_files(["design.scr"]) 27 | 28 | tf.tool.run() 29 | -------------------------------------------------------------------------------- /tests/test_tool_verilator.py: -------------------------------------------------------------------------------- 1 | from .edalize_tool_common import tool_fixture 2 | 3 | 4 | def test_tool_verilator(tool_fixture): 5 | 6 | tool_options = { 7 | "make_options": ["a", "few", "make", "options"], 8 | "verilator_options": ["some", "verilator", "options"], 9 | "run_options": ["and", "some", "run", "options"], 10 | } 11 | 12 | tf = tool_fixture("verilator", tool_options=tool_options) 13 | 14 | name = "design" 15 | 16 | tf.tool.configure() 17 | tf.compare_config_files( 18 | [ 19 | name + ".vc", 20 | ] 21 | ) 22 | 23 | 24 | def test_tool_verilator_minimal(tool_fixture): 25 | tf = tool_fixture("verilator", ref_subdir="minimal") 26 | 27 | name = "design" 28 | 29 | tf.tool.configure() 30 | tf.compare_config_files( 31 | [ 32 | name + ".vc", 33 | ] 34 | ) 35 | -------------------------------------------------------------------------------- /tests/test_trellis/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: test_trellis_0.bit 4 | 5 | test_trellis_0.json: edalize_yosys_template.tcl 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | 8 | test_trellis_0.config: test_trellis_0.json 9 | $(EDALIZE_LAUNCHER) nextpnr-ecp5 -l next.log a few nextpnr_options --lpf lpf_file.lpf --json test_trellis_0.json --textcfg test_trellis_0.config 10 | 11 | build-gui: test_trellis_0.json 12 | $(EDALIZE_LAUNCHER) nextpnr-ecp5 -l next.log a few nextpnr_options --lpf lpf_file.lpf --json test_trellis_0.json --textcfg test_trellis_0.config --gui 13 | 14 | test_trellis_0.bit: test_trellis_0.config 15 | $(EDALIZE_LAUNCHER) ecppack --svf test_trellis_0.svf test_trellis_0.config test_trellis_0.bit 16 | -------------------------------------------------------------------------------- /tests/test_trellis/ecppack.cmd: -------------------------------------------------------------------------------- 1 | --svf test_trellis_0.svf test_trellis_0.config test_trellis_0.bit 2 | -------------------------------------------------------------------------------- /tests/test_trellis/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | read_verilog -sv {sv_file.sv} 3 | source {tcl_file.tcl} 4 | read_verilog {vlog_file.v} 5 | read_verilog {vlog_with_define.v} 6 | read_verilog {vlog05_file.v} 7 | read_verilog -sv {another_sv_file.sv} 8 | } 9 | 10 | proc set_defines {} { 11 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 12 | 13 | foreach d ${defines} { 14 | set key [lindex $d 0] 15 | set val [lindex $d 1] 16 | verilog_defines "-D$key=$val" 17 | }} 18 | 19 | proc set_incdirs {} { 20 | verilog_defaults -add -I.} 21 | 22 | proc set_params {} { 23 | chparam -set vlogparam_bool 1 top_module 24 | chparam -set vlogparam_int 42 top_module 25 | chparam -set vlogparam_str {"hello"} top_module} 26 | 27 | proc synth {top} { 28 | synth_ecp5 some yosys_synth_options -top $top 29 | } 30 | 31 | set top top_module 32 | set name test_trellis_0 33 | -------------------------------------------------------------------------------- /tests/test_trellis/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | write_json test_trellis_0.json 17 | -------------------------------------------------------------------------------- /tests/test_trellis/minimal/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: test_trellis_0.bit 4 | 5 | test_trellis_0.json: edalize_yosys_template.tcl 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | 8 | test_trellis_0.config: test_trellis_0.json 9 | $(EDALIZE_LAUNCHER) nextpnr-ecp5 -l next.log --json test_trellis_0.json --textcfg test_trellis_0.config 10 | 11 | build-gui: test_trellis_0.json 12 | $(EDALIZE_LAUNCHER) nextpnr-ecp5 -l next.log --json test_trellis_0.json --textcfg test_trellis_0.config --gui 13 | 14 | test_trellis_0.bit: test_trellis_0.config 15 | $(EDALIZE_LAUNCHER) ecppack --svf test_trellis_0.svf test_trellis_0.config test_trellis_0.bit 16 | -------------------------------------------------------------------------------- /tests/test_trellis/minimal/ecppack.cmd: -------------------------------------------------------------------------------- 1 | --svf test_trellis_0.svf test_trellis_0.config test_trellis_0.bit 2 | -------------------------------------------------------------------------------- /tests/test_trellis/minimal/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc read_files {} { 2 | 3 | } 4 | 5 | proc set_defines {} { 6 | set defines {} 7 | 8 | foreach d ${defines} { 9 | set key [lindex $d 0] 10 | set val [lindex $d 1] 11 | verilog_defines "-D$key=$val" 12 | }} 13 | 14 | proc set_incdirs {} { 15 | } 16 | 17 | proc set_params {} { 18 | } 19 | 20 | proc synth {top} { 21 | synth_ecp5 -top $top 22 | } 23 | 24 | set top top_module 25 | set name test_trellis_0 26 | -------------------------------------------------------------------------------- /tests/test_trellis/minimal/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | 4 | verilog_defaults -push 5 | verilog_defaults -add -defer 6 | 7 | set_defines 8 | set_incdirs 9 | read_files 10 | set_params 11 | 12 | verilog_defaults -pop 13 | 14 | synth $top 15 | 16 | write_json test_trellis_0.json 17 | -------------------------------------------------------------------------------- /tests/test_trellis/minimal/nextpnr-ecp5.cmd: -------------------------------------------------------------------------------- 1 | -l next.log --json test_trellis_0.json --textcfg test_trellis_0.config 2 | -------------------------------------------------------------------------------- /tests/test_trellis/minimal/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_trellis/nextpnr-ecp5.cmd: -------------------------------------------------------------------------------- 1 | -l next.log a few nextpnr_options --lpf lpf_file.lpf --json test_trellis_0.json --textcfg test_trellis_0.config 2 | -------------------------------------------------------------------------------- /tests/test_trellis/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_vcs/minimal/Makefile: -------------------------------------------------------------------------------- 1 | all: test_vcs_minimal_0 2 | 3 | test_vcs_minimal_0: test_vcs_minimal_0.scr 4 | $(EDALIZE_LAUNCHER) vcs -full64 -top top -f test_vcs_minimal_0.scr -o $@ 5 | run: test_vcs_minimal_0 6 | ./test_vcs_minimal_0 -l vcs.log 7 | clean: 8 | $(RM) test_vcs_minimal_0 9 | -------------------------------------------------------------------------------- /tests/test_vcs/minimal/run.cmd: -------------------------------------------------------------------------------- 1 | -l vcs.log 2 | -------------------------------------------------------------------------------- /tests/test_vcs/minimal/test_vcs_minimal_0.scr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/edalize/1eedb7f726d1899465da30363763ea8c93d074af/tests/test_vcs/minimal/test_vcs_minimal_0.scr -------------------------------------------------------------------------------- /tests/test_vcs/minimal/vcs.cmd: -------------------------------------------------------------------------------- 1 | -full64 -top top -f test_vcs_minimal_0.scr -o test_vcs_minimal_0 2 | -------------------------------------------------------------------------------- /tests/test_vcs/no_tool_options/Makefile: -------------------------------------------------------------------------------- 1 | all: test_vcs_0 2 | 3 | test_vcs_0: test_vcs_0.scr 4 | $(EDALIZE_LAUNCHER) vcs -full64 -top top_module -f test_vcs_0.scr -o $@ -sverilog 5 | run: test_vcs_0 6 | ./test_vcs_0 -l vcs.log +plusarg_bool +plusarg_int=42 +plusarg_str=hello 7 | clean: 8 | $(RM) test_vcs_0 9 | -------------------------------------------------------------------------------- /tests/test_vcs/no_tool_options/run.cmd: -------------------------------------------------------------------------------- 1 | -l vcs.log +plusarg_bool +plusarg_int=42 +plusarg_str=hello 2 | -------------------------------------------------------------------------------- /tests/test_vcs/no_tool_options/test_vcs_0.scr: -------------------------------------------------------------------------------- 1 | +define+vlogdefine_bool=1 2 | +define+vlogdefine_int=42 3 | +define+vlogdefine_str=hello 4 | -pvalue+top_module.vlogparam_bool=1 5 | -pvalue+top_module.vlogparam_int=42 6 | -pvalue+top_module.vlogparam_str="hello" 7 | +incdir+. 8 | sv_file.sv 9 | vlog_file.v 10 | vlog_with_define.v 11 | vlog05_file.v 12 | c_file.c 13 | cpp_file.cpp 14 | another_sv_file.sv 15 | -------------------------------------------------------------------------------- /tests/test_vcs/no_tool_options/vcs.cmd: -------------------------------------------------------------------------------- 1 | -full64 -top top_module -f test_vcs_0.scr -o test_vcs_0 -sverilog 2 | -------------------------------------------------------------------------------- /tests/test_vcs/tool_options/Makefile: -------------------------------------------------------------------------------- 1 | all: test_vcs_tool_options_0 2 | 3 | test_vcs_tool_options_0: test_vcs_tool_options_0.scr 4 | $(EDALIZE_LAUNCHER) vcs -full64 -top top_module -f test_vcs_tool_options_0.scr -o $@ -debug_access+pp -debug_access+all -sverilog 5 | run: test_vcs_tool_options_0 6 | ./test_vcs_tool_options_0 -l vcs.log +plusarg_bool +plusarg_int=42 +plusarg_str=hello -licqueue 7 | clean: 8 | $(RM) test_vcs_tool_options_0 9 | -------------------------------------------------------------------------------- /tests/test_vcs/tool_options/run.cmd: -------------------------------------------------------------------------------- 1 | -l vcs.log +plusarg_bool +plusarg_int=42 +plusarg_str=hello -licqueue 2 | -------------------------------------------------------------------------------- /tests/test_vcs/tool_options/test_vcs_tool_options_0.scr: -------------------------------------------------------------------------------- 1 | +define+vlogdefine_bool=1 2 | +define+vlogdefine_int=42 3 | +define+vlogdefine_str=hello 4 | -pvalue+top_module.vlogparam_bool=1 5 | -pvalue+top_module.vlogparam_int=42 6 | -pvalue+top_module.vlogparam_str="hello" 7 | +incdir+. 8 | sv_file.sv 9 | vlog_file.v 10 | vlog_with_define.v 11 | vlog05_file.v 12 | c_file.c 13 | cpp_file.cpp 14 | another_sv_file.sv 15 | -------------------------------------------------------------------------------- /tests/test_vcs/tool_options/vcs.cmd: -------------------------------------------------------------------------------- 1 | -full64 -top top_module -f test_vcs_tool_options_0.scr -o test_vcs_tool_options_0 -debug_access+pp -debug_access+all -sverilog 2 | -------------------------------------------------------------------------------- /tests/test_veribleformat.py: -------------------------------------------------------------------------------- 1 | from .edalize_common import make_edalize_test 2 | 3 | 4 | def test_veribleformat_default(make_edalize_test): 5 | """Test the format mode of Verible""" 6 | tf = make_edalize_test( 7 | "veribleformat", 8 | test_name="test_verible", 9 | param_types=["vlogdefine", "vlogparam"], 10 | ref_dir="default", 11 | ) 12 | tf.backend.configure() 13 | tf.backend.build() 14 | tf.backend.run() 15 | tf.compare_files(["verible-verilog-format.cmd"]) 16 | -------------------------------------------------------------------------------- /tests/test_veribleformat/default/verible-verilog-format.cmd: -------------------------------------------------------------------------------- 1 | sv_file.sv 2 | vlog_file.v 3 | vlog_with_define.v 4 | vlog05_file.v 5 | another_sv_file.sv 6 | -------------------------------------------------------------------------------- /tests/test_veriblelint.py: -------------------------------------------------------------------------------- 1 | from .edalize_common import make_edalize_test 2 | 3 | 4 | def test_veriblelint_default(make_edalize_test): 5 | """Test the lint mode of Verible""" 6 | tf = make_edalize_test( 7 | "veriblelint", 8 | test_name="test_verible", 9 | param_types=["vlogdefine", "vlogparam"], 10 | ref_dir="lint", 11 | ) 12 | tf.backend.configure() 13 | tf.backend.build() 14 | tf.backend.run() 15 | tf.compare_files(["verible-verilog-lint.cmd"]) 16 | -------------------------------------------------------------------------------- /tests/test_veriblelint/lint/verible-verilog-lint.cmd: -------------------------------------------------------------------------------- 1 | --lint_fatal --parse_fatal --rules_config=config.vbl --waiver_files=verible_waiver.vbw,verible_waiver2.vbw sv_file.sv 2 | --lint_fatal --parse_fatal --rules_config=config.vbl --waiver_files=verible_waiver.vbw,verible_waiver2.vbw vlog_file.v 3 | --lint_fatal --parse_fatal --rules_config=config.vbl --waiver_files=verible_waiver.vbw,verible_waiver2.vbw vlog_with_define.v 4 | --lint_fatal --parse_fatal --rules_config=config.vbl --waiver_files=verible_waiver.vbw,verible_waiver2.vbw vlog05_file.v 5 | --lint_fatal --parse_fatal --rules_config=config.vbl --waiver_files=verible_waiver.vbw,verible_waiver2.vbw another_sv_file.sv 6 | -------------------------------------------------------------------------------- /tests/test_verilator/Vtop_module: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | echo "$@" > run.cmd 3 | -------------------------------------------------------------------------------- /tests/test_verilator/binary/config.mk: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | TOP_MODULE := top_module 4 | VC_FILE := test_verilator_0.vc 5 | VERILATOR_OPTIONS := 6 | MAKE_OPTIONS := 7 | -------------------------------------------------------------------------------- /tests/test_verilator/binary/test_verilator_0.vc: -------------------------------------------------------------------------------- 1 | --Mdir . 2 | +incdir+. 3 | -CFLAGS -I. 4 | sv_file.sv 5 | vlog_file.v 6 | vlog_with_define.v 7 | vlog05_file.v 8 | another_sv_file.sv 9 | --top-module top_module 10 | --exe 11 | c_file.c 12 | cpp_file.cpp 13 | -------------------------------------------------------------------------------- /tests/test_verilator/cc/config.mk: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | TOP_MODULE := top_module 4 | VC_FILE := test_verilator_0.vc 5 | VERILATOR_OPTIONS := -Wno-fatal --trace 6 | MAKE_OPTIONS := OPT_FAST=-O2 7 | -------------------------------------------------------------------------------- /tests/test_verilator/cc/test_verilator_0.vc: -------------------------------------------------------------------------------- 1 | --Mdir . 2 | --cc 3 | -LDFLAGS -lelf 4 | +incdir+. 5 | -CFLAGS -I. 6 | sv_file.sv 7 | vlog_file.v 8 | vlog_with_define.v 9 | vlog05_file.v 10 | another_sv_file.sv 11 | --top-module top_module 12 | --exe 13 | c_file.c 14 | cpp_file.cpp 15 | -Gvlogparam_bool=1 16 | -Gvlogparam_int=42 17 | -Gvlogparam_str=\"hello\" 18 | -Dvlogdefine_bool=1 19 | -Dvlogdefine_int=42 20 | -Dvlogdefine_str=hello 21 | -------------------------------------------------------------------------------- /tests/test_verilator/dpi-hdr-only/config.mk: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | TOP_MODULE := top_module 4 | VC_FILE := test_verilator_0.vc 5 | VERILATOR_OPTIONS := 6 | MAKE_OPTIONS := 7 | -------------------------------------------------------------------------------- /tests/test_verilator/dpi-hdr-only/test_verilator_0.vc: -------------------------------------------------------------------------------- 1 | --Mdir . 2 | +incdir+. 3 | -CFLAGS -I. 4 | sv_file.sv 5 | vlog_file.v 6 | vlog_with_define.v 7 | vlog05_file.v 8 | another_sv_file.sv 9 | --top-module top_module 10 | --exe 11 | c_file.c 12 | cpp_file.cpp 13 | -------------------------------------------------------------------------------- /tests/test_verilator/lint-only/config.mk: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | TOP_MODULE := top_module 4 | VC_FILE := test_verilator_0.vc 5 | VERILATOR_OPTIONS := 6 | MAKE_OPTIONS := 7 | -------------------------------------------------------------------------------- /tests/test_verilator/lint-only/test_verilator_0.vc: -------------------------------------------------------------------------------- 1 | --Mdir . 2 | +incdir+. 3 | -CFLAGS -I. 4 | sv_file.sv 5 | vlog_file.v 6 | vlog_with_define.v 7 | vlog05_file.v 8 | another_sv_file.sv 9 | --top-module top_module 10 | --exe 11 | c_file.c 12 | cpp_file.cpp 13 | -------------------------------------------------------------------------------- /tests/test_verilator/preprocess-only/config.mk: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | TOP_MODULE := top_module 4 | VC_FILE := test_verilator_0.vc 5 | VERILATOR_OPTIONS := 6 | MAKE_OPTIONS := 7 | -------------------------------------------------------------------------------- /tests/test_verilator/preprocess-only/test_verilator_0.vc: -------------------------------------------------------------------------------- 1 | --Mdir . 2 | +incdir+. 3 | -CFLAGS -I. 4 | sv_file.sv 5 | vlog_file.v 6 | vlog_with_define.v 7 | vlog05_file.v 8 | another_sv_file.sv 9 | --top-module top_module 10 | --exe 11 | c_file.c 12 | cpp_file.cpp 13 | -------------------------------------------------------------------------------- /tests/test_verilator/run.cmd: -------------------------------------------------------------------------------- 1 | +plusarg_bool=1 +plusarg_int=42 +plusarg_str=hello --cmdlinearg_bool=1 --cmdlinearg_int=42 --cmdlinearg_str=hello 2 | -------------------------------------------------------------------------------- /tests/test_verilator/sc/config.mk: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | TOP_MODULE := top_module 4 | VC_FILE := test_verilator_0.vc 5 | VERILATOR_OPTIONS := 6 | MAKE_OPTIONS := 7 | -------------------------------------------------------------------------------- /tests/test_verilator/sc/test_verilator_0.vc: -------------------------------------------------------------------------------- 1 | --Mdir . 2 | --sc 3 | +incdir+. 4 | -CFLAGS -I. 5 | sv_file.sv 6 | vlog_file.v 7 | vlog_with_define.v 8 | vlog05_file.v 9 | another_sv_file.sv 10 | --top-module top_module 11 | --exe 12 | c_file.c 13 | cpp_file.cpp 14 | -------------------------------------------------------------------------------- /tests/test_verilator/xml-only/config.mk: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | TOP_MODULE := top_module 4 | VC_FILE := test_verilator_0.vc 5 | VERILATOR_OPTIONS := 6 | MAKE_OPTIONS := 7 | -------------------------------------------------------------------------------- /tests/test_verilator/xml-only/test_verilator_0.vc: -------------------------------------------------------------------------------- 1 | --Mdir . 2 | +incdir+. 3 | -CFLAGS -I. 4 | sv_file.sv 5 | vlog_file.v 6 | vlog_with_define.v 7 | vlog05_file.v 8 | another_sv_file.sv 9 | --top-module top_module 10 | --exe 11 | c_file.c 12 | cpp_file.cpp 13 | -------------------------------------------------------------------------------- /tests/test_vivado/board_file/test_vivado_0_synth.tcl: -------------------------------------------------------------------------------- 1 | set outdated [get_property NEEDS_REFRESH [get_runs synth_1]] 2 | set progress [get_property PROGRESS [get_runs synth_1]] 3 | 4 | if {$outdated || $progress != "100%"} { 5 | reset_runs synth_1 6 | launch_runs synth_1 7 | wait_on_run synth_1 8 | } 9 | #exit [regexp -nocase -- {synth_design (error|failed)} [get_property STATUS [get_runs synth_1]] match] 10 | -------------------------------------------------------------------------------- /tests/test_vivado/board_file/test_vivado_minimal_0.tcl: -------------------------------------------------------------------------------- 1 | # Auto-generated project tcl file 2 | 3 | 4 | create_project test_vivado_minimal_0 -force 5 | 6 | set_property part xc7a35tcsg324-1 [current_project] 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | set_property include_dirs [list .] [get_filesets sources_1] 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /tests/test_vivado/board_file/test_vivado_minimal_0_synth.tcl: -------------------------------------------------------------------------------- 1 | launch_runs synth_1 2 | wait_on_run synth_1 3 | exit [regexp -nocase -- {synth_design (error|failed)} [get_property STATUS [get_runs synth_1]] match] 4 | -------------------------------------------------------------------------------- /tests/test_vivado/board_file/vivado.cmd: -------------------------------------------------------------------------------- 1 | -notrace -mode batch -source test_vivado_0.tcl 2 | -notrace -mode batch -source test_vivado_0_synth.tcl test_vivado_0_run.tcl test_vivado_0.xpr 3 | -------------------------------------------------------------------------------- /tests/test_vivado/edif_netlist/test_vivado_0.tcl: -------------------------------------------------------------------------------- 1 | # Auto-generated project tcl file 2 | 3 | 4 | create_project test_vivado_0 -force 5 | 6 | set_property part xc7a35tcsg324-1 [current_project] 7 | 8 | 9 | set_property generic {vlogparam_bool=1 vlogparam_int=42 vlogparam_str=hello } [get_filesets sources_1] 10 | set_property generic {generic_bool=true generic_int=42 generic_str=hello } [get_filesets sources_1] 11 | set_property verilog_define {vlogdefine_bool=1 vlogdefine_int=42 vlogdefine_str=hello } [get_filesets sources_1] 12 | read_edif {netlist.edif} 13 | 14 | set_property include_dirs [list .] [get_filesets sources_1] 15 | set_property top top_module [current_fileset] 16 | set_property source_mgmt_mode None [current_project] 17 | 18 | 19 | link_design -top test_vivado_0 -part xc7a35tcsg324-1 -------------------------------------------------------------------------------- /tests/test_vivado/edif_netlist/test_vivado_0_synth.tcl: -------------------------------------------------------------------------------- 1 | set outdated [get_property NEEDS_REFRESH [get_runs synth_1]] 2 | set progress [get_property PROGRESS [get_runs synth_1]] 3 | 4 | if {$outdated || $progress != "100%"} { 5 | reset_runs synth_1 6 | launch_runs synth_1 7 | wait_on_run synth_1 8 | } 9 | #exit [regexp -nocase -- {synth_design (error|failed)} [get_property STATUS [get_runs synth_1]] match] 10 | -------------------------------------------------------------------------------- /tests/test_vivado/edif_netlist/vivado.cmd: -------------------------------------------------------------------------------- 1 | -notrace -mode batch -source test_vivado_0.tcl 2 | -notrace -mode batch -source test_vivado_0_synth.tcl test_vivado_0_run.tcl test_vivado_0.xpr 3 | -------------------------------------------------------------------------------- /tests/test_vivado/edif_netlist_no_link_design/test_vivado_0.tcl: -------------------------------------------------------------------------------- 1 | # Auto-generated project tcl file 2 | 3 | 4 | create_project test_vivado_0 -force 5 | 6 | set_property part xc7a35tcsg324-1 [current_project] 7 | 8 | 9 | set_property generic {vlogparam_bool=1 vlogparam_int=42 vlogparam_str=hello } [get_filesets sources_1] 10 | set_property generic {generic_bool=true generic_int=42 generic_str=hello } [get_filesets sources_1] 11 | set_property verilog_define {vlogdefine_bool=1 vlogdefine_int=42 vlogdefine_str=hello } [get_filesets sources_1] 12 | read_edif {netlist.edif} 13 | 14 | set_property include_dirs [list .] [get_filesets sources_1] 15 | set_property top top_module [current_fileset] 16 | set_property source_mgmt_mode None [current_project] 17 | 18 | 19 | -------------------------------------------------------------------------------- /tests/test_vivado/edif_netlist_no_link_design/test_vivado_0_synth.tcl: -------------------------------------------------------------------------------- 1 | set outdated [get_property NEEDS_REFRESH [get_runs synth_1]] 2 | set progress [get_property PROGRESS [get_runs synth_1]] 3 | 4 | if {$outdated || $progress != "100%"} { 5 | reset_runs synth_1 6 | launch_runs synth_1 7 | wait_on_run synth_1 8 | } 9 | #exit [regexp -nocase -- {synth_design (error|failed)} [get_property STATUS [get_runs synth_1]] match] 10 | -------------------------------------------------------------------------------- /tests/test_vivado/edif_netlist_no_link_design/vivado.cmd: -------------------------------------------------------------------------------- 1 | -notrace -mode batch -source test_vivado_0.tcl 2 | -notrace -mode batch -source test_vivado_0_synth.tcl test_vivado_0_run.tcl test_vivado_0.xpr 3 | -------------------------------------------------------------------------------- /tests/test_vivado/minimal/test_vivado_minimal_0.tcl: -------------------------------------------------------------------------------- 1 | # Auto-generated project tcl file 2 | 3 | 4 | create_project test_vivado_minimal_0 -force 5 | 6 | set_property part xc7a35tcsg324-1 [current_project] 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | set_property include_dirs [list .] [get_filesets sources_1] 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /tests/test_vivado/minimal/test_vivado_minimal_0_synth.tcl: -------------------------------------------------------------------------------- 1 | set outdated [get_property NEEDS_REFRESH [get_runs synth_1]] 2 | set progress [get_property PROGRESS [get_runs synth_1]] 3 | 4 | if {$outdated || $progress != "100%"} { 5 | reset_runs synth_1 6 | launch_runs synth_1 7 | wait_on_run synth_1 8 | } 9 | #exit [regexp -nocase -- {synth_design (error|failed)} [get_property STATUS [get_runs synth_1]] match] 10 | -------------------------------------------------------------------------------- /tests/test_vivado/minimal/vivado.cmd: -------------------------------------------------------------------------------- 1 | -notrace -mode batch -source test_vivado_minimal_0.tcl 2 | -notrace -mode batch -source test_vivado_minimal_0_synth.tcl test_vivado_minimal_0_run.tcl test_vivado_minimal_0.xpr 3 | -------------------------------------------------------------------------------- /tests/test_vivado/test_vivado_0_synth.tcl: -------------------------------------------------------------------------------- 1 | set outdated [get_property NEEDS_REFRESH [get_runs synth_1]] 2 | set progress [get_property PROGRESS [get_runs synth_1]] 3 | 4 | if {$outdated || $progress != "100%"} { 5 | reset_runs synth_1 6 | launch_runs synth_1 7 | wait_on_run synth_1 8 | } 9 | #exit [regexp -nocase -- {synth_design (error|failed)} [get_property STATUS [get_runs synth_1]] match] 10 | -------------------------------------------------------------------------------- /tests/test_vivado/vivado.cmd: -------------------------------------------------------------------------------- 1 | -notrace -mode batch -source test_vivado_0.tcl 2 | -notrace -mode batch -source test_vivado_0_synth.tcl test_vivado_0_run.tcl test_vivado_0.xpr 3 | -------------------------------------------------------------------------------- /tests/test_vivado/yosys/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | 6 | } 7 | 8 | proc set_defines {} { 9 | set defines {} 10 | 11 | foreach d ${defines} { 12 | set key [lindex $d 0] 13 | set val [lindex $d 1] 14 | verilog_defines "-D$key=$val" 15 | }} 16 | 17 | proc set_incdirs {} { 18 | } 19 | 20 | proc set_params {} { 21 | } 22 | 23 | proc synth {top} { 24 | synth_xilinx -top $top 25 | } 26 | 27 | set top [] 28 | set name test_vivado_yosys_0 29 | -------------------------------------------------------------------------------- /tests/test_vivado/yosys/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_edif -pvector bra $name.edif 19 | -------------------------------------------------------------------------------- /tests/test_vivado/yosys/test_vivado_yosys_0.tcl: -------------------------------------------------------------------------------- 1 | # Auto-generated project tcl file 2 | 3 | 4 | create_project test_vivado_yosys_0 -force 5 | 6 | set_property part xc7a35tcsg324-1 [current_project] 7 | 8 | 9 | 10 | 11 | 12 | read_edif {test_vivado_yosys_0.edif} 13 | 14 | set_property include_dirs [list .] [get_filesets sources_1] 15 | 16 | 17 | 18 | link_design -top test_vivado_yosys_0 -part xc7a35tcsg324-1 -------------------------------------------------------------------------------- /tests/test_vivado/yosys/vivado.cmd: -------------------------------------------------------------------------------- 1 | -notrace -mode batch -source test_vivado_yosys_0.tcl 2 | -notrace -mode batch -source test_vivado_yosys_0_synth.tcl test_vivado_yosys_0_run.tcl test_vivado_yosys_0.xpr 3 | -------------------------------------------------------------------------------- /tests/test_vivado/yosys/yosys.cmd: -------------------------------------------------------------------------------- 1 | -l yosys.log -p tcl edalize_yosys_template.tcl 2 | -------------------------------------------------------------------------------- /tests/test_vpr/vpr/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: post_build 4 | 5 | pre_build: 6 | 7 | test_vpr_vpr_0.blif: edalize_yosys_template.tcl | pre_build 8 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 9 | 10 | test_vpr_vpr_0.net: test_vpr_vpr_0.blif 11 | $(EDALIZE_LAUNCHER) vpr /tmp/k6_N10_mem32K_40nm.xml test_vpr_vpr_0.blif --pack 12 | 13 | test_vpr_vpr_0.place: test_vpr_vpr_0.net 14 | $(EDALIZE_LAUNCHER) vpr /tmp/k6_N10_mem32K_40nm.xml test_vpr_vpr_0.blif --place 15 | 16 | test_vpr_vpr_0.route: test_vpr_vpr_0.place 17 | $(EDALIZE_LAUNCHER) vpr /tmp/k6_N10_mem32K_40nm.xml test_vpr_vpr_0.blif --route 18 | 19 | test_vpr_vpr_0.analysis: test_vpr_vpr_0.route 20 | $(EDALIZE_LAUNCHER) vpr /tmp/k6_N10_mem32K_40nm.xml test_vpr_vpr_0.blif --analysis 21 | 22 | post_build: test_vpr_vpr_0.analysis 23 | 24 | pre_run: 25 | 26 | run: pre_run 27 | 28 | post_run: run 29 | -------------------------------------------------------------------------------- /tests/test_vunit/minimal/tb_minimal.vhd: -------------------------------------------------------------------------------- 1 | library vunit_lib; 2 | context vunit_lib.vunit_context; 3 | 4 | entity tb_minimal is 5 | generic (runner_cfg : string); 6 | end entity; 7 | 8 | architecture tb of tb_minimal is 9 | begin 10 | main : process 11 | begin 12 | test_runner_setup(runner, runner_cfg); 13 | while test_suite loop 14 | 15 | if run("testcase_1") then 16 | report "Hello from testcase_1"; 17 | elsif run("testcase_2") then 18 | report "Hello from testcase_2"; 19 | end if; 20 | end loop; 21 | test_runner_cleanup(runner); 22 | end process; 23 | end architecture; 24 | -------------------------------------------------------------------------------- /tests/test_vunit/vunit_mock/vunit/__init__.py: -------------------------------------------------------------------------------- 1 | from os.path import dirname, join, abspath 2 | from .ui import VUnit 3 | -------------------------------------------------------------------------------- /tests/test_vunit/vunit_mock/vunit/ui.py: -------------------------------------------------------------------------------- 1 | from unittest.mock import MagicMock 2 | 3 | 4 | class Library(MagicMock): 5 | def add_source_files(self, file): 6 | print("add_source_files()") 7 | 8 | 9 | class VUnit(MagicMock): 10 | @staticmethod 11 | def from_argv(): 12 | return VUnit() 13 | 14 | def add_library(self): 15 | print("add_library()") 16 | return Library() 17 | -------------------------------------------------------------------------------- /tests/test_vunit/vunit_mock/vunit/vhdl_standard.py: -------------------------------------------------------------------------------- 1 | from unittest.mock import MagicMock 2 | 3 | 4 | class VHDL(MagicMock): 5 | @staticmethod 6 | def standard(std): 7 | pass 8 | -------------------------------------------------------------------------------- /tests/test_xcelium/edalize_build_rtl.f: -------------------------------------------------------------------------------- 1 | -makelib worklib some xmvlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello -sv +incdir+. sv_file.sv -endlib 2 | -makelib worklib some xmvlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. vlog_file.v -endlib 3 | -makelib worklib some xmvlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. vlog_with_define.v -endlib 4 | -makelib worklib some xmvlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello +incdir+. vlog05_file.v -endlib 5 | -makelib worklib various xmvhdl_options vhdl_file.vhd -endlib 6 | -makelib libx various xmvhdl_options vhdl_lfile -endlib 7 | -makelib worklib -v200x various xmvhdl_options vhdl2008_file -endlib 8 | -makelib worklib some xmvlog_options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=hello -sv +incdir+. another_sv_file.sv -endlib 9 | -------------------------------------------------------------------------------- /tests/test_xcelium/edalize_main.f: -------------------------------------------------------------------------------- 1 | -f edalize_build_rtl.f 2 | -input tcl_file.tcl 3 | -------------------------------------------------------------------------------- /tests/test_xcelium/xrun.cmd: -------------------------------------------------------------------------------- 1 | -q -f edalize_main.f plenty of xrun_options -sv_lib libdpi1.so -sv_lib libdpi2.so -xmsimargs 'a few xmsim_options' -defparam vlogparam_bool=1 -defparam vlogparam_int=42 -defparam vlogparam_str=hello +plusarg_bool=1 +plusarg_int=42 +plusarg_str=hello -top top_module 2 | -------------------------------------------------------------------------------- /tests/test_xsim/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | include config.mk 3 | 4 | all: xsim.dir/$(TARGET)/xsimk 5 | 6 | xsim.dir/$(TARGET)/xsimk: 7 | xelab $(TOPLEVEL) -prj $(TARGET).prj -snapshot $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(GEN_PARAMS) $(XELAB_OPTIONS) 8 | 9 | run: xsim.dir/$(TARGET)/xsimk 10 | xsim -R $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS) 11 | 12 | run-gui: xsim.dir/$(TARGET)/xsimk 13 | xsim --gui $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS) 14 | -------------------------------------------------------------------------------- /tests/test_xsim/config.mk: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | TARGET = test_xsim_0 3 | TOPLEVEL = top_module 4 | 5 | VLOG_DEFINES = --define vlogdefine_bool=1 --define vlogdefine_int=42 --define vlogdefine_str=hello 6 | VLOG_INCLUDES = -i . 7 | GEN_PARAMS = --generic_top "vlogparam_bool=1" --generic_top "vlogparam_int=42" --generic_top "vlogparam_str=hello" --generic_top "generic_bool=1" --generic_top "generic_int=42" --generic_top "generic_str=hello" 8 | 9 | XELAB_OPTIONS = some xelab_options 10 | XSIM_OPTIONS = a few xsim_options 11 | -------------------------------------------------------------------------------- /tests/test_xsim/mfc/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | include config.mk 3 | 4 | all: xsim.dir/$(TARGET)/xsimk 5 | 6 | xsim.dir/$(TARGET)/xsimk: 7 | xelab $(TOPLEVEL) -prj $(TARGET).prj -snapshot $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(GEN_PARAMS) $(XELAB_OPTIONS) 8 | 9 | run: xsim.dir/$(TARGET)/xsimk 10 | xsim -R $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS) 11 | 12 | run-gui: xsim.dir/$(TARGET)/xsimk 13 | xsim --gui $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS) 14 | -------------------------------------------------------------------------------- /tests/test_xsim/mfc/config.mk: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | TARGET = test_xsim_0 3 | TOPLEVEL = top_module 4 | 5 | VLOG_DEFINES = --define vlogdefine_bool=1 --define vlogdefine_int=42 --define vlogdefine_str=hello 6 | VLOG_INCLUDES = -i . 7 | GEN_PARAMS = --generic_top "vlogparam_bool=1" --generic_top "vlogparam_int=42" --generic_top "vlogparam_str=hello" --generic_top "generic_bool=1" --generic_top "generic_int=42" --generic_top "generic_str=hello" 8 | 9 | XELAB_OPTIONS = some xelab_options 10 | XSIM_OPTIONS = a few xsim_options 11 | -------------------------------------------------------------------------------- /tests/test_xsim/mfc/test_xsim_0.prj: -------------------------------------------------------------------------------- 1 | verilog work vlog_file.v 2 | verilog work vlog_with_define.v 3 | verilog work vlog05_file.v 4 | vhdl work vhdl_file.vhd 5 | vhdl libx vhdl_lfile 6 | vhdl2008 work vhdl2008_file 7 | sv work sv_file.sv another_sv_file.sv -------------------------------------------------------------------------------- /tests/test_xsim/mfc/xelab.cmd: -------------------------------------------------------------------------------- 1 | top_module -prj test_xsim_0.prj -snapshot test_xsim_0 --define vlogdefine_bool=1 --define vlogdefine_int=42 --define vlogdefine_str=hello -i . --generic_top vlogparam_bool=1 --generic_top vlogparam_int=42 --generic_top vlogparam_str=hello --generic_top generic_bool=1 --generic_top generic_int=42 --generic_top generic_str=hello some xelab_options 2 | -------------------------------------------------------------------------------- /tests/test_xsim/mfc/xsim.cmd: -------------------------------------------------------------------------------- 1 | -R a few xsim_options test_xsim_0 --testplusarg plusarg_bool=True --testplusarg plusarg_int=42 --testplusarg plusarg_str=hello 2 | -------------------------------------------------------------------------------- /tests/test_xsim/test_xsim_0.prj: -------------------------------------------------------------------------------- 1 | sv work sv_file.sv 2 | verilog work vlog_file.v 3 | verilog work vlog_with_define.v 4 | verilog work vlog05_file.v 5 | vhdl work vhdl_file.vhd 6 | vhdl libx vhdl_lfile 7 | vhdl2008 work vhdl2008_file 8 | sv work another_sv_file.sv 9 | -------------------------------------------------------------------------------- /tests/test_xsim/xelab.cmd: -------------------------------------------------------------------------------- 1 | top_module -prj test_xsim_0.prj -snapshot test_xsim_0 --define vlogdefine_bool=1 --define vlogdefine_int=42 --define vlogdefine_str=hello -i . --generic_top vlogparam_bool=1 --generic_top vlogparam_int=42 --generic_top vlogparam_str=hello --generic_top generic_bool=1 --generic_top generic_int=42 --generic_top generic_str=hello some xelab_options 2 | -------------------------------------------------------------------------------- /tests/test_xsim/xsim.cmd: -------------------------------------------------------------------------------- 1 | -R a few xsim_options test_xsim_0 --testplusarg plusarg_bool=True --testplusarg plusarg_int=42 --testplusarg plusarg_str=hello 2 | -------------------------------------------------------------------------------- /tests/test_yosys.py: -------------------------------------------------------------------------------- 1 | from .edalize_common import make_edalize_test 2 | 3 | 4 | def test_symbiyosys(make_edalize_test): 5 | output_names = { 6 | "default_output_name": { 7 | "arch": "ice40", 8 | }, 9 | "custom_output_name": {"arch": "ice40", "output_name": "test.json"}, 10 | } 11 | 12 | for test_name, tool_options in output_names.items(): 13 | tf = make_edalize_test( 14 | "yosys", 15 | param_types=["vlogdefine", "vlogparam"], 16 | tool_options=tool_options, 17 | ref_dir=test_name, 18 | ) 19 | 20 | tf.backend.configure() 21 | tf.compare_files(["Makefile"]) 22 | -------------------------------------------------------------------------------- /tests/test_yosys/custom_output_name/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: test.json 4 | 5 | test.json: edalize_yosys_template.tcl 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/test_yosys/default_output_name/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: test_yosys_0.blif 4 | 5 | test_yosys_0.blif: edalize_yosys_template.tcl 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/efinity/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: outflow/design.bit 4 | 5 | outflow/design.bit: sdc_file sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile vhdl_file.vhd vhdl_lfile vhdl2008_file another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) env EFXPT_HOME=path/to/efinity/intallation/pt EFXPGM_HOME=path/to/efinity/intallation/pgm path/to/efinity/intallation/bin/python3 path/to/efinity/intallation/scripts/efx_run.py --prj design.xml --flow compile 7 | -------------------------------------------------------------------------------- /tests/tools/gowin/edalize_gowin_template.tcl: -------------------------------------------------------------------------------- 1 | set_device dummy_part 2 | 3 | 4 | add_file -type sdc "sdc_file" 5 | add_file -type verilog "sv_file.sv" 6 | source tcl_file.tcl 7 | add_file -type verilog "vlog_file.v" 8 | add_file -type verilog "vlog_with_define.v" 9 | add_file -type verilog "vlog_incfile" 10 | add_file -type VHDL_FILE "vhdl_file.vhd" 11 | add_file -type VHDL_FILE "vhdl_lfile" 12 | set_file_prop -lib libx "vhdl_lfile" 13 | add_file -type verilog "another_sv_file.sv" 14 | 15 | set_option -top_module top_module 16 | set_option -vhdl_std vhd2008 17 | set_option -verilog_std sysv2017 18 | 19 | set_option some 20 | set_option gowin 21 | set_option options 22 | 23 | 24 | run syn 25 | run pnr -------------------------------------------------------------------------------- /tests/tools/gowin/minimal/edalize_gowin_template.tcl: -------------------------------------------------------------------------------- 1 | set_device dummy_part 2 | 3 | 4 | add_file -type sdc "sdc_file" 5 | add_file -type verilog "sv_file.sv" 6 | source tcl_file.tcl 7 | add_file -type verilog "vlog_file.v" 8 | add_file -type verilog "vlog_with_define.v" 9 | add_file -type verilog "vlog_incfile" 10 | add_file -type VHDL_FILE "vhdl_file.vhd" 11 | add_file -type VHDL_FILE "vhdl_lfile" 12 | set_file_prop -lib libx "vhdl_lfile" 13 | add_file -type verilog "another_sv_file.sv" 14 | 15 | set_option -top_module top_module 16 | set_option -vhdl_std vhd2008 17 | set_option -verilog_std sysv2017 18 | 19 | 20 | 21 | run syn 22 | run pnr -------------------------------------------------------------------------------- /tests/tools/icarus/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design 4 | 5 | design: sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv design.scr 6 | $(EDALIZE_LAUNCHER) iverilog -stop_module -c design.scr -o design a few iverilog options 7 | 8 | run: design 9 | $(EDALIZE_LAUNCHER) vvp -n -M. some vvp options design -fst $(EXTRA_OPTIONS) 10 | -------------------------------------------------------------------------------- /tests/tools/icarus/design.scr: -------------------------------------------------------------------------------- 1 | +define+vlogdefine_bool=1 2 | +define+vlogdefine_int=42 3 | +define+vlogdefine_str=hello 4 | +parameter+top_module.vlogparam_bool=1 5 | +parameter+top_module.vlogparam_int=42 6 | +parameter+top_module.vlogparam_str="hello" 7 | timescale.v 8 | +incdir+. 9 | sv_file.sv 10 | vlog_file.v 11 | vlog_with_define.v 12 | vlog05_file.v 13 | another_sv_file.sv 14 | -------------------------------------------------------------------------------- /tests/tools/icarus/multitop/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design 4 | 5 | design: sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv design.scr 6 | $(EDALIZE_LAUNCHER) iverilog -stop1 -stop2 -c design.scr -o design 7 | 8 | run: design 9 | $(EDALIZE_LAUNCHER) vvp -n -M. design -fst $(EXTRA_OPTIONS) 10 | -------------------------------------------------------------------------------- /tests/tools/icarus/multitop/design.scr: -------------------------------------------------------------------------------- 1 | +define+vlogdefine_bool=1 2 | +define+vlogdefine_int=42 3 | +define+vlogdefine_str=hello 4 | +parameter+top1.vlogparam_bool=1 5 | +parameter+top2.vlogparam_bool=1 6 | +parameter+top1.vlogparam_int=42 7 | +parameter+top2.vlogparam_int=42 8 | +parameter+top1.vlogparam_str="hello" 9 | +parameter+top2.vlogparam_str="hello" 10 | +incdir+. 11 | sv_file.sv 12 | vlog_file.v 13 | vlog_with_define.v 14 | vlog05_file.v 15 | another_sv_file.sv 16 | -------------------------------------------------------------------------------- /tests/tools/icepack/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: asc_file.bin 4 | 5 | asc_file.bin: asc_file.asc 6 | $(EDALIZE_LAUNCHER) icepack asc_file.asc asc_file.bin 7 | -------------------------------------------------------------------------------- /tests/tools/vcs/2stage_basic/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design 4 | 5 | design: vlog_incfile sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v another_sv_file.sv vcs.f parameters.txt 6 | $(EDALIZE_LAUNCHER) vcs -full64 -o design -file vcs.f -parameters parameters.txt sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v another_sv_file.sv 7 | 8 | run: 9 | $(EDALIZE_LAUNCHER) ./design $(EXTRA_OPTIONS) and some run options 10 | -------------------------------------------------------------------------------- /tests/tools/vcs/2stage_basic/parameters.txt: -------------------------------------------------------------------------------- 1 | assign 1 vlogparam_bool 2 | assign 42 vlogparam_int 3 | assign "hello" vlogparam_str 4 | -------------------------------------------------------------------------------- /tests/tools/vcs/2stage_basic/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | WORK > DEFAULT 2 | DEFAULT : ./work 3 | -------------------------------------------------------------------------------- /tests/tools/vcs/2stage_basic/vcs.f: -------------------------------------------------------------------------------- 1 | -top top_module -sverilog some vcs options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=""hello"" +incdir+. 2 | -------------------------------------------------------------------------------- /tests/tools/vcs/2stage_minimal/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design 4 | 5 | design: vlog_incfile sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v another_sv_file.sv vcs.f parameters.txt 6 | $(EDALIZE_LAUNCHER) vcs -full64 -o design -file vcs.f -parameters parameters.txt sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v another_sv_file.sv 7 | 8 | run: 9 | $(EDALIZE_LAUNCHER) ./design $(EXTRA_OPTIONS) 10 | -------------------------------------------------------------------------------- /tests/tools/vcs/2stage_minimal/parameters.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/edalize/1eedb7f726d1899465da30363763ea8c93d074af/tests/tools/vcs/2stage_minimal/parameters.txt -------------------------------------------------------------------------------- /tests/tools/vcs/2stage_minimal/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | WORK > DEFAULT 2 | DEFAULT : ./work 3 | -------------------------------------------------------------------------------- /tests/tools/vcs/2stage_minimal/vcs.f: -------------------------------------------------------------------------------- 1 | -top top_module -sverilog +incdir+. 2 | -------------------------------------------------------------------------------- /tests/tools/vcs/basic/libx.f: -------------------------------------------------------------------------------- 1 | also vhdlan options 2 | -------------------------------------------------------------------------------- /tests/tools/vcs/basic/parameters.txt: -------------------------------------------------------------------------------- 1 | assign 1 vlogparam_bool 2 | assign 42 vlogparam_int 3 | assign "hello" vlogparam_str 4 | -------------------------------------------------------------------------------- /tests/tools/vcs/basic/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | WORK > DEFAULT 2 | DEFAULT : ./work 3 | work_1 : ./work_1.workdir 4 | work_2 : ./work_2.workdir 5 | libx : ./libx.workdir 6 | -------------------------------------------------------------------------------- /tests/tools/vcs/basic/vcs.f: -------------------------------------------------------------------------------- 1 | -top top_module some vcs options 2 | -------------------------------------------------------------------------------- /tests/tools/vcs/basic/work.f: -------------------------------------------------------------------------------- 1 | -sverilog a few vlogan options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=""hello"" +incdir+. 2 | -------------------------------------------------------------------------------- /tests/tools/vcs/basic/work_1.f: -------------------------------------------------------------------------------- 1 | -sverilog a few vlogan options +define+vlogdefine_bool=1 +define+vlogdefine_int=42 +define+vlogdefine_str=""hello"" +define+FD_KEY=""FD_VAL"" +incdir+. 2 | -------------------------------------------------------------------------------- /tests/tools/vcs/basic/work_2.f: -------------------------------------------------------------------------------- 1 | also vhdlan options 2 | -------------------------------------------------------------------------------- /tests/tools/vcs/minimal/libx.f: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /tests/tools/vcs/minimal/parameters.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/edalize/1eedb7f726d1899465da30363763ea8c93d074af/tests/tools/vcs/minimal/parameters.txt -------------------------------------------------------------------------------- /tests/tools/vcs/minimal/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | WORK > DEFAULT 2 | DEFAULT : ./work 3 | work_1 : ./work_1.workdir 4 | work_2 : ./work_2.workdir 5 | libx : ./libx.workdir 6 | -------------------------------------------------------------------------------- /tests/tools/vcs/minimal/vcs.f: -------------------------------------------------------------------------------- 1 | -top top_module 2 | -------------------------------------------------------------------------------- /tests/tools/vcs/minimal/work.f: -------------------------------------------------------------------------------- 1 | -sverilog +incdir+. 2 | -------------------------------------------------------------------------------- /tests/tools/vcs/minimal/work_1.f: -------------------------------------------------------------------------------- 1 | -sverilog +define+FD_KEY=""FD_VAL"" +incdir+. 2 | -------------------------------------------------------------------------------- /tests/tools/vcs/minimal/work_2.f: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /tests/tools/verilator/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: Vtop_module 4 | 5 | Vtop_module.mk: design.vc sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) verilator -f design.vc 7 | 8 | Vtop_module: Vtop_module.mk c_file.c cpp_file.cpp 9 | $(EDALIZE_LAUNCHER) make -f Vtop_module.mk a few make options 10 | -------------------------------------------------------------------------------- /tests/tools/verilator/design.vc: -------------------------------------------------------------------------------- 1 | --Mdir . 2 | --cc 3 | some 4 | verilator 5 | options 6 | +incdir+. 7 | -CFLAGS -I. 8 | sv_file.sv 9 | vlog_file.v 10 | vlog_with_define.v 11 | vlog05_file.v 12 | another_sv_file.sv 13 | --top-module top_module 14 | 15 | --exe 16 | c_file.c 17 | cpp_file.cpp 18 | -Gvlogparam_bool=1 19 | -Gvlogparam_int=42 20 | -Gvlogparam_str=\"hello\" 21 | -Dvlogdefine_bool=1 22 | -Dvlogdefine_int=42 23 | -Dvlogdefine_str=hello 24 | -------------------------------------------------------------------------------- /tests/tools/verilator/minimal/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: Vtop_module 4 | 5 | Vtop_module.mk: design.vc sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) verilator -f design.vc 7 | 8 | Vtop_module: Vtop_module.mk c_file.c cpp_file.cpp 9 | $(EDALIZE_LAUNCHER) make -f Vtop_module.mk 10 | -------------------------------------------------------------------------------- /tests/tools/verilator/minimal/design.vc: -------------------------------------------------------------------------------- 1 | --Mdir . 2 | --cc 3 | +incdir+. 4 | -CFLAGS -I. 5 | sv_file.sv 6 | vlog_file.v 7 | vlog_with_define.v 8 | vlog05_file.v 9 | another_sv_file.sv 10 | --top-module top_module 11 | 12 | --exe 13 | c_file.c 14 | cpp_file.cpp 15 | -Gvlogparam_bool=1 16 | -Gvlogparam_int=42 17 | -Gvlogparam_str=\"hello\" 18 | -Dvlogdefine_bool=1 19 | -Dvlogdefine_int=42 20 | -Dvlogdefine_str=hello 21 | -------------------------------------------------------------------------------- /tests/tools/vivado/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.bit 4 | 5 | design.xpr: design.tcl sdc_file sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile vhdl_file.vhd vhdl_lfile vhdl2008_file xci_file.xci xdc_file.xdc bootrom.mem another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) vivado -notrace -mode batch -source design.tcl 7 | 8 | design.v design.edn: design_synth.tcl design_netlist.tcl | design.xpr 9 | $(EDALIZE_LAUNCHER) vivado -notrace -mode batch -source design_synth.tcl design_netlist.tcl design.xpr 10 | 11 | synth: design.v design.edn 12 | 13 | design.bit: design_synth.tcl design_run.tcl | design.xpr 14 | $(EDALIZE_LAUNCHER) vivado -notrace -mode batch -source design_synth.tcl design_run.tcl design.xpr 15 | 16 | build-gui: design.xpr 17 | $(EDALIZE_LAUNCHER) vivado design.xpr 18 | 19 | pgm: design_pgm.tcl design.bit 20 | $(EDALIZE_LAUNCHER) vivado -quiet -nolog -notrace -mode batch -source design_pgm.tcl -tclargs design.bit 21 | -------------------------------------------------------------------------------- /tests/tools/vivado/design_netlist.tcl: -------------------------------------------------------------------------------- 1 | open_run synth_1 2 | write_edif [current_project].edn 3 | write_verilog [current_project].v 4 | -------------------------------------------------------------------------------- /tests/tools/vivado/design_synth.tcl: -------------------------------------------------------------------------------- 1 | set outdated [get_property NEEDS_REFRESH [get_runs synth_1]] 2 | set progress [get_property PROGRESS [get_runs synth_1]] 3 | 4 | if {$outdated || $progress != "100%"} { 5 | reset_runs synth_1 6 | launch_runs synth_1 7 | wait_on_run synth_1 8 | } 9 | #exit [regexp -nocase -- {synth_design (error|failed)} [get_property STATUS [get_runs synth_1]] match] 10 | -------------------------------------------------------------------------------- /tests/tools/vivado/tags/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.bit 4 | 5 | design.xpr: design.tcl sdc_file sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile vhdl_file.vhd vhdl_lfile vhdl2008_file xci_file.xci xdc_file.xdc bootrom.mem another_sv_file.sv testbench.v 6 | $(EDALIZE_LAUNCHER) vivado -notrace -mode batch -source design.tcl 7 | 8 | design.v design.edn: design_synth.tcl design_netlist.tcl | design.xpr 9 | $(EDALIZE_LAUNCHER) vivado -notrace -mode batch -source design_synth.tcl design_netlist.tcl design.xpr 10 | 11 | synth: design.v design.edn 12 | 13 | design.bit: design_synth.tcl design_run.tcl | design.xpr 14 | $(EDALIZE_LAUNCHER) vivado -notrace -mode batch -source design_synth.tcl design_run.tcl design.xpr 15 | 16 | build-gui: design.xpr 17 | $(EDALIZE_LAUNCHER) vivado design.xpr 18 | 19 | pgm: design_pgm.tcl design.bit 20 | $(EDALIZE_LAUNCHER) vivado -quiet -nolog -notrace -mode batch -source design_pgm.tcl -tclargs design.bit 21 | -------------------------------------------------------------------------------- /tests/tools/vivado/tags/design_netlist.tcl: -------------------------------------------------------------------------------- 1 | open_run synth_1 2 | write_edif [current_project].edn 3 | write_verilog [current_project].v 4 | -------------------------------------------------------------------------------- /tests/tools/vivado/tags/design_synth.tcl: -------------------------------------------------------------------------------- 1 | set outdated [get_property NEEDS_REFRESH [get_runs synth_1]] 2 | set progress [get_property PROGRESS [get_runs synth_1]] 3 | 4 | if {$outdated || $progress != "100%"} { 5 | reset_runs synth_1 6 | launch_runs synth_1 7 | wait_on_run synth_1 8 | } 9 | #exit [regexp -nocase -- {synth_design (error|failed)} [get_property STATUS [get_runs synth_1]] match] 10 | -------------------------------------------------------------------------------- /tests/tools/yosys/ecp5-blif/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.blif 4 | 5 | design.blif: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/ecp5-blif/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_ecp5 some yosys synth options -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/ecp5-blif/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_blif $name.blif 19 | -------------------------------------------------------------------------------- /tests/tools/yosys/ecp5-edif/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.edif 4 | 5 | design.edif: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/ecp5-edif/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_ecp5 some yosys synth options -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/ecp5-edif/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_edif $name.edif 19 | -------------------------------------------------------------------------------- /tests/tools/yosys/ecp5-json/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.json 4 | 5 | design.json: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/ecp5-json/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_ecp5 some yosys synth options -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/ecp5-json/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_json $name.json 19 | -------------------------------------------------------------------------------- /tests/tools/yosys/ecp5-verilog/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.v 4 | 5 | design.v: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/ecp5-verilog/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_ecp5 some yosys synth options -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/ecp5-verilog/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_verilog $name.v 19 | -------------------------------------------------------------------------------- /tests/tools/yosys/ice40-blif/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.blif 4 | 5 | design.blif: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/ice40-blif/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_ice40 some yosys synth options -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/ice40-blif/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_blif $name.blif 19 | -------------------------------------------------------------------------------- /tests/tools/yosys/ice40-edif/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.edif 4 | 5 | design.edif: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/ice40-edif/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_ice40 some yosys synth options -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/ice40-edif/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_edif $name.edif 19 | -------------------------------------------------------------------------------- /tests/tools/yosys/ice40-json/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.json 4 | 5 | design.json: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/ice40-json/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_ice40 some yosys synth options -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/ice40-json/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_json $name.json 19 | -------------------------------------------------------------------------------- /tests/tools/yosys/ice40-verilog/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.v 4 | 5 | design.v: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/ice40-verilog/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_ice40 some yosys synth options -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/ice40-verilog/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_verilog $name.v 19 | -------------------------------------------------------------------------------- /tests/tools/yosys/minimal/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.blif 4 | 5 | design.blif: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/minimal/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_ice40 -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/minimal/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_blif $name.blif 19 | -------------------------------------------------------------------------------- /tests/tools/yosys/template/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.blif 4 | 5 | design.blif: some_file.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl some_file.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/template/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_ice40 -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/xilinx-blif/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.blif 4 | 5 | design.blif: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/xilinx-blif/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_xilinx some yosys synth options -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/xilinx-blif/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_blif $name.blif 19 | -------------------------------------------------------------------------------- /tests/tools/yosys/xilinx-edif/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.edif 4 | 5 | design.edif: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/xilinx-edif/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_xilinx some yosys synth options -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/xilinx-edif/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_edif -pvector bra $name.edif 19 | -------------------------------------------------------------------------------- /tests/tools/yosys/xilinx-json/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.json 4 | 5 | design.json: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/xilinx-json/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_xilinx some yosys synth options -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/xilinx-json/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_json $name.json 19 | -------------------------------------------------------------------------------- /tests/tools/yosys/xilinx-verilog/Makefile: -------------------------------------------------------------------------------- 1 | #Auto generated by Edalize 2 | 3 | all: design.v 4 | 5 | design.v: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv 6 | $(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl' 7 | -------------------------------------------------------------------------------- /tests/tools/yosys/xilinx-verilog/edalize_yosys_procs.tcl: -------------------------------------------------------------------------------- 1 | proc load_plugins {} { 2 | } 3 | 4 | proc read_files {} { 5 | read_verilog -sv {sv_file.sv} 6 | source {tcl_file.tcl} 7 | read_verilog {vlog_file.v} 8 | read_verilog {vlog_with_define.v} 9 | read_verilog {vlog05_file.v} 10 | read_verilog -sv {another_sv_file.sv} 11 | } 12 | 13 | proc set_defines {} { 14 | set defines {{vlogdefine_bool True} {vlogdefine_int 42} {vlogdefine_str hello}} 15 | 16 | foreach d ${defines} { 17 | set key [lindex $d 0] 18 | set val [lindex $d 1] 19 | verilog_defines "-D$key=$val" 20 | }} 21 | 22 | proc set_incdirs {} { 23 | verilog_defaults -add -I.} 24 | 25 | proc set_params {} { 26 | chparam -set vlogparam_bool 1 top_module 27 | chparam -set vlogparam_int 42 top_module 28 | chparam -set vlogparam_str {"hello"} top_module} 29 | 30 | proc synth {top} { 31 | synth_xilinx some yosys synth options -top $top 32 | } 33 | 34 | set top top_module 35 | set name design 36 | -------------------------------------------------------------------------------- /tests/tools/yosys/xilinx-verilog/edalize_yosys_template.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | source edalize_yosys_procs.tcl 3 | load_plugins 4 | yosys -import 5 | 6 | verilog_defaults -push 7 | verilog_defaults -add -defer 8 | 9 | set_defines 10 | set_incdirs 11 | read_files 12 | set_params 13 | 14 | verilog_defaults -pop 15 | 16 | synth $top 17 | 18 | write_verilog $name.v 19 | -------------------------------------------------------------------------------- /tox.ini: -------------------------------------------------------------------------------- 1 | [tox] 2 | envlist = py3 3 | 4 | [testenv] 5 | deps = 6 | pytest 7 | pandas<=2.0.3 8 | extras = reporting 9 | commands = pytest {posargs} 10 | passenv = GOLDEN_RUN 11 | --------------------------------------------------------------------------------