├── .github └── workflows │ └── ci.yml ├── LICENSE ├── README.md ├── data ├── gf180.tcl ├── nexys_a7.xdc ├── openlane_common.tcl └── sky130.tcl ├── doc ├── subservient.png ├── subservient_core.png ├── subservient_externals.png ├── subservient_fpga.png └── subservient_tb.png ├── el_docker_gf180 ├── rtl ├── subservient.v ├── subservient_core.v ├── subservient_debug_switch.v ├── subservient_fpga.v ├── subservient_generic_ram.v ├── subservient_gpio.v ├── subservient_nexys_a7_clock_gen.v ├── subservient_ram.v └── subservient_rf_ram_if.v ├── subservient.core ├── sw ├── Makefile ├── blinky.S ├── blinky.hex ├── hello.S ├── hello.hex └── link.ld └── tb ├── subservient_fpga_clock_gen_sim.v ├── subservient_fpga_tb.cpp ├── subservient_tb.v └── uart_decoder.v /.github/workflows/ci.yml: -------------------------------------------------------------------------------- 1 | name: build-openlane 2 | 3 | on: 4 | push: 5 | workflow_dispatch: # Allow manual triggering 6 | 7 | jobs: 8 | build-openlane-sky130: 9 | runs-on: ubuntu-latest 10 | env: 11 | REPO : subservient 12 | VLNV : subservient 13 | steps: 14 | - name: Checkout repo 15 | uses: actions/checkout@v3 16 | with: 17 | path: subservient 18 | - run: echo "EDALIZE_LAUNCHER=el_docker" >> $GITHUB_ENV 19 | - run: pip3 install fusesoc 20 | - run: fusesoc library add https://github.com/olofk/serv 21 | - run: fusesoc library add $GITHUB_WORKSPACE/$REPO 22 | - run: fusesoc --verbose run --target=sky130 $VLNV 23 | 24 | build-openlane-gf180: 25 | runs-on: ubuntu-latest 26 | env: 27 | REPO : subservient 28 | VLNV : subservient 29 | steps: 30 | - name: Checkout repo 31 | uses: actions/checkout@v2 32 | with: 33 | path: subservient 34 | - run: echo "EDALIZE_LAUNCHER=$(realpath subservient/el_docker_gf180)" >> $GITHUB_ENV 35 | - run: pip3 install fusesoc 36 | - run: fusesoc library add https://github.com/olofk/serv 37 | - run: fusesoc library add $GITHUB_WORKSPACE/$REPO 38 | - run: fusesoc --verbose run --target=gf180 $VLNV 39 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | 203 | 204 | --------------------------------------------------------------------------- 205 | Note: 206 | Individual files contain the following tag instead of the full license text. 207 | 208 | SPDX-License-Identifier: Apache-2.0 209 | 210 | This enables machine processing of license information based on the SPDX 211 | License Identifiers that are here available: http://spdx.org/licenses/ -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # subservient 2 | 3 | Small SERV-based SoC primarily for OpenMPW tapeout 4 | 5 | ## Introduction 6 | 7 | Subservient is a small SoClet around the award-winning SERV, the world's smallest RISC-V CPU intended to be used for ASIC implementations. The SoClet exposes a port intended to be connected to be connected to an SRAM used for both the register file and data/instruction memory and a GPIO pin. The memory is expected to be initialized with a valid application upon release of Subservient reset. 8 | 9 | ![Interfaces](doc/subservient_externals.png) 10 | 11 | ## Architecture 12 | 13 | ### Top-level 14 | ![Top level](doc/subservient.png) 15 | 16 | The top-level of Subservient consists of the subservient_core component which contains all the vital SoC infrastructure, and the standard peripheral controllers, currently only consisting of GPIO. This is a convenience wrapper for users who are happy with the standard set of peripherals. 17 | 18 | ### Subservient core 19 | ![Core](doc/subservient_core.png) 20 | 21 | Subservient core contains SERV and the necessary components to use a single SRAM for SERV's register file, data and instruction memories, all wrapped in the [Servile](https://serv.readthedocs.io/en/latest/reservoir.html#servile-convenience-wrapper) helper component. 22 | 23 | ### Testbench 24 | 25 | ![Core](doc/subservient_tb.png) 26 | 27 | Subservient comes with a simple testbench that allows running programs on the simulated SoC and monitor its outputs either as a GPIO or as a UART. Memory is preloaded from a verilog hex file. 28 | 29 | ## Getting started 30 | 31 | Subservient uses [FuseSoC](https://github.com/olofk/fusesoc) to handle its dependencies and run the SoC through different tool flows. 32 | 33 | 1. Install FuseSoC `pip3 install fusesoc` (Requires at least FuseSoC version 2.4) 34 | 2. Create an empty workspace directory and enter it `mkdir workspace && cd workspace` 35 | 3. From within your workspace directory add the required FuseSoC libraries 36 | - Base library `fusesoc library add https://github.com/fusesoc/fusesoc-cores` 37 | - SERV `fusesoc library add https://github.com/olofk/serv` 38 | - Subservient `fusesoc library add https://github.com/olofk/subservient` 39 | 4. FuseSoC should be able to see the subservient SoC. Verify this by running `fusesoc core show subservient` 40 | 5. We can now run a simulation with the simulator we have at hand. `fusesoc run --target=sim_hello --tool=icarus subservient --timeout=4000000` will launch a simulation using Icarus Verilog and printing out a text string twice before exiting. More information about simulations can be found in the simulation section 41 | 42 | ## FPGA 43 | 44 | ![Core](doc/subservient_fpga.png) 45 | 46 | Subservient can be implemented on an FPGA board for testing. Currently supported board is Nexys A7. For FPGA builds, the memory is expected to be preloaded with an application to run. To build Subservient for the Nexys A7 board, run: 47 | 48 | fusesoc run --target=nexys_a7 subservient 49 | 50 | ## Simulation 51 | 52 | Subservient can be run in a simulator. To use the default simulator (Icarus Verilog) with a preloaded hello world application run: 53 | 54 | fusesoc run --target=sim_hello subservient 55 | 56 | Other simulators can be used with the `--tool` option, e.g. 57 | 58 | fusesoc run --target=sim_hello --tool=modelsim subservient 59 | 60 | In order to run a custom application, use the `sim` target and supply an application as a Verilog hex file with the `--firmware` option, e.g.: 61 | 62 | fusesoc run --target=sim subservient --firmware=path/to/blinky.hex 63 | 64 | ## Acknowledgements 65 | 66 | [This project](https://nlnet.nl/project/Edalize-ASIC/) has been primarily funded through the [NGI0 PET Fund](https://nlnet.nl/PET/), a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 825310. 67 | 68 | -------------------------------------------------------------------------------- /data/gf180.tcl: -------------------------------------------------------------------------------- 1 | set ::env(CLOCK_PERIOD) "20" 2 | set ::env(FP_CORE_UTIL) 40 3 | set ::env(PL_TARGET_DENSITY) 0.45 4 | -------------------------------------------------------------------------------- /data/nexys_a7.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports i_clk]; 2 | set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports i_rst]; 3 | set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports q] 4 | 5 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk]; 6 | -------------------------------------------------------------------------------- /data/openlane_common.tcl: -------------------------------------------------------------------------------- 1 | set ::env(CLOCK_PORT) "i_clk" 2 | -------------------------------------------------------------------------------- /data/sky130.tcl: -------------------------------------------------------------------------------- 1 | set ::env(CLOCK_PERIOD) "10" 2 | -------------------------------------------------------------------------------- /doc/subservient.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/subservient/0989597f7a229bd4ae0f7400f7bf6ab483c66205/doc/subservient.png -------------------------------------------------------------------------------- /doc/subservient_core.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/subservient/0989597f7a229bd4ae0f7400f7bf6ab483c66205/doc/subservient_core.png -------------------------------------------------------------------------------- /doc/subservient_externals.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/subservient/0989597f7a229bd4ae0f7400f7bf6ab483c66205/doc/subservient_externals.png -------------------------------------------------------------------------------- /doc/subservient_fpga.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/subservient/0989597f7a229bd4ae0f7400f7bf6ab483c66205/doc/subservient_fpga.png -------------------------------------------------------------------------------- /doc/subservient_tb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/olofk/subservient/0989597f7a229bd4ae0f7400f7bf6ab483c66205/doc/subservient_tb.png -------------------------------------------------------------------------------- /el_docker_gf180: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | import os 3 | import shutil 4 | import subprocess 5 | import sys 6 | import logging 7 | import shlex 8 | 9 | logger = logging.getLogger(__name__) 10 | symbiflow_init = "bash -lec {}" 11 | 12 | # fmt: off 13 | containers = [ 14 | {'tool': 'flow.tcl', 'image': 'edalize/openlane-gf180mcu:2022.09.16', 'init': '', 'vendor': '', 'part': ''}, 15 | ] 16 | # fmt: on 17 | 18 | tool = sys.argv[1] 19 | toolname = os.path.basename(tool) 20 | 21 | # If it's in the container list, wrap with Docker 22 | if [c for c in containers if c["tool"] == toolname]: 23 | (build_root, work) = os.path.split(os.getcwd()) 24 | dockerEnv = "" 25 | for k in os.environ: 26 | dockerEnv = dockerEnv + "-e " + k + "=" " + os.environ[k] + " " " 27 | 28 | runtool = os.path.relpath(os.path.realpath(tool), os.getcwd()) 29 | for c in containers: 30 | # Vendor neutral 31 | if c["tool"] == toolname and c["vendor"] == "": 32 | image = c["image"] 33 | init = c["init"] 34 | break 35 | # Vendor specific toolchain 36 | elif ( 37 | c["tool"] == toolname 38 | and c["vendor"] == os.environ.get("EDALIZE_VENDOR") 39 | and os.environ.get("EDALIZE_PART") in c["part"] 40 | ): 41 | image = c["image"] 42 | init = c["init"] 43 | break 44 | else: 45 | image = "" 46 | init = "" 47 | 48 | if image: 49 | logger.info("INFO: Will use image '{}' with init '{}'".format(image, init)) 50 | else: 51 | logger.error("ERROR: Tool {} not found in container list.".format(toolname)) 52 | exit(1) 53 | 54 | prefix = [ 55 | "docker", 56 | "run", 57 | "--rm", 58 | "-v", 59 | build_root + ":/src", 60 | # '-e', dockerEnv, 61 | "-u", 62 | f"{os.getuid()}:{os.getgid()}", 63 | "-w", 64 | "/src/" + work, 65 | image, 66 | ] 67 | if init: 68 | c = init.format(shlex.quote(runtool + " " + shlex.join(sys.argv[2:]))) 69 | elif tool == "verilator": 70 | c = shlex.join(sys.argv[2:]) 71 | else: 72 | c = runtool + " " + shlex.join(sys.argv[2:]) 73 | cmd = prefix + shlex.split(c) 74 | # Otherwise, run it locally 75 | else: 76 | cmd = sys.argv[1:] 77 | 78 | logger.info("INFO: Wrapper Command: ".format(" ".join(cmd))) 79 | sys.exit(subprocess.call(cmd, env=os.environ)) 80 | -------------------------------------------------------------------------------- /rtl/subservient.v: -------------------------------------------------------------------------------- 1 | /* 2 | * subservient.v : Toplevel for the subservient SoC 3 | * 4 | * SPDX-FileCopyrightText: 2021 Olof Kindgren 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | 8 | `default_nettype none 9 | module subservient 10 | #(//Memory parameters 11 | parameter memsize = 512, 12 | parameter aw = $clog2(memsize), 13 | //Enable CSR + interrupts 14 | parameter WITH_CSR = 0) 15 | ( 16 | input wire i_clk, 17 | input wire i_rst, 18 | 19 | //SRAM interface 20 | output wire [aw-1:0] o_sram_waddr, 21 | output wire [7:0] o_sram_wdata, 22 | output wire o_sram_wen, 23 | output wire [aw-1:0] o_sram_raddr, 24 | input wire [7:0] i_sram_rdata, 25 | output wire o_sram_ren, 26 | 27 | //External I/O 28 | output wire o_gpio); 29 | 30 | wire [31:0] wb_core_adr; 31 | wire [31:0] wb_core_dat; 32 | wire [3:0] wb_core_sel; 33 | wire wb_core_we; 34 | wire wb_core_stb; 35 | wire [31:0] wb_core_rdt; 36 | wire wb_core_ack; 37 | 38 | wire wb_gpio_rdt; 39 | assign wb_core_rdt = {31'd0, wb_gpio_rdt}; 40 | 41 | subservient_gpio gpio 42 | (.i_wb_clk (i_clk), 43 | .i_wb_rst (i_rst), 44 | .i_wb_dat (wb_core_dat[0]), 45 | .i_wb_we (wb_core_we), 46 | .i_wb_stb (wb_core_stb), 47 | .o_wb_rdt (wb_gpio_rdt), 48 | .o_wb_ack (wb_core_ack), 49 | .o_gpio (o_gpio)); 50 | 51 | subservient_core 52 | #(.memsize (memsize), 53 | .WITH_CSR (WITH_CSR)) 54 | core 55 | (.i_clk (i_clk), 56 | .i_rst (i_rst), 57 | .i_timer_irq (1'b0), 58 | 59 | //SRAM interface 60 | .o_sram_waddr (o_sram_waddr), 61 | .o_sram_wdata (o_sram_wdata), 62 | .o_sram_wen (o_sram_wen), 63 | .o_sram_raddr (o_sram_raddr), 64 | .i_sram_rdata (i_sram_rdata), 65 | .o_sram_ren (o_sram_ren), 66 | 67 | //Peripheral interface 68 | .o_wb_adr (wb_core_adr), 69 | .o_wb_dat (wb_core_dat), 70 | .o_wb_sel (wb_core_sel), 71 | .o_wb_we (wb_core_we) , 72 | .o_wb_stb (wb_core_stb), 73 | .i_wb_rdt (wb_core_rdt), 74 | .i_wb_ack (wb_core_ack)); 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /rtl/subservient_core.v: -------------------------------------------------------------------------------- 1 | /* 2 | * subservient_core.v : Toplevel for the subservient SoC without peripherals 3 | * 4 | * SPDX-FileCopyrightText: 2021 Olof Kindgren 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | 8 | `default_nettype none 9 | module subservient_core 10 | #(//Memory parameters 11 | parameter memsize = 512, 12 | parameter RESET_STRATEGY = "MINI", 13 | parameter WITH_CSR = 1, 14 | parameter aw = $clog2(memsize)) 15 | ( 16 | input wire i_clk, 17 | input wire i_rst, 18 | input wire i_timer_irq, 19 | 20 | //SRAM interface 21 | output wire [aw-1:0] o_sram_waddr, 22 | output wire [7:0] o_sram_wdata, 23 | output wire o_sram_wen, 24 | output wire [aw-1:0] o_sram_raddr, 25 | input wire [7:0] i_sram_rdata, 26 | output wire o_sram_ren, 27 | 28 | //Periperal interface 29 | output wire [31:0] o_wb_adr, 30 | output wire [31:0] o_wb_dat, 31 | output wire [3:0] o_wb_sel, 32 | output wire o_wb_we , 33 | output wire o_wb_stb, 34 | input wire [31:0] i_wb_rdt, 35 | input wire i_wb_ack); 36 | 37 | localparam regs = 32+WITH_CSR*4; 38 | 39 | localparam rf_width = 8; 40 | 41 | wire [31:0] wb_mem_adr; 42 | wire [31:0] wb_mem_dat; 43 | wire [3:0] wb_mem_sel; 44 | wire wb_mem_we; 45 | wire wb_mem_stb; 46 | wire [31:0] wb_mem_rdt; 47 | wire wb_mem_ack; 48 | 49 | wire [6+WITH_CSR:0] rf_waddr; 50 | wire [rf_width-1:0] rf_wdata; 51 | wire rf_wen; 52 | wire [6+WITH_CSR:0] rf_raddr; 53 | wire [rf_width-1:0] rf_rdata; 54 | wire rf_ren; 55 | 56 | servile_rf_mem_if 57 | #(.depth (memsize), 58 | .rf_regs (regs)) 59 | rf_mem_if 60 | (// Wishbone interface 61 | .i_clk (i_clk), 62 | .i_rst (i_rst), 63 | 64 | .i_waddr (rf_waddr), 65 | .i_wdata (rf_wdata), 66 | .i_wen (rf_wen), 67 | .i_raddr (rf_raddr), 68 | .o_rdata (rf_rdata), 69 | .i_ren (rf_ren), 70 | 71 | .o_sram_waddr (o_sram_waddr), 72 | .o_sram_wdata (o_sram_wdata), 73 | .o_sram_wen (o_sram_wen), 74 | .o_sram_raddr (o_sram_raddr), 75 | .i_sram_rdata (i_sram_rdata), 76 | .o_sram_ren (o_sram_ren), 77 | 78 | .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]), 79 | .i_wb_stb (wb_mem_stb), 80 | .i_wb_we (wb_mem_we) , 81 | .i_wb_sel (wb_mem_sel), 82 | .i_wb_dat (wb_mem_dat), 83 | .o_wb_rdt (wb_mem_rdt), 84 | .o_wb_ack (wb_mem_ack)); 85 | 86 | servile 87 | #(.reset_strategy (RESET_STRATEGY), 88 | .rf_width (rf_width), 89 | .with_csr (WITH_CSR)) 90 | servile 91 | ( 92 | .i_clk (i_clk), 93 | .i_rst (i_rst), 94 | .i_timer_irq (i_timer_irq), 95 | //Memory interface 96 | .o_wb_mem_adr (wb_mem_adr), 97 | .o_wb_mem_dat (wb_mem_dat), 98 | .o_wb_mem_sel (wb_mem_sel), 99 | .o_wb_mem_we (wb_mem_we), 100 | .o_wb_mem_stb (wb_mem_stb), 101 | .i_wb_mem_rdt (wb_mem_rdt), 102 | .i_wb_mem_ack (wb_mem_ack), 103 | 104 | //Extension interface 105 | .o_wb_ext_adr (o_wb_adr), 106 | .o_wb_ext_dat (o_wb_dat), 107 | .o_wb_ext_sel (o_wb_sel), 108 | .o_wb_ext_we (o_wb_we), 109 | .o_wb_ext_stb (o_wb_stb), 110 | .i_wb_ext_rdt (i_wb_rdt), 111 | .i_wb_ext_ack (i_wb_ack), 112 | 113 | //RF IF 114 | .o_rf_waddr (rf_waddr), 115 | .o_rf_wdata (rf_wdata), 116 | .o_rf_wen (rf_wen), 117 | .o_rf_raddr (rf_raddr), 118 | .o_rf_ren (rf_ren), 119 | .i_rf_rdata (rf_rdata)); 120 | 121 | endmodule 122 | -------------------------------------------------------------------------------- /rtl/subservient_debug_switch.v: -------------------------------------------------------------------------------- 1 | /* 2 | * subservient_debug_switch.v : Wishbone debug switch for subservient SoC 3 | * 4 | * SPDX-FileCopyrightText: 2021 Olof Kindgren 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | 8 | module subservient_debug_switch 9 | (//Debug selector 10 | input wire i_debug_mode, 11 | 12 | //Debug interface 13 | input wire [31:0] i_wb_dbg_adr, 14 | input wire [31:0] i_wb_dbg_dat, 15 | input wire [3:0] i_wb_dbg_sel, 16 | input wire i_wb_dbg_we, 17 | input wire i_wb_dbg_stb, 18 | output wire [31:0] o_wb_dbg_rdt, 19 | output wire o_wb_dbg_ack, 20 | 21 | //Data bus interface towards CPU 22 | input wire [31:0] i_wb_dbus_adr, 23 | input wire [31:0] i_wb_dbus_dat, 24 | input wire [3:0] i_wb_dbus_sel, 25 | input wire i_wb_dbus_we, 26 | input wire i_wb_dbus_stb, 27 | output wire [31:0] o_wb_dbus_rdt, 28 | output wire o_wb_dbus_ack, 29 | 30 | //Data bus interface towards memory/peripherals 31 | output wire [31:0] o_wb_mux_adr, 32 | output wire [31:0] o_wb_mux_dat, 33 | output wire [3:0] o_wb_mux_sel, 34 | output wire o_wb_mux_we, 35 | output wire o_wb_mux_stb, 36 | input wire [31:0] i_wb_mux_rdt, 37 | input wire i_wb_mux_ack); 38 | 39 | assign o_wb_dbg_rdt = i_wb_mux_rdt; 40 | assign o_wb_dbg_ack = i_wb_mux_ack & i_debug_mode; 41 | 42 | assign o_wb_dbus_rdt = i_wb_mux_rdt; 43 | assign o_wb_dbus_ack = i_wb_mux_ack & !i_debug_mode; 44 | 45 | assign o_wb_mux_adr = i_debug_mode ? i_wb_dbg_adr : i_wb_dbus_adr; 46 | assign o_wb_mux_dat = i_debug_mode ? i_wb_dbg_dat : i_wb_dbus_dat; 47 | assign o_wb_mux_sel = i_debug_mode ? i_wb_dbg_sel : i_wb_dbus_sel; 48 | assign o_wb_mux_we = i_debug_mode ? i_wb_dbg_we : i_wb_dbus_we ; 49 | assign o_wb_mux_stb = i_debug_mode ? i_wb_dbg_stb : i_wb_dbus_stb; 50 | 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /rtl/subservient_fpga.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module subservient_fpga 3 | ( 4 | input wire i_clk, 5 | input wire i_rst, 6 | output wire q); 7 | 8 | parameter memfile = "hello.hex"; 9 | parameter memsize = 1024; 10 | localparam aw = $clog2(memsize); 11 | 12 | wire clk; 13 | wire rst; 14 | 15 | wire [aw-1:0] sram_waddr; 16 | wire [7:0] sram_wdata; 17 | wire sram_wen; 18 | wire [aw-1:0] sram_raddr; 19 | wire [7:0] sram_rdata; 20 | wire sram_ren; 21 | 22 | subservient_fpga_clock_gen clock_gen 23 | (.i_clk (i_clk), 24 | .i_rst (i_rst), 25 | .o_clk (clk), 26 | .o_rst (rst)); 27 | 28 | subservient_generic_ram 29 | #(.depth (memsize), 30 | .memfile (memfile)) 31 | memory 32 | (.i_clk (clk), 33 | .i_rst (rst), 34 | .i_waddr (sram_waddr), 35 | .i_wdata (sram_wdata), 36 | .i_wen (sram_wen), 37 | .i_raddr (sram_raddr), 38 | .o_rdata (sram_rdata), 39 | .i_ren (sram_ren)); 40 | 41 | subservient 42 | #(.memsize (memsize), 43 | .WITH_CSR (0)) 44 | dut 45 | (// Clock & reset 46 | .i_clk (clk), 47 | .i_rst (rst), 48 | 49 | //SRAM interface 50 | .o_sram_waddr (sram_waddr), 51 | .o_sram_wdata (sram_wdata), 52 | .o_sram_wen (sram_wen), 53 | .o_sram_raddr (sram_raddr), 54 | .i_sram_rdata (sram_rdata), 55 | .o_sram_ren (sram_ren), 56 | 57 | //Debug interface 58 | .i_debug_mode (1'b0), 59 | .i_wb_dbg_adr (32'd0), 60 | .i_wb_dbg_dat (32'd0), 61 | .i_wb_dbg_sel (4'd0), 62 | .i_wb_dbg_we (1'd0), 63 | .i_wb_dbg_stb (1'd0), 64 | .o_wb_dbg_rdt (), 65 | .o_wb_dbg_ack (), 66 | 67 | // External I/O 68 | .o_gpio (q)); 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /rtl/subservient_generic_ram.v: -------------------------------------------------------------------------------- 1 | module subservient_generic_ram 2 | #(parameter depth = 0, 3 | parameter aw = $clog2(depth), 4 | parameter memfile = "") 5 | (input wire i_clk, 6 | input wire i_rst, 7 | //SRAM interface 8 | input wire [aw-1:0] i_waddr, 9 | input wire [7:0] i_wdata, 10 | input wire i_wen, 11 | input wire [aw-1:0] i_raddr, 12 | output wire [7:0] o_rdata, 13 | input wire i_ren); 14 | 15 | reg [7:0] mem [0:depth-1] /* verilator public */; 16 | 17 | reg r0; 18 | 19 | reg [7:0] rdata; 20 | 21 | assign o_rdata = r0 ? 8'd0 : rdata; 22 | 23 | always @(posedge i_clk) 24 | r0 <= &i_raddr[aw-1:2]; 25 | 26 | always @(posedge i_clk) begin 27 | if (i_wen) mem[i_waddr] <= i_wdata; 28 | rdata <= i_ren ? mem[i_raddr] : 8'bx; 29 | end 30 | 31 | initial 32 | if(|memfile) begin 33 | $display("Preloading %m from %s", memfile); 34 | $readmemh(memfile, mem); 35 | end 36 | endmodule 37 | -------------------------------------------------------------------------------- /rtl/subservient_gpio.v: -------------------------------------------------------------------------------- 1 | /* 2 | * subservient_gpio.v : Single-bit GPIO for the subservient SoC 3 | * 4 | * SPDX-FileCopyrightText: 2021 Olof Kindgren 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | 8 | module subservient_gpio 9 | (input wire i_wb_clk, 10 | input wire i_wb_rst, 11 | input wire i_wb_dat, 12 | input wire i_wb_we, 13 | input wire i_wb_stb, 14 | output reg o_wb_rdt, 15 | output reg o_wb_ack, 16 | output reg o_gpio); 17 | 18 | always @(posedge i_wb_clk) begin 19 | o_wb_rdt <= o_gpio; 20 | if (i_wb_stb & i_wb_we) 21 | o_gpio <= i_wb_dat; 22 | o_wb_ack <= i_wb_stb & !o_wb_ack; 23 | 24 | if (i_wb_rst) begin 25 | o_wb_ack <= 1'b0; 26 | o_gpio <= 1'b0; 27 | end 28 | end 29 | endmodule 30 | -------------------------------------------------------------------------------- /rtl/subservient_nexys_a7_clock_gen.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module subservient_fpga_clock_gen 3 | (input wire i_clk, 4 | input wire i_rst, 5 | output wire o_clk, 6 | output reg o_rst); 7 | 8 | wire clkfb; 9 | wire locked; 10 | reg locked_r; 11 | 12 | PLLE2_BASE 13 | #(.BANDWIDTH("OPTIMIZED"), 14 | .CLKIN1_PERIOD(10.0), //100MHz 15 | .CLKFBOUT_MULT(16), 16 | .CLKOUT0_DIVIDE(50), 17 | .DIVCLK_DIVIDE(1), 18 | .STARTUP_WAIT("FALSE")) 19 | PLLE2_BASE_inst 20 | (.CLKOUT0(o_clk), //100MHz*16/50 = 32 MHz 21 | .CLKOUT1(), 22 | .CLKOUT2(), 23 | .CLKOUT3(), 24 | .CLKOUT4(), 25 | .CLKOUT5(), 26 | .CLKFBOUT(clkfb), 27 | .LOCKED(locked), 28 | .CLKIN1(i_clk), 29 | .PWRDWN(1'b0), 30 | .RST(!i_rst), 31 | .CLKFBIN(clkfb)); 32 | 33 | always @(posedge o_clk) begin 34 | locked_r <= locked; 35 | o_rst <= !locked_r; 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /rtl/subservient_ram.v: -------------------------------------------------------------------------------- 1 | /* 2 | * subservient_ram.v : Shared RF I/D SRAM interface for the subservient SoC 3 | * 4 | * SPDX-FileCopyrightText: 2021 Olof Kindgren 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | 8 | `default_nettype none 9 | module subservient_ram 10 | #(//Memory parameters 11 | parameter depth = 256, 12 | parameter aw = $clog2(depth)) 13 | (input wire i_clk, 14 | input wire i_rst, 15 | input wire [aw-1:0] i_waddr, 16 | input wire [7:0] i_wdata, 17 | input wire i_wen, 18 | input wire [aw-1:0] i_raddr, 19 | output wire [7:0] o_rdata, 20 | input wire i_ren, 21 | 22 | output wire [aw-1:0] o_sram_waddr, 23 | output wire [7:0] o_sram_wdata, 24 | output wire o_sram_wen, 25 | output wire [aw-1:0] o_sram_raddr, 26 | input wire [7:0] i_sram_rdata, 27 | output wire o_sram_ren, 28 | 29 | input wire [aw-1:2] i_wb_adr, 30 | input wire [31:0] i_wb_dat, 31 | input wire [3:0] i_wb_sel, 32 | input wire i_wb_we, 33 | input wire i_wb_stb, 34 | output wire [31:0] o_wb_rdt, 35 | output reg o_wb_ack); 36 | 37 | reg [aw-1:0] rf_waddr_r; 38 | reg [7:0] rf_wdata_r; 39 | reg rf_wen_r; 40 | 41 | reg [1:0] bsel; 42 | 43 | wire wb_en = i_wb_stb & !rf_wen_r & !o_wb_ack; 44 | 45 | wire wb_we = i_wb_we & i_wb_sel[bsel]; 46 | 47 | assign o_sram_waddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : rf_waddr_r; 48 | assign o_sram_wdata = wb_en ? i_wb_dat[bsel*8+:8] : rf_wdata_r; 49 | assign o_sram_wen = wb_en ? wb_we : rf_wen_r; 50 | assign o_sram_raddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_raddr; 51 | assign o_sram_ren = wb_en ? !i_wb_we : i_ren; 52 | 53 | reg [23:0] wb_rdt; 54 | assign o_wb_rdt = {i_sram_rdata, wb_rdt}; 55 | 56 | reg regzero; 57 | always @(posedge i_clk) begin 58 | rf_waddr_r <= i_waddr; 59 | rf_wdata_r <= i_wdata; 60 | rf_wen_r <= i_wen; 61 | 62 | if (wb_en) bsel <= bsel + 2'd1; 63 | o_wb_ack <= wb_en & &bsel; 64 | if (bsel == 2'b01) wb_rdt[7:0] <= i_sram_rdata; 65 | if (bsel == 2'b10) wb_rdt[15:8] <= i_sram_rdata; 66 | if (bsel == 2'b11) wb_rdt[23:16] <= i_sram_rdata; 67 | if (i_rst) begin 68 | bsel <= 2'd0; 69 | o_wb_ack <= 1'b0; 70 | end 71 | regzero <= &i_raddr[aw-1:2]; 72 | end 73 | 74 | assign o_rdata = regzero ? 8'd0 : i_sram_rdata; 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /rtl/subservient_rf_ram_if.v: -------------------------------------------------------------------------------- 1 | /* 2 | * subservient_rf_ram_if.v : Adapter from SERV RF IF to SRAM interface 3 | * 4 | * SPDX-FileCopyrightText: 2021 Olof Kindgren 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | 8 | `default_nettype none 9 | module subservient_rf_ram_if 10 | #(parameter width=8, 11 | parameter reset_strategy="MINI", 12 | parameter csr_regs=4, 13 | parameter depth=32*(32+csr_regs)/width, 14 | parameter l2w = $clog2(width)) 15 | ( 16 | //SERV side 17 | input wire i_clk, 18 | input wire i_rst, 19 | input wire i_wreq, 20 | input wire i_rreq, 21 | output wire o_ready, 22 | input wire [$clog2(32+csr_regs)-1:0] i_wreg0, 23 | input wire [$clog2(32+csr_regs)-1:0] i_wreg1, 24 | input wire i_wen0, 25 | input wire i_wen1, 26 | input wire i_wdata0, 27 | input wire i_wdata1, 28 | input wire [$clog2(32+csr_regs)-1:0] i_rreg0, 29 | input wire [$clog2(32+csr_regs)-1:0] i_rreg1, 30 | output wire o_rdata0, 31 | output wire o_rdata1, 32 | //RAM side 33 | output wire [$clog2(depth)-1:0] o_waddr, 34 | output wire [width-1:0] o_wdata, 35 | output wire o_wen, 36 | output wire [$clog2(depth)-1:0] o_raddr, 37 | input wire [width-1:0] i_rdata, 38 | output wire o_ren); 39 | 40 | reg rgnt; 41 | assign o_ready = rgnt | i_wreq; 42 | reg [4:0] rcnt; 43 | 44 | /* 45 | ********** Write side *********** 46 | */ 47 | 48 | wire [4:0] wcnt; 49 | 50 | reg [width-2:0] wdata0_r; 51 | reg [width-1:0] wdata1_r; 52 | 53 | reg wen0_r; 54 | reg wen1_r; 55 | wire wtrig0; 56 | wire wtrig1; 57 | 58 | generate if (width == 2) begin 59 | assign wtrig0 = ~wcnt[0]; 60 | assign wtrig1 = wcnt[0]; 61 | end else begin 62 | reg wtrig0_r; 63 | always @(posedge i_clk) wtrig0_r <= wtrig0; 64 | assign wtrig0 = (wcnt[l2w-1:0] == {{l2w-1{1'b1}},1'b0}); 65 | assign wtrig1 = wtrig0_r; 66 | end 67 | endgenerate 68 | 69 | assign o_wdata = wtrig1 ? 70 | wdata1_r : 71 | {i_wdata0, wdata0_r}; 72 | 73 | wire [$clog2(32+csr_regs)-1:0] wreg = wtrig1 ? i_wreg1 : i_wreg0; 74 | generate if (width == 32) 75 | assign o_waddr = wreg; 76 | else 77 | assign o_waddr = {wreg, wcnt[4:l2w]}; 78 | endgenerate 79 | 80 | assign o_wen = (wtrig0 & wen0_r) | (wtrig1 & wen1_r); 81 | 82 | generate if (width > 2) 83 | always @(posedge i_clk) wdata0_r <= {i_wdata0, wdata0_r[width-2:1]}; 84 | else 85 | always @(posedge i_clk) wdata0_r <= i_wdata0; 86 | endgenerate 87 | 88 | assign wcnt = rcnt-3; 89 | 90 | always @(posedge i_clk) begin 91 | wen0_r <= i_wen0; 92 | wen1_r <= i_wen1; 93 | 94 | wdata1_r <= {i_wdata1,wdata1_r[width-1:1]}; 95 | 96 | end 97 | 98 | /* 99 | ********** Read side *********** 100 | */ 101 | 102 | wire rtrig0; 103 | reg rtrig1; 104 | 105 | wire [$clog2(32+csr_regs)-1:0] rreg = rtrig0 ? i_rreg1 : i_rreg0; 106 | generate if (width == 32) 107 | assign o_raddr = rreg; 108 | else 109 | assign o_raddr = {rreg, rcnt[4:l2w]}; 110 | endgenerate 111 | 112 | reg [width-1:0] rdata0; 113 | reg [width-2:0] rdata1; 114 | 115 | reg rgate; 116 | reg rvalid; 117 | 118 | assign o_rdata0 = rvalid & rdata0[0]; 119 | assign o_rdata1 = rvalid & (rtrig1 ? i_rdata[0] : rdata1[0]); 120 | 121 | assign rtrig0 = (rcnt[l2w-1:0] == 1); 122 | assign o_ren = rgate & ((rcnt[l2w-1:0] == 0) | rtrig0); 123 | 124 | reg rreq_r; 125 | 126 | generate if (width>2) 127 | always @(posedge i_clk) begin 128 | rdata1 <= {1'b0,rdata1[width-2:1]}; //Optimize? 129 | if (rtrig1) 130 | rdata1[width-2:0] <= i_rdata[width-1:1]; 131 | end 132 | else 133 | always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1]; 134 | endgenerate 135 | 136 | always @(posedge i_clk) begin 137 | if (o_ready) 138 | rvalid <= rgate; 139 | 140 | if (&rcnt) 141 | rgate <= 1'b0; 142 | else if (i_rreq) 143 | rgate <= 1'b1; 144 | 145 | rtrig1 <= rtrig0; 146 | rcnt <= rcnt+5'd1; 147 | if (i_rreq) 148 | rcnt <= 5'd0; 149 | if (i_wreq) 150 | rcnt <= 5'd2; 151 | 152 | rreq_r <= i_rreq; 153 | rgnt <= rreq_r; 154 | 155 | rdata0 <= {1'b0,rdata0[width-1:1]}; 156 | if (rtrig0) 157 | rdata0 <= i_rdata; 158 | 159 | if (i_rst) begin 160 | if (reset_strategy != "NONE") begin 161 | rgate <= 1'b0; 162 | rcnt <= 5'd2; 163 | rgnt <= 1'b0; 164 | rreq_r <= 1'b0; 165 | end 166 | end 167 | end 168 | 169 | 170 | 171 | endmodule 172 | -------------------------------------------------------------------------------- /subservient.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::subservient:0.2.0 4 | description: Minimal SERV-based SoC for ASIC implementation 5 | 6 | filesets: 7 | core: 8 | files: 9 | - rtl/subservient_rf_ram_if.v 10 | - rtl/subservient_ram.v 11 | - rtl/subservient_debug_switch.v 12 | - rtl/subservient_core.v 13 | file_type : verilogSource 14 | depend : [">=servile-1.3.0"] 15 | 16 | mem_files: 17 | files: 18 | - sw/blinky.hex : {copyto : blinky.hex} 19 | - sw/hello.hex : {copyto : hello.hex} 20 | file_type : user 21 | 22 | sky130: 23 | files: 24 | - data/openlane_common.tcl : {file_type : tclSource} 25 | - data/sky130.tcl : {file_type : tclSource} 26 | 27 | gf180: 28 | files: 29 | - data/openlane_common.tcl : {file_type : tclSource} 30 | - data/gf180.tcl : {file_type : tclSource} 31 | 32 | tb: 33 | files: 34 | - rtl/subservient_generic_ram.v 35 | - tb/uart_decoder.v 36 | - tb/subservient_tb.v 37 | file_type : verilogSource 38 | depend : [vlog_tb_utils] 39 | 40 | soc: 41 | files: 42 | - rtl/subservient_gpio.v 43 | - rtl/subservient.v 44 | file_type : verilogSource 45 | 46 | fpga: 47 | files: 48 | - rtl/subservient_generic_ram.v : {file_type : verilogSource} 49 | - rtl/subservient_fpga.v : {file_type : verilogSource} 50 | 51 | fpga_tb: 52 | files: 53 | - tb/subservient_fpga_clock_gen_sim.v : {file_type : verilogSource} 54 | - tb/subservient_fpga_tb.cpp : {file_type : cppSource} 55 | 56 | nexys_a7: 57 | files: 58 | - data/nexys_a7.xdc : {file_type : xdc} 59 | - rtl/subservient_nexys_a7_clock_gen.v : {file_type : verilogSource} 60 | 61 | targets: 62 | default: 63 | filesets : [soc, core] 64 | 65 | lint: 66 | default_tool : verilator 67 | filesets : [core, soc] 68 | tools: 69 | verilator: 70 | mode : lint-only 71 | toplevel : subservient 72 | 73 | sky130: 74 | default_tool: openlane 75 | filesets : [core, soc, sky130] 76 | parameters : 77 | - memsize 78 | toplevel : subservient 79 | 80 | gf180: 81 | default_tool: openlane 82 | filesets : [core, soc, gf180] 83 | parameters : 84 | - memsize 85 | toplevel : subservient 86 | 87 | nexys_a7: 88 | default_tool: vivado 89 | filesets : [core, soc, mem_files, fpga, nexys_a7] 90 | parameters: [memfile] 91 | tools: 92 | vivado: {part : xc7a100tcsg324-1} 93 | toplevel: subservient_fpga 94 | 95 | sim: &sim 96 | default_tool: icarus 97 | filesets : [mem_files, core, soc, tb] 98 | parameters : 99 | - firmware 100 | - memsize 101 | - uart_baudrate 102 | toplevel : subservient_tb 103 | 104 | sim_hello: 105 | <<: *sim 106 | parameters : 107 | - firmware=hello.hex 108 | - memsize=1024 109 | - uart_baudrate=115200 110 | 111 | fpga_tb: 112 | default_tool : verilator 113 | filesets : [core, soc, mem_files, fpga, fpga_tb] 114 | parameters: [firmware, uart_baudrate=46080] 115 | tools: 116 | verilator: 117 | verilator_options : [-trace] 118 | toplevel: subservient_fpga 119 | 120 | parameters: 121 | firmware: 122 | datatype : file 123 | description : Preload RAM with a hex file at runtime 124 | paramtype : plusarg 125 | 126 | memfile: 127 | datatype : file 128 | description : Preload RAM with a hex file at compile-time 129 | paramtype : vlogparam 130 | 131 | memsize: 132 | datatype : int 133 | default : 1024 134 | description : Memory size in bytes for RAM (default 1kiB) 135 | paramtype : vlogparam 136 | 137 | uart_baudrate: 138 | datatype : int 139 | description : Treat gpio output as an UART with the specified baudrate (0 or omitted parameter disables UART decoding) 140 | paramtype : plusarg 141 | -------------------------------------------------------------------------------- /sw/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Makefile: Makefile for building subservient firmware 3 | # 4 | # SPDX-FileCopyrightText: 2021 Olof Kindgren 5 | # SPDX-License-Identifier: Apache-2.0 6 | # 7 | TOOLCHAIN_PREFIX ?= riscv64-unknown-elf- 8 | 9 | %.elf: %.S 10 | $(TOOLCHAIN_PREFIX)gcc -nostartfiles -march=rv32i -mabi=ilp32 -Tlink.ld -o$@ $< 11 | %.hex: %.elf 12 | $(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@ 13 | %.bin: %.elf 14 | $(TOOLCHAIN_PREFIX)objcopy -O binary $< $@ 15 | clean: 16 | rm -f *.elf *.bin *.hex 17 | -------------------------------------------------------------------------------- /sw/blinky.S: -------------------------------------------------------------------------------- 1 | /* 2 | * blinky.S : LED blink example firmware for the subservient SoC 3 | * 4 | * SPDX-FileCopyrightText: 2021 Olof Kindgren 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | 8 | /* 9 | * Assuming that GPIO_BASE is mapped to a GPIO core, which in turn is 10 | * connected to a LEDs, this will blink the LED. 11 | * Useful as smoke test to see that serv is running correctly 12 | */ 13 | #ifndef GPIO_BASE 14 | #define GPIO_BASE 0x40000000 15 | #endif 16 | 17 | #ifndef DELAY 18 | #define DELAY 0x10 /* Loop this many times before inverting the LED */ 19 | #endif 20 | 21 | /* 22 | a0 = GPIO Base address 23 | t0 = Value 24 | t1 = Timer max value 25 | t2 = Current timer value 26 | */ 27 | 28 | .globl _start 29 | _start: 30 | /* Load GPIO base address to a0 */ 31 | li a0, GPIO_BASE 32 | 33 | /* Set timer value to control blink speed */ 34 | li t1, DELAY 35 | 36 | /* Clear t0 */ 37 | addi t0, zero, 0 38 | 39 | /* Write to LED */ 40 | bl1: sb t0, 0(a0) 41 | 42 | /* invert LED */ 43 | xori t0, t0, 1 44 | 45 | /* Reset timer */ 46 | and t2, zero, zero 47 | 48 | /* Delay loop */ 49 | time1: addi t2, t2, 1 50 | bne t1, t2, time1 51 | j bl1 52 | -------------------------------------------------------------------------------- /sw/blinky.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 37 05 00 40 13 03 00 01 93 02 00 00 23 00 55 00 3 | 93 C2 12 00 B3 73 00 00 93 83 13 00 E3 1E 73 FE 4 | 6F F0 DF FE 5 | -------------------------------------------------------------------------------- /sw/hello.S: -------------------------------------------------------------------------------- 1 | /* 2 | * hello.S : Hello world for subservient 3 | * 4 | * SPDX-FileCopyrightText: 2021 Olof Kindgren 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | 8 | /* 9 | * 10 | * Continuously read a string from memory and transmit each character (bitbang) 11 | * like a UART over GPIO 12 | * 13 | */ 14 | #define GPIO_ADDR 0x40000000 15 | 16 | /* 17 | a0 = GPIO address 18 | a1 = String address 19 | t0 = Character to write 20 | */ 21 | 22 | .globl _start 23 | _start: 24 | /* Load gpio address to a0 */ 25 | li a0, GPIO_ADDR 26 | 27 | /* Set GPIO high initially */ 28 | addi t0, zero, 1 29 | sb t0, 0(a0) 30 | 31 | loop: 32 | /* Load string address to a1 */ 33 | la a1, str 34 | 35 | next_char: 36 | /* Read char from string */ 37 | lbu t0, 0(a1) 38 | 39 | /* If zero, we reached end of string and will reload first character */ 40 | beqz t0, loop 41 | 42 | /* Bitbanged UART loop */ 43 | ori t0, t0, 0x100 44 | slli t0, t0, 1 45 | 1: sb t0, 0(a0) 46 | srli t0, t0, 1 47 | 48 | /* 49 | * Adding delay nops to achieve an approximate 50 | * baud rate of 115200 at 100MHz 51 | */ 52 | nop 53 | nop 54 | nop 55 | nop 56 | nop 57 | nop 58 | nop 59 | nop 60 | nop 61 | nop 62 | nop 63 | nop 64 | nop 65 | nop 66 | nop 67 | nop 68 | nop 69 | bnez t0, 1b 70 | 71 | /* Increase address to next char in string */ 72 | addi a1, a1, 1 73 | 74 | j next_char 75 | 76 | str: 77 | .section .data 78 | .string "Hi! I'm subservient\n" 79 | -------------------------------------------------------------------------------- /sw/hello.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 37 05 00 40 93 02 10 00 23 00 55 00 97 05 00 00 3 | 93 85 05 07 83 C2 05 00 E3 8A 02 FE 93 E2 02 10 4 | 93 92 12 00 23 00 55 00 93 D2 12 00 13 00 00 00 5 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 6 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 7 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 8 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 9 | E3 9A 02 FA 93 85 15 00 6F F0 DF F9 10 | @0000007C 11 | 48 69 21 20 49 27 6D 20 73 75 62 73 65 72 76 69 12 | 65 6E 74 0A 00 13 | -------------------------------------------------------------------------------- /sw/link.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * link.ld : Linker script for subservient SoC 3 | * 4 | * SPDX-FileCopyrightText: 2021 Olof Kindgren 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | 8 | OUTPUT_ARCH( "riscv" ) 9 | ENTRY(_start) 10 | 11 | SECTIONS 12 | { 13 | . = 0; 14 | .text : { *(.text) } 15 | .data : { *(.data) } 16 | .bss : { *(.bss) } 17 | } 18 | -------------------------------------------------------------------------------- /tb/subservient_fpga_clock_gen_sim.v: -------------------------------------------------------------------------------- 1 | module subservient_fpga_clock_gen 2 | (input wire i_clk, 3 | input wire i_rst, 4 | output wire o_clk, 5 | output reg o_rst); 6 | 7 | assign o_clk = i_clk; 8 | always @(posedge i_clk) o_rst <= i_rst; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /tb/subservient_fpga_tb.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "verilated_vcd_c.h" 5 | #include "Vsubservient_fpga.h" 6 | 7 | using namespace std; 8 | 9 | static bool done; 10 | 11 | vluint64_t main_time = 0; // Current simulation time 12 | // This is a 64-bit integer to reduce wrap over issues and 13 | // allow modulus. You can also use a double, if you wish. 14 | 15 | double sc_time_stamp () { // Called by $time in Verilog 16 | return main_time; // converts to double, to match 17 | // what SystemC does 18 | } 19 | 20 | void INThandler(int signal) 21 | { 22 | printf("\nCaught ctrl-c\n"); 23 | done = true; 24 | } 25 | 26 | typedef struct { 27 | bool last_value; 28 | } gpio_context_t; 29 | 30 | void do_gpio(gpio_context_t *context, bool gpio) { 31 | if (context->last_value != gpio) { 32 | context->last_value = gpio; 33 | printf("%lu output q is %s\n", main_time, gpio ? "ON" : "OFF"); 34 | } 35 | } 36 | 37 | typedef struct { 38 | uint8_t state; 39 | char ch; 40 | uint32_t baud_t; 41 | vluint64_t last_update; 42 | } uart_context_t; 43 | 44 | void uart_init(uart_context_t *context, uint32_t baud_rate) { 45 | context->baud_t = 1000*1000*1000/baud_rate; 46 | context->state = 0; 47 | } 48 | 49 | bool do_uart(uart_context_t *context, bool rx) { 50 | if (context->state == 0) { 51 | if (rx) 52 | context->state++; 53 | } 54 | else if (context->state == 1) { 55 | if (!rx) { 56 | context->last_update = main_time + context->baud_t/2; 57 | context->state++; 58 | } 59 | } 60 | else if(context->state == 2) { 61 | if (main_time > context->last_update) { 62 | context->last_update += context->baud_t; 63 | context->ch = 0; 64 | context->state++; 65 | } 66 | } 67 | else if (context->state < 11) { 68 | if (main_time > context->last_update) { 69 | context->last_update += context->baud_t; 70 | context->ch |= rx << (context->state-3); 71 | context->state++; 72 | } 73 | } 74 | else { 75 | if (main_time > context->last_update) { 76 | context->last_update += context->baud_t; 77 | context->state=1; 78 | return true; 79 | } 80 | } 81 | return false; 82 | } 83 | 84 | int main(int argc, char **argv, char **env) 85 | { 86 | int baud_rate = 0; 87 | 88 | gpio_context_t gpio_context; 89 | uart_context_t uart_context; 90 | Verilated::commandArgs(argc, argv); 91 | 92 | Vsubservient_fpga* top = new Vsubservient_fpga; 93 | 94 | const char *arg = Verilated::commandArgsPlusMatch("uart_baudrate="); 95 | if (arg[0]) { 96 | baud_rate = atoi(arg+15); 97 | if (baud_rate) { 98 | uart_init(&uart_context, baud_rate); 99 | } 100 | } 101 | 102 | VerilatedVcdC * tfp = 0; 103 | const char *vcd = Verilated::commandArgsPlusMatch("vcd="); 104 | if (vcd[0]) { 105 | Verilated::traceEverOn(true); 106 | tfp = new VerilatedVcdC; 107 | top->trace (tfp, 99); 108 | tfp->open ("trace.vcd"); 109 | } 110 | 111 | signal(SIGINT, INThandler); 112 | 113 | vluint64_t timeout = 0; 114 | const char *arg_timeout = Verilated::commandArgsPlusMatch("timeout="); 115 | if (arg_timeout[0]) 116 | timeout = atoi(arg_timeout+9); 117 | 118 | vluint64_t vcd_start = 0; 119 | const char *arg_vcd_start = Verilated::commandArgsPlusMatch("vcd_start="); 120 | if (arg_vcd_start[0]) 121 | vcd_start = atoi(arg_vcd_start+11); 122 | 123 | bool dump = false; 124 | top->i_clk = 1; 125 | bool q = top->q; 126 | while (!(done || Verilated::gotFinish())) { 127 | if (tfp && !dump && (main_time > vcd_start)) { 128 | dump = true; 129 | } 130 | top->i_rst = main_time < 100; 131 | top->eval(); 132 | if (dump) 133 | tfp->dump(main_time); 134 | if (baud_rate) { 135 | if (do_uart(&uart_context, top->q)) 136 | putchar(uart_context.ch); 137 | } else { 138 | do_gpio(&gpio_context, top->q); 139 | } 140 | if (timeout && (main_time >= timeout)) { 141 | printf("Timeout: Exiting at time %lu\n", main_time); 142 | done = true; 143 | } 144 | 145 | top->i_clk = !top->i_clk; 146 | main_time+=12.5; 147 | 148 | } 149 | if (tfp) 150 | tfp->close(); 151 | exit(0); 152 | } 153 | -------------------------------------------------------------------------------- /tb/subservient_tb.v: -------------------------------------------------------------------------------- 1 | /* 2 | * subservient_tb.v : Verilog testbench for the subservient SoC 3 | * 4 | * SPDX-FileCopyrightText: 2021 Olof Kindgren 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | 8 | `default_nettype none 9 | module subservient_tb; 10 | 11 | parameter memfile = ""; 12 | parameter memsize = 8192; 13 | parameter with_csr = 0; 14 | parameter aw = $clog2(memsize); 15 | 16 | reg clk = 1'b0; 17 | reg rst = 1'b1; 18 | 19 | wire [aw-1:0] sram_waddr; 20 | wire [7:0] sram_wdata; 21 | wire sram_wen; 22 | wire [aw-1:0] sram_raddr; 23 | wire [7:0] sram_rdata; 24 | wire sram_ren; 25 | 26 | wire q; 27 | 28 | always #5 clk <= !clk; 29 | initial #62 rst <= 1'b0; 30 | 31 | vlog_tb_utils vtu(); 32 | 33 | integer baudrate = 0; 34 | initial begin 35 | if ($value$plusargs("uart_baudrate=%d", baudrate)) 36 | $display("UART decoder using baud rate %0d", baudrate); 37 | else 38 | forever 39 | @(q) $display("%0t output o_gpio is %s", $time, q ? "ON" : "OFF"); 40 | 41 | end 42 | 43 | reg [1023:0] firmware_file; 44 | 45 | initial begin 46 | if ($value$plusargs("firmware=%s", firmware_file)) begin 47 | $display("Writing %0s to SRAM", firmware_file); 48 | $readmemh(firmware_file, memory.mem); 49 | end else 50 | $display("No application to load. SRAM will be empty"); 51 | 52 | repeat (10) @(posedge clk); 53 | end 54 | 55 | uart_decoder uart_decoder (baudrate, q); 56 | 57 | subservient_generic_ram 58 | #(.depth (memsize)) 59 | memory 60 | (.i_clk (clk), 61 | .i_rst (rst), 62 | .i_waddr (sram_waddr), 63 | .i_wdata (sram_wdata), 64 | .i_wen (sram_wen), 65 | .i_raddr (sram_raddr), 66 | .o_rdata (sram_rdata), 67 | .i_ren (sram_ren)); 68 | 69 | //Note: This should probably be a proper assert instead 70 | always @(posedge clk) 71 | if (sram_ren & sram_wen) 72 | $display("$0t Error: Simultaneous SRAM read and write", $time); 73 | 74 | subservient 75 | #(.memsize (memsize), 76 | .WITH_CSR (with_csr)) 77 | dut 78 | (// Clock & reset 79 | .i_clk (clk), 80 | .i_rst (rst), 81 | 82 | //SRAM interface 83 | .o_sram_waddr (sram_waddr), 84 | .o_sram_wdata (sram_wdata), 85 | .o_sram_wen (sram_wen), 86 | .o_sram_raddr (sram_raddr), 87 | .i_sram_rdata (sram_rdata), 88 | .o_sram_ren (sram_ren), 89 | 90 | // External I/O 91 | .o_gpio (q)); 92 | 93 | endmodule 94 | -------------------------------------------------------------------------------- /tb/uart_decoder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * uart_decoder.v : UART decoder for the subservient SoC 3 | * 4 | * SPDX-FileCopyrightText: 2021 Olof Kindgren 5 | * SPDX-License-Identifier: Apache-2.0 6 | */ 7 | module uart_decoder 8 | (input wire [31:0] baud_rate, 9 | input wire rx); 10 | 11 | integer i; 12 | reg [7:0] ch; 13 | 14 | real t; 15 | 16 | initial begin 17 | 18 | @(posedge rx); 19 | t = 1000000000/baud_rate; 20 | 21 | forever begin 22 | @(negedge rx); 23 | #(t/2) ch = 0; 24 | for (i=0;i<8;i=i+1) 25 | #t ch[i] = rx; 26 | $write("%c",ch); 27 | $fflush; 28 | end 29 | end 30 | endmodule 31 | --------------------------------------------------------------------------------