├── Cache_Controller_FPGA_Implementation_Project ├── Cache_Controller_FPGA_Implementation_Project.cache │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ ├── webtalk_pa.xml │ │ └── xsim.wdf ├── Cache_Controller_FPGA_Implementation_Project.hw │ ├── Cache_Controller_FPGA_Implementation_Project.lpr │ └── hw_1 │ │ └── hw.xml ├── Cache_Controller_FPGA_Implementation_Project.ip_user_files │ └── README.txt ├── Cache_Controller_FPGA_Implementation_Project.runs │ ├── .jobs │ │ └── vrs_config_1.xml │ ├── impl_1 │ │ ├── .Vivado_Implementation.queue.rst │ │ ├── .init_design.begin.rst │ │ ├── .init_design.end.rst │ │ ├── .opt_design.begin.rst │ │ ├── .opt_design.end.rst │ │ ├── .place_design.begin.rst │ │ ├── .place_design.end.rst │ │ ├── .route_design.begin.rst │ │ ├── .route_design.end.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── .write_bitstream.begin.rst │ │ ├── .write_bitstream.end.rst │ │ ├── CACHE_CONTROLLER.bin │ │ ├── CACHE_CONTROLLER.bit │ │ ├── CACHE_CONTROLLER.tcl │ │ ├── CACHE_CONTROLLER.vdi │ │ ├── CACHE_CONTROLLER_bus_skew_routed.pb │ │ ├── CACHE_CONTROLLER_bus_skew_routed.rpt │ │ ├── CACHE_CONTROLLER_bus_skew_routed.rpx │ │ ├── CACHE_CONTROLLER_clock_utilization_routed.rpt │ │ ├── CACHE_CONTROLLER_control_sets_placed.rpt │ │ ├── CACHE_CONTROLLER_drc_opted.pb │ │ ├── CACHE_CONTROLLER_drc_opted.rpt │ │ ├── CACHE_CONTROLLER_drc_opted.rpx │ │ ├── CACHE_CONTROLLER_drc_routed.pb │ │ ├── CACHE_CONTROLLER_drc_routed.rpt │ │ ├── CACHE_CONTROLLER_drc_routed.rpx │ │ ├── CACHE_CONTROLLER_io_placed.rpt │ │ ├── CACHE_CONTROLLER_methodology_drc_routed.pb │ │ ├── CACHE_CONTROLLER_methodology_drc_routed.rpt │ │ ├── CACHE_CONTROLLER_methodology_drc_routed.rpx │ │ ├── CACHE_CONTROLLER_opt.dcp │ │ ├── CACHE_CONTROLLER_placed.dcp │ │ ├── CACHE_CONTROLLER_power_routed.rpt │ │ ├── CACHE_CONTROLLER_power_routed.rpx │ │ ├── CACHE_CONTROLLER_power_summary_routed.pb │ │ ├── CACHE_CONTROLLER_route_status.pb │ │ ├── CACHE_CONTROLLER_route_status.rpt │ │ ├── CACHE_CONTROLLER_routed.dcp │ │ ├── CACHE_CONTROLLER_timing_summary_routed.pb │ │ ├── CACHE_CONTROLLER_timing_summary_routed.rpt │ │ ├── CACHE_CONTROLLER_timing_summary_routed.rpx │ │ ├── CACHE_CONTROLLER_utilization_placed.pb │ │ ├── CACHE_CONTROLLER_utilization_placed.rpt │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── project.wdf │ │ ├── route_design.pb │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── usage_statistics_webtalk.html │ │ ├── usage_statistics_webtalk.xml │ │ ├── vivado.jou │ │ ├── vivado.pb │ │ └── write_bitstream.pb │ └── synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ └── CACHE_CONTROLLER_propImpl.xdc │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── CACHE_CONTROLLER.dcp │ │ ├── CACHE_CONTROLLER.tcl │ │ ├── CACHE_CONTROLLER.vds │ │ ├── CACHE_CONTROLLER_utilization_synth.pb │ │ ├── CACHE_CONTROLLER_utilization_synth.rpt │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb ├── Cache_Controller_FPGA_Implementation_Project.sim │ └── sim_1 │ │ └── behav │ │ └── xsim │ │ ├── TB_READ.tcl │ │ ├── TB_READ_behav.wdb │ │ ├── TB_READ_vlog.prj │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── elaborate.bat │ │ ├── elaborate.log │ │ ├── glbl.v │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── tb_CACHE_CONTROLLER.tcl │ │ ├── tb_CACHE_CONTROLLER_behav.wdb │ │ ├── tb_CACHE_CONTROLLER_vlog.prj │ │ ├── webtalk.jou │ │ ├── webtalk.log │ │ ├── webtalk_16080.backup.jou │ │ ├── webtalk_16080.backup.log │ │ ├── webtalk_1788.backup.jou │ │ ├── webtalk_1788.backup.log │ │ ├── webtalk_23044.backup.jou │ │ ├── webtalk_23044.backup.log │ │ ├── webtalk_26168.backup.jou │ │ ├── webtalk_26168.backup.log │ │ ├── webtalk_27976.backup.jou │ │ ├── webtalk_27976.backup.log │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── TB_READ_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ └── .xsim_webtallk.info │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ └── xil_defaultlib │ │ │ ├── @c@a@c@h@e_@c@o@n@t@r@o@l@l@e@r.sdb │ │ │ ├── @t@b_@r@e@a@d.sdb │ │ │ ├── glbl.sdb │ │ │ └── xil_defaultlib.rlx │ │ ├── xsim.ini │ │ ├── xvlog.log │ │ └── xvlog.pb ├── Cache_Controller_FPGA_Implementation_Project.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── Cache_Controller_Constraints.xdc │ ├── sim_1 │ │ └── new │ │ │ └── TB_READ.v │ └── sources_1 │ │ └── new │ │ └── CACHE_CONTROLLER.v ├── Cache_Controller_FPGA_Implementation_Project.xpr ├── vivado.jou ├── vivado.log ├── vivado_11816.backup.jou └── vivado_11816.backup.log ├── Cache_Controller_Poster.pdf ├── Cache_Controller_Simulation_Project ├── Cache_Controller_Simulation_Project.cache │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── webtalk_pa.xml │ │ └── xsim.wdf ├── Cache_Controller_Simulation_Project.hw │ └── Cache_Controller_Simulation_Project.lpr ├── Cache_Controller_Simulation_Project.ip_user_files │ └── README.txt ├── Cache_Controller_Simulation_Project.sim │ └── sim_1 │ │ └── behav │ │ └── xsim │ │ ├── TB_2.tcl │ │ ├── TB_2_behav.wdb │ │ ├── TB_2_vlog.prj │ │ ├── TB_READ.tcl │ │ ├── TB_READ_behav.wdb │ │ ├── TB_READ_vlog.prj │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── elaborate.bat │ │ ├── elaborate.log │ │ ├── glbl.v │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── tb_CACHE_CONTROLLER.tcl │ │ ├── tb_CACHE_CONTROLLER_behav.wdb │ │ ├── tb_CACHE_CONTROLLER_vlog.prj │ │ ├── webtalk.jou │ │ ├── webtalk.log │ │ ├── webtalk_12708.backup.jou │ │ ├── webtalk_20724.backup.jou │ │ ├── webtalk_20724.backup.log │ │ ├── webtalk_23072.backup.log │ │ ├── webtalk_26484.backup.jou │ │ ├── webtalk_26484.backup.log │ │ ├── webtalk_7160.backup.jou │ │ ├── webtalk_7160.backup.log │ │ ├── webtalk_9828.backup.jou │ │ ├── webtalk_9828.backup.log │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── TB_READ_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ └── .xsim_webtallk.info │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ └── xil_defaultlib │ │ │ ├── @c@a@c@h@e_@c@o@n@t@r@o@l@l@e@r.sdb │ │ │ ├── @l1_@c@a@c@h@e_@m@e@m@o@r@y.sdb │ │ │ ├── @l2_@c@a@c@h@e_@m@e@m@o@r@y.sdb │ │ │ ├── @m@a@i@n_@m@e@m@o@r@y.sdb │ │ │ ├── @t@b_@r@e@a@d.sdb │ │ │ ├── glbl.sdb │ │ │ └── xil_defaultlib.rlx │ │ ├── xsim.ini │ │ ├── xvlog.log │ │ └── xvlog.pb ├── Cache_Controller_Simulation_Project.srcs │ ├── sim_1 │ │ └── new │ │ │ └── TB_READ.v │ └── sources_1 │ │ └── new │ │ ├── CACHE_CONTROLLER.v │ │ ├── L1_CACHE_MEMORY.v │ │ ├── L2_CACHE_MEMORY.v │ │ └── MAIN_MEMORY.v ├── Cache_Controller_Simulation_Project.xpr ├── vivado.jou ├── vivado.log ├── vivado_21916.backup.jou └── vivado_21916.backup.log ├── Cache_controller_block_diagram.PNG ├── FPGA_Input_Ouput_Ports_and_Signals.JPG ├── README.md └── Simulation_Waveforms ├── Cache_Controller_FPGA_Implementation_Project ├── Cache_Controller_FPGA_Implementation_Project.cache │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ ├── synthesis_details.wdf │ │ ├── webtalk_pa.xml │ │ └── xsim.wdf ├── Cache_Controller_FPGA_Implementation_Project.hw │ ├── Cache_Controller_FPGA_Implementation_Project.lpr │ └── hw_1 │ │ └── hw.xml ├── Cache_Controller_FPGA_Implementation_Project.ip_user_files │ └── README.txt ├── Cache_Controller_FPGA_Implementation_Project.runs │ ├── .jobs │ │ └── vrs_config_1.xml │ ├── impl_1 │ │ ├── .Vivado_Implementation.queue.rst │ │ ├── .init_design.begin.rst │ │ ├── .init_design.end.rst │ │ ├── .opt_design.begin.rst │ │ ├── .opt_design.end.rst │ │ ├── .place_design.begin.rst │ │ ├── .place_design.end.rst │ │ ├── .route_design.begin.rst │ │ ├── .route_design.end.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── .write_bitstream.begin.rst │ │ ├── .write_bitstream.end.rst │ │ ├── CACHE_CONTROLLER.bin │ │ ├── CACHE_CONTROLLER.bit │ │ ├── CACHE_CONTROLLER.tcl │ │ ├── CACHE_CONTROLLER.vdi │ │ ├── CACHE_CONTROLLER_bus_skew_routed.pb │ │ ├── CACHE_CONTROLLER_bus_skew_routed.rpt │ │ ├── CACHE_CONTROLLER_bus_skew_routed.rpx │ │ ├── CACHE_CONTROLLER_clock_utilization_routed.rpt │ │ ├── CACHE_CONTROLLER_control_sets_placed.rpt │ │ ├── CACHE_CONTROLLER_drc_opted.pb │ │ ├── CACHE_CONTROLLER_drc_opted.rpt │ │ ├── CACHE_CONTROLLER_drc_opted.rpx │ │ ├── CACHE_CONTROLLER_drc_routed.pb │ │ ├── CACHE_CONTROLLER_drc_routed.rpt │ │ ├── CACHE_CONTROLLER_drc_routed.rpx │ │ ├── CACHE_CONTROLLER_io_placed.rpt │ │ ├── CACHE_CONTROLLER_methodology_drc_routed.pb │ │ ├── CACHE_CONTROLLER_methodology_drc_routed.rpt │ │ ├── CACHE_CONTROLLER_methodology_drc_routed.rpx │ │ ├── CACHE_CONTROLLER_opt.dcp │ │ ├── CACHE_CONTROLLER_placed.dcp │ │ ├── CACHE_CONTROLLER_power_routed.rpt │ │ ├── CACHE_CONTROLLER_power_routed.rpx │ │ ├── CACHE_CONTROLLER_power_summary_routed.pb │ │ ├── CACHE_CONTROLLER_route_status.pb │ │ ├── CACHE_CONTROLLER_route_status.rpt │ │ ├── CACHE_CONTROLLER_routed.dcp │ │ ├── CACHE_CONTROLLER_timing_summary_routed.pb │ │ ├── CACHE_CONTROLLER_timing_summary_routed.rpt │ │ ├── CACHE_CONTROLLER_timing_summary_routed.rpx │ │ ├── CACHE_CONTROLLER_utilization_placed.pb │ │ ├── CACHE_CONTROLLER_utilization_placed.rpt │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── place_design.pb │ │ ├── project.wdf │ │ ├── route_design.pb │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── usage_statistics_webtalk.html │ │ ├── usage_statistics_webtalk.xml │ │ ├── vivado.jou │ │ ├── vivado.pb │ │ └── write_bitstream.pb │ └── synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ └── CACHE_CONTROLLER_propImpl.xdc │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── CACHE_CONTROLLER.dcp │ │ ├── CACHE_CONTROLLER.tcl │ │ ├── CACHE_CONTROLLER.vds │ │ ├── CACHE_CONTROLLER_utilization_synth.pb │ │ ├── CACHE_CONTROLLER_utilization_synth.rpt │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb ├── Cache_Controller_FPGA_Implementation_Project.sim │ └── sim_1 │ │ └── behav │ │ └── xsim │ │ ├── TB_READ.tcl │ │ ├── TB_READ_behav.wdb │ │ ├── TB_READ_vlog.prj │ │ ├── compile.bat │ │ ├── compile.log │ │ ├── elaborate.bat │ │ ├── elaborate.log │ │ ├── glbl.v │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── tb_CACHE_CONTROLLER.tcl │ │ ├── tb_CACHE_CONTROLLER_behav.wdb │ │ ├── tb_CACHE_CONTROLLER_vlog.prj │ │ ├── webtalk.jou │ │ ├── webtalk.log │ │ ├── webtalk_16080.backup.jou │ │ ├── webtalk_16080.backup.log │ │ ├── webtalk_1788.backup.jou │ │ ├── webtalk_1788.backup.log │ │ ├── webtalk_23044.backup.jou │ │ ├── webtalk_23044.backup.log │ │ ├── webtalk_26168.backup.jou │ │ ├── webtalk_26168.backup.log │ │ ├── webtalk_27976.backup.jou │ │ ├── webtalk_27976.backup.log │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── TB_READ_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ └── .xsim_webtallk.info │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ └── xil_defaultlib │ │ │ ├── @c@a@c@h@e_@c@o@n@t@r@o@l@l@e@r.sdb │ │ │ ├── @t@b_@r@e@a@d.sdb │ │ │ ├── glbl.sdb │ │ │ └── xil_defaultlib.rlx │ │ ├── xsim.ini │ │ ├── xvlog.log │ │ └── xvlog.pb ├── Cache_Controller_FPGA_Implementation_Project.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── Cache_Controller_Constraints.xdc │ ├── sim_1 │ │ └── new │ │ │ └── TB_READ.v │ └── sources_1 │ │ └── new │ │ └── CACHE_CONTROLLER.v ├── Cache_Controller_FPGA_Implementation_Project.xpr ├── vivado.jou ├── vivado.log ├── vivado_11816.backup.jou └── vivado_11816.backup.log ├── Waveform_1.PNG ├── Waveform_2.PNG └── Waveform_3.PNG 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-------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:241934075 5 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.hw/Cache_Controller_FPGA_Implementation_Project.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.hw/hw_1/hw.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 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/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/CACHE_CONTROLLER_bus_skew_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 4 | | Date : Sun Nov 17 17:18:30 2019 5 | | Host : LAPTOP-V3L8ACTM running 64-bit major release (build 9200) 6 | | Command : report_bus_skew -warn_on_violation -file CACHE_CONTROLLER_bus_skew_routed.rpt -pb CACHE_CONTROLLER_bus_skew_routed.pb -rpx CACHE_CONTROLLER_bus_skew_routed.rpx 7 | | Design : CACHE_CONTROLLER 8 | | Device : 7a35t-cpg236 9 | | Speed File : -1 PRODUCTION 1.23 2018-06-13 10 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 11 | 12 | Bus Skew Report 13 | 14 | No bus skew constraints 15 | 16 | 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Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log CACHE_CONTROLLER.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CACHE_CONTROLLER.tcl -notrace 10 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/init_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/init_design.pb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/opt_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/opt_design.pb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/place_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/place_design.pb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/route_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/route_design.pb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; 12 | } else { 13 | PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | // pre-commands: 26 | ISETouchFile( "init_design", "begin" ); 27 | ISEStep( "vivado", 28 | "-log CACHE_CONTROLLER.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CACHE_CONTROLLER.tcl -notrace" ); 29 | 30 | 31 | 32 | 33 | 34 | function EAInclude( EAInclFilename ) { 35 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 36 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 37 | var EAIFContents = EAInclFile.ReadAll(); 38 | EAInclFile.Close(); 39 | return EAIFContents; 40 | } 41 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin 15 | else 16 | PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | # pre-commands: 44 | /bin/touch .init_design.begin.rst 45 | EAStep vivado -log CACHE_CONTROLLER.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CACHE_CONTROLLER.tcl -notrace 46 | 47 | 48 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 17:16:22 2019 6 | # Process ID: 16112 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1 8 | # Command line: vivado.exe -log CACHE_CONTROLLER.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CACHE_CONTROLLER.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/CACHE_CONTROLLER.vdi 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source CACHE_CONTROLLER.tcl -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/vivado.pb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/write_bitstream.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/write_bitstream.pb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/CACHE_CONTROLLER.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/CACHE_CONTROLLER.dcp -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/CACHE_CONTROLLER_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/CACHE_CONTROLLER_utilization_synth.pb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log CACHE_CONTROLLER.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CACHE_CONTROLLER.tcl 10 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; 12 | } else { 13 | PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | ISEStep( "vivado", 26 | "-log CACHE_CONTROLLER.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CACHE_CONTROLLER.tcl" ); 27 | 28 | 29 | 30 | function EAInclude( EAInclFilename ) { 31 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 32 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 33 | var EAIFContents = EAInclFile.ReadAll(); 34 | EAInclFile.Close(); 35 | return EAIFContents; 36 | } 37 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin 15 | else 16 | PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | EAStep vivado -log CACHE_CONTROLLER.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CACHE_CONTROLLER.tcl 44 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 17:13:57 2019 6 | # Process ID: 18252 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1 8 | # Command line: vivado.exe -log CACHE_CONTROLLER.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CACHE_CONTROLLER.tcl 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/CACHE_CONTROLLER.vds 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source CACHE_CONTROLLER.tcl -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/vivado.pb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/TB_READ.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/TB_READ_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/TB_READ_behav.wdb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/TB_READ_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../Cache_Controller_FPGA_Implementation_Project.srcs/sources_1/new/CACHE_CONTROLLER.v" \ 4 | "../../../../Cache_Controller_FPGA_Implementation_Project.srcs/sim_1/new/TB_READ.v" \ 5 | 6 | # compile glbl module 7 | verilog xil_defaultlib "glbl.v" 8 | 9 | # Do not sort compile order 10 | nosort 11 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/compile.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2019.1 (64-bit) 4 | REM 5 | REM Filename : compile.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for compiling the simulation design source files 8 | REM 9 | REM Generated by Vivado on Sun Nov 17 16:09:53 +0530 2019 10 | REM SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 11 | REM 12 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: compile.bat 15 | REM 16 | REM **************************************************************************** 17 | echo "xvlog --incr --relax -prj TB_READ_vlog.prj" 18 | call xvlog --incr --relax -prj TB_READ_vlog.prj -log xvlog.log 19 | call type xvlog.log > compile.log 20 | if "%errorlevel%"=="1" goto END 21 | if "%errorlevel%"=="0" goto SUCCESS 22 | :END 23 | exit 1 24 | :SUCCESS 25 | exit 0 26 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/compile.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sources_1/new/CACHE_CONTROLLER.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module CACHE_CONTROLLER 3 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sim_1/new/TB_READ.v" into library xil_defaultlib 4 | INFO: [VRFC 10-311] analyzing module TB_READ 5 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib 6 | INFO: [VRFC 10-311] analyzing module glbl 7 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/elaborate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2019.1 (64-bit) 4 | REM 5 | REM Filename : elaborate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for elaborating the compiled design 8 | REM 9 | REM Generated by Vivado on Sun Nov 17 16:09:56 +0530 2019 10 | REM SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 11 | REM 12 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: elaborate.bat 15 | REM 16 | REM **************************************************************************** 17 | echo "xelab -wto 83766c3071ae4d479e6a6dba0d7b53ba --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot TB_READ_behav xil_defaultlib.TB_READ xil_defaultlib.glbl -log elaborate.log" 18 | call xelab -wto 83766c3071ae4d479e6a6dba0d7b53ba --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot TB_READ_behav xil_defaultlib.TB_READ xil_defaultlib.glbl -log elaborate.log 19 | if "%errorlevel%"=="0" goto SUCCESS 20 | if "%errorlevel%"=="1" goto END 21 | :END 22 | exit 1 23 | :SUCCESS 24 | exit 0 25 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/elaborate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2019.1 2 | Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. 3 | Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 83766c3071ae4d479e6a6dba0d7b53ba --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot TB_READ_behav xil_defaultlib.TB_READ xil_defaultlib.glbl -log elaborate.log 4 | Using 2 slave threads. 5 | Starting static elaboration 6 | Completed static elaboration 7 | Starting simulation data flow analysis 8 | Completed simulation data flow analysis 9 | Time Resolution for simulation is 1ps 10 | Compiling module xil_defaultlib.CACHE_CONTROLLER 11 | Compiling module xil_defaultlib.TB_READ 12 | Compiling module xil_defaultlib.glbl 13 | Built simulation snapshot TB_READ_behav 14 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/simulate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2019.1 (64-bit) 4 | REM 5 | REM Filename : simulate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for simulating the design by launching the simulator 8 | REM 9 | REM Generated by Vivado on Sun Nov 17 16:10:01 +0530 2019 10 | REM SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 11 | REM 12 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: simulate.bat 15 | REM 16 | REM **************************************************************************** 17 | echo "xsim TB_READ_behav -key {Behavioral:sim_1:Functional:TB_READ} -tclbatch TB_READ.tcl -log simulate.log" 18 | call xsim TB_READ_behav -key {Behavioral:sim_1:Functional:TB_READ} -tclbatch TB_READ.tcl -log simulate.log 19 | if "%errorlevel%"=="0" goto SUCCESS 20 | if "%errorlevel%"=="1" goto END 21 | :END 22 | exit 1 23 | :SUCCESS 24 | exit 0 25 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/simulate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2019.1 2 | Time resolution is 1 ps 3 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/tb_CACHE_CONTROLLER.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/tb_CACHE_CONTROLLER_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/tb_CACHE_CONTROLLER_behav.wdb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/tb_CACHE_CONTROLLER_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../L1_Cache.srcs/sources_1/new/CACHE_CONTROLLER.v" \ 4 | "../../../../L1_Cache.srcs/sources_1/new/Cache_memory.v" \ 5 | "../../../../L1_Cache.srcs/sources_1/new/MAIN_MEMORY.v" \ 6 | "../../../../L1_Cache.srcs/sim_1/new/tb_CACHE_CONTROLLER.v" \ 7 | 8 | # compile glbl module 9 | verilog xil_defaultlib "glbl.v" 10 | 11 | # Do not sort compile order 12 | nosort 13 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:21:03 2019 6 | # Process ID: 14204 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:21:03 2019 6 | # Process ID: 14204 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | couldn't read file "C:/Users/RAGHAV/Desktop/Cache": no such file or directory 14 | INFO: [Common 17-206] Exiting Webtalk at Sun Nov 17 16:21:03 2019... 15 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_16080.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:10:00 2019 6 | # Process ID: 16080 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_16080.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:10:00 2019 6 | # Process ID: 16080 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | couldn't read file "C:/Users/RAGHAV/Desktop/Cache": no such file or directory 14 | INFO: [Common 17-206] Exiting Webtalk at Sun Nov 17 16:10:00 2019... 15 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_1788.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sat Nov 16 04:59:06 2019 6 | # Process ID: 1788 7 | # Current directory: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/DS -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_1788.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sat Nov 16 04:59:06 2019 6 | # Process ID: 1788 7 | # Current directory: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/DS -notrace 13 | invalid command name "%" 14 | while executing 15 | "% Total % Received % Xferd Average Speed Time Time Time Current" 16 | (file "C:/Users/RAGHAV/Desktop/DS" line 1) 17 | INFO: [Common 17-206] Exiting Webtalk at Sat Nov 16 04:59:06 2019... 18 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_23044.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 15:21:52 2019 6 | # Process ID: 23044 7 | # Current directory: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/DS -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_23044.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 15:21:52 2019 6 | # Process ID: 23044 7 | # Current directory: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/DS -notrace 13 | invalid command name "%" 14 | while executing 15 | "% Total % Received % Xferd Average Speed Time Time Time Current" 16 | (file "C:/Users/RAGHAV/Desktop/DS" line 1) 17 | INFO: [Common 17-206] Exiting Webtalk at Sun Nov 17 15:21:52 2019... 18 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_26168.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sat Nov 16 05:48:36 2019 6 | # Process ID: 26168 7 | # Current directory: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/DS -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_26168.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sat Nov 16 05:48:36 2019 6 | # Process ID: 26168 7 | # Current directory: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/DS -notrace 13 | invalid command name "%" 14 | while executing 15 | "% Total % Received % Xferd Average Speed Time Time Time Current" 16 | (file "C:/Users/RAGHAV/Desktop/DS" line 1) 17 | INFO: [Common 17-206] Exiting Webtalk at Sat Nov 16 05:48:36 2019... 18 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_27976.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Mon Nov 11 00:48:44 2019 6 | # Process ID: 27976 7 | # Current directory: C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_27976.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Mon Nov 11 00:48:44 2019 6 | # Process ID: 27976 7 | # Current directory: C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-186] 'C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Mon Nov 11 00:48:48 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2019.1/doc/webtalk_introduction.html. 14 | INFO: [Common 17-206] Exiting Webtalk at Mon Nov 11 00:48:48 2019... 15 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "83766c3071ae4d479e6a6dba0d7b53ba" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "TB_READ_behav" "xil_defaultlib.TB_READ" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/obj/xsim_0.win64.obj: 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/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/.xsim_webtallk.info: -------------------------------------------------------------------------------- 1 | 1573987199 2 | 1573987861 3 | 3 4 | 1 5 | 83766c3071ae4d479e6a6dba0d7b53ba 6 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.dbg -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.mem: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.mem -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.reloc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.reloc -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.rlx: -------------------------------------------------------------------------------- 1 | 2 | { 3 | crc : 823037254652216386 , 4 | ccp_crc : 0 , 5 | cmdline : " -wto 83766c3071ae4d479e6a6dba0d7b53ba --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot TB_READ_behav xil_defaultlib.TB_READ xil_defaultlib.glbl" , 6 | buildDate : "May 24 2019" , 7 | buildTime : "15:06:07" , 8 | linkCmd : "C:\\Xilinx\\Vivado\\2019.1\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_READ_behav/xsimk.exe\" \"xsim.dir/TB_READ_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_READ_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2019.1\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , 9 | aggregate_nets : 10 | [ 11 | ] 12 | } -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.rtti: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.rtti -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.svtype: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.svtype -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.type: -------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.xdbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.xdbg -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimSettings.ini: -------------------------------------------------------------------------------- 1 | [General] 2 | ARRAY_DISPLAY_LIMIT=1024 3 | RADIX=hex 4 | TIME_UNIT=ns 5 | TRACE_LIMIT=65536 6 | VHDL_ENTITY_SCOPE_FILTER=true 7 | VHDL_PACKAGE_SCOPE_FILTER=false 8 | VHDL_BLOCK_SCOPE_FILTER=true 9 | VHDL_PROCESS_SCOPE_FILTER=false 10 | VHDL_PROCEDURE_SCOPE_FILTER=false 11 | VERILOG_MODULE_SCOPE_FILTER=true 12 | VERILOG_PACKAGE_SCOPE_FILTER=false 13 | VERILOG_BLOCK_SCOPE_FILTER=false 14 | VERILOG_TASK_SCOPE_FILTER=false 15 | VERILOG_PROCESS_SCOPE_FILTER=false 16 | INPUT_OBJECT_FILTER=true 17 | OUTPUT_OBJECT_FILTER=true 18 | INOUT_OBJECT_FILTER=true 19 | INTERNAL_OBJECT_FILTER=true 20 | CONSTANT_OBJECT_FILTER=true 21 | VARIABLE_OBJECT_FILTER=true 22 | INPUT_PROTOINST_FILTER=true 23 | OUTPUT_PROTOINST_FILTER=true 24 | INOUT_PROTOINST_FILTER=true 25 | INTERNAL_PROTOINST_FILTER=true 26 | CONSTANT_PROTOINST_FILTER=true 27 | VARIABLE_PROTOINST_FILTER=true 28 | SCOPE_NAME_COLUMN_WIDTH=75 29 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 30 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 31 | OBJECT_NAME_COLUMN_WIDTH=75 32 | OBJECT_VALUE_COLUMN_WIDTH=75 33 | OBJECT_DATA_TYPE_COLUMN_WIDTH=75 34 | PROCESS_NAME_COLUMN_WIDTH=75 35 | PROCESS_TYPE_COLUMN_WIDTH=75 36 | FRAME_INDEX_COLUMN_WIDTH=75 37 | FRAME_NAME_COLUMN_WIDTH=75 38 | FRAME_FILE_NAME_COLUMN_WIDTH=75 39 | FRAME_LINE_NUM_COLUMN_WIDTH=75 40 | LOCAL_NAME_COLUMN_WIDTH=75 41 | LOCAL_VALUE_COLUMN_WIDTH=75 42 | LOCAL_DATA_TYPEPROTO_NAME_COLUMN_WIDTH=0 43 | PROTO_VALUE_COLUMN_WIDTH=0 44 | PROTO_DATA_TYPE_COLUMN_WIDTH=0 45 | INPUT_LOCAL_FILTER=1 46 | OUTPUT_LOCAL_FILTER=1 47 | INOUT_LOCAL_FILTER=1 48 | INTERNAL_LOCAL_FILTER=1 49 | CONSTANT_LOCAL_FILTER=1 50 | VARIABLE_LOCAL_FILTER=1 51 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimcrash.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimcrash.log -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimk.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimk.exe -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimkernel.log: -------------------------------------------------------------------------------- 1 | Running: xsim.dir/TB_READ_behav/xsimk.exe -simmode gui -wdb TB_READ_behav.wdb -simrunnum 0 -socket 50277 2 | Design successfully loaded 3 | Design Loading Memory Usage: 5616 KB (Peak: 5616 KB) 4 | Design Loading CPU Usage: 15 ms 5 | Simulation completed 6 | Simulation Memory Usage: 6312 KB (Peak: 6312 KB) 7 | Simulation CPU Usage: 15 ms 8 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/@c@a@c@h@e_@c@o@n@t@r@o@l@l@e@r.sdb: -------------------------------------------------------------------------------- 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/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx: -------------------------------------------------------------------------------- 1 | 0.6 2 | 2019.1 3 | May 24 2019 4 | 15:06:07 5 | C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/glbl.v,1573412823,verilog,,,,glbl,,,,,,,, 6 | C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sim_1/new/TB_READ.v,1573412824,verilog,,,,TB_READ,,,,,,,, 7 | C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sources_1/new/CACHE_CONTROLLER.v,1573984909,verilog,,C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sim_1/new/TB_READ.v,,CACHE_CONTROLLER,,,,,,,, 8 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.ini: -------------------------------------------------------------------------------- 1 | xil_defaultlib=xsim.dir/xil_defaultlib 2 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xvlog.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sources_1/new/CACHE_CONTROLLER.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module CACHE_CONTROLLER 3 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sim_1/new/TB_READ.v" into library xil_defaultlib 4 | INFO: [VRFC 10-311] analyzing module TB_READ 5 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib 6 | INFO: [VRFC 10-311] analyzing module glbl 7 | -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xvlog.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xvlog.pb -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sim_1/new/TB_READ.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18.10.2019 05:13:39 7 | // Design Name: 8 | // Module Name: TB_READ 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module TB_READ(); 24 | 25 | reg [10:0] address; 26 | reg [3:0] data; 27 | reg mode, clk; 28 | wire [3:0] output_data; 29 | wire hit1, hit2; 30 | wire Wait; 31 | wire clk2; 32 | 33 | CACHE_CONTROLLER inst( 34 | .address(address), 35 | .data(data), 36 | .mode(mode), 37 | .clk(clk), 38 | .output_data(output_data), 39 | .hit1(hit1), 40 | .hit2(hit2), 41 | .Wait(Wait), 42 | .clk2(clk2) 43 | ); 44 | 45 | initial 46 | begin 47 | clk = 1'b1; 48 | 49 | address = 11'b00000001101; //Block 3, byte 1 50 | data = 4'b1110; 51 | mode = 1'b1; //write 52 | 53 | #50 54 | address = 11'b00000101110; //Block 11, byte 2 55 | data = 4'b0001; 56 | mode = 1'b0; //read 57 | 58 | #50 59 | address = 11'b00000101110; //Block 11, byte 2 60 | data = 4'b0110; 61 | mode = 1'b1; //write 62 | 63 | #50 64 | address = 11'b00000001101; //Block 3, byte 1 65 | data = 4'b0001; 66 | mode = 1'b0; //read 67 | 68 | #50 69 | address = 11'b00000101111; //Block 11, byte 3 70 | data = 4'b1111; 71 | mode = 1'b1; //read 72 | 73 | end 74 | 75 | always #25 clk = ~clk; 76 | endmodule -------------------------------------------------------------------------------- /Cache_Controller_FPGA_Implementation_Project/vivado_11816.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:07:45 2019 6 | # Process ID: 11816 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project 8 | # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent24488 C:\Users\RAGHAV\Desktop\Cache Controller\Cache_Controller_FPGA_Implementation_Project\Cache_Controller_FPGA_Implementation_Project.xpr 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/vivado.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project\vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project {C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.xpr} 14 | update_compile_order -fileset sources_1 15 | launch_simulation 16 | source TB_READ.tcl 17 | close_sim 18 | -------------------------------------------------------------------------------- /Cache_Controller_Poster.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Poster.pdf -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3131:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:33:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 5 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:31:00:00 6 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766570726f6a6563746173:39:00:00 7 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:32:00:00 8 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:37:00:00 9 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:37:00:00 10 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:313033:00:00 11 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:77617665666f726d73617665636f6e66696775726174696f6e:31:00:00 12 | eof:1793722596 13 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:18 3 | eof: 4 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:241934075 5 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.hw/Cache_Controller_Simulation_Project.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/TB_2.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/TB_2_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/TB_2_behav.wdb -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/TB_2_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../cache_controller_final_stimulation.srcs/sources_1/new/CACHE_CONTROLLER.v" \ 4 | "../../../../cache_controller_final_stimulation.srcs/sources_1/new/L1_CACHE_MEMORY.v" \ 5 | "../../../../cache_controller_final_stimulation.srcs/sources_1/new/L2_CACHE_MEMORY.v" \ 6 | "../../../../cache_controller_final_stimulation.srcs/sources_1/new/MAIN_MEMORY.v" \ 7 | "../../../../cache_controller_final_stimulation.srcs/sim_1/new/TB_2.v" \ 8 | 9 | # compile glbl module 10 | verilog xil_defaultlib "glbl.v" 11 | 12 | # Do not sort compile order 13 | nosort 14 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/TB_READ.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/TB_READ_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/TB_READ_behav.wdb -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/TB_READ_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../Cache_Controller_Simulation_Project.srcs/sources_1/new/CACHE_CONTROLLER.v" \ 4 | "../../../../Cache_Controller_Simulation_Project.srcs/sources_1/new/L1_CACHE_MEMORY.v" \ 5 | "../../../../Cache_Controller_Simulation_Project.srcs/sources_1/new/L2_CACHE_MEMORY.v" \ 6 | "../../../../Cache_Controller_Simulation_Project.srcs/sources_1/new/MAIN_MEMORY.v" \ 7 | "../../../../Cache_Controller_Simulation_Project.srcs/sim_1/new/TB_READ.v" \ 8 | 9 | # compile glbl module 10 | verilog xil_defaultlib "glbl.v" 11 | 12 | # Do not sort compile order 13 | nosort 14 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/compile.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2019.1 (64-bit) 4 | REM 5 | REM Filename : compile.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for compiling the simulation design source files 8 | REM 9 | REM Generated by Vivado on Sun Nov 17 16:08:21 +0530 2019 10 | REM SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 11 | REM 12 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: compile.bat 15 | REM 16 | REM **************************************************************************** 17 | echo "xvlog --incr --relax -prj TB_READ_vlog.prj" 18 | call xvlog --incr --relax -prj TB_READ_vlog.prj -log xvlog.log 19 | call type xvlog.log > compile.log 20 | if "%errorlevel%"=="1" goto END 21 | if "%errorlevel%"=="0" goto SUCCESS 22 | :END 23 | exit 1 24 | :SUCCESS 25 | exit 0 26 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/compile.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/CACHE_CONTROLLER.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module CACHE_CONTROLLER 3 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/L1_CACHE_MEMORY.v" into library xil_defaultlib 4 | INFO: [VRFC 10-311] analyzing module L1_CACHE_MEMORY 5 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/L2_CACHE_MEMORY.v" into library xil_defaultlib 6 | INFO: [VRFC 10-311] analyzing module L2_CACHE_MEMORY 7 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/MAIN_MEMORY.v" into library xil_defaultlib 8 | INFO: [VRFC 10-311] analyzing module MAIN_MEMORY 9 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sim_1/new/TB_READ.v" into library xil_defaultlib 10 | INFO: [VRFC 10-311] analyzing module TB_READ 11 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib 12 | INFO: [VRFC 10-311] analyzing module glbl 13 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/elaborate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2019.1 (64-bit) 4 | REM 5 | REM Filename : elaborate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for elaborating the compiled design 8 | REM 9 | REM Generated by Vivado on Sun Nov 17 16:08:23 +0530 2019 10 | REM SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 11 | REM 12 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: elaborate.bat 15 | REM 16 | REM **************************************************************************** 17 | echo "xelab -wto 3b9e8922936a4e8cafb827006c3881f3 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot TB_READ_behav xil_defaultlib.TB_READ xil_defaultlib.glbl -log elaborate.log" 18 | call xelab -wto 3b9e8922936a4e8cafb827006c3881f3 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot TB_READ_behav xil_defaultlib.TB_READ xil_defaultlib.glbl -log elaborate.log 19 | if "%errorlevel%"=="0" goto SUCCESS 20 | if "%errorlevel%"=="1" goto END 21 | :END 22 | exit 1 23 | :SUCCESS 24 | exit 0 25 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/elaborate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2019.1 2 | Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. 3 | Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 3b9e8922936a4e8cafb827006c3881f3 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot TB_READ_behav xil_defaultlib.TB_READ xil_defaultlib.glbl -log elaborate.log 4 | Using 2 slave threads. 5 | Starting static elaboration 6 | Completed static elaboration 7 | Starting simulation data flow analysis 8 | Completed simulation data flow analysis 9 | Time Resolution for simulation is 1ps 10 | Compiling module xil_defaultlib.MAIN_MEMORY 11 | Compiling module xil_defaultlib.L1_CACHE_MEMORY 12 | Compiling module xil_defaultlib.L2_CACHE_MEMORY 13 | Compiling module xil_defaultlib.CACHE_CONTROLLER 14 | Compiling module xil_defaultlib.TB_READ 15 | Compiling module xil_defaultlib.glbl 16 | Built simulation snapshot TB_READ_behav 17 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/simulate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2019.1 (64-bit) 4 | REM 5 | REM Filename : simulate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for simulating the design by launching the simulator 8 | REM 9 | REM Generated by Vivado on Sun Nov 17 16:08:29 +0530 2019 10 | REM SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 11 | REM 12 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: simulate.bat 15 | REM 16 | REM **************************************************************************** 17 | echo "xsim TB_READ_behav -key {Behavioral:sim_1:Functional:TB_READ} -tclbatch TB_READ.tcl -log simulate.log" 18 | call xsim TB_READ_behav -key {Behavioral:sim_1:Functional:TB_READ} -tclbatch TB_READ.tcl -log simulate.log 19 | if "%errorlevel%"=="0" goto SUCCESS 20 | if "%errorlevel%"=="1" goto END 21 | :END 22 | exit 1 23 | :SUCCESS 24 | exit 0 25 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/tb_CACHE_CONTROLLER.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/tb_CACHE_CONTROLLER_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/tb_CACHE_CONTROLLER_behav.wdb -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/tb_CACHE_CONTROLLER_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../L1_Cache.srcs/sources_1/new/CACHE_CONTROLLER.v" \ 4 | "../../../../L1_Cache.srcs/sources_1/new/Cache_memory.v" \ 5 | "../../../../L1_Cache.srcs/sources_1/new/MAIN_MEMORY.v" \ 6 | "../../../../L1_Cache.srcs/sim_1/new/tb_CACHE_CONTROLLER.v" \ 7 | 8 | # compile glbl module 9 | verilog xil_defaultlib "glbl.v" 10 | 11 | # Do not sort compile order 12 | nosort 13 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:09:18 2019 6 | # Process ID: 13156 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:09:18 2019 6 | # Process ID: 13156 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | couldn't read file "C:/Users/RAGHAV/Desktop/Cache": no such file or directory 14 | INFO: [Common 17-206] Exiting Webtalk at Sun Nov 17 16:09:18 2019... 15 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk_12708.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Mon Nov 11 00:58:26 2019 6 | # Process ID: 12708 7 | # Current directory: C:/Users/Sachin/Documents/cache_controller_final_stimulation/cache_controller_final_stimulation.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/Sachin/Documents/cache_controller_final_stimulation/cache_controller_final_stimulation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/Sachin/Documents/cache_controller_final_stimulation/cache_controller_final_stimulation.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/Sachin/Documents/cache_controller_final_stimulation/cache_controller_final_stimulation.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/Sachin/Documents/cache_controller_final_stimulation/cache_controller_final_stimulation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk_20724.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 15:19:59 2019 6 | # Process ID: 20724 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk_20724.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 15:19:59 2019 6 | # Process ID: 20724 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | couldn't read file "C:/Users/RAGHAV/Desktop/Cache": no such file or directory 14 | INFO: [Common 17-206] Exiting Webtalk at Sun Nov 17 15:19:59 2019... 15 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk_23072.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Mon Nov 11 01:22:40 2019 6 | # Process ID: 23072 7 | # Current directory: C:/Users/Sachin/Documents/cache_controller_final_stimulation/cache_controller_final_stimulation.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/Sachin/Documents/cache_controller_final_stimulation/cache_controller_final_stimulation.sim/sim_1/behav/xsim/xsim.dir/TB_2_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/Sachin/Documents/cache_controller_final_stimulation/cache_controller_final_stimulation.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/Sachin/Documents/cache_controller_final_stimulation/cache_controller_final_stimulation.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/Sachin/Documents/cache_controller_final_stimulation/cache_controller_final_stimulation.sim/sim_1/behav/xsim/xsim.dir/TB_2_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-186] 'C:/Users/Sachin/Documents/cache_controller_final_stimulation/cache_controller_final_stimulation.sim/sim_1/behav/xsim/xsim.dir/TB_2_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Mon Nov 11 01:22:44 2019. For additional details about this file, please refer to the WebTalk help file at D:/Xilinx/Vivado/2019.1/doc/webtalk_introduction.html. 14 | INFO: [Common 17-206] Exiting Webtalk at Mon Nov 11 01:22:44 2019... 15 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk_26484.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 15:14:10 2019 6 | # Process ID: 26484 7 | # Current directory: C:/Users/RAGHAV/Downloads/SIMULATION_ENDGAME/SIMULATION_ENDGAME.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Downloads/SIMULATION_ENDGAME/SIMULATION_ENDGAME.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Downloads/SIMULATION_ENDGAME/SIMULATION_ENDGAME.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Downloads/SIMULATION_ENDGAME/SIMULATION_ENDGAME.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Downloads/SIMULATION_ENDGAME/SIMULATION_ENDGAME.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk_26484.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 15:14:10 2019 6 | # Process ID: 26484 7 | # Current directory: C:/Users/RAGHAV/Downloads/SIMULATION_ENDGAME/SIMULATION_ENDGAME.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Downloads/SIMULATION_ENDGAME/SIMULATION_ENDGAME.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Downloads/SIMULATION_ENDGAME/SIMULATION_ENDGAME.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Downloads/SIMULATION_ENDGAME/SIMULATION_ENDGAME.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Downloads/SIMULATION_ENDGAME/SIMULATION_ENDGAME.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-186] 'C:/Users/RAGHAV/Downloads/SIMULATION_ENDGAME/SIMULATION_ENDGAME.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Sun Nov 17 15:14:17 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2019.1/doc/webtalk_introduction.html. 14 | webtalk_transmit: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 109.375 ; gain = 17.832 15 | INFO: [Common 17-206] Exiting Webtalk at Sun Nov 17 15:14:17 2019... 16 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk_7160.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:08:29 2019 6 | # Process ID: 7160 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk_7160.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:08:29 2019 6 | # Process ID: 7160 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | couldn't read file "C:/Users/RAGHAV/Desktop/Cache": no such file or directory 14 | INFO: [Common 17-206] Exiting Webtalk at Sun Nov 17 16:08:29 2019... 15 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk_9828.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 15:19:25 2019 6 | # Process ID: 9828 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/webtalk_9828.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 15:19:25 2019 6 | # Process ID: 9828 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation/Cache_Controller_Simulation.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | couldn't read file "C:/Users/RAGHAV/Desktop/Cache": no such file or directory 14 | INFO: [Common 17-206] Exiting Webtalk at Sun Nov 17 15:19:25 2019... 15 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "3b9e8922936a4e8cafb827006c3881f3" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "TB_READ_behav" "xil_defaultlib.TB_READ" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/obj/xsim_0.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/obj/xsim_0.win64.obj -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/obj/xsim_1.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/obj/xsim_1.win64.obj -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/.xsim_webtallk.info: -------------------------------------------------------------------------------- 1 | 1573987107 2 | 1573987156 3 | 3 4 | 1 5 | 3b9e8922936a4e8cafb827006c3881f3 6 | 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https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.mem -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.reloc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.reloc -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.rlx: -------------------------------------------------------------------------------- 1 | 2 | { 3 | crc : 578852789634533302 , 4 | ccp_crc : 0 , 5 | cmdline : " -wto 3b9e8922936a4e8cafb827006c3881f3 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot TB_READ_behav xil_defaultlib.TB_READ xil_defaultlib.glbl" , 6 | buildDate : "May 24 2019" , 7 | buildTime : "15:06:07" , 8 | linkCmd : "C:\\Xilinx\\Vivado\\2019.1\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_READ_behav/xsimk.exe\" \"xsim.dir/TB_READ_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_READ_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2019.1\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , 9 | aggregate_nets : 10 | [ 11 | ] 12 | } -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.rtti: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.rtti -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.svtype: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.svtype -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.type: -------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.xdbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.xdbg -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimSettings.ini: -------------------------------------------------------------------------------- 1 | [General] 2 | ARRAY_DISPLAY_LIMIT=1024 3 | RADIX=hex 4 | TIME_UNIT=ns 5 | TRACE_LIMIT=65536 6 | VHDL_ENTITY_SCOPE_FILTER=true 7 | VHDL_PACKAGE_SCOPE_FILTER=false 8 | VHDL_BLOCK_SCOPE_FILTER=true 9 | VHDL_PROCESS_SCOPE_FILTER=false 10 | VHDL_PROCEDURE_SCOPE_FILTER=false 11 | VERILOG_MODULE_SCOPE_FILTER=true 12 | VERILOG_PACKAGE_SCOPE_FILTER=false 13 | VERILOG_BLOCK_SCOPE_FILTER=false 14 | VERILOG_TASK_SCOPE_FILTER=false 15 | VERILOG_PROCESS_SCOPE_FILTER=false 16 | INPUT_OBJECT_FILTER=true 17 | OUTPUT_OBJECT_FILTER=true 18 | INOUT_OBJECT_FILTER=true 19 | INTERNAL_OBJECT_FILTER=true 20 | CONSTANT_OBJECT_FILTER=true 21 | VARIABLE_OBJECT_FILTER=true 22 | INPUT_PROTOINST_FILTER=true 23 | OUTPUT_PROTOINST_FILTER=true 24 | INOUT_PROTOINST_FILTER=true 25 | INTERNAL_PROTOINST_FILTER=true 26 | CONSTANT_PROTOINST_FILTER=true 27 | VARIABLE_PROTOINST_FILTER=true 28 | SCOPE_NAME_COLUMN_WIDTH=75 29 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 30 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 31 | OBJECT_NAME_COLUMN_WIDTH=75 32 | OBJECT_VALUE_COLUMN_WIDTH=75 33 | OBJECT_DATA_TYPE_COLUMN_WIDTH=75 34 | PROCESS_NAME_COLUMN_WIDTH=75 35 | PROCESS_TYPE_COLUMN_WIDTH=75 36 | FRAME_INDEX_COLUMN_WIDTH=75 37 | FRAME_NAME_COLUMN_WIDTH=75 38 | FRAME_FILE_NAME_COLUMN_WIDTH=75 39 | FRAME_LINE_NUM_COLUMN_WIDTH=75 40 | LOCAL_NAME_COLUMN_WIDTH=75 41 | LOCAL_VALUE_COLUMN_WIDTH=75 42 | LOCAL_DATA_TYPEPROTO_NAME_COLUMN_WIDTH=0 43 | PROTO_VALUE_COLUMN_WIDTH=0 44 | PROTO_DATA_TYPE_COLUMN_WIDTH=0 45 | INPUT_LOCAL_FILTER=1 46 | OUTPUT_LOCAL_FILTER=1 47 | INOUT_LOCAL_FILTER=1 48 | INTERNAL_LOCAL_FILTER=1 49 | CONSTANT_LOCAL_FILTER=1 50 | VARIABLE_LOCAL_FILTER=1 51 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimcrash.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimcrash.log -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimk.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimk.exe -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimkernel.log: -------------------------------------------------------------------------------- 1 | Running: xsim.dir/TB_READ_behav/xsimk.exe -simmode gui -wdb TB_READ_behav.wdb -simrunnum 0 -socket 50084 2 | Design successfully loaded 3 | Design Loading Memory Usage: 5724 KB (Peak: 5724 KB) 4 | Design Loading CPU Usage: 46 ms 5 | Simulation completed 6 | Simulation Memory Usage: 6540 KB (Peak: 6540 KB) 7 | Simulation CPU Usage: 61 ms 8 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/@c@a@c@h@e_@c@o@n@t@r@o@l@l@e@r.sdb: -------------------------------------------------------------------------------- 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Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sim_1/new/TB_READ.v,1573987098,verilog,,,,TB_READ,,,,,,,, 7 | C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/CACHE_CONTROLLER.v,1573983804,verilog,,C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/L1_CACHE_MEMORY.v,,CACHE_CONTROLLER,,,,,,,, 8 | C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/L1_CACHE_MEMORY.v,1573983739,verilog,,C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/L2_CACHE_MEMORY.v,,L1_CACHE_MEMORY,,,,,,,, 9 | C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/L2_CACHE_MEMORY.v,1573983739,verilog,,C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/MAIN_MEMORY.v,,L2_CACHE_MEMORY,,,,,,,, 10 | C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/MAIN_MEMORY.v,1573983739,verilog,,C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sim_1/new/TB_READ.v,,MAIN_MEMORY,,,,,,,, 11 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xsim.ini: -------------------------------------------------------------------------------- 1 | xil_defaultlib=xsim.dir/xil_defaultlib 2 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xvlog.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/CACHE_CONTROLLER.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module CACHE_CONTROLLER 3 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/L1_CACHE_MEMORY.v" into library xil_defaultlib 4 | INFO: [VRFC 10-311] analyzing module L1_CACHE_MEMORY 5 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/L2_CACHE_MEMORY.v" into library xil_defaultlib 6 | INFO: [VRFC 10-311] analyzing module L2_CACHE_MEMORY 7 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/MAIN_MEMORY.v" into library xil_defaultlib 8 | INFO: [VRFC 10-311] analyzing module MAIN_MEMORY 9 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sim_1/new/TB_READ.v" into library xil_defaultlib 10 | INFO: [VRFC 10-311] analyzing module TB_READ 11 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib 12 | INFO: [VRFC 10-311] analyzing module glbl 13 | -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xvlog.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.sim/sim_1/behav/xsim/xvlog.pb -------------------------------------------------------------------------------- /Cache_Controller_Simulation_Project/Cache_Controller_Simulation_Project.srcs/sources_1/new/MAIN_MEMORY.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18.10.2019 03:56:56 7 | // Design Name: 8 | // Module Name: MAIN_MEMORY 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module MAIN_MEMORY(); 24 | 25 | parameter no_of_main_memory_blocks=16384; //2^14 No. of lines in main memory 26 | parameter main_memory_block_size=32; //No. of bits in a single line = No. of blocks in a line * no. of bits in a block =1*32=32 27 | parameter no_of_bytes_main_memory_block=4; //No. of bytes in a single given line on main memory ...No. of blocks in a single line * no. of bytes in a block = 1*4=4 28 | parameter byte_size=8; //No. of bits in a byte =8 29 | parameter main_memory_byte_size=65536; //no_of_main_memory_blocks*no_of_bytes_main_memory_block 30 | 31 | reg [main_memory_block_size-1:0]main_memory[0:no_of_main_memory_blocks-1]; 32 | initial 33 | begin: initialization_main_memory 34 | integer i; 35 | for (i=0;i 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.hw/hw_1/hw.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. 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All Rights Reserved. 2 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 4 | | Date : Sun Nov 17 17:18:30 2019 5 | | Host : LAPTOP-V3L8ACTM running 64-bit major release (build 9200) 6 | | Command : report_bus_skew -warn_on_violation -file CACHE_CONTROLLER_bus_skew_routed.rpt -pb CACHE_CONTROLLER_bus_skew_routed.pb -rpx CACHE_CONTROLLER_bus_skew_routed.rpx 7 | | Design : CACHE_CONTROLLER 8 | | Device : 7a35t-cpg236 9 | | Speed File : -1 PRODUCTION 1.23 2018-06-13 10 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 11 | 12 | Bus Skew Report 13 | 14 | No bus skew constraints 15 | 16 | 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Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log CACHE_CONTROLLER.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CACHE_CONTROLLER.tcl -notrace 10 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/init_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/init_design.pb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/opt_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/opt_design.pb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/place_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/place_design.pb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/route_design.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/route_design.pb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; 12 | } else { 13 | PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | // pre-commands: 26 | ISETouchFile( "init_design", "begin" ); 27 | ISEStep( "vivado", 28 | "-log CACHE_CONTROLLER.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CACHE_CONTROLLER.tcl -notrace" ); 29 | 30 | 31 | 32 | 33 | 34 | function EAInclude( EAInclFilename ) { 35 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 36 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 37 | var EAIFContents = EAInclFile.ReadAll(); 38 | EAInclFile.Close(); 39 | return EAIFContents; 40 | } 41 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin 15 | else 16 | PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | # pre-commands: 44 | /bin/touch .init_design.begin.rst 45 | EAStep vivado -log CACHE_CONTROLLER.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CACHE_CONTROLLER.tcl -notrace 46 | 47 | 48 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 17:16:22 2019 6 | # Process ID: 16112 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1 8 | # Command line: vivado.exe -log CACHE_CONTROLLER.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CACHE_CONTROLLER.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/CACHE_CONTROLLER.vdi 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source CACHE_CONTROLLER.tcl -notrace 13 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/vivado.pb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/write_bitstream.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/impl_1/write_bitstream.pb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/CACHE_CONTROLLER.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/CACHE_CONTROLLER.dcp -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/CACHE_CONTROLLER_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/CACHE_CONTROLLER_utilization_synth.pb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log CACHE_CONTROLLER.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CACHE_CONTROLLER.tcl 10 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; 12 | } else { 13 | PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | ISEStep( "vivado", 26 | "-log CACHE_CONTROLLER.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CACHE_CONTROLLER.tcl" ); 27 | 28 | 29 | 30 | function EAInclude( EAInclFilename ) { 31 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 32 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 33 | var EAIFContents = EAInclFile.ReadAll(); 34 | EAInclFile.Close(); 35 | return EAIFContents; 36 | } 37 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin 15 | else 16 | PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | EAStep vivado -log CACHE_CONTROLLER.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CACHE_CONTROLLER.tcl 44 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 17:13:57 2019 6 | # Process ID: 18252 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1 8 | # Command line: vivado.exe -log CACHE_CONTROLLER.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CACHE_CONTROLLER.tcl 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/CACHE_CONTROLLER.vds 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source CACHE_CONTROLLER.tcl -notrace 13 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.runs/synth_1/vivado.pb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/TB_READ.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/TB_READ_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/TB_READ_behav.wdb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/TB_READ_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../Cache_Controller_FPGA_Implementation_Project.srcs/sources_1/new/CACHE_CONTROLLER.v" \ 4 | "../../../../Cache_Controller_FPGA_Implementation_Project.srcs/sim_1/new/TB_READ.v" \ 5 | 6 | # compile glbl module 7 | verilog xil_defaultlib "glbl.v" 8 | 9 | # Do not sort compile order 10 | nosort 11 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/compile.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2019.1 (64-bit) 4 | REM 5 | REM Filename : compile.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for compiling the simulation design source files 8 | REM 9 | REM Generated by Vivado on Sun Nov 17 16:09:53 +0530 2019 10 | REM SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 11 | REM 12 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: compile.bat 15 | REM 16 | REM **************************************************************************** 17 | echo "xvlog --incr --relax -prj TB_READ_vlog.prj" 18 | call xvlog --incr --relax -prj TB_READ_vlog.prj -log xvlog.log 19 | call type xvlog.log > compile.log 20 | if "%errorlevel%"=="1" goto END 21 | if "%errorlevel%"=="0" goto SUCCESS 22 | :END 23 | exit 1 24 | :SUCCESS 25 | exit 0 26 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/compile.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sources_1/new/CACHE_CONTROLLER.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module CACHE_CONTROLLER 3 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sim_1/new/TB_READ.v" into library xil_defaultlib 4 | INFO: [VRFC 10-311] analyzing module TB_READ 5 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib 6 | INFO: [VRFC 10-311] analyzing module glbl 7 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/elaborate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2019.1 (64-bit) 4 | REM 5 | REM Filename : elaborate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for elaborating the compiled design 8 | REM 9 | REM Generated by Vivado on Sun Nov 17 16:09:56 +0530 2019 10 | REM SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 11 | REM 12 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: elaborate.bat 15 | REM 16 | REM **************************************************************************** 17 | echo "xelab -wto 83766c3071ae4d479e6a6dba0d7b53ba --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot TB_READ_behav xil_defaultlib.TB_READ xil_defaultlib.glbl -log elaborate.log" 18 | call xelab -wto 83766c3071ae4d479e6a6dba0d7b53ba --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot TB_READ_behav xil_defaultlib.TB_READ xil_defaultlib.glbl -log elaborate.log 19 | if "%errorlevel%"=="0" goto SUCCESS 20 | if "%errorlevel%"=="1" goto END 21 | :END 22 | exit 1 23 | :SUCCESS 24 | exit 0 25 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/elaborate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2019.1 2 | Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved. 3 | Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 83766c3071ae4d479e6a6dba0d7b53ba --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot TB_READ_behav xil_defaultlib.TB_READ xil_defaultlib.glbl -log elaborate.log 4 | Using 2 slave threads. 5 | Starting static elaboration 6 | Completed static elaboration 7 | Starting simulation data flow analysis 8 | Completed simulation data flow analysis 9 | Time Resolution for simulation is 1ps 10 | Compiling module xil_defaultlib.CACHE_CONTROLLER 11 | Compiling module xil_defaultlib.TB_READ 12 | Compiling module xil_defaultlib.glbl 13 | Built simulation snapshot TB_READ_behav 14 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/simulate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2019.1 (64-bit) 4 | REM 5 | REM Filename : simulate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for simulating the design by launching the simulator 8 | REM 9 | REM Generated by Vivado on Sun Nov 17 16:10:01 +0530 2019 10 | REM SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 11 | REM 12 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: simulate.bat 15 | REM 16 | REM **************************************************************************** 17 | echo "xsim TB_READ_behav -key {Behavioral:sim_1:Functional:TB_READ} -tclbatch TB_READ.tcl -log simulate.log" 18 | call xsim TB_READ_behav -key {Behavioral:sim_1:Functional:TB_READ} -tclbatch TB_READ.tcl -log simulate.log 19 | if "%errorlevel%"=="0" goto SUCCESS 20 | if "%errorlevel%"=="1" goto END 21 | :END 22 | exit 1 23 | :SUCCESS 24 | exit 0 25 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/simulate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2019.1 2 | Time resolution is 1 ps 3 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/tb_CACHE_CONTROLLER.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/tb_CACHE_CONTROLLER_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/tb_CACHE_CONTROLLER_behav.wdb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/tb_CACHE_CONTROLLER_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../L1_Cache.srcs/sources_1/new/CACHE_CONTROLLER.v" \ 4 | "../../../../L1_Cache.srcs/sources_1/new/Cache_memory.v" \ 5 | "../../../../L1_Cache.srcs/sources_1/new/MAIN_MEMORY.v" \ 6 | "../../../../L1_Cache.srcs/sim_1/new/tb_CACHE_CONTROLLER.v" \ 7 | 8 | # compile glbl module 9 | verilog xil_defaultlib "glbl.v" 10 | 11 | # Do not sort compile order 12 | nosort 13 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:21:03 2019 6 | # Process ID: 14204 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:21:03 2019 6 | # Process ID: 14204 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | couldn't read file "C:/Users/RAGHAV/Desktop/Cache": no such file or directory 14 | INFO: [Common 17-206] Exiting Webtalk at Sun Nov 17 16:21:03 2019... 15 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_16080.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:10:00 2019 6 | # Process ID: 16080 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_16080.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:10:00 2019 6 | # Process ID: 16080 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/Cache -notrace 13 | couldn't read file "C:/Users/RAGHAV/Desktop/Cache": no such file or directory 14 | INFO: [Common 17-206] Exiting Webtalk at Sun Nov 17 16:10:00 2019... 15 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_1788.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sat Nov 16 04:59:06 2019 6 | # Process ID: 1788 7 | # Current directory: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/DS -notrace 13 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_1788.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sat Nov 16 04:59:06 2019 6 | # Process ID: 1788 7 | # Current directory: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/DS -notrace 13 | invalid command name "%" 14 | while executing 15 | "% Total % Received % Xferd Average Speed Time Time Time Current" 16 | (file "C:/Users/RAGHAV/Desktop/DS" line 1) 17 | INFO: [Common 17-206] Exiting Webtalk at Sat Nov 16 04:59:06 2019... 18 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_23044.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 15:21:52 2019 6 | # Process ID: 23044 7 | # Current directory: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/DS -notrace 13 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_23044.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 15:21:52 2019 6 | # Process ID: 23044 7 | # Current directory: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/DS -notrace 13 | invalid command name "%" 14 | while executing 15 | "% Total % Received % Xferd Average Speed Time Time Time Current" 16 | (file "C:/Users/RAGHAV/Desktop/DS" line 1) 17 | INFO: [Common 17-206] Exiting Webtalk at Sun Nov 17 15:21:52 2019... 18 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_26168.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sat Nov 16 05:48:36 2019 6 | # Process ID: 26168 7 | # Current directory: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/DS -notrace 13 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_26168.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sat Nov 16 05:48:36 2019 6 | # Process ID: 26168 7 | # Current directory: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/DS Project/video/video.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Desktop/DS -notrace 13 | invalid command name "%" 14 | while executing 15 | "% Total % Received % Xferd Average Speed Time Time Time Current" 16 | (file "C:/Users/RAGHAV/Desktop/DS" line 1) 17 | INFO: [Common 17-206] Exiting Webtalk at Sat Nov 16 05:48:36 2019... 18 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_27976.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Mon Nov 11 00:48:44 2019 6 | # Process ID: 27976 7 | # Current directory: C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/webtalk_27976.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Mon Nov 11 00:48:44 2019 6 | # Process ID: 27976 7 | # Current directory: C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-186] 'C:/Users/RAGHAV/Downloads/Raghav_copy_implementation/Raghav_copy_implementation.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Mon Nov 11 00:48:48 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2019.1/doc/webtalk_introduction.html. 14 | INFO: [Common 17-206] Exiting Webtalk at Mon Nov 11 00:48:48 2019... 15 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "83766c3071ae4d479e6a6dba0d7b53ba" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "TB_READ_behav" "xil_defaultlib.TB_READ" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/obj/xsim_0.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/obj/xsim_0.win64.obj -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/obj/xsim_1.win64.obj: -------------------------------------------------------------------------------- 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-wto 83766c3071ae4d479e6a6dba0d7b53ba --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot TB_READ_behav xil_defaultlib.TB_READ xil_defaultlib.glbl" , 6 | buildDate : "May 24 2019" , 7 | buildTime : "15:06:07" , 8 | linkCmd : "C:\\Xilinx\\Vivado\\2019.1\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_READ_behav/xsimk.exe\" \"xsim.dir/TB_READ_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_READ_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2019.1\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , 9 | aggregate_nets : 10 | [ 11 | ] 12 | } -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsim.rtti: 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-------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimSettings.ini: -------------------------------------------------------------------------------- 1 | [General] 2 | ARRAY_DISPLAY_LIMIT=1024 3 | RADIX=hex 4 | TIME_UNIT=ns 5 | TRACE_LIMIT=65536 6 | VHDL_ENTITY_SCOPE_FILTER=true 7 | VHDL_PACKAGE_SCOPE_FILTER=false 8 | VHDL_BLOCK_SCOPE_FILTER=true 9 | VHDL_PROCESS_SCOPE_FILTER=false 10 | VHDL_PROCEDURE_SCOPE_FILTER=false 11 | VERILOG_MODULE_SCOPE_FILTER=true 12 | VERILOG_PACKAGE_SCOPE_FILTER=false 13 | VERILOG_BLOCK_SCOPE_FILTER=false 14 | VERILOG_TASK_SCOPE_FILTER=false 15 | VERILOG_PROCESS_SCOPE_FILTER=false 16 | INPUT_OBJECT_FILTER=true 17 | OUTPUT_OBJECT_FILTER=true 18 | INOUT_OBJECT_FILTER=true 19 | INTERNAL_OBJECT_FILTER=true 20 | CONSTANT_OBJECT_FILTER=true 21 | VARIABLE_OBJECT_FILTER=true 22 | INPUT_PROTOINST_FILTER=true 23 | OUTPUT_PROTOINST_FILTER=true 24 | INOUT_PROTOINST_FILTER=true 25 | INTERNAL_PROTOINST_FILTER=true 26 | CONSTANT_PROTOINST_FILTER=true 27 | VARIABLE_PROTOINST_FILTER=true 28 | SCOPE_NAME_COLUMN_WIDTH=75 29 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 30 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 31 | OBJECT_NAME_COLUMN_WIDTH=75 32 | OBJECT_VALUE_COLUMN_WIDTH=75 33 | OBJECT_DATA_TYPE_COLUMN_WIDTH=75 34 | PROCESS_NAME_COLUMN_WIDTH=75 35 | PROCESS_TYPE_COLUMN_WIDTH=75 36 | FRAME_INDEX_COLUMN_WIDTH=75 37 | FRAME_NAME_COLUMN_WIDTH=75 38 | FRAME_FILE_NAME_COLUMN_WIDTH=75 39 | FRAME_LINE_NUM_COLUMN_WIDTH=75 40 | LOCAL_NAME_COLUMN_WIDTH=75 41 | LOCAL_VALUE_COLUMN_WIDTH=75 42 | LOCAL_DATA_TYPEPROTO_NAME_COLUMN_WIDTH=0 43 | PROTO_VALUE_COLUMN_WIDTH=0 44 | PROTO_DATA_TYPE_COLUMN_WIDTH=0 45 | INPUT_LOCAL_FILTER=1 46 | OUTPUT_LOCAL_FILTER=1 47 | INOUT_LOCAL_FILTER=1 48 | INTERNAL_LOCAL_FILTER=1 49 | CONSTANT_LOCAL_FILTER=1 50 | VARIABLE_LOCAL_FILTER=1 51 | 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https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimk.exe -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/TB_READ_behav/xsimkernel.log: -------------------------------------------------------------------------------- 1 | Running: xsim.dir/TB_READ_behav/xsimk.exe -simmode gui -wdb TB_READ_behav.wdb -simrunnum 0 -socket 50277 2 | Design successfully loaded 3 | Design Loading Memory Usage: 5616 KB (Peak: 5616 KB) 4 | Design Loading CPU Usage: 15 ms 5 | Simulation completed 6 | Simulation Memory Usage: 6312 KB (Peak: 6312 KB) 7 | Simulation CPU Usage: 15 ms 8 | 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https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/@t@b_@r@e@a@d.sdb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx: -------------------------------------------------------------------------------- 1 | 0.6 2 | 2019.1 3 | May 24 2019 4 | 15:06:07 5 | C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/glbl.v,1573412823,verilog,,,,glbl,,,,,,,, 6 | C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sim_1/new/TB_READ.v,1573412824,verilog,,,,TB_READ,,,,,,,, 7 | C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sources_1/new/CACHE_CONTROLLER.v,1573984909,verilog,,C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sim_1/new/TB_READ.v,,CACHE_CONTROLLER,,,,,,,, 8 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xsim.ini: -------------------------------------------------------------------------------- 1 | xil_defaultlib=xsim.dir/xil_defaultlib 2 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xvlog.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sources_1/new/CACHE_CONTROLLER.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module CACHE_CONTROLLER 3 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sim_1/new/TB_READ.v" into library xil_defaultlib 4 | INFO: [VRFC 10-311] analyzing module TB_READ 5 | INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib 6 | INFO: [VRFC 10-311] analyzing module glbl 7 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xvlog.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/omega-rg/Cache-Controller/771ae5fd38c1736872e44730d34f5de652b5ed0a/Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.sim/sim_1/behav/xsim/xvlog.pb -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.srcs/sim_1/new/TB_READ.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18.10.2019 05:13:39 7 | // Design Name: 8 | // Module Name: TB_READ 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module TB_READ(); 24 | 25 | reg [10:0] address; 26 | reg [3:0] data; 27 | reg mode, clk; 28 | wire [3:0] output_data; 29 | wire hit1, hit2; 30 | wire Wait; 31 | wire clk2; 32 | 33 | CACHE_CONTROLLER inst( 34 | .address(address), 35 | .data(data), 36 | .mode(mode), 37 | .clk(clk), 38 | .output_data(output_data), 39 | .hit1(hit1), 40 | .hit2(hit2), 41 | .Wait(Wait), 42 | .clk2(clk2) 43 | ); 44 | 45 | initial 46 | begin 47 | clk = 1'b1; 48 | 49 | address = 11'b00000001101; //Block 3, byte 1 50 | data = 4'b1110; 51 | mode = 1'b1; //write 52 | 53 | #50 54 | address = 11'b00000101110; //Block 11, byte 2 55 | data = 4'b0001; 56 | mode = 1'b0; //read 57 | 58 | #50 59 | address = 11'b00000101110; //Block 11, byte 2 60 | data = 4'b0110; 61 | mode = 1'b1; //write 62 | 63 | #50 64 | address = 11'b00000001101; //Block 3, byte 1 65 | data = 4'b0001; 66 | mode = 1'b0; //read 67 | 68 | #50 69 | address = 11'b00000101111; //Block 11, byte 3 70 | data = 4'b1111; 71 | mode = 1'b1; //read 72 | 73 | end 74 | 75 | always #25 clk = ~clk; 76 | endmodule -------------------------------------------------------------------------------- /Simulation_Waveforms/Cache_Controller_FPGA_Implementation_Project/vivado_11816.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2019.1 (64-bit) 3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 5 | # Start of session at: Sun Nov 17 16:07:45 2019 6 | # Process ID: 11816 7 | # Current directory: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project 8 | # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent24488 C:\Users\RAGHAV\Desktop\Cache Controller\Cache_Controller_FPGA_Implementation_Project\Cache_Controller_FPGA_Implementation_Project.xpr 9 | # Log file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/vivado.log 10 | # Journal file: C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project\vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project {C:/Users/RAGHAV/Desktop/Cache Controller/Cache_Controller_FPGA_Implementation_Project/Cache_Controller_FPGA_Implementation_Project.xpr} 14 | update_compile_order -fileset sources_1 15 | launch_simulation 16 | source TB_READ.tcl 17 | close_sim 18 | -------------------------------------------------------------------------------- /Simulation_Waveforms/Waveform_1.PNG: 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