├── .gitignore ├── .gitmodules ├── LICENSE ├── PID4063257.pdf ├── README.md ├── board ├── PCB │ ├── Testing_board_CIDIC_rev_aamaya_brd_bot.pdf │ └── Testing_board_CIDIC_rev_aamaya_brd_top.pdf ├── eagle │ └── microAXI │ │ ├── LDO.lbr │ │ ├── PCB1-crop.pdf │ │ ├── PCB1.pdf │ │ ├── PCB2-crop.pdf │ │ ├── PCB2.pdf │ │ ├── Testing_board_CIDIC.pro │ │ ├── Testing_board_CIDIC_rev_aamaya.b## │ │ ├── Testing_board_CIDIC_rev_aamaya.b#1 │ │ ├── Testing_board_CIDIC_rev_aamaya.b#2 │ │ ├── Testing_board_CIDIC_rev_aamaya.b#3 │ │ ├── Testing_board_CIDIC_rev_aamaya.b#4 │ │ ├── Testing_board_CIDIC_rev_aamaya.brd │ │ ├── Testing_board_CIDIC_rev_aamaya.csv │ │ ├── Testing_board_CIDIC_rev_aamaya.s#1 │ │ ├── Testing_board_CIDIC_rev_aamaya.s#2 │ │ ├── Testing_board_CIDIC_rev_aamaya.s#3 │ │ ├── Testing_board_CIDIC_rev_aamaya.s#4 │ │ ├── Testing_board_CIDIC_rev_aamaya.sch │ │ ├── analog_microAXI.lbr │ │ ├── con-usb-3.lbr │ │ ├── crystal30.lbr │ │ ├── gerber_microaxi.zip │ │ ├── opamp.lbr │ │ ├── reg1.lbr │ │ ├── switch_hg.lbr │ │ └── tsmc130_AXI_uC2.lbr └── schematics │ └── Testing_board_CIDIC_rev_aamaya_sch.pdf ├── demo1.pdf ├── fully-synthesized-trng.pdf ├── mriscv.jpg ├── mriscv.pdf ├── mriscv_apb ├── ADC_interface_APB │ ├── ADC_interface_APB.v │ └── ADC_interface_APB_tb.v ├── DAC_interface_APB │ ├── DAC_interface_APB.v │ └── DAC_interface_APB_tb.v ├── GPIO │ ├── decodificador.v │ ├── flipflopRS.v │ ├── flipsdataw.v │ ├── gpioAPB.v │ ├── gpioAPB_tb.v │ ├── latchW.v │ └── macstate2.v ├── README.md ├── axi4_interconnect │ └── axi4_interconnect.v └── impl_axi_apb │ ├── impl_axi_apb.v │ └── impl_axi_apb_tb.v └── mriscv_axi ├── 32-bit-100mhz.pdf ├── ADC_interface_AXI ├── ADC_interface_AXI.v └── ADC_interface_AXI_tb.v ├── AXI_SP32B1024 ├── AXI_SP32B1024.v └── AXI_SP32B1024_tb.v ├── DAC_interface_AXI ├── DAC_interface_AXI.v └── DAC_interface_AXI_tb.v ├── GPIO ├── completogpio.v ├── completogpio_tb.v ├── decodificador.v ├── flipflopRS.v ├── flipsdataw.v ├── latchW.v └── macstate2.v ├── PeripheralRISCV.pptx.pdf ├── README.md ├── Yopuzzlemriscv.pptx.pdf ├── axi4_interconnect ├── axi4_interconnect.v └── axi4_interconnect_tb.v ├── impl_axi ├── impl_axi.v └── impl_axi_tb.v ├── spi_axi_master ├── spi_axi_master.v └── spi_axi_master_tb.v ├── spi_axi_slave ├── spi_axi_slave.v └── spi_axi_slave_tb.v └── util ├── bus_sync_sf.v └── priencr.v /.gitignore: -------------------------------------------------------------------------------- 1 | # Created by https://www.gitignore.io/api/eagle 2 | 3 | ### Eagle ### 4 | # Ignore list for Eagle, a PCB layout tool 5 | 6 | # Backup files 7 | *.s#? 8 | *.b#? 9 | *.l#? 10 | 11 | # Eagle project file 12 | # It contains a serial number and references to the file structure 13 | # on your computer. 14 | # comment the following line if you want to have your project file included. 15 | eagle.epf 16 | 17 | # Autorouter files 18 | *.pro 19 | *.job 20 | 21 | # CAM files 22 | *.$$$ 23 | *.cmp 24 | *.ly2 25 | *.l15 26 | *.sol 27 | *.plc 28 | *.stc 29 | *.sts 30 | *.crc 31 | *.crs 32 | 33 | *.dri 34 | *.drl 35 | *.gpi 36 | *.pls 37 | 38 | *.drd 39 | *.drd.* 40 | 41 | *.info 42 | 43 | *.eps 44 | 45 | # file locks introduced since 7.x 46 | *.lck 47 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "mriscvcore"] 2 | path = mriscvcore 3 | url = https://github.com/onchipuis/mriscvcore.git 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2016 OnchipUIS 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | The MIT License (MIT) 23 | 24 | 25 | 26 | Copyright (c) 2014, The Regents of the University of California (Regents). 27 | All Rights Reserved. 28 | 29 | Redistribution and use in source and binary forms, with or without 30 | modification, are permitted provided that the following conditions are met: 31 | 1. Redistributions of source code must retain the above copyright 32 | notice, this list of conditions and the following disclaimer. 33 | 2. Redistributions in binary form must reproduce the above copyright 34 | notice, this list of conditions and the following disclaimer in the 35 | documentation and/or other materials provided with the distribution. 36 | 3. Neither the name of the Regents nor the 37 | names of its contributors may be used to endorse or promote products 38 | derived from this software without specific prior written permission. 39 | 40 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 41 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING 42 | OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS 43 | BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 44 | 45 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 46 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 47 | PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED 48 | HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE 49 | MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. 50 | -------------------------------------------------------------------------------- /PID4063257.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/PID4063257.pdf -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # mriscv 2 | 3 | Building a pure RV32I Toolchain 4 | ------------------------------- 5 | 6 | The default settings in the [riscv-tools](https://github.com/riscv/riscv-tools) build 7 | scripts will build a compiler, assembler and linker that can target any RISC-V ISA, 8 | but the libraries are built for RV32G and RV64G targets. Follow the instructions 9 | below to build a complete toolchain (including libraries) that target a pure RV32I 10 | CPU. 11 | 12 | The following commands will build the RISC-V gnu toolchain and libraries for a 13 | pure RV32I target, and install it in `/opt/riscv32i`: 14 | 15 | # Ubuntu packages needed: 16 | sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev \ 17 | libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc 18 | 19 | sudo mkdir /opt/riscv32i 20 | sudo chown $USER /opt/riscv32i 21 | 22 | git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i 23 | cd riscv-gnu-toolchain-rv32i 24 | git checkout 7e48594 25 | git submodule update --init --recursive 26 | 27 | mkdir build; cd build 28 | ../configure --with-arch=RV32I --prefix=/opt/riscv32i 29 | make -j$(nproc) 30 | 31 | 32 | The Microcontroller 33 | ------------------- 34 | 35 | The microcontroller is composed by a 32b RISC-V core, a 4KB SRAM, a 10b ADC, a 12b DAC, 8 GPIO, and two SPI interfaces (master and slave). All the modules are conneted using two differente buses: AXI4 and APB. 36 | 37 | ![./mriscv.jpg](./mriscv.jpg) 38 | 39 | 40 | The directory tree is: 41 | 42 | mriscv/mriscv_axi/ADC_interface_AXI -----> ADC interface with the AXI4 bus 43 | 44 | mriscv/mriscv_axi/AXI_SP32B1024 -----> SRAM memory interface 45 | 46 | mriscv/mriscv_axi/DAC_interface_AXI -----> DAC interface with the AXI4 bus 47 | 48 | mriscv/mriscv_axi/axi4_interconnect -----> the AXI4 bus 49 | 50 | mriscv/mriscv_axi/impl_axi -----> the microcontroller 51 | 52 | mriscv/mriscv_axi/spi_axi_master -----> master SPI used for programming 53 | 54 | mriscv/mriscv_axi/spi_axi_slave -----> slave SPI used for data adquisition 55 | 56 | 57 | Development Board 58 | ----------------- 59 | 60 | Also, there are a PCB design for the development board, including circuits for sensing analog signals and the capability to use external clocks. The design is in mriscv/board 61 | 62 | 63 | 64 | 65 | -------------------------------------------------------------------------------- /board/PCB/Testing_board_CIDIC_rev_aamaya_brd_bot.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/board/PCB/Testing_board_CIDIC_rev_aamaya_brd_bot.pdf -------------------------------------------------------------------------------- /board/PCB/Testing_board_CIDIC_rev_aamaya_brd_top.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/board/PCB/Testing_board_CIDIC_rev_aamaya_brd_top.pdf -------------------------------------------------------------------------------- /board/eagle/microAXI/PCB1-crop.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/board/eagle/microAXI/PCB1-crop.pdf -------------------------------------------------------------------------------- /board/eagle/microAXI/PCB1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/board/eagle/microAXI/PCB1.pdf -------------------------------------------------------------------------------- /board/eagle/microAXI/PCB2-crop.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/board/eagle/microAXI/PCB2-crop.pdf -------------------------------------------------------------------------------- /board/eagle/microAXI/PCB2.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/board/eagle/microAXI/PCB2.pdf -------------------------------------------------------------------------------- /board/eagle/microAXI/Testing_board_CIDIC.pro: -------------------------------------------------------------------------------- 1 | EAGLE AutoRouter Statistics: 2 | 3 | Job : /home/hector/eagle/microAXI/Testing_board_CIDIC.brd 4 | 5 | Start at : 23:05:13 (8/2/16) 6 | End at : 23:20:19 (8/2/16) 7 | Elapsed time : 00:15:03 8 | 9 | Signals : 92 RoutingGrid: 3 mil Layers: 2 10 | Connections : 369 predefined: 112 ( 0 Vias ) 11 | 12 | Router memory : 6188352 13 | 14 | Passname : TopRouter Route Optimize1 Optimize2 Optimize3 Optimize4 Optimize5 Optimize6 Optimize7 Optimize8 15 | 16 | Time per pass : 00:07:34 00:01:18 00:00:48 00:00:48 00:00:46 00:00:45 00:00:48 00:00:46 00:00:45 00:00:45 17 | Number of Ripups : 0 13 0 0 0 0 0 0 0 0 18 | max. Level : 0 2 0 0 0 0 0 0 0 0 19 | max. Total : 0 6 0 0 0 0 0 0 0 0 20 | 21 | Routed : 64 241 241 241 242 242 242 242 242 242 22 | Vias : 0 94 104 103 103 99 91 85 85 85 23 | Resolution : 47.7 % 95.7 % 95.7 % 95.7 % 95.9 % 95.9 % 95.9 % 95.9 % 95.9 % 95.9 % 24 | 25 | Final : 94.3% finished. Polygons may have fallen apart. 26 | -------------------------------------------------------------------------------- /board/eagle/microAXI/Testing_board_CIDIC_rev_aamaya.csv: -------------------------------------------------------------------------------- 1 | "Qty";"Value";"Device";"Package";"Parts";"Description";"MF";"MPN";"OC_FARNELL";"OC_NEWARK";"PROD_ID";"TP_SIGNAL_NAME";"VALUE"; 2 | "1";"";"AUDIO-JACK_DIGIKEYSMD";"STEREOJACK2.5MM_SMD";"J1";"3.5mm Audio Jack";"";"";"";"";"CONN-10062";"";""; 3 | "1";"";"JP1E";"JP1";"JP10";"JUMPER";"";"";"";"";"";"";""; 4 | "3";"";"JP2Q";"JP2Q";"JP4, JP11, JP17";"JUMPER";"";"";"";"";"";"";""; 5 | "1";"";"JP2QE";"JP2Q";"JP8";"JUMPER";"";"";"";"";"";"";""; 6 | "2";"";"JP3Q";"JP3Q";"JP13, JP15";"JUMPER";"";"";"";"";"";"";""; 7 | "1";"";"JP3QE";"JP3Q";"JP16";"JUMPER";"";"";"";"";"";"";""; 8 | "1";"";"JP6QE";"JP6Q";"JP3";"JUMPER";"";"";"";"";"";"";""; 9 | "6";"";"LEDCHIPLED_0805";"CHIPLED_0805";"LED3, LED4, LED5, LED6, LED7, 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"5";"10-22uF";"C-EUC0603";"C0603";"C1, C2, C3, C17, C29";"CAPACITOR, European symbol";"";"";"";"";"";"";""; 22 | "2";"100";"R-EU_R0603";"R0603";"R19, R28";"RESISTOR, European symbol";"";"";"";"";"";"";""; 23 | "1";"1000";"R-EU_R0603";"R0603";"R20";"RESISTOR, European symbol";"";"";"";"";"";"";""; 24 | "10";"100n";"C-EUC0603";"C0603";"C4, C5, C6, C7, C8, C9, C11, C12, C35, C37";"CAPACITOR, European symbol";"";"";"";"";"";"";""; 25 | "10";"100nF";"C-EUC0603";"C0603";"C14, C15, C16, C19, C21, C26, C28, C30, C40, C41";"CAPACITOR, European symbol";"";"";"";"";"";"";""; 26 | "11";"10k";"R-EU_R0603";"R0603";"R3, R4, R5, R8, R16, R17, R22, R25, R26, R31, R32";"RESISTOR, European symbol";"";"";"";"";"";"";""; 27 | "11";"10u";"C-EUC0603";"C0603";"C10, C13, C18, C24, C31, C32, C33, C34, C36, C38, C39";"CAPACITOR, European symbol";"";"";"";"";"";"";""; 28 | "1";"1300";"R-EU_R0603";"R0603";"R23";"RESISTOR, European symbol";"";"";"";"";"";"";""; 29 | "8";"1800";"R-EU_R0603";"R0603";"R1, R2, R7, R11, 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"1";"BUZZERNS";"BUZZERNS";"BUZZER-12MM-NS";"SG1";"Buzzer 12mm";"";"";"";"";"";"";""; 40 | "3";"CIDIC_AXI_UC_TEST_DIE";"CIDIC_AXI_UC_TEST_DIE";"CIDIC_AXI_UC_TEST_DIE";"U$1, U$6, U$7";"";"";"";"";"";"";"";""; 41 | "4";"CKN9104CT-NDS";"CKN9104CT-NDS";"SKHMPXE010";"S1, S2, S3, S4";"http://www.digikey.com/product-detail/en/c-k-components/PTS525SM15SMTR2-LFS/CKN9104CT-ND/1146923";"";"";"";"";"";"";""; 42 | "1";"CY22150KFZXC";"CY22150KFZXC";"TSSOP16";"U$4";"";"";"";"";"";"";"";""; 43 | "2";"JUMPERAVDD";"SOLDERJUMPERROUND";"SJ_ROUND";"SJ1, SJ4";"Solder Jumper";"";"";"";"";"";"";""; 44 | "1";"JUMPERDVDD";"SOLDERJUMPERROUND";"SJ_ROUND";"SJ2";"Solder Jumper";"";"";"";"";"";"";""; 45 | "1";"JUMPERLEVEL";"SOLDERJUMPERROUND";"SJ_ROUND";"SJ3";"Solder Jumper";"";"";"";"";"";"";""; 46 | "1";"LEVEL_SHIFTER_8";"LEVEL_SHIFTER_8";"TSSOP20";"U$3";"";"";"";"";"";"";"";""; 47 | "1";"MAX4230";"MAX4230";"SC-70-5";"U1";"310020013";"";"LMV321IDCKR";"";"";"";"";"LMV321IDCKR-sc70-5"; 48 | "1";"MAX4234RU";"MAX4234RU";"TSSOP14";"IC4";"Precision Micropower, Low Noise CMOS, Rail-to-Rail Input/Output Operational Amplifiers";"ALTERA CORPORATION";"AD8609ARUZ";"1464994";"59K6934";"";"";""; 49 | "4";"PTR1B1,27";"PTR1B1,27";"B1,27";"TP_1.2, TP_1.2A, TP_2.5, TP_3.3";"TEST PIN";"";"";"";"";"";"";""; 50 | "13";"TPTP08R";"TPTP08R";"TP08R";"TP26, TP27, TP28, TP29, TP30, TP31, TP32, TP33, TP34, TP35, TP36, TP37, TP38";"Test pad";"";"";"";"";"";"";""; 51 | "31";"TPTP20R";"TPTP20R";"TP20R";"TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11, TP12, TP13, TP14, TP15, TP16, TP17, TP18, TP19, TP20, TP21, TP22, TP23, TP24, TP25, TP39, TP40, TP41, TP42, TP43, TP44";"Test pad";"";"";"";"";"";"";""; 52 | -------------------------------------------------------------------------------- /board/eagle/microAXI/analog_microAXI.lbr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | <b>8-Lead Small Outline IC</b> (SO-8)<p> 62 | Source: http://www.analog.com/UploadedFiles/Data_Sheets/703465986AD8611_2_0.pdf 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | >NAME 79 | >VALUE 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | -------------------------------------------------------------------------------- /board/eagle/microAXI/crystal30.lbr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | >NAME 139 | >VALUE 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | >Name 157 | >Value 158 | 159 | 160 | 161 | 162 | 163 | 164 | Abracon LLC ABM3B-30.000MHZ-B2-T 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | -------------------------------------------------------------------------------- /board/eagle/microAXI/gerber_microaxi.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/board/eagle/microAXI/gerber_microaxi.zip -------------------------------------------------------------------------------- /board/eagle/microAXI/switch_hg.lbr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | <b>6.2 X 6.5mm TACT Switch (SMD)</b><p> 62 | Source: http://www3.alps.co.jp/WebObjects/catalog.woa/PDF/E/Switch/Tact/SKHM/SKHM.PDF 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | >NAME 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | >NAME 116 | >VALUE 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | http://www.digikey.com/product-detail/en/c-k-components/PTS525SM15SMTR2-LFS/CKN9104CT-ND/1146923 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | -------------------------------------------------------------------------------- /board/schematics/Testing_board_CIDIC_rev_aamaya_sch.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/board/schematics/Testing_board_CIDIC_rev_aamaya_sch.pdf -------------------------------------------------------------------------------- /demo1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/demo1.pdf -------------------------------------------------------------------------------- /fully-synthesized-trng.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/fully-synthesized-trng.pdf -------------------------------------------------------------------------------- /mriscv.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/mriscv.jpg -------------------------------------------------------------------------------- /mriscv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/mriscv.pdf -------------------------------------------------------------------------------- /mriscv_apb/ADC_interface_APB/ADC_interface_APB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module ADC_interface_APB(CLK, RST, PWRITE, PSEL, PENABLE, PREADY, PADDR, PWDATA, PSTRB, PRDATA, BUSY, DATA); 3 | 4 | //----general--input---- 5 | input CLK,RST,PWRITE, PSEL, PENABLE; 6 | //----general--output---- 7 | output wire PREADY; 8 | //----write--input---- 9 | input [31:0] PADDR,PWDATA; 10 | input [3:0] PSTRB; 11 | //----write--output---- 12 | 13 | //----write--signals---- 14 | reg state_write; 15 | reg PREADY_W; 16 | //----read--input---- 17 | input [9:0] DATA; 18 | input BUSY; 19 | //----read--output---- 20 | output wire [31:0] PRDATA; 21 | //----read--signals---- 22 | reg state_read, ena_PRDATA; 23 | reg PREADY_R; 24 | reg [9:0] latch_DATA; 25 | 26 | 27 | //----FSM--WRITE---- 28 | 29 | parameter START_W = 1'b0, PREADY_P = 1'b1, START_R = 1'b0, PROCESS = 1'b1; 30 | 31 | //----RESET--PARAMETERS---- 32 | 33 | always @( posedge CLK or negedge RST) 34 | begin 35 | if (~RST) begin 36 | state_write = START_W; 37 | end 38 | //----LOGIC---- 39 | else 40 | begin 41 | case (state_write) 42 | 43 | START_W :if (PSEL & PWRITE & PENABLE == 1'b1) 44 | begin 45 | state_write = PREADY_P; 46 | end 47 | else 48 | begin 49 | state_write = START_W; 50 | end 51 | 52 | PREADY_P: 53 | begin 54 | state_write = START_W; 55 | end 56 | 57 | endcase 58 | end 59 | end 60 | //----OUTPUTS--FSM--WRITE---- 61 | always @(state_write or RST) 62 | begin 63 | if (RST == 1'b0) 64 | begin 65 | PREADY_W = 0; 66 | end 67 | //----LOGIC---- 68 | else 69 | begin 70 | case (state_write) 71 | START_W :begin //----0 72 | PREADY_W = 0; 73 | end 74 | PREADY_P :begin //----1 75 | PREADY_W = 1; 76 | end 77 | endcase 78 | end 79 | end 80 | //----OUTPUT--PREADY----**************************************** 81 | 82 | assign PREADY = PWRITE ? PREADY_W : PREADY_R; 83 | //----FSM--READ---- 84 | 85 | 86 | //----RESET--PARAMETERS---- 87 | always @( posedge CLK or negedge RST) 88 | begin 89 | if (~RST) begin 90 | state_read = START_R; 91 | end 92 | //----LOGIC---- 93 | else 94 | begin 95 | case (state_read) 96 | START_R :if (PSEL & ~PWRITE & PENABLE == 1'b1) 97 | begin 98 | state_read = PROCESS; 99 | end 100 | else 101 | begin 102 | state_read = START_R; 103 | end 104 | 105 | PROCESS: 106 | begin 107 | state_read = START_R; 108 | end 109 | 110 | endcase 111 | end 112 | end 113 | //----OUTPUTS--FSM--READ---- 114 | always @(state_read or RST) 115 | begin 116 | if (RST == 1'b0) 117 | begin 118 | PREADY_R = 0; 119 | ena_PRDATA = 0; 120 | end 121 | 122 | //----LOGIC---- 123 | else 124 | begin 125 | case (state_read) 126 | START_R :begin 127 | PREADY_R = 0; 128 | ena_PRDATA = 0; 129 | end 130 | PROCESS :begin 131 | PREADY_R = 1; 132 | ena_PRDATA = 1; 133 | end 134 | 135 | endcase 136 | end 137 | end 138 | 139 | //----FLIP--FLOPS--WRITE---- 140 | always @( posedge CLK ) 141 | begin 142 | if (~RST) begin 143 | latch_DATA <= 10'b0; 144 | end 145 | else 146 | begin 147 | if (BUSY) 148 | begin 149 | latch_DATA <= DATA; 150 | end 151 | else 152 | begin 153 | latch_DATA <= latch_DATA; 154 | end 155 | end 156 | end 157 | 158 | assign PRDATA = ena_PRDATA ? latch_DATA:10'b0; 159 | 160 | //----OUTPUT--PREADY----**************************************** 161 | 162 | assign PREADY = PWRITE ? PREADY_W : PREADY_R; 163 | 164 | endmodule 165 | 166 | 167 | -------------------------------------------------------------------------------- /mriscv_apb/ADC_interface_APB/ADC_interface_APB_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ADC_interface_APB_tb; 4 | parameter CLKPERIOD = 10; 5 | 6 | reg CLK = 0, RST; 7 | reg PWRITE, PSEL, PENABLE; 8 | reg [31:0] PADDR, PWDATA; 9 | reg [3:0] PSTRB; 10 | reg [9:0] DATA; 11 | reg BUSY; 12 | 13 | wire PREADY; 14 | wire [31:0] PRDATA; 15 | 16 | ADC_interface_APB ADC_interface_APB_inst( 17 | .RST(RST), 18 | .CLK(CLK), 19 | .PWRITE(PWRITE), 20 | .PSEL(PSEL), 21 | .PENABLE(PENABLE), 22 | .PADDR(PADDR), 23 | .PWDATA(PWDATA), 24 | .PSTRB(PSTRB), 25 | .PREADY(PREADY), 26 | .DATA(DATA), 27 | .PRDATA(PRDATA), 28 | .BUSY(BUSY)); 29 | 30 | always 31 | begin 32 | #(CLKPERIOD/2) CLK = ~CLK; 33 | end 34 | 35 | initial begin 36 | 37 | RST <= 1'b0; 38 | 39 | #(CLKPERIOD*20);//-------------------------START_W--AND--START_R 40 | 41 | RST <= 1'b1; 42 | PWRITE <= 1'b0; 43 | PSEL <= 1'b1; 44 | PENABLE <= 1'b1; 45 | PWDATA <= 32'h55555555; 46 | PADDR <= 32'h55555555; 47 | PSTRB <= 4'b1; 48 | BUSY <= 1'b1; 49 | DATA <= 10'b0000001111; 50 | 51 | #(CLKPERIOD*2);//-------------------------WAIT_WVALID--AND--WAIT_RREADY 52 | /* 53 | RST <= 1'b1; 54 | AWVALID <= 1'b0; 55 | WVALID <= 1'b0; 56 | BREADY <= 1'b0; 57 | AWADDR <= 32'b0; 58 | WDATA <= 32'b0; 59 | ARVALID <= 1'b0; 60 | RREADY <= 1'b0; 61 | 62 | #(CLKPERIOD*5);//------------------------- 63 | 64 | RST <= 1'b1; 65 | AWVALID <= 1'b0; 66 | WVALID <= 1'b0; 67 | BREADY <= 1'b0; 68 | AWADDR <= 32'hfffffff1; 69 | WDATA <= 32'h12345678; 70 | ARVALID <= 1'b0; 71 | RREADY <= 1'b0; 72 | 73 | 74 | #(CLKPERIOD*5);//------------------------- 75 | 76 | RST <= 1'bX; 77 | AWVALID <= 1'bX; 78 | WVALID <= 1'bX; 79 | BREADY <= 1'bX; 80 | AWADDR <= 32'bX; 81 | WDATA <= 32'bX; 82 | ARVALID <= 1'bX; 83 | RREADY <= 1'bX; 84 | 85 | 86 | #(CLKPERIOD*5);//------------------------- 87 | 88 | RST <= 1'bZ; 89 | AWVALID <= 1'bZ; 90 | WVALID <= 1'bZ; 91 | BREADY <= 1'bZ; 92 | AWADDR <= 32'bZ; 93 | WDATA <= 32'bZ; 94 | ARVALID <= 1'bZ; 95 | RREADY <= 1'bZ; 96 | 97 | #(CLKPERIOD*5);//------------------------- 98 | */ 99 | RST <= 1'b1; 100 | PWRITE <= 1'b0; 101 | PSEL <= 1'b1; 102 | PENABLE <= 1'b1; 103 | PWDATA <= 32'h44444444; 104 | PADDR <= 32'h55555555; 105 | PSTRB <= 4'b1; 106 | BUSY <= 1'b1; 107 | DATA <= 10'b0000001011; 108 | 109 | 110 | #(CLKPERIOD*2);//-------------------------WORKING--AND--START_R 111 | /* 112 | RST <= 1'b1; 113 | AWVALID <= 1'b0; 114 | WVALID <= 1'b0; 115 | BREADY <= 1'b0; 116 | AWADDR <= 32'b0; 117 | WDATA <= 32'b0; 118 | ARVALID <= 1'b0; 119 | RREADY <= 1'b0; 120 | 121 | #(CLKPERIOD*5);//------------------------- 122 | 123 | RST <= 1'b1; 124 | AWVALID <= 1'b0; 125 | WVALID <= 1'b0; 126 | BREADY <= 1'b0; 127 | AWADDR <= 32'hfffffff1; 128 | WDATA <= 32'h12345678; 129 | ARVALID <= 1'b0; 130 | RREADY <= 1'b0; 131 | 132 | #(CLKPERIOD*5);//------------------------- 133 | 134 | RST <= 1'bX; 135 | AWVALID <= 1'bX; 136 | WVALID <= 1'bX; 137 | BREADY <= 1'b0; 138 | AWADDR <= 32'bX; 139 | WDATA <= 32'bX; 140 | ARVALID <= 1'bX; 141 | RREADY <= 1'bX; 142 | 143 | #(CLKPERIOD*5);//------------------------- 144 | 145 | RST <= 1'bZ; 146 | AWVALID <= 1'bZ; 147 | WVALID <= 1'bZ; 148 | BREADY <= 1'bZ; 149 | AWADDR <= 32'bZ; 150 | WDATA <= 32'bZ; 151 | ARVALID <= 1'bZ; 152 | RREADY <= 1'bZ; 153 | 154 | #(CLKPERIOD*5);//------------------------- 155 | 156 | RST <= 1'b1; 157 | AWVALID <= 1'b0; 158 | WVALID <= 1'b0; 159 | BREADY <= 1'b0; 160 | AWADDR <= 32'b0; 161 | WDATA <= 32'b0; 162 | ARVALID <= 1'b0; 163 | RREADY <= 1'b0; 164 | 165 | #(CLKPERIOD*10); 166 | */ 167 | //----------------------------------reset------------------------ 168 | 169 | RST <= 1'b0; 170 | PWRITE <= 1'b0; 171 | PSEL <= 1'b0; 172 | PENABLE <= 1'b0; 173 | PWDATA <= 32'h0; 174 | PADDR <= 32'h0; 175 | PSTRB <= 4'b0; 176 | BUSY <= 1'b0; 177 | DATA <= 10'b0; 178 | 179 | 180 | #(CLKPERIOD*20);//-------------------------START_R--AND--START_W 181 | /* 182 | RST <= 1'b1; 183 | AWVALID <= 1'b0; 184 | WVALID <= 1'b0; 185 | BREADY <= 1'b0; 186 | AWADDR <= 32'b0; 187 | WDATA <= 32'b0; 188 | ARVALID <= 1'b0; 189 | RREADY <= 1'b0; 190 | 191 | #(CLKPERIOD*5);//------------------------- 192 | 193 | RST <= 1'b1; 194 | AWVALID <= 1'b0; 195 | WVALID <= 1'b0; 196 | BREADY <= 1'b0; 197 | AWADDR <= 32'hfffffff2; 198 | WDATA <= 32'h87654321; 199 | ARVALID <= 1'b0; 200 | RREADY <= 1'b0; 201 | 202 | #(CLKPERIOD*5);//------------------------- 203 | 204 | RST <= 1'bx; 205 | AWVALID <= 1'bx; 206 | WVALID <= 1'bx; 207 | BREADY <= 1'bx; 208 | AWADDR <= 32'bx; 209 | WDATA <= 32'hx; 210 | ARVALID <= 1'bX; 211 | RREADY <= 1'bX; 212 | 213 | #(CLKPERIOD*5);//------------------------- 214 | 215 | RST <= 1'bz; 216 | AWVALID <= 1'bz; 217 | WVALID <= 1'bz; 218 | BREADY <= 1'bz; 219 | AWADDR <= 32'bz; 220 | WDATA <= 32'hz; 221 | ARVALID <= 1'bZ; 222 | RREADY <= 1'bZ; 223 | 224 | #(CLKPERIOD*5);//------------------------- 225 | 226 | RST <= 1'b1; 227 | AWVALID <= 1'b1; 228 | WVALID <= 1'b0; 229 | BREADY <= 1'b0; 230 | AWADDR <= 32'hfffffff2; 231 | WDATA <= 32'h87654321; 232 | ARVALID <= 1'b1; 233 | RREADY <= 1'b0; 234 | 235 | */ 236 | 237 | RST <= 1'b1; 238 | PWRITE <= 1'b0; 239 | PSEL <= 1'b1; 240 | PENABLE <= 1'b1; 241 | PWDATA <= 32'h33333333; 242 | PADDR <= 32'h55555555; 243 | PSTRB <= 4'b1; 244 | BUSY <= 1'b1; 245 | DATA <= 10'b0000000001; 246 | 247 | 248 | #(CLKPERIOD*2);//-------------------------WAIT_WVALID--AND--WAIT_RREADY 249 | /* 250 | RST <= 1'b1; 251 | AWVALID <= 1'b0; 252 | WVALID <= 1'b0; 253 | BREADY <= 1'b0; 254 | AWADDR <= 32'b0; 255 | WDATA <= 32'b0; 256 | ARVALID <= 1'b0; 257 | RREADY <= 1'b0; 258 | 259 | #(CLKPERIOD*5);//------------------------- 260 | 261 | RST <= 1'b1; 262 | AWVALID <= 1'b0; 263 | WVALID <= 1'b0; 264 | BREADY <= 1'b0; 265 | AWADDR <= 32'hfffffff2; 266 | WDATA <= 32'h87654321; 267 | ARVALID <= 1'b0; 268 | RREADY <= 1'b0; 269 | 270 | 271 | #(CLKPERIOD*5);//------------------------- 272 | 273 | RST <= 1'bX; 274 | AWVALID <= 1'bX; 275 | WVALID <= 1'bX; 276 | BREADY <= 1'bX; 277 | AWADDR <= 32'bX; 278 | WDATA <= 32'bX; 279 | ARVALID <= 1'bX; 280 | RREADY <= 1'bX; 281 | 282 | 283 | #(CLKPERIOD*5);//------------------------- 284 | 285 | RST <= 1'bZ; 286 | AWVALID <= 1'bZ; 287 | WVALID <= 1'bZ; 288 | BREADY <= 1'bZ; 289 | AWADDR <= 32'bZ; 290 | WDATA <= 32'bZ; 291 | ARVALID <= 1'bZ; 292 | RREADY <= 1'bZ; 293 | 294 | #(CLKPERIOD*5);//------------------------- 295 | 296 | RST <= 1'b1; 297 | AWVALID <= 1'b0; 298 | WVALID <= 1'b1; 299 | BREADY <= 1'b1; 300 | AWADDR <= 32'hfffffff2; 301 | WDATA <= 32'h87654321; 302 | ARVALID <= 1'b0; 303 | RREADY <= 1'b1; 304 | */ 305 | RST <= 1'b1; 306 | PWRITE <= 1'b0; 307 | PSEL <= 1'b1; 308 | PENABLE <= 1'b1; 309 | PWDATA <= 32'h77777777; 310 | PADDR <= 32'h55555555; 311 | PSTRB <= 4'b1; 312 | BUSY <= 1'b0; 313 | DATA <= 10'b0000001001; 314 | 315 | 316 | #(CLKPERIOD*2);//-------------------------WORKING--AND--START_R 317 | /* 318 | RST <= 1'b1; 319 | AWVALID <= 1'b0; 320 | WVALID <= 1'b0; 321 | BREADY <= 1'b0; 322 | AWADDR <= 32'b0; 323 | WDATA <= 32'b0; 324 | ARVALID <= 1'b0; 325 | RREADY <= 1'b0; 326 | 327 | #(CLKPERIOD*5);//------------------------- 328 | 329 | RST <= 1'b1; 330 | AWVALID <= 1'b0; 331 | WVALID <= 1'b0; 332 | BREADY <= 1'b0; 333 | AWADDR <= 32'hfffffff2; 334 | WDATA <= 32'h87654321; 335 | ARVALID <= 1'b0; 336 | RREADY <= 1'b0; 337 | 338 | #(CLKPERIOD*5);//------------------------- 339 | 340 | RST <= 1'bX; 341 | AWVALID <= 1'bX; 342 | WVALID <= 1'bX; 343 | BREADY <= 1'b0; 344 | AWADDR <= 32'bX; 345 | WDATA <= 32'bX; 346 | ARVALID <= 1'bX; 347 | RREADY <= 1'bX; 348 | 349 | #(CLKPERIOD*5);//------------------------- 350 | 351 | RST <= 1'bZ; 352 | AWVALID <= 1'bZ; 353 | WVALID <= 1'bZ; 354 | BREADY <= 1'bZ; 355 | AWADDR <= 32'bZ; 356 | WDATA <= 32'bZ; 357 | ARVALID <= 1'bZ; 358 | RREADY <= 1'bZ; 359 | 360 | #(CLKPERIOD*5);//------------------------- 361 | 362 | 363 | RST <= 1'b1; 364 | AWVALID <= 1'b0; 365 | WVALID <= 1'b0; 366 | BREADY <= 1'b0; 367 | AWADDR <= 32'b0; 368 | WDATA <= 32'b0; 369 | ARVALID <= 1'b0; 370 | RREADY <= 1'b1; 371 | 372 | #(CLKPERIOD*10) 373 | */ 374 | RST <= 1'b1; 375 | PWRITE <= 1'b0; 376 | PSEL <= 1'b1; 377 | PENABLE <= 1'b1; 378 | PWDATA <= 32'h11111111; 379 | PADDR <= 32'h55555555; 380 | PSTRB <= 4'b1; 381 | BUSY <= 1'b0; 382 | DATA <= 10'b0000000001; 383 | 384 | 385 | //-------------------------START_R--AND--START_W 386 | 387 | //----------------------------------NO--reset------------------------ 388 | 389 | //RST <= 1'b0; 390 | 391 | #(CLKPERIOD*2);//-------------------------START_R--AND--START_W 392 | /* 393 | RST <= 1'b1; 394 | AWVALID <= 1'b0; 395 | WVALID <= 1'b0; 396 | BREADY <= 1'b0; 397 | AWADDR <= 32'b0; 398 | WDATA <= 32'b0; 399 | ARVALID <= 1'b0; 400 | RREADY <= 1'b0; 401 | 402 | #(CLKPERIOD*5);//------------------------- 403 | 404 | RST <= 1'b1; 405 | AWVALID <= 1'b0; 406 | WVALID <= 1'b0; 407 | BREADY <= 1'b0; 408 | AWADDR <= 32'hfffffff3; 409 | WDATA <= 32'h55555555; 410 | ARVALID <= 1'b0; 411 | RREADY <= 1'b0; 412 | 413 | #(CLKPERIOD*5);//------------------------- 414 | 415 | RST <= 1'bx; 416 | AWVALID <= 1'bx; 417 | WVALID <= 1'bx; 418 | BREADY <= 1'bx; 419 | AWADDR <= 32'bx; 420 | WDATA <= 32'hx; 421 | ARVALID <= 1'bX; 422 | RREADY <= 1'bX; 423 | 424 | #(CLKPERIOD*5);//------------------------- 425 | 426 | RST <= 1'bz; 427 | AWVALID <= 1'bz; 428 | WVALID <= 1'bz; 429 | BREADY <= 1'bz; 430 | AWADDR <= 32'bz; 431 | WDATA <= 32'hz; 432 | ARVALID <= 1'bZ; 433 | RREADY <= 1'bZ; 434 | 435 | #(CLKPERIOD*5);//------------------------- 436 | 437 | RST <= 1'b1; 438 | AWVALID <= 1'b1; 439 | WVALID <= 1'b0; 440 | BREADY <= 1'b0; 441 | AWADDR <= 32'hfffffff3; 442 | WDATA <= 32'h55555555; 443 | ARVALID <= 1'b1; 444 | RREADY <= 1'b0; 445 | */ 446 | RST <= 1'b1; 447 | PWRITE <= 1'b0; 448 | PSEL <= 1'b1; 449 | PENABLE <= 1'b1; 450 | PWDATA <= 32'h22222222; 451 | PADDR <= 32'h55555555; 452 | PSTRB <= 4'b1; 453 | BUSY <= 1'b1; 454 | DATA <= 10'b0000011111; 455 | 456 | 457 | #(CLKPERIOD*9);//-------------------------WAIT_WVALID--AND--WAIT_RREADY 458 | /* 459 | RST <= 1'b1; 460 | AWVALID <= 1'b0; 461 | WVALID <= 1'b0; 462 | BREADY <= 1'b0; 463 | AWADDR <= 32'b0; 464 | WDATA <= 32'b0; 465 | ARVALID <= 1'b0; 466 | RREADY <= 1'b0; 467 | 468 | #(CLKPERIOD*5);//------------------------- 469 | 470 | RST <= 1'b1; 471 | AWVALID <= 1'b0; 472 | WVALID <= 1'b0; 473 | BREADY <= 1'b0; 474 | AWADDR <= 32'hfffffff3; 475 | WDATA <= 32'h55555555; 476 | ARVALID <= 1'b0; 477 | RREADY <= 1'b0; 478 | 479 | 480 | #(CLKPERIOD*5);//------------------------- 481 | 482 | RST <= 1'bX; 483 | AWVALID <= 1'bX; 484 | WVALID <= 1'bX; 485 | BREADY <= 1'bX; 486 | AWADDR <= 32'bX; 487 | WDATA <= 32'bX; 488 | ARVALID <= 1'bX; 489 | RREADY <= 1'bX; 490 | 491 | 492 | #(CLKPERIOD*5);//------------------------- 493 | 494 | RST <= 1'bZ; 495 | AWVALID <= 1'bZ; 496 | WVALID <= 1'bZ; 497 | BREADY <= 1'bZ; 498 | AWADDR <= 32'bZ; 499 | WDATA <= 32'bZ; 500 | ARVALID <= 1'bZ; 501 | RREADY <= 1'bZ; 502 | 503 | #(CLKPERIOD*5);//------------------------- 504 | 505 | 506 | RST <= 1'b1; 507 | AWVALID <= 1'b0; 508 | WVALID <= 1'b1; 509 | BREADY <= 1'b1; 510 | AWADDR <= 32'hfffffff3; 511 | WDATA <= 32'h55555555; 512 | ARVALID <= 1'b0; 513 | RREADY <= 1'b1; 514 | 515 | */ 516 | 517 | RST <= 1'b1; 518 | PWRITE <= 1'b0; 519 | PSEL <= 1'b1; 520 | PENABLE <= 1'b1; 521 | PWDATA <= 32'h55555568; 522 | PADDR <= 32'h55555555; 523 | PSTRB <= 4'b1; 524 | BUSY <= 1'b0; 525 | DATA <= 10'b0000000001; 526 | 527 | 528 | #(CLKPERIOD*9);//-------------------------WORKING--AND--START_R 529 | /* 530 | RST <= 1'b1; 531 | AWVALID <= 1'b0; 532 | WVALID <= 1'b0; 533 | BREADY <= 1'b0; 534 | AWADDR <= 32'b0; 535 | WDATA <= 32'b0; 536 | ARVALID <= 1'b0; 537 | RREADY <= 1'b0; 538 | 539 | #(CLKPERIOD*5);//------------------------- 540 | 541 | RST <= 1'b1; 542 | AWVALID <= 1'b0; 543 | WVALID <= 1'b0; 544 | BREADY <= 1'b0; 545 | AWADDR <= 32'hfffffff3; 546 | WDATA <= 32'h55555555; 547 | ARVALID <= 1'b0; 548 | RREADY <= 1'b0; 549 | 550 | #(CLKPERIOD*5);//------------------------- 551 | 552 | RST <= 1'bX; 553 | AWVALID <= 1'bX; 554 | WVALID <= 1'bX; 555 | BREADY <= 1'b0; 556 | AWADDR <= 32'bX; 557 | WDATA <= 32'bX; 558 | ARVALID <= 1'bX; 559 | RREADY <= 1'bX; 560 | 561 | #(CLKPERIOD*5);//------------------------- 562 | 563 | RST <= 1'bZ; 564 | AWVALID <= 1'bZ; 565 | WVALID <= 1'bZ; 566 | BREADY <= 1'bZ; 567 | AWADDR <= 32'bZ; 568 | WDATA <= 32'bZ; 569 | ARVALID <= 1'bZ; 570 | RREADY <= 1'bZ; 571 | 572 | #(CLKPERIOD*5);//------------------------- 573 | 574 | RST <= 1'b1; 575 | AWVALID <= 1'b0; 576 | WVALID <= 1'b0; 577 | BREADY <= 1'b0; 578 | AWADDR <= 32'b0; 579 | WDATA <= 32'b0; 580 | ARVALID <= 1'b0; 581 | RREADY <= 1'b0; 582 | 583 | #(CLKPERIOD*10) 584 | 585 | //-------------------------START--AND--WAIT_RREADY 586 | */ 587 | $finish; 588 | 589 | end 590 | endmodule 591 | -------------------------------------------------------------------------------- /mriscv_apb/DAC_interface_APB/DAC_interface_APB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module DAC_interface_APB(CLK, RST, PWRITE, PSEL, PENABLE, PREADY, PADDR, PWDATA, PSTRB, DATA, PRDATA); 3 | 4 | //----general--input---- 5 | input CLK,RST,PWRITE, PSEL, PENABLE; 6 | //----general--output---- 7 | output wire PREADY; 8 | //----write--input---- 9 | input [31:0] PADDR,PWDATA; 10 | input [3:0] PSTRB; 11 | //----write--output---- 12 | output wire [11:0] DATA; 13 | //----write--signals---- 14 | reg [4:0] delay; 15 | reg [1:0] state_write; 16 | reg [11:0] latch_PWDATA; 17 | reg ena_DATA; 18 | reg PREADY_W; 19 | //----read--output---- 20 | output wire [31:0] PRDATA; 21 | //----read--signals---- 22 | reg state_read, ena_PRDATA; 23 | reg PREADY_R; 24 | 25 | //----FSM--WRITE----****************************************************************** 26 | 27 | parameter START_W = 2'b00, SAVE_PWDATA = 2'b01, WORKING = 2'b10, READY_W = 2'b11, START_R = 1'b0, READY_R = 1'b1; 28 | 29 | //----RESET--PARAMETERS---- 30 | 31 | always @( posedge CLK or negedge RST) 32 | begin 33 | if (RST == 1'b0) begin 34 | state_write = START_W; 35 | delay = 5'b00000; 36 | end 37 | //----LOGIC---- 38 | else 39 | begin 40 | case (state_write) 41 | 42 | START_W :if (PSEL & PWRITE & PENABLE == 1'b1) 43 | begin 44 | state_write = SAVE_PWDATA; 45 | delay = 5'b00000; 46 | end 47 | else 48 | begin 49 | state_write = START_W; 50 | end 51 | 52 | SAVE_PWDATA : 53 | begin 54 | state_write = WORKING; 55 | end 56 | 57 | WORKING : if (delay == 5'b01010) 58 | begin 59 | state_write = READY_W; 60 | end 61 | else 62 | begin 63 | state_write = WORKING; 64 | delay = delay + 5'b00001; 65 | end 66 | READY_W : 67 | begin 68 | state_write = START_W; 69 | end 70 | 71 | endcase 72 | end 73 | end 74 | //----OUTPUTS--FSM--WRITE---- 75 | always @(state_write or RST) 76 | begin 77 | if (RST == 1'b0) 78 | begin 79 | PREADY_W = 0; 80 | ena_DATA = 0; 81 | end 82 | //----LOGIC---- 83 | else 84 | begin 85 | case (state_write) 86 | START_W :begin //----0 87 | PREADY_W = 0; 88 | ena_DATA = 1; 89 | end 90 | SAVE_PWDATA :begin //----1 91 | PREADY_W = 0; 92 | ena_DATA = 1; 93 | end 94 | WORKING :begin //----2 95 | PREADY_W = 0; 96 | ena_DATA = 1; 97 | end 98 | READY_W :begin //----3 99 | PREADY_W = 1; 100 | ena_DATA = 1; 101 | end 102 | 103 | endcase 104 | end 105 | end 106 | 107 | //----FLIP--FLOP--WRITE----*************************************************** 108 | 109 | always @( posedge CLK ) 110 | begin 111 | if (RST == 1'b0) 112 | begin 113 | latch_PWDATA <= 12'b0; 114 | end 115 | else if (PSEL & PWRITE & PENABLE == 1'b1) 116 | begin 117 | latch_PWDATA <= PWDATA; 118 | end 119 | else 120 | begin 121 | latch_PWDATA <= latch_PWDATA; 122 | end 123 | end 124 | 125 | 126 | //----OUTPUT--DATA----****************************************** 127 | 128 | assign DATA = ena_DATA ? latch_PWDATA : 12'b0; 129 | 130 | //----OUTPUT--PREADY----**************************************** 131 | 132 | assign PREADY = PWRITE ? PREADY_W : PREADY_R; 133 | 134 | //----OUTPUT--PRDATA----**************************************** 135 | 136 | assign PRDATA = ena_PRDATA ? 32'h55555555 : 32'b0; 137 | 138 | //----FSM--READ----********************************************** 139 | 140 | 141 | //----RESET--PARAMETERS---- 142 | always @( posedge CLK or negedge RST) 143 | begin 144 | if (RST == 1'b0) begin 145 | state_read = START_R; 146 | end 147 | //----LOGIC---- 148 | else 149 | begin 150 | case (state_read) 151 | START_R :if (PSEL & ~PWRITE & PENABLE == 1'b1) 152 | begin 153 | state_read = READY_R; 154 | end 155 | else 156 | begin 157 | state_read = START_R; 158 | end 159 | 160 | READY_R : 161 | begin 162 | state_read = START_R; 163 | end 164 | 165 | endcase 166 | end 167 | end 168 | //----OUTPUTS--FSM--READ---- 169 | always @(state_read or RST) 170 | begin 171 | if (RST == 1'b0) 172 | begin 173 | PREADY_R = 0; 174 | ena_PRDATA = 0; 175 | end 176 | //----LOGIC---- 177 | else 178 | begin 179 | case (state_read) 180 | START_R :begin 181 | PREADY_R = 0; 182 | ena_PRDATA = 0; 183 | end 184 | READY_R :begin 185 | PREADY_R = 1; 186 | ena_PRDATA = 1; 187 | end 188 | 189 | endcase 190 | end 191 | end 192 | endmodule 193 | 194 | 195 | -------------------------------------------------------------------------------- /mriscv_apb/DAC_interface_APB/DAC_interface_APB_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module DAC_interface_APB_tb; 4 | parameter CLKPERIOD = 10; 5 | 6 | reg CLK = 0, RST; 7 | reg PWRITE, PSEL, PENABLE; 8 | reg [31:0] PADDR, PWDATA; 9 | reg [3:0] PSTRB; 10 | 11 | wire PREADY; 12 | wire [11:0] DATA; 13 | wire [31:0] PRDATA; 14 | 15 | DAC_interface_APB DAC_interface_APB_inst( 16 | .RST(RST), 17 | .CLK(CLK), 18 | .PWRITE(PWRITE), 19 | .PSEL(PSEL), 20 | .PENABLE(PENABLE), 21 | .PADDR(PADDR), 22 | .PWDATA(PWDATA), 23 | .PSTRB(PSTRB), 24 | .PREADY(PREADY), 25 | .DATA(DATA), 26 | .PRDATA(PRDATA)); 27 | 28 | always 29 | begin 30 | #(CLKPERIOD/2) CLK = ~CLK; 31 | end 32 | 33 | initial begin 34 | 35 | RST <= 1'b0; 36 | 37 | #(CLKPERIOD*100);//-------------------------START_W--AND--START_R 38 | /* 39 | 40 | RST <= 1'b1; 41 | PWRITE <= 1'b0; 42 | PSEL <= 1'b0; 43 | PENABLE <= 1'b0; 44 | PWDATA <= 32'b0; 45 | PADDR <= 32'b0; 46 | PSTRB <= 1'b0; 47 | 48 | #(CLKPERIOD*10);//------------------------- 49 | 50 | RST <= 1'b1; 51 | AWVALID <= 1'b0; 52 | WVALID <= 1'b0; 53 | BREADY <= 1'b0; 54 | AWADDR <= 32'hfffffff1; 55 | WDATA <= 32'h12345678; 56 | ARVALID <= 1'b0; 57 | RREADY <= 1'b0; 58 | 59 | #(CLKPERIOD*5);//------------------------- 60 | 61 | RST <= 1'bx; 62 | AWVALID <= 1'bx; 63 | WVALID <= 1'bx; 64 | BREADY <= 1'bx; 65 | AWADDR <= 32'bx; 66 | WDATA <= 32'hx; 67 | ARVALID <= 1'bX; 68 | RREADY <= 1'bX; 69 | 70 | #(CLKPERIOD*5);//------------------------- 71 | 72 | RST <= 1'bz; 73 | AWVALID <= 1'bz; 74 | WVALID <= 1'bz; 75 | BREADY <= 1'bz; 76 | AWADDR <= 32'bz; 77 | WDATA <= 32'hz; 78 | ARVALID <= 1'bZ; 79 | RREADY <= 1'bZ; 80 | 81 | #(CLKPERIOD*5);//------------------------- 82 | */ 83 | 84 | RST <= 1'b1; 85 | PWRITE <= 1'b1; 86 | PSEL <= 1'b1; 87 | PENABLE <= 1'b1; 88 | PWDATA <= 32'h55555555; 89 | PADDR <= 32'h55555555; 90 | PSTRB <= 4'b1; 91 | 92 | #(CLKPERIOD*9);//-------------------------WAIT_WVALID--AND--WAIT_RREADY 93 | /* 94 | RST <= 1'b1; 95 | AWVALID <= 1'b0; 96 | WVALID <= 1'b0; 97 | BREADY <= 1'b0; 98 | AWADDR <= 32'b0; 99 | WDATA <= 32'b0; 100 | ARVALID <= 1'b0; 101 | RREADY <= 1'b0; 102 | 103 | #(CLKPERIOD*5);//------------------------- 104 | 105 | RST <= 1'b1; 106 | AWVALID <= 1'b0; 107 | WVALID <= 1'b0; 108 | BREADY <= 1'b0; 109 | AWADDR <= 32'hfffffff1; 110 | WDATA <= 32'h12345678; 111 | ARVALID <= 1'b0; 112 | RREADY <= 1'b0; 113 | 114 | 115 | #(CLKPERIOD*5);//------------------------- 116 | 117 | RST <= 1'bX; 118 | AWVALID <= 1'bX; 119 | WVALID <= 1'bX; 120 | BREADY <= 1'bX; 121 | AWADDR <= 32'bX; 122 | WDATA <= 32'bX; 123 | ARVALID <= 1'bX; 124 | RREADY <= 1'bX; 125 | 126 | 127 | #(CLKPERIOD*5);//------------------------- 128 | 129 | RST <= 1'bZ; 130 | AWVALID <= 1'bZ; 131 | WVALID <= 1'bZ; 132 | BREADY <= 1'bZ; 133 | AWADDR <= 32'bZ; 134 | WDATA <= 32'bZ; 135 | ARVALID <= 1'bZ; 136 | RREADY <= 1'bZ; 137 | 138 | #(CLKPERIOD*5);//------------------------- 139 | */ 140 | RST <= 1'b1; 141 | PWRITE <= 1'b1; 142 | PSEL <= 1'b1; 143 | PENABLE <= 1'b1; 144 | PWDATA <= 32'h44444444; 145 | PADDR <= 32'h55555555; 146 | PSTRB <= 4'b1; 147 | 148 | 149 | #(CLKPERIOD*9);//-------------------------WORKING--AND--START_R 150 | /* 151 | RST <= 1'b1; 152 | AWVALID <= 1'b0; 153 | WVALID <= 1'b0; 154 | BREADY <= 1'b0; 155 | AWADDR <= 32'b0; 156 | WDATA <= 32'b0; 157 | ARVALID <= 1'b0; 158 | RREADY <= 1'b0; 159 | 160 | #(CLKPERIOD*5);//------------------------- 161 | 162 | RST <= 1'b1; 163 | AWVALID <= 1'b0; 164 | WVALID <= 1'b0; 165 | BREADY <= 1'b0; 166 | AWADDR <= 32'hfffffff1; 167 | WDATA <= 32'h12345678; 168 | ARVALID <= 1'b0; 169 | RREADY <= 1'b0; 170 | 171 | #(CLKPERIOD*5);//------------------------- 172 | 173 | RST <= 1'bX; 174 | AWVALID <= 1'bX; 175 | WVALID <= 1'bX; 176 | BREADY <= 1'b0; 177 | AWADDR <= 32'bX; 178 | WDATA <= 32'bX; 179 | ARVALID <= 1'bX; 180 | RREADY <= 1'bX; 181 | 182 | #(CLKPERIOD*5);//------------------------- 183 | 184 | RST <= 1'bZ; 185 | AWVALID <= 1'bZ; 186 | WVALID <= 1'bZ; 187 | BREADY <= 1'bZ; 188 | AWADDR <= 32'bZ; 189 | WDATA <= 32'bZ; 190 | ARVALID <= 1'bZ; 191 | RREADY <= 1'bZ; 192 | 193 | #(CLKPERIOD*5);//------------------------- 194 | 195 | RST <= 1'b1; 196 | AWVALID <= 1'b0; 197 | WVALID <= 1'b0; 198 | BREADY <= 1'b0; 199 | AWADDR <= 32'b0; 200 | WDATA <= 32'b0; 201 | ARVALID <= 1'b0; 202 | RREADY <= 1'b0; 203 | 204 | #(CLKPERIOD*10); 205 | */ 206 | //----------------------------------reset------------------------ 207 | 208 | RST <= 1'b0; 209 | PWRITE <= 1'b0; 210 | PSEL <= 1'b0; 211 | PENABLE <= 1'b0; 212 | PWDATA <= 32'h0; 213 | PADDR <= 32'h0; 214 | PSTRB <= 4'b0; 215 | 216 | 217 | #(CLKPERIOD*100);//-------------------------START_R--AND--START_W 218 | /* 219 | RST <= 1'b1; 220 | AWVALID <= 1'b0; 221 | WVALID <= 1'b0; 222 | BREADY <= 1'b0; 223 | AWADDR <= 32'b0; 224 | WDATA <= 32'b0; 225 | ARVALID <= 1'b0; 226 | RREADY <= 1'b0; 227 | 228 | #(CLKPERIOD*5);//------------------------- 229 | 230 | RST <= 1'b1; 231 | AWVALID <= 1'b0; 232 | WVALID <= 1'b0; 233 | BREADY <= 1'b0; 234 | AWADDR <= 32'hfffffff2; 235 | WDATA <= 32'h87654321; 236 | ARVALID <= 1'b0; 237 | RREADY <= 1'b0; 238 | 239 | #(CLKPERIOD*5);//------------------------- 240 | 241 | RST <= 1'bx; 242 | AWVALID <= 1'bx; 243 | WVALID <= 1'bx; 244 | BREADY <= 1'bx; 245 | AWADDR <= 32'bx; 246 | WDATA <= 32'hx; 247 | ARVALID <= 1'bX; 248 | RREADY <= 1'bX; 249 | 250 | #(CLKPERIOD*5);//------------------------- 251 | 252 | RST <= 1'bz; 253 | AWVALID <= 1'bz; 254 | WVALID <= 1'bz; 255 | BREADY <= 1'bz; 256 | AWADDR <= 32'bz; 257 | WDATA <= 32'hz; 258 | ARVALID <= 1'bZ; 259 | RREADY <= 1'bZ; 260 | 261 | #(CLKPERIOD*5);//------------------------- 262 | 263 | RST <= 1'b1; 264 | AWVALID <= 1'b1; 265 | WVALID <= 1'b0; 266 | BREADY <= 1'b0; 267 | AWADDR <= 32'hfffffff2; 268 | WDATA <= 32'h87654321; 269 | ARVALID <= 1'b1; 270 | RREADY <= 1'b0; 271 | 272 | */ 273 | 274 | RST <= 1'b1; 275 | PWRITE <= 1'b1; 276 | PSEL <= 1'b1; 277 | PENABLE <= 1'b1; 278 | PWDATA <= 32'h33333333; 279 | PADDR <= 32'h55555555; 280 | PSTRB <= 4'b1; 281 | 282 | 283 | #(CLKPERIOD*9);//-------------------------WAIT_WVALID--AND--WAIT_RREADY 284 | /* 285 | RST <= 1'b1; 286 | AWVALID <= 1'b0; 287 | WVALID <= 1'b0; 288 | BREADY <= 1'b0; 289 | AWADDR <= 32'b0; 290 | WDATA <= 32'b0; 291 | ARVALID <= 1'b0; 292 | RREADY <= 1'b0; 293 | 294 | #(CLKPERIOD*5);//------------------------- 295 | 296 | RST <= 1'b1; 297 | AWVALID <= 1'b0; 298 | WVALID <= 1'b0; 299 | BREADY <= 1'b0; 300 | AWADDR <= 32'hfffffff2; 301 | WDATA <= 32'h87654321; 302 | ARVALID <= 1'b0; 303 | RREADY <= 1'b0; 304 | 305 | 306 | #(CLKPERIOD*5);//------------------------- 307 | 308 | RST <= 1'bX; 309 | AWVALID <= 1'bX; 310 | WVALID <= 1'bX; 311 | BREADY <= 1'bX; 312 | AWADDR <= 32'bX; 313 | WDATA <= 32'bX; 314 | ARVALID <= 1'bX; 315 | RREADY <= 1'bX; 316 | 317 | 318 | #(CLKPERIOD*5);//------------------------- 319 | 320 | RST <= 1'bZ; 321 | AWVALID <= 1'bZ; 322 | WVALID <= 1'bZ; 323 | BREADY <= 1'bZ; 324 | AWADDR <= 32'bZ; 325 | WDATA <= 32'bZ; 326 | ARVALID <= 1'bZ; 327 | RREADY <= 1'bZ; 328 | 329 | #(CLKPERIOD*5);//------------------------- 330 | 331 | RST <= 1'b1; 332 | AWVALID <= 1'b0; 333 | WVALID <= 1'b1; 334 | BREADY <= 1'b1; 335 | AWADDR <= 32'hfffffff2; 336 | WDATA <= 32'h87654321; 337 | ARVALID <= 1'b0; 338 | RREADY <= 1'b1; 339 | */ 340 | RST <= 1'b1; 341 | PWRITE <= 1'b1; 342 | PSEL <= 1'b1; 343 | PENABLE <= 1'b1; 344 | PWDATA <= 32'h77777777; 345 | PADDR <= 32'h55555555; 346 | PSTRB <= 4'b1; 347 | 348 | 349 | #(CLKPERIOD*9);//-------------------------WORKING--AND--START_R 350 | /* 351 | RST <= 1'b1; 352 | AWVALID <= 1'b0; 353 | WVALID <= 1'b0; 354 | BREADY <= 1'b0; 355 | AWADDR <= 32'b0; 356 | WDATA <= 32'b0; 357 | ARVALID <= 1'b0; 358 | RREADY <= 1'b0; 359 | 360 | #(CLKPERIOD*5);//------------------------- 361 | 362 | RST <= 1'b1; 363 | AWVALID <= 1'b0; 364 | WVALID <= 1'b0; 365 | BREADY <= 1'b0; 366 | AWADDR <= 32'hfffffff2; 367 | WDATA <= 32'h87654321; 368 | ARVALID <= 1'b0; 369 | RREADY <= 1'b0; 370 | 371 | #(CLKPERIOD*5);//------------------------- 372 | 373 | RST <= 1'bX; 374 | AWVALID <= 1'bX; 375 | WVALID <= 1'bX; 376 | BREADY <= 1'b0; 377 | AWADDR <= 32'bX; 378 | WDATA <= 32'bX; 379 | ARVALID <= 1'bX; 380 | RREADY <= 1'bX; 381 | 382 | #(CLKPERIOD*5);//------------------------- 383 | 384 | RST <= 1'bZ; 385 | AWVALID <= 1'bZ; 386 | WVALID <= 1'bZ; 387 | BREADY <= 1'bZ; 388 | AWADDR <= 32'bZ; 389 | WDATA <= 32'bZ; 390 | ARVALID <= 1'bZ; 391 | RREADY <= 1'bZ; 392 | 393 | #(CLKPERIOD*5);//------------------------- 394 | 395 | 396 | RST <= 1'b1; 397 | AWVALID <= 1'b0; 398 | WVALID <= 1'b0; 399 | BREADY <= 1'b0; 400 | AWADDR <= 32'b0; 401 | WDATA <= 32'b0; 402 | ARVALID <= 1'b0; 403 | RREADY <= 1'b1; 404 | 405 | #(CLKPERIOD*10) 406 | */ 407 | RST <= 1'b1; 408 | PWRITE <= 1'b1; 409 | PSEL <= 1'b1; 410 | PENABLE <= 1'b1; 411 | PWDATA <= 32'h11111111; 412 | PADDR <= 32'h55555555; 413 | PSTRB <= 4'b1; 414 | 415 | 416 | //-------------------------START_R--AND--START_W 417 | 418 | //----------------------------------NO--reset------------------------ 419 | 420 | //RST <= 1'b0; 421 | 422 | #(CLKPERIOD*9);//-------------------------START_R--AND--START_W 423 | /* 424 | RST <= 1'b1; 425 | AWVALID <= 1'b0; 426 | WVALID <= 1'b0; 427 | BREADY <= 1'b0; 428 | AWADDR <= 32'b0; 429 | WDATA <= 32'b0; 430 | ARVALID <= 1'b0; 431 | RREADY <= 1'b0; 432 | 433 | #(CLKPERIOD*5);//------------------------- 434 | 435 | RST <= 1'b1; 436 | AWVALID <= 1'b0; 437 | WVALID <= 1'b0; 438 | BREADY <= 1'b0; 439 | AWADDR <= 32'hfffffff3; 440 | WDATA <= 32'h55555555; 441 | ARVALID <= 1'b0; 442 | RREADY <= 1'b0; 443 | 444 | #(CLKPERIOD*5);//------------------------- 445 | 446 | RST <= 1'bx; 447 | AWVALID <= 1'bx; 448 | WVALID <= 1'bx; 449 | BREADY <= 1'bx; 450 | AWADDR <= 32'bx; 451 | WDATA <= 32'hx; 452 | ARVALID <= 1'bX; 453 | RREADY <= 1'bX; 454 | 455 | #(CLKPERIOD*5);//------------------------- 456 | 457 | RST <= 1'bz; 458 | AWVALID <= 1'bz; 459 | WVALID <= 1'bz; 460 | BREADY <= 1'bz; 461 | AWADDR <= 32'bz; 462 | WDATA <= 32'hz; 463 | ARVALID <= 1'bZ; 464 | RREADY <= 1'bZ; 465 | 466 | #(CLKPERIOD*5);//------------------------- 467 | 468 | RST <= 1'b1; 469 | AWVALID <= 1'b1; 470 | WVALID <= 1'b0; 471 | BREADY <= 1'b0; 472 | AWADDR <= 32'hfffffff3; 473 | WDATA <= 32'h55555555; 474 | ARVALID <= 1'b1; 475 | RREADY <= 1'b0; 476 | */ 477 | RST <= 1'b1; 478 | PWRITE <= 1'b1; 479 | PSEL <= 1'b1; 480 | PENABLE <= 1'b1; 481 | PWDATA <= 32'h22222222; 482 | PADDR <= 32'h55555555; 483 | PSTRB <= 4'b1; 484 | 485 | 486 | #(CLKPERIOD*9);//-------------------------WAIT_WVALID--AND--WAIT_RREADY 487 | /* 488 | RST <= 1'b1; 489 | AWVALID <= 1'b0; 490 | WVALID <= 1'b0; 491 | BREADY <= 1'b0; 492 | AWADDR <= 32'b0; 493 | WDATA <= 32'b0; 494 | ARVALID <= 1'b0; 495 | RREADY <= 1'b0; 496 | 497 | #(CLKPERIOD*5);//------------------------- 498 | 499 | RST <= 1'b1; 500 | AWVALID <= 1'b0; 501 | WVALID <= 1'b0; 502 | BREADY <= 1'b0; 503 | AWADDR <= 32'hfffffff3; 504 | WDATA <= 32'h55555555; 505 | ARVALID <= 1'b0; 506 | RREADY <= 1'b0; 507 | 508 | 509 | #(CLKPERIOD*5);//------------------------- 510 | 511 | RST <= 1'bX; 512 | AWVALID <= 1'bX; 513 | WVALID <= 1'bX; 514 | BREADY <= 1'bX; 515 | AWADDR <= 32'bX; 516 | WDATA <= 32'bX; 517 | ARVALID <= 1'bX; 518 | RREADY <= 1'bX; 519 | 520 | 521 | #(CLKPERIOD*5);//------------------------- 522 | 523 | RST <= 1'bZ; 524 | AWVALID <= 1'bZ; 525 | WVALID <= 1'bZ; 526 | BREADY <= 1'bZ; 527 | AWADDR <= 32'bZ; 528 | WDATA <= 32'bZ; 529 | ARVALID <= 1'bZ; 530 | RREADY <= 1'bZ; 531 | 532 | #(CLKPERIOD*5);//------------------------- 533 | 534 | 535 | RST <= 1'b1; 536 | AWVALID <= 1'b0; 537 | WVALID <= 1'b1; 538 | BREADY <= 1'b1; 539 | AWADDR <= 32'hfffffff3; 540 | WDATA <= 32'h55555555; 541 | ARVALID <= 1'b0; 542 | RREADY <= 1'b1; 543 | 544 | */ 545 | 546 | RST <= 1'b1; 547 | PWRITE <= 1'b1; 548 | PSEL <= 1'b1; 549 | PENABLE <= 1'b1; 550 | PWDATA <= 32'h55555568; 551 | PADDR <= 32'h55555555; 552 | PSTRB <= 4'b1; 553 | 554 | 555 | #(CLKPERIOD*9);//-------------------------WORKING--AND--START_R 556 | /* 557 | RST <= 1'b1; 558 | AWVALID <= 1'b0; 559 | WVALID <= 1'b0; 560 | BREADY <= 1'b0; 561 | AWADDR <= 32'b0; 562 | WDATA <= 32'b0; 563 | ARVALID <= 1'b0; 564 | RREADY <= 1'b0; 565 | 566 | #(CLKPERIOD*5);//------------------------- 567 | 568 | RST <= 1'b1; 569 | AWVALID <= 1'b0; 570 | WVALID <= 1'b0; 571 | BREADY <= 1'b0; 572 | AWADDR <= 32'hfffffff3; 573 | WDATA <= 32'h55555555; 574 | ARVALID <= 1'b0; 575 | RREADY <= 1'b0; 576 | 577 | #(CLKPERIOD*5);//------------------------- 578 | 579 | RST <= 1'bX; 580 | AWVALID <= 1'bX; 581 | WVALID <= 1'bX; 582 | BREADY <= 1'b0; 583 | AWADDR <= 32'bX; 584 | WDATA <= 32'bX; 585 | ARVALID <= 1'bX; 586 | RREADY <= 1'bX; 587 | 588 | #(CLKPERIOD*5);//------------------------- 589 | 590 | RST <= 1'bZ; 591 | AWVALID <= 1'bZ; 592 | WVALID <= 1'bZ; 593 | BREADY <= 1'bZ; 594 | AWADDR <= 32'bZ; 595 | WDATA <= 32'bZ; 596 | ARVALID <= 1'bZ; 597 | RREADY <= 1'bZ; 598 | 599 | #(CLKPERIOD*5);//------------------------- 600 | 601 | RST <= 1'b1; 602 | AWVALID <= 1'b0; 603 | WVALID <= 1'b0; 604 | BREADY <= 1'b0; 605 | AWADDR <= 32'b0; 606 | WDATA <= 32'b0; 607 | ARVALID <= 1'b0; 608 | RREADY <= 1'b0; 609 | 610 | #(CLKPERIOD*10) 611 | 612 | //-------------------------START--AND--WAIT_RREADY 613 | */ 614 | $finish; 615 | 616 | end 617 | endmodule 618 | -------------------------------------------------------------------------------- /mriscv_apb/GPIO/decodificador.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module decodificador( 4 | input Psel, 5 | input clock, 6 | input [2:0] Lrad, 7 | output [7:0] W 8 | ); 9 | 10 | assign W = Psel? (1 << Lrad) : 0; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /mriscv_apb/GPIO/flipflopRS.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module flipflopRS( 4 | 5 | output reg Rx,Tx, 6 | input W1,reset, 7 | input R1, 8 | input clock 9 | ); 10 | 11 | reg D; 12 | always @(posedge clock) 13 | if (!reset) begin 14 | Rx<=1'b0; 15 | Tx<=1'b1; 16 | end 17 | else if (R1 && !W1) begin 18 | Tx <= 1'b1; 19 | Rx<=1'b1; 20 | 21 | end else if (W1 && !R1) begin 22 | Tx<= 1'b0; 23 | Rx<=1'b0; 24 | 25 | 26 | end 27 | else begin 28 | Tx<=Tx; 29 | Rx<=Rx; 30 | 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /mriscv_apb/GPIO/flipsdataw.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module flipsdataw( 4 | input en,clock,reset, 5 | input [1:0] datain, 6 | output reg outdata, 7 | output reg DS 8 | ); 9 | 10 | //reg es1,es2; 11 | always @ (posedge clock) begin 12 | 13 | if (!reset) begin 14 | DS<=0; 15 | outdata<=0; 16 | //es1<=0; 17 | //es2<=0; 18 | end 19 | 20 | 21 | else if (en) begin 22 | outdata<=datain[0]; 23 | DS<=datain[1]; 24 | //es1<=datain[0]; 25 | //es2<=datain[1]; 26 | 27 | end 28 | end 29 | 30 | endmodule -------------------------------------------------------------------------------- /mriscv_apb/GPIO/gpioAPB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | module gpioAPB( 5 | input clock, 6 | input reset, 7 | input [31:0] Paddr, 8 | input Penable, 9 | input Pwrite, 10 | input [31:0] Pwdata, 11 | input [7:0] pindata, 12 | input Psel, 13 | output reg [31:0] Prdata, 14 | output reg[7:0] Rx,datanw, 15 | output reg [7:0] Tx,DSE, 16 | output Pready, 17 | input [3:0] strobe 18 | ); 19 | 20 | wire [2:0] lwad,lrad; 21 | wire [7:0] W,R,Tm,Rm,outdataw,DS; 22 | reg Rdata1,vel; 23 | 24 | // Instantiate the module 25 | latchW lawrite ( 26 | .clock(clock), 27 | .reset(reset), 28 | .enable(Pwrite), 29 | .adress(Paddr), 30 | .Ladress(lwad) 31 | ); 32 | 33 | // Instantiate the module 34 | latchW laread ( 35 | .clock(clock), 36 | .reset(reset), 37 | .enable(~Pwrite), 38 | .adress(Paddr), 39 | .Ladress(lrad) 40 | ); 41 | 42 | //decodificador escritura 43 | decodificador decow ( 44 | .Psel(Psel), 45 | .clock(clock), 46 | .Lrad(lwad), 47 | .W(W) 48 | ); 49 | 50 | // decodificador lectura 51 | decodificador decoR ( 52 | .Psel(Psel), 53 | .clock(clock), 54 | .Lrad(lrad), 55 | .W(R) 56 | ); 57 | 58 | // maquina estados 59 | macstate2 maquina ( 60 | .vel(vel), 61 | .clock(clock), 62 | .reset(reset), 63 | .Pready(Pready), 64 | .Penable(Penable), 65 | .Pwrite(Pwrite) 66 | ); 67 | 68 | ////////////////////////////////////////////////////////////// 69 | 70 | always @ (posedge clock) begin 71 | 72 | if (!reset) begin 73 | vel<=1; 74 | 75 | end 76 | 77 | else begin 78 | vel<=Pwdata[2]; 79 | 80 | end 81 | end 82 | 83 | //////////////// FLIPS FLOPS HABILITADORES//////////////////// 84 | 85 | // flip1 86 | flipflopRS flip1 ( 87 | .reset(reset), 88 | .Tx(Tm[0]), 89 | .Rx(Rm[0]), 90 | .W1(W[0]), 91 | .R1(R[0]), 92 | .clock(clock) 93 | ); 94 | 95 | // flip2 96 | flipflopRS flip2 ( 97 | .reset(reset), 98 | .Tx(Tm[1]), 99 | .Rx(Rm[1]), 100 | .W1(W[1]), 101 | .R1(R[1]), 102 | .clock(clock) 103 | ); 104 | 105 | // flip3 106 | flipflopRS flip3 ( 107 | .reset(reset), 108 | .Tx(Tm[2]), 109 | .Rx(Rm[2]), 110 | .W1(W[2]), 111 | .R1(R[2]), 112 | .clock(clock) 113 | ); 114 | 115 | // flip4 116 | flipflopRS flip4 ( 117 | .reset(reset), 118 | .Tx(Tm[3]), 119 | .Rx(Rm[3]), 120 | .W1(W[3]), 121 | .R1(R[3]), 122 | .clock(clock) 123 | ); 124 | 125 | // flip5 126 | flipflopRS flip5 ( 127 | .reset(reset), 128 | .Tx(Tm[4]), 129 | .Rx(Rm[4]), 130 | .W1(W[4]), 131 | .R1(R[4]), 132 | .clock(clock) 133 | ); 134 | 135 | // flip6 136 | flipflopRS flip6 ( 137 | .reset(reset), 138 | .Tx(Tm[5]), 139 | .Rx(Rm[5]), 140 | .W1(W[5]), 141 | .R1(R[5]), 142 | .clock(clock) 143 | ); 144 | 145 | // flip7 146 | flipflopRS flip7 ( 147 | .reset(reset), 148 | .Tx(Tm[6]), 149 | .Rx(Rm[6]), 150 | .W1(W[6]), 151 | .R1(R[6]), 152 | .clock(clock) 153 | ); 154 | 155 | // flip8 156 | flipflopRS flip8 ( 157 | .reset(reset), 158 | .Tx(Tm[7]), 159 | .Rx(Rm[7]), 160 | .W1(W[7]), 161 | .R1(R[7]), 162 | .clock(clock) 163 | ); 164 | 165 | ///////////////////// FLIPS PARA DATO ESCRITURA 166 | 167 | ///////////////////////////////////// 168 | // Instantiate the module 169 | flipsdataw flipw1( 170 | .en(W[0]), 171 | .clock(clock), 172 | .reset(reset), 173 | .datain(Pwdata[1:0]), 174 | .outdata(outdataw[0]), 175 | .DS(DS[0]) 176 | ); 177 | 178 | flipsdataw flipw2 ( 179 | .en(W[1]), 180 | .reset(reset), 181 | .clock(clock), 182 | .datain(Pwdata[1:0]), 183 | .outdata(outdataw[1]), 184 | .DS(DS[1]) 185 | ); 186 | 187 | flipsdataw flipw3 ( 188 | .en(W[2]), 189 | .clock(clock), 190 | .reset(reset), 191 | .datain(Pwdata[1:0]), 192 | .outdata(outdataw[2]), 193 | .DS(DS[2]) 194 | ); 195 | 196 | flipsdataw flipw4 ( 197 | .en(W[3]), 198 | .clock(clock), 199 | .reset(reset), 200 | .datain(Pwdata[1:0]), 201 | .outdata(outdataw[3]), 202 | .DS(DS[3]) 203 | ); 204 | 205 | flipsdataw flipw5 ( 206 | .en(W[4]), 207 | .clock(clock), 208 | .reset(reset), 209 | .datain(Pwdata[1:0]), 210 | .outdata(outdataw[4]), 211 | .DS(DS[4]) 212 | ); 213 | 214 | flipsdataw flipw6 ( 215 | .en(W[5]), 216 | .clock(clock), 217 | .reset(reset), 218 | .datain(Pwdata[1:0]), 219 | .outdata(outdataw[5]), 220 | .DS(DS[5]) 221 | ); 222 | 223 | flipsdataw flipw7 ( 224 | .en(W[6]), 225 | .clock(clock), 226 | .reset(reset), 227 | .datain(Pwdata[1:0]), 228 | .outdata(outdataw[6]), 229 | .DS(DS[6]) 230 | ); 231 | 232 | flipsdataw flipw8 ( 233 | .en(W[7]), 234 | .clock(clock), 235 | .reset(reset), 236 | .datain(Pwdata[1:0]), 237 | .outdata(outdataw[7]), 238 | .DS(DS[7]) 239 | ); 240 | 241 | /////////////////////////////////////////////////// 242 | 243 | always @(lrad,pindata) begin 244 | case (lrad) 245 | 3'b000: Rdata1 =pindata[0]; 246 | 3'b001: Rdata1 =pindata[1]; 247 | 3'b010: Rdata1 =pindata[2]; 248 | 3'b011: Rdata1 =pindata[3]; 249 | 3'b100: Rdata1 =pindata[4]; 250 | 3'b101: Rdata1 =pindata[5]; 251 | 3'b110: Rdata1 =pindata[6]; 252 | 3'b111: Rdata1 =pindata[7]; 253 | endcase 254 | end 255 | 256 | always @(posedge clock) 257 | if (!reset) begin 258 | Prdata[0] <= 1'b0; 259 | end else begin 260 | Prdata[0] <= Rdata1; 261 | end 262 | 263 | always@* begin 264 | DSE=DS; 265 | Prdata[31:1]=0; 266 | Tx=Tm; 267 | Rx=Rm; 268 | datanw=outdataw; 269 | 270 | end 271 | 272 | endmodule 273 | -------------------------------------------------------------------------------- /mriscv_apb/GPIO/gpioAPB_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | module gpioAPB_tb; 5 | 6 | // Inputs 7 | reg clock; 8 | reg reset; 9 | reg [31:0] Paddr; 10 | reg Penable; 11 | reg Pwrite; 12 | reg [31:0] Pwdata; 13 | reg [7:0]pindata; 14 | reg Psel; 15 | reg [3:0] strobe; 16 | 17 | // Outputs 18 | wire [31:0] Prdata; 19 | wire [7:0] Rx; 20 | wire [7:0] datanw; 21 | wire [7:0] Tx; 22 | wire [7:0] DSE; 23 | wire Pready; 24 | 25 | // Instantiate the Unit Under Test (UUT) 26 | gpioAPB uut ( 27 | .clock(clock), 28 | .reset(reset), 29 | .Paddr(Paddr), 30 | .Penable(Penable), 31 | .Pwrite(Pwrite), 32 | .Pwdata(Pwdata), 33 | .pindata(pindata), 34 | .Psel(Psel), 35 | .Prdata(Prdata), 36 | .Rx(Rx), 37 | .datanw(datanw), 38 | .Tx(Tx), 39 | .DSE(DSE), 40 | .Pready(Pready), 41 | .strobe(strobe) 42 | ); 43 | always #1 clock=~clock; 44 | initial begin 45 | // Initialize Inputs 46 | clock = 0; 47 | reset = 0; 48 | Paddr = 0; 49 | Penable = 0; 50 | Pwrite = 0; 51 | Pwdata = 0; 52 | pindata =8'd0; 53 | Psel = 0; 54 | strobe = 0; 55 | 56 | 57 | // lectura 58 | #5; 59 | reset = 1; 60 | Paddr = 32'habcfdef; 61 | Penable = 1; 62 | Pwrite = 0; 63 | Pwdata = 32'h4567abcf;; 64 | pindata = 8'b10110101; 65 | Psel = 1; 66 | 67 | #5; 68 | reset=0; 69 | Penable=0; 70 | Paddr = 32'h348cf01f; 71 | 72 | 73 | // escritura 74 | #5; 75 | reset=1; 76 | Penable=1; 77 | Pwrite=1; 78 | pindata = 8'hff; 79 | 80 | #5; 81 | reset=0; 82 | Pwrite=0; 83 | Penable=0; 84 | Paddr = 32'h34; 85 | 86 | // lectura 87 | #5; 88 | reset=1; 89 | Penable=1; 90 | 91 | 92 | #5; 93 | reset=0; 94 | Penable=0; 95 | 96 | 97 | // escritura 98 | #5; 99 | reset=1; 100 | Penable=1; 101 | Pwrite=1; 102 | pindata = 8'h2a; 103 | Paddr = 32'h3a; 104 | 105 | #5; 106 | reset=0; 107 | Pwrite=0; 108 | Penable=0; 109 | #1; 110 | $finish; 111 | 112 | // Add stimulus here 113 | 114 | end 115 | 116 | endmodule 117 | 118 | -------------------------------------------------------------------------------- /mriscv_apb/GPIO/latchW.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ///////////////////////////////////////////////////////////////////////////////// 3 | module latchW( 4 | input clock, 5 | input reset, 6 | input enable, 7 | input [31:0] adress, 8 | output reg [2:0] Ladress 9 | ); 10 | 11 | always @ ( posedge clock ) 12 | if (!reset) begin 13 | Ladress=3'b0; 14 | end else if (enable) begin 15 | Ladress=adress[2:0]; 16 | end 17 | 18 | endmodule -------------------------------------------------------------------------------- /mriscv_apb/GPIO/macstate2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | module macstate2( 5 | input clock, 6 | input reset, 7 | output reg Pready, 8 | input Penable, 9 | input Pwrite, 10 | input vel 11 | ); 12 | 13 | reg [3:0] state,nexstate; 14 | parameter reposo = 4'd0; 15 | parameter sel = 4'b0001; 16 | parameter lectura = 4'b010; 17 | parameter waitR = 4'b0011; 18 | parameter endR = 4'b0100; 19 | parameter escritura = 4'b0101; 20 | parameter waitW = 4'b0110; 21 | parameter endW = 4'b0111; 22 | parameter delay1=4'b1000; 23 | parameter delay2=4'b1001; 24 | parameter delay3=4'b1010; 25 | parameter delay4=4'b1011; 26 | parameter delay5=4'b1100; 27 | parameter delay6=4'b1101; 28 | //asignacion estado siguiente 29 | 30 | always @(Pwrite,Penable,state) begin 31 | case (state) 32 | reposo : begin 33 | if (Penable) begin 34 | nexstate = sel; 35 | end 36 | else begin 37 | nexstate = reposo; 38 | end 39 | 40 | end 41 | sel : begin 42 | if (!Pwrite) begin 43 | nexstate = lectura; 44 | end 45 | else begin 46 | nexstate = escritura; 47 | end 48 | end 49 | lectura : begin 50 | if(!vel) begin 51 | nexstate = delay1; 52 | end 53 | else begin 54 | nexstate=endR; 55 | end 56 | end 57 | 58 | 59 | delay1 : begin 60 | nexstate=delay2; 61 | end 62 | 63 | delay2 : begin 64 | nexstate=delay3; 65 | end 66 | 67 | delay3 : begin 68 | nexstate=waitR; 69 | end 70 | 71 | waitR : begin 72 | nexstate =endR; 73 | end 74 | 75 | endR : begin 76 | nexstate=reposo; 77 | end 78 | 79 | escritura : begin 80 | if (!vel) begin 81 | nexstate = delay4; 82 | end 83 | else begin 84 | nexstate=endW; 85 | end 86 | end 87 | 88 | delay4 : begin 89 | nexstate=delay5; 90 | end 91 | 92 | delay5 : begin 93 | nexstate=delay6; 94 | end 95 | 96 | delay6 : begin 97 | nexstate=waitW; 98 | end 99 | 100 | waitW : begin 101 | nexstate=endW; 102 | end 103 | 104 | endW : begin 105 | nexstate=reposo; 106 | end 107 | 108 | default : begin // Fault Recovery 109 | nexstate = reposo; 110 | end 111 | endcase 112 | end 113 | 114 | // asignacion sincrona 115 | always @(posedge clock) 116 | if(reset == 0) state <= 4'b0; 117 | else state <= nexstate; 118 | 119 | // asignacion salidas 120 | 121 | always @(state) begin 122 | if (state==4'b0) 123 | Pready=0; 124 | else if(state==4'b1) 125 | Pready=0; 126 | else if (state==4'b0010) 127 | Pready=0; 128 | else if (state==4'b0011) 129 | Pready=1; 130 | else if (state==4'b0100) 131 | Pready=1; 132 | else if(state==4'b0101) 133 | Pready=0; 134 | else if(state==4'b0110) 135 | Pready=1; 136 | else if(state==4'b0111) 137 | Pready=1; 138 | else if(state==4'b1000) 139 | Pready=0; 140 | else if(state==4'b1001) 141 | Pready=0; 142 | else if(state==4'b1010) 143 | Pready=0; 144 | else if(state==4'b1011) 145 | Pready=0; 146 | else if(state==4'b1100) 147 | Pready=0; 148 | 149 | else 150 | Pready=0; 151 | end 152 | 153 | endmodule 154 | -------------------------------------------------------------------------------- /mriscv_apb/README.md: -------------------------------------------------------------------------------- 1 | mRISC-V code, APB version 2 | 3 | NOTES: 4 | Missing APB Peripherals (ADC, DAC, GPIO) 5 | Minor differences only included (impl* and axi4_interconnect) 6 | Same notes as AXI version. 7 | -------------------------------------------------------------------------------- /mriscv_apb/impl_axi_apb/impl_axi_apb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module impl_axi_apb( 4 | // General 5 | input CLK, 6 | input PCLK, 7 | input RST, 8 | // Master 1 (picorv32_axi), NOTHING 9 | // Master 2 (spi_axi_master), SPI Slave Interface 10 | input spi_axi_master_CEB, 11 | input spi_axi_master_SCLK, 12 | input spi_axi_master_DATA, 13 | output spi_axi_master_DOUT, 14 | // Slave 1 (AXI_SP32B1024), NOTHING 15 | // Slave 2 (APB_TOP), APB Interface 16 | output [11:0] DAC_interface_AXI_DATA, 17 | input ADC_interface_AXI_BUSY, 18 | input [9:0] ADC_interface_AXI_DATA, 19 | input [7:0] completogpio_pindata, 20 | output [7:0] completogpio_Rx, 21 | output [7:0] completogpio_Tx, 22 | output [7:0] completogpio_datanw, 23 | output [7:0] completogpio_DSE, 24 | output APB_TOP_CEB, 25 | output APB_TOP_SCLK, 26 | output APB_TOP_DATA_SPI, 27 | // Slave 3 (spi_axi_slave), SPI Master Interface 28 | output spi_axi_slave_CEB, 29 | output spi_axi_slave_SCLK, 30 | output spi_axi_slave_DATA 31 | ); 32 | 33 | // Internals 34 | // Picorv RST 35 | wire PICORV_RST; 36 | 37 | // ALL-AXI and its distribution 38 | // MEMORY MAP SPEC 39 | localparam sword = 32; 40 | localparam masters = 2; 41 | localparam slaves = 3; 42 | localparam [slaves*sword-1:0] addr_mask = {32'h00000000,32'h0000001F,32'h000003FF}; 43 | localparam [slaves*sword-1:0] addr_use = {32'h04000000,32'h00000400,32'h00000000}; 44 | 45 | // AXI4-lite master memory interfaces 46 | 47 | wire [masters-1:0] m_axi_awvalid; 48 | wire [masters-1:0] m_axi_awready; 49 | wire [masters*sword-1:0] m_axi_awaddr; 50 | wire [masters*3-1:0] m_axi_awprot; 51 | 52 | wire [masters-1:0] m_axi_wvalid; 53 | wire [masters-1:0] m_axi_wready; 54 | wire [masters*sword-1:0] m_axi_wdata; 55 | wire [masters*4-1:0] m_axi_wstrb; 56 | 57 | wire [masters-1:0] m_axi_bvalid; 58 | wire [masters-1:0] m_axi_bready; 59 | 60 | wire [masters-1:0] m_axi_arvalid; 61 | wire [masters-1:0] m_axi_arready; 62 | wire [masters*sword-1:0] m_axi_araddr; 63 | wire [masters*3-1:0] m_axi_arprot; 64 | 65 | wire [masters-1:0] m_axi_rvalid; 66 | wire [masters-1:0] m_axi_rready; 67 | wire [masters*sword-1:0] m_axi_rdata; 68 | 69 | // AXI4-lite slave memory interfaces 70 | 71 | wire [slaves-1:0] s_axi_awvalid; 72 | wire [slaves-1:0] s_axi_awready; 73 | wire [slaves*sword-1:0] s_axi_awaddr; 74 | wire [slaves*3-1:0] s_axi_awprot; 75 | 76 | wire [slaves-1:0] s_axi_wvalid; 77 | wire [slaves-1:0] s_axi_wready; 78 | wire [slaves*sword-1:0] s_axi_wdata; 79 | wire [slaves*4-1:0] s_axi_wstrb; 80 | 81 | wire [slaves-1:0] s_axi_bvalid; 82 | wire [slaves-1:0] s_axi_bready; 83 | 84 | wire [slaves-1:0] s_axi_arvalid; 85 | wire [slaves-1:0] s_axi_arready; 86 | wire [slaves*sword-1:0] s_axi_araddr; 87 | wire [slaves*3-1:0] s_axi_arprot; 88 | 89 | wire [slaves-1:0] s_axi_rvalid; 90 | wire [slaves-1:0] s_axi_rready; 91 | wire [slaves*sword-1:0] s_axi_rdata; 92 | 93 | // THE CONCENTRATION 94 | 95 | wire [sword-1:0] m_axi_awaddr_o [0:masters-1]; 96 | wire [3-1:0] m_axi_awprot_o [0:masters-1]; 97 | wire [sword-1:0] m_axi_wdata_o [0:masters-1]; 98 | wire [4-1:0] m_axi_wstrb_o [0:masters-1]; 99 | wire [sword-1:0] m_axi_araddr_o [0:masters-1]; 100 | wire [3-1:0] m_axi_arprot_o [0:masters-1]; 101 | wire [sword-1:0] m_axi_rdata_o [0:masters-1]; 102 | wire [sword-1:0] s_axi_awaddr_o [0:slaves-1]; 103 | wire [3-1:0] s_axi_awprot_o [0:slaves-1]; 104 | wire [sword-1:0] s_axi_wdata_o [0:slaves-1]; 105 | wire [4-1:0] s_axi_wstrb_o [0:slaves-1]; 106 | wire [sword-1:0] s_axi_araddr_o [0:slaves-1]; 107 | wire [3-1:0] s_axi_arprot_o [0:slaves-1]; 108 | wire [sword-1:0] s_axi_rdata_o [0:slaves-1]; 109 | 110 | wire [sword-1:0] addr_mask_o [0:slaves-1]; 111 | wire [sword-1:0] addr_use_o [0:slaves-1]; 112 | genvar k; 113 | generate 114 | for(k = 0; k < masters; k=k+1) begin 115 | assign m_axi_awaddr[(k+1)*sword-1:k*sword] = m_axi_awaddr_o[k]; 116 | assign m_axi_awprot[(k+1)*3-1:k*3] = m_axi_awprot_o[k]; 117 | assign m_axi_wdata[(k+1)*sword-1:k*sword] = m_axi_wdata_o[k]; 118 | assign m_axi_wstrb[(k+1)*4-1:k*4] = m_axi_wstrb_o[k]; 119 | assign m_axi_araddr[(k+1)*sword-1:k*sword] = m_axi_araddr_o[k]; 120 | assign m_axi_arprot[(k+1)*3-1:k*3] = m_axi_arprot_o[k]; 121 | assign m_axi_rdata_o[k] = m_axi_rdata[(k+1)*sword-1:k*sword]; 122 | end 123 | for(k = 0; k < slaves; k=k+1) begin 124 | assign s_axi_awaddr_o[k] = s_axi_awaddr[(k+1)*sword-1:k*sword]; 125 | assign s_axi_awprot_o[k] = s_axi_awprot[(k+1)*3-1:k*3]; 126 | assign s_axi_wdata_o[k] = s_axi_wdata[(k+1)*sword-1:k*sword]; 127 | assign s_axi_wstrb_o[k] = s_axi_wstrb[(k+1)*4-1:k*4]; 128 | assign s_axi_araddr_o[k] = s_axi_araddr[(k+1)*sword-1:k*sword]; 129 | assign s_axi_arprot_o[k] = s_axi_arprot[(k+1)*3-1:k*3]; 130 | assign addr_mask_o[k] = addr_mask[(k+1)*sword-1:k*sword]; 131 | assign addr_use_o[k] = addr_use[(k+1)*sword-1:k*sword]; 132 | assign s_axi_rdata[(k+1)*sword-1:k*sword] = s_axi_rdata_o[k]; 133 | end 134 | endgenerate 135 | 136 | // Slave 1 (AXI_SP32B1024), Memory Interface 137 | wire [31:0] AXI_SP32B1024_D; 138 | wire [31:0] AXI_SP32B1024_Q; 139 | wire [9:0] AXI_SP32B1024_A; 140 | wire AXI_SP32B1024_CEN; 141 | wire AXI_SP32B1024_WEN; 142 | 143 | // Instances 144 | 145 | // AXI INTERCONNECT, axi4_interconnect 146 | axi4_interconnect inst_axi4_interconnect 147 | ( 148 | .CLK (CLK), 149 | .RST (RST), 150 | .m_axi_awvalid(m_axi_awvalid), 151 | .m_axi_awready(m_axi_awready), 152 | .m_axi_awaddr(m_axi_awaddr), 153 | .m_axi_awprot(m_axi_awprot), 154 | .m_axi_wvalid(m_axi_wvalid), 155 | .m_axi_wready(m_axi_wready), 156 | .m_axi_wdata(m_axi_wdata), 157 | .m_axi_wstrb(m_axi_wstrb), 158 | .m_axi_bvalid(m_axi_bvalid), 159 | .m_axi_bready(m_axi_bready), 160 | .m_axi_arvalid(m_axi_arvalid), 161 | .m_axi_arready(m_axi_arready), 162 | .m_axi_araddr(m_axi_araddr), 163 | .m_axi_arprot(m_axi_arprot), 164 | .m_axi_rvalid(m_axi_rvalid), 165 | .m_axi_rready(m_axi_rready), 166 | .m_axi_rdata(m_axi_rdata), 167 | .s_axi_awvalid(s_axi_awvalid), 168 | .s_axi_awready(s_axi_awready), 169 | .s_axi_awaddr(s_axi_awaddr), 170 | .s_axi_awprot(s_axi_awprot), 171 | .s_axi_wvalid(s_axi_wvalid), 172 | .s_axi_wready(s_axi_wready), 173 | .s_axi_wdata(s_axi_wdata), 174 | .s_axi_wstrb(s_axi_wstrb), 175 | .s_axi_bvalid(s_axi_bvalid), 176 | .s_axi_bready(s_axi_bready), 177 | .s_axi_arvalid(s_axi_arvalid), 178 | .s_axi_arready(s_axi_arready), 179 | .s_axi_araddr(s_axi_araddr), 180 | .s_axi_arprot(s_axi_arprot), 181 | .s_axi_rvalid(s_axi_rvalid), 182 | .s_axi_rready(s_axi_rready), 183 | .s_axi_rdata(s_axi_rdata) 184 | ); 185 | 186 | // Master 1, picorv32_axi 187 | // For clifford, the memory increases in 4 bytes for address 188 | // For us, only increment one 189 | // This is a fix for this issue (as expresed on the testbench) 190 | wire [31:0] picorv_awaddr; assign m_axi_awaddr_o[0] = {2'b00, picorv_awaddr[31:2]}; 191 | wire [31:0] picorv_araddr; assign m_axi_araddr_o[0] = {2'b00, picorv_araddr[31:2]}; 192 | picorv32_axi inst_picorv32_axi 193 | ( 194 | .clk(CLK), 195 | .resetn(PICORV_RST), 196 | //.trap(DUMMY), 197 | .mem_axi_awvalid(m_axi_awvalid[0]), 198 | .mem_axi_awready(m_axi_awready[0]), 199 | .mem_axi_awaddr(picorv_awaddr), 200 | .mem_axi_awprot(m_axi_awprot_o[0]), 201 | .mem_axi_wvalid(m_axi_wvalid[0]), 202 | .mem_axi_wready(m_axi_wready[0]), 203 | .mem_axi_wdata(m_axi_wdata_o[0]), 204 | .mem_axi_wstrb(m_axi_wstrb_o[0]), 205 | .mem_axi_bvalid(m_axi_bvalid[0]), 206 | .mem_axi_bready(m_axi_bready[0]), 207 | .mem_axi_arvalid(m_axi_arvalid[0]), 208 | .mem_axi_arready(m_axi_arready[0]), 209 | .mem_axi_araddr(picorv_araddr), 210 | .mem_axi_arprot(m_axi_arprot_o[0]), 211 | .mem_axi_rvalid(m_axi_rvalid[0]), 212 | .mem_axi_rready(m_axi_rready[0]), 213 | .mem_axi_rdata(m_axi_rdata_o[0]) 214 | //.pcpi_valid(DUMMY), 215 | //.pcpi_insn(DUMMY), 216 | //.pcpi_rs1(DUMMY), 217 | //.pcpi_rs2(DUMMY), 218 | //.pcpi_wr(DUMMY), 219 | //.pcpi_rd(DUMMY), 220 | //.pcpi_wait(DUMMY), 221 | //.pcpi_ready(DUMMY), 222 | //.irq(DUMMY), 223 | //.eoi(DUMMY) 224 | ); 225 | 226 | // Master 2, spi_axi_master 227 | spi_axi_master inst_spi_axi_master 228 | ( 229 | .CEB(spi_axi_master_CEB), 230 | .SCLK(spi_axi_master_SCLK), 231 | .DATA(spi_axi_master_DATA), 232 | .DOUT(spi_axi_master_DOUT), 233 | .RST(RST), 234 | .PICORV_RST(PICORV_RST), 235 | .CLK(CLK), 236 | .axi_awvalid(m_axi_awvalid[1]), 237 | .axi_awready(m_axi_awready[1]), 238 | .axi_awaddr(m_axi_awaddr_o[1]), 239 | .axi_awprot(m_axi_awprot_o[1]), 240 | .axi_wvalid(m_axi_wvalid[1]), 241 | .axi_wready(m_axi_wready[1]), 242 | .axi_wdata(m_axi_wdata_o[1]), 243 | .axi_wstrb(m_axi_wstrb_o[1]), 244 | .axi_bvalid(m_axi_bvalid[1]), 245 | .axi_bready(m_axi_bready[1]), 246 | .axi_arvalid(m_axi_arvalid[1]), 247 | .axi_arready(m_axi_arready[1]), 248 | .axi_araddr(m_axi_araddr_o[1]), 249 | .axi_arprot(m_axi_arprot_o[1]), 250 | .axi_rvalid(m_axi_rvalid[1]), 251 | .axi_rready(m_axi_rready[1]), 252 | .axi_rdata(m_axi_rdata_o[1]) 253 | ); 254 | 255 | // Slave 1, AXI_SP32B1024 256 | AXI_SP32B1024 inst_AXI_SP32B1024( 257 | .CLK(CLK), 258 | .RST(RST), 259 | .axi_awvalid(s_axi_awvalid[0]), 260 | .axi_awready(s_axi_awready[0]), 261 | .axi_awaddr(s_axi_awaddr_o[0]), 262 | .axi_awprot(s_axi_awprot_o[0]), 263 | .axi_wvalid(s_axi_wvalid[0]), 264 | .axi_wready(s_axi_wready[0]), 265 | .axi_wdata(s_axi_wdata_o[0]), 266 | .axi_wstrb(s_axi_wstrb_o[0]), 267 | .axi_bvalid(s_axi_bvalid[0]), 268 | .axi_bready(s_axi_bready[0]), 269 | .axi_arvalid(s_axi_arvalid[0]), 270 | .axi_arready(s_axi_arready[0]), 271 | .axi_araddr(s_axi_araddr_o[0]), 272 | .axi_arprot(s_axi_arprot_o[0]), 273 | .axi_rvalid(s_axi_rvalid[0]), 274 | .axi_rready(s_axi_rready[0]), 275 | .axi_rdata(s_axi_rdata_o[0]), 276 | .Q(AXI_SP32B1024_Q), 277 | .CEN(AXI_SP32B1024_CEN), 278 | .WEN(AXI_SP32B1024_WEN), 279 | .A(AXI_SP32B1024_A), 280 | .D(AXI_SP32B1024_D) 281 | ); 282 | // THIS IS A STANDARD CELL! YOU IDIOT! 283 | SP32B1024 SP32B1024_INT( 284 | .Q (AXI_SP32B1024_Q), 285 | .CLK (CLK), 286 | .CEN (AXI_SP32B1024_CEN), 287 | .WEN (AXI_SP32B1024_WEN), 288 | .A (AXI_SP32B1024_A), 289 | .D (AXI_SP32B1024_D) 290 | ); 291 | 292 | // Slave 2, APB_TOP 293 | APB_TOP inst_APB_TOP( 294 | .RESETn(RST), 295 | .CLK(CLK), 296 | .PCLK(PCLK), 297 | .AWVALID(s_axi_awvalid[1]), 298 | .ARADDR(s_axi_araddr_o[1]), 299 | .WVALID(s_axi_wvalid[1]), 300 | .BREADY(s_axi_bready[1]), 301 | .AWADDR(s_axi_awaddr_o[1]), 302 | .WDATA(s_axi_wdata_o[1]), 303 | .STRB(s_axi_wstrb_o[1]), 304 | .AWREADY(s_axi_awready[1]), 305 | .WREADY(s_axi_wready[1]), 306 | .BVALID(s_axi_bvalid[1]), 307 | .ARVALID(s_axi_arvalid[1]), 308 | .RREADY(s_axi_rready[1]), 309 | .ARREADY(s_axi_arready[1]), 310 | .RVALID(s_axi_rvalid[1]), 311 | .RDATA(s_axi_rdata_o[1]), 312 | .DATA_DAC(DAC_interface_AXI_DATA), 313 | .BUSY(ADC_interface_AXI_BUSY), 314 | .DATA_ADC(ADC_interface_AXI_DATA), 315 | .pindata(completogpio_pindata), 316 | .Rx(completogpio_Rx), 317 | .Tx(completogpio_Tx), 318 | .datanw(completogpio_datanw), 319 | .DSE(completogpio_DSE), 320 | .CEB(APB_TOP_CEB), 321 | .SCLK(APB_TOP_SCLK), 322 | .DATA_SPI(APB_TOP_DATA_SPI) 323 | ); 324 | 325 | // Slave 3, spi_axi_slave 326 | spi_axi_slave inst_spi_axi_slave 327 | ( 328 | .CEB(spi_axi_slave_CEB), 329 | .SCLK(spi_axi_slave_SCLK), 330 | .DATA(spi_axi_slave_DATA), 331 | .RST(RST), 332 | .CLK(CLK), 333 | .axi_awvalid(s_axi_awvalid[2]), 334 | .axi_awready(s_axi_awready[2]), 335 | .axi_awaddr(s_axi_awaddr_o[2]), 336 | .axi_awprot(s_axi_awprot_o[2]), 337 | .axi_wvalid(s_axi_wvalid[2]), 338 | .axi_wready(s_axi_wready[2]), 339 | .axi_wdata(s_axi_wdata_o[2]), 340 | .axi_wstrb(s_axi_wstrb_o[2]), 341 | .axi_bvalid(s_axi_bvalid[2]), 342 | .axi_bready(s_axi_bready[2]), 343 | .axi_arvalid(s_axi_arvalid[2]), 344 | .axi_arready(s_axi_arready[2]), 345 | .axi_araddr(s_axi_araddr_o[2]), 346 | .axi_arprot(s_axi_arprot_o[2]), 347 | .axi_rvalid(s_axi_rvalid[2]), 348 | .axi_rready(s_axi_rready[2]), 349 | .axi_rdata(s_axi_rdata_o[2]) 350 | ); 351 | 352 | endmodule 353 | -------------------------------------------------------------------------------- /mriscv_axi/32-bit-100mhz.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/mriscv_axi/32-bit-100mhz.pdf -------------------------------------------------------------------------------- /mriscv_axi/ADC_interface_AXI/ADC_interface_AXI.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module ADC_interface_AXI (CLK,RST,AWVALID,WVALID,BREADY,AWADDR,WDATA,WSTRB,AWREADY,WREADY,BVALID,DATA,ARADDR,ARVALID,RREADY,ARREADY,RVALID,RDATA,BUSY); 3 | 4 | //----general--input---- 5 | input CLK,RST; 6 | //----write--input---- 7 | input AWVALID,WVALID, BREADY; 8 | input [31:0] AWADDR,WDATA; 9 | input [3:0] WSTRB; 10 | //----write--output---- 11 | output reg AWREADY, WREADY, BVALID; 12 | //----write--signals---- 13 | reg [2:0] state_write; 14 | //----read--input---- 15 | input [31:0] ARADDR; 16 | input ARVALID,RREADY,BUSY; 17 | input [9:0] DATA; 18 | //----read--output---- 19 | output reg ARREADY, RVALID; 20 | output wire [31:0] RDATA; 21 | //----read--signals---- 22 | reg [2:0] state_read; 23 | reg [9:0] latch_DATA; 24 | reg ena_rdata; 25 | 26 | //----FSM--WRITE---- 27 | 28 | parameter START_W = 3'b000, WAIT_BREADY = 3'b001, START_R = 3'b010, PROCESS = 3'b011; 29 | 30 | //----RESET--PARAMETERS---- 31 | 32 | always @( posedge CLK or negedge RST) 33 | begin 34 | if (RST == 1'b0) begin 35 | state_write = START_W; 36 | end 37 | //----LOGIC---- 38 | else 39 | begin 40 | case (state_write) 41 | START_W :if (AWVALID == 1'b1) 42 | begin 43 | state_write = WAIT_BREADY; 44 | end 45 | else 46 | begin 47 | state_write = START_W; 48 | end 49 | WAIT_BREADY : if (BREADY == 1'b1) 50 | begin 51 | state_write = START_W; 52 | end 53 | else 54 | begin 55 | state_write = WAIT_BREADY; 56 | end 57 | default : state_write = START_W; 58 | endcase 59 | end 60 | end 61 | //----OUTPUTS--FSM--WRITE---- 62 | always @(posedge CLK or negedge RST) 63 | begin 64 | if (RST == 1'b0) 65 | begin 66 | AWREADY <= 0; 67 | WREADY <= 0; 68 | BVALID <= 0; 69 | end 70 | //----LOGIC---- 71 | else 72 | begin 73 | case (state_write) 74 | START_W :begin //----0 75 | AWREADY <= 1; 76 | WREADY <= 0; 77 | BVALID <= 0; 78 | end 79 | WAIT_BREADY :begin //----1 80 | AWREADY <= 1; 81 | WREADY <= 1; 82 | BVALID <= 1; 83 | end 84 | endcase 85 | end 86 | end 87 | 88 | //----FSM--READ---- 89 | 90 | 91 | //----RESET--PARAMETERS---- 92 | always @( posedge CLK or negedge RST) 93 | begin 94 | if (~RST) begin 95 | state_read = START_R; 96 | end 97 | //----LOGIC---- 98 | else 99 | begin 100 | case (state_read) 101 | START_R :if (ARVALID == 1'b1) 102 | begin 103 | state_read = PROCESS; 104 | end 105 | else 106 | begin 107 | state_read = START_R; 108 | end 109 | 110 | PROCESS : if (RREADY == 1'b1) 111 | begin 112 | state_read = START_R; 113 | end 114 | else 115 | begin 116 | state_read = PROCESS; 117 | end 118 | 119 | default : state_read = START_R; 120 | endcase 121 | end 122 | end 123 | //----OUTPUTS--FSM--READ---- 124 | always @(posedge CLK) 125 | begin 126 | if (RST == 1'b0) 127 | begin 128 | ARREADY <= 0; 129 | RVALID <= 0; 130 | end 131 | 132 | //----LOGIC---- 133 | else 134 | begin 135 | case (state_read) 136 | START_R :begin 137 | ARREADY <= 0; 138 | RVALID <= 0; 139 | ena_rdata <= 0; 140 | end 141 | PROCESS :begin 142 | ARREADY <= 1; 143 | RVALID <= 1; 144 | ena_rdata <= 1; 145 | end 146 | default : begin 147 | ARREADY <= 0; 148 | RVALID <= 0; 149 | ena_rdata <= 0; 150 | end 151 | endcase 152 | end 153 | end 154 | 155 | //----FLIP--FLOPS--WRITE---- 156 | always @( posedge CLK ) 157 | begin 158 | if (~RST) begin 159 | latch_DATA <= 10'b0; 160 | end 161 | else begin 162 | if (BUSY) 163 | begin 164 | latch_DATA <= DATA; 165 | end 166 | else begin 167 | latch_DATA <= latch_DATA; 168 | end 169 | end 170 | end 171 | 172 | assign RDATA = ena_rdata ? latch_DATA:10'b0; 173 | 174 | endmodule 175 | 176 | 177 | -------------------------------------------------------------------------------- /mriscv_axi/ADC_interface_AXI/ADC_interface_AXI_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module DAC_interface_tb; 4 | parameter CLKPERIOD = 10; 5 | 6 | reg CLK = 0, RST; 7 | reg AWVALID, WVALID, BREADY; 8 | reg [31:0] AWADDR, WDATA; 9 | reg [3:0] WSTRB; 10 | reg ARVALID, RREADY, BUSY; 11 | reg [9:0] DATA; 12 | 13 | wire AWREADY, WREADY, BVALID; 14 | wire ARREADY, RVALID; 15 | wire [31:0] RDATA; 16 | 17 | ADC_interface_AXI ADC_interface_AXI_inst( 18 | .RST(RST), 19 | .CLK(CLK), 20 | .AWVALID(AWVALID), 21 | .WVALID(WVALID), 22 | .BREADY(BREADY), 23 | .AWADDR(AWADDR), 24 | .WDATA(WDATA), 25 | .WSTRB(WSTRB), 26 | .AWREADY(AWREADY), 27 | .WREADY(WREADY), 28 | .BVALID(BVALID), 29 | .ARVALID(ARVALID), 30 | .RREADY(RREADY), 31 | .BUSY(BUSY), 32 | .DATA(DATA), 33 | .ARREADY(ARREADY), 34 | .RVALID(RVALID), 35 | .RDATA(RDATA)); 36 | 37 | always 38 | begin 39 | #(CLKPERIOD/2) CLK = ~CLK; 40 | end 41 | 42 | initial begin 43 | 44 | RST <= 1'b0; 45 | 46 | #(CLKPERIOD*100);//-------------------------START_R--AND--START_W 47 | 48 | RST <= 1'b1; 49 | AWVALID <= 1'b0; 50 | WVALID <= 1'b0; 51 | BREADY <= 1'b0; 52 | AWADDR <= 32'b0; 53 | WDATA <= 32'b0; 54 | ARVALID <= 1'b0; 55 | RREADY <= 1'b0; 56 | DATA <= 57 | BUSY <= 58 | 59 | #(CLKPERIOD*5);//------------------------- 60 | 61 | RST <= 1'b1; 62 | AWVALID <= 1'b0; 63 | WVALID <= 1'b0; 64 | BREADY <= 1'b0; 65 | AWADDR <= 32'hfffffff1; 66 | WDATA <= 32'h12345678; 67 | ARVALID <= 1'b0; 68 | RREADY <= 1'b0; 69 | 70 | #(CLKPERIOD*5);//------------------------- 71 | 72 | RST <= 1'bx; 73 | AWVALID <= 1'bx; 74 | WVALID <= 1'bx; 75 | BREADY <= 1'bx; 76 | AWADDR <= 32'bx; 77 | WDATA <= 32'hx; 78 | ARVALID <= 1'bX; 79 | RREADY <= 1'bX; 80 | 81 | #(CLKPERIOD*5);//------------------------- 82 | 83 | RST <= 1'bz; 84 | AWVALID <= 1'bz; 85 | WVALID <= 1'bz; 86 | BREADY <= 1'bz; 87 | AWADDR <= 32'bz; 88 | WDATA <= 32'hz; 89 | ARVALID <= 1'bZ; 90 | RREADY <= 1'bZ; 91 | 92 | #(CLKPERIOD*5);//------------------------- 93 | 94 | RST <= 1'b1; 95 | AWVALID <= 1'b1; 96 | WVALID <= 1'b0; 97 | BREADY <= 1'b0; 98 | AWADDR <= 32'hfffffff1; 99 | WDATA <= 32'h12345678; 100 | ARVALID <= 1'b1; 101 | RREADY <= 1'b0; 102 | 103 | #(CLKPERIOD*10);//-------------------------WAIT_WVALID--AND--WAIT_RREADY 104 | 105 | RST <= 1'b1; 106 | AWVALID <= 1'b0; 107 | WVALID <= 1'b0; 108 | BREADY <= 1'b0; 109 | AWADDR <= 32'b0; 110 | WDATA <= 32'b0; 111 | ARVALID <= 1'b0; 112 | RREADY <= 1'b0; 113 | 114 | #(CLKPERIOD*5);//------------------------- 115 | 116 | RST <= 1'b1; 117 | AWVALID <= 1'b0; 118 | WVALID <= 1'b0; 119 | BREADY <= 1'b0; 120 | AWADDR <= 32'hfffffff1; 121 | WDATA <= 32'h12345678; 122 | ARVALID <= 1'b0; 123 | RREADY <= 1'b0; 124 | 125 | 126 | #(CLKPERIOD*5);//------------------------- 127 | 128 | RST <= 1'bX; 129 | AWVALID <= 1'bX; 130 | WVALID <= 1'bX; 131 | BREADY <= 1'bX; 132 | AWADDR <= 32'bX; 133 | WDATA <= 32'bX; 134 | ARVALID <= 1'bX; 135 | RREADY <= 1'bX; 136 | 137 | 138 | #(CLKPERIOD*5);//------------------------- 139 | 140 | RST <= 1'bZ; 141 | AWVALID <= 1'bZ; 142 | WVALID <= 1'bZ; 143 | BREADY <= 1'bZ; 144 | AWADDR <= 32'bZ; 145 | WDATA <= 32'bZ; 146 | ARVALID <= 1'bZ; 147 | RREADY <= 1'bZ; 148 | 149 | #(CLKPERIOD*5);//------------------------- 150 | 151 | RST <= 1'b1; 152 | AWVALID <= 1'b0; 153 | WVALID <= 1'b1; 154 | BREADY <= 1'b1; 155 | AWADDR <= 32'hfffffff1; 156 | WDATA <= 32'h12345678; 157 | ARVALID <= 1'b0; 158 | RREADY <= 1'b1; 159 | 160 | #(CLKPERIOD*10);//-------------------------WORKING--AND--START_R 161 | 162 | RST <= 1'b1; 163 | AWVALID <= 1'b0; 164 | WVALID <= 1'b0; 165 | BREADY <= 1'b0; 166 | AWADDR <= 32'b0; 167 | WDATA <= 32'b0; 168 | ARVALID <= 1'b0; 169 | RREADY <= 1'b0; 170 | 171 | #(CLKPERIOD*5);//------------------------- 172 | 173 | RST <= 1'b1; 174 | AWVALID <= 1'b0; 175 | WVALID <= 1'b0; 176 | BREADY <= 1'b0; 177 | AWADDR <= 32'hfffffff1; 178 | WDATA <= 32'h12345678; 179 | ARVALID <= 1'b0; 180 | RREADY <= 1'b0; 181 | 182 | #(CLKPERIOD*5);//------------------------- 183 | 184 | RST <= 1'bX; 185 | AWVALID <= 1'bX; 186 | WVALID <= 1'bX; 187 | BREADY <= 1'b0; 188 | AWADDR <= 32'bX; 189 | WDATA <= 32'bX; 190 | ARVALID <= 1'bX; 191 | RREADY <= 1'bX; 192 | 193 | #(CLKPERIOD*5);//------------------------- 194 | 195 | RST <= 1'bZ; 196 | AWVALID <= 1'bZ; 197 | WVALID <= 1'bZ; 198 | BREADY <= 1'bZ; 199 | AWADDR <= 32'bZ; 200 | WDATA <= 32'bZ; 201 | ARVALID <= 1'bZ; 202 | RREADY <= 1'bZ; 203 | 204 | #(CLKPERIOD*5);//------------------------- 205 | 206 | RST <= 1'b1; 207 | AWVALID <= 1'b0; 208 | WVALID <= 1'b0; 209 | BREADY <= 1'b0; 210 | AWADDR <= 32'b0; 211 | WDATA <= 32'b0; 212 | ARVALID <= 1'b0; 213 | RREADY <= 1'b0; 214 | 215 | #(CLKPERIOD*10); 216 | 217 | //----------------------------------reset------------------------ 218 | 219 | RST <= 1'b0; 220 | 221 | #(CLKPERIOD*100);//-------------------------START_R--AND--START_W 222 | 223 | RST <= 1'b1; 224 | AWVALID <= 1'b0; 225 | WVALID <= 1'b0; 226 | BREADY <= 1'b0; 227 | AWADDR <= 32'b0; 228 | WDATA <= 32'b0; 229 | ARVALID <= 1'b0; 230 | RREADY <= 1'b0; 231 | 232 | #(CLKPERIOD*5);//------------------------- 233 | 234 | RST <= 1'b1; 235 | AWVALID <= 1'b0; 236 | WVALID <= 1'b0; 237 | BREADY <= 1'b0; 238 | AWADDR <= 32'hfffffff2; 239 | WDATA <= 32'h87654321; 240 | ARVALID <= 1'b0; 241 | RREADY <= 1'b0; 242 | 243 | #(CLKPERIOD*5);//------------------------- 244 | 245 | RST <= 1'bx; 246 | AWVALID <= 1'bx; 247 | WVALID <= 1'bx; 248 | BREADY <= 1'bx; 249 | AWADDR <= 32'bx; 250 | WDATA <= 32'hx; 251 | ARVALID <= 1'bX; 252 | RREADY <= 1'bX; 253 | 254 | #(CLKPERIOD*5);//------------------------- 255 | 256 | RST <= 1'bz; 257 | AWVALID <= 1'bz; 258 | WVALID <= 1'bz; 259 | BREADY <= 1'bz; 260 | AWADDR <= 32'bz; 261 | WDATA <= 32'hz; 262 | ARVALID <= 1'bZ; 263 | RREADY <= 1'bZ; 264 | 265 | #(CLKPERIOD*5);//------------------------- 266 | 267 | RST <= 1'b1; 268 | AWVALID <= 1'b1; 269 | WVALID <= 1'b0; 270 | BREADY <= 1'b0; 271 | AWADDR <= 32'hfffffff2; 272 | WDATA <= 32'h87654321; 273 | ARVALID <= 1'b1; 274 | RREADY <= 1'b0; 275 | 276 | #(CLKPERIOD*10);//-------------------------WAIT_WVALID--AND--WAIT_RREADY 277 | 278 | RST <= 1'b1; 279 | AWVALID <= 1'b0; 280 | WVALID <= 1'b0; 281 | BREADY <= 1'b0; 282 | AWADDR <= 32'b0; 283 | WDATA <= 32'b0; 284 | ARVALID <= 1'b0; 285 | RREADY <= 1'b0; 286 | 287 | #(CLKPERIOD*5);//------------------------- 288 | 289 | RST <= 1'b1; 290 | AWVALID <= 1'b0; 291 | WVALID <= 1'b0; 292 | BREADY <= 1'b0; 293 | AWADDR <= 32'hfffffff2; 294 | WDATA <= 32'h87654321; 295 | ARVALID <= 1'b0; 296 | RREADY <= 1'b0; 297 | 298 | 299 | #(CLKPERIOD*5);//------------------------- 300 | 301 | RST <= 1'bX; 302 | AWVALID <= 1'bX; 303 | WVALID <= 1'bX; 304 | BREADY <= 1'bX; 305 | AWADDR <= 32'bX; 306 | WDATA <= 32'bX; 307 | ARVALID <= 1'bX; 308 | RREADY <= 1'bX; 309 | 310 | 311 | #(CLKPERIOD*5);//------------------------- 312 | 313 | RST <= 1'bZ; 314 | AWVALID <= 1'bZ; 315 | WVALID <= 1'bZ; 316 | BREADY <= 1'bZ; 317 | AWADDR <= 32'bZ; 318 | WDATA <= 32'bZ; 319 | ARVALID <= 1'bZ; 320 | RREADY <= 1'bZ; 321 | 322 | #(CLKPERIOD*5);//------------------------- 323 | 324 | RST <= 1'b1; 325 | AWVALID <= 1'b0; 326 | WVALID <= 1'b1; 327 | BREADY <= 1'b1; 328 | AWADDR <= 32'hfffffff2; 329 | WDATA <= 32'h87654321; 330 | ARVALID <= 1'b0; 331 | RREADY <= 1'b1; 332 | 333 | #(CLKPERIOD*10);//-------------------------WORKING--AND--START_R 334 | 335 | RST <= 1'b1; 336 | AWVALID <= 1'b0; 337 | WVALID <= 1'b0; 338 | BREADY <= 1'b0; 339 | AWADDR <= 32'b0; 340 | WDATA <= 32'b0; 341 | ARVALID <= 1'b0; 342 | RREADY <= 1'b0; 343 | 344 | #(CLKPERIOD*5);//------------------------- 345 | 346 | RST <= 1'b1; 347 | AWVALID <= 1'b0; 348 | WVALID <= 1'b0; 349 | BREADY <= 1'b0; 350 | AWADDR <= 32'hfffffff2; 351 | WDATA <= 32'h87654321; 352 | ARVALID <= 1'b0; 353 | RREADY <= 1'b0; 354 | 355 | #(CLKPERIOD*5);//------------------------- 356 | 357 | RST <= 1'bX; 358 | AWVALID <= 1'bX; 359 | WVALID <= 1'bX; 360 | BREADY <= 1'b0; 361 | AWADDR <= 32'bX; 362 | WDATA <= 32'bX; 363 | ARVALID <= 1'bX; 364 | RREADY <= 1'bX; 365 | 366 | #(CLKPERIOD*5);//------------------------- 367 | 368 | RST <= 1'bZ; 369 | AWVALID <= 1'bZ; 370 | WVALID <= 1'bZ; 371 | BREADY <= 1'bZ; 372 | AWADDR <= 32'bZ; 373 | WDATA <= 32'bZ; 374 | ARVALID <= 1'bZ; 375 | RREADY <= 1'bZ; 376 | 377 | #(CLKPERIOD*5);//------------------------- 378 | 379 | 380 | RST <= 1'b1; 381 | AWVALID <= 1'b0; 382 | WVALID <= 1'b0; 383 | BREADY <= 1'b0; 384 | AWADDR <= 32'b0; 385 | WDATA <= 32'b0; 386 | ARVALID <= 1'b0; 387 | RREADY <= 1'b1; 388 | 389 | #(CLKPERIOD*10) 390 | 391 | //-------------------------START_R--AND--START_W 392 | 393 | //----------------------------------NO--reset------------------------ 394 | 395 | //RST <= 1'b0; 396 | 397 | #(CLKPERIOD*100);//-------------------------START_R--AND--START_W 398 | 399 | RST <= 1'b1; 400 | AWVALID <= 1'b0; 401 | WVALID <= 1'b0; 402 | BREADY <= 1'b0; 403 | AWADDR <= 32'b0; 404 | WDATA <= 32'b0; 405 | ARVALID <= 1'b0; 406 | RREADY <= 1'b0; 407 | 408 | #(CLKPERIOD*5);//------------------------- 409 | 410 | RST <= 1'b1; 411 | AWVALID <= 1'b0; 412 | WVALID <= 1'b0; 413 | BREADY <= 1'b0; 414 | AWADDR <= 32'hfffffff3; 415 | WDATA <= 32'h55555555; 416 | ARVALID <= 1'b0; 417 | RREADY <= 1'b0; 418 | 419 | #(CLKPERIOD*5);//------------------------- 420 | 421 | RST <= 1'bx; 422 | AWVALID <= 1'bx; 423 | WVALID <= 1'bx; 424 | BREADY <= 1'bx; 425 | AWADDR <= 32'bx; 426 | WDATA <= 32'hx; 427 | ARVALID <= 1'bX; 428 | RREADY <= 1'bX; 429 | 430 | #(CLKPERIOD*5);//------------------------- 431 | 432 | RST <= 1'bz; 433 | AWVALID <= 1'bz; 434 | WVALID <= 1'bz; 435 | BREADY <= 1'bz; 436 | AWADDR <= 32'bz; 437 | WDATA <= 32'hz; 438 | ARVALID <= 1'bZ; 439 | RREADY <= 1'bZ; 440 | 441 | #(CLKPERIOD*5);//------------------------- 442 | 443 | RST <= 1'b1; 444 | AWVALID <= 1'b1; 445 | WVALID <= 1'b0; 446 | BREADY <= 1'b0; 447 | AWADDR <= 32'hfffffff3; 448 | WDATA <= 32'h55555555; 449 | ARVALID <= 1'b1; 450 | RREADY <= 1'b0; 451 | 452 | #(CLKPERIOD*10);//-------------------------WAIT_WVALID--AND--WAIT_RREADY 453 | 454 | RST <= 1'b1; 455 | AWVALID <= 1'b0; 456 | WVALID <= 1'b0; 457 | BREADY <= 1'b0; 458 | AWADDR <= 32'b0; 459 | WDATA <= 32'b0; 460 | ARVALID <= 1'b0; 461 | RREADY <= 1'b0; 462 | 463 | #(CLKPERIOD*5);//------------------------- 464 | 465 | RST <= 1'b1; 466 | AWVALID <= 1'b0; 467 | WVALID <= 1'b0; 468 | BREADY <= 1'b0; 469 | AWADDR <= 32'hfffffff3; 470 | WDATA <= 32'h55555555; 471 | ARVALID <= 1'b0; 472 | RREADY <= 1'b0; 473 | 474 | 475 | #(CLKPERIOD*5);//------------------------- 476 | 477 | RST <= 1'bX; 478 | AWVALID <= 1'bX; 479 | WVALID <= 1'bX; 480 | BREADY <= 1'bX; 481 | AWADDR <= 32'bX; 482 | WDATA <= 32'bX; 483 | ARVALID <= 1'bX; 484 | RREADY <= 1'bX; 485 | 486 | 487 | #(CLKPERIOD*5);//------------------------- 488 | 489 | RST <= 1'bZ; 490 | AWVALID <= 1'bZ; 491 | WVALID <= 1'bZ; 492 | BREADY <= 1'bZ; 493 | AWADDR <= 32'bZ; 494 | WDATA <= 32'bZ; 495 | ARVALID <= 1'bZ; 496 | RREADY <= 1'bZ; 497 | 498 | #(CLKPERIOD*5);//------------------------- 499 | 500 | 501 | RST <= 1'b1; 502 | AWVALID <= 1'b0; 503 | WVALID <= 1'b1; 504 | BREADY <= 1'b1; 505 | AWADDR <= 32'hfffffff3; 506 | WDATA <= 32'h55555555; 507 | ARVALID <= 1'b0; 508 | RREADY <= 1'b1; 509 | 510 | #(CLKPERIOD*10);//-------------------------WORKING--AND--START_R 511 | 512 | RST <= 1'b1; 513 | AWVALID <= 1'b0; 514 | WVALID <= 1'b0; 515 | BREADY <= 1'b0; 516 | AWADDR <= 32'b0; 517 | WDATA <= 32'b0; 518 | ARVALID <= 1'b0; 519 | RREADY <= 1'b0; 520 | 521 | #(CLKPERIOD*5);//------------------------- 522 | 523 | RST <= 1'b1; 524 | AWVALID <= 1'b0; 525 | WVALID <= 1'b0; 526 | BREADY <= 1'b0; 527 | AWADDR <= 32'hfffffff3; 528 | WDATA <= 32'h55555555; 529 | ARVALID <= 1'b0; 530 | RREADY <= 1'b0; 531 | 532 | #(CLKPERIOD*5);//------------------------- 533 | 534 | RST <= 1'bX; 535 | AWVALID <= 1'bX; 536 | WVALID <= 1'bX; 537 | BREADY <= 1'b0; 538 | AWADDR <= 32'bX; 539 | WDATA <= 32'bX; 540 | ARVALID <= 1'bX; 541 | RREADY <= 1'bX; 542 | 543 | #(CLKPERIOD*5);//------------------------- 544 | 545 | RST <= 1'bZ; 546 | AWVALID <= 1'bZ; 547 | WVALID <= 1'bZ; 548 | BREADY <= 1'bZ; 549 | AWADDR <= 32'bZ; 550 | WDATA <= 32'bZ; 551 | ARVALID <= 1'bZ; 552 | RREADY <= 1'bZ; 553 | 554 | #(CLKPERIOD*5);//------------------------- 555 | 556 | RST <= 1'b1; 557 | AWVALID <= 1'b0; 558 | WVALID <= 1'b0; 559 | BREADY <= 1'b0; 560 | AWADDR <= 32'b0; 561 | WDATA <= 32'b0; 562 | ARVALID <= 1'b0; 563 | RREADY <= 1'b0; 564 | 565 | #(CLKPERIOD*10) 566 | 567 | //-------------------------START--AND--WAIT_RREADY 568 | 569 | $finish; 570 | 571 | end 572 | endmodule 573 | -------------------------------------------------------------------------------- /mriscv_axi/AXI_SP32B1024/AXI_SP32B1024.v: -------------------------------------------------------------------------------- 1 | module AXI_SP32B1024( 2 | input CLK, 3 | input RST, 4 | 5 | // AXI-4 SLAVE Interface 6 | input axi_awvalid, 7 | output axi_awready, 8 | input [32-1:0] axi_awaddr, 9 | input [3-1:0] axi_awprot, 10 | 11 | input axi_wvalid, 12 | output axi_wready, 13 | input [32-1:0] axi_wdata, 14 | input [4-1:0] axi_wstrb, 15 | 16 | output axi_bvalid, 17 | input axi_bready, 18 | 19 | input axi_arvalid, 20 | output axi_arready, 21 | input [32-1:0] axi_araddr, 22 | input [3-1:0] axi_arprot, 23 | 24 | output axi_rvalid, 25 | input axi_rready, 26 | output [32-1:0] axi_rdata, 27 | 28 | // Memory Interface 29 | input [31:0] Q, 30 | output reg CEN, 31 | output reg WEN, 32 | output reg [9:0] A, 33 | output [31:0] D 34 | ); 35 | 36 | // The address capturing is a single operation, we can handle this always 1 37 | assign axi_awready = 1'b1; 38 | assign axi_arready = 1'b1; 39 | assign axi_wready = 1'b1; 40 | //reg [9:0] A; 41 | reg [31:0] DP; 42 | //wire [31:0] Q; 43 | assign axi_rdata = Q; 44 | // For memory, we provide the signals in negedge, because the setup and hold sh*t 45 | always @(negedge CLK) begin 46 | if (RST==1'b0) begin 47 | A <= {10{1'b0}}; 48 | DP <= {32{1'b0}}; 49 | end else begin 50 | if(axi_awvalid == 1'b1) begin 51 | A <= axi_awaddr[9:0]; 52 | end else if(axi_arvalid == 1'b1) begin 53 | A <= axi_araddr[9:0]; 54 | end 55 | 56 | if(axi_wvalid == 1'b1) begin 57 | DP <= axi_wdata; 58 | end 59 | end 60 | end 61 | 62 | // Flags for reading 63 | reg reading1, reading2; 64 | assign axi_rvalid = reading2; 65 | always @(posedge CLK) begin 66 | if (RST==1'b0) begin 67 | reading1 <= 1'b0; 68 | reading2 <= 1'b0; 69 | end else begin 70 | if(axi_rready == 1'b1 && reading1 == 1'b1 && reading2 == 1'b1) begin 71 | reading1 <= 1'b0; 72 | end else if(axi_arvalid == 1'b1) begin 73 | reading1 <= 1'b1; 74 | end 75 | 76 | if(axi_rready == 1'b1 && reading1 == 1'b1 && reading2 == 1'b1) begin 77 | reading2 <= 1'b0; 78 | end else if(reading1 == 1'b1) begin 79 | reading2 <= 1'b1; 80 | end 81 | end 82 | end 83 | 84 | // Flags for writting 85 | reg writting1, writting2, writting3; 86 | assign axi_bvalid = writting3; 87 | always @(posedge CLK) begin 88 | if (RST==1'b0) begin 89 | writting1 <= 1'b0; 90 | writting2 <= 1'b0; 91 | writting3 <= 1'b0; 92 | end else begin 93 | 94 | if(axi_bready == 1'b1 && writting1 == 1'b1 && writting2 == 1'b1 && writting3 == 1'b1) begin 95 | writting3 <= 1'b0; 96 | end else if(writting2 == 1'b1) begin 97 | writting3 <= 1'b1; 98 | end else begin 99 | writting3 <= writting3; 100 | end 101 | 102 | if(axi_bready == 1'b1 && writting1 == 1'b1 && writting2 == 1'b1 && writting3 == 1'b1) begin 103 | writting1 <= 1'b0; 104 | end else if(axi_awvalid == 1'b1) begin 105 | writting1 <= 1'b1; 106 | end else begin 107 | writting1 <= writting1; 108 | end 109 | 110 | if(axi_bready == 1'b1 && writting1 == 1'b1 && writting2 == 1'b1 && writting3 == 1'b1) begin 111 | writting2 <= 1'b0; 112 | end else if(axi_wvalid == 1'b1) begin 113 | writting2 <= 1'b1; 114 | end else begin 115 | writting2 <= writting2; 116 | end 117 | end 118 | end 119 | 120 | // Control of memory based on Flags 121 | //reg CEN, WEN; 122 | // For memory, we provide the signals in negedge, because the setup and hold sh*t 123 | always @(negedge CLK) begin 124 | if (RST==1'b0) begin 125 | CEN <= 1'b1; 126 | WEN <= 1'b1; 127 | end else begin 128 | CEN <= ~(reading1 | writting1); 129 | WEN <= ~writting2; 130 | end 131 | end 132 | //wire [31:0] D; 133 | assign D[7:0] = axi_wstrb[0]?DP[7:0] :Q[7:0]; 134 | assign D[15:8] = axi_wstrb[1]?DP[15:8] :Q[15:8]; 135 | assign D[23:16] = axi_wstrb[2]?DP[23:16]:Q[23:16]; 136 | assign D[31:24] = axi_wstrb[3]?DP[31:24]:Q[31:24]; 137 | 138 | // Thanks god, the memory provides their data in posedge. 139 | /*SP32B1024 THEMEMORY( 140 | .Q(Q), 141 | .CLK(CLK), 142 | .CEN(CEN), 143 | .WEN(WEN), 144 | .A(A), 145 | .D(D) 146 | );*/ 147 | endmodule 148 | -------------------------------------------------------------------------------- /mriscv_axi/AXI_SP32B1024/AXI_SP32B1024_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module AXI_SP32B1024_tb(); 4 | 5 | // HELPER 6 | function integer clogb2; 7 | input integer value; 8 | integer i; 9 | begin 10 | clogb2 = 0; 11 | for(i = 0; 2**i < value; i = i + 1) 12 | clogb2 = i + 1; 13 | end 14 | endfunction 15 | 16 | 17 | // Autogen localparams 18 | 19 | localparam BITS = 32; 20 | localparam word_depth = 1024; 21 | localparam addr_width = 10; 22 | localparam wordx = {BITS{1'bx}}; 23 | localparam addrx = {addr_width{1'bx}}; 24 | 25 | reg CLK = 1'b0; 26 | reg RST; 27 | 28 | // AXI4-lite master memory interfaces 29 | 30 | reg axi_awvalid; 31 | wire axi_awready; 32 | reg [32-1:0] axi_awaddr; 33 | reg [3-1:0] axi_awprot; 34 | 35 | reg axi_wvalid; 36 | wire axi_wready; 37 | reg [32-1:0] axi_wdata; 38 | reg [4-1:0] axi_wstrb; 39 | 40 | wire axi_bvalid; 41 | reg axi_bready; 42 | 43 | reg axi_arvalid; 44 | wire axi_arready; 45 | reg [32-1:0] axi_araddr; 46 | reg [3-1:0] axi_arprot; 47 | 48 | wire axi_rvalid; 49 | reg axi_rready; 50 | wire [32-1:0] axi_rdata; 51 | 52 | 53 | integer fd1, tmp1, ifstop; 54 | integer PERIOD = 20 ; 55 | integer i, j, error, l; 56 | 57 | 58 | AXI_SP32B1024_INTERCONNECT 59 | inst_AXI_SP32B1024_INTERCONNECT 60 | ( 61 | .CLK (CLK), 62 | .RST (RST), 63 | .axi_awvalid(axi_awvalid), 64 | .axi_awready(axi_awready), 65 | .axi_awaddr(axi_awaddr), 66 | .axi_awprot(axi_awprot), 67 | .axi_wvalid(axi_wvalid), 68 | .axi_wready(axi_wready), 69 | .axi_wdata(axi_wdata), 70 | .axi_wstrb(axi_wstrb), 71 | .axi_bvalid(axi_bvalid), 72 | .axi_bready(axi_bready), 73 | .axi_arvalid(axi_arvalid), 74 | .axi_arready(axi_arready), 75 | .axi_araddr(axi_araddr), 76 | .axi_arprot(axi_arprot), 77 | .axi_rvalid(axi_rvalid), 78 | .axi_rready(axi_rready), 79 | .axi_rdata(axi_rdata) 80 | ); 81 | 82 | always 83 | begin #(PERIOD/2) CLK = ~CLK; end 84 | 85 | task aexpect; 86 | input [BITS-1:0] av, e; 87 | begin 88 | if (av == e) 89 | $display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. MATCH!", av, e); 90 | else 91 | begin 92 | $display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. ERROR!", av, e); 93 | error = error + 1; 94 | end 95 | end 96 | endtask 97 | 98 | reg [63:0] xorshift64_state = 64'd88172645463325252; 99 | 100 | task xorshift64_next; 101 | begin 102 | // see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14). 103 | xorshift64_state = xorshift64_state ^ (xorshift64_state << 13); 104 | xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7); 105 | xorshift64_state = xorshift64_state ^ (xorshift64_state << 17); 106 | end 107 | endtask 108 | 109 | 110 | initial begin 111 | $sdf_annotate("AXI_SP32B1024.sdf",inst_AXI_SP32B1024_INTERCONNECT); 112 | CLK = 1'b1; 113 | RST = 1'b0; 114 | error = 0; 115 | axi_awvalid = 1'b0; 116 | axi_wvalid = 1'b0; 117 | axi_bready = 1'b0; 118 | axi_arvalid = 1'b0; 119 | axi_rready = 1'b0; 120 | axi_awaddr = {32{1'b0}}; 121 | axi_awprot = {3{1'b0}}; 122 | axi_wdata = {32{1'b0}}; 123 | axi_wstrb = 4'b1111; 124 | axi_araddr = {32{1'b0}}; 125 | axi_arprot = {3{1'b0}}; 126 | #101; 127 | RST = 1'b1; 128 | // init the memory (AXI style) 129 | for(i = 0; i < word_depth; i = i+1) begin 130 | #(PERIOD); 131 | // WRITTING TEST 132 | axi_awaddr = i & (word_depth-1); 133 | axi_awvalid = 1'b1; 134 | #PERIOD; 135 | while(!axi_awready) begin 136 | #PERIOD; 137 | end 138 | axi_wvalid = 1'b1; 139 | axi_wdata = xorshift64_state[BITS-1:0]; 140 | while(!axi_wready) begin 141 | #PERIOD; 142 | end 143 | while(!axi_bvalid) begin 144 | #PERIOD; 145 | end 146 | axi_bready = 1'b1; 147 | #PERIOD; 148 | axi_awvalid = 1'b0; 149 | axi_wvalid = 1'b0; 150 | axi_bready = 1'b0; 151 | xorshift64_next; 152 | end 153 | //$stop; 154 | // WRITTING AND READING TEST 155 | // BASICALLY, WHAT I READ, IS WHAT I WRITE 156 | for(i = 0; i < word_depth; i = i+1) begin 157 | #(PERIOD*8); 158 | //axi_wstrb = 1<<(i%4); // Set me ACTIVE if you want to see the behavioral with strobes, but all checking will fail 159 | // WRITTING TEST 160 | axi_awaddr = i & (word_depth-1); 161 | axi_awvalid = 1'b1; 162 | #PERIOD; 163 | while(!axi_awready) begin 164 | #PERIOD; 165 | end 166 | axi_wvalid = 1'b1; 167 | axi_wdata = xorshift64_state[BITS-1:0]; 168 | while(!axi_wready) begin 169 | #PERIOD; 170 | end 171 | while(!axi_bvalid) begin 172 | #PERIOD; 173 | end 174 | axi_bready = 1'b1; 175 | #PERIOD; 176 | axi_awvalid = 1'b0; 177 | axi_wvalid = 1'b0; 178 | axi_bready = 1'b0; 179 | // READING TEST 180 | #(PERIOD*8); 181 | axi_arvalid = 1'b1; 182 | axi_araddr = i & (word_depth-1); 183 | #PERIOD; 184 | while(!axi_arready) begin 185 | #PERIOD; 186 | end 187 | while(!axi_rvalid) begin 188 | #PERIOD; 189 | end 190 | axi_rready = 1'b1; 191 | aexpect(axi_rdata, xorshift64_state[BITS-1:0]); 192 | #PERIOD; 193 | axi_arvalid = 1'b0; 194 | axi_rready = 1'b0; 195 | xorshift64_next; 196 | end 197 | $timeformat(-9,0,"ns",7); 198 | #(PERIOD*8) if (error == 0) 199 | $display("All match"); 200 | else 201 | $display("Mismatches = %d", error); 202 | $finish; 203 | end 204 | 205 | endmodule 206 | -------------------------------------------------------------------------------- /mriscv_axi/DAC_interface_AXI/DAC_interface_AXI.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module DAC_interface_AXI(CLK,RST,AWVALID,WVALID,BREADY,AWADDR,WDATA,WSTRB,AWREADY,WREADY,BVALID,DATA,ARVALID,RREADY,ARREADY,RVALID,RDATA); 3 | 4 | //----general--input---- 5 | input CLK,RST; 6 | //----write--input---- 7 | input AWVALID,WVALID, BREADY; 8 | input [31:0] AWADDR,WDATA; 9 | input [3:0] WSTRB; 10 | //----write--output---- 11 | output reg AWREADY, WREADY, BVALID; 12 | output wire [11:0] DATA; 13 | //----write--signals---- 14 | reg [4:0] delay; 15 | reg [2:0] state_write; 16 | reg [11:0] latch_WDATA; 17 | reg latch_reset, Q_WVALID, ena_DATA; 18 | wire latch_WVALID; 19 | //----read--input---- 20 | input ARVALID,RREADY; 21 | //----read--output---- 22 | output reg ARREADY, RVALID; 23 | output reg [31:0] RDATA; 24 | //----read--signals---- 25 | reg state_read; 26 | 27 | //----FSM--WRITE---- 28 | 29 | parameter START_W = 3'b000, WAIT_WVALID = 3'b001, SAVE_WDATA = 3'b010, WORKING = 3'b011, RESET = 3'b100, START_R = 1'b0, WAIT_RREADY = 1'b1; 30 | 31 | //----RESET--PARAMETERS---- 32 | 33 | always @( posedge CLK or negedge RST) 34 | begin 35 | if (RST == 1'b0) begin 36 | state_write = START_W; 37 | delay = 5'b00000; 38 | end 39 | //----LOGIC---- 40 | else 41 | begin 42 | case (state_write) 43 | 44 | START_W :if (AWVALID == 1'b1) 45 | begin 46 | state_write = WAIT_WVALID; 47 | delay = 5'b00000; 48 | end 49 | else 50 | begin 51 | state_write = START_W; 52 | end 53 | 54 | WAIT_WVALID : if (WVALID == 1'b1) 55 | begin 56 | state_write = SAVE_WDATA; 57 | end 58 | else 59 | begin 60 | state_write = WAIT_WVALID; 61 | end 62 | 63 | 64 | SAVE_WDATA : 65 | begin 66 | state_write = WORKING; 67 | end 68 | 69 | 70 | WORKING : if (delay == 5'b01010) 71 | begin 72 | state_write = RESET; 73 | end 74 | else 75 | begin 76 | state_write = WORKING; 77 | delay = delay + 5'b00001; 78 | end 79 | 80 | 81 | RESET : if (BREADY == 1'b1) 82 | begin 83 | state_write = START_W; 84 | end 85 | else 86 | begin 87 | state_write = RESET; 88 | end 89 | 90 | default : 91 | begin 92 | state_write = START_W; 93 | end 94 | 95 | endcase 96 | end 97 | end 98 | //----OUTPUTS--FSM--WRITE---- 99 | always @(state_write or RST) 100 | begin 101 | if (RST == 1'b0) 102 | begin 103 | AWREADY = 0; 104 | WREADY = 0; 105 | BVALID = 0; 106 | ena_DATA = 0; 107 | latch_reset = 0; 108 | end 109 | //----LOGIC---- 110 | else 111 | begin 112 | case (state_write) 113 | START_W :begin //----0 114 | AWREADY = 0; 115 | WREADY = 0; 116 | BVALID = 0; 117 | ena_DATA = 1; 118 | latch_reset = 0; 119 | end 120 | WAIT_WVALID :begin //----1 121 | AWREADY = 1; 122 | WREADY = 0; 123 | BVALID = 0; 124 | ena_DATA = 1; 125 | latch_reset = 0; 126 | end 127 | SAVE_WDATA :begin //----2 128 | AWREADY = 1; 129 | WREADY = 1; 130 | BVALID = 0; 131 | ena_DATA = 1; 132 | latch_reset = 0; 133 | end 134 | WORKING :begin //----3 135 | AWREADY = 1; 136 | WREADY = 1; 137 | BVALID = 0; 138 | ena_DATA = 1; 139 | latch_reset = 0; 140 | end 141 | RESET :begin //----4 142 | AWREADY = 1; 143 | WREADY = 1; 144 | BVALID = 1; 145 | ena_DATA = 1; 146 | latch_reset = 1; 147 | end 148 | 149 | default :begin 150 | AWREADY = 0; 151 | WREADY = 0; 152 | BVALID = 0; 153 | ena_DATA = 1; 154 | latch_reset = 0; 155 | end 156 | 157 | 158 | 159 | endcase 160 | end 161 | end 162 | //----LATCH_WVALID---- 163 | 164 | assign latch_WVALID = WVALID & ~Q_WVALID; 165 | 166 | always @( posedge CLK ) 167 | begin 168 | if (RST == 1'b0 || latch_reset ) 169 | begin 170 | Q_WVALID <= 1'b0; 171 | end 172 | else 173 | begin 174 | Q_WVALID <= WVALID; 175 | end 176 | end 177 | 178 | 179 | //----FLIP--FLOPS--WRITE---- 180 | 181 | always @( posedge CLK ) 182 | begin 183 | if (RST == 1'b0) 184 | begin 185 | latch_WDATA <= 32'b0; 186 | end 187 | else if (latch_WVALID) 188 | begin 189 | latch_WDATA <= WDATA; 190 | end 191 | else 192 | begin 193 | latch_WDATA <= latch_WDATA; 194 | end 195 | end 196 | 197 | //----OUTPUT--DATA---- 198 | 199 | assign DATA = ena_DATA ? latch_WDATA : 12'b0; 200 | 201 | //----FSM--READ---- 202 | 203 | 204 | //----RESET--PARAMETERS---- 205 | always @( posedge CLK or negedge RST) 206 | begin 207 | if (RST == 1'b0) begin 208 | state_read = START_R; 209 | end 210 | //----LOGIC---- 211 | else 212 | begin 213 | case (state_read) 214 | START_R :if (ARVALID == 1'b1) 215 | begin 216 | state_read = WAIT_RREADY; 217 | end 218 | else 219 | begin 220 | state_read = START_R; 221 | end 222 | 223 | WAIT_RREADY : if (RREADY == 1'b1) 224 | begin 225 | state_read = START_R; 226 | end 227 | else 228 | begin 229 | state_read = WAIT_RREADY; 230 | end 231 | 232 | endcase 233 | end 234 | end 235 | //----OUTPUTS--FSM--READ---- 236 | always @(state_read or RST) 237 | begin 238 | if (RST == 1'b0) 239 | begin 240 | ARREADY = 0; 241 | RVALID = 0; 242 | RDATA = 32'b0; 243 | end 244 | //----LOGIC---- 245 | else 246 | begin 247 | case (state_read) 248 | START_R :begin 249 | ARREADY = 1; 250 | RVALID = 0; 251 | RDATA = 32'b0; 252 | end 253 | WAIT_RREADY :begin 254 | ARREADY = 1; 255 | RVALID = 1; 256 | RDATA = 32'h55555555; 257 | end 258 | 259 | endcase 260 | end 261 | end 262 | endmodule 263 | 264 | 265 | -------------------------------------------------------------------------------- /mriscv_axi/DAC_interface_AXI/DAC_interface_AXI_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module DAC_interface_AXI_tb; 4 | parameter CLKPERIOD = 10; 5 | 6 | reg CLK = 0, RST; 7 | reg AWVALID, WVALID, BREADY; 8 | reg [31:0] AWADDR, WDATA; 9 | reg [3:0] WSTRB; 10 | reg ARVALID, RREADY; 11 | 12 | wire AWREADY, WREADY, BVALID; 13 | wire [11:0] DATA; 14 | wire ARREADY, RVALID; 15 | wire [31:0] RDATA; 16 | 17 | DAC_interface_AXI DAC_interface_AXI_inst( 18 | .RST(RST), 19 | .CLK(CLK), 20 | .AWVALID(AWVALID), 21 | .WVALID(WVALID), 22 | .BREADY(BREADY), 23 | .AWADDR(AWADDR), 24 | .WDATA(WDATA), 25 | .WSTRB(WSTRB), 26 | .AWREADY(AWREADY), 27 | .WREADY(WREADY), 28 | .BVALID(BVALID), 29 | .DATA(DATA), 30 | .ARVALID(ARVALID), 31 | .RREADY(RREADY), 32 | .ARREADY(ARREADY), 33 | .RVALID(RVALID), 34 | .RDATA(RDATA)); 35 | 36 | always 37 | begin 38 | #(CLKPERIOD/2) CLK = ~CLK; 39 | end 40 | 41 | initial begin 42 | 43 | RST <= 1'b0; 44 | 45 | #(CLKPERIOD*100);//-------------------------START_W--AND--START_R 46 | 47 | /* 48 | RST <= 1'b1; 49 | AWVALID <= 1'b0; 50 | WVALID <= 1'b0; 51 | BREADY <= 1'b0; 52 | AWADDR <= 32'b0; 53 | WDATA <= 32'b0; 54 | ARVALID <= 1'b0; 55 | RREADY <= 1'b0; 56 | 57 | #(CLKPERIOD*5);//------------------------- 58 | 59 | RST <= 1'b1; 60 | AWVALID <= 1'b0; 61 | WVALID <= 1'b0; 62 | BREADY <= 1'b0; 63 | AWADDR <= 32'hfffffff1; 64 | WDATA <= 32'h12345678; 65 | ARVALID <= 1'b0; 66 | RREADY <= 1'b0; 67 | 68 | #(CLKPERIOD*5);//------------------------- 69 | 70 | RST <= 1'bx; 71 | AWVALID <= 1'bx; 72 | WVALID <= 1'bx; 73 | BREADY <= 1'bx; 74 | AWADDR <= 32'bx; 75 | WDATA <= 32'hx; 76 | ARVALID <= 1'bX; 77 | RREADY <= 1'bX; 78 | 79 | #(CLKPERIOD*5);//------------------------- 80 | 81 | RST <= 1'bz; 82 | AWVALID <= 1'bz; 83 | WVALID <= 1'bz; 84 | BREADY <= 1'bz; 85 | AWADDR <= 32'bz; 86 | WDATA <= 32'hz; 87 | ARVALID <= 1'bZ; 88 | RREADY <= 1'bZ; 89 | 90 | #(CLKPERIOD*5);//------------------------- 91 | */ 92 | 93 | RST <= 1'b1; 94 | AWVALID <= 1'b1; 95 | WVALID <= 1'b0; 96 | BREADY <= 1'b0; 97 | AWADDR <= 32'hfffffff1; 98 | WDATA <= 32'h12345678; 99 | ARVALID <= 1'b1; 100 | RREADY <= 1'b0; 101 | 102 | #(CLKPERIOD*20);//-------------------------WAIT_WVALID--AND--WAIT_RREADY 103 | /* 104 | RST <= 1'b1; 105 | AWVALID <= 1'b0; 106 | WVALID <= 1'b0; 107 | BREADY <= 1'b0; 108 | AWADDR <= 32'b0; 109 | WDATA <= 32'b0; 110 | ARVALID <= 1'b0; 111 | RREADY <= 1'b0; 112 | 113 | #(CLKPERIOD*5);//------------------------- 114 | 115 | RST <= 1'b1; 116 | AWVALID <= 1'b0; 117 | WVALID <= 1'b0; 118 | BREADY <= 1'b0; 119 | AWADDR <= 32'hfffffff1; 120 | WDATA <= 32'h12345678; 121 | ARVALID <= 1'b0; 122 | RREADY <= 1'b0; 123 | 124 | 125 | #(CLKPERIOD*5);//------------------------- 126 | 127 | RST <= 1'bX; 128 | AWVALID <= 1'bX; 129 | WVALID <= 1'bX; 130 | BREADY <= 1'bX; 131 | AWADDR <= 32'bX; 132 | WDATA <= 32'bX; 133 | ARVALID <= 1'bX; 134 | RREADY <= 1'bX; 135 | 136 | 137 | #(CLKPERIOD*5);//------------------------- 138 | 139 | RST <= 1'bZ; 140 | AWVALID <= 1'bZ; 141 | WVALID <= 1'bZ; 142 | BREADY <= 1'bZ; 143 | AWADDR <= 32'bZ; 144 | WDATA <= 32'bZ; 145 | ARVALID <= 1'bZ; 146 | RREADY <= 1'bZ; 147 | 148 | #(CLKPERIOD*5);//------------------------- 149 | */ 150 | RST <= 1'b1; 151 | AWVALID <= 1'b0; 152 | WVALID <= 1'b1; 153 | BREADY <= 1'b1; 154 | AWADDR <= 32'hfffffff1; 155 | WDATA <= 32'h55555555; 156 | ARVALID <= 1'b0; 157 | RREADY <= 1'b1; 158 | 159 | #(CLKPERIOD*20);//-------------------------WORKING--AND--START_R 160 | /* 161 | RST <= 1'b1; 162 | AWVALID <= 1'b0; 163 | WVALID <= 1'b0; 164 | BREADY <= 1'b0; 165 | AWADDR <= 32'b0; 166 | WDATA <= 32'b0; 167 | ARVALID <= 1'b0; 168 | RREADY <= 1'b0; 169 | 170 | #(CLKPERIOD*5);//------------------------- 171 | 172 | RST <= 1'b1; 173 | AWVALID <= 1'b0; 174 | WVALID <= 1'b0; 175 | BREADY <= 1'b0; 176 | AWADDR <= 32'hfffffff1; 177 | WDATA <= 32'h12345678; 178 | ARVALID <= 1'b0; 179 | RREADY <= 1'b0; 180 | 181 | #(CLKPERIOD*5);//------------------------- 182 | 183 | RST <= 1'bX; 184 | AWVALID <= 1'bX; 185 | WVALID <= 1'bX; 186 | BREADY <= 1'b0; 187 | AWADDR <= 32'bX; 188 | WDATA <= 32'bX; 189 | ARVALID <= 1'bX; 190 | RREADY <= 1'bX; 191 | 192 | #(CLKPERIOD*5);//------------------------- 193 | 194 | RST <= 1'bZ; 195 | AWVALID <= 1'bZ; 196 | WVALID <= 1'bZ; 197 | BREADY <= 1'bZ; 198 | AWADDR <= 32'bZ; 199 | WDATA <= 32'bZ; 200 | ARVALID <= 1'bZ; 201 | RREADY <= 1'bZ; 202 | 203 | #(CLKPERIOD*5);//------------------------- 204 | 205 | RST <= 1'b1; 206 | AWVALID <= 1'b0; 207 | WVALID <= 1'b0; 208 | BREADY <= 1'b0; 209 | AWADDR <= 32'b0; 210 | WDATA <= 32'b0; 211 | ARVALID <= 1'b0; 212 | RREADY <= 1'b0; 213 | 214 | #(CLKPERIOD*10); 215 | */ 216 | //----------------------------------reset------------------------ 217 | 218 | RST <= 1'b0; 219 | AWVALID <= 1'b0; 220 | WVALID <= 1'b0; 221 | BREADY <= 1'b0; 222 | AWADDR <= 32'h0; 223 | WDATA <= 32'h0; 224 | ARVALID <= 1'b0; 225 | RREADY <= 1'b0; 226 | 227 | #(CLKPERIOD*100);//-------------------------START_R--AND--START_W 228 | /* 229 | RST <= 1'b1; 230 | AWVALID <= 1'b0; 231 | WVALID <= 1'b0; 232 | BREADY <= 1'b0; 233 | AWADDR <= 32'b0; 234 | WDATA <= 32'b0; 235 | ARVALID <= 1'b0; 236 | RREADY <= 1'b0; 237 | 238 | #(CLKPERIOD*5);//------------------------- 239 | 240 | RST <= 1'b1; 241 | AWVALID <= 1'b0; 242 | WVALID <= 1'b0; 243 | BREADY <= 1'b0; 244 | AWADDR <= 32'hfffffff2; 245 | WDATA <= 32'h87654321; 246 | ARVALID <= 1'b0; 247 | RREADY <= 1'b0; 248 | 249 | #(CLKPERIOD*5);//------------------------- 250 | 251 | RST <= 1'bx; 252 | AWVALID <= 1'bx; 253 | WVALID <= 1'bx; 254 | BREADY <= 1'bx; 255 | AWADDR <= 32'bx; 256 | WDATA <= 32'hx; 257 | ARVALID <= 1'bX; 258 | RREADY <= 1'bX; 259 | 260 | #(CLKPERIOD*5);//------------------------- 261 | 262 | RST <= 1'bz; 263 | AWVALID <= 1'bz; 264 | WVALID <= 1'bz; 265 | BREADY <= 1'bz; 266 | AWADDR <= 32'bz; 267 | WDATA <= 32'hz; 268 | ARVALID <= 1'bZ; 269 | RREADY <= 1'bZ; 270 | 271 | #(CLKPERIOD*5);//------------------------- 272 | 273 | RST <= 1'b1; 274 | AWVALID <= 1'b1; 275 | WVALID <= 1'b0; 276 | BREADY <= 1'b0; 277 | AWADDR <= 32'hfffffff2; 278 | WDATA <= 32'h87654321; 279 | ARVALID <= 1'b1; 280 | RREADY <= 1'b0; 281 | 282 | */ 283 | 284 | RST <= 1'b1; 285 | AWVALID <= 1'b1; 286 | WVALID <= 1'b0; 287 | BREADY <= 1'b0; 288 | AWADDR <= 32'hfffffff1; 289 | WDATA <= 32'h44444444; 290 | ARVALID <= 1'b1; 291 | RREADY <= 1'b0; 292 | 293 | 294 | #(CLKPERIOD*20);//-------------------------WAIT_WVALID--AND--WAIT_RREADY 295 | /* 296 | RST <= 1'b1; 297 | AWVALID <= 1'b0; 298 | WVALID <= 1'b0; 299 | BREADY <= 1'b0; 300 | AWADDR <= 32'b0; 301 | WDATA <= 32'b0; 302 | ARVALID <= 1'b0; 303 | RREADY <= 1'b0; 304 | 305 | #(CLKPERIOD*5);//------------------------- 306 | 307 | RST <= 1'b1; 308 | AWVALID <= 1'b0; 309 | WVALID <= 1'b0; 310 | BREADY <= 1'b0; 311 | AWADDR <= 32'hfffffff2; 312 | WDATA <= 32'h87654321; 313 | ARVALID <= 1'b0; 314 | RREADY <= 1'b0; 315 | 316 | 317 | #(CLKPERIOD*5);//------------------------- 318 | 319 | RST <= 1'bX; 320 | AWVALID <= 1'bX; 321 | WVALID <= 1'bX; 322 | BREADY <= 1'bX; 323 | AWADDR <= 32'bX; 324 | WDATA <= 32'bX; 325 | ARVALID <= 1'bX; 326 | RREADY <= 1'bX; 327 | 328 | 329 | #(CLKPERIOD*5);//------------------------- 330 | 331 | RST <= 1'bZ; 332 | AWVALID <= 1'bZ; 333 | WVALID <= 1'bZ; 334 | BREADY <= 1'bZ; 335 | AWADDR <= 32'bZ; 336 | WDATA <= 32'bZ; 337 | ARVALID <= 1'bZ; 338 | RREADY <= 1'bZ; 339 | 340 | #(CLKPERIOD*5);//------------------------- 341 | 342 | RST <= 1'b1; 343 | AWVALID <= 1'b0; 344 | WVALID <= 1'b1; 345 | BREADY <= 1'b1; 346 | AWADDR <= 32'hfffffff2; 347 | WDATA <= 32'h87654321; 348 | ARVALID <= 1'b0; 349 | RREADY <= 1'b1; 350 | */ 351 | RST <= 1'b1; 352 | AWVALID <= 1'b0; 353 | WVALID <= 1'b1; 354 | BREADY <= 1'b1; 355 | AWADDR <= 32'hfffffff1; 356 | WDATA <= 32'h44444444; 357 | ARVALID <= 1'b0; 358 | RREADY <= 1'b1; 359 | 360 | #(CLKPERIOD*20);//-------------------------WORKING--AND--START_R 361 | /* 362 | RST <= 1'b1; 363 | AWVALID <= 1'b0; 364 | WVALID <= 1'b0; 365 | BREADY <= 1'b0; 366 | AWADDR <= 32'b0; 367 | WDATA <= 32'b0; 368 | ARVALID <= 1'b0; 369 | RREADY <= 1'b0; 370 | 371 | #(CLKPERIOD*5);//------------------------- 372 | 373 | RST <= 1'b1; 374 | AWVALID <= 1'b0; 375 | WVALID <= 1'b0; 376 | BREADY <= 1'b0; 377 | AWADDR <= 32'hfffffff2; 378 | WDATA <= 32'h87654321; 379 | ARVALID <= 1'b0; 380 | RREADY <= 1'b0; 381 | 382 | #(CLKPERIOD*5);//------------------------- 383 | 384 | RST <= 1'bX; 385 | AWVALID <= 1'bX; 386 | WVALID <= 1'bX; 387 | BREADY <= 1'b0; 388 | AWADDR <= 32'bX; 389 | WDATA <= 32'bX; 390 | ARVALID <= 1'bX; 391 | RREADY <= 1'bX; 392 | 393 | #(CLKPERIOD*5);//------------------------- 394 | 395 | RST <= 1'bZ; 396 | AWVALID <= 1'bZ; 397 | WVALID <= 1'bZ; 398 | BREADY <= 1'bZ; 399 | AWADDR <= 32'bZ; 400 | WDATA <= 32'bZ; 401 | ARVALID <= 1'bZ; 402 | RREADY <= 1'bZ; 403 | 404 | #(CLKPERIOD*5);//------------------------- 405 | 406 | 407 | RST <= 1'b1; 408 | AWVALID <= 1'b0; 409 | WVALID <= 1'b0; 410 | BREADY <= 1'b0; 411 | AWADDR <= 32'b0; 412 | WDATA <= 32'b0; 413 | ARVALID <= 1'b0; 414 | RREADY <= 1'b1; 415 | 416 | #(CLKPERIOD*10) 417 | */ 418 | RST <= 1'b1; 419 | AWVALID <= 1'b0; 420 | WVALID <= 1'b0; 421 | BREADY <= 1'b0; 422 | AWADDR <= 32'h0; 423 | WDATA <= 32'h0; 424 | ARVALID <= 1'b0; 425 | RREADY <= 1'b1; 426 | 427 | 428 | //-------------------------START_R--AND--START_W 429 | 430 | //----------------------------------NO--reset------------------------ 431 | 432 | //RST <= 1'b0; 433 | 434 | #(CLKPERIOD*100);//-------------------------START_R--AND--START_W 435 | /* 436 | RST <= 1'b1; 437 | AWVALID <= 1'b0; 438 | WVALID <= 1'b0; 439 | BREADY <= 1'b0; 440 | AWADDR <= 32'b0; 441 | WDATA <= 32'b0; 442 | ARVALID <= 1'b0; 443 | RREADY <= 1'b0; 444 | 445 | #(CLKPERIOD*5);//------------------------- 446 | 447 | RST <= 1'b1; 448 | AWVALID <= 1'b0; 449 | WVALID <= 1'b0; 450 | BREADY <= 1'b0; 451 | AWADDR <= 32'hfffffff3; 452 | WDATA <= 32'h55555555; 453 | ARVALID <= 1'b0; 454 | RREADY <= 1'b0; 455 | 456 | #(CLKPERIOD*5);//------------------------- 457 | 458 | RST <= 1'bx; 459 | AWVALID <= 1'bx; 460 | WVALID <= 1'bx; 461 | BREADY <= 1'bx; 462 | AWADDR <= 32'bx; 463 | WDATA <= 32'hx; 464 | ARVALID <= 1'bX; 465 | RREADY <= 1'bX; 466 | 467 | #(CLKPERIOD*5);//------------------------- 468 | 469 | RST <= 1'bz; 470 | AWVALID <= 1'bz; 471 | WVALID <= 1'bz; 472 | BREADY <= 1'bz; 473 | AWADDR <= 32'bz; 474 | WDATA <= 32'hz; 475 | ARVALID <= 1'bZ; 476 | RREADY <= 1'bZ; 477 | 478 | #(CLKPERIOD*5);//------------------------- 479 | 480 | RST <= 1'b1; 481 | AWVALID <= 1'b1; 482 | WVALID <= 1'b0; 483 | BREADY <= 1'b0; 484 | AWADDR <= 32'hfffffff3; 485 | WDATA <= 32'h55555555; 486 | ARVALID <= 1'b1; 487 | RREADY <= 1'b0; 488 | */ 489 | RST <= 1'b1; 490 | AWVALID <= 1'b1; 491 | WVALID <= 1'b0; 492 | BREADY <= 1'b0; 493 | AWADDR <= 32'hfffffff1; 494 | WDATA <= 32'h66666666; 495 | ARVALID <= 1'b1; 496 | RREADY <= 1'b0; 497 | 498 | #(CLKPERIOD*20);//-------------------------WAIT_WVALID--AND--WAIT_RREADY 499 | /* 500 | RST <= 1'b1; 501 | AWVALID <= 1'b0; 502 | WVALID <= 1'b0; 503 | BREADY <= 1'b0; 504 | AWADDR <= 32'b0; 505 | WDATA <= 32'b0; 506 | ARVALID <= 1'b0; 507 | RREADY <= 1'b0; 508 | 509 | #(CLKPERIOD*5);//------------------------- 510 | 511 | RST <= 1'b1; 512 | AWVALID <= 1'b0; 513 | WVALID <= 1'b0; 514 | BREADY <= 1'b0; 515 | AWADDR <= 32'hfffffff3; 516 | WDATA <= 32'h55555555; 517 | ARVALID <= 1'b0; 518 | RREADY <= 1'b0; 519 | 520 | 521 | #(CLKPERIOD*5);//------------------------- 522 | 523 | RST <= 1'bX; 524 | AWVALID <= 1'bX; 525 | WVALID <= 1'bX; 526 | BREADY <= 1'bX; 527 | AWADDR <= 32'bX; 528 | WDATA <= 32'bX; 529 | ARVALID <= 1'bX; 530 | RREADY <= 1'bX; 531 | 532 | 533 | #(CLKPERIOD*5);//------------------------- 534 | 535 | RST <= 1'bZ; 536 | AWVALID <= 1'bZ; 537 | WVALID <= 1'bZ; 538 | BREADY <= 1'bZ; 539 | AWADDR <= 32'bZ; 540 | WDATA <= 32'bZ; 541 | ARVALID <= 1'bZ; 542 | RREADY <= 1'bZ; 543 | 544 | #(CLKPERIOD*5);//------------------------- 545 | 546 | 547 | RST <= 1'b1; 548 | AWVALID <= 1'b0; 549 | WVALID <= 1'b1; 550 | BREADY <= 1'b1; 551 | AWADDR <= 32'hfffffff3; 552 | WDATA <= 32'h55555555; 553 | ARVALID <= 1'b0; 554 | RREADY <= 1'b1; 555 | 556 | */ 557 | 558 | RST <= 1'b1; 559 | AWVALID <= 1'b0; 560 | WVALID <= 1'b1; 561 | BREADY <= 1'b1; 562 | AWADDR <= 32'hfffffff1; 563 | WDATA <= 32'h66666666; 564 | ARVALID <= 1'b0; 565 | RREADY <= 1'b1; 566 | 567 | #(CLKPERIOD*100);//-------------------------WORKING--AND--START_R 568 | /* 569 | RST <= 1'b1; 570 | AWVALID <= 1'b0; 571 | WVALID <= 1'b0; 572 | BREADY <= 1'b0; 573 | AWADDR <= 32'b0; 574 | WDATA <= 32'b0; 575 | ARVALID <= 1'b0; 576 | RREADY <= 1'b0; 577 | 578 | #(CLKPERIOD*5);//------------------------- 579 | 580 | RST <= 1'b1; 581 | AWVALID <= 1'b0; 582 | WVALID <= 1'b0; 583 | BREADY <= 1'b0; 584 | AWADDR <= 32'hfffffff3; 585 | WDATA <= 32'h55555555; 586 | ARVALID <= 1'b0; 587 | RREADY <= 1'b0; 588 | 589 | #(CLKPERIOD*5);//------------------------- 590 | 591 | RST <= 1'bX; 592 | AWVALID <= 1'bX; 593 | WVALID <= 1'bX; 594 | BREADY <= 1'b0; 595 | AWADDR <= 32'bX; 596 | WDATA <= 32'bX; 597 | ARVALID <= 1'bX; 598 | RREADY <= 1'bX; 599 | 600 | #(CLKPERIOD*5);//------------------------- 601 | 602 | RST <= 1'bZ; 603 | AWVALID <= 1'bZ; 604 | WVALID <= 1'bZ; 605 | BREADY <= 1'bZ; 606 | AWADDR <= 32'bZ; 607 | WDATA <= 32'bZ; 608 | ARVALID <= 1'bZ; 609 | RREADY <= 1'bZ; 610 | 611 | #(CLKPERIOD*5);//------------------------- 612 | 613 | RST <= 1'b1; 614 | AWVALID <= 1'b0; 615 | WVALID <= 1'b0; 616 | BREADY <= 1'b0; 617 | AWADDR <= 32'b0; 618 | WDATA <= 32'b0; 619 | ARVALID <= 1'b0; 620 | RREADY <= 1'b0; 621 | 622 | #(CLKPERIOD*10) 623 | 624 | //-------------------------START--AND--WAIT_RREADY 625 | */ 626 | $finish; 627 | 628 | end 629 | endmodule 630 | -------------------------------------------------------------------------------- /mriscv_axi/GPIO/completogpio.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module completogpio( 4 | input [31:0] WAddress,Wdata, 5 | input AWvalid, 6 | input [7:0] pindata, 7 | input [31:0] RAddress, 8 | input Wvalid, 9 | input clock, 10 | input ARvalid, 11 | input reset, 12 | input Rready, 13 | input Bready, 14 | output reg ARready,Rvalid,AWready,Wready,Bvalid, 15 | output reg[7:0] Rx,datanw, 16 | output reg [7:0] Tx,DSE, 17 | output reg [31:0] Rdata 18 | ); 19 | 20 | wire [2:0] LWAddress,LRAddress; 21 | wire [7:0] W,R,Tm,Rm; 22 | wire [4:0] salm; 23 | wire [7:0] outdataw,DS; 24 | reg Rdata1,vel; 25 | 26 | 27 | 28 | 29 | //decodificador para Wend 30 | 31 | 32 | 33 | 34 | // maquina 35 | macstate2 maquina ( 36 | .clock(clock), 37 | .vel(vel), 38 | .reset(reset), 39 | .salida(salm), 40 | .AWvalid(AWvalid), 41 | .Wvalid(Wvalid), 42 | .Bready(Bready), 43 | .ARvalid(ARvalid), 44 | .Rready(Rready) 45 | ); 46 | 47 | 48 | //////////////////////////////////////////////////////////////////////// 49 | 50 | always @ (posedge clock) begin 51 | 52 | if (!reset) begin 53 | vel<=1; 54 | 55 | end 56 | 57 | else if (Wvalid) begin 58 | vel<=Wdata[2]; 59 | end 60 | 61 | else begin 62 | vel<=vel; 63 | end 64 | end 65 | 66 | ///////////////////////////////////// 67 | 68 | 69 | // latch escritura 70 | latchW latchW ( 71 | .clock(clock), 72 | .reset(reset), 73 | .AWvalid(AWvalid), 74 | .WAddres(WAddress), 75 | .LWAddres(LWAddress) 76 | ); 77 | 78 | // latch lectura 79 | latchW latchR ( 80 | .clock(clock), 81 | .reset(reset), 82 | .AWvalid(ARvalid), 83 | .WAddres(RAddress), 84 | .LWAddres(LRAddress) 85 | ); 86 | 87 | // decodificador escritura 88 | decodificador decow ( 89 | .AWready(salm[2]), 90 | .clock(clock), 91 | .LWAddress(LWAddress), 92 | .W(W) 93 | ); 94 | 95 | 96 | ///////////////////////////////////// 97 | // Instantiate the module 98 | flipsdataw flipw1( 99 | .reset(reset), 100 | .en(W[0]), 101 | .clock(clock), 102 | .datain(Wdata[1:0]), 103 | .outdata(outdataw[0]), 104 | .DS(DS[0]) 105 | ); 106 | flipsdataw flipw2 ( 107 | .reset(reset), 108 | .en(W[1]), 109 | .clock(clock), 110 | .datain(Wdata[1:0]), 111 | .outdata(outdataw[1]), 112 | .DS(DS[1]) 113 | ); 114 | flipsdataw flipw3 ( 115 | .reset(reset), 116 | .en(W[2]), 117 | .clock(clock), 118 | .datain(Wdata[1:0]), 119 | .outdata(outdataw[2]), 120 | .DS(DS[2]) 121 | ); 122 | flipsdataw flipw4 ( 123 | .reset(reset), 124 | .en(W[3]), 125 | .clock(clock), 126 | .datain(Wdata[1:0]), 127 | .outdata(outdataw[3]), 128 | .DS(DS[3]) 129 | ); 130 | flipsdataw flipw5 ( 131 | .reset(reset), 132 | .en(W[4]), 133 | .clock(clock), 134 | .datain(Wdata[1:0]), 135 | .outdata(outdataw[4]), 136 | .DS(DS[4]) 137 | ); 138 | 139 | flipsdataw flipw6 ( 140 | .reset(reset), 141 | .en(W[5]), 142 | .clock(clock), 143 | .datain(Wdata[1:0]), 144 | .outdata(outdataw[5]), 145 | .DS(DS[5]) 146 | ); 147 | flipsdataw flipw7 ( 148 | .reset(reset), 149 | .en(W[6]), 150 | .clock(clock), 151 | .datain(Wdata[1:0]), 152 | .outdata(outdataw[6]), 153 | .DS(DS[6]) 154 | ); 155 | flipsdataw flipw8 ( 156 | .reset(reset), 157 | .en(W[7]), 158 | .clock(clock), 159 | .datain(Wdata[1:0]), 160 | .outdata(outdataw[7]), 161 | .DS(DS[7]) 162 | ); 163 | 164 | 165 | 166 | 167 | ///////////////////////////////////// 168 | 169 | // decodificador lectura 170 | decodificador decor ( 171 | .AWready(salm[4]), 172 | .clock(clock), 173 | .LWAddress(LRAddress), 174 | .W(R) 175 | ); 176 | 177 | ///////////////////////////////////////////////////////////////// 178 | ///////////FLIP FLOPS////////////////////////////////// 179 | 180 | // flip1 181 | flipflopRS flip1 ( 182 | .reset(reset), 183 | .Tx(Tm[0]), 184 | .Rx(Rm[0]), 185 | .W1(W[0]), 186 | .R1(R[0]), 187 | .clock(clock) 188 | ); 189 | 190 | // flip2 191 | flipflopRS flip2 ( 192 | .reset(reset), 193 | .Tx(Tm[1]), 194 | .Rx(Rm[1]), 195 | .W1(W[1]), 196 | .R1(R[1]), 197 | .clock(clock) 198 | ); 199 | 200 | // flip3 201 | flipflopRS flip3 ( 202 | .reset(reset), 203 | .Tx(Tm[2]), 204 | .Rx(Rm[2]), 205 | .W1(W[2]), 206 | .R1(R[2]), 207 | .clock(clock) 208 | ); 209 | 210 | // flip4 211 | flipflopRS flip4 ( 212 | .reset(reset), 213 | .Tx(Tm[3]), 214 | .Rx(Rm[3]), 215 | .W1(W[3]), 216 | .R1(R[3]), 217 | .clock(clock) 218 | ); 219 | 220 | // flip5 221 | flipflopRS flip5 ( 222 | .reset(reset), 223 | .Tx(Tm[4]), 224 | .Rx(Rm[4]), 225 | .W1(W[4]), 226 | .R1(R[4]), 227 | .clock(clock) 228 | ); 229 | 230 | // flip6 231 | flipflopRS flip6 ( 232 | .reset(reset), 233 | .Tx(Tm[5]), 234 | .Rx(Rm[5]), 235 | .W1(W[5]), 236 | .R1(R[5]), 237 | .clock(clock) 238 | ); 239 | 240 | // flip7 241 | flipflopRS flip7 ( 242 | .reset(reset), 243 | .Tx(Tm[6]), 244 | .Rx(Rm[6]), 245 | .W1(W[6]), 246 | .R1(R[6]), 247 | .clock(clock) 248 | ); 249 | 250 | // flip8 251 | flipflopRS flip8 ( 252 | .reset(reset), 253 | .Tx(Tm[7]), 254 | .Rx(Rm[7]), 255 | .W1(W[7]), 256 | .R1(R[7]), 257 | .clock(clock) 258 | ); 259 | 260 | /* always @(P , reset) begin 261 | if (!reset) begin 262 | Rx=0; 263 | Tx=0; 264 | end 265 | else begin 266 | Rx=~P; 267 | Tx=P; 268 | end 269 | end 270 | */ 271 | 272 | always @(LRAddress or pindata) begin 273 | case (LRAddress) 274 | 3'b000: Rdata1 =pindata[0]; 275 | 3'b001: Rdata1 =pindata[1]; 276 | 3'b010: Rdata1 =pindata[2]; 277 | 3'b011: Rdata1 =pindata[3]; 278 | 3'b100: Rdata1 =pindata[4]; 279 | 3'b101: Rdata1 =pindata[5]; 280 | 3'b110: Rdata1 =pindata[6]; 281 | 3'b111: Rdata1 =pindata[7]; 282 | endcase 283 | end 284 | 285 | 286 | 287 | 288 | always @(posedge clock) 289 | if (!reset) begin 290 | Rdata[0] <= 1'b0; 291 | end else begin 292 | Rdata[0] <= Rdata1; 293 | end 294 | 295 | 296 | 297 | always@* begin 298 | DSE=DS; 299 | Rdata[31:1]=0; 300 | Tx=Tm; 301 | Rx=Rm; 302 | Bvalid=salm[0]; 303 | Wready=salm[1]; 304 | AWready=salm[2]; 305 | Rvalid=salm[3]; 306 | ARready=salm[4]; 307 | datanw=outdataw; 308 | //Rend=1'b1; 309 | //Wend=1'b1; 310 | end 311 | endmodule 312 | 313 | -------------------------------------------------------------------------------- /mriscv_axi/GPIO/completogpio_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | 5 | module completogpio_tb; 6 | 7 | // Inputs 8 | reg [31:0] WAddress; 9 | reg [31:0] Wdata; 10 | reg AWvalid; 11 | reg [7:0] pindata; 12 | reg [31:0] RAddress; 13 | reg Wvalid; 14 | reg clock; 15 | reg ARvalid; 16 | reg reset; 17 | reg Rready; 18 | reg Bready; 19 | reg [3:0 ]strobe; 20 | 21 | // Outputs 22 | wire [7:0] DSE; 23 | wire ARready; 24 | wire Rvalid; 25 | wire AWready; 26 | wire Wready; 27 | wire Bvalid; 28 | wire [7:0] Rx; 29 | wire [7:0] datanw; 30 | wire [7:0] Tx; 31 | wire [31:0] Rdata; 32 | 33 | // Instantiate the Unit Under Test (UUT) 34 | completogpio uut ( 35 | .WAddress(WAddress), 36 | .Wdata(Wdata), 37 | .AWvalid(AWvalid), 38 | .pindata(pindata), 39 | .RAddress(RAddress), 40 | .Wvalid(Wvalid), 41 | .clock(clock), 42 | .ARvalid(ARvalid), 43 | .reset(reset), 44 | .Rready(Rready), 45 | .Bready(Bready), 46 | .DSE(DSE), 47 | .ARready(ARready), 48 | .Rvalid(Rvalid), 49 | .AWready(AWready), 50 | .Wready(Wready), 51 | .Bvalid(Bvalid), 52 | .Rx(Rx), 53 | .datanw(datanw), 54 | .Tx(Tx), 55 | .Rdata(Rdata) 56 | ); 57 | 58 | always #1 clock=~clock; 59 | initial begin 60 | // Initialize Inputs 61 | WAddress = 0; 62 | Wdata = 0; 63 | AWvalid = 0; 64 | pindata = 8'd0; 65 | RAddress = 0; 66 | Wvalid = 0; 67 | clock = 0; 68 | ARvalid = 0; 69 | reset = 0; 70 | Rready = 0; 71 | Bready = 0; 72 | 73 | 74 | // escritura 75 | #2; 76 | reset=1; 77 | Rready=0; 78 | WAddress=32'hEFA; 79 | Wdata=32'hABCDEFFF; 80 | pindata = 8'b10101010; 81 | RAddress=32'd88393348; 82 | AWvalid=1; 83 | #1; 84 | Wvalid=1; 85 | #2.5; 86 | Wvalid=0; 87 | #2.5; 88 | AWvalid=0; 89 | Bready=1; 90 | 91 | #2.5; 92 | reset=0; 93 | Bready=0; 94 | // lectura 95 | 96 | #10; 97 | reset=1; 98 | 99 | ARvalid=1; 100 | #2.5; 101 | Rready=1; 102 | ARvalid=0; 103 | #2.0; 104 | Rready=0; 105 | 106 | 107 | 108 | #4; 109 | reset=0; 110 | // escritura 111 | #10; 112 | reset=1; 113 | Rready=0; 114 | WAddress=32'hEFA6; 115 | Wdata=32'hABCDEFF1; 116 | pindata = 8'b10101010; 117 | RAddress=32'd88393348; 118 | AWvalid=1; 119 | #1; 120 | Wvalid=1; 121 | #8; 122 | Wvalid=0; 123 | #9; 124 | AWvalid=0; 125 | Bready=1; 126 | 127 | #9; 128 | reset=0; 129 | Bready=0; 130 | 131 | // lectura 132 | 133 | #10; 134 | reset=1; 135 | ARvalid=1; 136 | #6; 137 | Rready=1; 138 | ARvalid=0; 139 | 140 | #4; 141 | reset=0; 142 | Rready=0; 143 | #2; 144 | reset=1; 145 | $finish; 146 | /* // escritura 147 | #100; 148 | reset=1; 149 | Rready=0; 150 | WAddress=32'hEFA; 151 | Wdata=32'hABCDEFFF; 152 | pindata = 8'b10101010; 153 | RAddress=32'd88393348; 154 | AWvalid=1; 155 | #10; 156 | Wvalid=1; 157 | #25; 158 | Wvalid=0; 159 | #25; 160 | AWvalid=0; 161 | Bready=1; 162 | 163 | #25; 164 | reset=0; 165 | // lectura 166 | 167 | #100; 168 | reset=1; 169 | Bready=0; 170 | ARvalid=1; 171 | #25; 172 | Rready=1; 173 | ARvalid=0; 174 | 175 | 176 | 177 | 178 | #20; 179 | reset=0; 180 | Rready=0;*/ 181 | /*// escritura 182 | #100; 183 | reset=1; 184 | Rready=0; 185 | WAddress=32'hEFA6; 186 | Wdata=32'hABCDEFF1; 187 | pindata = 8'b10101010; 188 | RAddress=32'd88393348; 189 | AWvalid=1; 190 | #10; 191 | Wvalid=1; 192 | #80; 193 | Wvalid=0; 194 | #90; 195 | AWvalid=0; 196 | Bready=1; 197 | 198 | #90; 199 | reset=0; 200 | 201 | // lectura 202 | 203 | #100; 204 | reset=1; 205 | Bready=0; 206 | ARvalid=1; 207 | #60; 208 | Rready=1; 209 | ARvalid=0; 210 | 211 | #60; 212 | reset=0; 213 | Rready=0;*/ 214 | 215 | // Add stimulus here 216 | 217 | end 218 | 219 | endmodule 220 | 221 | -------------------------------------------------------------------------------- /mriscv_axi/GPIO/decodificador.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module decodificador( 4 | input AWready, 5 | input clock, 6 | input [2:0] LWAddress, 7 | output [7:0] W 8 | ); 9 | 10 | 11 | assign W = AWready? (1 << LWAddress) : 0; 12 | /*always @(posedge clock) 13 | if (!AWready) 14 | W <= 8'h00; 15 | else 16 | case (LWAddress) 17 | 3'b000 : W <= 8'b00000001; 18 | 3'b001 : W <= 8'b00000010; 19 | 3'b010 : W <= 8'b00000100; 20 | 3'b011 : W <= 8'b00001000; 21 | 3'b100 : W <= 8'b00010000; 22 | 3'b101 : W <= 8'b00100000; 23 | 3'b110 : W <= 8'b01000000; 24 | default : W <= 8'b10000000; 25 | 26 | endcase*/ 27 | 28 | 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /mriscv_axi/GPIO/flipflopRS.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module flipflopRS( 4 | 5 | output reg Rx,Tx, 6 | input W1,reset, 7 | input R1, 8 | input clock 9 | ); 10 | 11 | reg D; 12 | always @(posedge clock) 13 | if (!reset) begin 14 | Rx<=1'b0; 15 | Tx<=1'b1; 16 | 17 | end 18 | else if (R1 && !W1) begin 19 | Tx <= 1'b1; 20 | Rx<=1'b1; 21 | 22 | end else if (W1 && !R1) begin 23 | Tx<= 1'b0; 24 | Rx<=1'b0; 25 | 26 | 27 | end 28 | else begin 29 | Tx<=Tx; 30 | Rx<=Rx; 31 | 32 | end 33 | 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /mriscv_axi/GPIO/flipsdataw.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module flipsdataw( 4 | input en,clock,reset, 5 | input [1:0] datain, 6 | output reg outdata, 7 | output reg DS 8 | ); 9 | 10 | //reg es1,es2; 11 | always @ (posedge clock) begin 12 | 13 | if (!reset) begin 14 | DS<=0; 15 | outdata<=0; 16 | //es1<=0; 17 | //es2<=0; 18 | end 19 | 20 | 21 | else if (en) begin 22 | outdata<=datain[0]; 23 | DS<=datain[1]; 24 | //es1<=datain[0]; 25 | //es2<=datain[1]; 26 | 27 | end 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /mriscv_axi/GPIO/latchW.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ///////////////////////////////////////////////////////////////////////////////// 3 | module latchW( 4 | input clock, 5 | input reset, 6 | input AWvalid, 7 | input [31:0] WAddres, 8 | output reg [2:0] LWAddres 9 | ); 10 | 11 | always @ ( posedge clock ) 12 | if (!reset) begin 13 | LWAddres=3'b0; 14 | end else if (AWvalid) begin 15 | LWAddres=WAddres[2:0]; 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /mriscv_axi/GPIO/macstate2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | module macstate2( 5 | input clock, 6 | input reset, 7 | output reg [4:0] salida, 8 | input AWvalid, 9 | input Wvalid,Bready, 10 | input ARvalid,Rready, 11 | input vel 12 | ); 13 | 14 | reg [3:0] state,nexstate; 15 | parameter reposo = 4'd0000; 16 | parameter lectura = 4'b0001; 17 | parameter waitR = 4'b0010; 18 | parameter escritura = 4'b0011; 19 | parameter waitW = 4'b0100; 20 | parameter delay1 = 4'b0101; 21 | parameter delay2=4'b0110; 22 | parameter delay3=4'b0111; 23 | parameter delay4=4'b1000; 24 | parameter delay5=4'b1001; 25 | parameter delay6=4'b1010; 26 | parameter delay7=4'b1011; 27 | //asignacion estado siguiente 28 | 29 | always @(state,ARvalid,AWvalid,Wvalid,Bready,Rready,vel) begin 30 | case (state) 31 | reposo : begin 32 | if (ARvalid) begin 33 | nexstate = lectura; 34 | end 35 | else if (AWvalid) begin 36 | nexstate = waitW; 37 | end 38 | else begin 39 | nexstate = reposo; 40 | end 41 | end 42 | 43 | lectura : begin 44 | if(!vel) begin 45 | nexstate = delay4; 46 | end 47 | else begin 48 | nexstate=delay7; 49 | end 50 | 51 | end 52 | 53 | delay4 : begin 54 | nexstate=delay5; 55 | end 56 | 57 | delay5 : begin 58 | nexstate=delay6; 59 | end 60 | 61 | delay6: begin 62 | nexstate=delay7; 63 | end 64 | 65 | delay7: begin 66 | if (Rready) begin 67 | nexstate=reposo; 68 | end 69 | else begin 70 | nexstate=delay7; 71 | end 72 | end 73 | 74 | waitW : begin 75 | if (Wvalid) begin 76 | nexstate = escritura; 77 | end 78 | else begin 79 | nexstate = waitW; 80 | end 81 | end 82 | 83 | escritura : begin 84 | if (!vel) begin 85 | nexstate=delay1; 86 | end 87 | else begin 88 | nexstate=delay3; 89 | end 90 | end 91 | 92 | 93 | delay1 : begin 94 | nexstate=delay2; 95 | end 96 | 97 | delay2: begin 98 | nexstate=delay3; 99 | end 100 | 101 | delay3: begin 102 | if (Bready) begin 103 | nexstate=reposo; 104 | end 105 | else begin 106 | nexstate=delay3; 107 | end 108 | end 109 | 110 | default : begin // Fault Recovery 111 | nexstate = reposo; 112 | end 113 | endcase 114 | end 115 | 116 | // asignacion sincrona 117 | always @(posedge clock) 118 | if(reset == 0) state <= 3'b0; 119 | else state <= nexstate; 120 | 121 | // asignacion salidas 122 | 123 | always @(state) begin 124 | if (state==4'b0) 125 | salida=5'b00000; 126 | else if(state==4'b1) 127 | salida=5'b10000; 128 | else if (state==4'b010) 129 | salida=5'b11000; 130 | else if (state==4'b011) 131 | salida=5'b00110; 132 | else if (state==4'b100) 133 | salida=5'b00100; 134 | else if (state==4'b101) 135 | salida=5'b00110; 136 | else if (state==4'b110) 137 | salida=5'b00110; 138 | else if (state==4'b111) 139 | salida=5'b00111; 140 | else if (state==4'b1000) 141 | salida=5'b10000; 142 | else if (state==4'b1001) 143 | salida=5'b10000; 144 | else if (state==4'b1010) 145 | salida=5'b10000; 146 | else if (state==4'b1011) 147 | salida=5'b11000; 148 | else 149 | salida=5'b0; 150 | 151 | 152 | end 153 | 154 | 155 | 156 | 157 | 158 | endmodule 159 | -------------------------------------------------------------------------------- /mriscv_axi/PeripheralRISCV.pptx.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/mriscv_axi/PeripheralRISCV.pptx.pdf -------------------------------------------------------------------------------- /mriscv_axi/README.md: -------------------------------------------------------------------------------- 1 | This is mRISC-V, AXI-version 2 | 3 | NOTES: 4 | Missing ADC, DAC and GPIO interfaces. 5 | Cannot include the SP32B1024 (aka RAM) because disclaimer an alternate version using register will be included. 6 | Generated versions of rc or encounter will not be included, just code. 7 | 8 | TODO: 9 | Create makefiles, because shell scripts are garbage. 10 | -------------------------------------------------------------------------------- /mriscv_axi/Yopuzzlemriscv.pptx.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/onchipuis/mriscv/62c09e4e21058ad5315865df84b57baaabdefb58/mriscv_axi/Yopuzzlemriscv.pptx.pdf -------------------------------------------------------------------------------- /mriscv_axi/axi4_interconnect/axi4_interconnect_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module axi4_interconnect_tb(); 4 | 5 | // HELPER 6 | function integer clogb2; 7 | input integer value; 8 | integer i; 9 | begin 10 | clogb2 = 0; 11 | for(i = 0; 2**i < value; i = i + 1) 12 | clogb2 = i + 1; 13 | end 14 | endfunction 15 | 16 | localparam masters = 2; 17 | localparam slaves = 5; 18 | localparam sword = 32; 19 | 20 | localparam impl = 0; 21 | localparam addressing = 0; 22 | 23 | // MEMORY MAP SPEC 24 | localparam [slaves*sword-1:0] addr_mask = {32'h00000000,32'h0000000F,32'h00000001,32'h00000001,32'h000003FF}; 25 | localparam [slaves*sword-1:0] addr_use = {32'h04000000,32'h00000410,32'h00000408,32'h00000400,32'h00000000}; 26 | 27 | // Autogen localparams 28 | 29 | reg CLK = 1'b0; 30 | reg RST; 31 | 32 | // AXI4-lite master memory interfaces 33 | 34 | reg [masters-1:0] m_axi_awvalid; 35 | wire [masters-1:0] m_axi_awready; 36 | wire [masters*sword-1:0] m_axi_awaddr; 37 | wire [masters*3-1:0] m_axi_awprot; 38 | 39 | reg [masters-1:0] m_axi_wvalid; 40 | wire [masters-1:0] m_axi_wready; 41 | wire [masters*sword-1:0] m_axi_wdata; 42 | wire [masters*4-1:0] m_axi_wstrb; 43 | 44 | wire [masters-1:0] m_axi_bvalid; 45 | reg [masters-1:0] m_axi_bready; 46 | 47 | reg [masters-1:0] m_axi_arvalid; 48 | wire [masters-1:0] m_axi_arready; 49 | wire [masters*sword-1:0] m_axi_araddr; 50 | wire [masters*3-1:0] m_axi_arprot; 51 | 52 | wire [masters-1:0] m_axi_rvalid; 53 | reg [masters-1:0] m_axi_rready; 54 | wire [masters*sword-1:0] m_axi_rdata; 55 | 56 | // AXI4-lite slave memory interfaces 57 | 58 | wire [slaves-1:0] s_axi_awvalid; 59 | reg [slaves-1:0] s_axi_awready; 60 | wire [slaves*sword-1:0] s_axi_awaddr; 61 | wire [slaves*3-1:0] s_axi_awprot; 62 | 63 | wire [slaves-1:0] s_axi_wvalid; 64 | reg [slaves-1:0] s_axi_wready; 65 | wire [slaves*sword-1:0] s_axi_wdata; 66 | wire [slaves*4-1:0] s_axi_wstrb; 67 | 68 | reg [slaves-1:0] s_axi_bvalid; 69 | wire [slaves-1:0] s_axi_bready; 70 | 71 | wire [slaves-1:0] s_axi_arvalid; 72 | reg [slaves-1:0] s_axi_arready; 73 | wire [slaves*sword-1:0] s_axi_araddr; 74 | wire [slaves*3-1:0] s_axi_arprot; 75 | 76 | reg [slaves-1:0] s_axi_rvalid; 77 | wire [slaves-1:0] s_axi_rready; 78 | wire [slaves*sword-1:0] s_axi_rdata; 79 | 80 | // THE CONCENTRATION 81 | 82 | reg [sword-1:0] m_axi_awaddr_o [0:masters-1]; 83 | reg [3-1:0] m_axi_awprot_o [0:masters-1]; 84 | reg [sword-1:0] m_axi_wdata_o [0:masters-1]; 85 | reg [4-1:0] m_axi_wstrb_o [0:masters-1]; 86 | reg [sword-1:0] m_axi_araddr_o [0:masters-1]; 87 | reg [3-1:0] m_axi_arprot_o [0:masters-1]; 88 | wire [sword-1:0] m_axi_rdata_o [0:masters-1]; 89 | wire [sword-1:0] s_axi_awaddr_o [0:slaves-1]; 90 | wire [3-1:0] s_axi_awprot_o [0:slaves-1]; 91 | wire [sword-1:0] s_axi_wdata_o [0:slaves-1]; 92 | wire [4-1:0] s_axi_wstrb_o [0:slaves-1]; 93 | wire [sword-1:0] s_axi_araddr_o [0:slaves-1]; 94 | wire [3-1:0] s_axi_arprot_o [0:slaves-1]; 95 | reg [sword-1:0] s_axi_rdata_o [0:slaves-1]; 96 | 97 | wire [sword-1:0] addr_mask_o [0:slaves-1]; 98 | wire [sword-1:0] addr_use_o [0:slaves-1]; 99 | genvar k; 100 | generate 101 | for(k = 0; k < masters; k=k+1) begin 102 | assign m_axi_awaddr[(k+1)*sword-1:k*sword] = m_axi_awaddr_o[k]; 103 | assign m_axi_awprot[(k+1)*3-1:k*3] = m_axi_awprot_o[k]; 104 | assign m_axi_wdata[(k+1)*sword-1:k*sword] = m_axi_wdata_o[k]; 105 | assign m_axi_wstrb[(k+1)*4-1:k*4] = m_axi_wstrb_o[k]; 106 | assign m_axi_araddr[(k+1)*sword-1:k*sword] = m_axi_araddr_o[k]; 107 | assign m_axi_arprot[(k+1)*3-1:k*3] = m_axi_arprot_o[k]; 108 | assign m_axi_rdata_o[k] = m_axi_rdata[(k+1)*sword-1:k*sword]; 109 | end 110 | for(k = 0; k < slaves; k=k+1) begin 111 | assign s_axi_awaddr_o[k] = s_axi_awaddr[(k+1)*sword-1:k*sword]; 112 | assign s_axi_awprot_o[k] = s_axi_awprot[(k+1)*3-1:k*3]; 113 | assign s_axi_wdata_o[k] = s_axi_wdata[(k+1)*sword-1:k*sword]; 114 | assign s_axi_wstrb_o[k] = s_axi_wstrb[(k+1)*4-1:k*4]; 115 | assign s_axi_araddr_o[k] = s_axi_araddr[(k+1)*sword-1:k*sword]; 116 | assign s_axi_arprot_o[k] = s_axi_arprot[(k+1)*3-1:k*3]; 117 | assign addr_mask_o[k] = addr_mask[(k+1)*sword-1:k*sword]; 118 | assign addr_use_o[k] = addr_use[(k+1)*sword-1:k*sword]; 119 | assign s_axi_rdata[(k+1)*sword-1:k*sword] = s_axi_rdata_o[k]; 120 | end 121 | endgenerate 122 | 123 | integer fd1, tmp1, ifstop; 124 | integer PERIOD = 20 ; 125 | integer i, j, error, l; 126 | 127 | 128 | axi4_interconnect/* # 129 | ( 130 | .masters(masters), 131 | .slaves(slaves), 132 | .sword(sword), 133 | .impl(impl), 134 | .addressing(addressing), 135 | .addr_mask(addr_mask), 136 | .addr_use(addr_use) 137 | ) */ 138 | inst_axi4_interconnect 139 | ( 140 | .CLK (CLK), 141 | .RST (RST), 142 | .m_axi_awvalid(m_axi_awvalid), 143 | .m_axi_awready(m_axi_awready), 144 | .m_axi_awaddr(m_axi_awaddr), 145 | .m_axi_awprot(m_axi_awprot), 146 | .m_axi_wvalid(m_axi_wvalid), 147 | .m_axi_wready(m_axi_wready), 148 | .m_axi_wdata(m_axi_wdata), 149 | .m_axi_wstrb(m_axi_wstrb), 150 | .m_axi_bvalid(m_axi_bvalid), 151 | .m_axi_bready(m_axi_bready), 152 | .m_axi_arvalid(m_axi_arvalid), 153 | .m_axi_arready(m_axi_arready), 154 | .m_axi_araddr(m_axi_araddr), 155 | .m_axi_arprot(m_axi_arprot), 156 | .m_axi_rvalid(m_axi_rvalid), 157 | .m_axi_rready(m_axi_rready), 158 | .m_axi_rdata(m_axi_rdata), 159 | .s_axi_awvalid(s_axi_awvalid), 160 | .s_axi_awready(s_axi_awready), 161 | .s_axi_awaddr(s_axi_awaddr), 162 | .s_axi_awprot(s_axi_awprot), 163 | .s_axi_wvalid(s_axi_wvalid), 164 | .s_axi_wready(s_axi_wready), 165 | .s_axi_wdata(s_axi_wdata), 166 | .s_axi_wstrb(s_axi_wstrb), 167 | .s_axi_bvalid(s_axi_bvalid), 168 | .s_axi_bready(s_axi_bready), 169 | .s_axi_arvalid(s_axi_arvalid), 170 | .s_axi_arready(s_axi_arready), 171 | .s_axi_araddr(s_axi_araddr), 172 | .s_axi_arprot(s_axi_arprot), 173 | .s_axi_rvalid(s_axi_rvalid), 174 | .s_axi_rready(s_axi_rready), 175 | .s_axi_rdata(s_axi_rdata) 176 | ); 177 | 178 | always 179 | begin #(PERIOD/2) CLK = ~CLK; end 180 | 181 | task aexpect; 182 | input [sword-1:0] av, e; 183 | begin 184 | if (av == e) 185 | $display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. MATCH!", av, e); 186 | else 187 | begin 188 | $display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. ERROR!", av, e); 189 | error = error + 1; 190 | end 191 | end 192 | endtask 193 | 194 | reg [63:0] xorshift64_state = 64'd88172645463325252; 195 | 196 | task xorshift64_next; 197 | begin 198 | // see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14). 199 | xorshift64_state = xorshift64_state ^ (xorshift64_state << 13); 200 | xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7); 201 | xorshift64_state = xorshift64_state ^ (xorshift64_state << 17); 202 | end 203 | endtask 204 | 205 | 206 | initial begin 207 | $sdf_annotate("axi4_interconnect.sdf",inst_axi4_interconnect); 208 | fd1 = $fopen ("data.txt","r"); 209 | CLK = 1'b1; 210 | RST = 1'b0; 211 | error = 0; 212 | m_axi_awvalid = {(masters){1'b0}}; 213 | m_axi_wvalid = {(masters){1'b0}}; 214 | m_axi_bready = {(masters){1'b0}}; 215 | m_axi_arvalid = {(masters){1'b0}}; 216 | m_axi_rready = {(masters){1'b0}}; 217 | s_axi_awready = {(slaves){1'b0}}; 218 | s_axi_wready = {(slaves){1'b0}}; 219 | s_axi_bvalid = {(slaves){1'b0}}; 220 | s_axi_arready = {(slaves){1'b0}}; 221 | s_axi_rvalid = {(slaves){1'b0}}; 222 | for(i = 0; i < masters; i=i+1) begin 223 | m_axi_awaddr_o[i] = {sword{1'b0}}; 224 | m_axi_awprot_o[i] = {3{1'b0}}; 225 | m_axi_wdata_o[i] = {sword{1'b0}}; 226 | m_axi_wstrb_o[i] = {4{1'b0}}; 227 | m_axi_araddr_o[i] = {sword{1'b0}}; 228 | m_axi_arprot_o[i] = {3{1'b0}}; 229 | end 230 | for(i = 0; i < slaves; i=i+1) begin 231 | s_axi_rdata_o[i] = {sword{1'b0}}; 232 | end 233 | #20 ; 234 | RST = 1'b1; 235 | // READING TEST 236 | for(i = 0; i < masters; i = i+1) begin 237 | for(j = 0; j < slaves; j = j+1) begin 238 | #(PERIOD*8); 239 | m_axi_arvalid[i] = 1'b1; 240 | m_axi_araddr_o[i] = addr_use_o[j] | (xorshift64_state[31:0] & addr_mask_o[j]); 241 | #PERIOD; 242 | while(!m_axi_arready[i]) begin 243 | #PERIOD; 244 | end 245 | while(!m_axi_rvalid[i]) begin 246 | #PERIOD; 247 | end 248 | m_axi_rready[i] = 1'b1; 249 | $display ("Master: %d, Task: RData", i); 250 | aexpect(m_axi_rdata_o[i], xorshift64_state[63:32]); 251 | #PERIOD; 252 | m_axi_arvalid[i] = 1'b0; 253 | m_axi_rready[i] = 1'b0; 254 | xorshift64_next; 255 | if(j == 2) begin 256 | #(PERIOD*6); 257 | RST = 1'b0; 258 | #(PERIOD*6); 259 | RST = 1'b1; 260 | #(PERIOD*6); 261 | end 262 | end 263 | end 264 | 265 | // WRITTING TEST 266 | for(i = 0; i < masters; i = i+1) begin 267 | for(j = 0; j < slaves; j = j+1) begin 268 | #(PERIOD*8); 269 | m_axi_awvalid[i] = 1'b1; 270 | m_axi_awaddr_o[i] = addr_use_o[j] | (xorshift64_state[31:0] & addr_mask_o[j]); 271 | #PERIOD; 272 | while(!m_axi_awready[i]) begin 273 | #PERIOD; 274 | end 275 | m_axi_wvalid[i] = 1'b1; 276 | m_axi_wdata_o[i] = xorshift64_state[63:32]; 277 | while(!m_axi_wready[i]) begin 278 | #PERIOD; 279 | end 280 | while(!m_axi_bvalid[i]) begin 281 | #PERIOD; 282 | end 283 | m_axi_bready[i] = 1'b1; 284 | #PERIOD; 285 | m_axi_awvalid[i] = 1'b0; 286 | m_axi_wvalid[i] = 1'b0; 287 | m_axi_bready[i] = 1'b0; 288 | xorshift64_next; 289 | if(j == 2) begin 290 | #(PERIOD*6); 291 | RST = 1'b0; 292 | #(PERIOD*6); 293 | RST = 1'b1; 294 | #(PERIOD*6); 295 | end 296 | end 297 | end 298 | $timeformat(-9,0,"ns",7); 299 | #(PERIOD*8) if (error == 0) 300 | $display("All match"); 301 | else 302 | $display("Mismatches = %d", error); 303 | $finish; 304 | end 305 | 306 | always @(posedge CLK) begin 307 | for(l = 0; l < slaves; l = l+1) begin 308 | if(s_axi_arvalid[l] && !s_axi_arready[i] && !s_axi_rready[l]) begin 309 | s_axi_arready[l] = 1'b1; 310 | s_axi_rvalid[l] = 1'b1; 311 | s_axi_rdata_o[l] = xorshift64_state[63:32]; 312 | $display ("Slave: %d, Task: RAddr", l); 313 | aexpect(s_axi_araddr_o[l], addr_use_o[l] | (xorshift64_state[31:0] & addr_mask_o[l])); 314 | end else if(s_axi_rready[l]) begin 315 | s_axi_arready[l] = 1'b0; 316 | s_axi_rvalid[l] = 1'b0; 317 | end 318 | 319 | 320 | if(s_axi_awvalid[l] && !s_axi_awready[i] && !s_axi_bready[l]) begin 321 | s_axi_awready[l] = 1'b1; 322 | $display ("Slave: %d, Task: WAddr", l); 323 | aexpect(s_axi_awaddr_o[l], addr_use_o[l] | (xorshift64_state[31:0] & addr_mask_o[l])); 324 | end if(s_axi_wvalid[l] && !s_axi_wready[i] && !s_axi_bready[l]) begin 325 | s_axi_wready[l] = 1'b1; 326 | s_axi_bvalid[l] = 1'b1; 327 | $display ("Slave: %d, Task: WData", l); 328 | aexpect(s_axi_wdata_o[l], xorshift64_state[63:32]); 329 | end else if(s_axi_bready[l]) begin 330 | s_axi_awready[l] = 1'b0; 331 | s_axi_wready[l] = 1'b0; 332 | s_axi_bvalid[l] = 1'b0; 333 | end 334 | end 335 | end 336 | 337 | endmodule 338 | -------------------------------------------------------------------------------- /mriscv_axi/spi_axi_master/spi_axi_master.v: -------------------------------------------------------------------------------- 1 | // Created by: CKDUR 2 | `timescale 1ns/1ns 3 | 4 | module spi_axi_master # 5 | ( 6 | parameter sword = 32, 7 | 8 | /* 9 | IMPLEMENTATION SETTINGS 10 | impl: 0,Classic 1,Simulation 11 | syncing: 0,ByCounterAndDecoder 1,ByMirrorShiftRegister 12 | */ 13 | parameter impl = 0, 14 | parameter syncing = 0 15 | ) 16 | 17 | ( 18 | // SPI INTERFACE 19 | input CEB, 20 | input SCLK, 21 | input DATA, 22 | output DOUT, 23 | // MISC 24 | input RST, 25 | output PICORV_RST, 26 | // AXI4-lite master memory interface 27 | 28 | input CLK, 29 | output reg axi_awvalid, 30 | input axi_awready, 31 | output [sword-1:0] axi_awaddr, 32 | output [3-1:0] axi_awprot, 33 | 34 | output reg axi_wvalid, 35 | input axi_wready, 36 | output [sword-1:0] axi_wdata, 37 | output [4-1:0] axi_wstrb, 38 | 39 | input axi_bvalid, 40 | output reg axi_bready, 41 | 42 | output reg axi_arvalid, 43 | input axi_arready, 44 | output [sword-1:0] axi_araddr, 45 | output [3-1:0] axi_arprot, 46 | 47 | input axi_rvalid, 48 | output reg axi_rready, 49 | input [sword-1:0] axi_rdata 50 | ); 51 | 52 | // HELPER 53 | function integer clogb2; 54 | input integer value; 55 | integer i; 56 | begin 57 | clogb2 = 0; 58 | for(i = 0; 2**i < value; i = i + 1) 59 | clogb2 = i + 1; 60 | end 61 | endfunction 62 | 63 | localparam numbit_instr = 2; // Nop (00), Read(01), Write(10) 64 | localparam numbit_address = sword; 65 | localparam numbit_handshake = numbit_instr+numbit_address+sword; 66 | localparam numbit_posthandshake = numbit_handshake; 67 | reg [numbit_handshake-1:0] sft_reg; // Because address + word width 68 | reg we; // Instruction Write 69 | reg re; // Instruction Read 70 | genvar i; 71 | 72 | // Serial to paralell registers 73 | always @ (posedge SCLK) 74 | begin 75 | if(RST == 1'b0) 76 | begin 77 | sft_reg <= {numbit_handshake{1'b0}}; // RESET 78 | end else if(CEB == 1'b0) 79 | begin 80 | sft_reg <= {sft_reg[numbit_handshake-2:0], DATA}; // SHIFT 81 | end else 82 | begin 83 | sft_reg <= sft_reg; // NOTHING 84 | end 85 | end 86 | 87 | // SPI SYNC 88 | /* 89 | sync 90 | + + + + + + + + + + + + + + + + + + + + + + + + + + + + 91 | */ 92 | wire [numbit_posthandshake - 1:0] sync; 93 | generate if(syncing) begin 94 | localparam numbit_counter = clogb2(numbit_posthandshake); 95 | reg [numbit_counter - 1:0] counter; 96 | always @ (posedge SCLK) 97 | begin 98 | if(RST == 1'b0) 99 | begin 100 | counter <= {numbit_counter{1'b0}}; // RESET 101 | end else 102 | begin 103 | if(CEB == 1'b1) 104 | begin 105 | counter <= {numbit_counter{1'b0}}; // RESET 106 | end else 107 | begin 108 | counter <= counter+1; // COUNTING 109 | end 110 | end 111 | end 112 | assign sync = (1 << counter); 113 | end else begin 114 | reg [numbit_posthandshake - 1:0] counter; 115 | always @ (posedge SCLK) 116 | begin 117 | if (RST == 1'b0) 118 | begin 119 | counter <= {{(numbit_posthandshake-1){1'b0}},1'b1}; // RESET 120 | end else 121 | begin 122 | if (CEB == 1'b1) 123 | begin 124 | counter <= {{(numbit_posthandshake-1){1'b0}},1'b1}; // RESET 125 | end else 126 | begin 127 | counter <= counter << 1; // SHIFTING 128 | end 129 | end 130 | end 131 | assign sync = counter; 132 | end 133 | endgenerate 134 | 135 | // we / re capturing 136 | always @ (posedge SCLK) 137 | begin 138 | if(RST == 1'b0) 139 | begin 140 | we <= 1'b0; // RESET 141 | re <= 1'b0; 142 | end else if(CEB == 1'b0) 143 | begin 144 | if(sync[0] == 1'b1) begin 145 | we <= DATA; 146 | end 147 | if(sync[1] == 1'b1) begin 148 | re <= DATA; 149 | end 150 | end 151 | end 152 | 153 | // A_ADDR and AWDATA capturing 154 | reg [sword-1:0] A_ADDR; 155 | reg [sword-1:0] WDATA; 156 | reg PICORV_RST_SPI; 157 | always @ (posedge SCLK) 158 | begin 159 | if(RST == 1'b0) 160 | begin 161 | A_ADDR <= {sword{1'b0}}; 162 | WDATA <= {sword{1'b0}}; 163 | PICORV_RST_SPI <= 1'b0; 164 | end else if(CEB == 1'b0) 165 | begin 166 | if(sync[numbit_instr+sword-1] == 1'b1 && (re ^ we)) begin 167 | A_ADDR <= {sft_reg[sword-2:0], DATA}; 168 | end 169 | if(sync[numbit_instr+sword+sword-1] == 1'b1 && we == 1'b1) begin 170 | WDATA <= {sft_reg[sword-2:0], DATA}; 171 | end 172 | if(sync[numbit_instr+sword+sword-1] == 1'b1 && we == 1'b0 && re == 1'b0) begin 173 | PICORV_RST_SPI <= DATA; 174 | end 175 | end 176 | end 177 | 178 | // Logic and stuff 179 | wire ens, encap_status, encap_rdata, enos_status, enos_rdata, en_status, en_rdata, is_hand; 180 | wire encap, enos, rdata_notstatus; 181 | // Enable shifting 182 | assign ens = |sync[sword+2-1:2]; 183 | // Enable output shifting for status data 184 | assign enos_status = ~we & ~re & ens; 185 | // Enable output shifting for read data 186 | assign enos_rdata = we & re & ens; 187 | // Enable capture for status data (Treat DATA as re) 188 | assign encap_status = ~we & ~DATA & sync[1]; 189 | // Enable capture for read data (Treat DATA as re) 190 | assign encap_rdata = we & DATA & sync[1]; 191 | // Enable output shifting (General) 192 | assign enos = enos_status | enos_rdata; 193 | // Enable capture (General) 194 | assign encap = encap_status | encap_rdata; 195 | // Enable status data (Info for FSM) 196 | assign en_status = enos_status | encap_status; 197 | // Enable read data (Info for FSM) 198 | assign en_rdata = enos_rdata | encap_rdata; 199 | // Is handshake (Info for FSM) 200 | assign is_hand = en_status | en_rdata; 201 | // Mux selector about capturing data 202 | assign rdata_notstatus = encap_rdata; 203 | 204 | // The status flags 205 | wire [sword-1:0] status; 206 | reg busy; // TODO: FSM 207 | reg rbusy; 208 | reg wbusy; 209 | wire [2:0] status_sclk; 210 | bus_sync_sf #(.impl(0), .sword(3)) bus_sync_status(.CLK1(CLK), .CLK2(SCLK), .RST(RST), .data_in({rbusy, wbusy, busy}), .data_out(status_sclk)); 211 | assign status = {{(sword-3){1'b0}}, status_sclk}; 212 | 213 | // The data reading 214 | reg encap_data; // TODO: FSM 215 | reg [sword-1:0] rdata; 216 | always @ (posedge CLK) 217 | begin 218 | if(RST == 1'b0) 219 | begin 220 | rdata <= {sword{1'b0}}; // RESET 221 | end else if(encap_data == 1'b1) 222 | begin 223 | rdata <= axi_rdata; // CAPTURE 224 | end 225 | end 226 | wire [sword-1:0] rdata_sclk; 227 | bus_sync_sf #(.impl(0), .sword(sword)) bus_sync_rdata(.CLK1(CLK), .CLK2(SCLK), .RST(RST), .data_in(rdata), .data_out(rdata_sclk)); 228 | 229 | // Assignment to the value to capture 230 | wire [sword-1:0] bus_rd; 231 | assign bus_rd = rdata_notstatus?rdata_sclk:status; 232 | 233 | // Capturing the value to put to Dout 234 | reg [sword-1:0] bus_cap; 235 | always @ (posedge SCLK) 236 | begin 237 | if(RST == 1'b0) 238 | begin 239 | bus_cap <= {sword{1'b0}}; // RESET 240 | end else if(encap == 1'b1) 241 | begin 242 | bus_cap <= bus_rd; // CAPTURE 243 | end else if(enos == 1'b1) 244 | begin 245 | bus_cap <= bus_cap << 1; // SHIFT 246 | end 247 | end 248 | 249 | // with reg for putting the Dout 250 | wire DOUTNOZ; 251 | assign DOUTNOZ = bus_cap[sword-1]; 252 | 253 | // tri-state out 254 | wire enoz; 255 | assign enoz = enos; 256 | assign DOUT = enoz&!CEB?DOUTNOZ:1'bz; 257 | 258 | // Axi assignments 259 | wire [sword-1:0] A_ADDR_CLK; 260 | wire [sword-1:0] WDATA_CLK; 261 | bus_sync_sf #(.impl(1), .sword(sword+sword)) bus_sync_axi_bus(.CLK1(SCLK), .CLK2(CLK), .RST(RST), .data_in({A_ADDR, WDATA}), .data_out({A_ADDR_CLK, WDATA_CLK})); 262 | assign axi_araddr = A_ADDR_CLK; 263 | assign axi_awaddr = A_ADDR_CLK; 264 | assign axi_wdata = WDATA_CLK; 265 | assign axi_wstrb = 4'b1111; // Write all, SPI must write all unless inside the handshake is the wstrb 266 | assign axi_awprot = 3'b000; // Unpriviliged access, Secure access, Data access 267 | assign axi_arprot = 3'b000; // Unpriviliged access, Secure access, Data access 268 | 269 | // THE FSM 270 | // Declare state register 271 | reg [3:0]state; 272 | wire we_clk, re_clk, fini_spi_clk; 273 | // This is for sync the data with the fini_spi 274 | reg fini_spi; 275 | always @(posedge SCLK) begin 276 | if(RST == 1'b0) begin 277 | fini_spi <= 1'b0; 278 | end else begin 279 | fini_spi <= sync[numbit_instr+sword+sword-1]; 280 | end 281 | end 282 | bus_sync_sf #(.impl(1), .sword(4)) bus_sync_state_machine(.CLK1(SCLK), .CLK2(CLK), .RST(RST), .data_in({PICORV_RST_SPI, we, re, fini_spi}), .data_out({PICORV_RST, we_clk, re_clk, fini_spi_clk})); 283 | 284 | // Declare states 285 | parameter st0_nothing = 0, st1_awvalid = 1, st2_wvalid = 2, st3_wwait = 3, st4_bready = 4, st5_arvalid = 5, st6_rwait = 6, st7_rready = 7, st8_wait_spi = 8; 286 | 287 | // Output depends only on the state 288 | always @ (state) begin 289 | case (state) 290 | st0_nothing: begin 291 | axi_arvalid = 1'b0; 292 | axi_awvalid = 1'b0; 293 | axi_wvalid = 1'b0; 294 | axi_rready = 1'b0; 295 | axi_bready = 1'b0; 296 | busy = 1'b0; 297 | rbusy = 1'b0; 298 | wbusy = 1'b0; 299 | encap_data = 1'b0; end 300 | st1_awvalid: begin 301 | axi_arvalid = 1'b0; 302 | axi_awvalid = 1'b1; 303 | axi_wvalid = 1'b0; 304 | axi_rready = 1'b0; 305 | axi_bready = 1'b0; 306 | busy = 1'b1; 307 | rbusy = 1'b0; 308 | wbusy = 1'b1; 309 | encap_data = 1'b0; end 310 | st2_wvalid: begin 311 | axi_arvalid = 1'b0; 312 | axi_awvalid = 1'b1; 313 | axi_wvalid = 1'b1; 314 | axi_rready = 1'b0; 315 | axi_bready = 1'b0; 316 | busy = 1'b1; 317 | rbusy = 1'b0; 318 | wbusy = 1'b1; 319 | encap_data = 1'b0; end 320 | st3_wwait: begin 321 | axi_arvalid = 1'b0; 322 | axi_awvalid = 1'b1; 323 | axi_wvalid = 1'b1; 324 | axi_rready = 1'b0; 325 | axi_bready = 1'b0; 326 | busy = 1'b1; 327 | rbusy = 1'b0; 328 | wbusy = 1'b1; 329 | encap_data = 1'b0; end 330 | st4_bready: begin 331 | axi_arvalid = 1'b0; 332 | axi_awvalid = 1'b1; 333 | axi_wvalid = 1'b1; 334 | axi_rready = 1'b0; 335 | axi_bready = 1'b1; 336 | busy = 1'b1; 337 | rbusy = 1'b0; 338 | wbusy = 1'b1; 339 | encap_data = 1'b0; end 340 | st5_arvalid: begin 341 | axi_arvalid = 1'b1; 342 | axi_awvalid = 1'b0; 343 | axi_wvalid = 1'b0; 344 | axi_rready = 1'b0; 345 | axi_bready = 1'b0; 346 | busy = 1'b1; 347 | rbusy = 1'b1; 348 | wbusy = 1'b0; 349 | encap_data = 1'b0; end 350 | st6_rwait: begin 351 | axi_arvalid = 1'b1; 352 | axi_awvalid = 1'b0; 353 | axi_wvalid = 1'b0; 354 | axi_rready = 1'b0; 355 | axi_bready = 1'b0; 356 | busy = 1'b1; 357 | rbusy = 1'b1; 358 | wbusy = 1'b0; 359 | encap_data = 1'b0; end 360 | st7_rready: begin 361 | axi_arvalid = 1'b1; 362 | axi_awvalid = 1'b0; 363 | axi_wvalid = 1'b0; 364 | axi_rready = 1'b1; 365 | axi_bready = 1'b0; 366 | busy = 1'b1; 367 | rbusy = 1'b1; 368 | wbusy = 1'b0; 369 | encap_data = 1'b1; end 370 | st8_wait_spi: begin 371 | axi_arvalid = 1'b0; 372 | axi_awvalid = 1'b0; 373 | axi_wvalid = 1'b0; 374 | axi_rready = 1'b0; 375 | axi_bready = 1'b0; 376 | busy = 1'b1; 377 | rbusy = 1'b0; 378 | wbusy = 1'b0; 379 | encap_data = 1'b0; end 380 | default: begin 381 | axi_arvalid = 1'b0; 382 | axi_awvalid = 1'b0; 383 | axi_wvalid = 1'b0; 384 | axi_rready = 1'b0; 385 | axi_bready = 1'b0; 386 | busy = 1'b0; 387 | rbusy = 1'b0; 388 | wbusy = 1'b0; 389 | encap_data = 1'b0; end 390 | endcase 391 | end 392 | 393 | // Determine the next state 394 | always @ (posedge CLK) begin 395 | if (RST == 1'b0) 396 | state <= st0_nothing; 397 | else 398 | case (state) 399 | st0_nothing: 400 | if(we_clk & ~re_clk & fini_spi_clk) 401 | state <= st1_awvalid; 402 | else if(re_clk & ~we_clk & fini_spi_clk) 403 | state <= st5_arvalid; 404 | else 405 | state <= st0_nothing; 406 | st1_awvalid: 407 | if (axi_awready) 408 | state <= st2_wvalid; 409 | else 410 | state <= st1_awvalid; 411 | st2_wvalid: 412 | if (axi_wready) 413 | state <= st3_wwait; 414 | else 415 | state <= st2_wvalid; 416 | st3_wwait: 417 | if (axi_bvalid) 418 | state <= st4_bready; 419 | else 420 | state <= st3_wwait; 421 | st4_bready: 422 | state <= st8_wait_spi; 423 | st5_arvalid: 424 | if (axi_arready) 425 | state <= st6_rwait; 426 | else 427 | state <= st5_arvalid; 428 | st6_rwait: 429 | if (axi_rvalid) 430 | state <= st7_rready; 431 | else 432 | state <= st6_rwait; 433 | st7_rready: 434 | state <= st8_wait_spi; 435 | st8_wait_spi: 436 | if(~fini_spi_clk) 437 | state <= st0_nothing; 438 | else 439 | state <= st8_wait_spi; 440 | default: 441 | state <= st0_nothing; 442 | endcase 443 | end 444 | 445 | endmodule 446 | -------------------------------------------------------------------------------- /mriscv_axi/spi_axi_master/spi_axi_master_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module spi_axi_master_tb(); 4 | 5 | // HELPER 6 | function integer clogb2; 7 | input integer value; 8 | integer i; 9 | begin 10 | clogb2 = 0; 11 | for(i = 0; 2**i < value; i = i + 1) 12 | clogb2 = i + 1; 13 | end 14 | endfunction 15 | 16 | localparam tries = 10; 17 | localparam sword = 32; 18 | 19 | localparam impl = 0; 20 | localparam syncing = 0; 21 | 22 | // Autogen localparams 23 | 24 | reg CLK = 1'b0; 25 | reg SCLK = 1'b0; 26 | reg RST; 27 | 28 | // AXI4-lite slave memory interfaces 29 | 30 | wire axi_awvalid; 31 | reg axi_awready; 32 | wire [sword-1:0] axi_awaddr; 33 | wire [3-1:0] axi_awprot; 34 | 35 | wire axi_wvalid; 36 | reg axi_wready; 37 | wire [sword-1:0] axi_wdata; 38 | wire [4-1:0] axi_wstrb; 39 | 40 | reg axi_bvalid; 41 | wire axi_bready; 42 | 43 | wire axi_arvalid; 44 | reg axi_arready; 45 | wire [sword-1:0] axi_araddr; 46 | wire [3-1:0] axi_arprot; 47 | 48 | reg axi_rvalid; 49 | wire axi_rready; 50 | reg [sword-1:0] axi_rdata; 51 | 52 | reg DATA; 53 | wire DOUT; 54 | reg CEB; 55 | 56 | wire PICORV_RST; 57 | 58 | localparam numbit_instr = 2; // Nop (00), Read(01), Write(10) 59 | localparam numbit_address = sword; 60 | localparam numbit_handshake = numbit_instr+numbit_address+sword; 61 | 62 | reg [numbit_handshake-1:0] handshake; 63 | reg [sword-1:0] result; 64 | 65 | reg stat; 66 | 67 | integer fd1, tmp1, ifstop; 68 | integer PERIOD = 8 ; 69 | integer SPERIOD = 20 ; 70 | integer i, j, error, l; 71 | 72 | 73 | spi_axi_master /*# 74 | ( 75 | .sword(sword), 76 | .impl(impl), 77 | .syncing(syncing) 78 | ) */ 79 | inst_spi_axi_master 80 | ( 81 | .SCLK (SCLK), 82 | .CEB (CEB), 83 | .DATA (DATA), 84 | .DOUT (DOUT), 85 | .RST (RST), 86 | .CLK (CLK), 87 | .PICORV_RST(PICORV_RST), 88 | .axi_awvalid(axi_awvalid), 89 | .axi_awready(axi_awready), 90 | .axi_awaddr(axi_awaddr), 91 | .axi_awprot(axi_awprot), 92 | .axi_wvalid(axi_wvalid), 93 | .axi_wready(axi_wready), 94 | .axi_wdata(axi_wdata), 95 | .axi_wstrb(axi_wstrb), 96 | .axi_bvalid(axi_bvalid), 97 | .axi_bready(axi_bready), 98 | .axi_arvalid(axi_arvalid), 99 | .axi_arready(axi_arready), 100 | .axi_araddr(axi_araddr), 101 | .axi_arprot(axi_arprot), 102 | .axi_rvalid(axi_rvalid), 103 | .axi_rready(axi_rready), 104 | .axi_rdata(axi_rdata) 105 | ); 106 | 107 | always 108 | begin #(SPERIOD/2) SCLK = ~SCLK; end 109 | always 110 | begin #(PERIOD/2) CLK = ~CLK; end 111 | 112 | task aexpect; 113 | input [sword-1:0] av, e; 114 | begin 115 | if (av == e) 116 | $display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. MATCH!", av, e); 117 | else 118 | begin 119 | $display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. ERROR!", av, e); 120 | error = error + 1; 121 | end 122 | end 123 | endtask 124 | 125 | reg [63:0] xorshift64_state = 64'd88172645463325252; 126 | 127 | task xorshift64_next; 128 | begin 129 | // see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14). 130 | xorshift64_state = xorshift64_state ^ (xorshift64_state << 13); 131 | xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7); 132 | xorshift64_state = xorshift64_state ^ (xorshift64_state << 17); 133 | end 134 | endtask 135 | 136 | 137 | initial begin 138 | $sdf_annotate("spi_axi_master.sdf",inst_spi_axi_master); 139 | CEB = 1'b1; 140 | CLK = 1'b0; 141 | SCLK = 1'b0; 142 | RST = 1'b0; 143 | DATA = 1'b0; 144 | stat = 1'b0; 145 | error = 0; 146 | axi_awready = 1'b0; 147 | axi_wready = 1'b0; 148 | axi_bvalid = 1'b0; 149 | axi_arready = 1'b0; 150 | axi_rvalid = 1'b0; 151 | axi_rdata = {sword{1'b0}}; 152 | result = {sword{1'b0}}; 153 | handshake = {numbit_handshake{1'b0}}; 154 | #(SPERIOD*20); 155 | RST = 1'b1; 156 | 157 | #(SPERIOD*6); 158 | 159 | // SENDING PICORV RESET TO ZERO 160 | CEB = 1'b0; 161 | DATA = 1'b0; 162 | #SPERIOD; 163 | DATA = 1'b0; 164 | #SPERIOD; // SENT "SEND STATUS", but we ignore totally the result 165 | #(SPERIOD*(2*sword-1)); 166 | DATA = 1'b0; // Send to the reset 167 | #SPERIOD; 168 | CEB = 1'b1; 169 | #(SPERIOD*4); 170 | 171 | $display("The PICORV_RST is on ZERO? %b", PICORV_RST); 172 | 173 | // WRITTING TEST 174 | for(i = 0; i < tries; i = i+1) begin 175 | #(SPERIOD*8); 176 | CEB = 1'b0; 177 | // Making handshake, writting, at random dir, at random data 178 | handshake = {2'b10,xorshift64_state}; 179 | for(j = 0; j < numbit_handshake; j = j+1) begin 180 | DATA = handshake[numbit_handshake-j-1]; 181 | #SPERIOD; 182 | end 183 | CEB = 1'b1; 184 | #SPERIOD; 185 | stat = 1'b1; 186 | // Wait the axi handshake, SPI-POV 187 | while(stat) begin 188 | CEB = 1'b0; 189 | DATA = 1'b0; 190 | #SPERIOD; 191 | DATA = 1'b0; 192 | #SPERIOD; // SENT "SEND STATUS" 193 | for(j = 0; j < sword; j = j+1) begin 194 | result[sword-j-1] = DOUT; 195 | #SPERIOD; 196 | end 197 | CEB = 1'b1; 198 | #(SPERIOD*2); 199 | if(result[1] == 1'b0 && result[0] == 1'b0) begin // CHECKING WBUSY AND BUSY 200 | stat = 1'b0; 201 | end 202 | end 203 | $display ("SPI: Task: WData"); 204 | xorshift64_next; 205 | #(SPERIOD*8); 206 | end 207 | 208 | // READING TEST 209 | for(i = 0; i < tries; i = i+1) begin 210 | #(SPERIOD*8); 211 | CEB = 1'b0; 212 | // Making handshake, reading, at random dir, at random data (ignored) 213 | handshake = {2'b01,xorshift64_state}; 214 | for(j = 0; j < numbit_handshake; j = j+1) begin 215 | DATA = handshake[numbit_handshake-j-1]; 216 | #SPERIOD; 217 | end 218 | CEB = 1'b1; 219 | #(SPERIOD*3); 220 | stat = 1'b1; 221 | // Wait the axi handshake, SPI-POV 222 | while(stat) begin 223 | CEB = 1'b0; 224 | DATA = 1'b0; 225 | #SPERIOD; 226 | DATA = 1'b0; 227 | #SPERIOD; // SENT "SEND STATUS" 228 | for(j = 0; j < sword; j = j+1) begin 229 | result[sword-j-1] = DOUT; 230 | #SPERIOD; 231 | end 232 | CEB = 1'b1; 233 | #(SPERIOD*3); 234 | if(result[2] == 1'b0 && result[0] == 1'b0) begin // CHECKING RBUSY AND BUSY 235 | stat = 1'b0; 236 | end 237 | end 238 | 239 | CEB = 1'b0; 240 | DATA = 1'b1; 241 | #SPERIOD; 242 | DATA = 1'b1; 243 | #SPERIOD; // SEND "SEND RDATA" 244 | for(j = 0; j < sword; j = j+1) begin 245 | result[sword-j-1] = DOUT; 246 | #SPERIOD; 247 | end 248 | CEB = 1'b1; 249 | $display ("SPI: Task: RData"); 250 | aexpect(result, xorshift64_state[31:0]); 251 | xorshift64_next; 252 | #(SPERIOD*8); 253 | end 254 | 255 | // SENDING PICORV RESET TO ONE 256 | CEB = 1'b0; 257 | DATA = 1'b0; 258 | #SPERIOD; 259 | DATA = 1'b0; 260 | #SPERIOD; // SENT "SEND STATUS", but we ignore totally the result 261 | #(SPERIOD*(2*sword-1)); 262 | DATA = 1'b1; // Send to the reset 263 | #SPERIOD; 264 | CEB = 1'b1; 265 | #(SPERIOD*4); 266 | $display("The PICORV_RST is on ONE? %b", PICORV_RST); 267 | 268 | $timeformat(-9,0,"ns",7); 269 | #(SPERIOD*8) if (error == 0) 270 | $display("All match"); 271 | else 272 | $display("Mismatches = %d", error); 273 | $finish; 274 | end 275 | 276 | always @(posedge CLK) begin 277 | if(axi_arvalid && !axi_arready && !axi_rready) begin 278 | axi_arready = 1'b1; 279 | axi_rvalid = 1'b1; 280 | axi_rdata = xorshift64_state[31:0]; 281 | $display ("AXI: Task: RAddr"); 282 | aexpect(axi_araddr, xorshift64_state[63:32]); 283 | end else if(axi_rready) begin 284 | axi_arready = 1'b0; 285 | axi_rvalid = 1'b0; 286 | end 287 | 288 | 289 | if(axi_awvalid && !axi_awready && !axi_bready) begin 290 | axi_awready = 1'b1; 291 | $display ("AXI: Task: WAddr"); 292 | aexpect(axi_awaddr, xorshift64_state[63:32]); 293 | end else if(axi_wvalid && !axi_wready && !axi_bready) begin 294 | axi_wready = 1'b1; 295 | axi_bvalid = 1'b1; 296 | $display ("AXI: Task: WData"); 297 | aexpect(axi_wdata, xorshift64_state[31:0]); 298 | end else if(axi_bready) begin 299 | axi_awready = 1'b0; 300 | axi_wready = 1'b0; 301 | axi_bvalid = 1'b0; 302 | end 303 | end 304 | 305 | endmodule 306 | -------------------------------------------------------------------------------- /mriscv_axi/spi_axi_slave/spi_axi_slave.v: -------------------------------------------------------------------------------- 1 | // Created by: CKDUR 2 | `timescale 1ns/1ns 3 | 4 | module spi_axi_slave # 5 | ( 6 | parameter sword = 32, 7 | parameter numbit_divisor = 1, // The SCLK will be CLK/2^(numbit_divisor-1) 8 | 9 | /* 10 | IMPLEMENTATION SETTINGS 11 | impl: 0,Classic 1,Simulation 12 | syncing: 0,ByCounterAndDecoder 1,ByMirrorShiftRegister 13 | */ 14 | parameter impl = 0, 15 | parameter syncing = 0 16 | ) 17 | 18 | ( 19 | // SPI INTERFACE 20 | output CEB, 21 | output SCLK, 22 | output DATA, 23 | // MISC 24 | input RST, 25 | // AXI4-lite slave memory interface 26 | 27 | input CLK, 28 | input axi_awvalid, 29 | output axi_awready, 30 | input [sword-1:0] axi_awaddr, 31 | input [3-1:0] axi_awprot, 32 | 33 | input axi_wvalid, 34 | output reg axi_wready, 35 | input [sword-1:0] axi_wdata, 36 | input [4-1:0] axi_wstrb, 37 | 38 | output reg axi_bvalid, 39 | input axi_bready, 40 | 41 | input axi_arvalid, 42 | output axi_arready, 43 | input [sword-1:0] axi_araddr, 44 | input [3-1:0] axi_arprot, 45 | 46 | output reg axi_rvalid, 47 | input axi_rready, 48 | output [sword-1:0] axi_rdata 49 | ); 50 | 51 | // HELPER 52 | function integer clogb2; 53 | input integer value; 54 | integer i; 55 | begin 56 | clogb2 = 0; 57 | for(i = 0; 2**i < value; i = i + 1) 58 | clogb2 = i + 1; 59 | end 60 | endfunction 61 | 62 | // CONSTRAINTS 63 | // This outputs are not used 64 | // Read Channel: 65 | assign axi_rdata = 32'h00000000; 66 | assign axi_arready = 1'b1; 67 | always @(posedge CLK ) begin // A simple reactor, we ignore totally the addr, and ignore the result 68 | if(RST == 1'b0) begin 69 | axi_rvalid <= 1'b0; 70 | end else begin 71 | if(axi_rready == 1'b1) begin 72 | axi_rvalid <= 1'b0; 73 | end else if(axi_arvalid == 1'b1) begin 74 | axi_rvalid <= 1'b1; 75 | end else begin 76 | axi_rvalid <= axi_rvalid; 77 | end 78 | end 79 | end 80 | // Write Channel: 81 | // CONSIDERATION: Is supposed that the ADDR is unique. 82 | // If awvalid is triggered, awaddr is ignored 83 | // But if wvalid is triggered, the data is taken 84 | // So you will understand why I trigger all time the 85 | // awready 86 | assign axi_awready = 1'b1; 87 | 88 | // Angry CLK divisor for SCLK 89 | reg [numbit_divisor-1:0] divisor; 90 | always @(posedge CLK ) begin 91 | if(RST == 1'b0) begin 92 | divisor <= {numbit_divisor{1'b0}}; 93 | end else begin 94 | divisor <= divisor + 1; 95 | end 96 | end 97 | wire SCLK_EN; // This is an Enable that does the same that the divisor 98 | localparam [numbit_divisor-1:0] div_comp = ~(1 << (numbit_divisor-1)); 99 | assign SCLK_EN = divisor == div_comp ? 1'b1:1'b0; 100 | wire SCLKA; 101 | assign SCLKA = ~divisor[numbit_divisor-1]; 102 | // SCLK Activator (High state thing) 103 | assign SCLK = SCLKA;//(~CEB)?SCLKA:1'b0; 104 | 105 | // Counter for SPI SYNC 106 | localparam numbit_sync = clogb2(sword); 107 | localparam [numbit_sync-1:0] sync_stop = sword - 1; 108 | reg [numbit_sync-1:0] sync; 109 | wire stop; 110 | reg transmit; 111 | assign stop = sync == sync_stop? 1'b1:1'b0; 112 | always @(posedge CLK ) begin 113 | if(RST == 1'b0) begin 114 | sync <= {numbit_sync{1'b0}}; 115 | end else begin 116 | if(SCLK_EN == 1'b1) begin 117 | if((transmit == 1'b1 && ~(|sync)) || (|sync)) begin 118 | if(stop == 1'b1) begin 119 | sync <= {numbit_sync{1'b0}}; 120 | end else begin 121 | sync <= sync + 1; 122 | end 123 | end else begin 124 | sync <= sync; 125 | end 126 | end 127 | end 128 | end 129 | 130 | // Register that captures and do the Paralell-Serial 131 | reg [sword-1:0] cap_data; 132 | always @(posedge CLK ) begin 133 | if(RST == 1'b0) begin 134 | cap_data <= {sword{1'b0}}; 135 | transmit <= 1'b0; 136 | //CEB <= 1'b1; 137 | end else begin 138 | if(SCLK_EN == 1'b1) begin 139 | if(stop == 1'b1) begin 140 | cap_data <= cap_data; 141 | transmit <= 1'b0; 142 | end else if(axi_wvalid == 1'b1 && transmit == 1'b0) begin 143 | cap_data <= axi_wdata; 144 | transmit <= 1'b1; 145 | end else if(transmit == 1'b1) begin 146 | cap_data <= cap_data << 1; 147 | transmit <= transmit; 148 | end else begin 149 | cap_data <= cap_data; 150 | transmit <= transmit; 151 | end 152 | 153 | /*if(stop == 1'b1) begin 154 | CEB <= 1'b1; 155 | end else if(axi_wvalid == 1'b1) begin 156 | CEB <= 1'b0; 157 | end else begin 158 | CEB <= CEB; 159 | end*/ 160 | end 161 | end 162 | end 163 | assign CEB = ~transmit; 164 | assign DATA = (CEB==1'b0) ?cap_data[sword-1]:1'bz; 165 | 166 | // AXI control according to all 167 | always @(posedge CLK ) begin 168 | if(RST == 1'b0) begin 169 | axi_wready <= 1'b0; 170 | axi_bvalid <= 1'b0; 171 | end else begin 172 | if(axi_bready == 1'b1 && axi_bvalid == 1'b1) begin 173 | axi_wready <= 1'b0; 174 | end else if(transmit == 1'b1) begin 175 | axi_wready <= 1'b1; 176 | end else begin 177 | axi_wready <= axi_wready; 178 | end 179 | 180 | if(axi_bready == 1'b1 && axi_bvalid == 1'b1) begin 181 | axi_bvalid <= 1'b0; 182 | end else if(stop == 1'b1) begin 183 | axi_bvalid <= 1'b1; 184 | end else begin 185 | axi_bvalid <= axi_bvalid; 186 | end 187 | end 188 | end 189 | /* 190 | // Declare states 191 | parameter st0_nothing = 0, st1_awvalid = 1, st2_wvalid = 2, st3_wwait = 3, st4_bready = 4, st5_arvalid = 5, st6_rwait = 6, st7_rready = 7, st8_wait_spi = 8; 192 | 193 | // Output depends only on the state 194 | always @ (state) begin 195 | case (state) 196 | st0_nothing: begin 197 | axi_arvalid = 1'b0; 198 | axi_awvalid = 1'b0; 199 | axi_wvalid = 1'b0; 200 | axi_rready = 1'b0; 201 | axi_bready = 1'b0; 202 | busy = 1'b0; 203 | rbusy = 1'b0; 204 | wbusy = 1'b0; 205 | encap_data = 1'b0; end 206 | st1_awvalid: begin 207 | axi_arvalid = 1'b0; 208 | axi_awvalid = 1'b1; 209 | axi_wvalid = 1'b0; 210 | axi_rready = 1'b0; 211 | axi_bready = 1'b0; 212 | busy = 1'b1; 213 | rbusy = 1'b0; 214 | wbusy = 1'b1; 215 | encap_data = 1'b0; end 216 | st2_wvalid: begin 217 | axi_arvalid = 1'b0; 218 | axi_awvalid = 1'b1; 219 | axi_wvalid = 1'b1; 220 | axi_rready = 1'b0; 221 | axi_bready = 1'b0; 222 | busy = 1'b1; 223 | rbusy = 1'b0; 224 | wbusy = 1'b1; 225 | encap_data = 1'b0; end 226 | st3_wwait: begin 227 | axi_arvalid = 1'b0; 228 | axi_awvalid = 1'b1; 229 | axi_wvalid = 1'b1; 230 | axi_rready = 1'b0; 231 | axi_bready = 1'b0; 232 | busy = 1'b1; 233 | rbusy = 1'b0; 234 | wbusy = 1'b1; 235 | encap_data = 1'b0; end 236 | st4_bready: begin 237 | axi_arvalid = 1'b0; 238 | axi_awvalid = 1'b1; 239 | axi_wvalid = 1'b1; 240 | axi_rready = 1'b0; 241 | axi_bready = 1'b1; 242 | busy = 1'b1; 243 | rbusy = 1'b0; 244 | wbusy = 1'b1; 245 | encap_data = 1'b0; end 246 | st5_arvalid: begin 247 | axi_arvalid = 1'b1; 248 | axi_awvalid = 1'b0; 249 | axi_wvalid = 1'b0; 250 | axi_rready = 1'b0; 251 | axi_bready = 1'b0; 252 | busy = 1'b1; 253 | rbusy = 1'b1; 254 | wbusy = 1'b0; 255 | encap_data = 1'b0; end 256 | st6_rwait: begin 257 | axi_arvalid = 1'b1; 258 | axi_awvalid = 1'b0; 259 | axi_wvalid = 1'b0; 260 | axi_rready = 1'b0; 261 | axi_bready = 1'b0; 262 | busy = 1'b1; 263 | rbusy = 1'b1; 264 | wbusy = 1'b0; 265 | encap_data = 1'b0; end 266 | st7_rready: begin 267 | axi_arvalid = 1'b1; 268 | axi_awvalid = 1'b0; 269 | axi_wvalid = 1'b0; 270 | axi_rready = 1'b1; 271 | axi_bready = 1'b0; 272 | busy = 1'b1; 273 | rbusy = 1'b1; 274 | wbusy = 1'b0; 275 | encap_data = 1'b1; end 276 | st8_wait_spi: begin 277 | axi_arvalid = 1'b0; 278 | axi_awvalid = 1'b0; 279 | axi_wvalid = 1'b0; 280 | axi_rready = 1'b0; 281 | axi_bready = 1'b0; 282 | busy = 1'b1; 283 | rbusy = 1'b0; 284 | wbusy = 1'b0; 285 | encap_data = 1'b0; end 286 | endcase 287 | end 288 | 289 | // Determine the next state 290 | always @ (posedge CLK ) begin 291 | if (RST == 1'b0) 292 | state <= st0_nothing; 293 | else 294 | case (state) 295 | st0_nothing: 296 | if(we_clk & ~re_clk & fini_spi_clk) 297 | state <= st1_awvalid; 298 | else if(re_clk & ~we_clk & fini_spi_clk) 299 | state <= st5_arvalid; 300 | else 301 | state <= st0_nothing; 302 | st1_awvalid: 303 | if (axi_awready) 304 | state <= st2_wvalid; 305 | else 306 | state <= st1_awvalid; 307 | st2_wvalid: 308 | if (axi_wready) 309 | state <= st3_wwait; 310 | else 311 | state <= st2_wvalid; 312 | st3_wwait: 313 | if (axi_bvalid) 314 | state <= st4_bready; 315 | else 316 | state <= st3_wwait; 317 | st4_bready: 318 | state <= st8_wait_spi; 319 | st5_arvalid: 320 | if (axi_arready) 321 | state <= st6_rwait; 322 | else 323 | state <= st5_arvalid; 324 | st6_rwait: 325 | if (axi_rvalid) 326 | state <= st7_rready; 327 | else 328 | state <= st6_rwait; 329 | st7_rready: 330 | state <= st8_wait_spi; 331 | st8_wait_spi: 332 | if(~fini_spi_clk) 333 | state <= st0_nothing; 334 | else 335 | state <= st8_wait_spi; 336 | default: 337 | state <= st0_nothing; 338 | endcase 339 | end 340 | */ 341 | endmodule 342 | -------------------------------------------------------------------------------- /mriscv_axi/spi_axi_slave/spi_axi_slave_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module spi_axi_slave_tb(); 4 | 5 | // HELPER 6 | function integer clogb2; 7 | input integer value; 8 | integer i; 9 | begin 10 | clogb2 = 0; 11 | for(i = 0; 2**i < value; i = i + 1) 12 | clogb2 = i + 1; 13 | end 14 | endfunction 15 | 16 | localparam tries = 512; 17 | localparam sword = 32; 18 | 19 | localparam impl = 0; 20 | localparam syncing = 0; 21 | 22 | // Autogen localparams 23 | 24 | reg CLK = 1'b0; 25 | reg RST; 26 | 27 | // AXI4-lite master memory interfaces 28 | 29 | reg axi_awvalid; 30 | wire axi_awready; 31 | reg [sword-1:0] axi_awaddr; 32 | reg [3-1:0] axi_awprot; 33 | 34 | reg axi_wvalid; 35 | wire axi_wready; 36 | reg [sword-1:0] axi_wdata; 37 | reg [4-1:0] axi_wstrb; 38 | 39 | wire axi_bvalid; 40 | reg axi_bready; 41 | 42 | reg axi_arvalid; 43 | wire axi_arready; 44 | reg [sword-1:0] axi_araddr; 45 | reg [3-1:0] axi_arprot; 46 | 47 | wire axi_rvalid; 48 | reg axi_rready; 49 | wire [sword-1:0] axi_rdata; 50 | 51 | // SPI interface 52 | wire SCLK; 53 | wire CEB; 54 | wire DATA; 55 | 56 | // Data per capturing 57 | reg [sword-1:0] cap; 58 | 59 | 60 | integer fd1, tmp1, ifstop; 61 | integer PERIOD = 20 ; 62 | integer i, j, error, l; 63 | 64 | 65 | spi_axi_slave 66 | inst_spi_axi_slave 67 | ( 68 | .CLK (CLK), 69 | .RST (RST), 70 | .SCLK(SCLK), 71 | .CEB(CEB), 72 | .DATA(DATA), 73 | .axi_awvalid(axi_awvalid), 74 | .axi_awready(axi_awready), 75 | .axi_awaddr(axi_awaddr), 76 | .axi_awprot(axi_awprot), 77 | .axi_wvalid(axi_wvalid), 78 | .axi_wready(axi_wready), 79 | .axi_wdata(axi_wdata), 80 | .axi_wstrb(axi_wstrb), 81 | .axi_bvalid(axi_bvalid), 82 | .axi_bready(axi_bready), 83 | .axi_arvalid(axi_arvalid), 84 | .axi_arready(axi_arready), 85 | .axi_araddr(axi_araddr), 86 | .axi_arprot(axi_arprot), 87 | .axi_rvalid(axi_rvalid), 88 | .axi_rready(axi_rready), 89 | .axi_rdata(axi_rdata) 90 | ); 91 | 92 | always 93 | begin #(PERIOD/2) CLK = ~CLK; end 94 | 95 | task aexpect; 96 | input [sword-1:0] av, e; 97 | begin 98 | if (av == e) 99 | $display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. MATCH!", av, e); 100 | else 101 | begin 102 | $display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. ERROR!", av, e); 103 | error = error + 1; 104 | end 105 | end 106 | endtask 107 | 108 | reg [63:0] xorshift64_state = 64'd88172645463325252; 109 | 110 | task xorshift64_next; 111 | begin 112 | // see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14). 113 | xorshift64_state = xorshift64_state ^ (xorshift64_state << 13); 114 | xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7); 115 | xorshift64_state = xorshift64_state ^ (xorshift64_state << 17); 116 | end 117 | endtask 118 | 119 | 120 | initial begin 121 | $sdf_annotate("spi_axi_slave.sdf",inst_spi_axi_slave); 122 | CLK = 1'b0; 123 | RST = 1'b0; 124 | cap = {sword{1'b0}}; 125 | error = 0; 126 | axi_awvalid = 1'b0; 127 | axi_wvalid = 1'b0; 128 | axi_bready = 1'b0; 129 | axi_arvalid = 1'b0; 130 | axi_rready = 1'b0; 131 | axi_awaddr = {sword{1'b0}}; 132 | axi_awprot = {3{1'b0}}; 133 | axi_wdata = {sword{1'b0}}; 134 | axi_wstrb = 4'b1111; 135 | axi_araddr = {sword{1'b0}}; 136 | axi_arprot = {3{1'b0}}; 137 | #101; 138 | RST = 1'b1; 139 | // WRITTING AND READING TEST 140 | // BASICALLY, WHAT I READ, IS WHAT I WRITE 141 | for(i = 0; i < tries; i = i+1) begin 142 | #(PERIOD*8); 143 | // WRITTING TEST 144 | axi_awvalid = 1'b1; 145 | #PERIOD; 146 | while(!axi_awready) begin 147 | #PERIOD; 148 | end 149 | axi_wvalid = 1'b1; 150 | axi_wdata = xorshift64_state[sword-1:0]; 151 | while(!axi_wready) begin 152 | #PERIOD; 153 | end 154 | while(!axi_bvalid) begin 155 | #PERIOD; 156 | end 157 | axi_bready = 1'b1; 158 | #PERIOD; 159 | axi_awvalid = 1'b0; 160 | axi_wvalid = 1'b0; 161 | axi_bready = 1'b0; 162 | 163 | // Waiting the SPI for finishing 164 | while(!CEB) begin 165 | #PERIOD; 166 | end 167 | aexpect(cap, xorshift64_state[sword-1:0]); 168 | xorshift64_next; 169 | end 170 | $timeformat(-9,0,"ns",7); 171 | #(PERIOD*8) if (error == 0) 172 | $display("All match"); 173 | else 174 | $display("Mismatches = %d", error); 175 | $finish; 176 | end 177 | 178 | always @(posedge SCLK) begin 179 | if(CEB == 1'b0) begin 180 | cap = {cap[sword-2:0], DATA}; 181 | end 182 | end 183 | 184 | endmodule 185 | -------------------------------------------------------------------------------- /mriscv_axi/util/bus_sync_sf.v: -------------------------------------------------------------------------------- 1 | // CLOCK DOMAIN SYNC BY CKDUR 2 | `timescale 1ns/1ns 3 | 4 | module bus_sync_sf # 5 | ( 6 | // 0 F1 > F2, 1 F1 < F2 7 | parameter impl = 0, 8 | // Numbits 9 | parameter sword = 32 10 | ) 11 | ( 12 | input CLK1, 13 | input CLK2, 14 | input RST, 15 | input [sword-1:0] data_in, 16 | output [sword-1:0] data_out 17 | ); 18 | 19 | generate 20 | if (impl) begin 21 | wire NCLK2; 22 | assign NCLK2 = ~CLK2; 23 | reg ECLK1, EECLK1; 24 | always @(posedge NCLK2) begin 25 | if(RST == 1'b0) begin 26 | ECLK1 <= 1'b0; 27 | EECLK1 <= 1'b0; 28 | end else begin 29 | ECLK1 <= CLK1; 30 | EECLK1 <= ECLK1; 31 | end 32 | end 33 | reg [sword-1:0] reg_data1; 34 | reg [sword-1:0] reg_data2; 35 | reg [sword-1:0] reg_data3; 36 | always @(posedge CLK1) begin 37 | if(RST == 1'b0) begin 38 | reg_data1 <= {sword{1'b0}}; 39 | end else begin 40 | reg_data1 <= data_in; 41 | end 42 | end 43 | always @(posedge CLK2) begin 44 | if(RST == 1'b0) begin 45 | reg_data2 <= {sword{1'b0}}; 46 | reg_data3 <= {sword{1'b0}}; 47 | end else begin 48 | if(EECLK1) begin 49 | reg_data2 <= reg_data1; 50 | end 51 | reg_data3 <= reg_data2; 52 | end 53 | end 54 | assign data_out = reg_data3; 55 | end else begin 56 | wire NCLK1; 57 | assign NCLK1 = ~CLK1; 58 | reg ECLK2, EECLK2; 59 | always @(posedge NCLK1) begin 60 | if(RST == 1'b0) begin 61 | ECLK2 <= 1'b0; 62 | EECLK2 <= 1'b0; 63 | end else begin 64 | ECLK2 <= CLK2; 65 | EECLK2 <= ECLK2; 66 | end 67 | end 68 | reg [sword-1:0] reg_data1; 69 | reg [sword-1:0] reg_data2; 70 | reg [sword-1:0] reg_data3; 71 | always @(posedge CLK1) begin 72 | if(RST == 1'b0) begin 73 | reg_data1 <= {sword{1'b0}}; 74 | reg_data2 <= {sword{1'b0}}; 75 | end else begin 76 | reg_data1 <= data_in; 77 | if(EECLK2) begin 78 | reg_data2 <= reg_data1; 79 | end 80 | end 81 | end 82 | always @(posedge CLK2) begin 83 | if(RST == 1'b0) begin 84 | reg_data3 <= {sword{1'b0}}; 85 | end else begin 86 | reg_data3 <= reg_data2; 87 | end 88 | end 89 | assign data_out = reg_data3; 90 | end 91 | endgenerate 92 | 93 | endmodule -------------------------------------------------------------------------------- /mriscv_axi/util/priencr.v: -------------------------------------------------------------------------------- 1 | module priencr #(parameter width = 64) 2 | ( 3 | input [width-1:0] decode, 4 | output [log2(width)-1:0] encode, 5 | output valid 6 | ); 7 | 8 | function [31:0] log2; 9 | input reg [31:0] value; 10 | begin 11 | value = value-1; 12 | for (log2=0; value>0; log2=log2+1) 13 | value = value>>1; 14 | end 15 | endfunction 16 | 17 | generate 18 | if (width == 2) 19 | begin 20 | assign valid = |decode; 21 | assign encode = decode[1]; 22 | end 23 | else if (width & (width-1)) 24 | priencr #(1<>1) low(decode[(width>>1)-1:0],encode_low,valid_low); 32 | priencr #(width>>1) high(decode[width-1:width>>1],encode_high,valid_high); 33 | assign valid = valid_low | valid_high; 34 | assign encode = valid_high ? {1'b1,encode_high} : {1'b0,encode_low}; 35 | end 36 | endgenerate 37 | endmodule --------------------------------------------------------------------------------