├── README.md ├── audio.json ├── core.json ├── data.json ├── dist ├── .gitkeep ├── assets │ └── .keep ├── icon.bin └── platforms │ ├── _images │ └── ex_platform.bin │ └── ex_platform.json ├── info.txt ├── input.json ├── interact.json ├── output ├── .gitkeep └── bitstream.rbf_r ├── src └── fpga │ ├── .gitignore │ ├── ap_core.qpf │ ├── ap_core.qsf │ ├── apf │ ├── apf.qip │ ├── apf_constraints.sdc │ ├── apf_top.v │ ├── build_id.mif │ ├── build_id_gen.tcl │ ├── common.v │ ├── io_bridge_peripheral.v │ ├── io_pad_controller.v │ ├── mf_datatable.qip │ ├── mf_datatable.v │ ├── mf_ddio_bidir_12.qip │ └── mf_ddio_bidir_12.v │ ├── core │ ├── core_bridge_cmd.v │ ├── core_constraints.sdc │ ├── core_top.v │ ├── mf_pllbase.bsf │ ├── mf_pllbase.ppf │ ├── mf_pllbase.qip │ ├── mf_pllbase.sip │ ├── mf_pllbase.spd │ ├── mf_pllbase.v │ ├── mf_pllbase │ │ ├── mf_pllbase_0002.qip │ │ └── mf_pllbase_0002.v │ ├── mf_pllbase_sim.f │ ├── mf_pllbase_sim │ │ ├── aldec │ │ │ └── rivierapro_setup.tcl │ │ ├── cadence │ │ │ ├── cds.lib │ │ │ ├── hdl.var │ │ │ └── ncsim_setup.sh │ │ ├── mentor │ │ │ └── msim_setup.tcl │ │ ├── mf_pllbase.vo │ │ └── synopsys │ │ │ ├── vcs │ │ │ └── vcs_setup.sh │ │ │ └── vcsmx │ │ │ ├── synopsys_sim.setup │ │ │ └── vcsmx_setup.sh │ ├── pin_ddio_clk.ppf │ ├── pin_ddio_clk.qip │ ├── pin_ddio_clk.v │ └── stp1.stp │ └── output_files │ ├── .gitignore │ ├── ap_core.jdi │ ├── ap_core.rbf │ └── ap_core.sof ├── variants.json └── video.json /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/README.md -------------------------------------------------------------------------------- /audio.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/audio.json -------------------------------------------------------------------------------- /core.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/core.json -------------------------------------------------------------------------------- /data.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/data.json -------------------------------------------------------------------------------- /dist/.gitkeep: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /dist/assets/.keep: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /dist/icon.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/dist/icon.bin -------------------------------------------------------------------------------- /dist/platforms/_images/ex_platform.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/dist/platforms/_images/ex_platform.bin -------------------------------------------------------------------------------- /dist/platforms/ex_platform.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/dist/platforms/ex_platform.json -------------------------------------------------------------------------------- /info.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/info.txt -------------------------------------------------------------------------------- /input.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/input.json -------------------------------------------------------------------------------- /interact.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/interact.json -------------------------------------------------------------------------------- /output/.gitkeep: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /output/bitstream.rbf_r: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/output/bitstream.rbf_r -------------------------------------------------------------------------------- /src/fpga/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/.gitignore -------------------------------------------------------------------------------- /src/fpga/ap_core.qpf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/ap_core.qpf -------------------------------------------------------------------------------- /src/fpga/ap_core.qsf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/ap_core.qsf -------------------------------------------------------------------------------- /src/fpga/apf/apf.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/apf/apf.qip -------------------------------------------------------------------------------- /src/fpga/apf/apf_constraints.sdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/apf/apf_constraints.sdc -------------------------------------------------------------------------------- /src/fpga/apf/apf_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/apf/apf_top.v -------------------------------------------------------------------------------- /src/fpga/apf/build_id.mif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/apf/build_id.mif -------------------------------------------------------------------------------- /src/fpga/apf/build_id_gen.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/apf/build_id_gen.tcl -------------------------------------------------------------------------------- /src/fpga/apf/common.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/apf/common.v -------------------------------------------------------------------------------- /src/fpga/apf/io_bridge_peripheral.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/apf/io_bridge_peripheral.v -------------------------------------------------------------------------------- /src/fpga/apf/io_pad_controller.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/apf/io_pad_controller.v -------------------------------------------------------------------------------- /src/fpga/apf/mf_datatable.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/apf/mf_datatable.qip -------------------------------------------------------------------------------- /src/fpga/apf/mf_datatable.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/apf/mf_datatable.v -------------------------------------------------------------------------------- /src/fpga/apf/mf_ddio_bidir_12.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/apf/mf_ddio_bidir_12.qip -------------------------------------------------------------------------------- /src/fpga/apf/mf_ddio_bidir_12.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/apf/mf_ddio_bidir_12.v -------------------------------------------------------------------------------- /src/fpga/core/core_bridge_cmd.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/core_bridge_cmd.v -------------------------------------------------------------------------------- /src/fpga/core/core_constraints.sdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/core_constraints.sdc -------------------------------------------------------------------------------- /src/fpga/core/core_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/core_top.v -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.bsf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase.bsf -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.ppf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase.ppf -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase.qip -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.sip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase.sip -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.spd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase.spd -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase.v -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase/mf_pllbase_0002.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase/mf_pllbase_0002.qip -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase/mf_pllbase_0002.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase/mf_pllbase_0002.v -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase_sim.f -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/cadence/cds.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase_sim/cadence/cds.lib -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/cadence/ncsim_setup.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase_sim/cadence/ncsim_setup.sh -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/mentor/msim_setup.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase_sim/mentor/msim_setup.tcl -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/mf_pllbase.vo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase_sim/mf_pllbase.vo -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/synopsys/vcs/vcs_setup.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase_sim/synopsys/vcs/vcs_setup.sh -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/synopsys_sim.setup -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/vcsmx_setup.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/vcsmx_setup.sh -------------------------------------------------------------------------------- /src/fpga/core/pin_ddio_clk.ppf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/pin_ddio_clk.ppf -------------------------------------------------------------------------------- /src/fpga/core/pin_ddio_clk.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/pin_ddio_clk.qip -------------------------------------------------------------------------------- /src/fpga/core/pin_ddio_clk.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/pin_ddio_clk.v -------------------------------------------------------------------------------- /src/fpga/core/stp1.stp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/core/stp1.stp -------------------------------------------------------------------------------- /src/fpga/output_files/.gitignore: -------------------------------------------------------------------------------- 1 | !*.sof 2 | !*.rbf -------------------------------------------------------------------------------- /src/fpga/output_files/ap_core.jdi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/output_files/ap_core.jdi -------------------------------------------------------------------------------- /src/fpga/output_files/ap_core.rbf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/output_files/ap_core.rbf -------------------------------------------------------------------------------- /src/fpga/output_files/ap_core.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/src/fpga/output_files/ap_core.sof -------------------------------------------------------------------------------- /variants.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/variants.json -------------------------------------------------------------------------------- /video.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/open-fpga/core-template/HEAD/video.json --------------------------------------------------------------------------------