├── README.md └── LICENSE /README.md: -------------------------------------------------------------------------------- 1 | # Awesome Neuromorphic Hardware [![Awesome](https://awesome.re/badge-flat.svg)](https://awesome.re) 2 | 3 | This repo collects papers, docs, codes about neuromorphic hardware for anyone who wants to do research on it. We are continuously improving the project. Welcome to PR the works (papers, repositories) that are missed by the repo. Inspired by [awesome-model-quantization](https://github.com/htqin/awesome-model-quantization). 4 | 5 | - [Survey Papers](#Survey_Papers) 6 | 7 | - [Papers](#Papers) 8 | - [2023](#2023) 9 | - [2022](#2022) 10 | - [2021](#2021) 11 | - [2020](#2020) 12 | - [2019](#2019) 13 | - [2018](#2018) 14 | - [2017](#2017) 15 | - [2016](#2016) 16 | - [2015](#2015) 17 | - [2014](#2014) 18 | - [2013](#2013) 19 | - [2011](#2011) 20 | - [2010](#2010) 21 | 22 | ## Survey Papers 23 | 24 | - [[IEEE-Proc](https://arxiv.org/abs/2109.12894)] Training Spiking Neural Networks Using Lessons From Deep Learning, **2023**. 25 | - [[IEEE-JETCAS](https://arxiv.org/abs/2306.15749)] To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration, **2023**. 26 | - [[IEEE-CICC](https://arxiv.org/abs/2203.07006)] Spiking Neural Network Integrated Circuits: A Review of Trends and Future Directions, **2022**. 27 | ## Papers 28 | 29 | ### 2023 30 | 31 | - [[IEEE-JETCAS](https://ieeexplore.ieee.org/document/10304185)] Programming Weights to Analog In-Memory Computing Cores by Direct Minimization of the Matrix-Vector Multiplication Error. [__`asic`__][__`imc`__][__`memristive`__][__`mixed-signal`__] 32 | - [[IEEE-JETCAS](https://ieeexplore.ieee.org/document/10286500)] Multicore Spiking Neuromorphic Chip in 180-nm with ReRAM Synapses and Digital Neurons. [__`asic`__][__`imc`__][__`memristive`__][__`mixed-signal`__] 33 | - [[IEEE-JETCAS](https://ieeexplore.ieee.org/abstract/document/10268434)] Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator with Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Application [__`asic`__][__`imc`__][__`memristive`__] 34 | - [[IEEE-TVLSI](https://ieeexplore.ieee.org/abstract/document/10269541)] Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory [__`asic`__][__`imc`__] 35 | - [[IEEE-TED](https://ieeexplore.ieee.org/abstract/document/10272308)] Neuromorphic Accelerator for Spiking Neural Network Using SOT-MRAM Crossbar Array [__`mixed-signal`__][__`asic`__][__`imc`__][__`memristive`__] 36 | - [[ArXiv](https://arxiv.org/abs/2310.00564)] DYNAP-SE2: a scalable multi-core dynamic neuromorphic asynchronous spiking neural network processor [__`mixed-signal`__][__`asic`__][__`async`__] 37 | - [[ArXiv](https://arxiv.org/abs/2309.16158)] FireFly v2: Advancing Hardware Support for High-Performance Spiking Neural Network with a Spatiotemporal FPGA Accelerator [__`digital`__][__`fgpa`__] 38 | - [[IEEE-JETCAS](https://ieeexplore.ieee.org/document/10271336)] C-DNN V2: Complementary Deep-Neural-Network Processor with Full-Adder/OR-based Reduction Tree and Reconfigurable Spatial Weight Reuse [__`digital`__][__`asic`__] 39 | - [[IEEE-TVLSI](https://arxiv.org/abs/2301.01905)] FireFly: A High-Throughput and Reconfigurable Hardware Accelerator for Spiking Neural Networks. [__`digital`__][__`fpga`__] 40 | - [[IEEE-ISCAS](https://arxiv.org/abs/2302.01015)] OpenSpike: An OpenRAM SNN Accelerator. [__`digital`__][__`asic`__][__`open-source`__][[Code](https://github.com/sfmth/OpenSpike)] 41 | - [[ArXiv](https://arxiv.org/abs/2212.01696)] THOR -- A Neuromorphic Processor with 7.29G TSOP2/mm2Js Energy-Throughput Efficiency. [__`digital`__][__`asic`__] 42 | - [[IEEE-TCAD](https://ieeexplore.ieee.org/document/9785601)] The Implementation and Optimization of Neuromorphic Hardware for Supporting Spiking Neural Networks With MLP and CNN Topologies [__`digital`__][__`fpga`__] 43 | - [[ArXiv](https://arxiv.org/abs/2305.05187)] DeepFire2: A Convolutional Spiking Neural Network Accelerator on FPGAs. [__`digital`__][__`fpga`__] 44 | - [[IEEE-JSSC](https://ieeexplore.ieee.org/abstract/document/10121702)] SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit. [__`digital`__][__`asic`__] 45 | - [[IEEE-ISSCC](https://ieeexplore.ieee.org/abstract/document/10067497)] C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation. [__`digital`__][__`asic`__] 46 | - [[IEEE-CICC](https://ieeexplore.ieee.org/abstract/document/10121315)] A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology. [__`digital`__][__`asic`__][__`in-memory-computing`__] 47 | - [[IEEE-ISCAS](https://www.linkedin.com/posts/bo-wang-114b17a0_shenjing-npu-activity-7064489906835787776-zroT?utm_source=share&utm_medium=member_desktop)] 1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing. [__`digital`__][__`asic`__] 48 | - [[IEEE-JSSC](https://ieeexplore.ieee.org/abstract/document/10130013)] Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital–Analog Networks. [__`digital`__][__`asic`__][__`mixed-signal`__] 49 | - [[IEEE-TCAS-II](https://ieeexplore.ieee.org/abstract/document/10129114)] Design of Time-Encoded Spiking Neural Networks in 7nm CMOS Technology. [__`digital`__][__`asic`__] 50 | - [[ArXiv](https://arxiv.org/abs/2305.16187)] A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses. [__`mixed-signal`__][__`memristive`__] 51 | - [[IEEE-TBioCAS](https://ieeexplore.ieee.org/abstract/document/10132492)] A 510μW 0.738-mm2 6.2-pJ/SOP Online Learning Multi-Topology SNN Processor with Unified Computation Engine in 40-nm CMOS. [__`digital`__][__`asic`__] 52 | - [[IEEE-TCAS-II](https://ieeexplore.ieee.org/abstract/document/10143982)] A 24.3μJ/Image SNN Accelerator for DVS-Gesture with WS-LOS Dataflow and Sparse Methods. [__`digital`__][__`asic`___] 53 | - [[IEEE-ISSCC](https://ieeexplore.ieee.org/document/10067650)] 22.6 ANP-I: A 28nm 1.5pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-O.1 μJ/Sample On-Chip Learning for Edge-AI Applications. [__`digital`__][__`asic`__][__`async`__] 54 | - [[IEEE-TCAD](https://ieeexplore.ieee.org/abstract/document/9914608)] SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks [__`digital`__][__`asic`__] 55 | - [[IEEE-COOL-CHIPS](https://ieeexplore.ieee.org/document/10121940)] COOL-NPU: Complementary Online Learning Neural Processing Unit with CNN-SNN Heterogeneous Core and Event-driven Backpropagation. 56 | - [[IEEE-TCAS-I](https://ieeexplore.ieee.org/abstract/document/10160227)] An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40- μ s Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique. [__`async`__][__`asic`__][__`imc`__][__`mixed-signal`__] 57 | - [[IEEE-AICAS](https://arxiv.org/abs/2307.06084)] Neuromorphic analog circuits for robust on-chip always-on learning in spiking neural networks. [__`asic`__][__`mixed-signal`__][__`on-chip-learning`__] 58 | - [[ArXiv](https://arxiv.org/abs/2307.08116)] Scaling Limits of Memristor-Based Routers for Asynchronous Neuromorphic Systems. [__`mixed-signal`__][__`memristive`__] 59 | 60 | ### 2022 61 | 62 | - [[IEEE-ISSCC](https://arxiv.org/abs/2208.09759)] ReckOn: A 28nm Sub-mm2 Task-Agnostic Spiking Recurrent Neural Network Processor Enabling On-Chip Learning over Second-Long Timescales. [__`digital`__][__`asic`__][__`open-source`__][[Code](https://github.com/chfrenkel/ReckON)] 63 | - [[DATE](https://arxiv.org/abs/2204.10687)] SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions. [__`digital`__][__`asic`__][__`open-source`__][[Code](https://github.com/pulp-platform/sne)] 64 | - [[IEEE-TCAS-I](https://arxiv.org/abs/2205.00778)] Sparse Compressed Spiking Neural Network Accelerator for Object Detection. [__`digital`__][__`asic`__] 65 | - [[IEEE-TCAD](https://arxiv.org/abs/2203.07516)] Skydiver: A Spiking Neural Network Accelerator Exploiting Spatio-Temporal Workload Balance [__`digital`__][__`fpga`__] 66 | - [[IEEE/ACM-DAC](https://mxhx7199.github.io/files/[DAC-2022]SATO_preprint.pdf)] SATO: spiking neural network acceleration via temporal-oriented dataflow and architecture [__`digital`__][__`asic`__] 67 | - [[IEEE-JSSC](https://ieeexplore.ieee.org/abstract/document/9731795)] An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique. [__`digital`__][__`asic`__][__`async`__][__`imc`__] 68 | - [[IEEE-Access](https://ieeexplore.ieee.org/abstract/document/9763524)] A 18.7 TOPS/W Mixed-Signal Spiking Neural Network Processor With 8-bit Synaptic Weight On-Chip Learning That Operates in the Continuous-Time Domain. [__`mixed-signal`__][__`online-learning`__][__`asic`__] 69 | 70 | ### 2021 71 | 72 | - [[Frontiers](https://www.frontiersin.org/articles/10.3389/fnins.2021.664208/full)] μBrain: An Event-Driven and Fully Synthesizable Architecture for Spiking Neural Networks. [__`digital`__][__`asic`__][__`async`__] 73 | - [[ArXiv](https://arxiv.org/abs/2103.08392)] The SpiNNaker 2 processing element architecture for hybrid digital neuromorphic computing. [__`digital`__][__`asic`__][__`async`__] 74 | - [[IEEE-TCAS-I](https://ieeexplore.ieee.org/document/9546038)] A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router. [__`digital`__][__`asic`__] 75 | - [[IEEE-LSSC](https://arxiv.org/abs/2105.08217)] IMPULSE: A 65-nm Digital Compute-in-Memory Macro With Fused Weights and Membrane Potential for Spike-Based Sequential Learning Tasks. [__`digital`__][__`asic`__] 76 | - [[IEEE-TVLSI](https://ieeexplore.ieee.org/document/9855834)] Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks [__`digital`__][__`fpga`__] 77 | - [[ACM-TRTS](https://www.sfu.ca/~zhenman/files/C21-FPL2021-SyncNN.pdf)] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs [__`digital`__][__`fpga`__][[Code](https://github.com/SFU-HiAccel/SyncNN)] 78 | - [[IEEE-FPL](https://www.comp.nus.edu.sg/~wongwf/papers/FPL_2021_FINAL.pdf)] DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays [__`digital-FPGA`__] 79 | - [[ACM-FPGA](https://dl.acm.org/doi/10.1145/3431920.3439283)] S2N2: A FPGA Accelerator for Streaming Spiking Neural Networks [__`digital`__][__`fpga`__] 80 | - [[IEEE-TCAS-I](https://ieeexplore.ieee.org/document/9336327)] A Fast and Energy-Efficient SNN Processor With Adaptive Clock/Event-Driven Computation Scheme and Online Learning [__`digital`__][__`fpga`__] 81 | 82 | ### 2020 83 | 84 | - [[IEEE-A-SSCC](https://arxiv.org/abs/2006.12314)] Always-On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device. [__`digital`__][__`asic`__][__`async`__] 85 | - [[IEEE-JSSC](https://ieeexplore.ieee.org/document/8998338)] Tianjic: A unified and scalable chip bridging spike-based and continuous neural computation. [__`digital`__][__`asic`__] 86 | - [[IEEE-RAW](https://arxiv.org/abs/2004.06061)] FPGA Based Emulation Environment for Neuromorphic Architectures. [__`digital`__][__`fpga`__][[Code](https://github.com/UA-RCL/RANC)] 87 | - [[IEEE-A-SSCC](https://ieeexplore.ieee.org/document/9336142)] 0.5V 4.8 pJ/SOP 0.93μW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron. [__`digital`__][__`asic`__] 88 | - [[IEEE-ISSCC](https://ieeexplore.ieee.org/document/9062979)] A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. [__`mixed-signal`__] 89 | - [[Springer-JCST](https://jcst.ict.ac.cn/fileup/1000-9000/PDF/2020-2-21-9686.pdf)] SIES: A Novel Implementation of Spiking Convolutional Neural Network Inference Engine on Field-Programmable Gate Array [__`digital`__][__`fpga`__] 90 | - [[IEEE/ACM-ISCA](https://users.cs.utah.edu/~rajeev/pubs/isca20s.pdf)] SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks [__`digital`__][__`asic`__] 91 | - [[IEEE/ACM-ICCAD](https://dl.acm.org/doi/10.1145/3400302.3415608)] Encoding, model, and architecture: systematic optimization for spiking neural network in FPGAs [__`digital`__][__`fpga`__] 92 | - [[IEEE-JSSC](https://ieeexplore.ieee.org/abstract/document/9222208)] NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics. [__`mixed-signal`__][__`asic`__] 93 | 94 | 95 | ### 2019 96 | 97 | - [[IEEE-TBioCAS](https://arxiv.org/abs/1804.07858)] A 0.086-mm2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS. [__`digital`__][__`asic`__][__`open-source`__][[ODIN](https://github.com/ChFrenkel/ODIN)][[TinyODIN](https://github.com/ChFrenkel/tinyODIN)] 98 | - [[IEEE-TBioCAS](https://arxiv.org/abs/1904.08513)] MorphIC: A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning. [__`digital`__][__`asic`__] 99 | - [[IJSSC](https://ieeexplore.ieee.org/document/8588363)] A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS. [__`digital`__][__`asic`__] 100 | - [[IEEE-CICC](https://web.eecs.umich.edu/~zhengya/papers/cho_cicc19.pdf)] A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS. [__`digital`__][__`asic`__] 101 | - [[IEEE-JSSC](https://ieeexplore.ieee.org/document/8867974)] A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback. [__`digital`__][__`asic`__] 102 | - [[IEEE-ISVLSI](https://picture.iczhiku.com/resource/ieee/SHKwGhQOijggRvXX.pdf)] RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation. [__`mixed-signal`__] 103 | 104 | ### 2018 105 | 106 | - [[IEEE-MICRO](https://redwood.berkeley.edu/wp-content/uploads/2021/08/Davies2018.pdf)] Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. [__`digital`__][__`asic`__] 107 | - [[IEEE-TBioCAS](https://ieeexplore.ieee.org/document/8094868)] A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs). [__`mixed-signal`__] 108 | - [[IEEE-JPROC](https://ieeexplore.ieee.org/document/8591981)] Braindrop: A Mixed-Signal Neuromorphic Architecture With a Dynamical Systems-Based Programming Model. [__`mixed-signal`__][[Thesis](https://stacks.stanford.edu/file/druid:sg377qc5355/thesis_toplevel-augmented.pdf)] 109 | 110 | ### 2017 111 | 112 | - [[IEEE-ISVLSI](https://ieeexplore.ieee.org/document/8008536)] A 3.43TOPS/W 48.9pJ/pixel 50.1nJ/classification 512 analog neuron sparse coding neural network with on-chip learning and classification in 40nm CMOS. [__`mixed-signal`__] 113 | 114 | ### 2015 115 | 116 | - [[IEEE-TCAD](https://redwood.berkeley.edu/wp-content/uploads/2021/08/Akopyan2015.pdf)] TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. [__`digital`__][__`asic`__][__`async`__] 117 | - [[Frontiers](https://www.frontiersin.org/articles/10.3389/fnins.2015.00141/full)] A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses. [__`mixed-signal`__][__`async`__] 118 | - [[IEEE-ISVLSI](http://vlsisp.engin.umich.edu/wp-content/uploads/sites/334/2017/11/kim-vlsi-2015.pdf)] A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning. 119 | - [[IEEE-TBioCAS](https://arxiv.org/pdf/1412.3233)] A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits. 120 | 121 | ### 2014 122 | 123 | - [[IEEE-BioCAS](https://ieeexplore.ieee.org/document/6981816)] A 65k-neuron 73-Mevents/s 22-pJ/event asynchronous micro-pipelined integrate-and-fire array transceiver.[__`async`__] 124 | - [[IEEE-JPROC](https://ieeexplore.ieee.org/document/6805187)] Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations. [__`mixed-signal`__] 125 | - [[IEEE-TVLSI](https://ieeexplore.ieee.org/document/6701396)] Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator. [__`digital`__][__`fpga`__] 126 | 127 | ### 2013 128 | 129 | - [[IEEE-MICRO](https://ieeexplore.ieee.org/document/6515159)] SpiNNaker: A 1-W 18-Core System-onChip for Massively-Parallel Neural Network Simulation. [__`digital`__][__`asic`__][__`async`__] 130 | 131 | ### 2011 132 | 133 | - [[IEEE-CICC](https://ieeexplore.ieee.org/document/6055293)] A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. 134 | 135 | ### 2010 136 | 137 | - [[IEEE-ISCAS](https://ieeexplore.ieee.org/document/5536970)] A wafer-scale neuromorphic hardware system for large-scale neural modeling. [__`mixed-signal`__] 138 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 2, June 1991 3 | 4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc., 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | Preamble 10 | 11 | The licenses for most software are designed to take away your 12 | freedom to share and change it. By contrast, the GNU General Public 13 | License is intended to guarantee your freedom to share and change free 14 | software--to make sure the software is free for all its users. This 15 | General Public License applies to most of the Free Software 16 | Foundation's software and to any other program whose authors commit to 17 | using it. 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Any attempt 174 | otherwise to copy, modify, sublicense or distribute the Program is 175 | void, and will automatically terminate your rights under this License. 176 | However, parties who have received copies, or rights, from you under 177 | this License will not have their licenses terminated so long as such 178 | parties remain in full compliance. 179 | 180 | 5. You are not required to accept this License, since you have not 181 | signed it. However, nothing else grants you permission to modify or 182 | distribute the Program or its derivative works. These actions are 183 | prohibited by law if you do not accept this License. Therefore, by 184 | modifying or distributing the Program (or any work based on the 185 | Program), you indicate your acceptance of this License to do so, and 186 | all its terms and conditions for copying, distributing or modifying 187 | the Program or works based on it. 188 | 189 | 6. Each time you redistribute the Program (or any work based on the 190 | Program), the recipient automatically receives a license from the 191 | original licensor to copy, distribute or modify the Program subject to 192 | these terms and conditions. You may not impose any further 193 | restrictions on the recipients' exercise of the rights granted herein. 194 | You are not responsible for enforcing compliance by third parties to 195 | this License. 196 | 197 | 7. If, as a consequence of a court judgment or allegation of patent 198 | infringement or for any other reason (not limited to patent issues), 199 | conditions are imposed on you (whether by court order, agreement or 200 | otherwise) that contradict the conditions of this License, they do not 201 | excuse you from the conditions of this License. If you cannot 202 | distribute so as to satisfy simultaneously your obligations under this 203 | License and any other pertinent obligations, then as a consequence you 204 | may not distribute the Program at all. For example, if a patent 205 | license would not permit royalty-free redistribution of the Program by 206 | all those who receive copies directly or indirectly through you, then 207 | the only way you could satisfy both it and this License would be to 208 | refrain entirely from distribution of the Program. 209 | 210 | If any portion of this section is held invalid or unenforceable under 211 | any particular circumstance, the balance of the section is intended to 212 | apply and the section as a whole is intended to apply in other 213 | circumstances. 214 | 215 | It is not the purpose of this section to induce you to infringe any 216 | patents or other property right claims or to contest validity of any 217 | such claims; this section has the sole purpose of protecting the 218 | integrity of the free software distribution system, which is 219 | implemented by public license practices. Many people have made 220 | generous contributions to the wide range of software distributed 221 | through that system in reliance on consistent application of that 222 | system; it is up to the author/donor to decide if he or she is willing 223 | to distribute software through any other system and a licensee cannot 224 | impose that choice. 225 | 226 | This section is intended to make thoroughly clear what is believed to 227 | be a consequence of the rest of this License. 228 | 229 | 8. If the distribution and/or use of the Program is restricted in 230 | certain countries either by patents or by copyrighted interfaces, the 231 | original copyright holder who places the Program under this License 232 | may add an explicit geographical distribution limitation excluding 233 | those countries, so that distribution is permitted only in or among 234 | countries not thus excluded. In such case, this License incorporates 235 | the limitation as if written in the body of this License. 236 | 237 | 9. The Free Software Foundation may publish revised and/or new versions 238 | of the General Public License from time to time. Such new versions will 239 | be similar in spirit to the present version, but may differ in detail to 240 | address new problems or concerns. 241 | 242 | Each version is given a distinguishing version number. If the Program 243 | specifies a version number of this License which applies to it and "any 244 | later version", you have the option of following the terms and conditions 245 | either of that version or of any later version published by the Free 246 | Software Foundation. If the Program does not specify a version number of 247 | this License, you may choose any version ever published by the Free Software 248 | Foundation. 249 | 250 | 10. If you wish to incorporate parts of the Program into other free 251 | programs whose distribution conditions are different, write to the author 252 | to ask for permission. For software which is copyrighted by the Free 253 | Software Foundation, write to the Free Software Foundation; we sometimes 254 | make exceptions for this. Our decision will be guided by the two goals 255 | of preserving the free status of all derivatives of our free software and 256 | of promoting the sharing and reuse of software generally. 257 | 258 | NO WARRANTY 259 | 260 | 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY 261 | FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN 262 | OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES 263 | PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED 264 | OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 265 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS 266 | TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE 267 | PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, 268 | REPAIR OR CORRECTION. 269 | 270 | 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 271 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR 272 | REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, 273 | INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING 274 | OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED 275 | TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY 276 | YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER 277 | PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE 278 | POSSIBILITY OF SUCH DAMAGES. 279 | 280 | END OF TERMS AND CONDITIONS 281 | 282 | How to Apply These Terms to Your New Programs 283 | 284 | If you develop a new program, and you want it to be of the greatest 285 | possible use to the public, the best way to achieve this is to make it 286 | free software which everyone can redistribute and change under these terms. 287 | 288 | To do so, attach the following notices to the program. It is safest 289 | to attach them to the start of each source file to most effectively 290 | convey the exclusion of warranty; and each file should have at least 291 | the "copyright" line and a pointer to where the full notice is found. 292 | 293 | 294 | Copyright (C) 295 | 296 | This program is free software; you can redistribute it and/or modify 297 | it under the terms of the GNU General Public License as published by 298 | the Free Software Foundation; either version 2 of the License, or 299 | (at your option) any later version. 300 | 301 | This program is distributed in the hope that it will be useful, 302 | but WITHOUT ANY WARRANTY; without even the implied warranty of 303 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 304 | GNU General Public License for more details. 305 | 306 | You should have received a copy of the GNU General Public License along 307 | with this program; if not, write to the Free Software Foundation, Inc., 308 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 309 | 310 | Also add information on how to contact you by electronic and paper mail. 311 | 312 | If the program is interactive, make it output a short notice like this 313 | when it starts in an interactive mode: 314 | 315 | Gnomovision version 69, Copyright (C) year name of author 316 | Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 317 | This is free software, and you are welcome to redistribute it 318 | under certain conditions; type `show c' for details. 319 | 320 | The hypothetical commands `show w' and `show c' should show the appropriate 321 | parts of the General Public License. Of course, the commands you use may 322 | be called something other than `show w' and `show c'; they could even be 323 | mouse-clicks or menu items--whatever suits your program. 324 | 325 | You should also get your employer (if you work as a programmer) or your 326 | school, if any, to sign a "copyright disclaimer" for the program, if 327 | necessary. Here is a sample; alter the names: 328 | 329 | Yoyodyne, Inc., hereby disclaims all copyright interest in the program 330 | `Gnomovision' (which makes passes at compilers) written by James Hacker. 331 | 332 | , 1 April 1989 333 | Ty Coon, President of Vice 334 | 335 | This General Public License does not permit incorporating your program into 336 | proprietary programs. If your program is a subroutine library, you may 337 | consider it more useful to permit linking proprietary applications with the 338 | library. If this is what you want to do, use the GNU Lesser General 339 | Public License instead of this License. 340 | --------------------------------------------------------------------------------