├── .gitignore ├── .gitmodules ├── LICENSE ├── Makefile ├── README.md ├── blinky-diffclk.v ├── blinky-genesys2.xdc ├── blinky-qmtech-zyjzgw.xdc ├── blinky-qmtech.xdc ├── blinky-stlv7325.xdc └── blinky.v /.gitignore: -------------------------------------------------------------------------------- 1 | *.bit 2 | *.fasm 3 | *.frames 4 | *.json 5 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "nextpnr-xilinx"] 2 | path = nextpnr-xilinx 3 | url = git@github.com:kintex-chatter/nextpnr-xilinx.git 4 | branch = iob18-trial 5 | [submodule "prjxray"] 6 | path = prjxray 7 | url = git@github.com:kintex-chatter/prjxray.git 8 | [submodule "db-workspace-for-kintex7"] 9 | path = db-workspace-for-kintex7 10 | url = git@github.com:kintex-chatter/db-workspace-for-kintex7.git 11 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2022, Hans Baier 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | 1. Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | 2. Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | 3. Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME ?= blinky 2 | PREFIX ?= ${HOME}/opt 3 | DB_DIR = ${PREFIX}/nextpnr/prjxray-db 4 | CHIPDB_DIR = ${PREFIX}/nextpnr/xilinx-chipdb 5 | XRAY_DIR ?= ${PREFIX}/prjxray 6 | XRAY_UTILS_DIR = ${PWD}/prjxray/env/bin 7 | XRAY_TOOLS_DIR = ${XRAY_DIR}/bin 8 | NEXTPNR_DIR ?= ${PREFIX}/nextpnr 9 | SHELL = /bin/bash 10 | PYTHONPATH ?= ${XRAY_DIR} 11 | QMTECH_CABLE ?= tigard 12 | STLV_CABLE ?= tigard 13 | JOBS ?= 4 14 | 15 | # This workaround is only required for macOS, because Apple has explicitly disabled OpenMP support in their compilers. 16 | ifeq ($(shell uname -s),Darwin) 17 | NEXTPNR_BUILD_ENV = env CC=/usr/local/opt/llvm/bin/clang CXX=/usr/local/opt/llvm/bin/clang++ LDFLAGS="-L/usr/local/opt/llvm/lib -Wl,-rpath,/usr/local/opt/llvm/lib" 18 | NEXTPNR_CMAKE_FLAGS = -DBUILD_GUI=0 19 | endif 20 | 21 | ifeq (${BOARD}, qmtech) 22 | PART = xc7k325tffg676-1 23 | PROG = openFPGALoader --cable ${QMTECH_CABLE} --board qmtechKintex7 --bitstream ${PROJECT_NAME}-${BOARD}.bit 24 | else ifeq (${BOARD}, genesys2) 25 | PART = xc7k325tffg900-2 26 | CLK = -diffclk 27 | PROG = openFPGALoader --board genesys2 --bitstream ${PROJECT_NAME}-${BOARD}.bit 28 | else ifeq (${BOARD}, stlv7325) 29 | PART = xc7k325tffg676-1 30 | CLK = -diffclk 31 | PROG = openFPGALoader --cable ${STLV_CABLE} --bitstream ${PROJECT_NAME}-${BOARD}.bit 32 | else 33 | .PHONY: check 34 | check: 35 | @echo "BOARD environment variable not set. Available boards:" 36 | @echo " * qmtech" 37 | @echo " * genesys2" 38 | @echo " * stlv7325" 39 | @exit 1 40 | endif 41 | 42 | .PHONY: all 43 | all: ${PROJECT_NAME}-${BOARD}.bit 44 | ${PROG} 45 | 46 | ${PROJECT_NAME}.json: ${PROJECT_NAME}${CLK}.v 47 | yosys -p "synth_xilinx -flatten -abc9 -nobram -arch xc7 -top ${PROJECT_NAME}; write_json ${PROJECT_NAME}.json" $< 48 | 49 | ${PROJECT_NAME}-${BOARD}.fasm: ${PROJECT_NAME}.json 50 | ${NEXTPNR_DIR}/bin/nextpnr-xilinx --chipdb ${CHIPDB_DIR}/${PART}.bin --xdc ${PROJECT_NAME}-${BOARD}.xdc --json $< --write ${PROJECT_NAME}-${BOARD}-routed.json --fasm $@ --verbose --debug 51 | 52 | ${PROJECT_NAME}-${BOARD}.frames: ${PROJECT_NAME}-${BOARD}.fasm 53 | ${XRAY_UTILS_DIR}/fasm2frames --part ${PART} --db-root ${DB_DIR}/kintex7 $< > $@ 54 | 55 | ${PROJECT_NAME}-${BOARD}.bit: ${PROJECT_NAME}-${BOARD}.frames 56 | ${XRAY_TOOLS_DIR}/xc7frames2bit --part_file ${DB_DIR}/kintex7/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@ 57 | 58 | .PHONY: setup 59 | setup: 60 | ifeq (${PART},) 61 | make check 62 | endif 63 | cp -rv db-workspace-for-kintex7/* nextpnr-xilinx/xilinx/external/prjxray-db/kintex7 64 | ${NEXTPNR_BUILD_ENV} cmake -S nextpnr-xilinx -B nextpnr-xilinx/build ${NEXTPNR_CMAKE_FLAGS} -DARCH=xilinx -DCMAKE_INSTALL_PREFIX=${NEXTPNR_DIR} 65 | make -C nextpnr-xilinx/build -j${JOBS} all 66 | make -C nextpnr-xilinx/build install 67 | if [ ! -f nextpnr-xilinx/xilinx/${PART}.bba ] ; then \ 68 | cd nextpnr-xilinx ; \ 69 | python3 xilinx/python/bbaexport.py --device ${PART} --bba xilinx/${PART}.bba ; \ 70 | fi 71 | if [ ! -f nextpnr-xilinx/xilinx/${PART}.bin ] ; then \ 72 | cd nextpnr-xilinx ; \ 73 | build/bbasm -l xilinx/${PART}.bba xilinx/${PART}.bin ; \ 74 | fi 75 | if [ ! -f ${NEXTPNR_DIR}/xilinx-chipdb/${PART}.bin ] ; then \ 76 | mkdir -p ${NEXTPNR_DIR}/xilinx-chipdb ; \ 77 | cp nextpnr-xilinx/xilinx/${PART}.bin ${NEXTPNR_DIR}/xilinx-chipdb/ ; \ 78 | fi 79 | if [ ! -e ${NEXTPNR_DIR}/prjxray-db ] ; then \ 80 | ln -s ${PWD}/nextpnr-xilinx/xilinx/external/prjxray-db ${NEXTPNR_DIR}/ ; \ 81 | fi 82 | cmake -S prjxray -B prjxray/build -DCMAKE_INSTALL_PREFIX=${XRAY_DIR} 83 | make -j${JOBS} -C prjxray/build 84 | make -j${JOBS} -C prjxray/build install 85 | make -j${JOBS} -C prjxray env 86 | 87 | .PHONY: clean 88 | clean: 89 | @rm -f *.bit 90 | @rm -f *.frames 91 | @rm -f *.fasm 92 | @rm -f *.json 93 | 94 | .PHONY: clobber 95 | clobber: 96 | rm -rf nextpnr-xilinx/build 97 | rm -rf prjxray/build 98 | rm -rf prjxray/env 99 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Full Open Source Blinky on XC7K325T using yosys+nextpnr-xilinx 2 | 3 | *NOTE*: This repository is now somewhat obsolete: 4 | 5 | Since the creation of the [toolchain installer](https://github.com/kintex-chatter/toolchain-installer), the 6 | `Makefile` used here will not work probably with the snap-packaged toolchain, 7 | because the `Makefile` here builds and installs its own toolchain instead in different directories. 8 | 9 | For examples of `Makefile`s using the packaged toolchain, see [demo-projects](https://github.com/kintex-chatter/demo-projects) 10 | 11 | ## Blinky on QMTech XC7K325T Core Board (xc7k325tffg676-1) 12 | ![qmtech_blinky](https://user-images.githubusercontent.com/89043237/152394699-52cf5a22-5fd6-45b6-b9a2-3d2ca89d1fd0.gif) 13 | - For guide to reproduce see list below 14 | - Full size video: [https://user-images.githubusercontent.com/148607/152079511-89539119-5d66-42f2-a709-3e35a81d7c0f.mp4] 15 | - Large image: https://user-images.githubusercontent.com/148607/152079663-e42ce6ed-66ef-461e-aed7-82a4e5667e39.png 16 | 17 | ## Blinky on Digilent Genesys2 (xc7k325tffg900-2) 18 | ![genesys2_blinky](https://user-images.githubusercontent.com/89043237/152396095-bc4dc672-1c3f-4a6a-8477-e953363d0f2f.gif) 19 | - For proof of concept see branch *ring-oscillator* 20 | - Full size video: https://user-images.githubusercontent.com/20798131/152385360-3e4f140e-cb57-4b04-bbc3-1ecd1d7374d5.mov 21 | - Stable operation possible with external "PMOD" type oscillator module 22 | - *Breaking:* Should now work with the default clock. Unfortunately I don't have the board, so please test if you have it and let us know! 23 | 24 | ## Blinky on the AliExpress STLV7325 board 25 | ![stlv7325_blinky](https://user-images.githubusercontent.com/148607/176102441-4fe2065f-4963-46c2-92b8-d6a5873fc28b.gif) 26 | - works with differential clock input on the high performance banks 27 | 28 | # Status 29 | * works on the QMTech XC7K325T board 30 | * works with differential clock input on the high performance banks on the STLV7325 board. 31 | * limited functionality on Digilent Genesys2 and [Memblaze PBlaze 3 SSD](https://github.com/kintex-chatter/xc7k325t-blinky-nextpnr/issues/12) 32 | 33 | # How to reproduce 34 | 1. Install required software 35 | - sudo apt install libftdi1-dev libudev-dev git cmake build-essential tclsh clang tcl-dev libreadline-dev flex bison python3-dev libboost-all-dev libqt5-base-dev-tools libeigen3-dev python3 python3-pip python3-yaml pypy3 pkg-config libqt5opengl5-dev 36 | - clone/build/install yosys from https://github.com/YosysHQ/yosys or download a release from https://github.com/YosysHQ/oss-cad-suite-build/releases 37 | note: test have been performed with Yosys 0.13+28 (git sha1 bf85dfee5, gcc 10.2.1-6 -fPIC -Os) 38 | 2. git clone --recurse-submodules https://github.com/kintex-chatter/xc7k325t-blinky-nextpnr.git 39 | 3. cd xc7k325t-blinky-nextpnr 40 | 4. make BOARD=qmtech setup 41 | 5. make BOARD=qmtech all 42 | 43 | Note: Every time you change the installation of nextpnr-xilinx you will have to regenerate the chipdb, 44 | because the chipdb does not seem to be compatible between different binaries of nextpnr-xilinx 45 | -------------------------------------------------------------------------------- /blinky-diffclk.v: -------------------------------------------------------------------------------- 1 | `default_nettype none //do not allow undeclared wires 2 | 3 | module blinky ( 4 | input wire clk_p, 5 | input wire clk_n, 6 | output wire led 7 | ); 8 | 9 | wire clk_ibufg; 10 | wire clk; 11 | 12 | IBUFDS ibuf_inst (.I(clk_p), .IB(clk_n), .O(clk_ibufg)); 13 | BUFG bufg_inst (.I(clk_ibufg), .O(clk)); 14 | 15 | reg [24:0] r_count = 0; 16 | 17 | always @(posedge(clk)) r_count <= r_count + 1; 18 | 19 | assign led = r_count[24]; 20 | endmodule 21 | -------------------------------------------------------------------------------- /blinky-genesys2.xdc: -------------------------------------------------------------------------------- 1 | set_property LOC AD12 [get_ports clk_p] 2 | set_property IOSTANDARD LVDS [get_ports {clk_p}] 3 | 4 | set_property LOC AD11 [get_ports clk_n] 5 | set_property IOSTANDARD LVDS [get_ports {clk_n}] 6 | 7 | set_property LOC T28 [get_ports led] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {led}] 9 | -------------------------------------------------------------------------------- /blinky-qmtech-zyjzgw.xdc: -------------------------------------------------------------------------------- 1 | set_property LOC F22 [get_ports clk] 2 | set_property IOSTANDARD LVCMOS33 [get_ports {clk}] 3 | 4 | ##### Daughter board LEDs ##### 5 | 6 | # LED3_FPGA BANK14_E25 7 | set_property LOC E25 [get_ports led] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {led}] 9 | 10 | # LED4_FPGA BANK16_C14 11 | # set_property LOC C14 [get_ports led] 12 | # set_property IOSTANDARD LVCMOS33 [get_ports {led}] 13 | 14 | # LED5_FPGA BANK16_B14 15 | # set_property LOC B14 [get_ports led] 16 | # set_property IOSTANDARD LVCMOS33 [get_ports {led}] 17 | -------------------------------------------------------------------------------- /blinky-qmtech.xdc: -------------------------------------------------------------------------------- 1 | set_property LOC F22 [get_ports clk] 2 | set_property IOSTANDARD LVCMOS33 [get_ports {clk}] 3 | 4 | set_property LOC J26 [get_ports led] 5 | set_property IOSTANDARD LVCMOS33 [get_ports {led}] 6 | -------------------------------------------------------------------------------- /blinky-stlv7325.xdc: -------------------------------------------------------------------------------- 1 | # (ab)use the single ended 60MHz clock from the ULPI PHY 2 | set_property LOC AB11 [get_ports clk_p] 3 | set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk_p}] 4 | 5 | set_property LOC AC11 [get_ports clk_n] 6 | set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk_n}] 7 | 8 | set_property LOC AA2 [get_ports led] 9 | set_property IOSTANDARD LVCMOS15 [get_ports {led}] 10 | -------------------------------------------------------------------------------- /blinky.v: -------------------------------------------------------------------------------- 1 | `default_nettype none //do not allow undeclared wires 2 | 3 | module blinky ( 4 | input wire clk, 5 | output wire led 6 | ); 7 | 8 | reg [24:0] r_count = 0; 9 | 10 | always @(posedge(clk)) r_count <= r_count + 1; 11 | 12 | assign led = r_count[24]; 13 | endmodule 14 | --------------------------------------------------------------------------------