├── LICENSE ├── README.md ├── rtl ├── .gitkeep ├── ctrl_engine.v ├── dp_ram.v ├── dp_ram_regout.v ├── fe_buf.v ├── olp_buf.v ├── param_buf.v ├── pe_array │ ├── pe.v │ ├── pe2.v │ ├── pe_array.v │ └── pe_ic.v ├── pu │ ├── pu_adder2.v │ ├── pu_adder4.v │ ├── pu_bias_add_pipe1.v │ ├── pu_hbm_pipe.v │ ├── pu_ic_add_pipe0.v │ ├── pu_lbm_pipe.v │ ├── pu_mul.v │ ├── pu_relu_mul_pipe2.v │ ├── pu_requant_pipe4.v │ ├── pu_resi_add_pipe_p3.v │ └── pu_top.v ├── res_buf.v ├── sch │ ├── addr_if.v │ ├── handshake_sche2pe.v │ ├── sche_sub.v │ └── scheduler.v ├── top.v └── wt_buf.v └── sim ├── .gitkeep ├── flist └── filelist.f ├── tb ├── tb_addr_if.v ├── tb_ctrl_engine.sv ├── tb_ppp.sv ├── tb_scheduler.sv ├── tb_scheduler.v ├── tb_top.sv └── tb_top_switch.sv ├── tv ├── dndm │ ├── fe_buf.txt │ ├── layer1.txt │ ├── layer2.txt │ ├── layer3.txt │ ├── layer4.txt │ ├── layer4_resi.txt │ ├── layer5.txt │ ├── param_buf.txt │ └── wt_buf.txt ├── reg.txt └── sr │ ├── fe_buf.txt │ ├── layer1.txt │ ├── layer2.txt │ ├── layer3.txt │ ├── layer4.txt │ ├── layer5.txt │ ├── param_buf.txt │ └── wt_buf.txt └── work └── makefile /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2024 OpenASIC 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # xkDLA 2 | XinKai Deep Learning Accelerator 3 | 4 | xkDLA 是面向AI-ISP的轻量化DLA数据流处理器，它由[复旦大学](http://fudan.edu.cn/)[专用集成电路与系统国家重点实验室](http://sme.fudan.edu.cn/)（State Key Lab of ASIC & System，Fudan University）[视频图像处理器实验室](http://viplab.fudan.edu.cn)（Video&Image Processor, VIP Lab）[范益波](https://sme.fudan.edu.cn/info/detail?id=132)教授研究团队开发完成，并开放源代码。任何组织个人可以无偿使用上述代码用于研究和生产目的，VIP Lab将会持续更新并维护xkDLA的开发。 5 | 6 | > ### 关于VIP Lab 7 | 8 | 复旦大学VIP实验室专注于从事下一代视频、图像硬件处器研究，包括超高清视频编码器（H.264/H.265 Video Encoder IP），图像去雾（Dehazing）处理器，双目视觉处理器（Stereo Matching），深度学习加速器（Deep Learning Accelerator）等。 9 | 实验室网站 http://viplab.fudan.edu.cn 10 | 11 | > ### 项目论坛 12 | 13 | http://www.openasic.org -------------------------------------------------------------------------------- /rtl/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/openasic-org/xkDLA/bed44c45b0e9e4f0049bfef0bcc29a04522ca584/rtl/.gitkeep -------------------------------------------------------------------------------- /rtl/ctrl_engine.v: -------------------------------------------------------------------------------- 1 | /* 2 | Top Module: control.v 3 | Author: Hao Zhang 4 | Time: 202307 5 | */ 6 | 7 | module ctrl_engine #( 8 | parameter REG_IFMH_WIDTH = 10 , 9 | parameter REG_IFMW_WIDTH = 10 , 10 | parameter REG_TILEH_WIDTH = 6 , 11 | parameter REG_TNY_WIDTH = 6 , 12 | parameter REG_TNX_WIDTH = 6 , 13 | parameter REG_TLW_WIDTH = 6 , 14 | parameter REG_TLH_WIDTH = 6 , 15 | parameter TILE_BASE_W = 32 , 16 | parameter REG_IH_WIDTH = 6 , 17 | parameter REG_OH_WIDTH = 6 , 18 | parameter REG_IW_WIDTH = 6 , 19 | parameter REG_OW_WIDTH = 6 , 20 | parameter REG_IC_WIDTH = 6 , 21 | parameter REG_OC_WIDTH = 6 , 22 | parameter REG_AF_WIDTH = 1 , 23 | parameter REG_HBM_SFT_WIDTH = 6 , 24 | parameter REG_LBM_SFT_WIDTH = 6 25 | ) 26 | ( 27 | input wire clk , 28 | input wire rst_n , 29 | input wire [ 32 - 1 : 0] ctrl_reg , 30 | output reg [ 32 - 1 : 0] state_reg , 31 | input wire [ 32 - 1 : 0] reg0 , 32 | input wire [ 32 - 1 : 0] reg1 , 33 | input wire layer_done , 34 | output wire layer_start , 35 | output wire [ 1 : 0] stat_ctrl , 36 | output reg [ 2 : 0] cnt_layer , 37 | output reg tile_switch_r , // layer active high 38 | output reg model_switch_r , // tile active high 39 | output wire tile_switch , // pulse @negedge tile_switch_r 40 | output wire model_switch , // pulse @negedge model_switch_r 41 | output wire model_switch_layer , // layer active high, last layer in model_switch_r tile 42 | output reg nn_proc , // 0-dndm 1-sr 43 | output wire [ REG_TNX_WIDTH - 1 : 0] tile_tot_num_x , 44 | output wire [ REG_IH_WIDTH - 1 : 0] tile_in_h , 45 | output wire [ REG_OH_WIDTH - 1 : 0] tile_out_h , 46 | output wire [ REG_IW_WIDTH - 1 : 0] tile_in_w , 47 | output wire [ REG_OW_WIDTH - 1 : 0] tile_out_w , 48 | output wire [ REG_IC_WIDTH - 1 : 0] tile_in_c , 49 | output wire [ REG_OC_WIDTH - 1 : 0] tile_out_c , 50 | output wire [ 2 : 0] ksize , 51 | output wire [ 2 : 0] ksize_nxt , 52 | output wire [ 3 : 0] tile_loc , 53 | output wire x4_shuffle_vld , 54 | output wire [ REG_AF_WIDTH - 1 : 0] prl_vld , 55 | output wire [ 1 : 0] res_proc_type , 56 | output wire [ REG_HBM_SFT_WIDTH - 1 : 0] pu_hbm_shift , 57 | output wire [ REG_LBM_SFT_WIDTH - 1 : 0] pu_lbm_shift , 58 | output reg buf_pp_flag 59 | ); 60 | 61 | wire [ REG_IFMH_WIDTH - 1 : 0] ifm_h ; 62 | wire [ REG_IFMW_WIDTH - 1 : 0] ifm_w ; 63 | wire [ REG_TILEH_WIDTH - 1 : 0] tile_base_h ; 64 | wire [ REG_TNY_WIDTH - 1 : 0] tile_tot_num_y ; 65 | wire [ REG_TLW_WIDTH - 1 : 0] tile_last_w ; 66 | wire [ REG_TLH_WIDTH - 1 : 0] tile_last_h ; 67 | wire [REG_HBM_SFT_WIDTH - 1 : 0] pu_hbm_shift_dndm ; 68 | wire [REG_HBM_SFT_WIDTH - 1 : 0] pu_hbm_shift_sr ; 69 | wire [REG_LBM_SFT_WIDTH - 1 : 0] pu_lbm_shift_dndm ; 70 | wire [REG_LBM_SFT_WIDTH - 1 : 0] pu_lbm_shift_sr ; 71 | reg [ REG_TNY_WIDTH - 1 : 0] tile_cnt_y_0 ; //dndm 72 | reg [ REG_TNX_WIDTH - 1 : 0] tile_cnt_x_0 ; //dndm 73 | reg [ REG_TNY_WIDTH - 1 : 0] tile_cnt_y_1 ; //sr 74 | reg [ REG_TNX_WIDTH - 1 : 0] tile_cnt_x_1 ; //sr 75 | reg layer_start_d ; 76 | reg tile_switch_r_d ; 77 | reg model_switch_r_d ; 78 | 79 | assign stat_ctrl = ctrl_reg[1:0] ; 80 | assign ifm_h = reg0[9:0] ; 81 | assign ifm_w = reg0[19:10] ; 82 | assign tile_base_h = reg1[5:0] ; 83 | assign tile_tot_num_y = reg1[11:6] ; 84 | assign tile_tot_num_x = reg1[17:12] ; 85 | assign tile_last_w = reg1[23:18] ; 86 | assign tile_last_h = reg1[29:24] ; 87 | assign layer_start = layer_start_d ; 88 | assign tile_switch = (~tile_switch_r) & tile_switch_r_d ; 89 | assign model_switch = (~model_switch_r) & model_switch_r_d ; 90 | assign ksize = (cnt_layer == 1 || cnt_layer == 5) ? 'd5 : 'd3 ; 91 | assign ksize_nxt = (cnt_layer == 4 || cnt_layer == 5) ? 'd5 : 'd3 ; 92 | assign x4_shuffle_vld = (nn_proc == 1 && cnt_layer == 5) ? 1'b0 : 1'b0 ; 93 | assign prl_vld = (cnt_layer == 5) ? 1'b0 : 1'b1 ; 94 | assign res_proc_type = (cnt_layer == 1) ? 2'b01 : 95 | (cnt_layer == 4) ? 2'b10 : 2'b00 ; 96 | assign model_switch_layer = (cnt_layer == 5) && model_switch_r ; 97 | assign tile_loc[3] = (nn_proc == 0 && tile_cnt_x_0 == 0) || (nn_proc == 1 && tile_cnt_x_1 == 0) ; //left 98 | assign tile_loc[2] = (nn_proc == 0 && tile_cnt_x_0 == tile_tot_num_x - 1) || (nn_proc == 1 && tile_cnt_x_1 == tile_tot_num_x - 1) ; //right 99 | assign tile_loc[1] = (nn_proc == 0 && tile_cnt_y_0 == 0) || (nn_proc == 1 && tile_cnt_y_1 == 0) ; //top 100 | assign tile_loc[0] = (nn_proc == 0 && tile_cnt_y_0 == tile_tot_num_y - 1) || (nn_proc == 1 && tile_cnt_y_1 == tile_tot_num_y - 1) ; //bottom 101 | 102 | assign pu_hbm_shift_dndm = (cnt_layer == 1) ? 'h18 : 103 | (cnt_layer == 2) || (cnt_layer == 3) || (cnt_layer == 4) ? 'h16 :'h19 ; 104 | 105 | //assign pu_hbm_shift_sr = (cnt_layer == 1 || cnt_layer == 2 || cnt_layer == 3) ? 'h17 : 106 | // (cnt_layer == 4) ? 'h15 : 'h19 ; 107 | reg [REG_HBM_SFT_WIDTH - 1 : 0] pu_hbm_shift_sr_comb ; 108 | always @(cnt_layer)begin 109 | case(cnt_layer) 110 | 3'd1:pu_hbm_shift_sr_comb = 'h16; 111 | 3'd2:pu_hbm_shift_sr_comb = 'h15; 112 | 3'd3:pu_hbm_shift_sr_comb = 'h16; 113 | 3'd4:pu_hbm_shift_sr_comb = 'h14; 114 | 3'd5:pu_hbm_shift_sr_comb = 'h15; 115 | default:pu_hbm_shift_sr_comb ='h0; 116 | endcase 117 | end 118 | 119 | assign pu_hbm_shift_sr = pu_hbm_shift_sr_comb ; 120 | assign pu_hbm_shift = nn_proc ? pu_hbm_shift_sr : pu_hbm_shift_dndm ; 121 | 122 | assign pu_lbm_shift_dndm = 'h10 ; 123 | assign pu_lbm_shift_sr = 'h11 ; 124 | assign pu_lbm_shift = nn_proc ? pu_lbm_shift_sr : pu_lbm_shift_dndm ; 125 | 126 | assign tile_in_c = (nn_proc == 0 && cnt_layer == 1) ? 'd3 : 127 | (nn_proc == 1 && cnt_layer == 1) ? 'd1 : 'd16 ; 128 | assign tile_out_c = (nn_proc == 0 && cnt_layer == 5) ? 'd3 : 'd16 ; 129 | assign tile_in_w = (tile_loc[3] == 1) ? ((cnt_layer == 1) ? TILE_BASE_W : 130 | (cnt_layer == 2) ? TILE_BASE_W - 2 : 131 | (cnt_layer == 3) ? TILE_BASE_W - 3 : 132 | (cnt_layer == 4) ? TILE_BASE_W - 4 : TILE_BASE_W - 5) : 133 | (tile_loc[2] == 1) ? ((cnt_layer == 1) ? tile_last_w : 134 | (cnt_layer == 2) ? tile_last_w + 2 : 135 | (cnt_layer == 3) ? tile_last_w + 3 : 136 | (cnt_layer == 4) ? tile_last_w + 4 : tile_last_w + 5) : TILE_BASE_W; 137 | assign tile_out_w = (tile_loc[3] == 1) ? ((cnt_layer == 1) ? TILE_BASE_W - 2 : 138 | (cnt_layer == 2) ? TILE_BASE_W - 3 : 139 | (cnt_layer == 3) ? TILE_BASE_W - 4 : 140 | (cnt_layer == 4) ? TILE_BASE_W - 5 : TILE_BASE_W - 7) : 141 | (tile_loc[2] == 1) ? ((cnt_layer == 1) ? tile_last_w + 2 : 142 | (cnt_layer == 2) ? tile_last_w + 3 : 143 | (cnt_layer == 3) ? tile_last_w + 4 : 144 | (cnt_layer == 4) ? tile_last_w + 5 : tile_last_w + 7) : TILE_BASE_W; 145 | assign tile_in_h = (tile_loc[1] == 1) ? ((cnt_layer == 1) ? tile_base_h : 146 | (cnt_layer == 2) ? tile_base_h - 2 : 147 | (cnt_layer == 3) ? tile_base_h - 3 : 148 | (cnt_layer == 4) ? tile_base_h - 4 : tile_base_h - 5) : 149 | (tile_loc[0] == 1) ? ((cnt_layer == 1) ? tile_last_h : 150 | (cnt_layer == 2) ? tile_last_h + 2 : 151 | (cnt_layer == 3) ? tile_last_h + 3 : 152 | (cnt_layer == 4) ? tile_last_h + 4 : tile_last_h + 5) : tile_base_h; 153 | assign tile_out_h = (tile_loc[1] == 1) ? ((cnt_layer == 1) ? tile_base_h - 2 : 154 | (cnt_layer == 2) ? tile_base_h - 3 : 155 | (cnt_layer == 3) ? tile_base_h - 4 : 156 | (cnt_layer == 4) ? tile_base_h - 5 : tile_base_h - 7) : 157 | (tile_loc[0] == 1) ? ((cnt_layer == 1) ? tile_last_h + 2 : 158 | (cnt_layer == 2) ? tile_last_h + 3 : 159 | (cnt_layer == 3) ? tile_last_h + 4 : 160 | (cnt_layer == 4) ? tile_last_h + 5 : tile_last_h + 7) : tile_base_h; 161 | 162 | always@(posedge clk or negedge rst_n)begin 163 | if(!rst_n) 164 | tile_cnt_x_0 <= 0; 165 | else if(nn_proc == 0 && layer_done && tile_switch_r) 166 | tile_cnt_x_0 <= (tile_cnt_x_0 == tile_tot_num_x - 1) ? 0 : tile_cnt_x_0 + 1; 167 | else 168 | tile_cnt_x_0 <= tile_cnt_x_0; 169 | end 170 | 171 | always@(posedge clk or negedge rst_n)begin 172 | if(!rst_n) 173 | tile_cnt_y_0 <= 0; 174 | else if(nn_proc == 0 && layer_done && tile_switch_r) 175 | tile_cnt_y_0 <= (tile_cnt_x_0 == tile_tot_num_x - 1) ? tile_cnt_y_0 + 1 : tile_cnt_y_0; 176 | else 177 | tile_cnt_y_0 <= tile_cnt_y_0; 178 | end 179 | 180 | always@(posedge clk or negedge rst_n)begin 181 | if(!rst_n) 182 | tile_cnt_x_1 <= 0; 183 | else if(nn_proc == 1 && layer_done && tile_switch_r) 184 | tile_cnt_x_1 <= (tile_cnt_x_1 == tile_tot_num_x - 1) ? 0 : tile_cnt_x_1 + 1; 185 | else 186 | tile_cnt_x_1 <= tile_cnt_x_1; 187 | end 188 | 189 | always@(posedge clk or negedge rst_n)begin 190 | if(!rst_n) 191 | tile_cnt_y_1 <= 0; 192 | else if(nn_proc == 1 && layer_done && tile_switch_r) 193 | tile_cnt_y_1 <= (tile_cnt_x_1 == tile_tot_num_x - 1) ? tile_cnt_y_1 + 1 : tile_cnt_y_1; 194 | else 195 | tile_cnt_y_1 <= tile_cnt_y_1; 196 | end 197 | 198 | always@(posedge clk or negedge rst_n)begin 199 | if(!rst_n) 200 | tile_switch_r <= 0; 201 | else if(layer_done && cnt_layer == 4) 202 | tile_switch_r <= 1; 203 | else if(layer_done && cnt_layer == 5) 204 | tile_switch_r <= 0; 205 | else 206 | tile_switch_r <= tile_switch_r; 207 | end 208 | 209 | always@(posedge clk or negedge rst_n)begin 210 | if(!rst_n) 211 | model_switch_r <= 0; 212 | else if(layer_done && cnt_layer == 5 && (((tile_cnt_x_0 == tile_tot_num_x - 2) && ((tile_cnt_y_0[0] == 1) || (tile_cnt_y_0 == tile_tot_num_y - 1))) || ((tile_cnt_x_1 == tile_tot_num_x - 2) && ((tile_cnt_y_1[0] == 1) || (tile_cnt_y_1 == tile_tot_num_y - 1))))) 213 | model_switch_r <= 1; 214 | else if(layer_done && cnt_layer == 5 && (((tile_cnt_x_0 == tile_tot_num_x - 1) && ((tile_cnt_y_0[0] == 1) || (tile_cnt_y_0 == tile_tot_num_y - 1))) || ((tile_cnt_x_1 == tile_tot_num_x - 1) && ((tile_cnt_y_1[0] == 1) || (tile_cnt_y_1 == tile_tot_num_y - 1))))) 215 | model_switch_r <= 0; 216 | else 217 | model_switch_r <= model_switch_r; 218 | end 219 | 220 | always@(posedge clk or negedge rst_n)begin 221 | if(!rst_n) 222 | layer_start_d <= 0; 223 | else if(cnt_layer == 5 && tile_cnt_x_1 == tile_tot_num_x - 1 && tile_cnt_y_1 == tile_tot_num_y - 1) 224 | layer_start_d <= 0; 225 | else 226 | layer_start_d <= (ctrl_reg[1:0] == 2'b11) || layer_done; 227 | end 228 | 229 | always@(posedge clk or negedge rst_n)begin 230 | if(!rst_n)begin 231 | tile_switch_r_d <= 0; 232 | model_switch_r_d <= 0; 233 | end 234 | else begin 235 | tile_switch_r_d <= tile_switch_r; 236 | model_switch_r_d <= model_switch_r; 237 | end 238 | end 239 | 240 | always@(posedge clk or negedge rst_n)begin //layer_cnt 1 ~ 5 241 | if(!rst_n) 242 | cnt_layer <= 1; 243 | else if(layer_done && tile_switch_r) 244 | cnt_layer <= 1; 245 | else if(layer_done && !tile_switch_r) 246 | cnt_layer <= cnt_layer + 1; 247 | else 248 | cnt_layer <= cnt_layer; 249 | end 250 | 251 | always@(posedge clk or negedge rst_n)begin 252 | if(!rst_n) 253 | nn_proc <= 0; 254 | else if(layer_done && model_switch_layer) 255 | nn_proc <= ~nn_proc; 256 | else 257 | nn_proc <= nn_proc; 258 | end 259 | //modify when tb 260 | /* 261 | always@(posedge clk or negedge rst_n)begin 262 | if(!rst_n) 263 | nn_proc <= 0; 264 | else if(layer_done && model_switch_layer) 265 | nn_proc <= 1; 266 | else 267 | nn_proc <= 1; 268 | end*/ 269 | // top dla fsm 270 | localparam IDLE = 1'b0; 271 | localparam CMPT = 1'b1; 272 | 273 | reg cur_state; 274 | reg next_state; 275 | 276 | always@(posedge clk or negedge rst_n)begin 277 | if(!rst_n) 278 | cur_state <= IDLE; 279 | else 280 | cur_state <= next_state; 281 | end 282 | 283 | always@(*)begin 284 | case(cur_state) 285 | IDLE:begin 286 | if(ctrl_reg[1:0] == 2'b11) 287 | next_state = CMPT; 288 | else 289 | next_state = IDLE; 290 | end 291 | CMPT:begin 292 | if(ctrl_reg[1:0] == 2'b01 || ((tile_cnt_x_1 == tile_tot_num_x - 1) && (tile_cnt_y_1 == tile_tot_num_y - 1) && (cnt_layer == 5) && layer_done)) 293 | next_state = IDLE; 294 | else 295 | next_state = CMPT; 296 | end 297 | default: 298 | next_state = IDLE; 299 | endcase 300 | end 301 | 302 | always@(posedge clk or negedge rst_n)begin 303 | if(!rst_n) 304 | state_reg[1:0] <= 2'b01; 305 | else 306 | case(next_state) 307 | IDLE:begin 308 | state_reg[1:0] <= 2'b01; 309 | end 310 | CMPT:begin 311 | state_reg[1:0] <= 2'b11; 312 | end 313 | default:begin 314 | state_reg[1:0] <= 2'b01; 315 | end 316 | endcase 317 | end 318 | 319 | // weight & param buf ping-pong fsm 320 | localparam A0 = 2'b00; 321 | localparam SP0_A1 = 2'b01; 322 | localparam A0_SP1 = 2'b11; 323 | 324 | reg [1:0] cur_state_0; 325 | reg [1:0] next_state_0; 326 | 327 | always@(posedge clk or negedge rst_n)begin 328 | if(!rst_n) 329 | cur_state_0 <= A0; 330 | else 331 | cur_state_0 <= next_state_0; 332 | end 333 | 334 | always@(*)begin 335 | case(cur_state_0) 336 | A0:begin 337 | if(stat_ctrl == 2'b10) 338 | next_state_0 = SP0_A1; 339 | else 340 | next_state_0 = A0; 341 | end 342 | SP0_A1:begin 343 | if(layer_done && model_switch_layer) 344 | next_state_0 = A0_SP1; 345 | else 346 | next_state_0 = SP0_A1; 347 | end 348 | A0_SP1:begin 349 | if(layer_done && model_switch_layer) 350 | next_state_0 = SP0_A1; 351 | else 352 | next_state_0 = A0_SP1; 353 | end 354 | default: 355 | next_state_0 = A0; 356 | endcase 357 | end 358 | 359 | always@(posedge clk or negedge rst_n)begin 360 | if(!rst_n) 361 | buf_pp_flag <= 0; 362 | else begin 363 | case(cur_state_0) 364 | A0: 365 | buf_pp_flag <= 0; 366 | SP0_A1: 367 | buf_pp_flag <= 1; 368 | A0_SP1: 369 | buf_pp_flag <= 0; 370 | default: 371 | buf_pp_flag <= 0; 372 | endcase 373 | end 374 | end 375 | 376 | endmodule -------------------------------------------------------------------------------- /rtl/dp_ram.v: -------------------------------------------------------------------------------- 1 | module dp_ram #( 2 | parameter ADDR_WIDTH = 10, 3 | parameter DATA_WIDTH = 256, 4 | parameter DATA_DEPTH = 1024 5 | )( 6 | input wire clk, 7 | input wire [ ADDR_WIDTH-1:0] wr_addr, 8 | input wire wr_en, 9 | input wire [ DATA_WIDTH-1:0] wr_data, 10 | input wire [ ADDR_WIDTH-1:0] rd_addr, 11 | input wire rd_en, 12 | output reg [ DATA_WIDTH-1:0] rd_data 13 | ); 14 | 15 | reg [ DATA_WIDTH-1:0] data_buf [ DATA_DEPTH-1:0]; 16 | 17 | always@(posedge clk) begin 18 | if (wr_en) begin 19 | data_buf[wr_addr] <= wr_data; 20 | end 21 | end 22 | 23 | always @(posedge clk) begin 24 | if (rd_en) begin 25 | rd_data <= data_buf[rd_addr]; 26 | end 27 | else begin 28 | rd_data <= rd_data; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /rtl/dp_ram_regout.v: -------------------------------------------------------------------------------- 1 | module dp_ram_regout #( 2 | parameter KNOB_REGOUT = 0, 3 | parameter ADDR_WIDTH = 10, 4 | parameter DATA_WIDTH = 256, 5 | parameter DATA_DEPTH = 1024 6 | )( 7 | input wire clk, 8 | input wire [ ADDR_WIDTH-1:0] wr_addr, 9 | input wire wr_en, 10 | input wire [ DATA_WIDTH-1:0] wr_data, 11 | input wire [ ADDR_WIDTH-1:0] rd_addr, 12 | input wire rd_en, 13 | output wire [ DATA_WIDTH-1:0] rd_data 14 | ); 15 | 16 | reg [ DATA_WIDTH-1:0] data_buf [ DATA_DEPTH-1:0]; 17 | reg [DATA_WIDTH + DATA_WIDTH * KNOB_REGOUT - 1 : 0] data_dly_r; 18 | 19 | always@(posedge clk) begin 20 | if (wr_en) begin 21 | data_buf[wr_addr] <= wr_data; 22 | end 23 | end 24 | 25 | always @(posedge clk) begin 26 | if (rd_en) begin 27 | data_dly_r <= {data_dly_r ,data_buf[rd_addr]}; 28 | end 29 | else begin 30 | data_dly_r <= data_dly_r; 31 | end 32 | end 33 | 34 | assign rd_data = data_dly_r[DATA_WIDTH + DATA_WIDTH * KNOB_REGOUT - 1 : DATA_WIDTH * KNOB_REGOUT]; 35 | 36 | endmodule -------------------------------------------------------------------------------- /rtl/param_buf.v: -------------------------------------------------------------------------------- 1 | /* 2 | Top Module: param_buf.v 3 | Author: Hao Zhang 4 | Time: 202308 5 | */ 6 | 7 | module param_buf#( 8 | parameter BIAS_DATA_WIDTH = 16 , 9 | parameter HBM_DATA_WIDTH = 16 , 10 | parameter LBM_DATA_WIDTH = 16 , 11 | parameter OC_NUM = 4 , 12 | parameter P_ADDR_WIDTH = 5 , 13 | parameter P_BUF0_DEPTH = 17 , //DNDM 14 | parameter P_BUF1_DEPTH = 20 , //SR 15 | parameter P_BUF_WIDTH = (BIAS_DATA_WIDTH + HBM_DATA_WIDTH + LBM_DATA_WIDTH) * OC_NUM , 16 | parameter P2PU_RD_WIDTH = BIAS_DATA_WIDTH + HBM_DATA_WIDTH + LBM_DATA_WIDTH 17 | ) 18 | ( 19 | input wire clk , 20 | input wire rst_n , 21 | // control 22 | input wire buf_pp_flag , 23 | // axi 24 | input wire [ P_ADDR_WIDTH - 1 : 0] axi2p_waddr , 25 | input wire axi2p_wen , 26 | input wire [ P_BUF_WIDTH - 1 : 0] axi2p_wdata , 27 | input wire [ P_ADDR_WIDTH - 1 : 0] axi2p_raddr , 28 | input wire axi2p_ren , 29 | output wire [ P_BUF_WIDTH - 1 : 0] axi2p_rdata , 30 | // buf_rd 31 | input wire pu2p_ren , 32 | input wire [ P_ADDR_WIDTH - 1 : 0] pu2p_raddr , 33 | output wire [ P2PU_RD_WIDTH - 1 : 0] p2pu_rdata_0 , //c 0/4... 34 | output wire [ P2PU_RD_WIDTH - 1 : 0] p2pu_rdata_1 , //c 1/5... 35 | output wire [ P2PU_RD_WIDTH - 1 : 0] p2pu_rdata_2 , //c 2/6... 36 | output wire [ P2PU_RD_WIDTH - 1 : 0] p2pu_rdata_3 //c 3/7... 37 | ); 38 | 39 | wire [ P_ADDR_WIDTH - 1 : 0] b0_waddr ; 40 | wire b0_wen ; 41 | wire [ P_BUF_WIDTH - 1 : 0] b0_wdata ; 42 | wire [ P_ADDR_WIDTH - 1 : 0] b0_raddr ; 43 | wire b0_ren ; 44 | wire [ P_BUF_WIDTH - 1 : 0] b0_rdata ; 45 | wire [ P_ADDR_WIDTH - 1 : 0] b1_waddr ; 46 | wire b1_wen ; 47 | wire [ P_BUF_WIDTH - 1 : 0] b1_wdata ; 48 | wire [ P_ADDR_WIDTH - 1 : 0] b1_raddr ; 49 | wire b1_ren ; 50 | wire [ P_BUF_WIDTH - 1 : 0] b1_rdata ; 51 | 52 | // buffer_wr & buffer_rd 53 | assign b0_waddr = axi2p_waddr; 54 | assign b0_wen = (buf_pp_flag == 0) ? axi2p_wen : 0; 55 | assign b0_wdata = axi2p_wdata; 56 | assign b0_raddr = (buf_pp_flag == 0) ? axi2p_raddr : pu2p_raddr; 57 | assign b0_ren = (buf_pp_flag == 0) ? axi2p_ren : pu2p_ren; 58 | assign b1_waddr = axi2p_waddr; 59 | assign b1_wen = (buf_pp_flag == 1) ? axi2p_wen : 0; 60 | assign b1_wdata = axi2p_wdata; 61 | assign b1_raddr = (buf_pp_flag == 1) ? axi2p_raddr : pu2p_raddr; 62 | assign b1_ren = (buf_pp_flag == 1) ? axi2p_ren : pu2p_ren; 63 | assign axi2p_rdata = (buf_pp_flag == 0) ? b0_rdata : b1_rdata; 64 | assign p2pu_rdata_0 = (buf_pp_flag == 0) ? b1_rdata[1*P2PU_RD_WIDTH - 1 : 0*P2PU_RD_WIDTH] : b0_rdata[1*P2PU_RD_WIDTH - 1 : 0*P2PU_RD_WIDTH]; 65 | assign p2pu_rdata_1 = (buf_pp_flag == 0) ? b1_rdata[2*P2PU_RD_WIDTH - 1 : 1*P2PU_RD_WIDTH] : b0_rdata[2*P2PU_RD_WIDTH - 1 : 1*P2PU_RD_WIDTH]; 66 | assign p2pu_rdata_2 = (buf_pp_flag == 0) ? b1_rdata[3*P2PU_RD_WIDTH - 1 : 2*P2PU_RD_WIDTH] : b0_rdata[3*P2PU_RD_WIDTH - 1 : 2*P2PU_RD_WIDTH]; 67 | assign p2pu_rdata_3 = (buf_pp_flag == 0) ? b1_rdata[4*P2PU_RD_WIDTH - 1 : 3*P2PU_RD_WIDTH] : b0_rdata[4*P2PU_RD_WIDTH - 1 : 3*P2PU_RD_WIDTH]; 68 | 69 | // bias ping-pong buffer instantiation 70 | dp_ram #( 71 | .ADDR_WIDTH (P_ADDR_WIDTH ), 72 | .DATA_WIDTH (P_BUF_WIDTH ), 73 | .DATA_DEPTH (P_BUF0_DEPTH ) 74 | ) 75 | u_b0_buf( //DNDM 76 | .clk (clk ), 77 | .wr_addr (b0_waddr ), 78 | .wr_en (b0_wen ), 79 | .wr_data (b0_wdata ), 80 | .rd_addr (b0_raddr ), 81 | .rd_en (b0_ren ), 82 | .rd_data (b0_rdata ) 83 | ); 84 | dp_ram #( //SR 85 | .ADDR_WIDTH (P_ADDR_WIDTH ), 86 | .DATA_WIDTH (P_BUF_WIDTH ), 87 | .DATA_DEPTH (P_BUF1_DEPTH ) 88 | ) 89 | u_b1_buf( 90 | .clk (clk ), 91 | .wr_addr (b1_waddr ), 92 | .wr_en (b1_wen ), 93 | .wr_data (b1_wdata ), 94 | .rd_addr (b1_raddr ), 95 | .rd_en (b1_ren ), 96 | .rd_data (b1_rdata ) 97 | ); 98 | 99 | endmodule -------------------------------------------------------------------------------- /rtl/pe_array/pe.v: -------------------------------------------------------------------------------- 1 | /************************************************************************* 2 | > File Name: pe.v 3 | > Author: kehongbo 4 | > Mail: 5 | > Created Time: Sun 6 Aug 2023 12:03:22 PM CST 6 | > Description: 7 | ************************************************************************/ 8 | 9 | 10 | //------------------------------------------------------------------------------ 11 | // 12 | // Modified : 2023-8-13 by WYH 13 | // Description : add signed number proc 14 | 15 | 16 | //------------------------------------------------------------------------------ 17 | module pe#( 18 | parameter FEATURE_WD = 8, 19 | parameter WEIGHT_WD = 8, 20 | parameter PE_OUTPUT_WD = 18 21 | ) 22 | ( 23 | input clk , 24 | input rstn , 25 | input clr_i , 26 | input signed [FEATURE_WD -1: 0] pe_row_input , 27 | input signed [WEIGHT_WD -1: 0] pe_row_weight , 28 | output [PE_OUTPUT_WD -1: 0] pe_row_output , 29 | input [1 -1: 0] pe_col_vld , 30 | input [1 -1: 0] pe_row_vld , 31 | input [1 -1: 0] pe_array_vld 32 | ); 33 | 34 | reg signed [PE_OUTPUT_WD -1: 0] pe_out_r ; 35 | wire accum_ena_w ; 36 | (*use_dsp = "yes"*)wire signed [PE_OUTPUT_WD : 0] prod_w ; 37 | 38 | assign accum_ena_w = pe_col_vld & pe_row_vld & pe_array_vld; 39 | assign prod_w = pe_row_input * pe_row_weight + pe_out_r; 40 | always @(posedge clk or negedge rstn) begin 41 | if(!rstn) begin 42 | pe_out_r <= 'd0 ; 43 | end 44 | else begin 45 | if(clr_i) 46 | pe_out_r <= 'd0 ; 47 | else if(accum_ena_w) 48 | pe_out_r <= prod_w; 49 | end 50 | end 51 | 52 | assign pe_row_output = pe_out_r; 53 | 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /rtl/pe_array/pe2.v: -------------------------------------------------------------------------------- 1 | //`define FPGA 2 | module pe2#( 3 | parameter FEATURE_WD = 8, 4 | parameter WEIGHT_WD = 8, 5 | parameter PE_OUTPUT_WD = 18 6 | )( 7 | input clk , 8 | input rstn , 9 | input clr_i , 10 | input [2 * FEATURE_WD -1: 0] pe_row_input , 11 | input [WEIGHT_WD -1: 0] pe_row_weight , 12 | output [2 * PE_OUTPUT_WD -1: 0] pe_row_output , 13 | input [2 -1: 0] pe_col_vld , 14 | input [1 -1: 0] pe_row_vld , 15 | input [1 -1: 0] pe_array_vld 16 | ); 17 | // function : pack 2 mac into 1 module 18 | 19 | 20 | /************************ reg & wire ********************************/ 21 | 22 | `ifdef FPGA 23 | reg signed [36 -1: 0] pe_out_r ; 24 | reg signed [36 -1: 0] pe_out_w ; 25 | wire signed [2 -1: 0] accum_ena_w ; 26 | wire signed [FEATURE_WD + WEIGHT_WD -1: 0] prod_w ; 27 | wire signed [28 -1: 0] dsp_28_i_w ; 28 | wire signed [18 -1: 0] dsp_18_i_w ; 29 | wire signed [36 -1: 0] dsp_36_i_w ; 30 | wire signed [36 -1: 0] dsp_36_o_w ; 31 | wire signed [10 -1: 0] pe_row_1_w ; 32 | wire signed [10 -1: 0] pe_row_0_w ; 33 | wire signed [1 -1: 0] refined_num_w ; 34 | wire signed [18 -1: 0] pe_row_1_ref_w ; 35 | wire signed [8 -1: 0] pe_row_weight_w ; 36 | 37 | 38 | 39 | // using dsp to implement a(27 bit) * b(18 bit) + c(48 bit) 40 | assign pe_row_1_w = pe_row_input[15:8]; 41 | assign pe_row_0_w = pe_row_input[7:0]; 42 | assign pe_row_weight_w = pe_row_weight; 43 | assign accum_ena_w = {pe_col_vld[1] & pe_row_vld & pe_array_vld, pe_col_vld[0] & pe_row_vld & pe_array_vld}; 44 | assign dsp_28_i_w = {{2{pe_row_1_w[7]}}, pe_row_1_w, {8{pe_row_0_w[7]}}, {2{pe_row_0_w[7]}}, pe_row_0_w}; 45 | //assign dsp_18_i_w = {{10{pe_row_weight[7]}}, pe_row_weight}; 46 | assign refined_num_w = pe_row_0_w[7] ^ pe_row_weight[7]; 47 | 48 | assign pe_row_1_ref_w = $signed(pe_out_r[35:18]) + refined_num_w; 49 | assign dsp_36_i_w = {pe_row_1_ref_w, pe_out_r[17:0]}; 50 | // pe2 mul need to be refined 51 | (*use_dsp = "yes"*)assign dsp_36_o_w = dsp_28_i_w * pe_row_weight_w ; 52 | 53 | 54 | 55 | always @(*) begin 56 | case(accum_ena_w) 57 | 2'd0: pe_out_w = pe_out_r; 58 | 2'd1: pe_out_w = {pe_out_r[35:18], dsp_36_o_w[17:0]}; 59 | 2'd2: pe_out_w = {dsp_36_o_w[35:18], pe_out_r[17:0]}; 60 | 2'd3: pe_out_w = {dsp_36_o_w[35:18], dsp_36_o_w[17:0]}; 61 | endcase 62 | end 63 | 64 | always @(posedge clk or negedge rstn) begin 65 | if(~rstn) 66 | pe_out_r <= 'd0; 67 | else if(clr_i) 68 | pe_out_r <= 'd0; 69 | else 70 | pe_out_r <= pe_out_w; 71 | end 72 | 73 | assign pe_row_output = pe_out_r; 74 | 75 | 76 | 77 | // debug circuit 78 | wire signed [18 -1: 0] pe_debug_1_w ; 79 | wire signed [18 -1: 0] pe_debug_0_w ; 80 | wire signed [18 -1: 0] pe_dut_1_w ; 81 | wire signed [18 -1: 0] pe_dut_0_w ; 82 | 83 | 84 | assign pe_dut_1_w = dsp_36_o_w[35:18]; 85 | assign pe_dut_0_w = dsp_36_o_w[17:0]; 86 | 87 | assign pe_debug_1_w = pe_row_1_w * pe_row_weight_w; 88 | assign pe_debug_0_w = pe_row_0_w * pe_row_weight_w; 89 | 90 | initial begin 91 | while (rstn!==0) begin 92 | @(posedge clk); 93 | end 94 | while (rstn===0) begin 95 | @(posedge clk); 96 | end 97 | while (1) begin 98 | if(pe_dut_1_w != pe_debug_1_w) begin 99 | $display("MISMATCH!!!"); 100 | $display("%d", pe_out_r[35:18]); 101 | $display("%d %d %d %d", pe_dut_1_w, pe_dut_0_w, pe_debug_1_w, pe_debug_0_w); 102 | $display("%d %d", pe_row_1_w, pe_row_weight); 103 | $display("%d %d", pe_row_0_w, pe_row_weight); 104 | $finish(); 105 | end 106 | @(posedge clk); 107 | end 108 | end 109 | 110 | `else 111 | pe #( 112 | .FEATURE_WD (FEATURE_WD ), 113 | .WEIGHT_WD (WEIGHT_WD ), 114 | .PE_OUTPUT_WD (PE_OUTPUT_WD ) 115 | )pe_0( 116 | .clk (clk ), 117 | .rstn (rstn ), 118 | .clr_i (clr_i ), 119 | .pe_row_input (pe_row_input[0 +: FEATURE_WD] ), 120 | .pe_row_weight (pe_row_weight ), 121 | .pe_row_output (pe_row_output[0 +: PE_OUTPUT_WD] ), 122 | .pe_col_vld (pe_col_vld[0] ), 123 | .pe_row_vld (pe_row_vld ), 124 | .pe_array_vld (pe_array_vld ) 125 | ); 126 | 127 | pe #( 128 | .FEATURE_WD (FEATURE_WD ), 129 | .WEIGHT_WD (WEIGHT_WD ), 130 | .PE_OUTPUT_WD (PE_OUTPUT_WD ) 131 | )pe_1( 132 | .clk (clk ), 133 | .rstn (rstn ), 134 | .clr_i (clr_i ), 135 | .pe_row_input (pe_row_input[FEATURE_WD +: FEATURE_WD] ), 136 | .pe_row_weight (pe_row_weight ), 137 | .pe_row_output (pe_row_output[PE_OUTPUT_WD +: PE_OUTPUT_WD]), 138 | .pe_col_vld (pe_col_vld[1] ), 139 | .pe_row_vld (pe_row_vld ), 140 | .pe_array_vld (pe_array_vld ) 141 | ); 142 | 143 | `endif 144 | 145 | endmodule 146 | -------------------------------------------------------------------------------- /rtl/pu/pu_adder2.v: -------------------------------------------------------------------------------- 1 | module pu_adder2#( 2 | parameter INPUT_WD1 = 20, 3 | parameter INPUT_WD2 = 16, 4 | parameter OUTPUT_WD = 20 5 | )( 6 | input [INPUT_WD1 -1 : 0] op1_i , 7 | input [INPUT_WD2 -1 : 0] op2_i , 8 | output [OUTPUT_WD -1 : 0] acc_o 9 | ); 10 | 11 | wire [OUTPUT_WD - 1 : 0] level_0_1_w; 12 | wire [OUTPUT_WD - 1 : 0] level_0_2_w; 13 | wire [OUTPUT_WD - 1 : 0] level_1_1_w; 14 | 15 | 16 | /*************** dbg signals ****************/ 17 | wire mon_overflow1; 18 | 19 | 20 | 21 | //assign level_0_1_w = {{(OUTPUT_WD - INPUT_WD2){1'b0}},op1_i }; 22 | //assign level_0_2_w = {{(OUTPUT_WD - INPUT_WD2){1'b0}},op2_i }; 23 | assign level_0_1_w = {{(OUTPUT_WD - INPUT_WD1){op1_i[INPUT_WD1 - 1]}}, op1_i}; 24 | assign level_0_2_w = {{(OUTPUT_WD - INPUT_WD2){op2_i[INPUT_WD2 - 1]}}, op2_i}; 25 | 26 | assign {mon_overflow1, level_1_1_w} = { {level_0_1_w[OUTPUT_WD-1]}, level_0_1_w} + {{level_0_1_w[OUTPUT_WD-1]}, level_0_2_w} ; 27 | 28 | 29 | assign acc_o = level_1_1_w; 30 | 31 | endmodule -------------------------------------------------------------------------------- /rtl/pu/pu_adder4.v: -------------------------------------------------------------------------------- 1 | module pu_adder4#( 2 | parameter PE_OUTPUT_WD = 18, 3 | parameter ACCUM_WD = 20 4 | )( 5 | input [PE_OUTPUT_WD -1 : 0] pe_rf_ic1_i, 6 | input [PE_OUTPUT_WD -1 : 0] pe_rf_ic2_i, 7 | input [PE_OUTPUT_WD -1 : 0] pe_rf_ic3_i, 8 | input [PE_OUTPUT_WD -1 : 0] pe_rf_ic4_i, 9 | output [ACCUM_WD -1 : 0] accum_o 10 | ); 11 | 12 | wire [ACCUM_WD - 1 : 0] level_0_1_w; 13 | wire [ACCUM_WD - 1 : 0] level_0_2_w; 14 | wire [ACCUM_WD - 1 : 0] level_0_3_w; 15 | wire [ACCUM_WD - 1 : 0] level_1_1_w; 16 | 17 | /*************** dbg signals ****************/ 18 | wire mon_overflow1; 19 | wire mon_overflow2; 20 | wire mon_overflow3; 21 | wire mon_overflow4; 22 | 23 | assign {level_0_1_w} = { {(ACCUM_WD - PE_OUTPUT_WD){pe_rf_ic1_i[PE_OUTPUT_WD - 1]}}, pe_rf_ic1_i} + {{(ACCUM_WD - PE_OUTPUT_WD){pe_rf_ic2_i[PE_OUTPUT_WD - 1]}}, pe_rf_ic2_i} ; 24 | assign {level_0_2_w} = { {(ACCUM_WD - PE_OUTPUT_WD){pe_rf_ic3_i[PE_OUTPUT_WD - 1]}}, pe_rf_ic3_i} + {{(ACCUM_WD - PE_OUTPUT_WD){pe_rf_ic4_i[PE_OUTPUT_WD - 1]}}, pe_rf_ic4_i} ; 25 | 26 | assign {level_1_1_w} = {level_0_1_w} + {level_0_2_w} ; 27 | 28 | assign accum_o = level_1_1_w; 29 | 30 | endmodule -------------------------------------------------------------------------------- /rtl/pu/pu_bias_add_pipe1.v: -------------------------------------------------------------------------------- 1 | /************************************************************************* 2 | > File Name: pu_bias_add_pipe1.v 3 | > Author: YuhengWei 4 | > Mail: 5 | > Created Time: Sun 6 Aug 2023 12:03:22 PM CST 6 | > Description: 7 | ************************************************************************/ 8 | 9 | module pu_bias_add_pipe1 #( 10 | parameter PE_OUTPUT_WD = 20 , 11 | parameter BIAS_WD = 16 , 12 | parameter PE_COL_NUM = 32 , 13 | parameter ACCUM_OUTPUT_WD = 20 14 | 15 | )( 16 | 17 | input clk , 18 | input rstn , 19 | 20 | // 1h 4oc per cycles 21 | // oc_h 22 | input pu_accum_bias_p1_vld_i , 23 | output pu_accum_bias_p1_rdy_o , 24 | 25 | input [PE_OUTPUT_WD * PE_COL_NUM -1: 0] acc_0_i , // one row of oc0 26 | input [PE_OUTPUT_WD * PE_COL_NUM -1: 0] acc_1_i , // one row of oc1 27 | input [PE_OUTPUT_WD * PE_COL_NUM -1: 0] acc_2_i , // one row of oc2 28 | input [PE_OUTPUT_WD * PE_COL_NUM -1: 0] acc_3_i , // one row of oc3 29 | 30 | input [BIAS_WD -1: 0] bias_oc0_i , 31 | input [BIAS_WD -1: 0] bias_oc1_i , 32 | input [BIAS_WD -1: 0] bias_oc2_i , 33 | input [BIAS_WD -1: 0] bias_oc3_i , 34 | 35 | output pu_accum_bias_p1_vld_o , 36 | input pu_accum_bias_p1_rdy_i , 37 | 38 | output [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] conv_oc0_o , 39 | output [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] conv_oc1_o , 40 | output [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] conv_oc2_o , 41 | output [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] conv_oc3_o 42 | 43 | ); 44 | 45 | 46 | //----------------------------- 47 | 48 | // WIRE & REG 49 | 50 | // 51 | 52 | //----------------------------- 53 | reg vld_r ; 54 | reg [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] conv_oc0_r ; 55 | reg [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] conv_oc1_r ; 56 | reg [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] conv_oc2_r ; 57 | reg [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] conv_oc3_r ; 58 | 59 | wire [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] conv_oc0_w ; 60 | wire [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] conv_oc1_w ; 61 | wire [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] conv_oc2_w ; 62 | wire [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] conv_oc3_w ; 63 | 64 | 65 | 66 | 67 | 68 | genvar i; 69 | 70 | 71 | //---------------------------------------------------------------------------------------------------------- 72 | 73 | // ADD BIAS TO ONE ROW OF OC0 74 | 75 | //---------------------------------------------------------------------------------------------------------- 76 | 77 | generate 78 | 79 | for(i = 0; i < PE_COL_NUM; i = i + 1)begin:OC0 80 | 81 | pu_adder2 #( 82 | .INPUT_WD1(PE_OUTPUT_WD ), 83 | .INPUT_WD2(BIAS_WD ), 84 | .OUTPUT_WD(ACCUM_OUTPUT_WD ) 85 | ) 86 | pu_adder_oc0( 87 | .op1_i(acc_0_i[PE_COL_NUM * PE_OUTPUT_WD - 1 - i * PE_OUTPUT_WD -: PE_OUTPUT_WD] ) , 88 | .op2_i(bias_oc0_i ) , //fanout to 32 adder2 89 | .acc_o(conv_oc0_w[PE_COL_NUM * ACCUM_OUTPUT_WD - 1 - i * ACCUM_OUTPUT_WD -: ACCUM_OUTPUT_WD]) 90 | ); 91 | 92 | end 93 | 94 | endgenerate 95 | 96 | 97 | //---------------------------------------------------------------------------------------------------------- 98 | 99 | // ADD BIAS TO ONE ROW OF OC1 100 | 101 | //---------------------------------------------------------------------------------------------------------- 102 | 103 | generate 104 | 105 | for(i = 0; i < PE_COL_NUM; i = i + 1)begin:OC1 106 | 107 | pu_adder2 #( 108 | .INPUT_WD1(PE_OUTPUT_WD ), 109 | .INPUT_WD2(BIAS_WD ), 110 | .OUTPUT_WD(ACCUM_OUTPUT_WD ) 111 | ) 112 | pu_adder_oc1( 113 | .op1_i(acc_1_i[PE_COL_NUM * PE_OUTPUT_WD - 1 - i * PE_OUTPUT_WD -: PE_OUTPUT_WD] ) , 114 | .op2_i(bias_oc1_i ) , //fanout to 32 adder2 115 | .acc_o(conv_oc1_w[PE_COL_NUM * ACCUM_OUTPUT_WD - 1 - i * ACCUM_OUTPUT_WD -: ACCUM_OUTPUT_WD]) 116 | ); 117 | 118 | end 119 | 120 | endgenerate 121 | 122 | //---------------------------------------------------------------------------------------------------------- 123 | 124 | // ADD BIAS TO ONE ROW OF OC2 125 | 126 | //---------------------------------------------------------------------------------------------------------- 127 | 128 | generate 129 | 130 | for(i = 0; i < PE_COL_NUM; i = i + 1)begin:OC2 131 | 132 | pu_adder2 #( 133 | .INPUT_WD1(PE_OUTPUT_WD ), 134 | .INPUT_WD2(BIAS_WD ), 135 | .OUTPUT_WD(ACCUM_OUTPUT_WD ) 136 | ) 137 | pu_adder_oc2( 138 | .op1_i(acc_2_i[PE_COL_NUM * PE_OUTPUT_WD - 1 - i * PE_OUTPUT_WD -: PE_OUTPUT_WD] ) , 139 | .op2_i(bias_oc2_i ) , //fanout to 32 adder2 140 | .acc_o(conv_oc2_w[PE_COL_NUM * ACCUM_OUTPUT_WD - 1 - i * ACCUM_OUTPUT_WD -: ACCUM_OUTPUT_WD]) 141 | ); 142 | 143 | end 144 | 145 | endgenerate 146 | 147 | //---------------------------------------------------------------------------------------------------------- 148 | 149 | // ADD BIAS TO ONE ROW OF OC3 150 | 151 | //---------------------------------------------------------------------------------------------------------- 152 | 153 | generate 154 | 155 | for(i = 0; i < PE_COL_NUM; i = i + 1)begin:OC3 156 | 157 | pu_adder2 #( 158 | .INPUT_WD1(PE_OUTPUT_WD ), 159 | .INPUT_WD2(BIAS_WD ), 160 | .OUTPUT_WD(ACCUM_OUTPUT_WD ) 161 | ) 162 | pu_adder_oc3( 163 | .op1_i(acc_3_i[PE_COL_NUM * PE_OUTPUT_WD - 1 - i * PE_OUTPUT_WD -: PE_OUTPUT_WD] ) , 164 | .op2_i(bias_oc3_i ) , //fanout to 32 adder2 165 | .acc_o(conv_oc3_w[PE_COL_NUM * ACCUM_OUTPUT_WD - 1 - i * ACCUM_OUTPUT_WD -: ACCUM_OUTPUT_WD]) 166 | ); 167 | 168 | end 169 | 170 | endgenerate 171 | 172 | 173 | 174 | // bubble collapse 175 | 176 | assign pu_accum_bias_p1_rdy_o = ~vld_r | pu_accum_bias_p1_rdy_i ; 177 | 178 | always@(posedge clk or negedge rstn) begin 179 | if(~rstn)begin 180 | vld_r <= 'b0; 181 | end 182 | else if(~vld_r | pu_accum_bias_p1_rdy_i )begin 183 | vld_r <= pu_accum_bias_p1_vld_i; 184 | end 185 | end 186 | 187 | always @(posedge clk) begin 188 | if(pu_accum_bias_p1_rdy_o && pu_accum_bias_p1_vld_i)begin 189 | conv_oc0_r <= conv_oc0_w ; 190 | conv_oc1_r <= conv_oc1_w ; 191 | conv_oc2_r <= conv_oc2_w ; 192 | conv_oc3_r <= conv_oc3_w ; 193 | end 194 | end 195 | 196 | 197 | assign pu_accum_bias_p1_vld_o = vld_r ; 198 | 199 | assign conv_oc0_o = conv_oc0_r ; 200 | assign conv_oc1_o = conv_oc1_r ; 201 | assign conv_oc2_o = conv_oc2_r ; 202 | assign conv_oc3_o = conv_oc3_r ; 203 | 204 | 205 | 206 | endmodule -------------------------------------------------------------------------------- /rtl/pu/pu_mul.v: -------------------------------------------------------------------------------- 1 | module pu_mul#( 2 | parameter INPUT_WD1 = 20, 3 | parameter INPUT_WD2 = 16, 4 | parameter OUTPUT_WD = 36 5 | )( 6 | input signed [INPUT_WD1 -1 : 0] op1_i , 7 | input [INPUT_WD2 -1 : 0] op2_i , 8 | output signed [OUTPUT_WD -1 : 0] mul_o 9 | ); 10 | wire signed [INPUT_WD2 : 0] op2_w; 11 | assign op2_w = {1'b0, op2_i}; 12 | assign mul_o = op1_i * op2_w; 13 | 14 | /* 15 | wire [INPUT_WD1 + INPUT_WD2 - 1 : 0] unsigned_mul_w ; 16 | wire [OUTPUT_WD - 1 : 0] shift_mul_w ; 17 | 18 | wire [OUTPUT_WD - 1 : 0] signed_mul_w ; 19 | 20 | wire [INPUT_WD1 - 1 : 0] op1_w ; 21 | wire [INPUT_WD2 - 1 : 0] op2_w ; 22 | 23 | assign op1_w = op1_i[INPUT_WD1 - 1] ? ( ~op1_i + 'd1 ) : op1_i ; 24 | // assign op2_w = op2_i[INPUT_WD2 - 1] ? ( ~op2_i + 'd1 ) : op2_i ; 25 | 26 | // requant factor is unsigned 27 | assign op2_w = op2_i; 28 | 29 | 30 | 31 | assign unsigned_mul_w = op1_w * op2_w ; 32 | assign shift_mul_w = unsigned_mul_w[0+:OUTPUT_WD] ; 33 | 34 | assign signed_mul_w = (op1_i[INPUT_WD1 - 1] )? (~shift_mul_w +'d1) : shift_mul_w ; 35 | 36 | 37 | 38 | 39 | assign mul_o = signed_mul_w ; 40 | */ 41 | 42 | endmodule -------------------------------------------------------------------------------- /rtl/pu/pu_relu_mul_pipe2.v: -------------------------------------------------------------------------------- 1 | /************************************************************************* 2 | > File Name: pu_relu_mul_pipe2.v 3 | > Author: YuhengWei 4 | > Mail: 5 | > Created Time: Sun 6 Aug 2023 12:03:22 PM CST 6 | > Description: 7 | ************************************************************************/ 8 | 9 | module pu_relu_mul_pipe2 #( 10 | parameter RELU_IN_WD = 24 , 11 | parameter RELU_OUT_WD = 24 , 12 | parameter PE_COL_NUM = 32 , 13 | parameter RELU_PARAM_WD = 8 14 | )( 15 | 16 | input clk , 17 | input rstn , 18 | 19 | // 1h 4oc per cycles 20 | // oc_h 21 | input pu_relu_mul_p2_vld_i , 22 | output pu_relu_mul_p2_rdy_o , 23 | 24 | input [RELU_IN_WD * PE_COL_NUM -1: 0] conv_oc0_i , // one row of oc0 25 | input [RELU_IN_WD * PE_COL_NUM -1: 0] conv_oc1_i , // one row of oc1 26 | input [RELU_IN_WD * PE_COL_NUM -1: 0] conv_oc2_i , // one row of oc2 27 | input [RELU_IN_WD * PE_COL_NUM -1: 0] conv_oc3_i , // one row of oc3 28 | 29 | input [RELU_PARAM_WD -1: 0] relu_para_oc0_i , 30 | input [RELU_PARAM_WD -1: 0] relu_para_oc1_i , 31 | input [RELU_PARAM_WD -1: 0] relu_para_oc2_i , 32 | input [RELU_PARAM_WD -1: 0] relu_para_oc3_i , 33 | 34 | output pu_relu_mul_p2_vld_o , 35 | input pu_relu_mul_p2_rdy_i , 36 | 37 | output [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_oc0_o , 38 | output [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_oc1_o , 39 | output [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_oc2_o , 40 | output [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_oc3_o 41 | 42 | ); 43 | 44 | 45 | //----------------------------- 46 | 47 | // WIRE & REG 48 | 49 | // 50 | 51 | //----------------------------- 52 | reg vld_r ; 53 | 54 | reg [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_oc0_r ; 55 | reg [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_oc1_r ; 56 | reg [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_oc2_r ; 57 | reg [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_oc3_r ; 58 | 59 | wire [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_oc0_w ; 60 | wire [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_oc1_w ; 61 | wire [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_oc2_w ; 62 | wire [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_oc3_w ; 63 | 64 | wire [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_mul_oc0_w ; 65 | wire [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_mul_oc1_w ; 66 | wire [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_mul_oc2_w ; 67 | wire [RELU_OUT_WD * PE_COL_NUM -1: 0] prelu_mul_oc3_w ; 68 | 69 | 70 | 71 | 72 | 73 | genvar i; 74 | 75 | 76 | //---------------------------------------------------------------------------------------------------------- 77 | 78 | // PRELU TO ONE ROW OF OC0 79 | 80 | //---------------------------------------------------------------------------------------------------------- 81 | 82 | generate 83 | 84 | for(i = 0; i < PE_COL_NUM; i = i + 1)begin:OC0 85 | 86 | pu_mul #( 87 | .INPUT_WD1(RELU_IN_WD ), 88 | .INPUT_WD2(RELU_PARAM_WD ), 89 | .OUTPUT_WD(RELU_OUT_WD ) 90 | ) 91 | pu_relu_mul_oc0( 92 | .op1_i(conv_oc0_i[PE_COL_NUM * RELU_IN_WD - 1 - i * RELU_IN_WD -: RELU_IN_WD] ) , 93 | .op2_i(relu_para_oc0_i ) , //fanout to 32 mul 94 | .mul_o(prelu_mul_oc0_w[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] ) 95 | ); 96 | assign prelu_oc0_w[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] = conv_oc0_i[PE_COL_NUM * RELU_IN_WD - 1 - i * RELU_IN_WD] ? 97 | prelu_mul_oc0_w[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] : 98 | conv_oc0_i[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] ; 99 | 100 | end 101 | 102 | endgenerate 103 | 104 | //---------------------------------------------------------------------------------------------------------- 105 | 106 | // PRELU TO ONE ROW OF OC1 107 | 108 | //---------------------------------------------------------------------------------------------------------- 109 | 110 | generate 111 | 112 | for(i = 0; i < PE_COL_NUM; i = i + 1)begin:OC1 113 | 114 | pu_mul #( 115 | .INPUT_WD1(RELU_IN_WD ), 116 | .INPUT_WD2(RELU_PARAM_WD ), 117 | .OUTPUT_WD(RELU_OUT_WD ) 118 | ) 119 | pu_relu_mul_oc1( 120 | .op1_i(conv_oc1_i[PE_COL_NUM * RELU_IN_WD - 1 - i * RELU_IN_WD -: RELU_IN_WD] ) , 121 | .op2_i(relu_para_oc1_i ) , //fanout to 32 mul 122 | .mul_o(prelu_mul_oc1_w[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] ) 123 | ); 124 | assign prelu_oc1_w[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] = conv_oc1_i[PE_COL_NUM * RELU_IN_WD - 1 - i * RELU_IN_WD] ? 125 | prelu_mul_oc1_w[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] : 126 | conv_oc1_i[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] ; 127 | 128 | end 129 | 130 | endgenerate 131 | 132 | 133 | //---------------------------------------------------------------------------------------------------------- 134 | 135 | // PRELU TO ONE ROW OF OC2 136 | 137 | //---------------------------------------------------------------------------------------------------------- 138 | 139 | generate 140 | 141 | for(i = 0; i < PE_COL_NUM; i = i + 1)begin:OC2 142 | 143 | pu_mul #( 144 | .INPUT_WD1(RELU_IN_WD ), 145 | .INPUT_WD2(RELU_PARAM_WD ), 146 | .OUTPUT_WD(RELU_OUT_WD ) 147 | ) 148 | pu_relu_mul_oc2( 149 | .op1_i(conv_oc2_i[PE_COL_NUM * RELU_IN_WD - 1 - i * RELU_IN_WD -: RELU_IN_WD] ) , 150 | .op2_i(relu_para_oc2_i ) , //fanout to 32 mul 151 | .mul_o(prelu_mul_oc2_w[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] ) 152 | ); 153 | assign prelu_oc2_w[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] = conv_oc2_i[PE_COL_NUM * RELU_IN_WD - 1 - i * RELU_IN_WD] ? 154 | prelu_mul_oc2_w[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] : 155 | conv_oc2_i[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] ; 156 | 157 | end 158 | 159 | endgenerate 160 | 161 | 162 | //---------------------------------------------------------------------------------------------------------- 163 | 164 | // PRELU TO ONE ROW OF OC3 165 | 166 | //---------------------------------------------------------------------------------------------------------- 167 | 168 | generate 169 | 170 | for(i = 0; i < PE_COL_NUM; i = i + 1)begin:OC3 171 | 172 | pu_mul #( 173 | .INPUT_WD1(RELU_IN_WD ), 174 | .INPUT_WD2(RELU_PARAM_WD ), 175 | .OUTPUT_WD(RELU_OUT_WD ) 176 | ) 177 | pu_relu_mul_oc3( 178 | .op1_i(conv_oc3_i[PE_COL_NUM * RELU_IN_WD - 1 - i * RELU_IN_WD -: RELU_IN_WD] ) , 179 | .op2_i(relu_para_oc3_i ) , //fanout to 32 mul 180 | .mul_o(prelu_mul_oc3_w[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] ) 181 | ); 182 | assign prelu_oc3_w[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] = conv_oc3_i[PE_COL_NUM * RELU_IN_WD - 1 - i * RELU_IN_WD] ? 183 | prelu_mul_oc3_w[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] : 184 | conv_oc3_i[PE_COL_NUM * RELU_OUT_WD - 1 - i * RELU_OUT_WD -: RELU_OUT_WD] ; 185 | 186 | end 187 | 188 | endgenerate 189 | 190 | 191 | 192 | 193 | // bubble collapse 194 | 195 | assign pu_relu_mul_p2_rdy_o = ~vld_r | pu_relu_mul_p2_rdy_i ; 196 | 197 | always@(posedge clk or negedge rstn) begin 198 | if(~rstn)begin 199 | vld_r <= 'b0; 200 | end 201 | else if(~vld_r | pu_relu_mul_p2_rdy_i )begin 202 | vld_r <= pu_relu_mul_p2_vld_i ; 203 | end 204 | end 205 | 206 | always @(posedge clk) begin 207 | if(pu_relu_mul_p2_rdy_o && pu_relu_mul_p2_vld_i )begin 208 | prelu_oc0_r <= prelu_oc0_w ; 209 | prelu_oc1_r <= prelu_oc1_w ; 210 | prelu_oc2_r <= prelu_oc2_w ; 211 | prelu_oc3_r <= prelu_oc3_w ; 212 | end 213 | end 214 | 215 | 216 | assign pu_relu_mul_p2_vld_o = vld_r ; 217 | 218 | assign prelu_oc0_o = prelu_oc0_r ; 219 | assign prelu_oc1_o = prelu_oc1_r ; 220 | assign prelu_oc2_o = prelu_oc2_r ; 221 | assign prelu_oc3_o = prelu_oc3_r ; 222 | 223 | 224 | 225 | endmodule -------------------------------------------------------------------------------- /rtl/pu/pu_requant_pipe4.v: -------------------------------------------------------------------------------- 1 | /************************************************************************* 2 | > File Name: pu_requant_pipe4.v 3 | > Author: YuhengWei 4 | > Mail: 5 | > Created Time: Sun 6 Aug 2023 12:03:22 PM CST 6 | > Description: 7 | ************************************************************************/ 8 | 9 | 10 | // TODO: need multiplier 11 | module pu_requant_pipe4 #( 12 | parameter PE_OUTPUT_WD = 24 , 13 | parameter PE_COL_NUM = 32 , 14 | parameter REQUANT_PARM_WD = 8 , 15 | parameter REQUANT_WD = 8 16 | 17 | )( 18 | 19 | input clk , 20 | input rstn , 21 | 22 | // 1h 4oc per cycles 23 | // oc_h 24 | input pu_requant_p4_vld_i , 25 | output pu_requant_p4_rdy_o , 26 | 27 | input [PE_OUTPUT_WD * PE_COL_NUM -1: 0] requant_oc0_i , // one row of oc0 28 | input [PE_OUTPUT_WD * PE_COL_NUM -1: 0] requant_oc1_i , // one row of oc1 29 | input [PE_OUTPUT_WD * PE_COL_NUM -1: 0] requant_oc2_i , // one row of oc2 30 | input [PE_OUTPUT_WD * PE_COL_NUM -1: 0] requant_oc3_i , // one row of oc3 31 | 32 | input [REQUANT_PARM_WD -1: 0] parm_oc0_i , 33 | input [REQUANT_PARM_WD -1: 0] parm_oc1_i , 34 | input [REQUANT_PARM_WD -1: 0] parm_oc2_i , 35 | input [REQUANT_PARM_WD -1: 0] parm_oc3_i , 36 | 37 | output pu_requant_p4_vld_o , 38 | input pu_requant_p4_rdy_i , 39 | 40 | output [REQUANT_WD * PE_COL_NUM -1: 0] requant_oc0_o , 41 | output [REQUANT_WD * PE_COL_NUM -1: 0] requant_oc1_o , 42 | output [REQUANT_WD * PE_COL_NUM -1: 0] requant_oc2_o , 43 | output [REQUANT_WD * PE_COL_NUM -1: 0] requant_oc3_o 44 | 45 | ); 46 | 47 | 48 | //----------------------------- 49 | 50 | // WIRE & REG 51 | 52 | // 53 | 54 | //----------------------------- 55 | reg vld_r ; 56 | reg [REQUANT_WD * PE_COL_NUM -1: 0] requant_oc0_r ; 57 | reg [REQUANT_WD * PE_COL_NUM -1: 0] requant_oc1_r ; 58 | reg [REQUANT_WD * PE_COL_NUM -1: 0] requant_oc2_r ; 59 | reg [REQUANT_WD * PE_COL_NUM -1: 0] requant_oc3_r ; 60 | wire [REQUANT_WD * PE_COL_NUM -1: 0] requant_oc0_w ; 61 | wire [REQUANT_WD * PE_COL_NUM -1: 0] requant_oc1_w ; 62 | wire [REQUANT_WD * PE_COL_NUM -1: 0] requant_oc2_w ; 63 | wire [REQUANT_WD * PE_COL_NUM -1: 0] requant_oc3_w ; 64 | 65 | 66 | 67 | 68 | 69 | genvar i; 70 | 71 | 72 | //---------------------------------------------------------------------------------------------------------- 73 | 74 | // REQUANT TO 8BIT FOR ONE ROW OF OC0 1 2 3 75 | 76 | // TODO: 77 | 78 | //---------------------------------------------------------------------------------------------------------- 79 | 80 | generate 81 | 82 | for(i = 0; i < PE_COL_NUM; i = i + 1)begin:OC0 83 | 84 | assign requant_oc0_w[PE_COL_NUM * REQUANT_WD - 1 - i * REQUANT_WD -: REQUANT_WD] = requant_oc0_i[PE_COL_NUM * PE_OUTPUT_WD - 1 - i * PE_OUTPUT_WD -: REQUANT_WD] ; //reduce to 8bit 85 | assign requant_oc1_w[PE_COL_NUM * REQUANT_WD - 1 - i * REQUANT_WD -: REQUANT_WD] = requant_oc1_i[PE_COL_NUM * PE_OUTPUT_WD - 1 - i * PE_OUTPUT_WD -: REQUANT_WD] ; //reduce to 8bit 86 | assign requant_oc2_w[PE_COL_NUM * REQUANT_WD - 1 - i * REQUANT_WD -: REQUANT_WD] = requant_oc2_i[PE_COL_NUM * PE_OUTPUT_WD - 1 - i * PE_OUTPUT_WD -: REQUANT_WD] ; //reduce to 8bit 87 | assign requant_oc3_w[PE_COL_NUM * REQUANT_WD - 1 - i * REQUANT_WD -: REQUANT_WD] = requant_oc3_i[PE_COL_NUM * PE_OUTPUT_WD - 1 - i * PE_OUTPUT_WD -: REQUANT_WD] ; //reduce to 8bit 88 | 89 | end 90 | 91 | endgenerate 92 | 93 | 94 | 95 | 96 | // bubble collapse 97 | 98 | assign pu_requant_p4_rdy_o = ~vld_r | pu_requant_p4_rdy_i ; 99 | 100 | always@(posedge clk or negedge rstn) begin 101 | if(~rstn)begin 102 | vld_r <= 'b0; 103 | end 104 | else if(~vld_r | pu_requant_p4_rdy_i )begin 105 | vld_r <= pu_requant_p4_vld_i ; 106 | end 107 | end 108 | 109 | always @(posedge clk) begin 110 | if(pu_requant_p4_rdy_o && pu_requant_p4_vld_i )begin 111 | requant_oc0_r <= requant_oc0_w ; 112 | requant_oc1_r <= requant_oc1_w ; 113 | requant_oc2_r <= requant_oc2_w ; 114 | requant_oc3_r <= requant_oc3_w ; 115 | end 116 | 117 | end 118 | 119 | 120 | assign pu_requant_p4_vld_o = vld_r ; 121 | 122 | assign requant_oc0_o = requant_oc0_r ; 123 | assign requant_oc1_o = requant_oc1_r ; 124 | assign requant_oc2_o = requant_oc2_r ; 125 | assign requant_oc3_o = requant_oc3_r ; 126 | 127 | 128 | endmodule -------------------------------------------------------------------------------- /rtl/pu/pu_resi_add_pipe_p3.v: -------------------------------------------------------------------------------- 1 | /************************************************************************* 2 | > File Name: pu_resi_add_pipe3.v 3 | > Author: YuhengWei 4 | > Mail: 5 | > Created Time: Sun 6 Aug 2023 12:03:22 PM CST 6 | > Description: 7 | ************************************************************************/ 8 | 9 | module pu_resi_add_pipe_p3 #( 10 | parameter PE_OUTPUT_WD = 8 , 11 | parameter PE_COL_NUM = 32 , 12 | parameter ACCUM_OUTPUT_WD = 9 , 13 | parameter RESI_WD = 8 , 14 | parameter X_N = PE_COL_NUM , 15 | parameter ACC_WD = ACCUM_OUTPUT_WD 16 | 17 | )( 18 | 19 | input clk , 20 | input rstn , 21 | 22 | // 1h 4oc per cycle 23 | // oc_h 24 | input pu_resi_add_p3_vld_i , 25 | output pu_resi_add_p3_rdy_o , 26 | input is_bypass_i , 27 | input [PE_OUTPUT_WD * PE_COL_NUM -1: 0] prelu_0_i , // one row of oc0 28 | input [PE_OUTPUT_WD * PE_COL_NUM -1: 0] prelu_1_i , // one row of oc1 29 | input [PE_OUTPUT_WD * PE_COL_NUM -1: 0] prelu_2_i , // one row of oc2 30 | input [PE_OUTPUT_WD * PE_COL_NUM -1: 0] prelu_3_i , // one row of oc3 31 | 32 | input [RESI_WD * PE_COL_NUM -1: 0] resi_oc0_i , 33 | input [RESI_WD * PE_COL_NUM -1: 0] resi_oc1_i , 34 | input [RESI_WD * PE_COL_NUM -1: 0] resi_oc2_i , 35 | input [RESI_WD * PE_COL_NUM -1: 0] resi_oc3_i , 36 | 37 | output pu_resi_add_p3_vld_o , 38 | input pu_resi_add_p3_rdy_i , 39 | 40 | output [(ACC_WD + 2) * PE_COL_NUM -1: 0] resi_oc0_o , 41 | output [(ACC_WD + 2) * PE_COL_NUM -1: 0] resi_oc1_o , 42 | output [(ACC_WD + 2) * PE_COL_NUM -1: 0] resi_oc2_o , 43 | output [(ACC_WD + 2) * PE_COL_NUM -1: 0] resi_oc3_o 44 | 45 | ); 46 | 47 | 48 | //----------------------------- 49 | 50 | // WIRE & REG 51 | 52 | // 53 | 54 | //----------------------------- 55 | reg vld_r ; 56 | reg [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] resi_oc0_r ; 57 | reg [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] resi_oc1_r ; 58 | reg [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] resi_oc2_r ; 59 | reg [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] resi_oc3_r ; 60 | wire [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] resi_oc0_w ; 61 | wire [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] resi_oc1_w ; 62 | wire [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] resi_oc2_w ; 63 | wire [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] resi_oc3_w ; 64 | 65 | wire [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] resi_oc0_mux_w ; 66 | wire [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] resi_oc1_mux_w ; 67 | wire [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] resi_oc2_mux_w ; 68 | wire [ACCUM_OUTPUT_WD * PE_COL_NUM -1: 0] resi_oc3_mux_w ; 69 | 70 | reg p0_vld_r ; 71 | wire p0_rdy_w ; 72 | wire p0_bc_rdy_w ; 73 | reg p1_vld_r ; 74 | wire p1_rdy_w ; 75 | wire p1_bc_rdy_w ; 76 | 77 | reg [(ACC_WD + 2) * X_N -1: 0] resi_add_256_oc0_r ; 78 | reg [(ACC_WD + 2) * X_N -1: 0] resi_add_256_oc1_r ; 79 | reg [(ACC_WD + 2) * X_N -1: 0] resi_add_256_oc2_r ; 80 | reg [(ACC_WD + 2) * X_N -1: 0] resi_add_256_oc3_r ; 81 | 82 | wire [(ACC_WD + 2) * X_N -1: 0] resi_add_256_oc0_w ; //11 bit 83 | wire [(ACC_WD + 2) * X_N -1: 0] resi_add_256_oc1_w ; 84 | wire [(ACC_WD + 2) * X_N -1: 0] resi_add_256_oc2_w ; 85 | wire [(ACC_WD + 2) * X_N -1: 0] resi_add_256_oc3_w ; 86 | 87 | genvar i; 88 | 89 | 90 | //---------------------------------------------------------------------------------------------------------- 91 | 92 | // ADD RESI TO ONE ROW OF OC0 93 | 94 | //---------------------------------------------------------------------------------------------------------- 95 | 96 | generate 97 | 98 | for(i = 0; i < PE_COL_NUM; i = i + 1 )begin:OC0 99 | 100 | pu_adder2 #( 101 | .INPUT_WD1(PE_OUTPUT_WD ), 102 | .INPUT_WD2(RESI_WD ), 103 | .OUTPUT_WD(ACCUM_OUTPUT_WD ) 104 | ) 105 | pu_adder_oc0( 106 | .op1_i(prelu_0_i[PE_COL_NUM * PE_OUTPUT_WD - 1 - i * PE_OUTPUT_WD -: PE_OUTPUT_WD] ) , 107 | .op2_i(resi_oc0_i[PE_COL_NUM * RESI_WD - 1 - i * RESI_WD -: RESI_WD] ) , 108 | .acc_o(resi_oc0_w[PE_COL_NUM * ACCUM_OUTPUT_WD - 1 - i * ACCUM_OUTPUT_WD -: ACCUM_OUTPUT_WD]) 109 | ); 110 | 111 | end 112 | 113 | endgenerate 114 | 115 | //---------------------------------------------------------------------------------------------------------- 116 | 117 | // ADD RESI TO ONE ROW OF OC1 118 | 119 | //---------------------------------------------------------------------------------------------------------- 120 | 121 | generate 122 | 123 | for(i = 0; i < PE_COL_NUM; i = i + 1)begin:OC1 124 | 125 | pu_adder2 #( 126 | .INPUT_WD1(PE_OUTPUT_WD ), 127 | .INPUT_WD2(RESI_WD ), 128 | .OUTPUT_WD(ACCUM_OUTPUT_WD ) 129 | ) 130 | pu_adder_oc1( 131 | .op1_i(prelu_1_i[PE_COL_NUM * PE_OUTPUT_WD - 1 - i * PE_OUTPUT_WD -: PE_OUTPUT_WD] ) , 132 | .op2_i(resi_oc1_i[PE_COL_NUM * RESI_WD - 1 - i * RESI_WD -: RESI_WD] ) , 133 | .acc_o(resi_oc1_w[PE_COL_NUM * ACCUM_OUTPUT_WD - 1 - i * ACCUM_OUTPUT_WD -: ACCUM_OUTPUT_WD]) 134 | ); 135 | 136 | end 137 | 138 | endgenerate 139 | 140 | //---------------------------------------------------------------------------------------------------------- 141 | 142 | // ADD RESI TO ONE ROW OF OC2 143 | 144 | //---------------------------------------------------------------------------------------------------------- 145 | 146 | generate 147 | 148 | for(i = 0; i < PE_COL_NUM; i = i + 1)begin:OC2 149 | 150 | pu_adder2 #( 151 | .INPUT_WD1(PE_OUTPUT_WD ), 152 | .INPUT_WD2(RESI_WD ), 153 | .OUTPUT_WD(ACCUM_OUTPUT_WD ) 154 | ) 155 | pu_adder_oc2( 156 | .op1_i(prelu_2_i[PE_COL_NUM * PE_OUTPUT_WD - 1 - i * PE_OUTPUT_WD -: PE_OUTPUT_WD] ) , 157 | .op2_i(resi_oc2_i[PE_COL_NUM * RESI_WD - 1 - i * RESI_WD -: RESI_WD] ) , 158 | .acc_o(resi_oc2_w[PE_COL_NUM * ACCUM_OUTPUT_WD - 1 - i * ACCUM_OUTPUT_WD -: ACCUM_OUTPUT_WD]) 159 | ); 160 | 161 | end 162 | 163 | endgenerate 164 | 165 | //---------------------------------------------------------------------------------------------------------- 166 | 167 | // ADD RESI TO ONE ROW OF OC3 168 | 169 | //---------------------------------------------------------------------------------------------------------- 170 | 171 | generate 172 | 173 | for(i = 0; i < PE_COL_NUM; i = i + 1)begin:OC3 174 | 175 | pu_adder2 #( 176 | .INPUT_WD1(PE_OUTPUT_WD ), 177 | .INPUT_WD2(RESI_WD ), 178 | .OUTPUT_WD(ACCUM_OUTPUT_WD ) 179 | ) 180 | pu_adder_oc3( 181 | .op1_i(prelu_3_i[PE_COL_NUM * PE_OUTPUT_WD - 1 - i * PE_OUTPUT_WD -: PE_OUTPUT_WD] ) , 182 | .op2_i(resi_oc3_i[PE_COL_NUM * RESI_WD - 1 - i * RESI_WD -: RESI_WD] ) , 183 | .acc_o(resi_oc3_w[PE_COL_NUM * ACCUM_OUTPUT_WD - 1 - i * ACCUM_OUTPUT_WD -: ACCUM_OUTPUT_WD]) 184 | ); 185 | 186 | end 187 | 188 | endgenerate 189 | 190 | 191 | 192 | // bubble collapse 193 | 194 | wire pipe_vld ; 195 | wire pipe_rdy ; 196 | assign pipe_vld = pu_resi_add_p3_vld_i ; 197 | assign pu_resi_add_p3_rdy_o = pipe_rdy ; 198 | 199 | 200 | assign pipe_rdy = p0_bc_rdy_w ; 201 | assign p0_bc_rdy_w = ~p0_vld_r || p0_rdy_w ; 202 | 203 | always@(posedge clk or negedge rstn) begin 204 | if(~rstn)begin 205 | p0_vld_r <= 1'b0; 206 | end 207 | else if(p0_bc_rdy_w)begin 208 | p0_vld_r <= pipe_vld ; 209 | end 210 | end 211 | 212 | 213 | 214 | always @(posedge clk) begin 215 | if(pipe_vld && p0_bc_rdy_w )begin 216 | resi_oc0_r <= is_bypass_i ? prelu_0_i : resi_oc0_w ; 217 | resi_oc1_r <= is_bypass_i ? prelu_1_i : resi_oc1_w ; 218 | resi_oc2_r <= is_bypass_i ? prelu_2_i : resi_oc2_w ; 219 | resi_oc3_r <= is_bypass_i ? prelu_3_i : resi_oc3_w ; 220 | end 221 | end 222 | assign p0_rdy_w = p1_bc_rdy_w ; 223 | 224 | 225 | 226 | 227 | generate 228 | for(i = 0 ; i < 32 ; i = i + 1)begin : add256_c_0_3 229 | assign resi_add_256_oc0_w[X_N * (ACC_WD + 2) - 1 - i * (ACC_WD + 2) -: (ACC_WD + 2)] = $signed(resi_oc0_r[X_N * ACC_WD - 1 - i * ACC_WD -: ACC_WD]) + $signed(11'd256); 230 | assign resi_add_256_oc1_w[X_N * (ACC_WD + 2) - 1 - i * (ACC_WD + 2) -: (ACC_WD + 2)] = $signed(resi_oc1_r[X_N * ACC_WD - 1 - i * ACC_WD -: ACC_WD]) + $signed(11'd256); 231 | assign resi_add_256_oc2_w[X_N * (ACC_WD + 2) - 1 - i * (ACC_WD + 2) -: (ACC_WD + 2)] = $signed(resi_oc2_r[X_N * ACC_WD - 1 - i * ACC_WD -: ACC_WD]) + $signed(11'd256); 232 | assign resi_add_256_oc3_w[X_N * (ACC_WD + 2) - 1 - i * (ACC_WD + 2) -: (ACC_WD + 2)] = $signed(resi_oc3_r[X_N * ACC_WD - 1 - i * ACC_WD -: ACC_WD]) + $signed(11'd256); 233 | 234 | end 235 | endgenerate 236 | 237 | assign p1_bc_rdy_w = ~p1_vld_r || p1_rdy_w ; 238 | always @(posedge clk or negedge rstn)begin 239 | if(~rstn)begin 240 | p1_vld_r <= 1'b0; 241 | end 242 | else if(p1_bc_rdy_w)begin 243 | p1_vld_r <= p0_vld_r ; 244 | end 245 | end 246 | always @(posedge clk)begin 247 | if(p1_bc_rdy_w && p0_vld_r)begin 248 | resi_add_256_oc0_r <= is_bypass_i ? {{32{2'b0}}, resi_oc0_r} : resi_add_256_oc0_w ; 249 | resi_add_256_oc1_r <= is_bypass_i ? {{32{2'b0}}, resi_oc1_r} : resi_add_256_oc1_w ; 250 | resi_add_256_oc2_r <= is_bypass_i ? {{32{2'b0}}, resi_oc2_r} : resi_add_256_oc2_w ; 251 | resi_add_256_oc3_r <= is_bypass_i ? {{32{2'b0}}, resi_oc3_r} : resi_add_256_oc3_w ; 252 | end 253 | end 254 | assign p1_rdy_w = pu_resi_add_p3_rdy_i ; 255 | assign pu_resi_add_p3_vld_o = p1_vld_r ; 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | // 264 | assign resi_oc0_o = resi_add_256_oc0_r ; 265 | assign resi_oc1_o = resi_add_256_oc1_r ; 266 | assign resi_oc2_o = resi_add_256_oc2_r ; 267 | assign resi_oc3_o = resi_add_256_oc3_r ; 268 | 269 | 270 | endmodule -------------------------------------------------------------------------------- /rtl/sch/handshake_sche2pe.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////// 2 | // 3 | // File: handshake_sche2pe.v 4 | // Project Name: DLA_v2 5 | // Module Name: handshake_sche2pe 6 | // Description: handshake between scheduler and pe 7 | // 8 | // Author: Wanwei Xiao 9 | // Setup Data: 13/8/2023 10 | // Modify Date: 01/9/2023 11 | // 12 | ////////////////////////////////////////////////// 13 | module handshake_sche2pe 14 | #( 15 | parameter PE_COL_NUM = 32 , 16 | parameter PE_H_NUM = 4 , 17 | parameter PE_IC_NUM = 4 , 18 | parameter IFM_WIDTH = 8 , 19 | parameter WT_WIDTH = 8 20 | ) 21 | ( 22 | clk , 23 | rst_n , 24 | pe2sch_rdy , 25 | 26 | sch2pe_row_start_i , 27 | sch2pe_row_done_i , 28 | sch2pe_vld_i , 29 | mux_col_vld_i , 30 | mux_row_vld_i , 31 | mux_array_vld_i , 32 | 33 | sch_data_output_0_0_i, 34 | sch_data_output_0_1_i, 35 | sch_data_output_0_2_i, 36 | sch_data_output_0_3_i, 37 | sch_data_output_1_0_i, 38 | sch_data_output_1_1_i, 39 | sch_data_output_1_2_i, 40 | sch_data_output_1_3_i, 41 | sch_data_output_2_0_i, 42 | sch_data_output_2_1_i, 43 | sch_data_output_2_2_i, 44 | sch_data_output_2_3_i, 45 | sch_data_output_3_0_i, 46 | sch_data_output_3_1_i, 47 | sch_data_output_3_2_i, 48 | sch_data_output_3_3_i, 49 | 50 | sch_weight_output_0_0_i, 51 | sch_weight_output_0_1_i, 52 | sch_weight_output_0_2_i, 53 | sch_weight_output_0_3_i, 54 | sch_weight_output_1_0_i, 55 | sch_weight_output_1_1_i, 56 | sch_weight_output_1_2_i, 57 | sch_weight_output_1_3_i, 58 | sch_weight_output_2_0_i, 59 | sch_weight_output_2_1_i, 60 | sch_weight_output_2_2_i, 61 | sch_weight_output_2_3_i, 62 | sch_weight_output_3_0_i, 63 | sch_weight_output_3_1_i, 64 | sch_weight_output_3_2_i, 65 | sch_weight_output_3_3_i, 66 | 67 | sch2pe_row_start_o , 68 | sch2pe_row_done_o , 69 | sch2pe_vld_o , 70 | mux_col_vld_o , 71 | mux_row_vld_o , 72 | mux_array_vld_o , 73 | 74 | sch_data_output_0_0_o, 75 | sch_data_output_0_1_o, 76 | sch_data_output_0_2_o, 77 | sch_data_output_0_3_o, 78 | sch_data_output_1_0_o, 79 | sch_data_output_1_1_o, 80 | sch_data_output_1_2_o, 81 | sch_data_output_1_3_o, 82 | sch_data_output_2_0_o, 83 | sch_data_output_2_1_o, 84 | sch_data_output_2_2_o, 85 | sch_data_output_2_3_o, 86 | sch_data_output_3_0_o, 87 | sch_data_output_3_1_o, 88 | sch_data_output_3_2_o, 89 | sch_data_output_3_3_o, 90 | 91 | sch_weight_output_0_0_o, 92 | sch_weight_output_0_1_o, 93 | sch_weight_output_0_2_o, 94 | sch_weight_output_0_3_o, 95 | sch_weight_output_1_0_o, 96 | sch_weight_output_1_1_o, 97 | sch_weight_output_1_2_o, 98 | sch_weight_output_1_3_o, 99 | sch_weight_output_2_0_o, 100 | sch_weight_output_2_1_o, 101 | sch_weight_output_2_2_o, 102 | sch_weight_output_2_3_o, 103 | sch_weight_output_3_0_o, 104 | sch_weight_output_3_1_o, 105 | sch_weight_output_3_2_o, 106 | sch_weight_output_3_3_o 107 | ); 108 | 109 | input clk ; 110 | input rst_n ; 111 | input pe2sch_rdy ; 112 | 113 | input sch2pe_row_start_i; 114 | input sch2pe_row_done_i ; 115 | input sch2pe_vld_i ; 116 | input [PE_COL_NUM - 1 : 0] mux_col_vld_i ; 117 | input [PE_H_NUM - 1 : 0] mux_row_vld_i ; 118 | input [PE_IC_NUM - 1 : 0] mux_array_vld_i ; 119 | 120 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_0_0_i; 121 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_0_1_i; 122 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_0_2_i; 123 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_0_3_i; 124 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_1_0_i; 125 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_1_1_i; 126 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_1_2_i; 127 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_1_3_i; 128 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_2_0_i; 129 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_2_1_i; 130 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_2_2_i; 131 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_2_3_i; 132 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_3_0_i; 133 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_3_1_i; 134 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_3_2_i; 135 | input [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_3_3_i; 136 | 137 | input [WT_WIDTH - 1 : 0] sch_weight_output_0_0_i; 138 | input [WT_WIDTH - 1 : 0] sch_weight_output_0_1_i; 139 | input [WT_WIDTH - 1 : 0] sch_weight_output_0_2_i; 140 | input [WT_WIDTH - 1 : 0] sch_weight_output_0_3_i; 141 | input [WT_WIDTH - 1 : 0] sch_weight_output_1_0_i; 142 | input [WT_WIDTH - 1 : 0] sch_weight_output_1_1_i; 143 | input [WT_WIDTH - 1 : 0] sch_weight_output_1_2_i; 144 | input [WT_WIDTH - 1 : 0] sch_weight_output_1_3_i; 145 | input [WT_WIDTH - 1 : 0] sch_weight_output_2_0_i; 146 | input [WT_WIDTH - 1 : 0] sch_weight_output_2_1_i; 147 | input [WT_WIDTH - 1 : 0] sch_weight_output_2_2_i; 148 | input [WT_WIDTH - 1 : 0] sch_weight_output_2_3_i; 149 | input [WT_WIDTH - 1 : 0] sch_weight_output_3_0_i; 150 | input [WT_WIDTH - 1 : 0] sch_weight_output_3_1_i; 151 | input [WT_WIDTH - 1 : 0] sch_weight_output_3_2_i; 152 | input [WT_WIDTH - 1 : 0] sch_weight_output_3_3_i; 153 | 154 | output reg sch2pe_row_start_o; 155 | output reg sch2pe_row_done_o ; 156 | output reg sch2pe_vld_o ; 157 | output reg [PE_COL_NUM - 1 : 0] mux_col_vld_o ; 158 | output reg [PE_H_NUM - 1 : 0] mux_row_vld_o ; 159 | output reg [PE_IC_NUM - 1 : 0] mux_array_vld_o ; 160 | 161 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_0_0_o; 162 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_0_1_o; 163 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_0_2_o; 164 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_0_3_o; 165 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_1_0_o; 166 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_1_1_o; 167 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_1_2_o; 168 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_1_3_o; 169 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_2_0_o; 170 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_2_1_o; 171 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_2_2_o; 172 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_2_3_o; 173 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_3_0_o; 174 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_3_1_o; 175 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_3_2_o; 176 | output reg [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_3_3_o; 177 | 178 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_0_0_o; 179 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_0_1_o; 180 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_0_2_o; 181 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_0_3_o; 182 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_1_0_o; 183 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_1_1_o; 184 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_1_2_o; 185 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_1_3_o; 186 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_2_0_o; 187 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_2_1_o; 188 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_2_2_o; 189 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_2_3_o; 190 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_3_0_o; 191 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_3_1_o; 192 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_3_2_o; 193 | output reg [WT_WIDTH - 1 : 0] sch_weight_output_3_3_o; 194 | 195 | always@(posedge clk or negedge rst_n) 196 | begin 197 | if(!rst_n) begin 198 | sch2pe_row_start_o <= 0 ; 199 | //sch2pe_row_done_o <= 0 ; 200 | sch_data_output_0_0_o <= 0 ; 201 | sch_data_output_0_1_o <= 0 ; 202 | sch_data_output_0_2_o <= 0 ; 203 | sch_data_output_0_3_o <= 0 ; 204 | sch_data_output_1_0_o <= 0 ; 205 | sch_data_output_1_1_o <= 0 ; 206 | sch_data_output_1_2_o <= 0 ; 207 | sch_data_output_1_3_o <= 0 ; 208 | sch_data_output_2_0_o <= 0 ; 209 | sch_data_output_2_1_o <= 0 ; 210 | sch_data_output_2_2_o <= 0 ; 211 | sch_data_output_2_3_o <= 0 ; 212 | sch_data_output_3_0_o <= 0 ; 213 | sch_data_output_3_1_o <= 0 ; 214 | sch_data_output_3_2_o <= 0 ; 215 | sch_data_output_3_3_o <= 0 ; 216 | sch_weight_output_0_0_o <= 0 ; 217 | sch_weight_output_0_1_o <= 0 ; 218 | sch_weight_output_0_2_o <= 0 ; 219 | sch_weight_output_0_3_o <= 0 ; 220 | sch_weight_output_1_0_o <= 0 ; 221 | sch_weight_output_1_1_o <= 0 ; 222 | sch_weight_output_1_2_o <= 0 ; 223 | sch_weight_output_1_3_o <= 0 ; 224 | sch_weight_output_2_0_o <= 0 ; 225 | sch_weight_output_2_1_o <= 0 ; 226 | sch_weight_output_2_2_o <= 0 ; 227 | sch_weight_output_2_3_o <= 0 ; 228 | sch_weight_output_3_0_o <= 0 ; 229 | sch_weight_output_3_1_o <= 0 ; 230 | sch_weight_output_3_2_o <= 0 ; 231 | sch_weight_output_3_3_o <= 0 ; 232 | end 233 | else if(sch2pe_vld_i && pe2sch_rdy) begin 234 | sch2pe_row_start_o <= sch2pe_row_start_i ; 235 | //sch2pe_row_done_o <= sch2pe_row_done_i ; 236 | sch_data_output_0_0_o <= sch_data_output_0_0_i ; 237 | sch_data_output_0_1_o <= sch_data_output_0_1_i ; 238 | sch_data_output_0_2_o <= sch_data_output_0_2_i ; 239 | sch_data_output_0_3_o <= sch_data_output_0_3_i ; 240 | sch_data_output_1_0_o <= sch_data_output_1_0_i ; 241 | sch_data_output_1_1_o <= sch_data_output_1_1_i ; 242 | sch_data_output_1_2_o <= sch_data_output_1_2_i ; 243 | sch_data_output_1_3_o <= sch_data_output_1_3_i ; 244 | sch_data_output_2_0_o <= sch_data_output_2_0_i ; 245 | sch_data_output_2_1_o <= sch_data_output_2_1_i ; 246 | sch_data_output_2_2_o <= sch_data_output_2_2_i ; 247 | sch_data_output_2_3_o <= sch_data_output_2_3_i ; 248 | sch_data_output_3_0_o <= sch_data_output_3_0_i ; 249 | sch_data_output_3_1_o <= sch_data_output_3_1_i ; 250 | sch_data_output_3_2_o <= sch_data_output_3_2_i ; 251 | sch_data_output_3_3_o <= sch_data_output_3_3_i ; 252 | sch_weight_output_0_0_o <= sch_weight_output_0_0_i ; 253 | sch_weight_output_0_1_o <= sch_weight_output_0_1_i ; 254 | sch_weight_output_0_2_o <= sch_weight_output_0_2_i ; 255 | sch_weight_output_0_3_o <= sch_weight_output_0_3_i ; 256 | sch_weight_output_1_0_o <= sch_weight_output_1_0_i ; 257 | sch_weight_output_1_1_o <= sch_weight_output_1_1_i ; 258 | sch_weight_output_1_2_o <= sch_weight_output_1_2_i ; 259 | sch_weight_output_1_3_o <= sch_weight_output_1_3_i ; 260 | sch_weight_output_2_0_o <= sch_weight_output_2_0_i ; 261 | sch_weight_output_2_1_o <= sch_weight_output_2_1_i ; 262 | sch_weight_output_2_2_o <= sch_weight_output_2_2_i ; 263 | sch_weight_output_2_3_o <= sch_weight_output_2_3_i ; 264 | sch_weight_output_3_0_o <= sch_weight_output_3_0_i ; 265 | sch_weight_output_3_1_o <= sch_weight_output_3_1_i ; 266 | sch_weight_output_3_2_o <= sch_weight_output_3_2_i ; 267 | sch_weight_output_3_3_o <= sch_weight_output_3_3_i ; 268 | end 269 | end 270 | 271 | always @(posedge clk or negedge rst_n) 272 | begin 273 | if(!rst_n) 274 | sch2pe_row_done_o <= 0; 275 | else if(sch2pe_vld_i && pe2sch_rdy) 276 | sch2pe_row_done_o <= sch2pe_row_done_i; 277 | else 278 | sch2pe_row_done_o <= sch2pe_row_done_o && sch2pe_vld_i; 279 | end 280 | 281 | always @(posedge clk or negedge rst_n) 282 | begin 283 | if(!rst_n) begin 284 | sch2pe_vld_o <= 0 ; 285 | mux_col_vld_o <= 0 ; 286 | mux_row_vld_o <= 0 ; 287 | mux_array_vld_o <= 0 ; 288 | end 289 | else if(pe2sch_rdy) begin 290 | sch2pe_vld_o <= sch2pe_vld_i ; 291 | mux_col_vld_o <= mux_col_vld_i ; 292 | mux_row_vld_o <= mux_row_vld_i ; 293 | mux_array_vld_o <= mux_array_vld_i ; 294 | end 295 | end 296 | 297 | endmodule -------------------------------------------------------------------------------- /rtl/wt_buf.v: -------------------------------------------------------------------------------- 1 | /* 2 | Top Module: wt_buf.v 3 | Author: Hao Zhang 4 | Time: 202307 5 | */ 6 | 7 | module wt_buf#( 8 | parameter WT_WIDTH = 8 , 9 | parameter WT_ADDR_WIDTH = 7 , 10 | parameter WT_BUF0_DEPTH = 73 ,//DNDM 11 | parameter WT_BUF1_DEPTH = 108 ,//SR 12 | parameter IC_NUM = 4 , 13 | parameter OC_NUM = 4 , 14 | parameter WT_BUF_WIDTH = WT_WIDTH*IC_NUM*OC_NUM , 15 | parameter WT_GRP_NUM = 8 , 16 | parameter AXI2W_WIDTH = WT_BUF_WIDTH*WT_GRP_NUM , 17 | parameter KNOB_REGOUT = 0 18 | ) 19 | ( 20 | input wire clk , 21 | input wire rst_n , 22 | // control 23 | input wire buf_pp_flag , 24 | // axi 25 | input wire [ WT_ADDR_WIDTH - 1 : 0] axi2w_waddr , 26 | input wire axi2w_wen , 27 | input wire [ AXI2W_WIDTH - 1 : 0] axi2w_wdata , 28 | input wire [ WT_ADDR_WIDTH - 1 : 0] axi2w_raddr , 29 | input wire axi2w_ren , 30 | output wire [ AXI2W_WIDTH - 1 : 0] axi2w_rdata , 31 | // buf_rd 32 | input wire [ WT_GRP_NUM - 1 : 0] sch2w_ren , 33 | input wire [ WT_ADDR_WIDTH - 1 : 0] sch2w_raddr , 34 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_0_0 , 35 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_0_1 , 36 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_0_2 , 37 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_0_3 , 38 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_1_0 , 39 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_1_1 , 40 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_1_2 , 41 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_1_3 , 42 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_2_0 , 43 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_2_1 , 44 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_2_2 , 45 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_2_3 , 46 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_3_0 , 47 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_3_1 , 48 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_3_2 , 49 | output reg [ WT_WIDTH - 1 : 0] w2sch_rdata_3_3 50 | ); 51 | 52 | wire [ WT_ADDR_WIDTH - 1 : 0] wt0_waddr ; 53 | wire wt0_wen ; 54 | wire [ AXI2W_WIDTH - 1 : 0] wt0_wdata ; 55 | wire [ WT_ADDR_WIDTH - 1 : 0] wt0_raddr ; 56 | wire [ WT_GRP_NUM - 1 : 0] wt0_ren ; 57 | wire [ WT_BUF_WIDTH*WT_GRP_NUM - 1 : 0] wt0_rdata ; 58 | wire [ WT_ADDR_WIDTH - 1 : 0] wt1_waddr ; 59 | wire wt1_wen ; 60 | wire [ AXI2W_WIDTH - 1 : 0] wt1_wdata ; 61 | wire [ WT_ADDR_WIDTH - 1 : 0] wt1_raddr ; 62 | wire [ WT_GRP_NUM - 1 : 0] wt1_ren ; 63 | wire [ WT_BUF_WIDTH*WT_GRP_NUM - 1 : 0] wt1_rdata ; 64 | wire [ WT_BUF_WIDTH*WT_GRP_NUM - 1 : 0] w2sch_rdata_w; 65 | 66 | reg [ 8 - 1 : 0] sch2w_ren_d; 67 | 68 | genvar idx_inst; 69 | genvar idx_buf; 70 | 71 | // buffer_wr & buffer_rd 72 | generate 73 | for(idx_buf = 0; idx_buf < WT_GRP_NUM; idx_buf = idx_buf + 1)begin: wt_pp 74 | assign wt0_wdata[(idx_buf+1)*WT_BUF_WIDTH - 1 : idx_buf*WT_BUF_WIDTH] = axi2w_wdata[(idx_buf+1)*WT_BUF_WIDTH - 1 : idx_buf*WT_BUF_WIDTH]; 75 | assign wt0_ren[idx_buf] = (buf_pp_flag == 0) ? axi2w_ren : sch2w_ren[idx_buf]; 76 | assign axi2w_rdata[(idx_buf+1)*WT_BUF_WIDTH - 1 : idx_buf*WT_BUF_WIDTH] = (buf_pp_flag == 0) ? wt0_rdata[(idx_buf+1)*WT_BUF_WIDTH - 1 : idx_buf*WT_BUF_WIDTH] : wt1_rdata[(idx_buf+1)*WT_BUF_WIDTH - 1 : idx_buf*WT_BUF_WIDTH]; 77 | assign wt1_wdata[(idx_buf+1)*WT_BUF_WIDTH - 1 : idx_buf*WT_BUF_WIDTH] = axi2w_wdata[(idx_buf+1)*WT_BUF_WIDTH - 1 : idx_buf*WT_BUF_WIDTH]; 78 | assign wt1_ren[idx_buf] = (buf_pp_flag == 1) ? axi2w_ren : sch2w_ren[idx_buf]; 79 | assign w2sch_rdata_w[(idx_buf+1)*WT_BUF_WIDTH - 1 : idx_buf*WT_BUF_WIDTH] = (buf_pp_flag == 1) ? wt0_rdata[(idx_buf+1)*WT_BUF_WIDTH - 1 : idx_buf*WT_BUF_WIDTH] : wt1_rdata[(idx_buf+1)*WT_BUF_WIDTH - 1 : idx_buf*WT_BUF_WIDTH]; 80 | end 81 | endgenerate 82 | 83 | assign wt0_waddr = axi2w_waddr ; 84 | assign wt0_wen = (buf_pp_flag == 0) ? axi2w_wen : 0 ; 85 | assign wt0_raddr = (buf_pp_flag == 0) ? axi2w_raddr : sch2w_raddr ; 86 | assign wt1_waddr = axi2w_waddr ; 87 | assign wt1_wen = (buf_pp_flag == 1) ? axi2w_wen : 0 ; 88 | assign wt1_raddr = (buf_pp_flag == 1) ? axi2w_raddr : sch2w_raddr ; 89 | 90 | always@(posedge clk or negedge rst_n)begin 91 | if(!rst_n) 92 | sch2w_ren_d <= 0; 93 | else 94 | sch2w_ren_d <= sch2w_ren; 95 | end 96 | 97 | always@(*)begin 98 | case(sch2w_ren_d) 99 | 8'b00000001:begin 100 | w2sch_rdata_0_0 = w2sch_rdata_w[(0*WT_BUF_WIDTH+1*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+0*WT_WIDTH]; 101 | w2sch_rdata_0_1 = w2sch_rdata_w[(0*WT_BUF_WIDTH+2*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+1*WT_WIDTH]; 102 | w2sch_rdata_0_2 = w2sch_rdata_w[(0*WT_BUF_WIDTH+3*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+2*WT_WIDTH]; 103 | w2sch_rdata_0_3 = w2sch_rdata_w[(0*WT_BUF_WIDTH+4*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+3*WT_WIDTH]; 104 | w2sch_rdata_1_0 = w2sch_rdata_w[(0*WT_BUF_WIDTH+5*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+4*WT_WIDTH]; 105 | w2sch_rdata_1_1 = w2sch_rdata_w[(0*WT_BUF_WIDTH+6*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+5*WT_WIDTH]; 106 | w2sch_rdata_1_2 = w2sch_rdata_w[(0*WT_BUF_WIDTH+7*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+6*WT_WIDTH]; 107 | w2sch_rdata_1_3 = w2sch_rdata_w[(0*WT_BUF_WIDTH+8*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+7*WT_WIDTH]; 108 | w2sch_rdata_2_0 = w2sch_rdata_w[(0*WT_BUF_WIDTH+9*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+8*WT_WIDTH]; 109 | w2sch_rdata_2_1 = w2sch_rdata_w[(0*WT_BUF_WIDTH+10*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+9*WT_WIDTH]; 110 | w2sch_rdata_2_2 = w2sch_rdata_w[(0*WT_BUF_WIDTH+11*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+10*WT_WIDTH]; 111 | w2sch_rdata_2_3 = w2sch_rdata_w[(0*WT_BUF_WIDTH+12*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+11*WT_WIDTH]; 112 | w2sch_rdata_3_0 = w2sch_rdata_w[(0*WT_BUF_WIDTH+13*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+12*WT_WIDTH]; 113 | w2sch_rdata_3_1 = w2sch_rdata_w[(0*WT_BUF_WIDTH+14*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+13*WT_WIDTH]; 114 | w2sch_rdata_3_2 = w2sch_rdata_w[(0*WT_BUF_WIDTH+15*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+14*WT_WIDTH]; 115 | w2sch_rdata_3_3 = w2sch_rdata_w[(0*WT_BUF_WIDTH+16*WT_WIDTH) - 1 : 0*WT_BUF_WIDTH+15*WT_WIDTH]; 116 | end 117 | 8'b00000010:begin 118 | w2sch_rdata_0_0 = w2sch_rdata_w[(1*WT_BUF_WIDTH+1*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+0*WT_WIDTH]; 119 | w2sch_rdata_0_1 = w2sch_rdata_w[(1*WT_BUF_WIDTH+2*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+1*WT_WIDTH]; 120 | w2sch_rdata_0_2 = w2sch_rdata_w[(1*WT_BUF_WIDTH+3*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+2*WT_WIDTH]; 121 | w2sch_rdata_0_3 = w2sch_rdata_w[(1*WT_BUF_WIDTH+4*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+3*WT_WIDTH]; 122 | w2sch_rdata_1_0 = w2sch_rdata_w[(1*WT_BUF_WIDTH+5*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+4*WT_WIDTH]; 123 | w2sch_rdata_1_1 = w2sch_rdata_w[(1*WT_BUF_WIDTH+6*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+5*WT_WIDTH]; 124 | w2sch_rdata_1_2 = w2sch_rdata_w[(1*WT_BUF_WIDTH+7*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+6*WT_WIDTH]; 125 | w2sch_rdata_1_3 = w2sch_rdata_w[(1*WT_BUF_WIDTH+8*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+7*WT_WIDTH]; 126 | w2sch_rdata_2_0 = w2sch_rdata_w[(1*WT_BUF_WIDTH+9*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+8*WT_WIDTH]; 127 | w2sch_rdata_2_1 = w2sch_rdata_w[(1*WT_BUF_WIDTH+10*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+9*WT_WIDTH]; 128 | w2sch_rdata_2_2 = w2sch_rdata_w[(1*WT_BUF_WIDTH+11*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+10*WT_WIDTH]; 129 | w2sch_rdata_2_3 = w2sch_rdata_w[(1*WT_BUF_WIDTH+12*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+11*WT_WIDTH]; 130 | w2sch_rdata_3_0 = w2sch_rdata_w[(1*WT_BUF_WIDTH+13*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+12*WT_WIDTH]; 131 | w2sch_rdata_3_1 = w2sch_rdata_w[(1*WT_BUF_WIDTH+14*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+13*WT_WIDTH]; 132 | w2sch_rdata_3_2 = w2sch_rdata_w[(1*WT_BUF_WIDTH+15*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+14*WT_WIDTH]; 133 | w2sch_rdata_3_3 = w2sch_rdata_w[(1*WT_BUF_WIDTH+16*WT_WIDTH) - 1 : 1*WT_BUF_WIDTH+15*WT_WIDTH]; 134 | end 135 | 8'b00000100:begin 136 | w2sch_rdata_0_0 = w2sch_rdata_w[(2*WT_BUF_WIDTH+1*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+0*WT_WIDTH]; 137 | w2sch_rdata_0_1 = w2sch_rdata_w[(2*WT_BUF_WIDTH+2*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+1*WT_WIDTH]; 138 | w2sch_rdata_0_2 = w2sch_rdata_w[(2*WT_BUF_WIDTH+3*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+2*WT_WIDTH]; 139 | w2sch_rdata_0_3 = w2sch_rdata_w[(2*WT_BUF_WIDTH+4*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+3*WT_WIDTH]; 140 | w2sch_rdata_1_0 = w2sch_rdata_w[(2*WT_BUF_WIDTH+5*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+4*WT_WIDTH]; 141 | w2sch_rdata_1_1 = w2sch_rdata_w[(2*WT_BUF_WIDTH+6*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+5*WT_WIDTH]; 142 | w2sch_rdata_1_2 = w2sch_rdata_w[(2*WT_BUF_WIDTH+7*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+6*WT_WIDTH]; 143 | w2sch_rdata_1_3 = w2sch_rdata_w[(2*WT_BUF_WIDTH+8*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+7*WT_WIDTH]; 144 | w2sch_rdata_2_0 = w2sch_rdata_w[(2*WT_BUF_WIDTH+9*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+8*WT_WIDTH]; 145 | w2sch_rdata_2_1 = w2sch_rdata_w[(2*WT_BUF_WIDTH+10*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+9*WT_WIDTH]; 146 | w2sch_rdata_2_2 = w2sch_rdata_w[(2*WT_BUF_WIDTH+11*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+10*WT_WIDTH]; 147 | w2sch_rdata_2_3 = w2sch_rdata_w[(2*WT_BUF_WIDTH+12*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+11*WT_WIDTH]; 148 | w2sch_rdata_3_0 = w2sch_rdata_w[(2*WT_BUF_WIDTH+13*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+12*WT_WIDTH]; 149 | w2sch_rdata_3_1 = w2sch_rdata_w[(2*WT_BUF_WIDTH+14*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+13*WT_WIDTH]; 150 | w2sch_rdata_3_2 = w2sch_rdata_w[(2*WT_BUF_WIDTH+15*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+14*WT_WIDTH]; 151 | w2sch_rdata_3_3 = w2sch_rdata_w[(2*WT_BUF_WIDTH+16*WT_WIDTH) - 1 : 2*WT_BUF_WIDTH+15*WT_WIDTH]; 152 | end 153 | 8'b00001000:begin 154 | w2sch_rdata_0_0 = w2sch_rdata_w[(3*WT_BUF_WIDTH+1*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+0*WT_WIDTH]; 155 | w2sch_rdata_0_1 = w2sch_rdata_w[(3*WT_BUF_WIDTH+2*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+1*WT_WIDTH]; 156 | w2sch_rdata_0_2 = w2sch_rdata_w[(3*WT_BUF_WIDTH+3*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+2*WT_WIDTH]; 157 | w2sch_rdata_0_3 = w2sch_rdata_w[(3*WT_BUF_WIDTH+4*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+3*WT_WIDTH]; 158 | w2sch_rdata_1_0 = w2sch_rdata_w[(3*WT_BUF_WIDTH+5*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+4*WT_WIDTH]; 159 | w2sch_rdata_1_1 = w2sch_rdata_w[(3*WT_BUF_WIDTH+6*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+5*WT_WIDTH]; 160 | w2sch_rdata_1_2 = w2sch_rdata_w[(3*WT_BUF_WIDTH+7*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+6*WT_WIDTH]; 161 | w2sch_rdata_1_3 = w2sch_rdata_w[(3*WT_BUF_WIDTH+8*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+7*WT_WIDTH]; 162 | w2sch_rdata_2_0 = w2sch_rdata_w[(3*WT_BUF_WIDTH+9*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+8*WT_WIDTH]; 163 | w2sch_rdata_2_1 = w2sch_rdata_w[(3*WT_BUF_WIDTH+10*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+9*WT_WIDTH]; 164 | w2sch_rdata_2_2 = w2sch_rdata_w[(3*WT_BUF_WIDTH+11*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+10*WT_WIDTH]; 165 | w2sch_rdata_2_3 = w2sch_rdata_w[(3*WT_BUF_WIDTH+12*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+11*WT_WIDTH]; 166 | w2sch_rdata_3_0 = w2sch_rdata_w[(3*WT_BUF_WIDTH+13*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+12*WT_WIDTH]; 167 | w2sch_rdata_3_1 = w2sch_rdata_w[(3*WT_BUF_WIDTH+14*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+13*WT_WIDTH]; 168 | w2sch_rdata_3_2 = w2sch_rdata_w[(3*WT_BUF_WIDTH+15*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+14*WT_WIDTH]; 169 | w2sch_rdata_3_3 = w2sch_rdata_w[(3*WT_BUF_WIDTH+16*WT_WIDTH) - 1 : 3*WT_BUF_WIDTH+15*WT_WIDTH]; 170 | end 171 | 8'b00010000:begin 172 | w2sch_rdata_0_0 = w2sch_rdata_w[(4*WT_BUF_WIDTH+1*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+0*WT_WIDTH]; 173 | w2sch_rdata_0_1 = w2sch_rdata_w[(4*WT_BUF_WIDTH+2*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+1*WT_WIDTH]; 174 | w2sch_rdata_0_2 = w2sch_rdata_w[(4*WT_BUF_WIDTH+3*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+2*WT_WIDTH]; 175 | w2sch_rdata_0_3 = w2sch_rdata_w[(4*WT_BUF_WIDTH+4*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+3*WT_WIDTH]; 176 | w2sch_rdata_1_0 = w2sch_rdata_w[(4*WT_BUF_WIDTH+5*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+4*WT_WIDTH]; 177 | w2sch_rdata_1_1 = w2sch_rdata_w[(4*WT_BUF_WIDTH+6*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+5*WT_WIDTH]; 178 | w2sch_rdata_1_2 = w2sch_rdata_w[(4*WT_BUF_WIDTH+7*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+6*WT_WIDTH]; 179 | w2sch_rdata_1_3 = w2sch_rdata_w[(4*WT_BUF_WIDTH+8*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+7*WT_WIDTH]; 180 | w2sch_rdata_2_0 = w2sch_rdata_w[(4*WT_BUF_WIDTH+9*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+8*WT_WIDTH]; 181 | w2sch_rdata_2_1 = w2sch_rdata_w[(4*WT_BUF_WIDTH+10*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+9*WT_WIDTH]; 182 | w2sch_rdata_2_2 = w2sch_rdata_w[(4*WT_BUF_WIDTH+11*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+10*WT_WIDTH]; 183 | w2sch_rdata_2_3 = w2sch_rdata_w[(4*WT_BUF_WIDTH+12*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+11*WT_WIDTH]; 184 | w2sch_rdata_3_0 = w2sch_rdata_w[(4*WT_BUF_WIDTH+13*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+12*WT_WIDTH]; 185 | w2sch_rdata_3_1 = w2sch_rdata_w[(4*WT_BUF_WIDTH+14*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+13*WT_WIDTH]; 186 | w2sch_rdata_3_2 = w2sch_rdata_w[(4*WT_BUF_WIDTH+15*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+14*WT_WIDTH]; 187 | w2sch_rdata_3_3 = w2sch_rdata_w[(4*WT_BUF_WIDTH+16*WT_WIDTH) - 1 : 4*WT_BUF_WIDTH+15*WT_WIDTH]; 188 | end 189 | 8'b00100000:begin 190 | w2sch_rdata_0_0 = w2sch_rdata_w[(5*WT_BUF_WIDTH+1*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+0*WT_WIDTH]; 191 | w2sch_rdata_0_1 = w2sch_rdata_w[(5*WT_BUF_WIDTH+2*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+1*WT_WIDTH]; 192 | w2sch_rdata_0_2 = w2sch_rdata_w[(5*WT_BUF_WIDTH+3*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+2*WT_WIDTH]; 193 | w2sch_rdata_0_3 = w2sch_rdata_w[(5*WT_BUF_WIDTH+4*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+3*WT_WIDTH]; 194 | w2sch_rdata_1_0 = w2sch_rdata_w[(5*WT_BUF_WIDTH+5*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+4*WT_WIDTH]; 195 | w2sch_rdata_1_1 = w2sch_rdata_w[(5*WT_BUF_WIDTH+6*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+5*WT_WIDTH]; 196 | w2sch_rdata_1_2 = w2sch_rdata_w[(5*WT_BUF_WIDTH+7*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+6*WT_WIDTH]; 197 | w2sch_rdata_1_3 = w2sch_rdata_w[(5*WT_BUF_WIDTH+8*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+7*WT_WIDTH]; 198 | w2sch_rdata_2_0 = w2sch_rdata_w[(5*WT_BUF_WIDTH+9*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+8*WT_WIDTH]; 199 | w2sch_rdata_2_1 = w2sch_rdata_w[(5*WT_BUF_WIDTH+10*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+9*WT_WIDTH]; 200 | w2sch_rdata_2_2 = w2sch_rdata_w[(5*WT_BUF_WIDTH+11*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+10*WT_WIDTH]; 201 | w2sch_rdata_2_3 = w2sch_rdata_w[(5*WT_BUF_WIDTH+12*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+11*WT_WIDTH]; 202 | w2sch_rdata_3_0 = w2sch_rdata_w[(5*WT_BUF_WIDTH+13*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+12*WT_WIDTH]; 203 | w2sch_rdata_3_1 = w2sch_rdata_w[(5*WT_BUF_WIDTH+14*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+13*WT_WIDTH]; 204 | w2sch_rdata_3_2 = w2sch_rdata_w[(5*WT_BUF_WIDTH+15*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+14*WT_WIDTH]; 205 | w2sch_rdata_3_3 = w2sch_rdata_w[(5*WT_BUF_WIDTH+16*WT_WIDTH) - 1 : 5*WT_BUF_WIDTH+15*WT_WIDTH]; 206 | end 207 | 8'b01000000:begin 208 | w2sch_rdata_0_0 = w2sch_rdata_w[(6*WT_BUF_WIDTH+1*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+0*WT_WIDTH]; 209 | w2sch_rdata_0_1 = w2sch_rdata_w[(6*WT_BUF_WIDTH+2*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+1*WT_WIDTH]; 210 | w2sch_rdata_0_2 = w2sch_rdata_w[(6*WT_BUF_WIDTH+3*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+2*WT_WIDTH]; 211 | w2sch_rdata_0_3 = w2sch_rdata_w[(6*WT_BUF_WIDTH+4*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+3*WT_WIDTH]; 212 | w2sch_rdata_1_0 = w2sch_rdata_w[(6*WT_BUF_WIDTH+5*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+4*WT_WIDTH]; 213 | w2sch_rdata_1_1 = w2sch_rdata_w[(6*WT_BUF_WIDTH+6*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+5*WT_WIDTH]; 214 | w2sch_rdata_1_2 = w2sch_rdata_w[(6*WT_BUF_WIDTH+7*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+6*WT_WIDTH]; 215 | w2sch_rdata_1_3 = w2sch_rdata_w[(6*WT_BUF_WIDTH+8*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+7*WT_WIDTH]; 216 | w2sch_rdata_2_0 = w2sch_rdata_w[(6*WT_BUF_WIDTH+9*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+8*WT_WIDTH]; 217 | w2sch_rdata_2_1 = w2sch_rdata_w[(6*WT_BUF_WIDTH+10*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+9*WT_WIDTH]; 218 | w2sch_rdata_2_2 = w2sch_rdata_w[(6*WT_BUF_WIDTH+11*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+10*WT_WIDTH]; 219 | w2sch_rdata_2_3 = w2sch_rdata_w[(6*WT_BUF_WIDTH+12*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+11*WT_WIDTH]; 220 | w2sch_rdata_3_0 = w2sch_rdata_w[(6*WT_BUF_WIDTH+13*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+12*WT_WIDTH]; 221 | w2sch_rdata_3_1 = w2sch_rdata_w[(6*WT_BUF_WIDTH+14*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+13*WT_WIDTH]; 222 | w2sch_rdata_3_2 = w2sch_rdata_w[(6*WT_BUF_WIDTH+15*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+14*WT_WIDTH]; 223 | w2sch_rdata_3_3 = w2sch_rdata_w[(6*WT_BUF_WIDTH+16*WT_WIDTH) - 1 : 6*WT_BUF_WIDTH+15*WT_WIDTH]; 224 | end 225 | 8'b10000000:begin 226 | w2sch_rdata_0_0 = w2sch_rdata_w[(7*WT_BUF_WIDTH+1*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+0*WT_WIDTH]; 227 | w2sch_rdata_0_1 = w2sch_rdata_w[(7*WT_BUF_WIDTH+2*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+1*WT_WIDTH]; 228 | w2sch_rdata_0_2 = w2sch_rdata_w[(7*WT_BUF_WIDTH+3*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+2*WT_WIDTH]; 229 | w2sch_rdata_0_3 = w2sch_rdata_w[(7*WT_BUF_WIDTH+4*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+3*WT_WIDTH]; 230 | w2sch_rdata_1_0 = w2sch_rdata_w[(7*WT_BUF_WIDTH+5*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+4*WT_WIDTH]; 231 | w2sch_rdata_1_1 = w2sch_rdata_w[(7*WT_BUF_WIDTH+6*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+5*WT_WIDTH]; 232 | w2sch_rdata_1_2 = w2sch_rdata_w[(7*WT_BUF_WIDTH+7*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+6*WT_WIDTH]; 233 | w2sch_rdata_1_3 = w2sch_rdata_w[(7*WT_BUF_WIDTH+8*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+7*WT_WIDTH]; 234 | w2sch_rdata_2_0 = w2sch_rdata_w[(7*WT_BUF_WIDTH+9*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+8*WT_WIDTH]; 235 | w2sch_rdata_2_1 = w2sch_rdata_w[(7*WT_BUF_WIDTH+10*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+9*WT_WIDTH]; 236 | w2sch_rdata_2_2 = w2sch_rdata_w[(7*WT_BUF_WIDTH+11*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+10*WT_WIDTH]; 237 | w2sch_rdata_2_3 = w2sch_rdata_w[(7*WT_BUF_WIDTH+12*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+11*WT_WIDTH]; 238 | w2sch_rdata_3_0 = w2sch_rdata_w[(7*WT_BUF_WIDTH+13*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+12*WT_WIDTH]; 239 | w2sch_rdata_3_1 = w2sch_rdata_w[(7*WT_BUF_WIDTH+14*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+13*WT_WIDTH]; 240 | w2sch_rdata_3_2 = w2sch_rdata_w[(7*WT_BUF_WIDTH+15*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+14*WT_WIDTH]; 241 | w2sch_rdata_3_3 = w2sch_rdata_w[(7*WT_BUF_WIDTH+16*WT_WIDTH) - 1 : 7*WT_BUF_WIDTH+15*WT_WIDTH]; 242 | end 243 | default:begin 244 | w2sch_rdata_0_0 = 0; 245 | w2sch_rdata_0_1 = 0; 246 | w2sch_rdata_0_2 = 0; 247 | w2sch_rdata_0_3 = 0; 248 | w2sch_rdata_1_0 = 0; 249 | w2sch_rdata_1_1 = 0; 250 | w2sch_rdata_1_2 = 0; 251 | w2sch_rdata_1_3 = 0; 252 | w2sch_rdata_2_0 = 0; 253 | w2sch_rdata_2_1 = 0; 254 | w2sch_rdata_2_2 = 0; 255 | w2sch_rdata_2_3 = 0; 256 | w2sch_rdata_3_0 = 0; 257 | w2sch_rdata_3_1 = 0; 258 | w2sch_rdata_3_2 = 0; 259 | w2sch_rdata_3_3 = 0; 260 | end 261 | endcase 262 | end 263 | 264 | // weight ping-pong buffer instantiation 265 | generate 266 | for(idx_inst = 0; idx_inst < WT_GRP_NUM; idx_inst = idx_inst + 1)begin: buf_inst 267 | dp_ram_regout #( 268 | .KNOB_REGOUT (KNOB_REGOUT), 269 | .ADDR_WIDTH (WT_ADDR_WIDTH), 270 | .DATA_WIDTH (WT_BUF_WIDTH), 271 | .DATA_DEPTH (WT_BUF0_DEPTH) 272 | ) 273 | u_wt0_buf( //DNDM 274 | .clk (clk), 275 | .wr_addr (wt0_waddr), 276 | .wr_en (wt0_wen), 277 | .wr_data (wt0_wdata[(idx_inst+1)*WT_BUF_WIDTH - 1 : idx_inst*WT_BUF_WIDTH]), 278 | .rd_addr (wt0_raddr), 279 | .rd_en (wt0_ren[idx_inst]), 280 | .rd_data (wt0_rdata[(idx_inst+1)*WT_BUF_WIDTH - 1 : idx_inst*WT_BUF_WIDTH]) 281 | ); 282 | dp_ram_regout #( //SR 283 | .KNOB_REGOUT (KNOB_REGOUT), 284 | .ADDR_WIDTH (WT_ADDR_WIDTH), 285 | .DATA_WIDTH (WT_BUF_WIDTH), 286 | .DATA_DEPTH (WT_BUF1_DEPTH) 287 | ) 288 | u_wt1_buf( 289 | .clk (clk), 290 | .wr_addr (wt1_waddr), 291 | .wr_en (wt1_wen), 292 | .wr_data (wt1_wdata[(idx_inst+1)*WT_BUF_WIDTH - 1 : idx_inst*WT_BUF_WIDTH]), 293 | .rd_addr (wt1_raddr), 294 | .rd_en (wt1_ren[idx_inst]), 295 | .rd_data (wt1_rdata[(idx_inst+1)*WT_BUF_WIDTH - 1 : idx_inst*WT_BUF_WIDTH]) 296 | ); 297 | end 298 | endgenerate 299 | 300 | endmodule -------------------------------------------------------------------------------- /sim/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/openasic-org/xkDLA/bed44c45b0e9e4f0049bfef0bcc29a04522ca584/sim/.gitkeep -------------------------------------------------------------------------------- /sim/flist/filelist.f: -------------------------------------------------------------------------------- 1 | //top 2 | ../../rtl/top.v 3 | ../../rtl/ctrl_engine.v 4 | //scheduler 5 | ../../rtl/sch/scheduler.v 6 | ../../rtl/sch/addr_if.v 7 | ../../rtl/sch/sche_sub.v 8 | ../../rtl/sch/handshake_sche2pe.v 9 | //PE 10 | ../../rtl/pe_array/pe_array.v 11 | ../../rtl/pe_array/pe_ic.v 12 | ../../rtl/pe_array/pe2.v 13 | ../../rtl/pe_array/pe.v 14 | //PU 15 | ../../rtl/pu/pu_top.v 16 | ../../rtl/pu/pu_adder2.v 17 | ../../rtl/pu/pu_adder4.v 18 | ../../rtl/pu/pu_bias_add_pipe1.v 19 | ../../rtl/pu/pu_ic_add_pipe0.v 20 | ../../rtl/pu/pu_mul.v 21 | //../../rtl/pu/pu_relu_mul_pipe2.v 22 | //../../rtl/pu/pu_requant_pipe4.v 23 | ../../rtl/pu/pu_resi_add_pipe_p3.v 24 | ../../rtl/pu/pu_hbm_pipe.v 25 | ../../rtl/pu/pu_lbm_pipe.v 26 | //buf 27 | ../../rtl/dp_ram.v 28 | ../../rtl/dp_ram_regout.v 29 | ../../rtl/wt_buf.v 30 | ../../rtl/fe_buf.v 31 | ../../rtl/olp_buf.v 32 | ../../rtl/param_buf.v 33 | ../../rtl/res_buf.v 34 | //tb 35 | //../tb/tb_top.sv 36 | ../tb/tb_top_switch.sv 37 | //../tb/sub_bench/task.sv -------------------------------------------------------------------------------- /sim/tb/tb_addr_if.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module tb_addr_if; 3 | 4 | parameter IFM_WIDTH = 8; 5 | parameter SCH_COL_NUM = 40; 6 | parameter WT_WIDTH = 16; 7 | parameter PE_COL_NUM = 32; 8 | parameter PE_ROW_NUM = 4; 9 | parameter PE_IC_NUM = 4; 10 | parameter PE_OC_NUM = 4; 11 | parameter ADDR_WIDTH = 10; 12 | 13 | reg rstn; 14 | reg clk; 15 | // ctrl_i 16 | reg stack_switch; 17 | reg ctrl2sch_tile_start; 18 | reg pe2sch_rdy; 19 | reg [3:0] tile_loc; 20 | reg [3:0] ksize; 21 | reg [14:0] tile_in_h; 22 | reg [14:0] tile_out_h; 23 | reg [14:0] tile_in_w; 24 | reg [14:0] tile_out_w; 25 | reg [14:0] tile_in_c; 26 | reg [14:0] tile_out_c; 27 | reg [99:0] pu2sch_olp_addr; 28 | 29 | 30 | // rd addr 31 | wire [3:0] fe_olp_buf_rd_en; 32 | wire [ADDR_WIDTH - 1 : 0] fe_buf_rd_addr_0; 33 | wire [ADDR_WIDTH - 1 : 0] fe_buf_rd_addr_1; 34 | wire [ADDR_WIDTH - 1 : 0] fe_buf_rd_addr_2; 35 | wire [ADDR_WIDTH - 1 : 0] fe_buf_rd_addr_3; 36 | wire [ADDR_WIDTH - 1 : 0] olp_buf_rd_addr_0; 37 | wire [ADDR_WIDTH - 1 : 0] olp_buf_rd_addr_1; 38 | wire [ADDR_WIDTH - 1 : 0] olp_buf_rd_addr_2; 39 | wire [ADDR_WIDTH - 1 : 0] olp_buf_rd_addr_3; 40 | wire [7 : 0] wt_buf_rd_en; 41 | wire [ADDR_WIDTH - 1 : 0] wt_buf_rd_addr; 42 | 43 | wire row_done; 44 | wire sch2pe_vld; 45 | wire [PE_COL_NUM - 1 : 0] mux_col_vld; 46 | wire [PE_ROW_NUM - 1 : 0] mux_row_vld; 47 | wire [PE_IC_NUM - 1 : 0] mux_array_vld; 48 | wire [3 : 0] cnt_ksize_r; 49 | wire [2 : 0] cur_state_r; 50 | wire [2 : 0] addr_offset_r; 51 | 52 | 53 | 54 | initial begin 55 | clk =1'b0; 56 | forever #5 clk <= ~clk; 57 | end 58 | 59 | initial begin 60 | clk <= 1'b0; 61 | rstn <= 1'b1; 62 | #22 63 | rstn <= 1'b0; 64 | #17 65 | rstn <= 1'b1; 66 | #20 67 | stack_switch <= 0; 68 | ctrl2sch_tile_start <= 1; 69 | pe2sch_rdy <= 1; 70 | tile_loc <= 0001; 71 | ksize <= 3; 72 | tile_in_h <= 10; 73 | tile_out_h <= 9; 74 | tile_in_w <= 32; 75 | tile_out_w <= 32; 76 | tile_in_c <= 9; 77 | tile_out_c <= 8; 78 | pu2sch_olp_addr <= 0; 79 | #10 80 | ctrl2sch_tile_start <= 0; 81 | #2000 82 | ctrl2sch_tile_start <= 1; 83 | #10 84 | ctrl2sch_tile_start <= 0; 85 | #2000 86 | $finish; 87 | end 88 | 89 | // tile_loc == 0010; 90 | /* 91 | initial begin 92 | clk <= 1'b0; 93 | rstn <= 1'b1; 94 | #22 95 | rstn <= 1'b0; 96 | #17 97 | rstn <= 1'b1; 98 | #20 99 | stack_switch <= 0; 100 | ctrl2sch_tile_start <= 1; 101 | pe2sch_rdy <= 1; 102 | tile_loc <= 0010; 103 | ksize <= 3; 104 | tile_in_h <= 10; 105 | tile_out_h <= 9; 106 | tile_in_w <= 32; 107 | tile_out_w <= 32; 108 | tile_in_c <= 9; 109 | tile_out_c <= 8; 110 | pu2sch_olp_addr <= 0; 111 | #10 112 | ctrl2sch_tile_start <= 0; 113 | #2000 114 | ctrl2sch_tile_start <= 1; 115 | #10 116 | ctrl2sch_tile_start <= 0; 117 | #2000 118 | $finish; 119 | end*/ 120 | 121 | // tile_loc == 0000; 122 | /* 123 | initial begin 124 | clk <= 1'b0; 125 | rstn <= 1'b1; 126 | #22 127 | rstn <= 1'b0; 128 | #17 129 | rstn <= 1'b1; 130 | #20 131 | stack_switch <= 0; 132 | ctrl2sch_tile_start <= 1; 133 | pe2sch_rdy <= 1; 134 | tile_loc <= 0000; 135 | ksize <= 3; 136 | tile_in_h <= 10; 137 | tile_out_h <= 8; 138 | tile_in_w <= 32; 139 | tile_out_w <= 32; 140 | tile_in_c <= 8; 141 | tile_out_c <= 8; 142 | pu2sch_olp_addr <= 0; 143 | #10 144 | ctrl2sch_tile_start <= 0; 145 | #2000 146 | ctrl2sch_tile_start <= 1; 147 | #10 148 | ctrl2sch_tile_start <= 0; 149 | #2000 150 | $finish; 151 | end 152 | */ 153 | 154 | 155 | addr_if #( 156 | .IFM_WIDTH (8), 157 | .SCH_COL_NUM (40), 158 | .WT_WIDTH (16), 159 | .PE_COL_NUM (32), 160 | .PE_ROW_NUM (4), 161 | .PE_IC_NUM (4), 162 | .PE_OC_NUM (4), 163 | .ADDR_WIDTH (10) 164 | ) 165 | u0_addr_if 166 | ( 167 | .rstn (rstn), 168 | .clk (clk), 169 | 170 | // ctrl_i 171 | .stack_switch (stack_switch), 172 | .ctrl2sch_tile_start (ctrl2sch_tile_start), 173 | .pe2sch_rdy (pe2sch_rdy), 174 | .tile_loc (tile_loc), 175 | .ksize (ksize), 176 | .tile_in_h (tile_in_h), 177 | .tile_out_h (tile_out_h), 178 | .tile_in_w (tile_in_w), 179 | .tile_out_w (tile_out_w), 180 | .tile_in_c (tile_in_c), 181 | .tile_out_c (tile_out_c), 182 | .pu2sch_olp_addr (pu2sch_olp_addr), 183 | 184 | //buffer rd 185 | .fe_olp_buf_rd_en (fe_olp_buf_rd_en), 186 | .fe_buf_rd_addr_0 (fe_buf_rd_addr_0), 187 | .fe_buf_rd_addr_1 (fe_buf_rd_addr_1), 188 | .fe_buf_rd_addr_2 (fe_buf_rd_addr_2), 189 | .fe_buf_rd_addr_3 (fe_buf_rd_addr_3), 190 | .olp_buf_rd_addr_0 (olp_buf_rd_addr_0), 191 | .olp_buf_rd_addr_1 (olp_buf_rd_addr_1), 192 | .olp_buf_rd_addr_2 (olp_buf_rd_addr_2), 193 | .olp_buf_rd_addr_3 (olp_buf_rd_addr_3), 194 | .wt_buf_rd_en (wt_buf_rd_en), 195 | .wt_buf_rd_addr (wt_buf_rd_addr), 196 | 197 | .row_done (row_done), 198 | .sch2pe_vld (sch2pe_vld), 199 | .mux_col_vld (mux_col_vld), 200 | .mux_row_vld (mux_row_vld), 201 | .mux_array_vld (mux_array_vld), 202 | .cnt_ksize_r (cnt_ksize_r), 203 | .cur_state_r (cur_state_r), 204 | .addr_offset_r (addr_offset_r) 205 | ); 206 | 207 | `ifdef DUMP_VPD 208 | initial begin 209 | $display("Dump VPD wave!"); 210 | $vcdpluson(); 211 | end 212 | `endif 213 | 214 | initial begin 215 | $display("Dump fsdb wave!"); 216 | $fsdbDumpfile("tb.fsdb"); 217 | $fsdbDumpvars; 218 | end 219 | 220 | initial begin 221 | $display("\033[30;41m Hello error!\033[0m"); 222 | $display("\033[30;42m Hello pass!\033[0m"); 223 | $display("\033[30;43m Hello warning!\033[0m"); 224 | 225 | end 226 | 227 | `ifdef GLS_SIM 228 | initial begin 229 | $sdf_annotate("../../netlist_sim/sdf/TOP.sdf",tb.U_TOP,,"sdf.log","TYPICAL"); 230 | end 231 | `endif 232 | 233 | endmodule 234 | -------------------------------------------------------------------------------- /sim/tb/tb_ctrl_engine.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | `define PERIOD 8 3 | 4 | module tb_ctrl_engine; 5 | parameter REG_IFMH_WIDTH = 10 ; 6 | parameter REG_IFMW_WIDTH = 10 ; 7 | parameter REG_TILEH_WIDTH = 6 ; 8 | parameter REG_TNY_WIDTH = 6 ; 9 | parameter REG_TNX_WIDTH = 6 ; 10 | parameter REG_TLW_WIDTH = 6 ; 11 | parameter REG_TLH_WIDTH = 6 ; 12 | parameter TILE_BASE_W = 32 ; 13 | parameter REG_IH_WIDTH = 6 ; 14 | parameter REG_OH_WIDTH = 6 ; 15 | parameter REG_IW_WIDTH = 6 ; 16 | parameter REG_OW_WIDTH = 6 ; 17 | parameter REG_IC_WIDTH = 6 ; 18 | parameter REG_OC_WIDTH = 6 ; 19 | parameter REG_AF_WIDTH = 1 ; 20 | parameter REG_HBM_SFT_WIDTH = 6 ; 21 | parameter REG_LBM_SFT_WIDTH = 6 ; 22 | 23 | logic clk ; 24 | logic rst_n ; 25 | logic [ 32 - 1 : 0] ctrl_reg ; 26 | logic [ 32 - 1 : 0] state_reg ; 27 | logic [ 32 - 1 : 0] reg0 ; 28 | logic [ 32 - 1 : 0] reg1 ; 29 | logic layer_done ; 30 | logic layer_start ; 31 | logic [ 1 : 0] stat_ctrl ; 32 | logic [ 2 : 0] cnt_layer ; 33 | logic tile_switch_r ; 34 | logic model_switch_r ; 35 | logic tile_switch ; 36 | logic model_switch ; 37 | logic model_switch_layer ; 38 | logic nn_proc ; 39 | logic [ REG_TNX_WIDTH - 1 : 0] tile_tot_num_x ; 40 | logic [ REG_IH_WIDTH - 1 : 0] tile_in_h ; 41 | logic [ REG_OH_WIDTH - 1 : 0] tile_out_h ; 42 | logic [ REG_IW_WIDTH - 1 : 0] tile_in_w ; 43 | logic [ REG_OW_WIDTH - 1 : 0] tile_out_w ; 44 | logic [ REG_IC_WIDTH - 1 : 0] tile_in_c ; 45 | logic [ REG_OC_WIDTH - 1 : 0] tile_out_c ; 46 | logic [ 2 : 0] ksize ; 47 | logic [ 3 : 0] tile_loc ; 48 | logic x4_shuffle_vld ; 49 | logic [ REG_AF_WIDTH - 1 : 0] prl_vld ; 50 | logic [ 1 : 0] res_proc_type ; 51 | logic [ REG_HBM_SFT_WIDTH - 1 : 0] pu_hbm_shift ; 52 | logic [ REG_LBM_SFT_WIDTH - 1 : 0] pu_lbm_shift ; 53 | logic buf_pp_flag ; 54 | 55 | // logic moniter_done ; 56 | 57 | // event nxt_tile_event ; 58 | // event nxt_stack_event; 59 | // event nxt_reg_event; 60 | // event nxt_loading_event; 61 | // event nxt_wt_param_event; 62 | 63 | /******************************************************************************/ 64 | /************************************** DUT ***********************************/ 65 | /******************************************************************************/ 66 | ctrl_engine #( 67 | .REG_IFMH_WIDTH (REG_IFMH_WIDTH ), 68 | .REG_IFMW_WIDTH (REG_IFMW_WIDTH ), 69 | .REG_TILEH_WIDTH (REG_TILEH_WIDTH ), 70 | .REG_TNY_WIDTH (REG_TNY_WIDTH ), 71 | .REG_TNX_WIDTH (REG_TNX_WIDTH ), 72 | .REG_TLW_WIDTH (REG_TLW_WIDTH ), 73 | .REG_TLH_WIDTH (REG_TLH_WIDTH ), 74 | .TILE_BASE_W (TILE_BASE_W ), 75 | .REG_IH_WIDTH (REG_IH_WIDTH ), 76 | .REG_OH_WIDTH (REG_OH_WIDTH ), 77 | .REG_IW_WIDTH (REG_IW_WIDTH ), 78 | .REG_OW_WIDTH (REG_OW_WIDTH ), 79 | .REG_IC_WIDTH (REG_IC_WIDTH ), 80 | .REG_OC_WIDTH (REG_OC_WIDTH ), 81 | .REG_AF_WIDTH (REG_AF_WIDTH ), 82 | .REG_HBM_SFT_WIDTH (REG_HBM_SFT_WIDTH ), 83 | .REG_LBM_SFT_WIDTH (REG_LBM_SFT_WIDTH ) 84 | ) 85 | u_ctrl_engine ( 86 | .clk (clk ), 87 | .rst_n (rst_n ), 88 | .ctrl_reg (ctrl_reg ), 89 | .state_reg (state_reg ), 90 | .reg0 (reg0 ), 91 | .reg1 (reg1 ), 92 | .layer_done (layer_done ), 93 | .layer_start (layer_start ), 94 | .stat_ctrl (stat_ctrl ), 95 | .cnt_layer (cnt_layer ), 96 | .tile_switch_r (tile_switch_r ), 97 | .model_switch_r (model_switch_r ), 98 | .tile_switch (tile_switch ), 99 | .model_switch (model_switch ), 100 | .model_switch_layer (model_switch_layer ), 101 | .nn_proc (nn_proc ), 102 | .tile_tot_num_x (tile_tot_num_x ), 103 | .tile_in_h (tile_in_h ), 104 | .tile_out_h (tile_out_h ), 105 | .tile_in_w (tile_in_w ), 106 | .tile_out_w (tile_out_w ), 107 | .tile_in_c (tile_in_c ), 108 | .tile_out_c (tile_out_c ), 109 | .ksize (ksize ), 110 | .tile_loc (tile_loc ), 111 | .x4_shuffle_vld (x4_shuffle_vld ), 112 | .prl_vld (prl_vld ), 113 | .res_proc_type (res_proc_type ), 114 | .pu_hbm_shift (pu_hbm_shift ), 115 | .pu_lbm_shift (pu_lbm_shift ), 116 | .buf_pp_flag (buf_pp_flag ) 117 | ); 118 | 119 | /******************************************************************************/ 120 | /**************************** Clock Value Generation **************************/ 121 | /******************************************************************************/ 122 | initial begin 123 | clk = 1'b1; 124 | end 125 | 126 | always #(`PERIOD/2) clk = ~clk; 127 | 128 | /*******************************************************************************/ 129 | /******************************* Test Flow Generation **************************/ 130 | /*******************************************************************************/ 131 | initial begin 132 | system_rst_n(); 133 | wait_half_cycle(); 134 | set_reg(); 135 | end 136 | 137 | // finish 138 | initial begin 139 | wait(state_reg == 32'h00000001); 140 | #(`PERIOD*1000) $display("Simulation DONE!"); 141 | $finish; 142 | end 143 | 144 | initial begin 145 | #(`PERIOD*1000000) $display("Simulation Timeout!"); 146 | $finish; 147 | end 148 | 149 | // nxt_loading_event 150 | /* 151 | initial begin 152 | forever begin 153 | @(negedge u_top.tile_switch_r); 154 | ->nxt_tile_event; 155 | wait(u_top.u_fe_buf.layer_done && u_top.u_fe_buf.tile_switch_r); 156 | begin 157 | -> nxt_loading_event; 158 | end 159 | end 160 | end*/ 161 | // nxt_loading_event 162 | initial begin 163 | forever begin 164 | @(!rst_n) 165 | layer_done <= 0; 166 | end 167 | end 168 | 169 | initial begin 170 | forever begin 171 | @(posedge u_ctrl_engine.layer_start); 172 | wait_some_cycles(); 173 | layer_done <= 1; 174 | wait_one_cycle(); 175 | layer_done <= 0; 176 | end 177 | end 178 | 179 | /* 180 | initial begin 181 | #(`PERIOD*1010) -> nxt_loading_event; 182 | end*/ 183 | 184 | // initial begin 185 | // #(`PERIOD*30) -> nxt_loading_event; 186 | // end 187 | 188 | // //nxt_wt_param_event 189 | 190 | // initial begin 191 | // #(`PERIOD*40) -> nxt_wt_param_event; 192 | // end 193 | 194 | 195 | // // nxt_reg_event 196 | // initial begin 197 | // forever begin 198 | // @(posedge u_top.layer_done); 199 | // -> nxt_reg_event; 200 | // end 201 | // end 202 | 203 | // initial begin 204 | // #(`PERIOD*1000) -> nxt_reg_event; 205 | // end 206 | 207 | 208 | /******************************************************************************/ 209 | /********************************** moniter ***********************************/ 210 | /******************************************************************************/ 211 | // integer golden_buf; 212 | // integer golden_i; 213 | // integer golden_j; 214 | // reg [REG_IH_WIDTH : 0] fe_oh; 215 | // reg [REG_IC_WIDTH - 1 : 0] fe_oc; 216 | // reg [REG_OH_WIDTH - 1 : 0] golden_oh; 217 | // reg [REG_OC_WIDTH - 1 : 0] golden_oc; 218 | // reg [REG_OC_WIDTH - 1 : 0] num_oc; 219 | // reg [AXI2F_DATA_WIDTH - 1 : 0] axi2f_rdata_golden; 220 | // reg [AXI2F_DATA_WIDTH - 1 : 0] axi2f_rdata_golden_r; 221 | // reg [AXI2F_ADDR_WIDTH - 1 : 0] axi2f_raddr_r; 222 | // reg axi2f_ren_r; 223 | // reg moniter_done; 224 | // reg lst_tile_done_r; 225 | // reg lst_tile_done_r2; 226 | // wire lst_tile_done; 227 | // reg layer_done_r; 228 | // //reg [AXI2F_ADDR_WIDTH - 1 : 0] axi2f_raddr_golden; 229 | 230 | // always @(posedge clk or negedge rst_n) 231 | // begin 232 | // if(!rst_n) lst_tile_done_r <= 0; 233 | // else if(reg0 == 32'hffffffff && reg1 == 32'hffffffff && ctrl_reg == 32'h00000001) 234 | // lst_tile_done_r <= 1; 235 | // end 236 | 237 | // always @(posedge clk) lst_tile_done_r2 <= lst_tile_done_r; 238 | // always @(posedge clk) layer_done_r <= u_top.u_fe_buf.layer_done; 239 | 240 | // assign lst_tile_done = lst_tile_done_r2 ^ lst_tile_done_r; 241 | 242 | // initial begin 243 | // forever begin 244 | // wait((layer_done_r && u_top.u_ctrl_engine.tile_switch) || lst_tile_done) begin 245 | // golden_buf = $fopen(`GOLDEN_BUF_FILE ,"r" ); 246 | 247 | // $fscanf(golden_buf, "%d", fe_oc); 248 | // $fscanf(golden_buf, "%d", fe_oh); 249 | 250 | // for(golden_i = 0; golden_i < (((fe_oc + 3) >> 2) << 2); golden_i = golden_i + 1) begin 251 | // $fscanf(golden_buf, "%d", num_oc); 252 | // for(golden_j = 0; golden_j < ((fe_oh + 3) >> 2); golden_j = golden_j + 1) begin 253 | // wait_one_cycle(); 254 | // $fscanf(golden_buf, "%h", axi2f_rdata_golden[AXI2F_DATA_WIDTH - 1 : AXI2F_DATA_WIDTH - FE_BUF_WIDTH]); 255 | // $fscanf(golden_buf, "%h", axi2f_rdata_golden[AXI2F_DATA_WIDTH - FE_BUF_WIDTH - 1 : AXI2F_DATA_WIDTH - 2*FE_BUF_WIDTH]); 256 | // $fscanf(golden_buf, "%h", axi2f_rdata_golden[AXI2F_DATA_WIDTH - 2*FE_BUF_WIDTH - 1 : AXI2F_DATA_WIDTH - 3*FE_BUF_WIDTH]); 257 | // $fscanf(golden_buf, "%h", axi2f_rdata_golden[AXI2F_DATA_WIDTH - 3*FE_BUF_WIDTH - 1 : 0]); 258 | // axi2f_raddr[AXI2F_ADDR_WIDTH - 1 : AXI2F_ADDR_WIDTH - 2] = num_oc[1:0]; 259 | // axi2f_raddr[AXI2F_ADDR_WIDTH - 3 : 0] = num_oc[REG_IC_WIDTH - 1 : 2] * ((fe_oh + 3) >> 2) + golden_j; 260 | // axi2f_ren = 1; 261 | // end 262 | // end 263 | 264 | // wait_one_cycle(); 265 | // axi2f_ren = 0; 266 | // moniter_done = 1; 267 | // wait_one_cycle(); 268 | // moniter_done = 0; 269 | // end 270 | // end 271 | // end 272 | 273 | // initial begin 274 | // forever @(posedge clk) begin 275 | // axi2f_rdata_golden_r <= axi2f_rdata_golden; 276 | // axi2f_ren_r <= axi2f_ren; 277 | // axi2f_raddr_r <= axi2f_raddr; 278 | // end 279 | // end 280 | 281 | // initial begin 282 | // forever begin 283 | // @(posedge clk) begin 284 | // if(axi2f_ren_r == 1 && (axi2f_rdata_golden_r != axi2f_rdata)) begin 285 | // $display("\033[30;41m mismatch happened at time %0t\033[0m", $time); 286 | // $display("the mismatch in buffer %d", axi2f_raddr_r[AXI2F_ADDR_WIDTH - 1 : AXI2F_ADDR_WIDTH - 2]); 287 | // $display("the mismatch addr is %d", axi2f_raddr_r[AXI2F_ADDR_WIDTH - 3 : 0]); 288 | // //#(`PERIOD*100) $finish; 289 | // end 290 | // end 291 | // end 292 | // end 293 | 294 | /*******************************************************************************/ 295 | /********************** Task Definition in Testbench ***************************/ 296 | /*******************************************************************************/ 297 | //`include "../tb/sub_bench/task.sv" 298 | task wait_some_cycles(); 299 | #(`PERIOD*4); 300 | endtask 301 | 302 | task wait_one_cycle(); 303 | #(`PERIOD); 304 | endtask 305 | 306 | task wait_half_cycle(); 307 | #(`PERIOD/2); 308 | endtask 309 | 310 | task wait_quarter_cycle(); 311 | #(`PERIOD/4); 312 | endtask 313 | 314 | task system_rst_n(); 315 | wait_some_cycles(); 316 | rst_n <= 1; 317 | wait_some_cycles(); 318 | rst_n <= 0; 319 | wait_some_cycles(); 320 | rst_n <= 1; 321 | endtask 322 | 323 | task set_reg(); 324 | ctrl_reg <= 32'h00000002; 325 | wait_one_cycle(); 326 | ctrl_reg <= 32'h00000000; 327 | wait_some_cycles(); 328 | // reg0 <= 32'h0000a028; //40*40 329 | // reg1 <= 32'h082020a0; 330 | reg0 <= 32'h000873C0; //960*540 331 | reg1 <= 32'h1C01F460; 332 | wait_one_cycle(); 333 | ctrl_reg <= 32'h00000003; 334 | wait_one_cycle(); 335 | ctrl_reg <= 32'h00000000; 336 | endtask 337 | 338 | // task loading_fe_buf(); 339 | // //------------------------------------------------ 340 | // //ih(h) 341 | // //ic(h) 342 | // //num ic(h) 343 | // //ic0 fea0_0 data(256'h) 344 | // //ic0 fea0_1 data(256'h) 345 | // //ic0 fea0_2 data(256'h) 346 | // //ic0 fea0_3 data(256'h) 347 | // //... 348 | // //ic0 fea0_3 data(256'h) h/4 (fill 0 when h/4 != 0) 349 | // //num ic(h) 350 | // //ic1 fea1_0 data(256'h) 351 | // //... 352 | // //------------------------------------------------- 353 | // integer fe_buf; 354 | // integer fe_i; 355 | // integer fe_j; 356 | // reg [REG_IH_WIDTH : 0] fe_ih; 357 | // reg [REG_IC_WIDTH - 1 : 0] fe_ic; 358 | // reg [REG_IC_WIDTH - 1 : 0] num_ic; 359 | 360 | // fe_buf = $fopen( `FE_BUF_FILE ,"r" ); 361 | 362 | // forever begin 363 | // @(nxt_loading_event); 364 | 365 | // $fscanf(fe_buf, "%d", fe_ih); 366 | // $fscanf(fe_buf, "%d", fe_ic); 367 | 368 | // for(fe_i = 0; fe_i < (((fe_ic + 3) >> 2) << 2); fe_i = fe_i + 1) begin 369 | // $fscanf(fe_buf, "%d", num_ic); 370 | // for(fe_j = 0; fe_j < ((fe_ih + 3) >> 2); fe_j = fe_j + 1) begin 371 | // wait_one_cycle(); 372 | // $fscanf(fe_buf, "%h", axi2f_wdata[AXI2F_DATA_WIDTH - 1 : AXI2F_DATA_WIDTH - FE_BUF_WIDTH]); 373 | // $fscanf(fe_buf, "%h", axi2f_wdata[AXI2F_DATA_WIDTH - FE_BUF_WIDTH - 1 : AXI2F_DATA_WIDTH - 2*FE_BUF_WIDTH]); 374 | // $fscanf(fe_buf, "%h", axi2f_wdata[AXI2F_DATA_WIDTH - 2*FE_BUF_WIDTH - 1 : AXI2F_DATA_WIDTH - 3*FE_BUF_WIDTH]); 375 | // $fscanf(fe_buf, "%h", axi2f_wdata[AXI2F_DATA_WIDTH - 3*FE_BUF_WIDTH - 1 : 0]); 376 | // axi2f_waddr[AXI2F_ADDR_WIDTH - 1 : AXI2F_ADDR_WIDTH - 2] <= num_ic[1:0]; 377 | // axi2f_waddr[AXI2F_ADDR_WIDTH - 3 : 0] <= num_ic[REG_IC_WIDTH - 1 : 2] * ((fe_ih + 3) >> 2) + fe_j; 378 | // axi2f_wen = 1; 379 | // end 380 | // end 381 | 382 | // wait_one_cycle(); 383 | // axi2f_wen = 0; 384 | // end 385 | 386 | // $fclose(fe_buf); 387 | // endtask 388 | 389 | // task loading_wt_buf(); 390 | // //-------------------------------------------------------- 391 | // //the first line ceil(num of wt line) 392 | // //there are 16 wt_data every line, the data arrangement 393 | // //is ic0oc0, ic0oc1, ... , ic1oc0, ... , ic3oc3(8'h). 394 | // //fill 0 when ic or oc unvalid. 395 | // //the vertical sequence is ksize * ksize, ic, oc, h, layer 396 | // //-------------------------------------------------------- 397 | // integer wt_buf; 398 | // integer i, j, k; 399 | // reg [15 - 1 : 0] num_wt; 400 | // reg [6 - 1 : 0] num_layer; 401 | // reg [WT_BUF_WIDTH - 1 : 0] wt_data_0, wt_data_1, wt_data_2, wt_data_3, wt_data_4, wt_data_5, wt_data_6, wt_data_7; 402 | // reg [WT_BUF_WIDTH - 1 : 0] wt_data_0_r, wt_data_1_r, wt_data_2_r, wt_data_3_r, wt_data_4_r, wt_data_5_r, wt_data_6_r, wt_data_7_r; 403 | 404 | // wt_buf = $fopen(`WT_BUF_FILE, "r"); 405 | 406 | // forever begin 407 | // @(nxt_wt_param_event); 408 | 409 | // $fscanf(wt_buf, "%h", num_wt); 410 | 411 | // for(i = 0; i < ((num_wt + 7) >> 3); i = i + 1) begin 412 | // wait_one_cycle(); 413 | // $fscanf(wt_buf, "%h", wt_data_0); 414 | // $fscanf(wt_buf, "%h", wt_data_1); 415 | // $fscanf(wt_buf, "%h", wt_data_2); 416 | // $fscanf(wt_buf, "%h", wt_data_3); 417 | // $fscanf(wt_buf, "%h", wt_data_4); 418 | // $fscanf(wt_buf, "%h", wt_data_5); 419 | // $fscanf(wt_buf, "%h", wt_data_6); 420 | // $fscanf(wt_buf, "%h", wt_data_7); 421 | // for(k = 0; k < 16; k++) begin 422 | // wt_data_0_r[k*WT_WIDTH +:WT_WIDTH] = wt_data_0[(15-k)*WT_WIDTH +:WT_WIDTH]; 423 | // wt_data_1_r[k*WT_WIDTH +:WT_WIDTH] = wt_data_1[(15-k)*WT_WIDTH +:WT_WIDTH]; 424 | // wt_data_2_r[k*WT_WIDTH +:WT_WIDTH] = wt_data_2[(15-k)*WT_WIDTH +:WT_WIDTH]; 425 | // wt_data_3_r[k*WT_WIDTH +:WT_WIDTH] = wt_data_3[(15-k)*WT_WIDTH +:WT_WIDTH]; 426 | // wt_data_4_r[k*WT_WIDTH +:WT_WIDTH] = wt_data_4[(15-k)*WT_WIDTH +:WT_WIDTH]; 427 | // wt_data_5_r[k*WT_WIDTH +:WT_WIDTH] = wt_data_5[(15-k)*WT_WIDTH +:WT_WIDTH]; 428 | // wt_data_6_r[k*WT_WIDTH +:WT_WIDTH] = wt_data_6[(15-k)*WT_WIDTH +:WT_WIDTH]; 429 | // wt_data_7_r[k*WT_WIDTH +:WT_WIDTH] = wt_data_7[(15-k)*WT_WIDTH +:WT_WIDTH]; 430 | // end 431 | // axi2w_wdata = {wt_data_0_r, wt_data_1_r, wt_data_2_r, wt_data_3_r, wt_data_4_r, wt_data_5_r, wt_data_6_r, wt_data_7_r}; 432 | // axi2w_waddr = i; 433 | // axi2w_wen = 1; 434 | // end 435 | 436 | // wait_one_cycle(); 437 | // axi2w_wen = 0; 438 | // end 439 | 440 | // $fclose(wt_buf); 441 | // endtask 442 | 443 | // task loading_param_buf(); 444 | // //--------------------------- 445 | // //ceil(oc/4)*4 446 | // //bias,LBM,HBM (16'h*3) h0,oc0 447 | // //bias,LBM,HBM (16'h*3) h0,oc1 448 | // //bias,LBM,HBM (16'h*3) h0,oc2 449 | // //bias,LBM,HBM (16'h*3) h0,oc3 450 | // //bias,LBM,HBM (16'h*3) h0,oc4 451 | // //... 452 | // //... 453 | // //ceil(oc/4)*4 next_layer 454 | // //... 455 | // //---------------------------- 456 | // integer param_buf; 457 | // integer i, j; 458 | // reg [6 - 1 : 0] num_layer; 459 | // reg [14:0] num_oc; 460 | 461 | // param_buf = $fopen(`PARAM_BUF_FILE, "r"); 462 | 463 | // forever begin 464 | // @(nxt_wt_param_event); 465 | 466 | // $fscanf(param_buf, "%h", num_layer); 467 | 468 | // for(j = 0; j < num_layer; j = j + 1) begin 469 | 470 | // $fscanf(param_buf, "%d", num_oc); 471 | 472 | // for(i = 0; i < ((num_oc + 3) >> 2); i = i + 1) begin 473 | // wait_one_cycle(); 474 | // $fscanf(param_buf, "%h", axi2p_wdata[BIAS_DATA_WIDTH+HBM_DATA_WIDTH+LBM_DATA_WIDTH - 1 : 0]); 475 | // $fscanf(param_buf, "%h", axi2p_wdata[2*(BIAS_DATA_WIDTH+HBM_DATA_WIDTH+LBM_DATA_WIDTH) - 1 : BIAS_DATA_WIDTH+HBM_DATA_WIDTH+LBM_DATA_WIDTH]); 476 | // $fscanf(param_buf, "%h", axi2p_wdata[3*(BIAS_DATA_WIDTH+HBM_DATA_WIDTH+LBM_DATA_WIDTH) - 1 : 2*(BIAS_DATA_WIDTH+HBM_DATA_WIDTH+LBM_DATA_WIDTH)]); 477 | // $fscanf(param_buf, "%h", axi2p_wdata[4*(BIAS_DATA_WIDTH+HBM_DATA_WIDTH+LBM_DATA_WIDTH) - 1 : 3*(BIAS_DATA_WIDTH+HBM_DATA_WIDTH+LBM_DATA_WIDTH)]); 478 | // axi2p_waddr = j * ((num_oc + 3) >> 2) + i; 479 | // axi2p_wen = 1; 480 | // end 481 | // end 482 | 483 | // wait_one_cycle(); 484 | // axi2p_wen = 0; 485 | // end 486 | 487 | // $fclose(param_buf); 488 | // endtask 489 | 490 | // task loading_reg(); 491 | // //------------------------- 492 | // //reg0(32'h) 493 | // //reg1(32'h) 494 | // //ctrl_reg(32'h) 495 | // //...(next layer) 496 | // //------------------------- 497 | // integer reg_file; 498 | // integer i; 499 | // reg [14:0] num_layer; 500 | 501 | // reg_file = $fopen(`REG_FILE, "r"); 502 | 503 | // forever begin 504 | // @(nxt_reg_event) 505 | // //for(i = 0; i < num_layer - 1; i = i + 1) begin 506 | // $fscanf(reg_file, "%h", reg0); 507 | // $fscanf(reg_file, "%h", reg1); 508 | // wait_one_cycle(); 509 | // $fscanf(reg_file, "%h", ctrl_reg); 510 | // //end 511 | // end 512 | 513 | // $fclose(reg_file); 514 | // endtask 515 | 516 | /*******************************************************************************/ 517 | /****************************** dump wave **************************************/ 518 | /*******************************************************************************/ 519 | `ifdef DUMP_VPD 520 | initial begin 521 | $display("Dump VPD wave!"); 522 | $vcdpluson(); 523 | end 524 | `endif 525 | 526 | initial begin 527 | $display("Dump fsdb wave!"); 528 | $fsdbDumpfile("tb.fsdb"); 529 | $fsdbDumpvars; 530 | end 531 | 532 | endmodule 533 | -------------------------------------------------------------------------------- /sim/tb/tb_ppp.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | 4 | 5 | 6 | 7 | module tb_ppp; 8 | 9 | parameter IMAGE_WIDTH = 'd1024; 10 | parameter IMGW_WIDTH = 'd11; 11 | parameter IMGH_WIDTH = 'd11; 12 | parameter ISP_DATA_WIDTH = 'd32 * 'd8 *'d3; 13 | parameter ISP_ADDR_WIDTH = 'd10; 14 | parameter DLA_ADDR_WIDTH = 'd10; 15 | parameter DLA_DATA_WIDTH = 'd32 * 'd8 * 'd4; 16 | parameter DATA_WIDTH = 'd32 * 'd8; 17 | parameter ADDR_WIDTH = 'd10; 18 | parameter DATA_DEPTH = 'd256; 19 | parameter CLK_FULL = 'd10; 20 | parameter CLK_HALF = 'd5; 21 | 22 | 23 | 24 | reg rst_n ; 25 | reg clk ; 26 | reg [IMGW_WIDTH -1: 0] img_width_i ; 27 | reg [IMGH_WIDTH -1: 0] img_height_i ; 28 | // 29 | reg top_start_i ; 30 | // isp - ppp interface 31 | reg isp_rchn_i ; 32 | reg isp_resp_i ; 33 | wire isp_rdy_o ; 34 | reg isp_done_i ; 35 | wire [ISP_DATA_WIDTH -1: 0] isp_rdata_o ; 36 | reg [ISP_ADDR_WIDTH -1: 0] isp_raddr_i ; 37 | reg isp_ren_i ; 38 | reg [ISP_DATA_WIDTH -1: 0] isp_wdata_i ; 39 | reg [ISP_ADDR_WIDTH -1: 0] isp_waddr_i ; 40 | reg isp_wen_i ; 41 | reg isp_wchn_i ; 42 | // dla - ppp interface 43 | reg dla_resp_i ; 44 | wire dla_rdy_o ; 45 | reg dla_done_i ; 46 | wire [DLA_DATA_WIDTH -1: 0] dla_rdata_o ; 47 | reg [DLA_ADDR_WIDTH -1: 0] dla_raddr_i ; 48 | reg dla_ren_i ; 49 | reg [DLA_DATA_WIDTH -1: 0] dla_wdata_i ; 50 | reg [DLA_ADDR_WIDTH -1: 0] dla_waddr_i ; 51 | reg dla_wen_i ; 52 | 53 | 54 | ppp_top #( 55 | .DLA_DATA_WIDTH (DLA_DATA_WIDTH), 56 | .DLA_ADDR_WIDTH (DLA_ADDR_WIDTH), 57 | .ISP_DATA_WIDTH (ISP_DATA_WIDTH), 58 | .ISP_ADDR_WIDTH (ISP_ADDR_WIDTH), 59 | .DATA_WIDTH (DATA_WIDTH), 60 | .ADDR_WIDTH (ADDR_WIDTH), 61 | .DATA_DEPTH (DATA_DEPTH) 62 | ) u_ppp_top( 63 | .clk (clk), 64 | .rst_n (rst_n), 65 | .img_width_i (img_width_i), 66 | .img_height_i (img_height_i), 67 | .top_start_i (top_start_i), 68 | .isp_resp_i (isp_resp_i), 69 | .isp_rdy_o (isp_rdy_o), 70 | .isp_done_i (isp_done_i), 71 | .isp_wdata_i (isp_wdata_i), 72 | .isp_wen_i (isp_wen_i), 73 | .isp_waddr_i (isp_waddr_i), 74 | .isp_wchn_i (isp_wchn_i), 75 | .isp_rdata_o (isp_rdata_o), 76 | .isp_ren_i (isp_ren_i), 77 | .isp_raddr_i (isp_raddr_i), 78 | .isp_rchn_i (isp_rchn_i), 79 | .dla_resp_i (dla_resp_i), 80 | .dla_rdy_o (dla_rdy_o), 81 | .dla_done_i (dla_done_i), 82 | .dla_wdata_i (dla_wdata_i), 83 | .dla_wen_i (dla_wen_i), 84 | .dla_waddr_i (dla_waddr_i), 85 | .dla_rdata_o (dla_rdata_o), 86 | .dla_ren_i (dla_ren_i), 87 | .dla_raddr_i (dla_raddr_i) 88 | ); 89 | 90 | event isp_write_event; 91 | 92 | initial begin 93 | ISP_WRITE; 94 | end 95 | 96 | task ISP_WRITE; 97 | integer tile_i; 98 | integer row_i; 99 | reg [768 -1: 0] data; 100 | reg [8 -1: 0] pix_dat; 101 | begin 102 | forever begin 103 | @(isp_write_event); 104 | for(tile_i = 0; tile_i < 32; tile_i = tile_i + 1) begin 105 | for(row_i = 0; row_i < 32; row_i = row_i + 1) begin 106 | pix_dat = tile_i[7:0]; 107 | data = {96{pix_dat}}; 108 | @(negedge clk); 109 | isp_wen_i = 1'b1; 110 | isp_wdata_i = data; 111 | isp_waddr_i = {row_i[4:0], tile_i[4:0]}; 112 | end 113 | end 114 | @(negedge clk); 115 | isp_wen_i = 1'b0; 116 | isp_done_i = 1'b1; 117 | @(negedge clk); 118 | isp_done_i = 1'b0; 119 | end 120 | end 121 | endtask 122 | 123 | event dla_read_event; 124 | 125 | initial begin 126 | DLA_READ; 127 | end 128 | 129 | task DLA_READ; 130 | integer tile_i; 131 | integer row_i; 132 | reg [1024 -1: 0] check_data; 133 | reg [8 -1: 0] pix_dat; 134 | begin 135 | forever begin 136 | @(dla_read_event); 137 | for(tile_i = 0; tile_i < 32; tile_i = tile_i + 1) begin 138 | for(row_i = 0; row_i < 8; row_i = row_i + 1) begin 139 | pix_dat = tile_i[7:0]; 140 | check_data = {32{pix_dat}}; 141 | @(negedge clk); 142 | dla_ren_i = 1'b1; 143 | dla_raddr_i = {2'b00,tile_i[4:0], row_i[2:0]}; 144 | check_data = {128{pix_dat}}; 145 | @(negedge clk); 146 | if(check_data != dla_rdata_o) begin 147 | $display("MISMATCH!\n"); 148 | $finish(); 149 | end 150 | end 151 | end 152 | @(negedge clk); 153 | dla_wen_i = 1'b0; 154 | dla_done_i = 1'b1; 155 | @(negedge clk); 156 | dla_done_i = 1'b0; 157 | end 158 | end 159 | endtask 160 | 161 | 162 | 163 | initial begin 164 | clk = 1'b0; 165 | forever #5 clk <= ~clk; 166 | end 167 | 168 | 169 | initial begin 170 | rst_n = 1'b0; 171 | #(CLK_FULL * 5) ; 172 | @(negedge clk); 173 | rst_n = 1'b1; 174 | end 175 | 176 | // data 177 | initial begin 178 | img_height_i = 'd32; 179 | img_width_i = 'd1024; 180 | isp_done_i = 'd0; 181 | dla_done_i = 'd0; 182 | isp_wen_i = 'd0; 183 | isp_ren_i = 'd0; 184 | isp_wchn_i = 'd1; 185 | isp_rchn_i = 'd1; 186 | dla_wen_i = 'd0; 187 | dla_ren_i = 'd0; 188 | #(CLK_FULL * 5) ; 189 | @(negedge clk); 190 | @(negedge clk); 191 | //start 192 | top_start_i = 'd1; 193 | @(negedge clk); 194 | top_start_i = 'd0; 195 | // ISP WRITE EVENT 196 | @(negedge clk); 197 | ->isp_write_event; 198 | @(posedge isp_done_i); 199 | // DLA READ EVENT 200 | @(negedge clk); 201 | ->dla_read_event; 202 | @(posedge dla_done_i); 203 | #(10 * CLK_FULL); 204 | $display("PASS !!!!!!!\n"); 205 | $finish(); 206 | end 207 | 208 | 209 | initial begin 210 | $display("Dump fsdb wave!"); 211 | $fsdbDumpfile("tb.fsdb"); 212 | $fsdbDumpvars; 213 | end 214 | 215 | initial begin 216 | $display("\033[30;41m Hello error!\033[0m"); 217 | $display("\033[30;42m Hello pass!\033[0m"); 218 | $display("\033[30;43m Hello warning!\033[0m"); 219 | 220 | end 221 | 222 | endmodule -------------------------------------------------------------------------------- /sim/tb/tb_scheduler.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module tb_sche_sub; 3 | 4 | parameter IFM_WIDTH = 8; 5 | parameter SCH_COL_NUM = 40; 6 | parameter WT_WIDTH = 16; 7 | parameter PE_COL_NUM = 32; 8 | parameter PE_ROW_NUM = 4; 9 | parameter PE_IC_NUM = 4; 10 | parameter PE_OC_NUM = 4; 11 | parameter ADDR_WIDTH = 10; 12 | 13 | reg clk; 14 | reg rstn; 15 | 16 | reg tile_switch; 17 | reg ctrl2sch_layer_start; 18 | reg [3 : 0] cnt_layer; 19 | reg [3 : 0] tile_loc; 20 | reg [3 : 0] ksize; 21 | reg pe2sch_rdy; 22 | reg [14 : 0] tile_in_h; 23 | reg [14 : 0] tile_out_h; 24 | reg [14 : 0] tile_in_w; 25 | reg [14 : 0] tile_out_w; 26 | reg [14 : 0] tile_in_c; 27 | reg [14 : 0] tile_out_c; 28 | reg [99 : 0] pu2sch_olp_addr; 29 | 30 | wire [3 : 0] fe_olp_buf_rd_en; 31 | wire [ADDR_WIDTH - 1 : 0] fe_buf_rd_addr_0; 32 | wire [ADDR_WIDTH - 1 : 0] fe_buf_rd_addr_1; 33 | wire [ADDR_WIDTH - 1 : 0] fe_buf_rd_addr_2; 34 | wire [ADDR_WIDTH - 1 : 0] fe_buf_rd_addr_3; 35 | wire [ADDR_WIDTH - 1 : 0] olp_buf_rd_addr_0; 36 | wire [ADDR_WIDTH - 1 : 0] olp_buf_rd_addr_1; 37 | wire [ADDR_WIDTH - 1 : 0] olp_buf_rd_addr_2; 38 | wire [ADDR_WIDTH - 1 : 0] olp_buf_rd_addr_3; 39 | wire [7 : 0] wt_buf_rd_en; 40 | wire [ADDR_WIDTH - 1 : 0] wt_buf_rd_addr; 41 | 42 | wire sch2pe_row_done; 43 | wire sch2pe_vld_o; 44 | wire [PE_COL_NUM - 1 : 0] mux_col_vld_o; 45 | wire [PE_ROW_NUM - 1 : 0] mux_row_vld_o; 46 | wire [PE_IC_NUM - 1 : 0] mux_array_vld_o; 47 | 48 | // interface with scheduler 49 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_0_0; 50 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_0_1; 51 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_0_2; 52 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_0_3; 53 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_1_0; 54 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_1_1; 55 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_1_2; 56 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_1_3; 57 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_2_0; 58 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_2_1; 59 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_2_2; 60 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_2_3; 61 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_3_0; 62 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_3_1; 63 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_3_2; 64 | reg [SCH_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_input_3_3; 65 | 66 | reg [WT_WIDTH - 1 : 0] sch_weight_input_0_0; 67 | reg [WT_WIDTH - 1 : 0] sch_weight_input_0_1; 68 | reg [WT_WIDTH - 1 : 0] sch_weight_input_0_2; 69 | reg [WT_WIDTH - 1 : 0] sch_weight_input_0_3; 70 | reg [WT_WIDTH - 1 : 0] sch_weight_input_1_0; 71 | reg [WT_WIDTH - 1 : 0] sch_weight_input_1_1; 72 | reg [WT_WIDTH - 1 : 0] sch_weight_input_1_2; 73 | reg [WT_WIDTH - 1 : 0] sch_weight_input_1_3; 74 | reg [WT_WIDTH - 1 : 0] sch_weight_input_2_0; 75 | reg [WT_WIDTH - 1 : 0] sch_weight_input_2_1; 76 | reg [WT_WIDTH - 1 : 0] sch_weight_input_2_2; 77 | reg [WT_WIDTH - 1 : 0] sch_weight_input_2_3; 78 | reg [WT_WIDTH - 1 : 0] sch_weight_input_3_0; 79 | reg [WT_WIDTH - 1 : 0] sch_weight_input_3_1; 80 | reg [WT_WIDTH - 1 : 0] sch_weight_input_3_2; 81 | reg [WT_WIDTH - 1 : 0] sch_weight_input_3_3; 82 | 83 | // dat_o 84 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_0_0; 85 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_0_1; 86 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_0_2; 87 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_0_3; 88 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_1_0; 89 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_1_1; 90 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_1_2; 91 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_1_3; 92 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_2_0; 93 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_2_1; 94 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_2_2; 95 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_2_3; 96 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_3_0; 97 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_3_1; 98 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_3_2; 99 | wire [PE_COL_NUM * IFM_WIDTH - 1 : 0] sch_data_output_3_3; 100 | 101 | wire [WT_WIDTH - 1 : 0] sch_weight_output_0_0; 102 | wire [WT_WIDTH - 1 : 0] sch_weight_output_0_1; 103 | wire [WT_WIDTH - 1 : 0] sch_weight_output_0_2; 104 | wire [WT_WIDTH - 1 : 0] sch_weight_output_0_3; 105 | wire [WT_WIDTH - 1 : 0] sch_weight_output_1_0; 106 | wire [WT_WIDTH - 1 : 0] sch_weight_output_1_1; 107 | wire [WT_WIDTH - 1 : 0] sch_weight_output_1_2; 108 | wire [WT_WIDTH - 1 : 0] sch_weight_output_1_3; 109 | wire [WT_WIDTH - 1 : 0] sch_weight_output_2_0; 110 | wire [WT_WIDTH - 1 : 0] sch_weight_output_2_1; 111 | wire [WT_WIDTH - 1 : 0] sch_weight_output_2_2; 112 | wire [WT_WIDTH - 1 : 0] sch_weight_output_2_3; 113 | wire [WT_WIDTH - 1 : 0] sch_weight_output_3_0; 114 | wire [WT_WIDTH - 1 : 0] sch_weight_output_3_1; 115 | wire [WT_WIDTH - 1 : 0] sch_weight_output_3_2; 116 | wire [WT_WIDTH - 1 : 0] sch_weight_output_3_3; 117 | 118 | wire [3:0] k; 119 | 120 | initial begin 121 | clk =1'b0; 122 | forever #5 clk <= ~clk; 123 | end 124 | /* 125 | initial begin 126 | clk <= 1'b0; 127 | rstn <= 1'b1; 128 | #22 129 | rstn <= 1'b0; 130 | #17 131 | rstn <= 1'b1; 132 | #20 133 | sch_data_input_0_0 <= 256'h01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010203; 134 | sch_data_input_0_1 <= 256'h02020202_02020202_02020202_02020202_02020202_02020202_02020202_02010203; 135 | sch_data_input_0_2 <= 256'h03030303_03030303_03030303_03030303_03030303_03030303_03030303_03010203; 136 | sch_data_input_0_3 <= 256'h04040404_04040404_04040404_04040404_04040404_04040404_04040404_04010203; 137 | tile_switch <= 0; 138 | ctrl2sch_layer_start <= 1; 139 | pe2sch_rdy <= 1; 140 | tile_loc <= 0001; 141 | ksize <= 3; 142 | tile_in_h <= 10; 143 | tile_out_h <= 9; 144 | tile_in_w <= 32; 145 | tile_out_w <= 32; 146 | tile_in_c <= 9; 147 | tile_out_c <= 8; 148 | pu2sch_olp_addr <= 0; 149 | #10 150 | ctrl2sch_layer_start <= 0; 151 | #2000 152 | ctrl2sch_layer_start <= 1; 153 | #10 154 | ctrl2sch_layer_start <= 0; 155 | #3000 156 | $finish; 157 | end*/ 158 | 159 | // tile_loc == 0010; 160 | 161 | initial begin 162 | clk <= 1'b0; 163 | rstn <= 1'b1; 164 | #22 165 | rstn <= 1'b0; 166 | #17 167 | rstn <= 1'b1; 168 | #20 169 | tile_switch <= 0; 170 | ctrl2sch_layer_start <= 1; 171 | pe2sch_rdy <= 1; 172 | tile_loc <= 0010; 173 | ksize <= 3; 174 | tile_in_h <= 10; 175 | tile_out_h <= 9; 176 | tile_in_w <= 32; 177 | tile_out_w <= 32; 178 | tile_in_c <= 9; 179 | tile_out_c <= 8; 180 | pu2sch_olp_addr <= 0; 181 | rstn <= 1'b1; 182 | #22 183 | rstn <= 1'b0; 184 | #17 185 | rstn <= 1'b1; 186 | #10 187 | ctrl2sch_layer_start <= 0; 188 | #90 189 | pe2sch_rdy <= 0; 190 | #30 191 | pe2sch_rdy <= 1; 192 | #2000 193 | ctrl2sch_layer_start <= 1; 194 | #10 195 | ctrl2sch_layer_start <= 0; 196 | #2000 197 | $finish; 198 | end 199 | 200 | always @(posedge clk) 201 | begin 202 | sch_data_input_0_0 <= fe_olp_buf_rd_en[3] ? 256'h01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010203 : 0; 203 | sch_data_input_0_1 <= fe_olp_buf_rd_en[2] ? 256'h02020202_02020202_02020202_02020202_02020202_02020202_02020202_02010203 : 0; 204 | sch_data_input_0_2 <= fe_olp_buf_rd_en[1] ? 256'h03030303_03030303_03030303_03030303_03030303_03030303_03030303_03010203 : 0; 205 | sch_data_input_0_3 <= fe_olp_buf_rd_en[0] ? 256'h04040404_04040404_04040404_04040404_04040404_04040404_04040404_04010203 : 0; 206 | end 207 | 208 | always @(posedge clk) 209 | begin 210 | sch_weight_input_0_0 <= wt_buf_rd_addr != 0 ? 32'h1234_5678 : 0; 211 | sch_weight_input_0_1 <= wt_buf_rd_addr != 0 ? 32'h8765_4321 : 0; 212 | sch_weight_input_0_2 <= wt_buf_rd_addr != 0 ? 32'h1234_5678 : 0; 213 | sch_weight_input_0_3 <= wt_buf_rd_addr != 0 ? 32'h8765_4321 : 0; 214 | end 215 | 216 | // tile_loc == 0000; 217 | /* 218 | initial begin 219 | clk <= 1'b0; 220 | rstn <= 1'b1; 221 | #22 222 | rstn <= 1'b0; 223 | #17 224 | rstn <= 1'b1; 225 | #20 226 | tile_switch <= 0; 227 | ctrl2sch_layer_start <= 1; 228 | pe2sch_rdy <= 1; 229 | tile_loc <= 0000; 230 | ksize <= 3; 231 | tile_in_h <= 10; 232 | tile_out_h <= 8; 233 | tile_in_w <= 32; 234 | tile_out_w <= 32; 235 | tile_in_c <= 8; 236 | tile_out_c <= 8; 237 | pu2sch_olp_addr <= 0; 238 | #10 239 | ctrl2sch_layer_start <= 0; 240 | #2000 241 | ctrl2sch_layer_start <= 1; 242 | #10 243 | ctrl2sch_layer_start <= 0; 244 | #2000 245 | $finish; 246 | end 247 | */ 248 | 249 | scheduler #( 250 | .IFM_WIDTH (IFM_WIDTH), 251 | .SCH_COL_NUM (SCH_COL_NUM), 252 | .WT_WIDTH (WT_WIDTH), 253 | .PE_COL_NUM (PE_COL_NUM), 254 | .PE_ROW_NUM (PE_ROW_NUM), 255 | .PE_IC_NUM (PE_IC_NUM), 256 | .PE_OC_NUM (PE_OC_NUM), 257 | .ADDR_WIDTH (ADDR_WIDTH) 258 | ) 259 | u0_scheduler 260 | ( 261 | .clk(clk), 262 | .rstn(rstn), 263 | 264 | // ctrl_i 265 | .tile_switch (tile_switch), 266 | .ctrl2sch_layer_start (ctrl2sch_layer_start), 267 | .cnt_layer (cnt_layer), 268 | .pe2sch_rdy (pe2sch_rdy), 269 | .tile_loc (tile_loc), 270 | .ksize (ksize), 271 | .tile_in_h (tile_in_h), 272 | .tile_out_h (tile_out_h), 273 | .tile_in_w (tile_in_w), 274 | .tile_out_w (tile_out_w), 275 | .tile_in_c (tile_in_c), 276 | .tile_out_c (tile_out_c), 277 | .pu2sch_olp_addr (pu2sch_olp_addr), 278 | 279 | //buffer rd 280 | .fe_olp_buf_rd_en (fe_olp_buf_rd_en), 281 | .fe_buf_rd_addr_0 (fe_buf_rd_addr_0), 282 | .fe_buf_rd_addr_1 (fe_buf_rd_addr_1), 283 | .fe_buf_rd_addr_2 (fe_buf_rd_addr_2), 284 | .fe_buf_rd_addr_3 (fe_buf_rd_addr_3), 285 | .olp_buf_rd_addr_0 (olp_buf_rd_addr_0), 286 | .olp_buf_rd_addr_1 (olp_buf_rd_addr_1), 287 | .olp_buf_rd_addr_2 (olp_buf_rd_addr_2), 288 | .olp_buf_rd_addr_3 (olp_buf_rd_addr_3), 289 | .wt_buf_rd_en (wt_buf_rd_en), 290 | .wt_buf_rd_addr (wt_buf_rd_addr), 291 | 292 | .sch2pe_row_done(sch2pe_row_done), 293 | .sch2pe_vld_o(sch2pe_vld_o), 294 | .mux_col_vld_o(mux_col_vld_o), 295 | .mux_row_vld_o(mux_row_vld_o), 296 | .mux_array_vld_o(mux_array_vld_o), 297 | 298 | .sch_data_input_0_0(sch_data_input_0_0), 299 | .sch_data_input_0_1(sch_data_input_0_1), 300 | .sch_data_input_0_2(sch_data_input_0_2), 301 | .sch_data_input_0_3(sch_data_input_0_3), 302 | .sch_data_input_1_0(sch_data_input_1_0), 303 | .sch_data_input_1_1(sch_data_input_1_1), 304 | .sch_data_input_1_2(sch_data_input_1_2), 305 | .sch_data_input_1_3(sch_data_input_1_3), 306 | .sch_data_input_2_0(sch_data_input_2_0), 307 | .sch_data_input_2_1(sch_data_input_2_1), 308 | .sch_data_input_2_2(sch_data_input_2_2), 309 | .sch_data_input_2_3(sch_data_input_2_3), 310 | .sch_data_input_3_0(sch_data_input_3_0), 311 | .sch_data_input_3_1(sch_data_input_3_1), 312 | .sch_data_input_3_2(sch_data_input_3_2), 313 | .sch_data_input_3_3(sch_data_input_3_3), 314 | 315 | .sch_weight_input_0_0(sch_weight_input_0_0), 316 | .sch_weight_input_0_1(sch_weight_input_0_1), 317 | .sch_weight_input_0_2(sch_weight_input_0_2), 318 | .sch_weight_input_0_3(sch_weight_input_0_3), 319 | .sch_weight_input_1_0(sch_weight_input_1_0), 320 | .sch_weight_input_1_1(sch_weight_input_1_1), 321 | .sch_weight_input_1_2(sch_weight_input_1_2), 322 | .sch_weight_input_1_3(sch_weight_input_1_3), 323 | .sch_weight_input_2_0(sch_weight_input_2_0), 324 | .sch_weight_input_2_1(sch_weight_input_2_1), 325 | .sch_weight_input_2_2(sch_weight_input_2_2), 326 | .sch_weight_input_2_3(sch_weight_input_2_3), 327 | .sch_weight_input_3_0(sch_weight_input_3_0), 328 | .sch_weight_input_3_1(sch_weight_input_3_1), 329 | .sch_weight_input_3_2(sch_weight_input_3_2), 330 | .sch_weight_input_3_3(sch_weight_input_3_3), 331 | 332 | .sch_data_output_0_0(sch_data_output_0_0), 333 | .sch_data_output_0_1(sch_data_output_0_1), 334 | .sch_data_output_0_2(sch_data_output_0_2), 335 | .sch_data_output_0_3(sch_data_output_0_3), 336 | .sch_data_output_1_0(sch_data_output_1_0), 337 | .sch_data_output_1_1(sch_data_output_1_1), 338 | .sch_data_output_1_2(sch_data_output_1_2), 339 | .sch_data_output_1_3(sch_data_output_1_3), 340 | .sch_data_output_2_0(sch_data_output_2_0), 341 | .sch_data_output_2_1(sch_data_output_2_1), 342 | .sch_data_output_2_2(sch_data_output_2_2), 343 | .sch_data_output_2_3(sch_data_output_2_3), 344 | .sch_data_output_3_0(sch_data_output_3_0), 345 | .sch_data_output_3_1(sch_data_output_3_1), 346 | .sch_data_output_3_2(sch_data_output_3_2), 347 | .sch_data_output_3_3(sch_data_output_3_3), 348 | 349 | .sch_weight_output_0_0(sch_weight_output_0_0), 350 | .sch_weight_output_0_1(sch_weight_output_0_1), 351 | .sch_weight_output_0_2(sch_weight_output_0_2), 352 | .sch_weight_output_0_3(sch_weight_output_0_3), 353 | .sch_weight_output_1_0(sch_weight_output_1_0), 354 | .sch_weight_output_1_1(sch_weight_output_1_1), 355 | .sch_weight_output_1_2(sch_weight_output_1_2), 356 | .sch_weight_output_1_3(sch_weight_output_1_3), 357 | .sch_weight_output_2_0(sch_weight_output_2_0), 358 | .sch_weight_output_2_1(sch_weight_output_2_1), 359 | .sch_weight_output_2_2(sch_weight_output_2_2), 360 | .sch_weight_output_2_3(sch_weight_output_2_3), 361 | .sch_weight_output_3_0(sch_weight_output_3_0), 362 | .sch_weight_output_3_1(sch_weight_output_3_1), 363 | .sch_weight_output_3_2(sch_weight_output_3_2), 364 | .sch_weight_output_3_3(sch_weight_output_3_3) 365 | ); 366 | 367 | `ifdef DUMP_VPD 368 | initial begin 369 | $display("Dump VPD wave!"); 370 | $vcdpluson(); 371 | end 372 | `endif 373 | 374 | initial begin 375 | $display("Dump fsdb wave!"); 376 | $fsdbDumpfile("tb.fsdb"); 377 | $fsdbDumpvars; 378 | end 379 | 380 | initial begin 381 | $display("\033[30;41m Hello error!\033[0m"); 382 | $display("\033[30;42m Hello pass!\033[0m"); 383 | $display("\033[30;43m Hello warning!\033[0m"); 384 | 385 | end 386 | 387 | `ifdef GLS_SIM 388 | initial begin 389 | $sdf_annotate("../../netlist_sim/sdf/TOP.sdf",tb.U_TOP,,"sdf.log","TYPICAL"); 390 | end 391 | `endif 392 | 393 | endmodule 394 | -------------------------------------------------------------------------------- /sim/tv/dndm/param_buf.txt: -------------------------------------------------------------------------------- 1 | 05 2 | 10 3 | 7fff8ce994c5 4 | 7fff8ce994c5 5 | 7fff8ce994c5 6 | 7fff8ce994c5 7 | 48248ce994c5 8 | f2618ce994c5 9 | 7fff8ce994c5 10 | 80008ce994c5 11 | 80008ce994c5 12 | 80008ce994c5 13 | 80008ce994c5 14 | 7fff8ce994c5 15 | 80008ce994c5 16 | 80008ce994c5 17 | 7fff8ce994c5 18 | 7eac8ce994c5 19 | 10 20 | 1820886d94c5 21 | 19a4886d94c5 22 | 4268886d94c5 23 | 6f3f886d94c5 24 | 320d886d94c5 25 | 457c886d94c5 26 | 2f8d886d94c5 27 | 7fff886d94c5 28 | 19bd886d94c5 29 | 515b886d94c5 30 | 6c25886d94c5 31 | 3d66886d94c5 32 | 7426886d94c5 33 | 4038886d94c5 34 | 1323886d94c5 35 | 546d886d94c5 36 | 10 37 | 33a8b44c94c5 38 | 10f8b44c94c5 39 | 5148b44c94c5 40 | 22bfb44c94c5 41 | fa07b44c94c5 42 | 22e1b44c94c5 43 | 32d6b44c94c5 44 | 3a11b44c94c5 45 | 156db44c94c5 46 | 3411b44c94c5 47 | 4732b44c94c5 48 | 3797b44c94c5 49 | fe26b44c94c5 50 | 23bfb44c94c5 51 | 2772b44c94c5 52 | 2542b44c94c5 53 | 10 54 | 4087aa3794c5 55 | 3ca3aa3794c5 56 | 3980aa3794c5 57 | 0000aa3794c5 58 | 243daa3794c5 59 | 239caa3794c5 60 | 1831aa3794c5 61 | 5f55aa3794c5 62 | 3dfcaa3794c5 63 | 2aa2aa3794c5 64 | 2e63aa3794c5 65 | 3189aa3794c5 66 | 464baa3794c5 67 | 20f8aa3794c5 68 | 2398aa3794c5 69 | 1ae7aa3794c5 70 | 03 71 | 7ffffd2094c5 72 | 6131fd2094c5 73 | 7ffffd2094c5 74 | -------------------------------------------------------------------------------- /sim/tv/dndm/wt_buf.txt: -------------------------------------------------------------------------------- 1 | 278 2 | e3d0fff4f8f7f9fd0629111f00000000 3 | e1041122fe0afde1161e01e600000000 4 | 1fe51d02f90df5db3ff92c2d00000000 5 | f9f31dfffae50ae8390c0c0400000000 6 | edc604f70b05db0df911313d00000000 7 | f0d8182bfd04edf62823d91400000000 8 | 2aecfc580d10f5fc0232190900000000 9 | 25cd37e517edd5f32c1fdd0900000000 10 | ef050f452bff22e1340627ef00000000 11 | 03f11fc5f91ee81d0a23e1f700000000 12 | e6e205ebf52c01ef1d130a3b00000000 13 | feef15211105d70e440b18ed00000000 14 | 25072ee5253020153135086000000000 15 | d4eaff04f02af6142e3202fa00000000 16 | fbe50a06fe0ef8003a02144600000000 17 | faf80ae2d01cf4fa3d17011600000000 18 | fef8fe400e1de6031a2005e800000000 19 | eef418f12b1b2ada482826cf00000000 20 | 13dbd923110608fc281ef0df00000000 21 | 19fe1e1f0c1a0580370ff0ec00000000 22 | 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6c088e7186fc 82 | 7fff8e7186fc 83 | 7fff8e7186fc 84 | 7a868e7186fc 85 | 60098e7186fc 86 | 7a088e7186fc 87 | -------------------------------------------------------------------------------- /sim/work/makefile: -------------------------------------------------------------------------------- 1 | .PHONY: vcs sim verdi clean 2 | all:vcs sim verdi 3 | 4 | OUTPUT = simv 5 | ALL_DEFINE = +define+DUMP_VPD 6 | VPD_NAME = +vpdfile+${OUTPUT}.vpd 7 | ##========== code coverage command ======= 8 | CM_NAME = -cm_name ${OUTPUT} 9 | CM_DIR = -cm_dir ./${OUTPUT}.vdb 10 | CM = -cm line+cond+fsm+branch+tgl 11 | ##====================================== 12 | vcs: 13 | vcs \ 14 | -f ../flist/filelist.f \ 15 | -timescale=1ns/1ns \ 16 | -full64 +v2k -sverilog -debug_all \ 17 | -fsdb \ 18 | -l vcs.log \ 19 | -notimingcheck \ 20 | -nospecify \ 21 | -o ${OUTPUT} \ 22 | ${CM} \ 23 | ${CM_NAME} \ 24 | ${CM_DIR} \ 25 | ${VPD_NAME} \ 26 | ${ALL_DEFINE} \ 27 | +lint=TFIPC-L \ 28 | +vcs+lic+wait 29 | sim: 30 | ./${OUTPUT} \ 31 | -l sim.log \ 32 | ${CM} \ 33 | ${CM_NAME} \ 34 | ${CM_DIR} \ 35 | ${VPD_NAME} 36 | #show the coverage 37 | dve_cov: 38 | dve -covdir *.vdb & 39 | urg: 40 | urg -dir *.vdb -report urgReport 41 | dve: 42 | dve -vpd ${OUTPUT}.vpd & 43 | verdi : 44 | verdi -sv -f ../flist/filelist.f -ssf tb.fsdb & 45 | clean : 46 | rm -rf *~ core csrc simv* vc_hdrs.h ucli.key urg* *.log novas.* *.fsdb* verdiLog 64* DVEfiles *.vpd *.dat 47 | 48 | --------------------------------------------------------------------------------