├── .github ├── FUNDING.yml ├── ISSUE_TEMPLATE │ ├── BUG_REPORT.yml │ └── QUESTION.yml ├── PULL_REQUEST_TEMPLATE.md └── workflows │ └── build-pocket.yml ├── .gitignore ├── LICENSE ├── docs ├── CODE_OF_CONDUCT.md ├── README.md ├── git-social.jpg └── supervision-logo.png ├── gateware.json ├── modules ├── cpu-r65c02_tc │ ├── core.vhd │ ├── fsm_execution_unit.vhd │ ├── fsm_intnmi.vhd │ ├── index.qip │ ├── r65c02_tc.vhd │ ├── reg_pc.vhd │ ├── reg_sp.vhd │ └── regbank_axy.vhd ├── general-sync_fifo │ ├── index.qip │ └── sync_fifo.sv ├── pocket-dataloader │ ├── data_loader.sv │ ├── data_unloader.sv │ └── index.qip ├── pocket-i2s │ ├── index.qip │ └── pocket_i2s.sv ├── pocket-joypad │ ├── index.qip │ └── joypad.v ├── pocket-video │ ├── index.qip │ └── pocket_video.sv └── video-scanlines │ ├── index.qip │ └── scanlines.v ├── pkg ├── palettes │ ├── Default │ │ ├── Andrade.gbp │ │ ├── Biverted.gbp │ │ ├── Chocolate.gbp │ │ ├── DMG.gbp │ │ ├── GrafxGray.gbp │ │ ├── GrafxGreen.gbp │ │ ├── KidIcarus.gbp │ │ ├── Kirby.gbp │ │ ├── LinksAwakening.gbp │ │ ├── MegaManV.gbp │ │ ├── MetroidII.gbp │ │ ├── PJ.gbp │ │ ├── Pastel.gbp │ │ ├── Pokemon.gbp │ │ ├── Red.gbp │ │ ├── SGBDefault.gbp │ │ ├── SML2.gbp │ │ ├── Sameboy.gbp │ │ └── Yellow.gbp │ ├── Extra │ │ ├── Angry Volcano.gbp │ │ ├── Avalon.gbp │ │ ├── Bicycle.gbp │ │ ├── Blk Aqu4.gbp │ │ ├── Blue Gameboy.gbp │ │ ├── Blue Seni.gbp │ │ ├── Cave4.gbp │ │ ├── Christmas.gbp │ │ ├── Coldfire.gbp │ │ ├── Darkboy4.gbp │ │ ├── Do the Dew.gbp │ │ ├── DraculaTheme.com.gbp │ │ ├── Earth.gbp │ │ ├── Easy Greens.gbp │ │ ├── Gruel.gbp │ │ ├── Hisato no Iro.gbp │ │ ├── Ice Cream.gbp │ │ ├── Kiosk.gbp │ │ ├── Kirokaze.gbp │ │ ├── Muddysand.gbp │ │ ├── NASCAR.gbp │ │ ├── Nostalgia.gbp │ │ ├── Novocaine.gbp │ │ ├── Nymph.gbp │ │ ├── Penny.gbp │ │ ├── Platinum.gbp │ │ ├── Purpledawn.gbp │ │ ├── Retro Bogeda.gbp │ │ ├── Rustic.gbp │ │ ├── Scooby-Doo Mystery.gbp │ │ ├── Solarized Dark.gbp │ │ ├── Spacehaze.gbp │ │ ├── Wish.gbp │ │ ├── Workbench.gbp │ │ ├── bgb Emulator green.gbp │ │ └── blue.gbp │ ├── SGB │ │ ├── 1-A.gbp │ │ ├── 1-B.gbp │ │ ├── 1-C.gbp │ │ ├── 1-D.gbp │ │ ├── 1-E.gbp │ │ ├── 1-F.gbp │ │ ├── 1-G.gbp │ │ ├── 1-H.gbp │ │ ├── 2-A.gbp │ │ ├── 2-B.gbp │ │ ├── 2-C.gbp │ │ ├── 2-D.gbp │ │ ├── 2-E.gbp │ │ ├── 2-F.gbp │ │ ├── 2-G.gbp │ │ ├── 2-H.gbp │ │ ├── 3-A.gbp │ │ ├── 3-B.gbp │ │ ├── 3-C.gbp │ │ ├── 3-D.gbp │ │ ├── 3-E.gbp │ │ ├── 3-F.gbp │ │ ├── 3-G.gbp │ │ ├── 3-H.gbp │ │ ├── 4-A.gbp │ │ ├── 4-B.gbp │ │ ├── 4-C.gbp │ │ ├── 4-D.gbp │ │ ├── 4-E.gbp │ │ ├── 4-F.gbp │ │ ├── 4-G.gbp │ │ └── 4-H.gbp │ ├── TrashUncle │ │ ├── Artistic │ │ │ ├── TU Paisley Park.gbp │ │ │ └── TU Quicksilver.gbp │ │ ├── Crush │ │ │ ├── TU Blueberry Crush.gbp │ │ │ ├── TU Grape Crush.gbp │ │ │ ├── TU Kiwi Crush.gbp │ │ │ ├── TU Lavender Crush.gbp │ │ │ ├── TU Orange Crush.gbp │ │ │ ├── TU Pineapple Crush.gbp │ │ │ └── TU Strawberry Crush.gbp │ │ ├── DMG │ │ │ ├── TU DMG Bright.gbp │ │ │ ├── TU DMG Clean.gbp │ │ │ ├── TU DMG Weak Alt.gbp │ │ │ └── TU DMG Weak.gbp │ │ ├── GBP │ │ │ ├── TU GBP Bright.gbp │ │ │ ├── TU GBP Clean.gbp │ │ │ ├── TU GBP Weak Alt.gbp │ │ │ └── TU GBP Weak.gbp │ │ └── Light │ │ │ ├── TU Light Bright.gbp │ │ │ ├── TU Light Clean.gbp │ │ │ ├── TU Light Dark.gbp │ │ │ └── TU Light Idealized.gbp │ └── _HC │ │ ├── andrade.gbp │ │ ├── biverted.gbp │ │ ├── dmg.gbp │ │ ├── sgbdefault.gbp │ │ ├── tu_blueberry_crush.gbp │ │ ├── tu_dmg_bright.gbp │ │ ├── tu_dmg_clean.gbp │ │ ├── tu_dmg_weak.gbp │ │ ├── tu_gbp_bright.gbp │ │ ├── tu_gbp_clean.gbp │ │ ├── tu_gbp_weak.gbp │ │ ├── tu_grape_crush.gbp │ │ ├── tu_orange_crush.gbp │ │ ├── tu_paisley_park.gbp │ │ ├── tu_quicksilver.gbp │ │ └── tu_strawberry_crush.gbp └── pocket │ ├── Assets │ └── supervision │ │ └── common │ │ └── .gitkeep │ ├── Cores │ └── boogermann.supervision │ │ ├── audio.json │ │ ├── core.json │ │ ├── data.json │ │ ├── icon.bin │ │ ├── icon.png │ │ ├── info.txt │ │ ├── input.json │ │ ├── interact.json │ │ ├── variants.json │ │ └── video.json │ └── Platforms │ ├── _images │ ├── supervision.bin │ └── supervision.png │ └── supervision.json ├── platform └── pocket │ ├── apf.qip │ ├── apf_constraints.sdc │ ├── apf_top.v │ ├── build_cdf.tcl │ ├── build_id_gen.tcl │ ├── common.v │ ├── io_bridge_peripheral.v │ ├── io_pad_controller.v │ ├── mf_datatable.qip │ ├── mf_datatable.v │ ├── mf_ddio_bidir_12.qip │ ├── mf_ddio_bidir_12.v │ └── pocket.tcl ├── projects ├── supervision_pocket.qip ├── supervision_pocket.qpf ├── supervision_pocket.qsf └── supervision_pocket.sdc ├── rtl ├── audio.sv ├── bram.vhd ├── dma.sv ├── index.qip ├── lcd.sv ├── sdram.sv ├── supervision.qip └── supervision.sv └── target └── pocket ├── core.qip ├── core_bridge_cmd.v ├── core_constraints.sdc ├── core_top.sv ├── mf_pllbase.ppf ├── mf_pllbase.qip ├── mf_pllbase.v └── mf_pllbase ├── mf_pllbase_0002.qip └── mf_pllbase_0002.v /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | ##################################################################### 2 | # SPDX-License-Identifier: CC0-1.0 3 | # SPDX-FileType: OTHER 4 | # SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors 5 | ##################################################################### 6 | patreon: pierco 7 | custom: ["https://www.paypal.com/donate/?hosted_button_id=N7HXKEL8VJ9CN"] 8 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/BUG_REPORT.yml: -------------------------------------------------------------------------------- 1 | ##################################################################### 2 | # SPDX-License-Identifier: CC0-1.0 3 | # SPDX-FileType: OTHER 4 | # SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors 5 | ##################################################################### 6 | name: "Bug Report" 7 | description: "Let us know about an unexpected error, a crash, or an incorrect behavior." 8 | title: 'Title of your Bug Report' 9 | labels: 10 | - bug 11 | assignees: 12 | - boogermann 13 | body: 14 | - type: markdown 15 | attributes: 16 | value: | 17 | Hi there, 18 | 19 | Thank you for opening an issue. Please note that we try to keep the issue tracker reserved for bug reports. 20 | Make sure to [search for existing issues](https://github.com/opengateware/console-supervision/issues?q=label%3Abug) before filing a new one! 21 | 22 | - type: input 23 | id: version 24 | attributes: 25 | label: Version (or build number) 26 | placeholder: "1.0.0" 27 | description: | 28 | You can find the version in the about dialog. 29 | 30 | If you are not running the latest version, please try upgrading because your issue may have already been fixed. 31 | validations: 32 | required: true 33 | 34 | - type: textarea 35 | id: steps 36 | attributes: 37 | label: Steps to reproduce 38 | description: | 39 | Please list the full steps required to reproduce the issue 40 | placeholder: | 41 | - Be precise 42 | - Include exact data used during testing for easy reference 43 | - The steps have to be in the exact order 44 | - Mention pre-requisites when applicable 45 | validations: 46 | required: false 47 | 48 | - type: textarea 49 | id: expected_behavior 50 | attributes: 51 | label: Expected Behavior 52 | description: If you want to include screenshots, paste them into the markdown editor below or follow up with a separate comment. 53 | placeholder: What were you expecting? 54 | validations: 55 | required: false 56 | 57 | - type: textarea 58 | id: actual_behavior 59 | attributes: 60 | label: Actual Behavior 61 | placeholder: What happened instead? 62 | validations: 63 | required: true 64 | 65 | - type: textarea 66 | id: bug_context 67 | attributes: 68 | label: Additional Context 69 | description: | 70 | Are there anything atypical about your situation that we should know? 71 | validations: 72 | required: false 73 | 74 | - type: input 75 | id: bug_firmware 76 | attributes: 77 | label: Opened Issues and Pull Requests 78 | placeholder: "#1234" 79 | description: | 80 | Are there any other GitHub issues (open or closed) or Pull Requests that should be linked here? For example: #1234 81 | validations: 82 | required: false 83 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/QUESTION.yml: -------------------------------------------------------------------------------- 1 | ##################################################################### 2 | # SPDX-License-Identifier: CC0-1.0 3 | # SPDX-FileType: OTHER 4 | # SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors 5 | ##################################################################### 6 | name: "Question" 7 | description: "Ask a question about the project." 8 | title: 'Title of your Question' 9 | labels: 10 | - question 11 | assignees: 12 | - boogermann 13 | body: 14 | - type: markdown 15 | attributes: 16 | value: | 17 | Hi there, 18 | 19 | Please note that we try to keep the issue tracker reserved for bug reports. 20 | Make sure to [search for existing questions](https://github.com/opengateware/console-supervision/issues?q=label%3Aquestion) before filing a new one! 21 | 22 | - type: textarea 23 | id: question 24 | attributes: 25 | label: Ask a question about Green Beret Compatible Gateware IP Core 26 | placeholder: | 27 | Ask your question here! Please keep the questions related to the FPGA Core only. 28 | validations: 29 | required: true 30 | -------------------------------------------------------------------------------- /.github/PULL_REQUEST_TEMPLATE.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | ## What does this do / why do we need it? 8 | 9 | 14 | 15 | {Please write here} 16 | 17 | Fixes # (issue) 18 | 19 | ## Type of change 20 | 21 | 24 | 25 | - [ ] Bug fix (non-breaking change which fixes an issue) 26 | - [ ] New feature (non-breaking change which adds functionality) 27 | - [ ] Breaking change (fix or feature that would cause existing functionality to not work as expected) 28 | - [ ] This change requires a documentation update 29 | - [ ] Coding style (indentation, etc) 30 | - [ ] {Please write custom change here} 31 | 32 | ## What should a reviewer look out for in this PR? 33 | 34 | 39 | 40 | {Please write here} 41 | 42 | ## Additional Comments (if any) 43 | 44 | {Please write here} 45 | -------------------------------------------------------------------------------- /.github/workflows/build-pocket.yml: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # SPDX-License-Identifier: CC0-1.0 3 | # SPDX-FileType: OTHER 4 | # SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors 5 | ################################################################################ 6 | name: Build/Release 7 | ################################################################################ 8 | # How to create a tag to launch the workflow 9 | # git tag -a "0.1.0" -m "Release v0.1.0" 10 | # git push origin --tags 11 | ################################################################################ 12 | on: 13 | push: 14 | tags: 15 | - "[0-9]+.[0-9]+.[0-9]+" 16 | ################################################################################ 17 | jobs: 18 | synthesis: 19 | runs-on: ubuntu-latest 20 | env: 21 | CORE: supervision 22 | DISPLAY_NAME: "Supervision by Watara" 23 | CATEGORY: console 24 | AUTHOR: boogermann 25 | TARGET: pocket 26 | STAGE_FOLDER: staging 27 | RELEASE_FOLDER: release 28 | RECIPE_FOLDER: rom-recipes 29 | GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} 30 | RAETRO_WEBHOOK: ${{ secrets.RAETRO_WEBHOOK }} 31 | FPGAGAMING_WEBHOOK: ${{ secrets.FPGAGAMING_WEBHOOK }} 32 | 33 | steps: 34 | - name: "🧰 Checkout Repository" 35 | uses: actions/checkout@v3 36 | 37 | - name: "🏗️ Compile Design" 38 | run: | 39 | docker run --rm -v ${{ github.workspace }}:/build raetro/quartus:pocket \ 40 | quartus_sh --flow compile projects/${CORE}_${TARGET}.qpf 41 | 42 | - name: "🟦 Staging Files for Release" 43 | if: startsWith(github.ref, 'refs/tags/') 44 | id: stage 45 | run: | 46 | ############################################################ 47 | # Create Tags 48 | ############################################################ 49 | VERSION=${GITHUB_REF#refs/*/} 50 | DATE=$(date +'%Y-%m-%d') 51 | CORE_FOLDER=${AUTHOR}.${CORE} 52 | RBF_FILE=${CORE}_${TARGET}.rbf 53 | echo ::set-output name=VERSION::${VERSION} 54 | echo ::set-output name=REPO::${CATEGORY}-${CORE} 55 | echo ::set-output name=TITLE::${DISPLAY_NAME} 56 | echo ::set-output name=RELEASE_FOLDER::${RELEASE_FOLDER} 57 | echo ::set-output name=RELEASE_FILE::${CORE_FOLDER}_${TARGET}-${VERSION}.zip 58 | echo ::set-output name=RECIPE_FILE::${CORE_FOLDER}_rom-recipes-${VERSION}.zip 59 | ############################################################ 60 | # Clear/Create Folders 61 | ############################################################ 62 | rm -rf ${STAGE_FOLDER} ${RELEASE_FOLDER} 63 | mkdir -p ${STAGE_FOLDER} ${RELEASE_FOLDER} 64 | ############################################################ 65 | # Copy Packaging Folder 66 | ############################################################ 67 | cp -R pkg/${TARGET}/* ${STAGE_FOLDER} 68 | ############################################################ 69 | # Clear git and png source files 70 | ############################################################ 71 | find ./${STAGE_FOLDER} -type f \( -name "*.png*" -o -name "*.gitkeep*" \) -delete; 72 | ############################################################ 73 | # Update core.json Version and Release Date 74 | ############################################################ 75 | sed -i -e "s/<%- VERSION %>/${VERSION}/g" -e "s/<%- RELEASE_DATE %>/${DATE}/g" ${STAGE_FOLDER}/Cores/${CORE_FOLDER}/core.json 76 | ############################################################ 77 | # Reverse Bitstream 78 | ############################################################ 79 | wget https://gist.githubusercontent.com/boogermann/fba1f59c87f9c8c9404cc68878b4eb1a/raw/7e93a3560902e0136dcb29fa6c41d06f06d78fb2/reverse_bits.c 80 | g++ reverse_bits.c -o reverse_bits 81 | ./reverse_bits projects/output_files/${RBF_FILE} ${STAGE_FOLDER}/Cores/${CORE_FOLDER}/bitstream.rbf_r 82 | 83 | - name: "📦 Create Distribution Files" 84 | if: startsWith(github.ref, 'refs/tags/') 85 | id: zip 86 | run: | 87 | pushd ./${STAGE_FOLDER} 88 | zip -r ../${RELEASE_FOLDER}/${{ steps.stage.outputs.RELEASE_FILE }} . 89 | popd 90 | 91 | - name: "🚀 Create a new GitHub Release" 92 | uses: softprops/action-gh-release@v0.1.14 93 | if: startsWith(github.ref, 'refs/tags/') 94 | with: 95 | name: Release v${{ steps.stage.outputs.VERSION }} 96 | files: | 97 | ${{ steps.stage.outputs.RELEASE_FOLDER }}/* 98 | 99 | - name: "📢 Send Discord Announcements" 100 | if: startsWith(github.ref, 'refs/tags/') 101 | run: | 102 | declare -a StringArray=("${RAETRO_WEBHOOK}" "${FPGAGAMING_WEBHOOK}") 103 | for webhook_url in ${StringArray[@]}; do 104 | curl \ 105 | -H "Content-Type: application/json" \ 106 | -d '{ 107 | "username": "OpenGateware", 108 | "avatar_url": "https://avatars.githubusercontent.com/u/112050328", 109 | "embeds": [{ 110 | "color": 2021216, 111 | "title": "A new core stable release is available for the Pocket", 112 | "thumbnail": { "url": "https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/raw/master/docs/git-social.jpg" }, 113 | "fields": [ 114 | { "name": "Title", "value": "[${{ steps.stage.outputs.TITLE }}](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/)", "inline": true }, 115 | { "name": "Version", "value": "[${{ steps.stage.outputs.VERSION }}](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases/tag/${{ steps.stage.outputs.VERSION }})", "inline": true }, 116 | { "name": "Category", "value": "Arcade" }, 117 | { "name": "Developer", "value": "[Boogermann](https://github.com/boogermann)" }, 118 | { "name": "Download Core", "value": "[${{ steps.stage.outputs.RELEASE_FILE }}](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases/download/${{ steps.stage.outputs.VERSION }}/${{ steps.stage.outputs.RELEASE_FILE }})" }, 119 | { "name": "Previous Releases", "value": "[https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases)" } 120 | ] 121 | }] 122 | }' \ 123 | $webhook_url 124 | done 125 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Quartus directories and files 2 | db 3 | greybox_tmp 4 | hps_isw_handoff 5 | incremental_db 6 | output_files 7 | PLLJ_PLLSPE_INFO.txt 8 | simulation 9 | vip 10 | .qsys_edit 11 | *_netlist 12 | *_sim 13 | *.bak 14 | *.bsf 15 | *.cdf 16 | *.cmp 17 | *.csv 18 | *.done 19 | *.f 20 | *.pin 21 | *.pof 22 | *.ptf.* 23 | *.qar 24 | *.qarlog 25 | *.qdf 26 | *.qws 27 | *.rbf 28 | *.rbf_r 29 | *.rpt 30 | *.sip 31 | *.sld 32 | *.smsg 33 | *.sof 34 | *.sopc_builder 35 | *.sopcinfo 36 | *.spd 37 | *.summary 38 | *.txt 39 | *.xml 40 | *~ 41 | **/.DS_Store 42 | build_id.mif 43 | build_id.v 44 | c5_pin_model_dump.txt 45 | cr_ie_info.json 46 | # Gateman directories and files 47 | !.gateman/* 48 | !gateware.json 49 | !/pkg/* 50 | /pkg/**/*.rom 51 | /pkg/**/*.zip 52 | /staging/* 53 | /release/* 54 | # Editor directories and files 55 | .vscode 56 | .idea 57 | *.suo 58 | *.ntvs* 59 | *.njsproj 60 | *.sln 61 | *.sw? 62 | # Pocket directories and files 63 | !info.txt 64 | # ROMS Checklist 65 | !checklist.sha1 66 | !checklist.md5 67 | -------------------------------------------------------------------------------- /docs/CODE_OF_CONDUCT.md: -------------------------------------------------------------------------------- 1 | # Code Of Conduct 2 | 3 | ## Our Pledge 4 | 5 | In the interest of fostering an open and welcoming environment, we as contributors and leaders pledge to making participation in our project and our community a harassment-free experience for everyone, regardless of age, body size, disability, ethnicity, gender identity and expression, level or type of experience, education, socio-economic status, nationality, personal appearance, race, religion, or sexual identity and orientation. 6 | Note, however, that religion, political party, or other ideological affiliation provide no exemptions for the behavior we outline as unacceptable in this Code of Conduct. 7 | 8 | ## Our Standards 9 | 10 | We are committed to providing a friendly, safe and welcoming environment for all. 11 | 12 | Examples of behavior that contributes to creating a positive environment include: 13 | 14 | - Be kind and courteous to others 15 | - Using welcoming and inclusive language 16 | - Being respectful of differing viewpoints and experiences 17 | - Collaborating with other community members 18 | - Gracefully accepting constructive criticism 19 | - Focusing on what is best for the community 20 | - Showing empathy towards other community members 21 | 22 | Examples of unacceptable behavior by participants include: 23 | 24 | - The use of sexualized language or imagery and sexual attention or advances 25 | - The use of inappropriate images, including in a community member's avatar 26 | - The use of inappropriate language, including in a community member's nickname 27 | - Any spamming, flaming, baiting or other attention-stealing behavior 28 | - Excessive or unwelcome helping; answering outside the scope of the question asked 29 | - Trolling, insulting/derogatory comments, and personal or political attacks 30 | - Public or private harassment 31 | - Publishing others' private information, such as a physical or electronic address, without explicit permission 32 | - Other conduct which could reasonably be considered inappropriate 33 | 34 | The goal of the standards and moderation guidelines outlined here is to build and maintain a respectful community. We ask that you don’t just aim to be "technically unimpeachable", but rather try to be your best self. 35 | 36 | We value many things beyond technical expertise, including collaboration and supporting others within our community. Providing a positive experience for other community members can have a much more significant impact than simply providing the correct answer. 37 | 38 | ## Our Responsibilities 39 | 40 | Project leaders are responsible for clarifying the standards of acceptable behavior and are expected to take appropriate and fair corrective action in response to any instances of unacceptable behavior. 41 | 42 | Project leaders respect all people who contribute through reporting issues, posting feature requests, updating documentation, metadata, artwork, manuals, videos, submitting pull requests or patches, and other activities. But also have the right and responsibility to remove, edit, or reject messages, comments, commits, code, issues, and other contributions that are not aligned to this Code of Conduct, or to ban temporarily or permanently any community member for other behaviors that they deem inappropriate, threatening, offensive, or harmful. 43 | 44 | ## Scope 45 | 46 | This Code of Conduct and the enforcement policies listed above apply to all Rætro Community venues. This includes but is not limited to any community spaces (both public and private), the entire Rætro Discord server, and all Rætro associated GitHub repositories. Examples of Rætro Community spaces include but are not limited to meet-ups, audio chats on the Rætro Discord, or interaction at a conference. 47 | 48 | This Code of Conduct applies both within project spaces and in public spaces when an individual is representing the project or its community. As a community member, you are representing our community, and are expected to behave accordingly. 49 | 50 | ## Enforcement 51 | 52 | Instances of abusive, harassing, or otherwise unacceptable behavior may be reported by contacting the project team at or contact [community@raetro.org][conduct-email]. 53 | All complaints will be reviewed and investigated and will result in a response that is deemed necessary and appropriate to the circumstances. 54 | The project team is obligated to maintain confidentiality with regard to the reporter of an incident. 55 | Further details of specific enforcement policies may be posted separately. 56 | 57 | Project maintainers who do not follow or enforce the Code of Conduct in good faith may face temporary or permanent repercussions as determined by other members of the project's leadership. 58 | 59 | ## Attribution 60 | 61 | This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4, available at https://www.contributor-covenant.org/version/1/4/code-of-conduct.html, and the Rust Code of Conduct, available at https://www.rust-lang.org/en-US/conduct.html and the Adafruit Community Code of Conduct, available at https://github.com/adafruit/Adafruit_Community_Code_of_Conduct. 62 | 63 | [homepage]: https://www.contributor-covenant.org 64 | [conduct-email]: mailto:community@raetro.org 65 | -------------------------------------------------------------------------------- /docs/README.md: -------------------------------------------------------------------------------- 1 | [![Supervision Logo](supervision-logo.png)](#) 2 | 3 | --- 4 | 5 | [![Active Development](https://img.shields.io/badge/Maintenance%20Level-Actively%20Developed-brightgreen.svg)](#) 6 | [![Build](https://github.com/opengateware/console-supervision/actions/workflows/build-pocket.yml/badge.svg)](https://github.com/opengateware/console-supervision/actions/workflows/build-pocket.yml) 7 | [![release](https://img.shields.io/github/release/opengateware/console-supervision.svg)](https://github.com/opengateware/console-supervision/releases) 8 | [![license](https://img.shields.io/github/license/opengateware/console-supervision.svg?label=License&color=yellow)](#legal-notices) 9 | [![issues](https://img.shields.io/github/issues/opengateware/console-supervision.svg?label=Issues&color=red)](https://github.com/opengateware/console-supervision/issues) 10 | [![stars](https://img.shields.io/github/stars/opengateware/console-supervision.svg?label=Project%20Stars)](https://github.com/opengateware/console-supervision/stargazers) 11 | [![discord](https://img.shields.io/discord/676418475635507210.svg?logo=discord&logoColor=white&label=Discord&color=5865F2)](https://chat.raetro.org) 12 | [![Twitter Follow](https://img.shields.io/twitter/follow/marcusjordan?style=social)](https://twitter.com/marcusjordan) 13 | 14 | ## [Watara Supervision](https://en.wikipedia.org/wiki/Watara_Supervision) Compatible Gateware IP Core 15 | 16 | This Implementation of a compatible Watara Supervision hardware in HDL is the work of [Pierre Cornier](https://github.com/pcornier) and [Jamie Blanks](https://github.com/Kitrinx). 17 | 18 | ## Overview 19 | 20 | The Watara Supervision, also known as the QuickShot Supervision in the UK, is a monochrome handheld game console which was introduced in 1992 as a low-cost competitor for Nintendo's Game Boy. It came packaged with a game called Crystball, which is similar to Breakout. One unique feature of the Supervision was that it could be linked up to a television via a link cable. Games played in this way would display in four colors, much like Nintendo's Super Game Boy add-on for the SNES. A full color TV link was also in the works, but because of the Supervision's failure to make a major impression among gamers it was cancelled, along with the games which were in development for it. Only a tiny handful of games were developed by third parties and many were developed in Taiwan or Hong Kong. 21 | 22 | ## Technical specifications 23 | 24 | - The CPU is an 8-bit WDC 65C02 processor. 25 | - The Supervision screen is 2.37 inches x 2.37 inches, or 160 pixels x 160 pixels. It uses an LCD that can display 4 monochrome shades. 26 | - The unit is powered by 4 AA batteries or a 6V AC/DC adapter. 27 | - The unit includes a cartridge port, contrast dial, and a DB-9 connector port for multiplayer. 28 | - Sound is handled by 4 tonal and 1 Noise channel plus an additional DMA stereo output channel via the - built-in speaker or the headphone jack. Volume is controlled with a dial. 29 | 30 | ## Usage 31 | 32 | ROMs should be placed in `/Assets/supervision/common` 33 | 34 | ## Compatible Platforms 35 | 36 | - Analogue Pocket 37 | 38 | ## Credits and acknowledgment 39 | 40 | - [Jamie Blanks](https://github.com/Kitrinx) 41 | - [Jens Gutschmidt](https://opencores.org/projects/cpu65c02_true_cycle) 42 | - [Osman Celimli](http://www.tailchao.com/index.php) 43 | - [Pierre Cornier] 44 | - [Trash Uncle](https://github.com/trashuncle/Gameboy_Palettes) 45 | 46 | ## Support 47 | 48 | Please consider showing your support for this and future projects by contributing to the developers. While it isn't necessary, it's greatly appreciated. 49 | 50 | - IP Core Developer: [Pierre Cornier](https://www.patreon.com/pierco) 51 | 52 | ## Powered by Open-Source Software 53 | 54 | This project borrowed and use code from several other projects. A great thanks to their efforts! 55 | 56 | | Modules | Copyright/Developer | 57 | | :----------------------------- | :----------------------- | 58 | | [Supervision RTL] | 2020 (c) Pierre Cornier | 59 | | [R65C02] | 2008 (c) Jens Gutschmidt | 60 | 61 | ## License 62 | 63 | This work is licensed under multiple licenses. 64 | 65 | - All original source code is licensed under [GNU General Public License v3.0 or later] unless implicit indicated. 66 | - All documentation is licensed under [Creative Commons Attribution Share Alike 4.0 International] Public License. 67 | - Some configuration and data files are licensed under [Creative Commons Zero v1.0 Universal]. 68 | 69 | Open Gateware and any contributors reserve all others rights, whether under their respective copyrights, patents, or trademarks, whether by implication, estoppel or otherwise. 70 | 71 | Individual files may contain the following SPDX license tags as a shorthand for the above copyright and warranty notices: 72 | 73 | ```text 74 | SPDX-License-Identifier: GPL-3.0-or-later 75 | SPDX-License-Identifier: CC-BY-SA-4.0 76 | SPDX-License-Identifier: CC0-1.0 77 | ``` 78 | 79 | This eases machine processing of licensing information based on the SPDX License Identifiers that are available at . 80 | 81 | ## Legal Notices 82 | 83 | Supervision © 1992 Watara. All rights reserved. 84 | 85 | The Open Gateware authors and contributors or any of its maintainers are in no way associated with or endorsed by Intel®, Altera®, AMD®, Xilinx®, Lattice®, Microsoft® or any other company not implicit indicated. 86 | All other brands or product names are the property of their respective holders. 87 | 88 | [Supervision RTL]: https://github.com/MiSTer-devel/SuperVision_MiSTer/tree/master/rtl 89 | [R65C02]: https://opencores.org/projects/cpu65c02_true_cycle 90 | [Pierre Cornier]: https://github.com/pcornier 91 | 92 | [GNU General Public License v3.0 or later]: https://spdx.org/licenses/GPL-3.0-or-later.html 93 | [Creative Commons Attribution Share Alike 4.0 International]: https://spdx.org/licenses/CC-BY-SA-4.0.html 94 | [Creative Commons Zero v1.0 Universal]: https://spdx.org/licenses/CC0-1.0.html 95 | -------------------------------------------------------------------------------- /docs/git-social.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/opengateware/console-supervision/7c01e71e028de81171f74f835812dfc1e109cefe/docs/git-social.jpg -------------------------------------------------------------------------------- /docs/supervision-logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/opengateware/console-supervision/7c01e71e028de81171f74f835812dfc1e109cefe/docs/supervision-logo.png -------------------------------------------------------------------------------- /gateware.json: -------------------------------------------------------------------------------- 1 | { 2 | "name": "supervision", 3 | "displayName": "supervision", 4 | "description": "Watara SuperVision", 5 | "author": "boogermann", 6 | "version": "0.1.0", 7 | "license": "GPL-3.0-or-later", 8 | "repository": "https://github.com/opengateware/console-supervision", 9 | "keywords": [ 10 | "ecosystem:gateman" 11 | ], 12 | "scripts": { 13 | "verilator": "echo \"Error: no simulation specified\" && exit 1", 14 | "build:pocket": "quartus_sh --flow compile projects/supervision_pocket.qpf", 15 | "program:pocket": "quartus_pgm -m jtag -c 1 -o \"p;projects/output_files/supervision_pocket.sof@1\"" 16 | }, 17 | "hardware": { 18 | "id": "supervision", 19 | "name": "Supervision", 20 | "year": 1992, 21 | "manufacturer": "Watara" 22 | }, 23 | "platforms": { 24 | "pocket": "1.1.1" 25 | }, 26 | "modules": { 27 | "cpu-r65c02_tc": "1.5.2", 28 | "general-sync_fifo": "0.1.0", 29 | "pocket-dataloader": "1.0.0", 30 | "pocket-i2s": "1.0.0", 31 | "pocket-joypad": "1.0.0", 32 | "pocket-video": "1.0.0", 33 | "video-scanlines": "0.1.0" 34 | } 35 | } -------------------------------------------------------------------------------- /modules/cpu-r65c02_tc/fsm_intnmi.vhd: -------------------------------------------------------------------------------- 1 | -- VHDL Entity r65c02_tc.fsm_intnmi.symbol 2 | -- 3 | -- Created: 4 | -- by - eda.UNKNOWN (ENTW-7HPZ200) 5 | -- at - 12:35:56 10.09.2018 6 | -- 7 | -- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) 8 | -- 9 | LIBRARY ieee; 10 | USE ieee.std_logic_1164.all; 11 | USE ieee.std_logic_arith.all; 12 | 13 | entity fsm_intnmi is 14 | port( 15 | clk_clk_i : in std_logic; 16 | nmi_n_i : in std_logic; 17 | rst_nmi_i : in std_logic; 18 | rst_rst_n_i : in std_logic; 19 | ce : in std_logic; 20 | nmi_o : out std_logic 21 | ); 22 | 23 | -- Declarations 24 | 25 | end fsm_intnmi ; 26 | 27 | -- (C) 2008 - 2013 Jens Gutschmidt 28 | -- (email: opencores@vivare-services.com) 29 | -- 30 | -- Versions: 31 | -- Revision 1.8 2018/09/01 18:07:00 jens 32 | -- - NMI = '0' need at least 1 cycles for correct 33 | -- operation now (2 cycles in the past) 34 | -- 35 | -- Revision 1.7 2013/07/21 11:11:00 jens 36 | -- - Changing the title block and internal revision history 37 | -- 38 | -- Revision 1.6 2009/01/04 10:20:47 eda 39 | -- Changes for cosmetic issues only 40 | -- 41 | -- Revision 1.5 2009/01/04 09:23:10 eda 42 | -- - Delete unused nets and blocks (same as R6502_TC) 43 | -- - Rename blocks 44 | -- 45 | -- Revision 1.4 2009/01/03 16:53:02 eda 46 | -- - Unused nets and blocks deleted 47 | -- - Renamed blocks 48 | -- 49 | -- Revision 1.3 2009/01/03 16:42:02 eda 50 | -- - Unused nets and blocks deleted 51 | -- - Renamed blocks 52 | -- 53 | -- Revision 1.2 2008/12/31 19:31:24 eda 54 | -- Production Release 55 | -- 56 | -- 57 | -- 58 | -- VHDL Architecture r65c02_tc.fsm_intnmi.fsm 59 | -- 60 | -- Created: 61 | -- by - eda.UNKNOWN (ENTW-7HPZ200) 62 | -- at - 12:35:56 10.09.2018 63 | -- 64 | -- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) 65 | -- 66 | -- COPYRIGHT (C) 2008 - 2013 by Jens Gutschmidt 67 | -- 68 | -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. 69 | -- 70 | -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. 71 | -- 72 | -- You should have received a copy of the GNU General Public License along with this program. If not, see . 73 | -- 74 | -- 75 | LIBRARY ieee; 76 | USE ieee.std_logic_1164.all; 77 | USE ieee.std_logic_arith.all; 78 | 79 | architecture fsm of fsm_intnmi is 80 | 81 | type state_type is ( 82 | idle, 83 | idle1, 84 | IMP 85 | ); 86 | 87 | -- State vector declaration 88 | attribute state_vector : string; 89 | attribute state_vector of fsm : architecture is "current_state"; 90 | 91 | -- Declare current and next state signals 92 | signal current_state : state_type; 93 | signal next_state : state_type; 94 | 95 | -- Declare any pre-registered internal signals 96 | signal nmi_o_cld : std_logic ; 97 | 98 | begin 99 | 100 | ----------------------------------------------------------------- 101 | clocked_proc : process ( 102 | clk_clk_i, 103 | ce, 104 | rst_rst_n_i 105 | ) 106 | ----------------------------------------------------------------- 107 | begin 108 | if (rst_rst_n_i = '0') then 109 | current_state <= idle; 110 | -- Default Reset Values 111 | nmi_o_cld <= '0'; 112 | elsif (clk_clk_i'event and clk_clk_i = '1' and ce = '1') then 113 | current_state <= next_state; 114 | -- Default Assignment To Internals 115 | nmi_o_cld <= '0'; 116 | 117 | -- Combined Actions 118 | case current_state is 119 | when idle1 => 120 | if (nmi_n_i = '0') then 121 | nmi_o_cld <= '1'; 122 | end if; 123 | when IMP => 124 | nmi_o_cld <= '1'; 125 | if (rst_nmi_i = '1') then 126 | nmi_o_cld <= '0'; 127 | end if; 128 | when others => 129 | null; 130 | end case; 131 | end if; 132 | end process clocked_proc; 133 | 134 | ----------------------------------------------------------------- 135 | nextstate_proc : process ( 136 | current_state, 137 | nmi_n_i, 138 | rst_nmi_i 139 | ) 140 | ----------------------------------------------------------------- 141 | begin 142 | case current_state is 143 | when idle => 144 | if (nmi_n_i = '1') then 145 | next_state <= idle1; 146 | else 147 | next_state <= idle; 148 | end if; 149 | when idle1 => 150 | if (nmi_n_i = '0') then 151 | next_state <= IMP; 152 | else 153 | next_state <= idle1; 154 | end if; 155 | when IMP => 156 | if (rst_nmi_i = '1') then 157 | next_state <= idle; 158 | else 159 | next_state <= IMP; 160 | end if; 161 | when others => 162 | next_state <= idle; 163 | end case; 164 | end process nextstate_proc; 165 | 166 | -- Concurrent Statements 167 | -- Clocked output assignments 168 | nmi_o <= nmi_o_cld; 169 | end fsm; 170 | -------------------------------------------------------------------------------- /modules/cpu-r65c02_tc/index.qip: -------------------------------------------------------------------------------- 1 | # ============================================================================== 2 | # Quartus Prime QIP Index File 3 | # ============================================================================== 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "core.vhd"] 5 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "fsm_execution_unit.vhd"] 6 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "fsm_intnmi.vhd"] 7 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "r65c02_tc.vhd"] 8 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "regbank_axy.vhd"] 9 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "reg_pc.vhd"] 10 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "reg_sp.vhd"] 11 | -------------------------------------------------------------------------------- /modules/cpu-r65c02_tc/r65c02_tc.vhd: -------------------------------------------------------------------------------- 1 | -- VHDL Entity r65c02_tc.r65c02_tc.symbol 2 | -- 3 | -- Created: 4 | -- by - remoteghost.UNKNOWN (ENTW-7HPZ200) 5 | -- at - 10:24:26 07/21/13 6 | -- 7 | -- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) 8 | -- 9 | LIBRARY ieee; 10 | USE ieee.std_logic_1164.all; 11 | USE ieee.std_logic_arith.all; 12 | 13 | entity r65c02_tc is 14 | port( 15 | clk_clk_i : in std_logic; 16 | d_i : in std_logic_vector (7 downto 0); 17 | irq_n_i : in std_logic; 18 | nmi_n_i : in std_logic; 19 | rdy_i : in std_logic; 20 | rst_rst_n_i : in std_logic; 21 | so_n_i : in std_logic; 22 | ce : in std_logic; 23 | a_o : out std_logic_vector (15 downto 0); 24 | d_o : out std_logic_vector (7 downto 0); 25 | rd_o : out std_logic; 26 | sync_o : out std_logic; 27 | wr_n_o : out std_logic; 28 | wr_o : out std_logic 29 | ); 30 | 31 | -- Declarations 32 | 33 | end r65c02_tc ; 34 | 35 | -- (C) 2008 - 2018 Jens Gutschmidt 36 | -- (email: opencores@vivare-services.com) 37 | -- 38 | -- Versions: 39 | -- Revision 1.52 2018/09/10 12:14:00 jens 40 | -- - RESET generates SYNC now, 1 dead cycle delayed 41 | -- Revision 1.52 RC 2018/09/09 03:00:00 jens 42 | -- - ADC / SBC flags and A like R65C02 now 43 | -- Revision 1.52 BETA 2018/09/05 19:35:00 jens 44 | -- - BBRx/BBSx internal cycles like real 65C02 now 45 | -- - Bug Fix ADC and SBC in decimal mode (all op codes - 46 | -- 1 cycle is missing 47 | -- - Bug Fix ADC and SBC in decimal mode (all op codes - 48 | -- "Overflow" flag was computed wrong) 49 | -- Revision 1.52 BETA 2018/09/02 18:49:00 jens 50 | -- - Interrupt NMI and IRQ processing via FETCH stage now 51 | -- Revision 1.52 BETA 2018/08/30 15:39:00 jens 52 | -- - Interrupt priority order is now: BRQ - NMI - IRQ 53 | -- - Performance improvements on-going (Mealy -> Moore) 54 | -- Revision 1.52 BETA 2018/08/23 20:27:00 jens 55 | -- - Bug Fixes All Branch Instructions 56 | -- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA) 57 | -- 3 cycles now if branch forward occur and the branch 58 | -- instruction lies on a xxFEh location. 59 | -- (BBR, BBS) 6 cycles now if branch forward occur and the 60 | -- branch instruction lies on a xxFDh location. 61 | -- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now 62 | -- - Bug Fix Now all cycles are delayable (WR and internal) 63 | -- 64 | -- Revision 1.51 RC 2014/04/19 14:44:00 jens 65 | -- (never submitted to opencores) 66 | -- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH. 67 | -- When the ABS address data bytes cross the page 68 | -- boundary (e.g. $02FE JMP hhll reads hh from 69 | -- $02FF and ll from $0200, instead $02FF and $0300) 70 | -- 71 | -- Revision 1.5 RC 2013/08/01 11:00:00 jens 72 | -- - Change Block name to lower case 73 | -- - Bug Fix CMP (IND) - wrongly decoded as function AND 74 | -- - Bug Fix BRK should clear decimal flag in P Reg 75 | -- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address 76 | -- - Bug Fix Unknown Ops - Used always 1b2c NOP ($EA) - new NOPs created 77 | -- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong) 78 | -- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed 79 | -- - Bug Fix RTI - should increment stack pointer 80 | -- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates. 81 | -- - Bug Fix ADC and SBC (all sub codes - "Overflow" flag was computed wrong) 82 | -- - Bug Fix RMB, SMB Bug - Bit position decoded wrong 83 | -- 84 | -- Revision 1.4 2013/07/21 11:11:00 jens 85 | -- - Changing the title block and internal revision history 86 | -- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH) 87 | -- 88 | -- Revision 1.3 2009/01/04 10:20:50 eda 89 | -- Changes for cosmetic issues only 90 | -- 91 | -- Revision 1.2 2009/01/04 09:23:12 eda 92 | -- - Delete unused nets and blocks (same as R6502_TC) 93 | -- - Rename blocks 94 | -- - Re-arrage FSM symbols in block FSM_Execution_Unit 95 | -- 96 | -- Revision 1.1 2009/01/03 16:36:48 eda 97 | -- -- no description -- 98 | -- 99 | -- 100 | -- 101 | -- VHDL Architecture r65c02_tc.r65c02_tc.struct 102 | -- 103 | -- Created: 104 | -- by - eda.UNKNOWN (ENTW-7HPZ200) 105 | -- at - 12:21:16 10.09.2018 106 | -- 107 | -- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) 108 | -- 109 | -- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt 110 | -- 111 | -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. 112 | -- 113 | -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. 114 | -- 115 | -- You should have received a copy of the GNU General Public License along with this program. If not, see . 116 | -- 117 | -- 118 | LIBRARY ieee; 119 | USE ieee.std_logic_1164.all; 120 | USE ieee.std_logic_arith.all; 121 | 122 | library r65c02_tc; 123 | 124 | architecture struct of r65c02_tc is 125 | 126 | -- Architecture declarations 127 | 128 | -- Internal signal declarations 129 | 130 | 131 | -- Component Declarations 132 | component core 133 | port ( 134 | clk_clk_i : in std_logic ; 135 | d_i : in std_logic_vector (7 downto 0); 136 | irq_n_i : in std_logic ; 137 | nmi_n_i : in std_logic ; 138 | rdy_i : in std_logic ; 139 | rst_rst_n_i : in std_logic ; 140 | so_n_i : in std_logic ; 141 | ce : in std_logic ; 142 | a_o : out std_logic_vector (15 downto 0); 143 | d_o : out std_logic_vector (7 downto 0); 144 | rd_o : out std_logic ; 145 | sync_o : out std_logic ; 146 | wr_n_o : out std_logic ; 147 | wr_o : out std_logic 148 | ); 149 | end component; 150 | 151 | -- Optional embedded configurations 152 | -- pragma synthesis_off 153 | for all : core use entity r65c02_tc.core; 154 | -- pragma synthesis_on 155 | 156 | 157 | begin 158 | 159 | -- Instance port mappings. 160 | U_0 : core 161 | port map ( 162 | clk_clk_i => clk_clk_i, 163 | d_i => d_i, 164 | irq_n_i => irq_n_i, 165 | nmi_n_i => nmi_n_i, 166 | rdy_i => rdy_i, 167 | rst_rst_n_i => rst_rst_n_i, 168 | so_n_i => so_n_i, 169 | ce => ce, 170 | a_o => a_o, 171 | d_o => d_o, 172 | rd_o => rd_o, 173 | sync_o => sync_o, 174 | wr_n_o => wr_n_o, 175 | wr_o => wr_o 176 | ); 177 | 178 | end struct; 179 | -------------------------------------------------------------------------------- /modules/cpu-r65c02_tc/reg_pc.vhd: -------------------------------------------------------------------------------- 1 | -- VHDL Entity r65c02_tc.reg_pc.symbol 2 | -- 3 | -- Created: 4 | -- by - eda.UNKNOWN (ENTW-7HPZ200) 5 | -- at - 11:59:59 06.09.2018 6 | -- 7 | -- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) 8 | -- 9 | LIBRARY ieee; 10 | USE ieee.std_logic_1164.all; 11 | USE ieee.std_logic_arith.all; 12 | 13 | entity reg_pc is 14 | port( 15 | adr_i : in std_logic_vector (15 downto 0); 16 | clk_clk_i : in std_logic; 17 | ld_i : in std_logic_vector (1 downto 0); 18 | ld_pc_i : in std_logic; 19 | offset_i : in std_logic_vector (15 downto 0); 20 | rst_rst_n_i : in std_logic; 21 | sel_pc_in_i : in std_logic; 22 | sel_pc_val_i : in std_logic_vector (1 downto 0); 23 | ce : in std_logic; 24 | adr_nxt_pc_o : out std_logic_vector (15 downto 0); 25 | adr_pc_o : out std_logic_vector (15 downto 0) 26 | ); 27 | 28 | -- Declarations 29 | 30 | end reg_pc ; 31 | 32 | -- (C) 2008 - 2018 Jens Gutschmidt 33 | -- (email: opencores@vivare-services.com) 34 | -- 35 | -- Versions: 36 | -- Revision 1.7 2013/07/21 11:11:00 jens 37 | -- - Changing the title block and internal revision history 38 | -- 39 | -- Revision 1.6 2009/01/04 10:20:47 eda 40 | -- Changes for cosmetic issues only 41 | -- 42 | -- Revision 1.5 2009/01/04 09:23:10 eda 43 | -- - Delete unused nets and blocks (same as R6502_TC) 44 | -- - Rename blocks 45 | -- 46 | -- Revision 1.4 2009/01/03 16:53:02 eda 47 | -- - Unused nets and blocks deleted 48 | -- - Renamed blocks 49 | -- 50 | -- Revision 1.3 2009/01/03 16:42:02 eda 51 | -- - Unused nets and blocks deleted 52 | -- - Renamed blocks 53 | -- 54 | -- Revision 1.2 2008/12/31 19:31:24 eda 55 | -- Production Release 56 | -- 57 | -- 58 | -- 59 | -- VHDL Architecture r65c02_tc.reg_pc.struct 60 | -- 61 | -- Created: 62 | -- by - eda.UNKNOWN (ENTW-7HPZ200) 63 | -- at - 11:59:59 06.09.2018 64 | -- 65 | -- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) 66 | -- 67 | -- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt 68 | -- 69 | -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. 70 | -- 71 | -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. 72 | -- 73 | -- You should have received a copy of the GNU General Public License along with this program. If not, see . 74 | -- 75 | -- 76 | LIBRARY ieee; 77 | USE ieee.std_logic_1164.all; 78 | USE ieee.std_logic_arith.all; 79 | 80 | 81 | architecture struct of reg_pc is 82 | 83 | -- Architecture declarations 84 | 85 | -- Internal signal declarations 86 | signal adr_pc_high_o_i : std_logic_vector(7 downto 0); 87 | signal adr_pc_low_o_i : std_logic_vector(7 downto 0); 88 | signal adr_pc_o_i : std_logic_vector(15 downto 0); 89 | signal ci_o_i : std_logic; 90 | signal cout_pc_o_i : std_logic; 91 | signal load3_o_i : std_logic; 92 | signal load_o_i : std_logic; 93 | signal offset_high_o_i : std_logic_vector(7 downto 0); 94 | signal offset_low_o_i : std_logic_vector(7 downto 0); 95 | signal val_o_i : std_logic_vector(7 downto 0); 96 | signal val_one : std_logic_vector(7 downto 0); 97 | signal val_zero : std_logic_vector(7 downto 0); 98 | 99 | -- Implicit buffer signal declarations 100 | signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0); 101 | signal adr_pc_o_internal : std_logic_vector (15 downto 0); 102 | 103 | 104 | -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' 105 | signal mw_U_0reg_cval : std_logic_vector(7 downto 0); 106 | 107 | -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff' 108 | signal mw_U_4reg_cval : std_logic_vector(7 downto 0); 109 | 110 | -- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'split' 111 | signal mw_U_3temp_din : std_logic_vector(15 downto 0); 112 | 113 | -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'split' 114 | signal mw_U_5temp_din : std_logic_vector(15 downto 0); 115 | 116 | 117 | begin 118 | 119 | -- ModuleWare code(v1.12) for instance 'U_2' of 'add' 120 | u_2combo_proc: process (adr_pc_low_o_i, val_o_i) 121 | variable temp_din0 : std_logic_vector(8 downto 0); 122 | variable temp_din1 : std_logic_vector(8 downto 0); 123 | variable temp_sum : unsigned(8 downto 0); 124 | variable temp_carry : std_logic; 125 | begin 126 | temp_din0 := '0' & adr_pc_low_o_i; 127 | temp_din1 := '0' & val_o_i; 128 | temp_carry := '0'; 129 | temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; 130 | adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 downto 0),8); 131 | cout_pc_o_i <= temp_sum(8) ; 132 | end process u_2combo_proc; 133 | 134 | -- ModuleWare code(v1.12) for instance 'U_11' of 'add' 135 | u_11combo_proc: process (adr_pc_high_o_i, offset_high_o_i, ci_o_i) 136 | variable temp_din0 : std_logic_vector(8 downto 0); 137 | variable temp_din1 : std_logic_vector(8 downto 0); 138 | variable temp_sum : unsigned(8 downto 0); 139 | variable temp_carry : std_logic; 140 | begin 141 | temp_din0 := '0' & adr_pc_high_o_i; 142 | temp_din1 := '0' & offset_high_o_i; 143 | temp_carry := ci_o_i; 144 | temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; 145 | adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 downto 0),8); 146 | end process u_11combo_proc; 147 | 148 | -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' 149 | adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; 150 | u_0seq_proc: process (clk_clk_i, ce, rst_rst_n_i) 151 | begin 152 | if (rst_rst_n_i = '0') then 153 | mw_U_0reg_cval <= "00000000"; 154 | elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then 155 | if (load_o_i = '1') then 156 | mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0); 157 | end if; 158 | end if; 159 | end process u_0seq_proc; 160 | 161 | -- ModuleWare code(v1.12) for instance 'U_4' of 'adff' 162 | adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval; 163 | u_4seq_proc: process (clk_clk_i, ce, rst_rst_n_i) 164 | begin 165 | if (rst_rst_n_i = '0') then 166 | mw_U_4reg_cval <= "00000000"; 167 | elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then 168 | if (load3_o_i = '1') then 169 | mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8); 170 | end if; 171 | end if; 172 | end process u_4seq_proc; 173 | 174 | -- ModuleWare code(v1.12) for instance 'U_6' of 'and' 175 | load_o_i <= ld_pc_i and ld_i(0); 176 | 177 | -- ModuleWare code(v1.12) for instance 'U_7' of 'and' 178 | load3_o_i <= ld_pc_i and ld_i(1); 179 | 180 | -- ModuleWare code(v1.12) for instance 'U_10' of 'and' 181 | ci_o_i <= cout_pc_o_i and ld_pc_i; 182 | 183 | -- ModuleWare code(v1.12) for instance 'U_1' of 'constval' 184 | val_zero <= "00000000"; 185 | 186 | -- ModuleWare code(v1.12) for instance 'U_9' of 'constval' 187 | val_one <= "00000001"; 188 | 189 | -- ModuleWare code(v1.12) for instance 'U_8' of 'mux' 190 | u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i) 191 | begin 192 | case sel_pc_in_i is 193 | when '0' => adr_pc_o_i <= adr_pc_o_internal; 194 | when '1' => adr_pc_o_i <= adr_i; 195 | when others => adr_pc_o_i <= (others => 'X'); 196 | end case; 197 | end process u_8combo_proc; 198 | 199 | -- ModuleWare code(v1.12) for instance 'U_13' of 'mux' 200 | u_13combo_proc: process(val_one, val_zero, offset_low_o_i, 201 | sel_pc_val_i) 202 | begin 203 | case sel_pc_val_i is 204 | when "00" => val_o_i <= val_one; 205 | when "01" => val_o_i <= val_zero; 206 | when "10" => val_o_i <= offset_low_o_i; 207 | when "11" => val_o_i <= val_zero; 208 | when others => val_o_i <= (others => 'X'); 209 | end case; 210 | end process u_13combo_proc; 211 | 212 | -- ModuleWare code(v1.12) for instance 'U_3' of 'split' 213 | mw_U_3temp_din <= adr_pc_o_i; 214 | u_3combo_proc: process (mw_U_3temp_din) 215 | variable temp_din: std_logic_vector(15 downto 0); 216 | begin 217 | temp_din := mw_U_3temp_din(15 downto 0); 218 | adr_pc_low_o_i <= temp_din(7 downto 0); 219 | adr_pc_high_o_i <= temp_din(15 downto 8); 220 | end process u_3combo_proc; 221 | 222 | -- ModuleWare code(v1.12) for instance 'U_5' of 'split' 223 | mw_U_5temp_din <= offset_i; 224 | u_5combo_proc: process (mw_U_5temp_din) 225 | variable temp_din: std_logic_vector(15 downto 0); 226 | begin 227 | temp_din := mw_U_5temp_din(15 downto 0); 228 | offset_low_o_i <= temp_din(7 downto 0); 229 | offset_high_o_i <= temp_din(15 downto 8); 230 | end process u_5combo_proc; 231 | 232 | -- Instance port mappings. 233 | 234 | -- Implicit buffered output assignments 235 | adr_nxt_pc_o <= adr_nxt_pc_o_internal; 236 | adr_pc_o <= adr_pc_o_internal; 237 | 238 | end struct; 239 | -------------------------------------------------------------------------------- /modules/cpu-r65c02_tc/reg_sp.vhd: -------------------------------------------------------------------------------- 1 | -- VHDL Entity r65c02_tc.reg_sp.symbol 2 | -- 3 | -- Created: 4 | -- by - eda.UNKNOWN (ENTW-7HPZ200) 5 | -- at - 12:04:08 06.09.2018 6 | -- 7 | -- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) 8 | -- 9 | LIBRARY ieee; 10 | USE ieee.std_logic_1164.all; 11 | USE ieee.std_logic_arith.all; 12 | 13 | entity reg_sp is 14 | port( 15 | adr_low_i : in std_logic_vector (7 downto 0); 16 | clk_clk_i : in std_logic; 17 | ld_low_i : in std_logic; 18 | ld_sp_i : in std_logic; 19 | rst_rst_n_i : in std_logic; 20 | sel_sp_as_i : in std_logic; 21 | sel_sp_in_i : in std_logic; 22 | ce : in std_logic; 23 | adr_sp_o : out std_logic_vector (15 downto 0) 24 | ); 25 | 26 | -- Declarations 27 | 28 | end reg_sp ; 29 | 30 | -- (C) 2008 - 2018 Jens Gutschmidt 31 | -- (email: opencores@vivare-services.com) 32 | -- 33 | -- Versions: 34 | -- Revision 1.7 2013/07/21 11:11:00 jens 35 | -- - Changing the title block and internal revision history 36 | -- 37 | -- Revision 1.6 2009/01/04 10:20:47 eda 38 | -- Changes for cosmetic issues only 39 | -- 40 | -- Revision 1.5 2009/01/04 09:23:10 eda 41 | -- - Delete unused nets and blocks (same as R6502_TC) 42 | -- - Rename blocks 43 | -- 44 | -- Revision 1.4 2009/01/03 16:53:02 eda 45 | -- - Unused nets and blocks deleted 46 | -- - Renamed blocks 47 | -- 48 | -- Revision 1.3 2009/01/03 16:42:02 eda 49 | -- - Unused nets and blocks deleted 50 | -- - Renamed blocks 51 | -- 52 | -- Revision 1.2 2008/12/31 19:31:24 eda 53 | -- Production Release 54 | -- 55 | -- 56 | -- 57 | -- VHDL Architecture r65c02_tc.reg_sp.struct 58 | -- 59 | -- Created: 60 | -- by - eda.UNKNOWN (ENTW-7HPZ200) 61 | -- at - 12:04:08 06.09.2018 62 | -- 63 | -- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) 64 | -- 65 | -- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt 66 | -- 67 | -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. 68 | -- 69 | -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. 70 | -- 71 | -- You should have received a copy of the GNU General Public License along with this program. If not, see . 72 | -- 73 | -- 74 | LIBRARY ieee; 75 | USE ieee.std_logic_1164.all; 76 | USE ieee.std_logic_arith.all; 77 | 78 | 79 | architecture struct of reg_sp is 80 | 81 | -- Architecture declarations 82 | 83 | -- Internal signal declarations 84 | signal adr_sp_low_o_i : std_logic_vector(7 downto 0); 85 | signal load_o_i : std_logic; 86 | signal result_low1_o_i : std_logic_vector(7 downto 0); 87 | signal result_low_o_i : std_logic_vector(7 downto 0); 88 | signal sp_as_n_o_i : std_logic; 89 | signal val_one : std_logic_vector(7 downto 0); 90 | 91 | -- Implicit buffer signal declarations 92 | signal adr_sp_o_internal : std_logic_vector (15 downto 0); 93 | 94 | 95 | -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' 96 | signal mw_U_0reg_cval : std_logic_vector(7 downto 0); 97 | 98 | 99 | begin 100 | 101 | -- ModuleWare code(v1.12) for instance 'U_11' of 'addsub' 102 | u_11combo_proc: process (adr_sp_low_o_i, val_one, sp_as_n_o_i) 103 | variable temp_din0 : std_logic_vector(8 downto 0); 104 | variable temp_din1 : std_logic_vector(8 downto 0); 105 | variable temp_sum : unsigned(8 downto 0); 106 | variable temp_carry : std_logic; 107 | begin 108 | temp_din0 := '0' & adr_sp_low_o_i; 109 | temp_din1 := '0' & val_one; 110 | temp_carry := '0'; 111 | if (sp_as_n_o_i = '1') then 112 | temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; 113 | else 114 | temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry; 115 | end if; 116 | result_low_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8); 117 | end process u_11combo_proc; 118 | 119 | -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' 120 | adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; 121 | u_0seq_proc: process (clk_clk_i, ce, rst_rst_n_i) 122 | begin 123 | if (rst_rst_n_i = '0') then 124 | mw_U_0reg_cval <= "00000000"; 125 | elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then 126 | if (load_o_i = '1') then 127 | mw_U_0reg_cval <= result_low1_o_i; 128 | end if; 129 | end if; 130 | end process u_0seq_proc; 131 | 132 | -- ModuleWare code(v1.12) for instance 'U_6' of 'and' 133 | load_o_i <= ld_sp_i and ld_low_i; 134 | 135 | -- ModuleWare code(v1.12) for instance 'U_3' of 'buff' 136 | adr_sp_o_internal(15 DOWNTO 8) <= val_one; 137 | 138 | -- ModuleWare code(v1.12) for instance 'U_4' of 'constval' 139 | val_one <= "00000001"; 140 | 141 | -- ModuleWare code(v1.12) for instance 'U_2' of 'inv' 142 | sp_as_n_o_i <= not(sel_sp_as_i); 143 | 144 | -- ModuleWare code(v1.12) for instance 'U_8' of 'mux' 145 | u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i) 146 | begin 147 | case sel_sp_in_i is 148 | when '0' => result_low1_o_i <= result_low_o_i; 149 | when '1' => result_low1_o_i <= adr_low_i; 150 | when others => result_low1_o_i <= (others => 'X'); 151 | end case; 152 | end process u_8combo_proc; 153 | 154 | -- ModuleWare code(v1.12) for instance 'U_10' of 'tap' 155 | adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0); 156 | 157 | -- Instance port mappings. 158 | 159 | -- Implicit buffered output assignments 160 | adr_sp_o <= adr_sp_o_internal; 161 | 162 | end struct; 163 | -------------------------------------------------------------------------------- /modules/cpu-r65c02_tc/regbank_axy.vhd: -------------------------------------------------------------------------------- 1 | -- VHDL Entity r65c02_tc.regbank_axy.symbol 2 | -- 3 | -- Created: 4 | -- by - eda.UNKNOWN (ENTW-7HPZ200) 5 | -- at - 20:45:48 27.08.2018 6 | -- 7 | -- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) 8 | -- 9 | LIBRARY ieee; 10 | USE ieee.std_logic_1164.all; 11 | USE ieee.std_logic_arith.all; 12 | 13 | entity regbank_axy is 14 | port( 15 | clk_clk_i : in std_logic; 16 | d_regs_in_i : in std_logic_vector (7 downto 0); 17 | load_regs_i : in std_logic; 18 | rst_rst_n_i : in std_logic; 19 | sel_rb_in_i : in std_logic_vector (1 downto 0); 20 | sel_rb_out_i : in std_logic_vector (1 downto 0); 21 | sel_reg_i : in std_logic_vector (1 downto 0); 22 | ce : in std_logic; 23 | d_regs_out_o : out std_logic_vector (7 downto 0); 24 | q_a_o : out std_logic_vector (7 downto 0); 25 | q_x_o : out std_logic_vector (7 downto 0); 26 | q_y_o : out std_logic_vector (7 downto 0) 27 | ); 28 | 29 | -- Declarations 30 | 31 | end regbank_axy ; 32 | 33 | -- (C) 2008 - 2018 Jens Gutschmidt 34 | -- (email: opencores@vivare-services.com) 35 | -- 36 | -- Versions: 37 | -- Revision 1.7 2013/07/21 11:11:00 jens 38 | -- - Changing the title block and internal revision history 39 | -- 40 | -- Revision 1.6 2009/01/04 10:20:47 eda 41 | -- Changes for cosmetic issues only 42 | -- 43 | -- Revision 1.5 2009/01/04 09:23:10 eda 44 | -- - Delete unused nets and blocks (same as R6502_TC) 45 | -- - Rename blocks 46 | -- 47 | -- Revision 1.4 2009/01/03 16:53:02 eda 48 | -- - Unused nets and blocks deleted 49 | -- - Renamed blocks 50 | -- 51 | -- Revision 1.3 2009/01/03 16:42:02 eda 52 | -- - Unused nets and blocks deleted 53 | -- - Renamed blocks 54 | -- 55 | -- Revision 1.2 2008/12/31 19:31:24 eda 56 | -- Production Release 57 | -- 58 | -- 59 | -- 60 | -- VHDL Architecture r65c02_tc.regbank_axy.struct 61 | -- 62 | -- Created: 63 | -- by - eda.UNKNOWN (ENTW-7HPZ200) 64 | -- at - 12:04:48 06.09.2018 65 | -- 66 | -- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) 67 | -- 68 | -- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt 69 | -- 70 | -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. 71 | -- 72 | -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. 73 | -- 74 | -- You should have received a copy of the GNU General Public License along with this program. If not, see . 75 | -- 76 | -- 77 | LIBRARY ieee; 78 | USE ieee.std_logic_1164.all; 79 | USE ieee.std_logic_arith.all; 80 | 81 | 82 | architecture struct of regbank_axy is 83 | 84 | -- Architecture declarations 85 | 86 | -- Internal signal declarations 87 | signal ld : std_logic_vector(2 downto 0); 88 | signal load1_o_i : std_logic; 89 | signal load2_o_i : std_logic; 90 | signal load_o_i : std_logic; 91 | signal q_mux_o_i : std_logic_vector(7 downto 0); 92 | signal val_zero : std_logic_vector(7 downto 0); 93 | 94 | -- Implicit buffer signal declarations 95 | signal q_a_o_internal : std_logic_vector (7 downto 0); 96 | signal q_x_o_internal : std_logic_vector (7 downto 0); 97 | signal q_y_o_internal : std_logic_vector (7 downto 0); 98 | 99 | 100 | -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' 101 | signal mw_U_0reg_cval : std_logic_vector(7 downto 0); 102 | 103 | -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff' 104 | signal mw_U_4reg_cval : std_logic_vector(7 downto 0); 105 | 106 | -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'adff' 107 | signal mw_U_5reg_cval : std_logic_vector(7 downto 0); 108 | 109 | 110 | begin 111 | 112 | -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' 113 | q_a_o_internal <= mw_U_0reg_cval; 114 | u_0seq_proc: process (clk_clk_i, ce, rst_rst_n_i) 115 | begin 116 | if (rst_rst_n_i = '0') then 117 | mw_U_0reg_cval <= "00000000"; 118 | elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then 119 | if (load_o_i = '1') then 120 | mw_U_0reg_cval <= q_mux_o_i; 121 | end if; 122 | end if; 123 | end process u_0seq_proc; 124 | 125 | -- ModuleWare code(v1.12) for instance 'U_4' of 'adff' 126 | q_x_o_internal <= mw_U_4reg_cval; 127 | u_4seq_proc: process (clk_clk_i, ce, rst_rst_n_i) 128 | begin 129 | if (rst_rst_n_i = '0') then 130 | mw_U_4reg_cval <= "00000000"; 131 | elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then 132 | if (load1_o_i = '1') then 133 | mw_U_4reg_cval <= q_mux_o_i; 134 | end if; 135 | end if; 136 | end process u_4seq_proc; 137 | 138 | -- ModuleWare code(v1.12) for instance 'U_5' of 'adff' 139 | q_y_o_internal <= mw_U_5reg_cval; 140 | u_5seq_proc: process (clk_clk_i, ce, rst_rst_n_i) 141 | begin 142 | if (rst_rst_n_i = '0') then 143 | mw_U_5reg_cval <= "00000000"; 144 | elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then 145 | if (load2_o_i = '1') then 146 | mw_U_5reg_cval <= q_mux_o_i; 147 | end if; 148 | end if; 149 | end process u_5seq_proc; 150 | 151 | -- ModuleWare code(v1.12) for instance 'U_6' of 'and' 152 | load_o_i <= load_regs_i and ld(0); 153 | 154 | -- ModuleWare code(v1.12) for instance 'U_7' of 'and' 155 | load1_o_i <= load_regs_i and ld(1); 156 | 157 | -- ModuleWare code(v1.12) for instance 'U_8' of 'and' 158 | load2_o_i <= load_regs_i and ld(2); 159 | 160 | -- ModuleWare code(v1.12) for instance 'U_11' of 'constval' 161 | val_zero <= "00000000"; 162 | 163 | -- ModuleWare code(v1.12) for instance 'U_1' of 'decoder1' 164 | u_1combo_proc: process (sel_reg_i) 165 | begin 166 | ld <= (others => '0'); 167 | case sel_reg_i is 168 | when "00" => ld(0) <= '1'; 169 | when "01" => ld(1) <= '1'; 170 | when "10" => ld(2) <= '1'; 171 | when others => ld <= (others => '0'); 172 | end case; 173 | end process u_1combo_proc; 174 | 175 | -- ModuleWare code(v1.12) for instance 'U_2' of 'mux' 176 | u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal, 177 | val_zero, sel_rb_out_i) 178 | begin 179 | case sel_rb_out_i is 180 | when "00" => d_regs_out_o <= q_a_o_internal; 181 | when "01" => d_regs_out_o <= q_x_o_internal; 182 | when "10" => d_regs_out_o <= q_y_o_internal; 183 | when "11" => d_regs_out_o <= val_zero; 184 | when others => d_regs_out_o <= (others => 'X'); 185 | end case; 186 | end process u_2combo_proc; 187 | 188 | -- ModuleWare code(v1.12) for instance 'U_3' of 'mux' 189 | u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal, 190 | d_regs_in_i, sel_rb_in_i) 191 | begin 192 | case sel_rb_in_i is 193 | when "00" => q_mux_o_i <= q_a_o_internal; 194 | when "01" => q_mux_o_i <= q_y_o_internal; 195 | when "10" => q_mux_o_i <= q_x_o_internal; 196 | when "11" => q_mux_o_i <= d_regs_in_i; 197 | when others => q_mux_o_i <= (others => 'X'); 198 | end case; 199 | end process u_3combo_proc; 200 | 201 | -- Instance port mappings. 202 | 203 | -- Implicit buffered output assignments 204 | q_a_o <= q_a_o_internal; 205 | q_x_o <= q_x_o_internal; 206 | q_y_o <= q_y_o_internal; 207 | 208 | end struct; 209 | -------------------------------------------------------------------------------- /modules/general-sync_fifo/index.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "sync_fifo.sv"] 2 | -------------------------------------------------------------------------------- /modules/general-sync_fifo/sync_fifo.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // SPDX-License-Identifier: MIT 3 | // SPDX-FileType: SOURCE 4 | // SPDX-FileCopyrightText: (c) 2022 Adam Gastineau 5 | //------------------------------------------------------------------------------ 6 | // Permission is hereby granted, free of charge, to any person obtaining a copy 7 | // of this software and associated documentation files (the "Software"), to deal 8 | // in the Software without restriction, including without limitation the rights 9 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | // copies of the Software, and to permit persons to whom the Software is 11 | // furnished to do so, subject to the following conditions: 12 | // 13 | // The above copyright notice and this permission notice shall be included in 14 | // all copies or substantial portions of the Software. 15 | // 16 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | // SOFTWARE. 23 | //------------------------------------------------------------------------------ 24 | // Easily reusable method for synchronizing multiple bits across clock domains 25 | // Uses a shallow depth (4 entries) FIFO, so make sure to empty it quickly 26 | //------------------------------------------------------------------------------ 27 | 28 | module sync_fifo #( 29 | parameter WIDTH = 2 30 | ) ( 31 | input wire clk_write, 32 | input wire clk_read, 33 | 34 | input wire write_en, 35 | input wire [WIDTH - 1:0] data_in, 36 | output reg [WIDTH - 1:0] data_out = 0 37 | ); 38 | 39 | reg read_req = 0; 40 | wire empty; 41 | 42 | wire [WIDTH - 1:0] fifo_out; 43 | 44 | dcfifo dcfifo_component ( 45 | .data(data_in), 46 | .rdclk(clk_read), 47 | .rdreq(read_req), 48 | .wrclk(clk_write), 49 | .wrreq(write_en), 50 | .q(fifo_out), 51 | .rdempty(empty), 52 | .aclr(), 53 | .eccstatus(), 54 | .rdfull(), 55 | .rdusedw(), 56 | .wrempty(), 57 | .wrfull(), 58 | .wrusedw() 59 | ); 60 | 61 | defparam dcfifo_component.intended_device_family = "Cyclone V", 62 | dcfifo_component.lpm_numwords = 4, 63 | dcfifo_component.lpm_showahead = "OFF", 64 | dcfifo_component.lpm_type = "dcfifo", 65 | dcfifo_component.lpm_width = 32, 66 | dcfifo_component.lpm_widthu = 2, 67 | dcfifo_component.overflow_checking = "ON", 68 | dcfifo_component.rdsync_delaypipe = 5, 69 | dcfifo_component.underflow_checking = "ON", 70 | dcfifo_component.use_eab = "ON", 71 | dcfifo_component.wrsync_delaypipe = 5; 72 | 73 | reg [1:0] read_state = 0; 74 | localparam READ_DELAY = 1; 75 | localparam READ_WRITE = 2; 76 | 77 | always @(posedge clk_read) begin 78 | read_req <= 0; 79 | 80 | if (~empty) begin 81 | read_state <= READ_DELAY; 82 | read_req <= 1; 83 | end 84 | 85 | case (read_state) 86 | READ_DELAY: begin 87 | read_state <= READ_WRITE; 88 | end 89 | READ_WRITE: begin 90 | read_state <= 0; 91 | data_out <= fifo_out; 92 | end 93 | endcase 94 | end 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /modules/pocket-dataloader/data_loader.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // SPDX-License-Identifier: MIT 3 | // SPDX-FileType: SOURCE 4 | // SPDX-FileCopyrightText: (c) 2022 Adam Gastineau 5 | //------------------------------------------------------------------------------ 6 | // Permission is hereby granted, free of charge, to any person obtaining a copy 7 | // of this software and associated documentation files (the "Software"), to deal 8 | // in the Software without restriction, including without limitation the rights 9 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | // copies of the Software, and to permit persons to whom the Software is 11 | // furnished to do so, subject to the following conditions: 12 | // 13 | // The above copyright notice and this permission notice shall be included in 14 | // all copies or substantial portions of the Software. 15 | // 16 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | // SOFTWARE. 23 | //------------------------------------------------------------------------------ 24 | // 25 | // A data loader for consuming APF bridge writes and directing them to some storage medium 26 | // 27 | // This takes the 32 bit words from APF, and splits it into four / OUTPUT_WORD_SIZE words (4 separate bytes, or 2 16-bit words). 28 | // You can configure the cycle delay by setting WRITE_MEM_CLOCK_DELAY 29 | // 30 | //------------------------------------------------------------------------------ 31 | 32 | module data_loader #( 33 | // Upper 4 bits of address 34 | parameter ADDRESS_MASK_UPPER_4 = 0, 35 | parameter ADDRESS_SIZE = 28, 36 | 37 | // Number of clk_memory cycles to delay each write output 38 | // Min 4. Component will assert this value is within the valid range 39 | // Be aware that APF sends data every ~75 74MHz cycles, so you cannot send data slower than this 40 | parameter WRITE_MEM_CLOCK_DELAY = 4, 41 | 42 | // Number of clk_memory cycles to hold the write_en signal high 43 | // Min 1. Component will assert this value is within the valid range 44 | parameter WRITE_MEM_EN_CYCLE_LENGTH = 1, 45 | 46 | // Word size in number of bytes. Can either be 1 (output 8 bits), or 2 (output 16 bits) 47 | // Component will assert this value is within the valid range 48 | parameter OUTPUT_WORD_SIZE = 1 49 | ) ( 50 | input wire clk_74a, 51 | input wire clk_memory, 52 | 53 | input wire bridge_wr, 54 | input wire bridge_endian_little, 55 | input wire [31:0] bridge_addr, 56 | input wire [31:0] bridge_wr_data, 57 | 58 | // These outputs are synced to the memory clock 59 | output reg write_en = 0, 60 | output reg [ADDRESS_SIZE-1:0] write_addr = 0, 61 | output reg [8 * OUTPUT_WORD_SIZE - 1:0] write_data = 0 62 | ); 63 | 64 | `define MAX(x, y) ((x > y) ? x : y) 65 | 66 | localparam WORD_SIZE = 8 * OUTPUT_WORD_SIZE; 67 | // Only use the lower 28 bits of the address 68 | localparam FIFO_SIZE = WORD_SIZE + 28; 69 | 70 | wire mem_empty; 71 | 72 | wire [FIFO_SIZE - 1:0] fifo_out; 73 | 74 | reg read_req = 0; 75 | reg write_req = 0; 76 | reg [31:0] shift_data; 77 | reg [27:0] buff_bridge_addr; 78 | 79 | wire [FIFO_SIZE - 1:0] fifo_in = {shift_data[WORD_SIZE-1:0], buff_bridge_addr[27:0]}; 80 | 81 | dcfifo dcfifo_component ( 82 | .data(fifo_in), 83 | .rdclk(clk_memory), 84 | .rdreq(read_req), 85 | .wrclk(clk_74a), 86 | .wrreq(write_req), 87 | .q(fifo_out), 88 | .rdempty(mem_empty) 89 | // .wrempty(), 90 | // .aclr(), 91 | // .eccstatus(), 92 | // .rdfull(), 93 | // .rdusedw(), 94 | // .wrfull(), 95 | // .wrusedw() 96 | ); 97 | 98 | defparam dcfifo_component.clocks_are_synchronized = "FALSE", 99 | dcfifo_component.intended_device_family = "Cyclone V", 100 | dcfifo_component.lpm_numwords = 4, 101 | dcfifo_component.lpm_showahead = "OFF", 102 | dcfifo_component.lpm_type = "dcfifo", 103 | dcfifo_component.lpm_width = FIFO_SIZE, 104 | dcfifo_component.lpm_widthu = 2, 105 | dcfifo_component.overflow_checking = "OFF", 106 | dcfifo_component.rdsync_delaypipe = 5, 107 | dcfifo_component.underflow_checking = "OFF", 108 | dcfifo_component.use_eab = "OFF", 109 | dcfifo_component.wrsync_delaypipe = 5; 110 | 111 | /// APF to Mem clock 112 | reg prev_bridge_wr = 0; 113 | reg [2:0] write_count = 0; 114 | reg [2:0] write_state = 0; 115 | 116 | localparam WRITE_START = 1; 117 | localparam WRITE_REQ_SHIFT = 2; 118 | 119 | // Receive APF writes and buffer them into the memory clock domain 120 | always @(posedge clk_74a) begin 121 | prev_bridge_wr <= bridge_wr; 122 | 123 | if (~prev_bridge_wr && bridge_wr && bridge_addr[31:28] == ADDRESS_MASK_UPPER_4) begin 124 | // Beginning APF write to core 125 | write_state <= WRITE_REQ_SHIFT; 126 | write_req <= 1; 127 | write_count <= 0; 128 | 129 | shift_data <= bridge_endian_little ? bridge_wr_data : { 130 | bridge_wr_data[7:0], bridge_wr_data[15:8], bridge_wr_data[23:16], bridge_wr_data[31:24] 131 | }; 132 | 133 | buff_bridge_addr <= bridge_addr[27:0]; 134 | end 135 | 136 | case (write_state) 137 | WRITE_START: begin 138 | write_req <= 1; 139 | 140 | write_state <= WRITE_REQ_SHIFT; 141 | end 142 | WRITE_REQ_SHIFT: begin 143 | write_req <= 0; 144 | 145 | // We will be writing again in the next cycle 146 | shift_data <= {8'h0, shift_data[31:WORD_SIZE]}; 147 | buff_bridge_addr <= buff_bridge_addr + OUTPUT_WORD_SIZE; 148 | 149 | write_count <= write_count + 1; 150 | 151 | if (write_count == (4 / OUTPUT_WORD_SIZE) - 1) begin 152 | // Finished write 153 | write_state <= 0; 154 | end 155 | else begin 156 | write_state <= WRITE_START; 157 | end 158 | end 159 | endcase 160 | end 161 | 162 | /// Mem clock to core 163 | 164 | reg [5:0] read_state = 0; 165 | 166 | localparam READ_DELAY = 1; 167 | localparam READ_WRITE = 2; 168 | localparam READ_WRITE_EN_CYCLE_OFF = READ_WRITE + WRITE_MEM_EN_CYCLE_LENGTH; 169 | localparam READ_WRITE_END_DEFAULT = WRITE_MEM_CLOCK_DELAY - 1; 170 | // Must use max to prevent READ_WRITE_END from being the same as READ_WRITE_EN_CYCLE_OFF 171 | localparam READ_WRITE_END = `MAX(READ_WRITE_END_DEFAULT, READ_WRITE_EN_CYCLE_OFF + 1); 172 | localparam HAS_DELAY = READ_WRITE_END_DEFAULT > READ_WRITE_EN_CYCLE_OFF; 173 | 174 | always @(posedge clk_memory) begin 175 | if (read_state != 0) begin 176 | read_state <= read_state + 1; 177 | end 178 | else if (~mem_empty) begin 179 | // Start read 180 | read_state <= READ_DELAY; 181 | read_req <= 1; 182 | end 183 | 184 | case (read_state) 185 | READ_DELAY: begin 186 | read_req <= 0; 187 | write_en <= 0; 188 | end 189 | READ_WRITE: begin 190 | // Read data is available 191 | write_en <= 1; 192 | // Lowest 28 bits are the address 193 | write_addr <= fifo_out[27:0]; 194 | write_data <= fifo_out[WORD_SIZE+27:28]; 195 | read_req <= 0; 196 | end 197 | READ_WRITE_EN_CYCLE_OFF: begin 198 | write_en <= 0; 199 | if (!HAS_DELAY) begin 200 | // No extra delay, immediately go back to start 201 | read_state <= 0; 202 | end 203 | end 204 | READ_WRITE_END: begin 205 | read_state <= 0; 206 | end 207 | endcase 208 | end 209 | 210 | initial begin 211 | // Verify parameters 212 | if (WRITE_MEM_CLOCK_DELAY < 4) begin 213 | $error("WRITE_MEM_CLOCK_DELAY has a minimum value of 4. Received %d", WRITE_MEM_CLOCK_DELAY); 214 | end 215 | if (WRITE_MEM_EN_CYCLE_LENGTH < 1 || WRITE_MEM_EN_CYCLE_LENGTH >= WRITE_MEM_CLOCK_DELAY - 2) begin 216 | $error("WRITE_MEM_EN_CYCLE_LENGTH must be between 1 and %d (inclusive, based off of WRITE_MEM_CLOCK_DELAY). Received %d", WRITE_MEM_CLOCK_DELAY - 2 - 1, WRITE_MEM_EN_CYCLE_LENGTH); 217 | end 218 | if (OUTPUT_WORD_SIZE < 1 || OUTPUT_WORD_SIZE > 2) begin 219 | $error("OUTPUT_WORD_SIZE must be 1 or 2. Received %d", OUTPUT_WORD_SIZE); 220 | end 221 | end 222 | 223 | endmodule 224 | -------------------------------------------------------------------------------- /modules/pocket-dataloader/data_unloader.sv: -------------------------------------------------------------------------------- 1 | // MIT License 2 | 3 | // Copyright (c) 2022 Adam Gastineau 4 | 5 | // Permission is hereby granted, free of charge, to any person obtaining a copy 6 | // of this software and associated documentation files (the "Software"), to deal 7 | // in the Software without restriction, including without limitation the rights 8 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | // copies of the Software, and to permit persons to whom the Software is 10 | // furnished to do so, subject to the following conditions: 11 | 12 | // The above copyright notice and this permission notice shall be included in all 13 | // copies or substantial portions of the Software. 14 | 15 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | // SOFTWARE. 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | // A data unloader for consuming APF bridge reads, reading from some underlying memory, and supplying that data to APF 26 | // 27 | // This consumes four / OUTPUT_WORD_SIZE words (4 separate bytes, or 2 16-bit words) and sends APF 32 bit words. 28 | // You can configure the cycle delay by setting READ_MEM_CLOCK_DELAY 29 | module data_unloader #( 30 | // Upper 4 bits of address 31 | parameter ADDRESS_MASK_UPPER_4 = 0, 32 | parameter ADDRESS_SIZE = 28, 33 | 34 | // Number of memory clock cycles it takes for a read to complete 35 | parameter READ_MEM_CLOCK_DELAY = 1, 36 | 37 | // Word size in number of bytes. Can either be 1 (input 8 bits), or 2 (input 16 bits) 38 | parameter INPUT_WORD_SIZE = 1 39 | ) ( 40 | input wire clk_74a, 41 | input wire clk_memory, 42 | 43 | input wire bridge_rd, 44 | input wire bridge_endian_little, 45 | input wire [31:0] bridge_addr, 46 | output reg [31:0] bridge_rd_data = 0, 47 | 48 | // These outputs are synced to the memory clock 49 | output reg read_en = 0, 50 | output reg [ADDRESS_SIZE-1:0] read_addr = 0, 51 | input wire [8 * INPUT_WORD_SIZE - 1:0] read_data 52 | ); 53 | 54 | localparam WORD_SIZE = 8 * INPUT_WORD_SIZE; 55 | 56 | // APF address to memory FIFO 57 | reg [27:0] fifo_address_in = 0; 58 | reg address_read_req = 0; 59 | reg address_write_req = 0; 60 | wire address_empty; 61 | 62 | wire [27:0] fifo_address_out; 63 | 64 | dcfifo fifo_address_req ( 65 | .data(fifo_address_in), 66 | .rdclk(clk_memory), 67 | .rdreq(address_read_req), 68 | .wrclk(clk_74a), 69 | .wrreq(address_write_req), 70 | .q(fifo_address_out), 71 | .rdempty(address_empty) 72 | // .wrempty(), 73 | // .aclr(), 74 | // .eccstatus(), 75 | // .rdfull(), 76 | // .rdusedw(), 77 | // .wrfull(), 78 | // .wrusedw() 79 | ); 80 | defparam fifo_address_req.clocks_are_synchronized = "FALSE", 81 | fifo_address_req.intended_device_family = "Cyclone V", fifo_address_req.lpm_numwords = 4, 82 | fifo_address_req.lpm_showahead = "OFF", fifo_address_req.lpm_type = "dcfifo", 83 | fifo_address_req.lpm_width = 28, fifo_address_req.lpm_widthu = 2, 84 | fifo_address_req.overflow_checking = "OFF", fifo_address_req.rdsync_delaypipe = 5, 85 | fifo_address_req.underflow_checking = "OFF", fifo_address_req.use_eab = "OFF", 86 | fifo_address_req.wrsync_delaypipe = 5; 87 | 88 | // Memory output to APF FIFO 89 | reg data_read_req = 0; 90 | reg data_write_req = 0; 91 | wire data_empty; 92 | 93 | reg [WORD_SIZE - 1:0] fifo_data_in = 0; 94 | wire [WORD_SIZE - 1:0] fifo_data_out; 95 | 96 | dcfifo fifo_data_response ( 97 | .data(fifo_data_in), 98 | .rdclk(clk_74a), 99 | .rdreq(data_read_req), 100 | .wrclk(clk_memory), 101 | .wrreq(data_write_req), 102 | .q(fifo_data_out), 103 | .rdempty(data_empty) 104 | // .wrempty(), 105 | // .aclr(), 106 | // .eccstatus(), 107 | // .rdfull(), 108 | // .rdusedw(), 109 | // .wrfull(), 110 | // .wrusedw() 111 | ); 112 | defparam fifo_data_response.clocks_are_synchronized = "FALSE", 113 | fifo_data_response.intended_device_family = "Cyclone V", fifo_data_response.lpm_numwords = 4, 114 | fifo_data_response.lpm_showahead = "OFF", fifo_data_response.lpm_type = "dcfifo", 115 | fifo_data_response.lpm_width = WORD_SIZE, fifo_data_response.lpm_widthu = 2, 116 | fifo_data_response.overflow_checking = "OFF", fifo_data_response.rdsync_delaypipe = 5, 117 | fifo_data_response.underflow_checking = "OFF", fifo_data_response.use_eab = "OFF", 118 | fifo_data_response.wrsync_delaypipe = 5; 119 | 120 | /// APF side 121 | 122 | reg prev_bridge_rd = 0; 123 | reg [2:0] addr_count = 0; 124 | reg [2:0] addr_state = 0; 125 | 126 | localparam ADDR_START = 1; 127 | localparam ADDR_REQ = 2; 128 | 129 | // Receive APF read addresses and buffer them into the memory clock domain 130 | always @(posedge clk_74a) begin 131 | prev_bridge_rd <= bridge_rd; 132 | 133 | if (~prev_bridge_rd && bridge_rd && bridge_addr[31:28] == ADDRESS_MASK_UPPER_4) begin 134 | // Beginning APF read from core 135 | addr_state <= ADDR_REQ; 136 | address_write_req <= 1; 137 | addr_count <= 0; 138 | fifo_address_in <= bridge_addr[27:0]; 139 | end 140 | 141 | case (addr_state) 142 | ADDR_START: begin 143 | address_write_req <= 1; 144 | addr_state <= ADDR_REQ; 145 | end 146 | ADDR_REQ: begin 147 | address_write_req <= 0; 148 | fifo_address_in <= fifo_address_in + INPUT_WORD_SIZE; 149 | addr_count <= addr_count + 1; 150 | if (addr_count == (4 / INPUT_WORD_SIZE) - 1) begin 151 | // Finished write 152 | addr_count <= 0; 153 | addr_state <= 0; 154 | end 155 | else begin 156 | addr_state <= ADDR_START; 157 | end 158 | end 159 | endcase 160 | end 161 | 162 | reg [2:0] data_send_state = 0; 163 | reg [2:0] apf_data_count = 0; 164 | reg [31:0] apf_bridge_write_data = 0; 165 | 166 | wire [31:0] apf_final_data = {fifo_data_out, apf_bridge_write_data[31-WORD_SIZE:0]}; 167 | 168 | localparam READ_DATA_DELAY = 1; 169 | localparam READ_DATA_WRITE = 2; 170 | 171 | // Receive data from memory and write to APF bridge 172 | always @(posedge clk_74a) begin 173 | if (data_send_state != 0) begin 174 | data_send_state <= data_send_state + 1; 175 | end 176 | else if (~data_empty) begin 177 | // Start data read 178 | data_send_state <= READ_DATA_DELAY; 179 | data_read_req <= 1; 180 | 181 | apf_data_count <= 0; 182 | end 183 | 184 | case (data_send_state) 185 | READ_DATA_DELAY: begin 186 | data_read_req <= 0; 187 | 188 | // Shift current APF data 189 | apf_bridge_write_data <= apf_bridge_write_data >> WORD_SIZE; 190 | end 191 | READ_DATA_WRITE: begin 192 | // Data from memory is available 193 | if (apf_data_count == (4 / INPUT_WORD_SIZE) - 1) begin 194 | // We have all of the data we need, send to APF 195 | bridge_rd_data <= bridge_endian_little ? apf_final_data : { 196 | apf_final_data[7:0], apf_final_data[15:8], apf_final_data[23:16], apf_final_data[31:24] 197 | }; 198 | 199 | data_send_state <= 0; 200 | end 201 | else begin 202 | apf_bridge_write_data <= apf_final_data; 203 | 204 | data_read_req <= 1; 205 | data_send_state <= READ_DATA_DELAY; 206 | 207 | apf_data_count <= apf_data_count + 1; 208 | end 209 | end 210 | endcase 211 | end 212 | 213 | /// Mem side 214 | 215 | reg [5:0] data_read_state = 0; 216 | 217 | localparam READ_ADDRESS_DELAY = 1; 218 | localparam READ_MEM_START = 2; 219 | localparam READ_MEM_COMPLETE = READ_MEM_START + READ_MEM_CLOCK_DELAY; 220 | localparam READ_ADDRESS_END = READ_MEM_COMPLETE + 1; 221 | 222 | always @(posedge clk_memory) begin 223 | if (data_read_state != 0) begin 224 | data_read_state <= data_read_state + 1; 225 | end 226 | else if (~address_empty) begin 227 | // Start address read 228 | data_read_state <= READ_ADDRESS_DELAY; 229 | address_read_req <= 1; 230 | end 231 | 232 | case (data_read_state) 233 | READ_ADDRESS_DELAY: begin 234 | address_read_req <= 0; 235 | end 236 | READ_MEM_START: begin 237 | // Address read data is available 238 | read_en <= 1; 239 | 240 | read_addr <= fifo_address_out[ADDRESS_SIZE-1:0]; 241 | end 242 | READ_MEM_COMPLETE: begin 243 | // We have data to send to APF 244 | read_en <= 0; 245 | 246 | data_write_req <= 1; 247 | fifo_data_in <= read_data; 248 | end 249 | READ_ADDRESS_END: begin 250 | data_write_req <= 0; 251 | 252 | data_read_state <= 0; 253 | end 254 | endcase 255 | end 256 | 257 | endmodule 258 | -------------------------------------------------------------------------------- /modules/pocket-dataloader/index.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "data_loader.sv"] 2 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "data_unloader.sv"] 3 | -------------------------------------------------------------------------------- /modules/pocket-i2s/index.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "pocket_i2s.sv"] 2 | -------------------------------------------------------------------------------- /modules/pocket-i2s/pocket_i2s.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // SPDX-License-Identifier: MIT 3 | // SPDX-FileType: SOURCE 4 | // SPDX-FileCopyrightText: (c) 2022 Adam Gastineau 5 | //------------------------------------------------------------------------------ 6 | // Permission is hereby granted, free of charge, to any person obtaining a copy 7 | // of this software and associated documentation files (the "Software"), to deal 8 | // in the Software without restriction, including without limitation the rights 9 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | // copies of the Software, and to permit persons to whom the Software is 11 | // furnished to do so, subject to the following conditions: 12 | // 13 | // The above copyright notice and this permission notice shall be included in 14 | // all copies or substantial portions of the Software. 15 | // 16 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | // SOFTWARE. 23 | //------------------------------------------------------------------------------ 24 | // A very simple audio i2s bridge to APF, based on their example code 25 | //------------------------------------------------------------------------------ 26 | 27 | module sound_i2s #( 28 | parameter CHANNEL_WIDTH = 15, 29 | parameter SIGNED_INPUT = 0 30 | ) ( 31 | input wire clk_74a, 32 | input wire clk_audio, 33 | 34 | // Left and Right channels. Can be in an arbitrary clock domain 35 | input wire [CHANNEL_WIDTH - 1:0] audio_l, 36 | input wire [CHANNEL_WIDTH - 1:0] audio_r, 37 | 38 | output reg audio_mclk, 39 | output reg audio_lrck, 40 | output reg audio_dac 41 | ); 42 | 43 | // 44 | // audio i2s generator 45 | // 46 | reg audgen_nextsamp; 47 | 48 | // generate MCLK = 12.288mhz with fractional accumulator 49 | reg [21:0] audgen_accum = 0; 50 | parameter [20:0] CYCLE_48KHZ = 21'd122880 * 2; 51 | 52 | always @(posedge clk_74a) begin 53 | audgen_accum <= audgen_accum + CYCLE_48KHZ; 54 | if (audgen_accum >= 21'd742500) begin 55 | audio_mclk <= ~audio_mclk; 56 | audgen_accum <= audgen_accum - 21'd742500 + CYCLE_48KHZ; 57 | end 58 | end 59 | 60 | // generate SCLK = 3.072mhz by dividing MCLK by 4 61 | reg [1:0] aud_mclk_divider; 62 | reg prev_audio_mclk; 63 | wire audgen_sclk = aud_mclk_divider[1] /* synthesis keep */; 64 | 65 | always @(posedge clk_74a) begin 66 | if (audio_mclk && ~prev_audio_mclk) begin 67 | aud_mclk_divider <= aud_mclk_divider + 1'b1; 68 | end 69 | 70 | prev_audio_mclk <= audio_mclk; 71 | end 72 | 73 | // Shift out audio data as I2S 74 | // 32 total bits per channel, but only 16 active bits at the start and then 16 dummy bits 75 | // 76 | // Synchronize audio samples coming from the core 77 | localparam CHANNEL_LEFT_HIGH = SIGNED_INPUT ? 16 : 15; 78 | localparam CHANNEL_RIGHT_HIGH = 16 + CHANNEL_LEFT_HIGH; 79 | 80 | // Width of channel with signed component 81 | localparam SIGNED_CHANNEL_WIDTH = SIGNED_INPUT ? CHANNEL_WIDTH : CHANNEL_WIDTH + 1; 82 | 83 | wire [31:0] audgen_sampdata; 84 | 85 | assign audgen_sampdata[CHANNEL_LEFT_HIGH-1:CHANNEL_LEFT_HIGH-CHANNEL_WIDTH] = audio_l; 86 | assign audgen_sampdata[CHANNEL_RIGHT_HIGH-1:CHANNEL_RIGHT_HIGH-CHANNEL_WIDTH] = audio_r; 87 | 88 | generate 89 | if (!SIGNED_INPUT) begin 90 | // If not signed, make sure high bit is 0 91 | assign audgen_sampdata[31] = 0; 92 | assign audgen_sampdata[15] = 0; 93 | end 94 | endgenerate 95 | 96 | generate 97 | if (15 - SIGNED_CHANNEL_WIDTH > 0) begin 98 | assign audgen_sampdata[31-SIGNED_CHANNEL_WIDTH:16] = 0; 99 | assign audgen_sampdata[15-SIGNED_CHANNEL_WIDTH:0] = 0; 100 | end 101 | endgenerate 102 | 103 | sync_fifo #(.WIDTH(32)) 104 | sync_fifo ( 105 | .clk_write(clk_audio), 106 | .clk_read (clk_74a), 107 | 108 | .write_en(write_en), 109 | .data_in (audgen_sampdata), 110 | .data_out(audgen_sampdata_s) 111 | ); 112 | 113 | reg write_en = 0; 114 | reg [CHANNEL_WIDTH - 1:0] prev_left; 115 | reg [CHANNEL_WIDTH - 1:0] prev_right; 116 | // Mark write when necessary 117 | always @(posedge clk_audio) begin 118 | prev_left <= audio_l; 119 | prev_right <= audio_r; 120 | 121 | write_en <= 0; 122 | 123 | if (audio_l != prev_left || audio_r != prev_right) begin 124 | write_en <= 1; 125 | end 126 | end 127 | 128 | wire [31:0] audgen_sampdata_s; 129 | reg [31:0] audgen_sampshift; 130 | reg [4:0] audio_lrck_cnt; 131 | reg prev_audgen_sclk; 132 | always @(posedge clk_74a) begin 133 | if (prev_audgen_sclk && ~audgen_sclk) begin 134 | audio_dac <= audgen_sampshift[31]; // Output the next bit 135 | audio_lrck_cnt <= audio_lrck_cnt + 1'b1; // 48khz * 64 136 | if (audio_lrck_cnt == 31) begin 137 | audio_lrck <= ~audio_lrck; // Switch channels 138 | if (~audio_lrck) begin 139 | audgen_sampshift <= audgen_sampdata_s; // Reload sample shifter 140 | end 141 | end 142 | else if (audio_lrck_cnt < 16) begin 143 | audgen_sampshift <= {audgen_sampshift[30:0], 1'b0}; // Only shift for 16 clocks per channel 144 | end 145 | end 146 | 147 | prev_audgen_sclk <= audgen_sclk; 148 | end 149 | 150 | // Verify parameters 151 | initial begin 152 | if (CHANNEL_WIDTH > 16) begin 153 | $error("CHANNEL_WIDTH must be <= 16. Received %d", CHANNEL_WIDTH); 154 | end 155 | 156 | if (SIGNED_INPUT != 0 && SIGNED_INPUT != 1) begin 157 | $error("SIGNED_INPUT must be 0 or 1. Received %d", SIGNED_INPUT); 158 | end 159 | 160 | if (CHANNEL_WIDTH == 16 && SIGNED_INPUT == 0) begin 161 | $error("Cannot have CHANNEL_WIDTH of 16 and an unsigned input"); 162 | end 163 | end 164 | 165 | endmodule 166 | -------------------------------------------------------------------------------- /modules/pocket-joypad/index.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "joypad.v"] 2 | -------------------------------------------------------------------------------- /modules/pocket-joypad/joypad.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // SPDX-License-Identifier: MPL-2.0 3 | // SPDX-FileType: SOURCE 4 | // SPDX-FileCopyrightText: (c) 2022 Marcus Andrade 5 | //------------------------------------------------------------------------------ 6 | // 7 | // This Source Code Form is subject to the terms of the Mozilla Public 8 | // License, v. 2.0. If a copy of the MPL was not distributed with this file, 9 | // You can obtain one at https://mozilla.org/MPL/2.0/. 10 | // 11 | //------------------------------------------------------------------------------ 12 | // Generic Gamepad interface for the Analogue Pocket 13 | //------------------------------------------------------------------------------ 14 | 15 | module pocket_gamepad 16 | ( 17 | input wire iCLK, //! Clock to Sync To (eg: clk_sys) 18 | input wire [31:0] iJOY, //! Pocket Joystick Interface 19 | 20 | output wire PAD_U, PAD_D, PAD_L, PAD_R, //! D-PAD 21 | output wire BTN_A, BTN_B, BTN_X, BTN_Y, //! Face Buttons 22 | output wire BTN_L1, BTN_R1, BTN_L2, BTN_R2, BTN_L3, BTN_R3, //! Shoulder/Trigger Buttons 23 | output wire BTN_SE, BTN_ST //! Select and Start Buttons 24 | ); 25 | 26 | // D-PAD 27 | assign PAD_U = rJOY_KEY[0]; assign PAD_D = rJOY_KEY[1]; 28 | assign PAD_L = rJOY_KEY[2]; assign PAD_R = rJOY_KEY[3]; 29 | 30 | // Face Buttons 31 | assign BTN_B = rJOY_KEY[5]; assign BTN_A = rJOY_KEY[4]; 32 | assign BTN_Y = rJOY_KEY[7]; assign BTN_X = rJOY_KEY[6]; 33 | 34 | // Shoulder/Trigger Buttons 35 | assign BTN_L1 = rJOY_KEY[8]; assign BTN_R1 = rJOY_KEY[9]; 36 | assign BTN_L2 = rJOY_KEY[10]; assign BTN_R2 = rJOY_KEY[11]; 37 | assign BTN_L3 = rJOY_KEY[12]; assign BTN_R3 = rJOY_KEY[13]; 38 | 39 | // Select and Start Buttons 40 | assign BTN_SE = rJOY_KEY[14]; assign BTN_ST = rJOY_KEY[15]; 41 | 42 | reg [31:0] rJOY_KEY; //! Synced Joystick Register 43 | reg [31:0] S1, S2; //! Register for 2 Stages Sync 44 | 45 | always @(posedge iCLK) begin 46 | {rJOY_KEY, S2, S1} <= {S2, S1, iJOY}; 47 | end 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /modules/pocket-video/index.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "pocket_video.sv"] 2 | -------------------------------------------------------------------------------- /modules/pocket-video/pocket_video.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // SPDX-License-Identifier: MPL-2.0 3 | // SPDX-FileType: SOURCE 4 | // SPDX-FileCopyrightText: (c) 2022 Marcus Andrade 5 | //------------------------------------------------------------------------------ 6 | // 7 | // This Source Code Form is subject to the terms of the Mozilla Public 8 | // License, v. 2.0. If a copy of the MPL was not distributed with this file, 9 | // You can obtain one at https://mozilla.org/MPL/2.0/. 10 | // 11 | //------------------------------------------------------------------------------ 12 | // Generic Video Interface for the Analogue Pocket Display 13 | // 14 | // Note: APF scaler requires HSync and VSync to last for a single clock, and 15 | // video_rgb to be 0 when video_de is low 16 | //------------------------------------------------------------------------------ 17 | 18 | module pocket_video 19 | ( 20 | input iPCLK, //! Display Pixel Clock 21 | input iPCLK_90D, //! Display Pixel Clock 90º Phase Shift 22 | input [2:0] iPRESET, //! Video preset scaling configurations (up to 8) 23 | 24 | input [23:0] iRGB, //! Core: RGB Video 25 | input iVS, //! Core: Vsync 26 | input iHS, //! Core: Hsync 27 | input iDE, //! Core: Data Enable 28 | 29 | output reg [23:0] oRGB, //! Pixel color: Red[23:16] Green[15:8] Blue[7:0] 30 | output reg oVS, //! Frame Vsync Active high 31 | output reg oHS, //! Frame Hsync Active high 32 | output reg oDE, //! Data enable Active high 33 | 34 | output wire oPCLK, //! Display Pixel Clock 35 | output wire oPCLK_90D //! Display Pixel Clock 90º Phase Shift 36 | ); 37 | 38 | assign oPCLK = iPCLK; 39 | assign oPCLK_90D = iPCLK_90D; 40 | 41 | reg [23:0] rRGB; 42 | reg rHS; 43 | reg rVS; 44 | reg rDE; 45 | 46 | always @(posedge iPCLK) begin 47 | oDE <= 0; 48 | oRGB <= {8'b0, iPRESET, 13'b0}; 49 | if (rDE) begin 50 | oDE <= 1; 51 | oRGB <= rRGB; 52 | end 53 | // Set HSync and VSync to be high for a single cycle on the rising edge of the HSync and VSync coming out of the core 54 | oHS <= ~rHS && iHS; 55 | oVS <= ~rVS && iVS; 56 | rVS <= iVS; 57 | rHS <= iHS; 58 | rDE <= iDE; 59 | rRGB <= iRGB; 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /modules/video-scanlines/index.qip: -------------------------------------------------------------------------------- 1 | # ============================================================================== 2 | # Quartus Prime QIP Index File 3 | # ============================================================================== 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "scanlines.v"] 5 | -------------------------------------------------------------------------------- /modules/video-scanlines/scanlines.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // SPDX-License-Identifier: GPL-3.0-or-later 3 | // SPDX-FileType: SOURCE 4 | // SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors 5 | //------------------------------------------------------------------------------ 6 | // 7 | // Copyright (c) 2022 OpenGateware authors and contributors 8 | // Copyright (c) 2017 Alexey Melnikov 9 | // Copyright (c) 2015 Till Harbaum 10 | // 11 | // This program is free software: you can redistribute it and/or modify 12 | // it under the terms of the GNU General Public License as published by 13 | // the Free Software Foundation, version 3. 14 | // 15 | // This program is distributed in the hope that it will be useful, but 16 | // WITHOUT ANY WARRANTY; without even the implied warranty of 17 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 | // General Public License for more details. 19 | // 20 | // You should have received a copy of the GNU General Public License 21 | // along with this program. If not, see . 22 | // 23 | //------------------------------------------------------------------------------ 24 | // Generic Video Scanlines 25 | //------------------------------------------------------------------------------ 26 | 27 | module scanlines #( 28 | parameter v2 = 0 //! Enable Scanlines V2 29 | ) ( 30 | input iPCLK, //! Pixel Clock 31 | 32 | input [1:0] iSCANLINES, //! Scanlines (00-None / 01-25% / 10-50% / 11-75%) 33 | input [23:0] iRGB, //! Core: RGB Video 34 | input iHS, //! Core: Vsync 35 | input iVS, //! Core: Hsync 36 | input iDE, //! Core: Data Enable 37 | input iCE, //! Core: Clock Enable 38 | 39 | output reg [23:0] oRGB, //! Video Ouput: RGB Video 40 | output reg oHS, //! Video Ouput: Vsync 41 | output reg oVS, //! Video Ouput: Hsync 42 | output reg oDE, //! Video Ouput: Data Enable 43 | output reg oCE //! Video Ouput: Clock Enable 44 | ); 45 | 46 | reg [1:0] rSCANLINE; //! Scanline Register 47 | always @(posedge iPCLK) begin 48 | reg rOLD_HS, rOLD_VS; 49 | 50 | rOLD_HS <= iHS; rOLD_VS <= iVS; 51 | 52 | if(rOLD_HS && ~iHS) begin 53 | if(v2) begin 54 | rSCANLINE <= rSCANLINE + 1'd1; 55 | if (rSCANLINE == iSCANLINES) 56 | rSCANLINE <= 0; 57 | end 58 | else 59 | rSCANLINE <= rSCANLINE ^ iSCANLINES; 60 | end 61 | if(rOLD_VS && ~iVS) rSCANLINE <= 0; 62 | end 63 | 64 | wire [7:0] r,g,b; //! RGB Signals 65 | assign {r,g,b} = iRGB; 66 | 67 | reg [23:0] rgb_d; //! RGB Data 68 | always @(*) begin 69 | case(rSCANLINE) 70 | 1: //! 25% = 1/2 + 1/4 71 | rgb_d = { 72 | {1'b0, r[7:1]} + {2'b0, r[7:2]}, 73 | {1'b0, g[7:1]} + {2'b0, g[7:2]}, 74 | {1'b0, b[7:1]} + {2'b0, b[7:2]} 75 | }; 76 | 2: //! 50% = 1/2 77 | rgb_d = { 78 | {1'b0, r[7:1]}, 79 | {1'b0, g[7:1]}, 80 | {1'b0, b[7:1]} 81 | }; 82 | 3: //! 75% = 1/4 83 | rgb_d = { 84 | {2'b0, r[7:2]}, 85 | {2'b0, g[7:2]}, 86 | {2'b0, b[7:2]} 87 | }; 88 | default: 89 | rgb_d = {r, g, b}; 90 | endcase 91 | end 92 | 93 | always @(posedge iPCLK) begin 94 | reg [23:0] rgb1, rgb2; 95 | reg de1, de2; 96 | reg vs1, vs2; 97 | reg hs1, hs2; 98 | reg ce1, ce2; 99 | 100 | oRGB <= rgb2; rgb2 <= rgb1; rgb1 <= rgb_d; 101 | oVS <= vs2; vs2 <= vs1; vs1 <= iVS; 102 | oHS <= hs2; hs2 <= hs1; hs1 <= iHS; 103 | oDE <= de2; de2 <= de1; de1 <= iDE; 104 | oCE <= ce2; ce2 <= ce1; ce1 <= iCE; 105 | end 106 | 107 | endmodule 108 | -------------------------------------------------------------------------------- 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"description": "Watara Supervision Compatible Gateware IP Core", 10 | "author": "boogermann", 11 | "url": "https://github.com/opengateware/console-supervision", 12 | "version": "<%- VERSION %>", 13 | "date_release": "<%- RELEASE_DATE %>" 14 | }, 15 | "framework": { 16 | "target_product": "Analogue Pocket", 17 | "version_required": "1.1", 18 | "sleep_supported": false, 19 | "dock": { 20 | "supported": true, 21 | "analog_output": false 22 | }, 23 | "hardware": { 24 | "link_port": false, 25 | "cartridge_adapter": -1 26 | } 27 | }, 28 | "cores": [ 29 | { 30 | "name": "default", 31 | "id": 0, 32 | "filename": "bitstream.rbf_r" 33 | } 34 | ] 35 | } 36 | } -------------------------------------------------------------------------------- /pkg/pocket/Cores/boogermann.supervision/data.json: -------------------------------------------------------------------------------- 1 | { 2 | "data": { 3 | "magic": "APF_VER_1", 4 | "data_slots": [ 5 | { 6 | "id": 0, 7 | "name": "Cartridge", 8 | "required": true, 9 | "parameters": "0x109", 10 | "extensions": [ 11 | "sv", 12 | "bin" 13 | ], 14 | "address": "0x00000000" 15 | } 16 | ] 17 | } 18 | } -------------------------------------------------------------------------------- /pkg/pocket/Cores/boogermann.supervision/icon.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/opengateware/console-supervision/7c01e71e028de81171f74f835812dfc1e109cefe/pkg/pocket/Cores/boogermann.supervision/icon.bin -------------------------------------------------------------------------------- /pkg/pocket/Cores/boogermann.supervision/icon.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/opengateware/console-supervision/7c01e71e028de81171f74f835812dfc1e109cefe/pkg/pocket/Cores/boogermann.supervision/icon.png -------------------------------------------------------------------------------- /pkg/pocket/Cores/boogermann.supervision/info.txt: -------------------------------------------------------------------------------- 1 | Supervision © 1992 Watara. 2 | 3 | The Watara Supervision, also known as the QuickShot Supervision in the UK, is a monochrome handheld game console, originating from Asia, and introduced in 1992 as a cut-price competitor for Nintendo's Game Boy. 4 | It came packaged with a game called Crystball, which is similar to Breakout. 5 | One unique feature of the Supervision was that it could be linked up to a television via a link cable. 6 | Games played in this way would display in four colors, much like Nintendo's Super Game Boy add-on for the SNES. 7 | A full color TV link was also in the works, but because of the Supervision's failure to make a major impression among gamers it was cancelled, along with the games which were in development for it. 8 | 9 | This Implementation of a compatible Watara Supervision hardware in HDL is the work of Pierre Cornier and Jamie Blanks. 10 | 11 | Analogue Pocket port by Marcus Andrade (Boogermann) 12 | 13 | All trademarks, logos, and copyrights are property of their respective owners. 14 | 15 | The authors and contributors or any of its maintainers are in no way associated with or endorsed by Watara. 16 | -------------------------------------------------------------------------------- /pkg/pocket/Cores/boogermann.supervision/input.json: -------------------------------------------------------------------------------- 1 | { 2 | "input": { 3 | "magic": "APF_VER_1", 4 | "controllers": [ 5 | { 6 | "type": "default", 7 | "mappings": [ 8 | { 9 | "id": 0, 10 | "name": "A Button", 11 | "key": "pad_btn_a" 12 | }, 13 | { 14 | "id": 1, 15 | "name": "B Button", 16 | "key": "pad_btn_b" 17 | }, 18 | { 19 | "id": 20, 20 | "name": "Start", 21 | "key": "pad_btn_start" 22 | }, 23 | { 24 | "id": 21, 25 | "name": "Select", 26 | "key": "pad_btn_select" 27 | } 28 | ] 29 | } 30 | ] 31 | } 32 | } -------------------------------------------------------------------------------- /pkg/pocket/Cores/boogermann.supervision/interact.json: -------------------------------------------------------------------------------- 1 | { 2 | "interact": { 3 | "magic": "APF_VER_1", 4 | "variables": [ 5 | { 6 | "name": "Reset Core", 7 | "id": 1, 8 | "type": "action", 9 | "enabled": true, 10 | "address": "0xF0000000", 11 | "value": 1 12 | }, 13 | { 14 | "name": "Flickerblend", 15 | "id": 2, 16 | "type": "check", 17 | "enabled": true, 18 | "persist": true, 19 | "address": "0xF1000000", 20 | "mask": "0xFFFFFFF0", 21 | "value": "0x000F" 22 | }, 23 | { 24 | "name": "60Hz Mode", 25 | "id": 3, 26 | "type": "check", 27 | "enabled": true, 28 | "persist": true, 29 | "address": "0xF1000000", 30 | "mask": "0xFFFFFF0F", 31 | "value": "0x00F0" 32 | }, 33 | { 34 | "name": "Custom Palette", 35 | "id": 4, 36 | "type": "check", 37 | "enabled": true, 38 | "persist": true, 39 | "address": "0xF1000000", 40 | "mask": "0xFFFFF0FF", 41 | "value": "0x0F00" 42 | }, 43 | { 44 | "name": "Palettes", 45 | "id": 5, 46 | "type": "list", 47 | "enabled": true, 48 | "persist": true, 49 | "address": "0xF2000000", 50 | "defaultval": 0, 51 | "mask": "0xFFFFFFF0", 52 | "options": [ 53 | { 54 | "name": "Andrade", 55 | "value": 0 56 | }, 57 | { 58 | "name": "Biverted", 59 | "value": 1 60 | }, 61 | { 62 | "name": "DMG", 63 | "value": 2 64 | }, 65 | { 66 | "name": "SGB Default", 67 | "value": 3 68 | }, 69 | { 70 | "name": "Blueberry Crush", 71 | "value": 4 72 | }, 73 | { 74 | "name": "DMG Bright", 75 | "value": 5 76 | }, 77 | { 78 | "name": "DMG Clean", 79 | "value": 6 80 | }, 81 | { 82 | "name": "DMG Weak", 83 | "value": 7 84 | }, 85 | { 86 | "name": "GBP Bright", 87 | "value": 8 88 | }, 89 | { 90 | "name": "GBP Clean", 91 | "value": 9 92 | }, 93 | { 94 | "name": "GBP Weak", 95 | "value": 10 96 | }, 97 | { 98 | "name": "Grape Crush", 99 | "value": 11 100 | }, 101 | { 102 | "name": "Orange Crush", 103 | "value": 12 104 | }, 105 | { 106 | "name": "Paisley Park", 107 | "value": 13 108 | }, 109 | { 110 | "name": "Quicksilver", 111 | "value": 14 112 | }, 113 | { 114 | "name": "Strawberry Crush", 115 | "value": 15 116 | } 117 | ] 118 | }, 119 | { 120 | "name": "Scanlines", 121 | "id": 100, 122 | "type": "list", 123 | "enabled": true, 124 | "persist": true, 125 | "address": "0xF3000000", 126 | "defaultval": 0, 127 | "options": [ 128 | { 129 | "name": "Disabled", 130 | "value": 0 131 | }, 132 | { 133 | "name": "Soft (25%)", 134 | "value": 1 135 | }, 136 | { 137 | "name": "Medium (50%)", 138 | "value": 2 139 | }, 140 | { 141 | "name": "Hard (75%)", 142 | "value": 3 143 | } 144 | ] 145 | } 146 | ], 147 | "messages": [] 148 | } 149 | } -------------------------------------------------------------------------------- /pkg/pocket/Cores/boogermann.supervision/variants.json: -------------------------------------------------------------------------------- 1 | { 2 | "variants": { 3 | "magic": "APF_VER_1", 4 | "variant_list": [] 5 | } 6 | } -------------------------------------------------------------------------------- /pkg/pocket/Cores/boogermann.supervision/video.json: -------------------------------------------------------------------------------- 1 | { 2 | "video": { 3 | "magic": "APF_VER_1", 4 | "scaler_modes": [ 5 | { 6 | "width": 320, 7 | "height": 160, 8 | "aspect_w": 1, 9 | "aspect_h": 1, 10 | "rotation": 0, 11 | "mirror": 0 12 | } 13 | ] 14 | } 15 | } -------------------------------------------------------------------------------- /pkg/pocket/Platforms/_images/supervision.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/opengateware/console-supervision/7c01e71e028de81171f74f835812dfc1e109cefe/pkg/pocket/Platforms/_images/supervision.bin -------------------------------------------------------------------------------- /pkg/pocket/Platforms/_images/supervision.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/opengateware/console-supervision/7c01e71e028de81171f74f835812dfc1e109cefe/pkg/pocket/Platforms/_images/supervision.png -------------------------------------------------------------------------------- /pkg/pocket/Platforms/supervision.json: -------------------------------------------------------------------------------- 1 | { 2 | "platform": { 3 | "category": "Handheld", 4 | "name": "Supervision", 5 | "manufacturer": "Watara", 6 | "year": 1992 7 | } 8 | } -------------------------------------------------------------------------------- /platform/pocket/apf.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "apf_top.v"] 2 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "common.v"] 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_bridge_peripheral.v"] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_pad_controller.v"] 5 | set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) "apf_constraints.sdc"] 6 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.qip"] 7 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_datatable.qip"] 8 | -------------------------------------------------------------------------------- /platform/pocket/apf_constraints.sdc: -------------------------------------------------------------------------------- 1 | # 2 | # APF constraints 3 | # Do not edit this file. 4 | # 5 | # Add your own constraints in the \core_constraints.sdc in the core directory, which will also be loaded. 6 | 7 | create_clock -name clk_74a -period 13.468 [get_ports clk_74a] 8 | create_clock -name clk_74b -period 13.468 [get_ports clk_74b] 9 | create_clock -name bridge_spiclk -period 13.468 [get_ports bridge_spiclk] 10 | 11 | # autogenerate PLL clock names for use down below 12 | derive_pll_clocks 13 | -------------------------------------------------------------------------------- /platform/pocket/build_cdf.tcl: -------------------------------------------------------------------------------- 1 | # ============================================================================== 2 | # SPDX-License-Identifier: CC0-1.0 3 | # SPDX-FileType: SOURCE 4 | # SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors 5 | # ============================================================================== 6 | # @file: build_cd.h 7 | # @brief: Generate a JTAG Chain Description File. 8 | # Create a .cdf file to be used with Quartus Prime Programmer 9 | # ============================================================================== 10 | proc createChainDescriptionFile {revision device outpath project_name} { 11 | set outputFileName "$project_name.cdf" 12 | set outputFile [open $outputFileName "w"] 13 | 14 | puts $outputFile "JedecChain;" 15 | puts $outputFile " FileRevision(JESD32A);" 16 | puts $outputFile " DefaultMfr(6E);" 17 | puts $outputFile "" 18 | puts $outputFile " P ActionCode(Cfg)" 19 | puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));" 20 | puts $outputFile "ChainEnd;" 21 | puts $outputFile "" 22 | puts $outputFile "AlteraBegin;" 23 | puts $outputFile " ChainType(JTAG);" 24 | puts $outputFile "AlteraEnd;" 25 | } 26 | 27 | set project_name [lindex $quartus(args) 1] 28 | set revision [lindex $quartus(args) 2] 29 | 30 | if {[project_exists $project_name]} { 31 | if {[string equal "" $revision]} { 32 | project_open $project_name -revision [get_current_revision $project_name] 33 | } else { 34 | project_open $project_name -revision $revision 35 | } 36 | } else { 37 | post_message -type error "Project $project_name does not exist" 38 | exit 39 | } 40 | 41 | set device [get_global_assignment -name DEVICE] 42 | set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY] 43 | 44 | if [is_project_open] { 45 | project_close 46 | } 47 | 48 | createChainDescriptionFile $revision $device $outpath $project_name 49 | -------------------------------------------------------------------------------- /platform/pocket/build_id_gen.tcl: -------------------------------------------------------------------------------- 1 | # ================================================================================ 2 | # (c) 2011 Altera Corporation. All rights reserved. 3 | # Altera products are protected under numerous U.S. and foreign patents, maskwork 4 | # rights, copyrights and other intellectual property laws. 5 | # 6 | # This reference design file, and your use thereof, is subject to and governed 7 | # by the terms and conditions of the applicable Altera Reference Design License 8 | # Agreement (either as signed by you, agreed by you upon download or as a 9 | # "click-through" agreement upon installation andor found at www.altera.com). 10 | # By using this reference design file, you indicate your acceptance of such terms 11 | # and conditions between you and Altera Corporation. In the event that you do 12 | # not agree with such terms and conditions, you may not use the reference design 13 | # file and please promptly destroy any copies you have made. 14 | # 15 | # This reference design file is being provided on an "as-is" basis and as an 16 | # accommodation and therefore all warranties, representations or guarantees of 17 | # any kind (whether express, implied or statutory) including, without limitation, 18 | # warranties of merchantability, non-infringement, or fitness for a particular 19 | # purpose, are specifically disclaimed. By making this reference design file 20 | # available, Altera expressly does not recommend, suggest or require that this 21 | # reference design file be used in combination with any other product not 22 | # provided by Altera. 23 | # ================================================================================ 24 | # 25 | # Build ID Verilog Module Script 26 | # Jeff Wiencrot - 8/1/2011 27 | # 28 | # Generates a Verilog module that contains a timestamp, physical address, and host name 29 | # from the current build. These values are available from the build_date, build_time, 30 | # physical_address, and host_name output ports of the build_id module in the build_id.v 31 | # Verilog source file. 32 | # 33 | # The format for each value is as follows: 34 | # Date - 32-bit decimal number of the format mmddyyyy 35 | # Time - 32-bit decimal number of the format hhmmss 36 | # Phyiscal Address - 48-bit hexadecimal number 37 | # Host name - 120-bit hexadecimal number with pairs of digits equal to the 38 | # hexadecimal code for the first 15 ASCII characters of the host 39 | # name. For added clarity, host names that have fewer than 30 40 | # hexadecimal digits (15 characters) are padded on the left with 41 | # zeros. 42 | # 43 | # Usage: 44 | # 45 | # To manually execute this script, source this file using the following Tcl commands: 46 | # source build_id_verilog.tcl 47 | # 48 | # To have this script automatically execute each time your project is built, use the 49 | # following command (see: http://www.altera.com/support/examples/tcl/auto_processing.html): 50 | # set_global_assignment -name PRE_FLOW_SCRIPT_FILE quartus_sh:build_id_verilog.tcl 51 | # 52 | # Comment out the last line to prevent the process from automatically executing when 53 | # the file is sourced. The process can then be executed with the following command: 54 | # generateBuildID_Verilog 55 | # 56 | # 57 | # For more information, see "build_identification.pdf" 58 | # 59 | # ================================================================================ 60 | # 61 | # 2021-01-21 Analogue 62 | # 63 | # Only care about generating build date/time, so the rest was removed. 64 | # The original can be downloaded from the Intel resource page 65 | # 66 | 67 | proc generateBuildID_Verilog {} { 68 | 69 | # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) 70 | set buildDate [ clock format [ clock seconds ] -format %Y%m%d ] 71 | set buildTime [ clock format [ clock seconds ] -format %H%M%S ] 72 | 73 | # Create a Verilog file for output 74 | set outputFileName "../platform/pocket/build_id.v" 75 | set outputFile [open $outputFileName "w"] 76 | 77 | # Output the Verilog source 78 | puts $outputFile "// Build ID Verilog Module" 79 | puts $outputFile "//" 80 | puts $outputFile "// Note - these are stored as binary coded decimal" 81 | puts $outputFile "// Date: $buildDate" 82 | puts $outputFile "// Time: $buildTime" 83 | puts $outputFile "" 84 | puts $outputFile "module build_id" 85 | puts $outputFile "(" 86 | puts $outputFile " output \[31:0\] build_date," 87 | puts $outputFile " output \[31:0\] build_time" 88 | puts $outputFile ");" 89 | puts $outputFile "" 90 | puts $outputFile " assign build_date = 32'h$buildDate;" 91 | puts $outputFile " assign build_time = 32'h$buildTime;" 92 | puts $outputFile "" 93 | puts $outputFile "endmodule" 94 | close $outputFile 95 | 96 | 97 | 98 | # Send confirmation message to the Messages window 99 | #post_message "APF core build date/time generated: [pwd]/$outputFileName" 100 | #post_message "Date: $buildDate" 101 | #post_message "Time: $buildTime" 102 | } 103 | 104 | 105 | proc generateBuildID_MIF {} { 106 | 107 | # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) 108 | set buildDate [ clock format [ clock seconds ] -format %Y%m%d ] 109 | set buildTime [ clock format [ clock seconds ] -format %H%M%S ] 110 | set buildUnique [expr {int(rand()*(4294967295))}] 111 | 112 | set buildDateNoLeadingZeros [string trimleft $buildDate "0"] 113 | set buildTimeNoLeadingZeros [string trimleft $buildTime "0"] 114 | set buildDate4Byte [format "%08d" $buildDateNoLeadingZeros] 115 | set buildTime4Byte [format "%08d" $buildTimeNoLeadingZeros] 116 | set buildUnique4Byte [format "%08x" $buildUnique] 117 | 118 | #set buildDate4Byte \ 119 | [concat [string range $buildDate 0 1] \ 120 | [string range $buildDate 2 3] \ 121 | [string range $buildDate 4 5] \ 122 | [string range $buildDate 6 7] ] 123 | 124 | 125 | set buildDateNumBytes 4 126 | set buildTimeNumBytes 4 127 | 128 | # Calculate depth of the memory (8-bit) words 129 | set memoryDepth [expr $buildDateNumBytes + $buildTimeNumBytes] 130 | 131 | # Create a Memory Initialization File for output 132 | set outputFileName "../platform/pocket/build_id.mif" 133 | set outputFile [open $outputFileName "w"] 134 | 135 | # Output the MIF header (see: http://quartushelp.altera.com/current/mergedProjects/reference/glossary/def_mif.htm) 136 | puts $outputFile "-- Build ID Memory Initialization File" 137 | puts $outputFile "--" 138 | puts $outputFile "" 139 | puts $outputFile "DEPTH = 256;" 140 | puts $outputFile "WIDTH = 32;" 141 | puts $outputFile "ADDRESS_RADIX = HEX;" 142 | puts $outputFile "DATA_RADIX = HEX;" 143 | puts $outputFile "" 144 | puts $outputFile "CONTENT" 145 | puts $outputFile "BEGIN" 146 | puts $outputFile "" 147 | puts $outputFile " 0E0 : $buildDate4Byte;" 148 | puts $outputFile " 0E1 : $buildTime4Byte;" 149 | puts $outputFile " 0E2 : $buildUnique4Byte;" 150 | puts $outputFile "" 151 | puts $outputFile "END;" 152 | 153 | # Close file to complete write 154 | close $outputFile 155 | 156 | # Send confirmation message to the Messages window 157 | post_message "APF core build date/time generated: [pwd]/$outputFileName" 158 | } 159 | 160 | generateBuildID_MIF 161 | 162 | # 2021-01-21 Analogue 163 | # 164 | # There are some circumstances where you want all parts of a FPGA flow to be deterministic, especially 165 | # when trying to hash out timing issues. 166 | # You should comment this line out and temporarily bypass buildid generation so that synthesis/par 167 | # have consistent working input. MIF bram contents like above won't affect the random seed or trigger 168 | # recompilation. 169 | # Don't forget to re-enable before you release. 170 | # 171 | # generateBuildID_Verilog 172 | -------------------------------------------------------------------------------- /platform/pocket/common.v: -------------------------------------------------------------------------------- 1 | // Software License Agreement 2 | 3 | // The software supplied herewith by Analogue Enterprises Limited (the "Company”), 4 | // the Analogue Pocket Framework (“APF”), is provided and licensed to you, the 5 | // Company's customer, solely for use in designing, testing and creating 6 | // applications for use with Company's Products or Services. The software is 7 | // owned by the Company and/or its licensors, and is protected under applicable 8 | // laws, including, but not limited to, U.S. copyright law. All rights are 9 | // reserved. By using the APF code you are agreeing to the terms of the End User 10 | // License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] 11 | // and incorporated herein by reference. To the extent any use of the APF requires 12 | // application of the MIT License or the GNU General Public License and terms of 13 | // this APF Software License Agreement and EULA are inconsistent with such license, 14 | // the applicable terms of the MIT License or the GNU General Public License, as 15 | // applicable, will prevail. 16 | 17 | // THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED 18 | // WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, 19 | // ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR 20 | // NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM 21 | // DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE 22 | // MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, 23 | // THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND 24 | // DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING 25 | // THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR 26 | // ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY 27 | // INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, 28 | // INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR 29 | // INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY 30 | // OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY 31 | // CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, 32 | // WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU 33 | // TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH 34 | // YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE 35 | // FULLEST EXTENT PERMITTED BY APPLICABLE LAW. 36 | // 37 | // 2-stage synchronizer 38 | // 39 | module synch_2 #(parameter WIDTH = 1) ( 40 | input wire [WIDTH-1:0] i, // input signal 41 | output reg [WIDTH-1:0] o, // synchronized output 42 | input wire clk, // clock to synchronize on 43 | output wire rise, // one-cycle rising edge pulse 44 | output wire fall // one-cycle falling edge pulse 45 | ); 46 | 47 | reg [WIDTH-1:0] stage_1; 48 | reg [WIDTH-1:0] stage_2; 49 | reg [WIDTH-1:0] stage_3; 50 | 51 | assign rise = (WIDTH == 1) ? (o & ~stage_2) : 1'b0; 52 | assign fall = (WIDTH == 1) ? (~o & stage_2) : 1'b0; 53 | always @(posedge clk) 54 | {stage_2, o, stage_1} <= {o, stage_1, i}; 55 | 56 | endmodule 57 | 58 | 59 | // 60 | // 3-stage synchronizer 61 | // 62 | module synch_3 #(parameter WIDTH = 1) ( 63 | input wire [WIDTH-1:0] i, // input signal 64 | output reg [WIDTH-1:0] o, // synchronized output 65 | input wire clk, // clock to synchronize on 66 | output wire rise, // one-cycle rising edge pulse 67 | output wire fall // one-cycle falling edge pulse 68 | ); 69 | 70 | reg [WIDTH-1:0] stage_1; 71 | reg [WIDTH-1:0] stage_2; 72 | reg [WIDTH-1:0] stage_3; 73 | 74 | assign rise = (WIDTH == 1) ? (o & ~stage_3) : 1'b0; 75 | assign fall = (WIDTH == 1) ? (~o & stage_3) : 1'b0; 76 | always @(posedge clk) 77 | {stage_3, o, stage_2, stage_1} <= {o, stage_2, stage_1, i}; 78 | 79 | endmodule 80 | 81 | 82 | module bram_block_dp #( 83 | parameter DATA = 32, 84 | parameter ADDR = 7 85 | ) ( 86 | input wire a_clk, 87 | input wire a_wr, 88 | input wire [ADDR-1:0] a_addr, 89 | input wire [DATA-1:0] a_din, 90 | output reg [DATA-1:0] a_dout, 91 | 92 | input wire b_clk, 93 | input wire b_wr, 94 | input wire [ADDR-1:0] b_addr, 95 | input wire [DATA-1:0] b_din, 96 | output reg [DATA-1:0] b_dout 97 | ); 98 | 99 | reg [DATA-1:0] mem [(2**ADDR)-1:0]; 100 | 101 | always @(posedge a_clk) begin 102 | if(a_wr) begin 103 | a_dout <= a_din; 104 | mem[a_addr] <= a_din; 105 | end else 106 | a_dout <= mem[a_addr]; 107 | end 108 | 109 | always @(posedge b_clk) begin 110 | if(b_wr) begin 111 | b_dout <= b_din; 112 | mem[b_addr] <= b_din; 113 | end else 114 | b_dout <= mem[b_addr]; 115 | end 116 | 117 | endmodule 118 | 119 | 120 | module bram_block_dp_nonstd #( 121 | parameter DATA = 32, 122 | parameter ADDR = 7, 123 | parameter DEPTH = 128 124 | ) ( 125 | input wire a_clk, 126 | input wire a_wr, 127 | input wire [ADDR-1:0] a_addr, 128 | input wire [DATA-1:0] a_din, 129 | output reg [DATA-1:0] a_dout, 130 | 131 | input wire b_clk, 132 | input wire b_wr, 133 | input wire [ADDR-1:0] b_addr, 134 | input wire [DATA-1:0] b_din, 135 | output reg [DATA-1:0] b_dout 136 | ); 137 | 138 | reg [DATA-1:0] mem [DEPTH-1:0]; 139 | 140 | always @(posedge a_clk) begin 141 | if(a_wr) begin 142 | a_dout <= a_din; 143 | mem[a_addr] <= a_din; 144 | end else 145 | a_dout <= mem[a_addr]; 146 | end 147 | 148 | always @(posedge b_clk) begin 149 | if(b_wr) begin 150 | b_dout <= b_din; 151 | mem[b_addr] <= b_din; 152 | end else 153 | b_dout <= mem[b_addr]; 154 | end 155 | 156 | endmodule 157 | -------------------------------------------------------------------------------- /platform/pocket/mf_datatable.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_datatable.v"] 5 | -------------------------------------------------------------------------------- /platform/pocket/mf_ddio_bidir_12.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.ppf"] 6 | -------------------------------------------------------------------------------- /platform/pocket/mf_ddio_bidir_12.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTDDIO_BIDIR% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: ALTDDIO_BIDIR 5 | 6 | // ============================================================ 7 | // File Name: mf_ddio_bidir_12.v 8 | // Megafunction Name(s): 9 | // ALTDDIO_BIDIR 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.1.1 Build 646 04/11/2019 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2019 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and any partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details, at 34 | //https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module mf_ddio_bidir_12 ( 41 | datain_h, 42 | datain_l, 43 | inclock, 44 | oe, 45 | outclock, 46 | dataout_h, 47 | dataout_l, 48 | padio); 49 | 50 | input [11:0] datain_h; 51 | input [11:0] datain_l; 52 | input inclock; 53 | input oe; 54 | input outclock; 55 | output [11:0] dataout_h; 56 | output [11:0] dataout_l; 57 | inout [11:0] padio; 58 | 59 | wire [11:0] sub_wire0; 60 | wire [11:0] sub_wire1; 61 | wire [11:0] dataout_h = sub_wire0[11:0]; 62 | wire [11:0] dataout_l = sub_wire1[11:0]; 63 | 64 | altddio_bidir ALTDDIO_BIDIR_component ( 65 | .datain_h (datain_h), 66 | .datain_l (datain_l), 67 | .inclock (inclock), 68 | .oe (oe), 69 | .outclock (outclock), 70 | .padio (padio), 71 | .dataout_h (sub_wire0), 72 | .dataout_l (sub_wire1), 73 | .aclr (1'b0), 74 | .aset (1'b0), 75 | .combout (), 76 | .dqsundelayedout (), 77 | .inclocken (1'b1), 78 | .oe_out (), 79 | .outclocken (1'b1), 80 | .sclr (1'b0), 81 | .sset (1'b0)); 82 | defparam 83 | ALTDDIO_BIDIR_component.extend_oe_disable = "OFF", 84 | ALTDDIO_BIDIR_component.implement_input_in_lcell = "OFF", 85 | ALTDDIO_BIDIR_component.intended_device_family = "Cyclone V", 86 | ALTDDIO_BIDIR_component.invert_output = "OFF", 87 | ALTDDIO_BIDIR_component.lpm_hint = "UNUSED", 88 | ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir", 89 | ALTDDIO_BIDIR_component.oe_reg = "UNREGISTERED", 90 | ALTDDIO_BIDIR_component.power_up_high = "OFF", 91 | ALTDDIO_BIDIR_component.width = 12; 92 | 93 | 94 | endmodule 95 | 96 | // ============================================================ 97 | // CNX file retrieval info 98 | // ============================================================ 99 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 100 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 101 | // Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" 102 | // Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "OFF" 103 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 104 | // Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" 105 | // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" 106 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" 107 | // Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" 108 | // Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" 109 | // Retrieval info: CONSTANT: WIDTH NUMERIC "12" 110 | // Retrieval info: USED_PORT: datain_h 0 0 12 0 INPUT NODEFVAL "datain_h[11..0]" 111 | // Retrieval info: CONNECT: @datain_h 0 0 12 0 datain_h 0 0 12 0 112 | // Retrieval info: USED_PORT: datain_l 0 0 12 0 INPUT NODEFVAL "datain_l[11..0]" 113 | // Retrieval info: CONNECT: @datain_l 0 0 12 0 datain_l 0 0 12 0 114 | // Retrieval info: USED_PORT: dataout_h 0 0 12 0 OUTPUT NODEFVAL "dataout_h[11..0]" 115 | // Retrieval info: CONNECT: dataout_h 0 0 12 0 @dataout_h 0 0 12 0 116 | // Retrieval info: USED_PORT: dataout_l 0 0 12 0 OUTPUT NODEFVAL "dataout_l[11..0]" 117 | // Retrieval info: CONNECT: dataout_l 0 0 12 0 @dataout_l 0 0 12 0 118 | // Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" 119 | // Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 120 | // Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" 121 | // Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 122 | // Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" 123 | // Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 124 | // Retrieval info: USED_PORT: padio 0 0 12 0 BIDIR NODEFVAL "padio[11..0]" 125 | // Retrieval info: CONNECT: padio 0 0 12 0 @padio 0 0 12 0 126 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.v TRUE FALSE 127 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.qip TRUE FALSE 128 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.bsf FALSE TRUE 129 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_inst.v FALSE TRUE 130 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_bb.v FALSE TRUE 131 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.inc FALSE TRUE 132 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.cmp FALSE TRUE 133 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.ppf TRUE FALSE 134 | // Retrieval info: LIB_FILE: altera_mf 135 | -------------------------------------------------------------------------------- /projects/supervision_pocket.qip: -------------------------------------------------------------------------------- 1 | # ============================================================================== 2 | # Quartus Prime Platform Specific Modules File 3 | # Generated by OpenGateware - Gateman CLI v0.1.0 4 | # ============================================================================== 5 | # A single file that contains paths to platform specific third-party modules. 6 | # Quartus will use this file but won't edit it. 7 | # You need to edit it manually to add/remove files here. 8 | # ============================================================================== 9 | 10 | set_global_assignment -name QIP_FILE "../modules/general-sync_fifo/index.qip" 11 | set_global_assignment -name QIP_FILE "../modules/pocket-i2s/index.qip" 12 | set_global_assignment -name QIP_FILE "../modules/pocket-joypad/index.qip" 13 | set_global_assignment -name QIP_FILE "../modules/pocket-dataloader/index.qip" 14 | set_global_assignment -name QIP_FILE "../modules/pocket-video/index.qip" 15 | set_global_assignment -name QIP_FILE "../modules/video-scanlines/index.qip" -------------------------------------------------------------------------------- /projects/supervision_pocket.qpf: -------------------------------------------------------------------------------- 1 | # ============================================================================== 2 | # Quartus Prime Project File 3 | # Generated by OpenGateware - Gateman CLI v0.1.0 4 | # ============================================================================== 5 | 6 | QUARTUS_VERSION = "18.1" 7 | DATE = "15:42:21 October 14, 2022" 8 | 9 | # Revisions 10 | 11 | PROJECT_REVISION = "supervision_pocket" 12 | -------------------------------------------------------------------------------- /projects/supervision_pocket.qsf: -------------------------------------------------------------------------------- 1 | # ============================================================================== 2 | # Quartus Prime Settings File 3 | # Generated by OpenGateware - Gateman CLI v0.1.0 4 | # ============================================================================== 5 | # WARNING: DO NOT ADD FILES TO THE PROJECT VIA THE QUARTUS IDE! 6 | # Add them manually to supervision_pocket.qip or Quartus will overwrite this file. 7 | # ============================================================================== 8 | 9 | # ============================================================================== 10 | # Project-Wide Assignments 11 | # ============================================================================== 12 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1 13 | set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Standard Edition" 14 | set_global_assignment -name TOP_LEVEL_ENTITY apf_top 15 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 16 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 17 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 18 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 19 | 20 | # ============================================================================== 21 | # Compiler Assignments 22 | # ============================================================================== 23 | set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL 24 | set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" 25 | set_global_assignment -name SAVE_DISK_SPACE OFF 26 | set_global_assignment -name SEED 1 27 | set_global_assignment -name SMART_RECOMPILE ON 28 | 29 | # ============================================================================== 30 | # Analysis & Synthesis Assignments 31 | # ============================================================================== 32 | set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON 33 | set_global_assignment -name MUX_RESTRUCTURE OFF 34 | set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED 35 | set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON 36 | set_global_assignment -name SAFE_STATE_MACHINE ON 37 | set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON 38 | 39 | # ============================================================================== 40 | # Fitter Assignments 41 | # ============================================================================== 42 | set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ 43 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON 44 | set_global_assignment -name ECO_OPTIMIZE_TIMING ON 45 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 46 | set_global_assignment -name FITTER_EFFORT "AUTO FIT" 47 | set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON 48 | set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON 49 | set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON 50 | set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON 51 | set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON 52 | set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON 53 | set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON 54 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" 55 | 56 | # ============================================================================== 57 | # Platform/Core Assignments 58 | # ============================================================================== 59 | source ../platform/pocket/pocket.tcl 60 | set_global_assignment -name QIP_FILE supervision_pocket.qip 61 | set_global_assignment -name SDC_FILE supervision_pocket.sdc 62 | set_global_assignment -name QIP_FILE ../rtl/supervision.qip 63 | 64 | # ============================================================================== 65 | 66 | 67 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /projects/supervision_pocket.sdc: -------------------------------------------------------------------------------- 1 | # ============================================================================== 2 | # Quartus Prime Synopsys Design Constraint File 3 | # Generated by OpenGateware - Gateman CLI v0.1.0 4 | # ============================================================================== 5 | # pocket SDC settings 6 | # Users are recommended to modify this file to match users logic. 7 | # Put your clock groups in here as well as any net assignments. 8 | # ============================================================================== 9 | 10 | # ============================================================================== 11 | # Time Information 12 | # ============================================================================== 13 | 14 | # ============================================================================== 15 | # Create Clock 16 | # ============================================================================== 17 | 18 | # ============================================================================== 19 | # Create Generated Clock 20 | # ============================================================================== 21 | 22 | # ============================================================================== 23 | # Set Clock Latency 24 | # ============================================================================== 25 | 26 | # ============================================================================== 27 | # Set Clock Uncertainty 28 | # ============================================================================== 29 | 30 | # ============================================================================== 31 | # Set Input Delay 32 | # ============================================================================== 33 | 34 | # ============================================================================== 35 | # Set Output Delay 36 | # ============================================================================== 37 | 38 | # ============================================================================== 39 | # Set Clock Groups 40 | # ============================================================================== 41 | 42 | # ============================================================================== 43 | # Set False Path 44 | # ============================================================================== 45 | 46 | # ============================================================================== 47 | # Set Multicycle Path 48 | # ============================================================================== 49 | 50 | # ============================================================================== 51 | # Set Maximum Delay 52 | # ============================================================================== 53 | 54 | # ============================================================================== 55 | # Set Minimum Delay 56 | # ============================================================================== 57 | 58 | # ============================================================================== 59 | # Set Input Transition 60 | # ============================================================================== 61 | 62 | -------------------------------------------------------------------------------- /rtl/bram.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- SPDX-License-Identifier: GPL-3.0-or-later 3 | -- SPDX-FileType: SOURCE 4 | -- SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors 5 | -------------------------------------------------------------------------------- 6 | -- 7 | -- Copyright (c) 2021 Jamie Blanks 8 | -- Copyright (c) 2020 Pierre Cornier (Pierco) 9 | -- 10 | -- This source file is free software: you can redistribute it and/or modify 11 | -- it under the terms of the GNU General Public License as published 12 | -- by the Free Software Foundation, either version 3 of the License, or 13 | -- (at your option) any later version. 14 | -- 15 | -- This source file is distributed in the hope that it will be useful, 16 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | -- GNU General Public License for more details. 19 | -- 20 | -- You should have received a copy of the GNU General Public License 21 | -- along with this program. If not, see . 22 | -- 23 | -------------------------------------------------------------------------------- 24 | 25 | -------------------------------------------------------------- 26 | -- Single port Block RAM 27 | -------------------------------------------------------------- 28 | 29 | library ieee; 30 | use ieee.std_logic_1164.all; 31 | 32 | library altera_mf; 33 | use altera_mf.altera_mf_components.all; 34 | 35 | entity spram is 36 | generic ( 37 | addr_width : integer := 8; 38 | data_width : integer := 8; 39 | mem_init_file : string := " "; 40 | mem_name : string := "MEM" -- for InSystem Memory content editor. 41 | ); 42 | port ( 43 | clock : in std_logic; 44 | address : in std_logic_vector (addr_width - 1 downto 0); 45 | data : in std_logic_vector (data_width - 1 downto 0) := (others => '0'); 46 | enable : in std_logic := '1'; 47 | wren : in std_logic := '0'; 48 | q : out std_logic_vector (data_width - 1 downto 0); 49 | cs : in std_logic := '1' 50 | ); 51 | end spram; 52 | architecture SYN of spram is 53 | begin 54 | spram_sz : work.spram_sz 55 | generic map(addr_width, data_width, 2 ** addr_width, mem_init_file, mem_name) 56 | port map(clock, address, data, enable, wren, q, cs); 57 | end SYN; 58 | -------------------------------------------------------------- 59 | -- Single port Block RAM with specific size 60 | -------------------------------------------------------------- 61 | 62 | library ieee; 63 | use ieee.std_logic_1164.all; 64 | 65 | library altera_mf; 66 | use altera_mf.altera_mf_components.all; 67 | 68 | entity spram_sz is 69 | generic ( 70 | addr_width : integer := 8; 71 | data_width : integer := 8; 72 | numwords : integer := 2 ** 8; 73 | mem_init_file : string := " "; 74 | mem_name : string := "MEM" -- for InSystem Memory content editor. 75 | ); 76 | port ( 77 | clock : in std_logic; 78 | address : in std_logic_vector (addr_width - 1 downto 0); 79 | data : in std_logic_vector (data_width - 1 downto 0) := (others => '0'); 80 | enable : in std_logic := '1'; 81 | wren : in std_logic := '0'; 82 | q : out std_logic_vector (data_width - 1 downto 0); 83 | cs : in std_logic := '1' 84 | ); 85 | end entity; 86 | 87 | architecture SYN of spram_sz is 88 | signal q0 : std_logic_vector((data_width - 1) downto 0); 89 | begin 90 | q <= q0 when cs = '1' else (others => '1'); 91 | 92 | altsyncram_component : altsyncram 93 | generic map( 94 | clock_enable_input_a => "BYPASS", 95 | clock_enable_output_a => "BYPASS", 96 | intended_device_family => "Cyclone V", 97 | lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=" & mem_name, 98 | lpm_type => "altsyncram", 99 | numwords_a => numwords, 100 | operation_mode => "SINGLE_PORT", 101 | outdata_aclr_a => "NONE", 102 | outdata_reg_a => "UNREGISTERED", 103 | power_up_uninitialized => "FALSE", 104 | read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", 105 | init_file => mem_init_file, 106 | widthad_a => addr_width, 107 | width_a => data_width, 108 | width_byteena_a => 1 109 | ) 110 | port map( 111 | address_a => address, 112 | clock0 => clock, 113 | data_a => data, 114 | wren_a => wren and cs, 115 | q_a => q0 116 | ); 117 | 118 | end SYN; 119 | 120 | -------------------------------------------------------------- 121 | -- Dual port Block RAM same parameters on both ports 122 | -------------------------------------------------------------- 123 | library ieee; 124 | use ieee.std_logic_1164.all; 125 | 126 | library altera_mf; 127 | use altera_mf.altera_mf_components.all; 128 | 129 | entity dpram is 130 | generic ( 131 | addr_width : integer := 8; 132 | data_width : integer := 8; 133 | mem_init_file : string := " " 134 | ); 135 | port ( 136 | clock : in std_logic; 137 | 138 | address_a : in std_logic_vector (addr_width - 1 downto 0); 139 | data_a : in std_logic_vector (data_width - 1 downto 0) := (others => '0'); 140 | enable_a : in std_logic := '1'; 141 | wren_a : in std_logic := '0'; 142 | q_a : out std_logic_vector (data_width - 1 downto 0); 143 | cs_a : in std_logic := '1'; 144 | 145 | address_b : in std_logic_vector (addr_width - 1 downto 0) := (others => '0'); 146 | data_b : in std_logic_vector (data_width - 1 downto 0) := (others => '0'); 147 | enable_b : in std_logic := '1'; 148 | wren_b : in std_logic := '0'; 149 | q_b : out std_logic_vector (data_width - 1 downto 0); 150 | cs_b : in std_logic := '1' 151 | ); 152 | end entity; 153 | architecture SYN of dpram is 154 | begin 155 | ram : work.dpram_dif generic map(addr_width, data_width, addr_width, data_width, mem_init_file) 156 | port map(clock, address_a, data_a, enable_a, wren_a, q_a, cs_a, address_b, data_b, enable_b, wren_b, q_b, cs_b); 157 | end SYN; 158 | 159 | -------------------------------------------------------------- 160 | -- Dual port Block RAM different parameters on ports 161 | -------------------------------------------------------------- 162 | library ieee; 163 | use ieee.std_logic_1164.all; 164 | 165 | library altera_mf; 166 | use altera_mf.altera_mf_components.all; 167 | 168 | entity dpram_dif is 169 | generic ( 170 | addr_width_a : integer := 8; 171 | data_width_a : integer := 8; 172 | addr_width_b : integer := 8; 173 | data_width_b : integer := 8; 174 | mem_init_file : string := " " 175 | ); 176 | port ( 177 | clock : in std_logic; 178 | 179 | address_a : in std_logic_vector (addr_width_a - 1 downto 0); 180 | data_a : in std_logic_vector (data_width_a - 1 downto 0) := (others => '0'); 181 | enable_a : in std_logic := '1'; 182 | wren_a : in std_logic := '0'; 183 | q_a : out std_logic_vector (data_width_a - 1 downto 0); 184 | cs_a : in std_logic := '1'; 185 | 186 | address_b : in std_logic_vector (addr_width_b - 1 downto 0) := (others => '0'); 187 | data_b : in std_logic_vector (data_width_b - 1 downto 0) := (others => '0'); 188 | enable_b : in std_logic := '1'; 189 | wren_b : in std_logic := '0'; 190 | q_b : out std_logic_vector (data_width_b - 1 downto 0); 191 | cs_b : in std_logic := '1' 192 | ); 193 | end entity; 194 | architecture SYN of dpram_dif is 195 | 196 | signal q0 : std_logic_vector((data_width_a - 1) downto 0); 197 | signal q1 : std_logic_vector((data_width_b - 1) downto 0); 198 | 199 | begin 200 | q_a <= q0 when cs_a = '1' else (others => '1'); 201 | q_b <= q1 when cs_b = '1' else (others => '1'); 202 | 203 | altsyncram_component : altsyncram 204 | generic map( 205 | address_reg_b => "CLOCK1", 206 | clock_enable_input_a => "NORMAL", 207 | clock_enable_input_b => "NORMAL", 208 | clock_enable_output_a => "BYPASS", 209 | clock_enable_output_b => "BYPASS", 210 | indata_reg_b => "CLOCK1", 211 | intended_device_family => "Cyclone V", 212 | lpm_type => "altsyncram", 213 | numwords_a => 2 ** addr_width_a, 214 | numwords_b => 2 ** addr_width_b, 215 | operation_mode => "BIDIR_DUAL_PORT", 216 | outdata_aclr_a => "NONE", 217 | outdata_aclr_b => "NONE", 218 | outdata_reg_a => "UNREGISTERED", 219 | outdata_reg_b => "UNREGISTERED", 220 | power_up_uninitialized => "FALSE", 221 | read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", 222 | read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", 223 | init_file => mem_init_file, 224 | widthad_a => addr_width_a, 225 | widthad_b => addr_width_b, 226 | width_a => data_width_a, 227 | width_b => data_width_b, 228 | width_byteena_a => 1, 229 | width_byteena_b => 1, 230 | wrcontrol_wraddress_reg_b => "CLOCK1" 231 | ) 232 | port map( 233 | address_a => address_a, 234 | address_b => address_b, 235 | clock0 => clock, 236 | clock1 => clock, 237 | clocken0 => enable_a, 238 | clocken1 => enable_b, 239 | data_a => data_a, 240 | data_b => data_b, 241 | wren_a => wren_a and cs_a, 242 | wren_b => wren_b and cs_b, 243 | q_a => q0, 244 | q_b => q1 245 | ); 246 | 247 | end SYN; 248 | -------------------------------------------------------------------------------- /rtl/dma.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // SPDX-License-Identifier: GPL-3.0-or-later 3 | // SPDX-FileType: SOURCE 4 | // SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors 5 | //------------------------------------------------------------------------------ 6 | // 7 | // Copyright (c) 2021 Jamie Blanks 8 | // Copyright (c) 2020 Pierre Cornier (Pierco) 9 | // 10 | // This source file is free software: you can redistribute it and/or modify 11 | // it under the terms of the GNU General Public License as published 12 | // by the Free Software Foundation, either version 3 of the License, or 13 | // (at your option) any later version. 14 | // 15 | // This source file is distributed in the hope that it will be useful, 16 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | // GNU General Public License for more details. 19 | // 20 | // You should have received a copy of the GNU General Public License 21 | // along with this program. If not, see . 22 | // 23 | //------------------------------------------------------------------------------ 24 | 25 | module dma 26 | ( 27 | input clk, 28 | input ce, 29 | input reset, 30 | input [5:0] AB, 31 | input cpu_rwn, 32 | input dma_cs, 33 | input lcd_en, 34 | input [7:0] data_in, 35 | output reg [15:0] cbus_addr, 36 | output reg [12:0] vbus_addr, 37 | output reg dma_dir, 38 | output dma_en 39 | ); 40 | 41 | reg dma_started; 42 | reg [7:0] dma_length; 43 | reg [3:0] dma_phase; 44 | reg [2:0] lcd_div; 45 | 46 | assign dma_en = dma_started; 47 | wire lcd_ce = lcd_div == 5 && lcd_en; 48 | 49 | always_ff @(posedge clk) begin 50 | if (ce) begin 51 | lcd_div <= lcd_div + 1'd1; 52 | if (lcd_div == 5) 53 | lcd_div <= 0; 54 | 55 | if (dma_started && ~lcd_ce) begin 56 | cbus_addr <= cbus_addr + 1'd1; 57 | vbus_addr <= vbus_addr + 1'd1; 58 | dma_phase <= dma_phase - 1'd1; 59 | if (~|dma_phase) begin 60 | dma_length <= dma_length - 1'd1; 61 | if (dma_length == 1) begin 62 | dma_started <= 0; 63 | end 64 | end 65 | end 66 | 67 | if (~cpu_rwn && dma_cs) begin 68 | case(AB) 69 | 6'h08: cbus_addr[7:0] <= data_in; 70 | 6'h09: cbus_addr[15:8] <= data_in; 71 | 6'h0A: vbus_addr[7:0] <= data_in; 72 | 6'h0B: {dma_dir, vbus_addr[12:8]} <= {data_in[6], data_in[4:0]}; 73 | 6'h0C: dma_length <= data_in; 74 | 6'h0D: if (data_in[7]) begin dma_started <= 1; dma_phase <= 4'd15; end 75 | endcase 76 | end 77 | end 78 | if (reset) begin 79 | dma_started <= 0; 80 | dma_length <= 0; 81 | vbus_addr <= 0; 82 | cbus_addr <= 0; 83 | lcd_div <= 0; 84 | dma_dir <= 0; 85 | end 86 | end 87 | endmodule 88 | -------------------------------------------------------------------------------- /rtl/index.qip: -------------------------------------------------------------------------------- 1 | # ============================================================================== 2 | # Quartus Prime QIP Index File 3 | # ============================================================================== 4 | -------------------------------------------------------------------------------- /rtl/lcd.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // SPDX-License-Identifier: GPL-3.0-or-later 3 | // SPDX-FileType: SOURCE 4 | // SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors 5 | //------------------------------------------------------------------------------ 6 | // 7 | // Copyright (c) 2021 Jamie Blanks 8 | // Copyright (c) 2020 Pierre Cornier (Pierco) 9 | // 10 | // This source file is free software: you can redistribute it and/or modify 11 | // it under the terms of the GNU General Public License as published 12 | // by the Free Software Foundation, either version 3 of the License, or 13 | // (at your option) any later version. 14 | // 15 | // This source file is distributed in the hope that it will be useful, 16 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | // GNU General Public License for more details. 19 | // 20 | // You should have received a copy of the GNU General Public License 21 | // along with this program. If not, see . 22 | // 23 | //------------------------------------------------------------------------------ 24 | 25 | module lcd 26 | ( 27 | input clk, 28 | input ce, 29 | input reset, 30 | input lcd_cs, 31 | input cpu_rwn, 32 | input compat60, 33 | input [5:0] AB, 34 | input [7:0] dbus_in, 35 | input [7:0] vram_data, 36 | input lcd_off, 37 | output ce_pix, 38 | output reg [1:0] pixel, 39 | output [12:0] vram_addr, 40 | output hsync, 41 | output vsync, 42 | output reg hblank, 43 | output reg vblank 44 | ); 45 | 46 | localparam H_WIDTH = 9'd300; 47 | localparam H_WIDTH_COMPAT = 9'd254; 48 | localparam V_HEIGHT = 9'd262; 49 | localparam PHYS_WIDTH = 9'd160; 50 | localparam PHYS_HEIGHT = 9'd160; 51 | 52 | wire [8:0] h_w = compat60 ? H_WIDTH_COMPAT : H_WIDTH; 53 | 54 | reg [7:0] lcd_xsize, lcd_ysize, lcd_xscroll, lcd_yscroll; 55 | reg lcd_off_latch; 56 | reg wrapped; 57 | reg [9:0] wrap_offset; 58 | reg [8:0] hblank_start, hblank_end, vblank_start, vblank_end, vpos, hpos; 59 | reg [31:0] dot_count, frame_len; 60 | 61 | wire [9:0] vpos_off = (vpos - vblank_end) + lcd_yscroll; 62 | wire [9:0] hpos_off = (hpos - hblank_end) + lcd_xscroll; 63 | wire [9:0] vpos_wrap = vpos_off > 169 && lcd_xscroll < 8'h1C ? vpos_off - 10'd170 : vpos_off; 64 | wire [7:0] hpos_div_4 = hpos_off[9:2]; 65 | wire [13:0] vram_addr_t = (vpos_wrap * 8'h30) + hpos_div_4; 66 | 67 | // The lcd does a weird trunction of any extra bits past the end of it's buffer to make the 192x170 68 | // dimensions work, while the memory is 8kb. This is intentionally truncated to 12 bits. 69 | 70 | assign vram_addr = vram_addr_t > 14'h1FE0 ? (vram_addr_t + 8'h40) : vram_addr_t[12:0]; 71 | 72 | initial begin 73 | hblank_end = 8'd70; 74 | vblank_end = 8'd51; 75 | vpos = 0; 76 | hpos = 0; 77 | lcd_xsize = 8'd160; 78 | lcd_ysize = 8'd160; 79 | frame_len = 20'd78719; 80 | end 81 | 82 | assign ce_pix = ce; 83 | 84 | reg [7:0] vb; 85 | 86 | wire hblank_im = hpos <= hblank_end || hpos > hblank_end + PHYS_WIDTH; 87 | wire vblank_im = vpos < vblank_end || vpos >= vblank_end + PHYS_HEIGHT; 88 | assign vsync = vpos < 2 || vpos > V_HEIGHT - 1'd1; // Catch the uneven line in vsync to see if it helps 89 | assign hsync = hpos < 16 || hpos > (h_w - 8'd16); 90 | 91 | 92 | always_ff @(posedge clk) begin 93 | reg old_compat; 94 | if (ce) begin 95 | old_compat <= compat60; 96 | hblank <= hblank_im; 97 | vblank <= vblank_im; 98 | pixel <= lcd_off_latch ? 2'b00 : vram_data[{hpos_off[1:0], 1'b1}-:2]; 99 | 100 | if (lcd_off) 101 | lcd_off_latch <= 1; 102 | 103 | dot_count <= dot_count + 1'd1; 104 | hpos <= hpos + 1'd1; 105 | if (hpos == (h_w - 1'd1)) begin 106 | hpos <= 0; 107 | vpos <= vpos + 1'd1; 108 | end 109 | 110 | // Synchronize with real frame, we'll see how it goes. 111 | if ((compat60 ? (hpos == (h_w - 1'd1) && vpos == (V_HEIGHT - 1'd1)) : (dot_count >= frame_len)) || (old_compat != compat60)) begin 112 | hpos <= 0; 113 | vpos <= 0; 114 | dot_count <= 0; 115 | hblank_end <= (h_w - PHYS_WIDTH) >> 1'd1; 116 | vblank_end <= (V_HEIGHT - PHYS_HEIGHT) >> 1'd1; 117 | lcd_off_latch <= lcd_off; 118 | frame_len <= ((lcd_xsize[7:2] + 1'd1) * lcd_ysize * 12) - 1'd1; 119 | end 120 | 121 | if (lcd_cs && ~cpu_rwn) begin 122 | case(AB) 123 | 6'h00, 6'h04: lcd_xsize <= dbus_in; 124 | 6'h01, 6'h05: lcd_ysize <= dbus_in; 125 | 6'h02, 6'h06: lcd_xscroll <= dbus_in; 126 | 6'h03, 6'h07: lcd_yscroll <= dbus_in; 127 | endcase 128 | end 129 | end 130 | 131 | if (reset) begin 132 | lcd_xscroll <= 0; 133 | lcd_yscroll <= 0; 134 | hblank_end <= (h_w - lcd_xsize) >> 1'd1; 135 | vblank_end <= (V_HEIGHT - lcd_ysize) >> 1'd1; 136 | lcd_off_latch <= 1; 137 | // Do not reset these registers intentionally 138 | // lcd_xsize <= 8'd160; 139 | // lcd_ysize <= 8'd160; 140 | end 141 | end 142 | 143 | endmodule 144 | -------------------------------------------------------------------------------- /rtl/sdram.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // SPDX-License-Identifier: GPL-3.0-or-later 3 | // SPDX-FileType: SOURCE 4 | // SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors 5 | //------------------------------------------------------------------------------ 6 | // 7 | // Copyright (c) 2021 Jamie Blanks 8 | // Copyright (c) 2020 Pierre Cornier (Pierco) 9 | // Copyright (c) 2018 Alexey Melnikov 10 | // 11 | // This source file is free software: you can redistribute it and/or modify 12 | // it under the terms of the GNU General Public License as published 13 | // by the Free Software Foundation, either version 3 of the License, or 14 | // (at your option) any later version. 15 | // 16 | // This source file is distributed in the hope that it will be useful, 17 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 18 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 | // GNU General Public License for more details. 20 | // 21 | // You should have received a copy of the GNU General Public License 22 | // along with this program. If not, see . 23 | // 24 | //------------------------------------------------------------------------------ 25 | // SDRAM Controller Implementation 26 | //------------------------------------------------------------------------------ 27 | 28 | module sdram 29 | ( 30 | 31 | // interface to the MT48LC16M16 chip 32 | inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus 33 | output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus 34 | output reg SDRAM_DQML, // byte mask 35 | output reg SDRAM_DQMH, // byte mask 36 | output reg [1:0] SDRAM_BA, // two banks 37 | output reg SDRAM_nCS, // a single chip select 38 | output reg SDRAM_nWE, // write enable 39 | output reg SDRAM_nRAS, // row address select 40 | output reg SDRAM_nCAS, // columns address select 41 | output SDRAM_CLK, 42 | output SDRAM_CKE, 43 | 44 | // cpu/chipset interface 45 | input init, // init signal after FPGA config to initialize RAM 46 | input clk, // sdram is accessed at up to 128MHz 47 | 48 | input [24:0] ch0_addr, 49 | input ch0_rd, 50 | input ch0_wr, 51 | input [7:0] ch0_din, 52 | output reg [7:0] ch0_dout, 53 | output reg ch0_busy, 54 | 55 | input [24:0] ch1_addr, 56 | input ch1_rd, 57 | input ch1_wr, 58 | input [7:0] ch1_din, 59 | output reg [7:0] ch1_dout, 60 | output reg ch1_busy, 61 | 62 | input [24:0] ch2_addr, 63 | input ch2_rd, 64 | input ch2_wr, 65 | input [7:0] ch2_din, 66 | output reg [7:0] ch2_dout, 67 | output reg ch2_busy 68 | ); 69 | 70 | assign SDRAM_nCS = 0; 71 | assign SDRAM_CKE = 1; 72 | assign {SDRAM_DQMH,SDRAM_DQML} = SDRAM_A[12:11]; 73 | 74 | localparam RASCAS_DELAY = 3'd1; // tRCD=20ns -> 2 cycles@85MHz 75 | localparam BURST_LENGTH = 3'd0; // 0=1, 1=2, 2=4, 3=8, 7=full page 76 | localparam ACCESS_TYPE = 1'd0; // 0=sequential, 1=interleaved 77 | localparam CAS_LATENCY = 3'd2; // 2/3 allowed 78 | localparam OP_MODE = 2'd0; // only 0 (standard operation) allowed 79 | localparam NO_WRITE_BURST = 1'd1; // 0=write burst enabled, 1=only single access write 80 | 81 | localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; 82 | 83 | localparam STATE_IDLE = 3'd0; // state to check the requests 84 | localparam STATE_START = STATE_IDLE+1'd1; // state in which a new command is started 85 | localparam STATE_NEXT = STATE_START+1'd1; // state in which a new command is started 86 | localparam STATE_CONT = STATE_START+RASCAS_DELAY; 87 | localparam STATE_READY = STATE_CONT+CAS_LATENCY+2'd2; 88 | localparam STATE_LAST = STATE_READY; // last state in cycle 89 | 90 | reg [2:0] state; 91 | reg [22:0] a; 92 | reg [1:0] bank; 93 | reg [15:0] data; 94 | reg we; 95 | reg ram_req=0; 96 | 97 | wire [2:0] rd,wr; 98 | 99 | assign rd = {ch2_rd, ch1_rd, ch0_rd}; 100 | assign wr = {ch2_wr, ch1_wr, ch0_wr}; 101 | 102 | // access manager 103 | always @(posedge clk) begin 104 | reg old_ref; 105 | reg [2:0] old_rd,old_wr;//,rd,wr; 106 | reg [24:1] last_a[3] = '{'1,'1,'1}; 107 | 108 | old_rd <= old_rd & rd; 109 | old_wr <= old_wr & wr; 110 | 111 | if(state == STATE_IDLE && mode == MODE_NORMAL) begin 112 | ram_req <= 0; 113 | we <= 0; 114 | ch0_busy <= 0; 115 | ch1_busy <= 0; 116 | ch2_busy <= 0; 117 | if((~old_rd[0] & rd[0]) | (~old_wr[0] & wr[0])) begin 118 | old_rd[0] <= rd[0]; 119 | old_wr[0] <= wr[0]; 120 | we <= wr[0]; 121 | {bank,a} <= ch0_addr; 122 | data <= {ch0_din,ch0_din}; 123 | ram_req <= wr[0] || (last_a[0] != ch0_addr[24:1]); 124 | last_a[0] <= wr[0] ? '1 : ch0_addr[24:1]; 125 | ch0_busy <= 1; 126 | state <= STATE_START; 127 | end 128 | else if((~old_rd[1] & rd[1]) | (~old_wr[1] & wr[1])) begin 129 | old_rd[1] <= rd[1]; 130 | old_wr[1] <= wr[1]; 131 | we <= wr[1]; 132 | {bank,a} <= ch1_addr; 133 | data <= {ch1_din,ch1_din}; 134 | ram_req <= wr[1] || (last_a[1] != ch1_addr[24:1]); 135 | last_a[1] <= wr[1] ? '1 : ch1_addr[24:1]; 136 | ch1_busy <= 1; 137 | state <= STATE_START; 138 | end 139 | else if((~old_rd[2] & rd[2]) | (~old_wr[2] & wr[2])) begin 140 | old_rd[2] <= rd[2]; 141 | old_wr[2] <= wr[2]; 142 | we <= wr[2]; 143 | {bank,a} <= ch2_addr; 144 | data <= {ch2_din,ch2_din}; 145 | ram_req <= wr[2] || (last_a[2] != ch2_addr[24:1]); 146 | last_a[2] <= wr[2] ? '1 : ch2_addr[24:1]; 147 | ch2_busy <= 1; 148 | state <= STATE_START; 149 | end 150 | end 151 | 152 | if (state == STATE_READY) begin 153 | ch0_busy <= 0; 154 | ch1_busy <= 0; 155 | ch2_busy <= 0; 156 | end 157 | 158 | if(mode != MODE_NORMAL || state != STATE_IDLE || reset) begin 159 | state <= state + 1'd1; 160 | if(state == STATE_LAST) state <= STATE_IDLE; 161 | end 162 | end 163 | 164 | localparam MODE_NORMAL = 2'b00; 165 | localparam MODE_RESET = 2'b01; 166 | localparam MODE_LDM = 2'b10; 167 | localparam MODE_PRE = 2'b11; 168 | 169 | // initialization 170 | reg [1:0] mode; 171 | reg [4:0] reset=5'h1f; 172 | always @(posedge clk) begin 173 | reg init_old=0; 174 | init_old <= init; 175 | 176 | if(init_old & ~init) reset <= 5'h1f; 177 | else if(state == STATE_LAST) begin 178 | if(reset != 0) begin 179 | reset <= reset - 5'd1; 180 | if(reset == 14) mode <= MODE_PRE; 181 | else if(reset == 3) mode <= MODE_LDM; 182 | else mode <= MODE_RESET; 183 | end 184 | else mode <= MODE_NORMAL; 185 | end 186 | end 187 | 188 | localparam CMD_NOP = 3'b111; 189 | localparam CMD_ACTIVE = 3'b011; 190 | localparam CMD_READ = 3'b101; 191 | localparam CMD_WRITE = 3'b100; 192 | localparam CMD_BURST_TERMINATE = 3'b110; 193 | localparam CMD_PRECHARGE = 3'b010; 194 | localparam CMD_AUTO_REFRESH = 3'b001; 195 | localparam CMD_LOAD_MODE = 3'b000; 196 | 197 | wire [1:0] dqm = {we & ~a[0], we & a[0]}; 198 | 199 | // SDRAM state machines 200 | always @(posedge clk) begin 201 | reg [15:0] last_data[3]; 202 | reg [15:0] data_reg; 203 | 204 | if(state == STATE_START) SDRAM_BA <= (mode == MODE_NORMAL) ? bank : 2'b00; 205 | 206 | SDRAM_DQ <= 'Z; 207 | casex({ram_req,we,mode,state}) 208 | {2'b1X, MODE_NORMAL, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_ACTIVE; 209 | {2'b11, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE, SDRAM_DQ} <= {CMD_WRITE, data}; 210 | {2'b10, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_READ; 211 | {2'b0X, MODE_NORMAL, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_AUTO_REFRESH; 212 | 213 | // init 214 | {2'bXX, MODE_LDM, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_LOAD_MODE; 215 | {2'bXX, MODE_PRE, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_PRECHARGE; 216 | 217 | default: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_NOP; 218 | endcase 219 | 220 | casex({ram_req,mode,state}) 221 | {1'b1, MODE_NORMAL, STATE_START}: SDRAM_A <= a[13:1]; 222 | {1'b1, MODE_NORMAL, STATE_CONT }: SDRAM_A <= {dqm, 2'b10, a[22:14]}; 223 | 224 | // init 225 | {1'bX, MODE_LDM, STATE_START}: SDRAM_A <= MODE; 226 | {1'bX, MODE_PRE, STATE_START}: SDRAM_A <= 13'b0010000000000; 227 | 228 | default: SDRAM_A <= 13'b0000000000000; 229 | endcase 230 | 231 | data_reg <= SDRAM_DQ; 232 | 233 | if(state == STATE_READY) begin 234 | if(ch0_busy) begin 235 | if(ram_req) begin 236 | if(we) ch0_dout <= data[7:0]; 237 | else begin 238 | ch0_dout <= a[0] ? data_reg[15:8] : data_reg[7:0]; 239 | last_data[0] <= data_reg; 240 | end 241 | end 242 | else ch0_dout <= a[0] ? last_data[0][15:8] : last_data[0][7:0]; 243 | end 244 | if(ch1_busy) begin 245 | if(ram_req) begin 246 | if(we) ch1_dout <= data[7:0]; 247 | else begin 248 | ch1_dout <= a[0] ? data_reg[15:8] : data_reg[7:0]; 249 | last_data[1] <= data_reg; 250 | end 251 | end 252 | else ch1_dout <= a[0] ? last_data[1][15:8] : last_data[1][7:0]; 253 | end 254 | if(ch2_busy) begin 255 | if(ram_req) begin 256 | if(we) ch2_dout <= data[7:0]; 257 | else begin 258 | ch2_dout <= a[0] ? data_reg[15:8] : data_reg[7:0]; 259 | last_data[2] <= data_reg; 260 | end 261 | end 262 | else ch2_dout <= a[0] ? last_data[2][15:8] : last_data[2][7:0]; 263 | end 264 | end 265 | end 266 | 267 | 268 | altddio_out 269 | #( 270 | .extend_oe_disable("OFF"), 271 | .intended_device_family("Cyclone V"), 272 | .invert_output("OFF"), 273 | .lpm_hint("UNUSED"), 274 | .lpm_type("altddio_out"), 275 | .oe_reg("UNREGISTERED"), 276 | .power_up_high("OFF"), 277 | .width(1) 278 | ) 279 | sdramclk_ddr 280 | ( 281 | .datain_h(1'b0), 282 | .datain_l(1'b1), 283 | .outclock(clk), 284 | .dataout(SDRAM_CLK), 285 | .aclr(1'b0), 286 | .aset(1'b0), 287 | .oe(1'b1), 288 | .outclocken(1'b1), 289 | .sclr(1'b0), 290 | .sset(1'b0) 291 | ); 292 | 293 | endmodule 294 | -------------------------------------------------------------------------------- /rtl/supervision.qip: -------------------------------------------------------------------------------- 1 | # ============================================================================== 2 | # RTL 3 | # ============================================================================== 4 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "audio.sv"] 5 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "dma.sv"] 6 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "lcd.sv"] 7 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "sdram.sv"] 8 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "supervision.sv"] 9 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "bram.vhd"] 10 | 11 | # ============================================================================== 12 | # MODULES 13 | # ============================================================================== 14 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "../modules/cpu-r65c02_tc/index.qip"] 15 | -------------------------------------------------------------------------------- /target/pocket/core.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "core_top.sv"] 2 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "core_bridge_cmd.v"] 3 | set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) "core_constraints.sdc"] 4 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_pllbase.qip"] 5 | -------------------------------------------------------------------------------- /target/pocket/core_constraints.sdc: -------------------------------------------------------------------------------- 1 | # 2 | # user core constraints 3 | # 4 | # put your clock groups in here as well as any net assignments 5 | # 6 | 7 | set_clock_groups -asynchronous \ 8 | -group { bridge_spiclk } \ 9 | -group { clk_74a } \ 10 | -group { clk_74b } \ 11 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ 12 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ 13 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \ 14 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk } 15 | -------------------------------------------------------------------------------- /target/pocket/mf_pllbase.ppf: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /target/pocket/mf_pllbase/mf_pllbase_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET OFF -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /target/pocket/mf_pllbase/mf_pllbase_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module mf_pllbase_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'outclk1' 14 | output wire outclk_1, 15 | 16 | // interface 'outclk2' 17 | output wire outclk_2, 18 | 19 | // interface 'outclk3' 20 | output wire outclk_3, 21 | 22 | // interface 'locked' 23 | output wire locked 24 | ); 25 | 26 | altera_pll #( 27 | .fractional_vco_multiplier("true"), 28 | .reference_clock_frequency("74.25 MHz"), 29 | .operation_mode("normal"), 30 | .number_of_clocks(4), 31 | .output_clock_frequency0("64.000000 MHz"), 32 | .phase_shift0("0 ps"), 33 | .duty_cycle0(50), 34 | .output_clock_frequency1("8.000000 MHz"), 35 | .phase_shift1("0 ps"), 36 | .duty_cycle1(50), 37 | .output_clock_frequency2("8.000000 MHz"), 38 | .phase_shift2("31250 ps"), 39 | .duty_cycle2(50), 40 | .output_clock_frequency3("16.000000 MHz"), 41 | .phase_shift3("0 ps"), 42 | .duty_cycle3(50), 43 | .output_clock_frequency4("0 MHz"), 44 | .phase_shift4("0 ps"), 45 | .duty_cycle4(50), 46 | .output_clock_frequency5("0 MHz"), 47 | .phase_shift5("0 ps"), 48 | .duty_cycle5(50), 49 | .output_clock_frequency6("0 MHz"), 50 | .phase_shift6("0 ps"), 51 | .duty_cycle6(50), 52 | .output_clock_frequency7("0 MHz"), 53 | .phase_shift7("0 ps"), 54 | .duty_cycle7(50), 55 | .output_clock_frequency8("0 MHz"), 56 | .phase_shift8("0 ps"), 57 | .duty_cycle8(50), 58 | .output_clock_frequency9("0 MHz"), 59 | .phase_shift9("0 ps"), 60 | .duty_cycle9(50), 61 | .output_clock_frequency10("0 MHz"), 62 | .phase_shift10("0 ps"), 63 | .duty_cycle10(50), 64 | .output_clock_frequency11("0 MHz"), 65 | .phase_shift11("0 ps"), 66 | .duty_cycle11(50), 67 | .output_clock_frequency12("0 MHz"), 68 | .phase_shift12("0 ps"), 69 | .duty_cycle12(50), 70 | .output_clock_frequency13("0 MHz"), 71 | .phase_shift13("0 ps"), 72 | .duty_cycle13(50), 73 | .output_clock_frequency14("0 MHz"), 74 | .phase_shift14("0 ps"), 75 | .duty_cycle14(50), 76 | .output_clock_frequency15("0 MHz"), 77 | .phase_shift15("0 ps"), 78 | .duty_cycle15(50), 79 | .output_clock_frequency16("0 MHz"), 80 | .phase_shift16("0 ps"), 81 | .duty_cycle16(50), 82 | .output_clock_frequency17("0 MHz"), 83 | .phase_shift17("0 ps"), 84 | .duty_cycle17(50), 85 | .pll_type("General"), 86 | .pll_subtype("General") 87 | ) altera_pll_i ( 88 | .rst (rst), 89 | .outclk ({outclk_3, outclk_2, outclk_1, outclk_0}), 90 | .locked (locked), 91 | .fboutclk ( ), 92 | .fbclk (1'b0), 93 | .refclk (refclk) 94 | ); 95 | endmodule 96 | 97 | --------------------------------------------------------------------------------