├── docs ├── .gitignore ├── images │ ├── CV32E40P_Pipeline.png │ ├── image_sources │ │ ├── wfi.tim │ │ ├── load_event.tim │ │ ├── debug_halted.tim │ │ ├── debug_running.tim │ │ ├── obi_data_basic.tim │ │ ├── obi_data_back_to_back.tim │ │ ├── obi_instruction_basic.tim │ │ ├── obi_data_slow_response.tim │ │ ├── Events_PCCR_PCMR_and_PCER.odg │ │ ├── obi_data_multiple_outstanding.tim │ │ └── obi_instruction_multiple_outstanding.tim │ ├── openhw-landscape.png │ ├── rtl_freeze_rules.png │ ├── CV32E40P_Block_Diagram.png │ ├── Events_PCCR_PCMR_PCER.png │ ├── riscv_prefetch_buffer.png │ ├── Basic_Memory_Transaction.png │ ├── Back_to_Back_Memory_Transaction.png │ ├── Slow_Response_Memory_Transaction.png │ └── ImperasDV_diagram_May_2023-reduced.jpg ├── requirements.txt ├── source │ ├── _static │ │ └── css │ │ │ └── custom.css │ ├── list.issue │ ├── preface.rst │ ├── index.rst │ ├── register_file.rst │ └── glossary.rst ├── make.bat └── Makefile ├── .github ├── ISSUE_TEMPLATE │ ├── enhancement.md │ ├── question.md │ ├── task.md │ ├── config.yml │ └── bug.md ├── release.yml └── workflows │ ├── check_target_on_pr.yml │ ├── merge_dev_to_master.yml │ ├── aws.yml │ ├── lint.yml │ └── aws_cv32e40p.md ├── scripts ├── lint │ ├── qverify_autocheck.do │ ├── qverify_analysis.do │ ├── formal_lint_rules.do │ ├── config_0p_0f_0z_0lat_0c │ │ └── cv32e40p_config_pkg.sv │ ├── config_1p_0f_0z_0lat_0c │ │ └── cv32e40p_config_pkg.sv │ ├── config_1p_1f_0z_0lat_0c │ │ └── cv32e40p_config_pkg.sv │ ├── config_1p_1f_0z_1lat_0c │ │ └── cv32e40p_config_pkg.sv │ ├── config_1p_1f_0z_2lat_0c │ │ └── cv32e40p_config_pkg.sv │ ├── config_1p_1f_1z_0lat_0c │ │ └── cv32e40p_config_pkg.sv │ ├── config_1p_1f_1z_1lat_0c │ │ └── cv32e40p_config_pkg.sv │ ├── config_1p_1f_1z_2lat_0c │ │ └── cv32e40p_config_pkg.sv │ ├── config_1p_1f_1z_2lat_1c │ │ └── cv32e40p_config_pkg.sv │ ├── autocheck_common_rules.do │ ├── README.md │ ├── lint.sh │ └── proc_dumpAutoCheckSummary.tcl ├── slec │ ├── tb_src │ │ ├── cv32e40p_tb_src.flist │ │ ├── cv32e40p_bind2.sv │ │ ├── data_assert2.sv │ │ └── insn_assert2.sv │ ├── siemens │ │ └── Makefile │ └── cadence │ │ ├── sec.tcl │ │ └── lec.tcl ├── formal │ ├── fpv.tcl │ ├── README.md │ ├── cv32e40p_formal.flist │ ├── formal.do │ ├── src │ │ ├── interrupt_assert.sv │ │ ├── debug_assert.sv │ │ ├── fpnew_divsqrt_th_32_assert.sv │ │ └── cv32e40p_ID_assert.sv │ └── Makefile └── riscv_isa_formal │ ├── verif │ ├── cv32e40p │ │ ├── info.txt │ │ └── setup_mv.tcl │ ├── t.sh │ └── core_checker.sv │ ├── Makefile │ ├── README.md │ └── launch_command_example ├── python-requirements.txt ├── .gitlab-ci.yml ├── example_tb ├── core │ ├── .gitignore │ ├── mem_stall │ │ ├── mem_stall.h │ │ └── mem_stall.c │ ├── vsim.tcl │ ├── custom_fp │ │ └── matmulNxN.c │ ├── custom │ │ ├── hello_world.c │ │ └── crt0.S │ ├── .clang-format │ ├── hwlp_test │ │ └── hwlp_test.c │ ├── software.tcl │ ├── firmware │ │ └── stats.c │ ├── include │ │ └── perturbation_pkg.sv │ ├── README.md │ └── interrupt │ │ └── isr.h └── README.md ├── .gitignore ├── rtl ├── vendor │ ├── pulp_platform_fpnew.lock.hjson │ ├── pulp_platform_common_cells.lock.hjson │ ├── pulp_platform_fpnew │ │ ├── README.license.md │ │ └── vendor │ │ │ └── opene906 │ │ │ └── E906_RTL_FACTORY │ │ │ └── gen_rtl │ │ │ └── clk │ │ │ └── rtl │ │ │ └── gated_clk_cell.v │ ├── pulp_platform_common_cells.vendor.hjson │ ├── pulp_platform_fpnew.vendor.hjson │ └── pulp_platform_common_cells │ │ └── src │ │ ├── unread.sv │ │ ├── binary_to_gray.sv │ │ ├── gray_to_binary.sv │ │ ├── stream_filter.sv │ │ ├── edge_propagator_rx.sv │ │ ├── cb_filter_pkg.sv │ │ ├── rstgen.sv │ │ ├── sync.sv │ │ ├── deprecated │ │ ├── pulp_sync.sv │ │ ├── pulp_sync_wedge.sv │ │ ├── sram.sv │ │ ├── generic_LFSR_8bit.sv │ │ └── rrarbiter.sv │ │ ├── edge_detect.sv │ │ ├── edge_propagator_tx.sv │ │ ├── ecc_pkg.sv │ │ ├── stream_demux.sv │ │ ├── onehot_to_bin.sv │ │ ├── stream_intf.sv │ │ ├── counter.sv │ │ ├── clk_div.sv │ │ ├── edge_propagator.sv │ │ ├── sync_wedge.sv │ │ ├── mv_filter.sv │ │ ├── stream_mux.sv │ │ ├── stream_join.sv │ │ ├── serial_deglitch.sv │ │ ├── shift_reg.sv │ │ ├── lfsr_8bit.sv │ │ ├── rstgen_bypass.sv │ │ ├── stream_arbiter.sv │ │ ├── lfsr_16bit.sv │ │ ├── stream_register.sv │ │ ├── fall_through_register.sv │ │ ├── popcount.sv │ │ ├── max_counter.sv │ │ ├── stream_fifo.sv │ │ └── cf_math_pkg.sv ├── include │ └── cv32e40p_apu_core_pkg.sv └── cv32e40p_popcnt.sv ├── .dir-locals.el ├── util ├── format-verible └── git-diff.py ├── .readthedocs.yaml ├── ci ├── make-tmp.sh ├── install-verilator.sh ├── download-pulp-gcc.sh ├── build-riscv-gcc.sh ├── veri-run-openocd-compliance.sh ├── get-openocd.sh ├── run-openocd-compliance.sh ├── Jenkinsfile ├── rv32tests-to-junit.py └── openocd-to-junit.py ├── bhv └── cv32e40p_sim_clock_gate.sv ├── CITATION.cff ├── Bender.yml ├── CONTRIBUTING.md └── cv32e40p_manifest.flist /docs/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | 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-------------------------------------------------------------------------------- /python-requirements.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2021 OpenHW Group 2 | # Solderpad Hardware License, Version 2.1, see LICENSE.md for details. 3 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 4 | 5 | gitpython 6 | 7 | -------------------------------------------------------------------------------- /scripts/slec/tb_src/cv32e40p_tb_src.flist: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Cirrus Logic 2 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | ${TB_SRC_DIR}/insn_assert2.sv 4 | ${TB_SRC_DIR}/data_assert2.sv 5 | ${TB_SRC_DIR}/cv32e40p_bind2.sv 6 | -------------------------------------------------------------------------------- /.github/release.yml: -------------------------------------------------------------------------------- 1 | # .github/release.yml 2 | 3 | changelog: 4 | exclude: 5 | labels: 6 | - ignore-for-release 7 | categories: 8 | - title: Documentation Changes 9 | labels: 10 | - Component:Doc 11 | -------------------------------------------------------------------------------- /docs/source/_static/css/custom.css: -------------------------------------------------------------------------------- 1 | .no-scrollbar-table td { 2 | white-space: normal !important; 3 | } 4 | .wy-side-nav-search>div.version { 5 | color:black 6 | } 7 | .wy-side-nav-search>a.icon.icon-home { 8 | color:black 9 | } 10 | -------------------------------------------------------------------------------- /scripts/lint/qverify_analysis.do: -------------------------------------------------------------------------------- 1 | set top cv32e40p_wrapper 2 | source ../../autocheck_common_rules.do 3 | source ../../formal_lint_rules.do 4 | autocheck report inconclusives 5 | autocheck compile -work design_lib -d cv32e40p_wrapper -L design_lib -L work 6 | autocheck verify -jobs 1 7 | exit 8 | 9 | -------------------------------------------------------------------------------- /.gitlab-ci.yml: -------------------------------------------------------------------------------- 1 | dummy_test_to_trigger_pulpino_ci: 2 | stage: test 3 | script: 4 | - ci/dummy.csh 5 | 6 | trigger_build: 7 | stage: deploy 8 | script: 9 | - "curl -X POST -F token=d80b010cbbb5f0143e0aed386e3202 -F ref=master https://iis-git.ee.ethz.ch/api/v4/projects/72/trigger/pipeline" 10 | -------------------------------------------------------------------------------- /example_tb/core/.gitignore: -------------------------------------------------------------------------------- 1 | csmith/platform.info 2 | csmith/test.c 3 | csmith/test.elf 4 | csmith/test_ref 5 | csmith/output_ref.txt 6 | csmith/output_sim.txt 7 | platform.info 8 | memory_dump.bin 9 | riscv-fesvr 10 | riscv-isa-sim 11 | modelsim.ini 12 | DVEfiles 13 | csrc 14 | inter.vpd 15 | ucli.key 16 | vc_hdrs.h 17 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | TAGS 2 | *.swp 3 | *~ 4 | *.o 5 | *.log 6 | *.vcd 7 | *.xml 8 | *.dbg 9 | *.wlf 10 | *.elf 11 | *.hex 12 | *.map 13 | *.out 14 | *.json 15 | .build-rtl 16 | .lib-rtl 17 | .opt-rtl 18 | /build 19 | /Bender.lock 20 | /Bender.local 21 | golden_reference_design 22 | ref_design 23 | golden.src 24 | revised.src 25 | cadence_conformal 26 | synopsys_formality 27 | questa_autocheck 28 | reports 29 | -------------------------------------------------------------------------------- /example_tb/README.md: -------------------------------------------------------------------------------- 1 | ## Example Testbench 2 | 3 | This directory supports a minimalist verilog testbench intended to support 4 | sanity level testing of the CV32E40P core. The complete verification 5 | environment for the CV32E40P is _not_ in this Repository. Please refer to the 6 | [README](https://github.com/openhwgroup/cv32e40p/edit/master/README.md) at the 7 | top of this repo for more information. 8 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_fpnew.lock.hjson: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // This file is generated by the util/vendor script. Please do not modify it 6 | // manually. 7 | 8 | { 9 | upstream: 10 | { 11 | url: https://github.com/pulp-platform/fpnew.git 12 | rev: 79e453139072df42c9ec8f697132ba485d74e23d 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /scripts/lint/formal_lint_rules.do: -------------------------------------------------------------------------------- 1 | # define all clocks 2 | netlist clock clk_i -period 100 -waveform 0 50 3 | 4 | # define all reset 5 | netlist reset rst_ni -active_low -async 6 | 7 | # define clock domain for reset 8 | netlist port domain rst_ni -clock clk_i 9 | 10 | # define special case 11 | netlist constant scan_cg_en_i 1'b0 12 | netlist constant pulp_clock_en_i 1'b0 13 | 14 | # disable rules 15 | autocheck disable -type FSM_DEADLOCK_STATE FSM_LOCKOUT_STATE 16 | 17 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells.lock.hjson: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // This file is generated by the util/vendor script. Please do not modify it 6 | // manually. 7 | 8 | { 9 | upstream: 10 | { 11 | url: https://github.com/pulp-platform/common_cells.git 12 | rev: 6aeee85d0a34fedc06c14f04fd6363c9f7b4eeea 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /.dir-locals.el: -------------------------------------------------------------------------------- 1 | ;;; Directory Local Variables 2 | ;;; For more information see (info "(emacs) Directory Variables") 3 | 4 | ((nil . ((fill-column . 80))) 5 | (verilog-mode 6 | ;; (verilog-indent-lists quote nil) 7 | ;; (verilog-auto-lineup quote all) 8 | (verilog-cexp-indent . 2) 9 | (verilog-case-indent . 2) 10 | (verilog-indent-level-behavioral . 2) 11 | (verilog-indent-level-declaration . 2) 12 | (verilog-indent-level-module . 2) 13 | (verilog-indent-level . 2))) 14 | 15 | -------------------------------------------------------------------------------- /docs/source/list.issue: -------------------------------------------------------------------------------- 1 | #598 2 | #595 3 | #594 4 | #593 5 | #592 6 | #591 7 | #590 8 | #586 9 | #585 10 | #584 11 | #583 12 | #571 13 | #566 14 | #549 15 | #548 16 | #526 17 | #462 18 | #452 19 | #428 20 | #427 21 | #392 22 | #386 23 | #366 24 | #343 25 | #308 26 | #306 27 | #301 28 | #293 29 | #270 30 | #258 31 | #252 32 | #247 33 | #239 34 | #223 35 | #197 36 | #183 37 | #182 38 | #175 39 | #174 40 | #170 41 | #169 42 | #161 43 | #159 44 | #157 45 | #140 46 | #132 47 | #124 48 | #122 49 | 50 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_fpnew/README.license.md: -------------------------------------------------------------------------------- 1 | # Licensing 2 | 3 | FPnew is released under the *SolderPad Hardware License*, which is a permissive license based on Apache 2.0. Please refer to the [SolderPad license file](LICENSE.solderpad) for further information. 4 | 5 | The T-Head E906 DivSqrt unit, integrated into FPnew in [`vendor/opene906`](vendor/opene906), is reseased under the *Apache License, Version 2.0*. Please refer to the [Apache 2.0 license file](LICENSE.apache) for further information. 6 | -------------------------------------------------------------------------------- /scripts/formal/fpv.tcl: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Cirrus Logic 2 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | 4 | set DESIGN_RTL_DIR ../../rtl 5 | 6 | analyze -sv -f ../../cv32e40p_fpu_manifest.flist 7 | analyze -sva -f cv32e40p_formal.flist 8 | 9 | elaborate -top cv32e40p_formal_top 10 | 11 | #Set up clocks and reset 12 | clock clk_i 13 | reset ~rst_ni 14 | 15 | # Get design information to check general complexity 16 | get_design_info 17 | 18 | #Prove properties 19 | prove -all 20 | 21 | #Report proof results 22 | report 23 | 24 | -------------------------------------------------------------------------------- /util/format-verible: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Copyright 2021 OpenHW Group 3 | # Solderpad Hardware License, Version 2.1, see LICENSE.md for details. 4 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 5 | 6 | set -e 7 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 8 | 9 | if command -v verible-verilog-format &> /dev/null 10 | then 11 | find rtl/ bhv/ -not -path "*rtl/vendor*" \ 12 | -name '*.sv' | \ 13 | xargs verible-verilog-format --inplace 2> /dev/zero 14 | else 15 | echo "verible-verilog-format not available!" 16 | fi 17 | -------------------------------------------------------------------------------- /.github/workflows/check_target_on_pr.yml: -------------------------------------------------------------------------------- 1 | name: check_target 2 | on: [push, pull_request] 3 | 4 | jobs: 5 | check_target: 6 | runs-on: ubuntu-latest 7 | steps: 8 | - if: ${{ (github.event.pull_request.head.ref == 'dev' && github.event.pull_request.base.ref == 'master') || github.event.pull_request.base.ref == 'dev' || github.event.push.ref != 'refs/heads/master'}} 9 | run: exit 0 10 | - if: ${{ github.event.pull_request.base.ref != 'dev' || github.event.push.ref == 'refs/heads/master'}} 11 | run: exit 1 12 | -------------------------------------------------------------------------------- /scripts/lint/config_0p_0f_0z_0lat_0c/cv32e40p_config_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef CV32E40P_CONFIG_PKG 2 | `define CV32E40P_CONFIG_PKG 3 | 4 | package cv32e40p_config_pkg; 5 | 6 | parameter bit COREV_PULP = 0; 7 | parameter bit COREV_CLUSTER = 0; 8 | parameter bit FPU = 0; 9 | parameter int FPU_ADDMUL_LAT = 0; 10 | parameter int FPU_OTHERS_LAT = 0; 11 | parameter bit ZFINX = 0; 12 | parameter int INSTR_ADDR_MEM_WIDTH = 13; 13 | parameter int DATA_ADDR_MEM_WIDTH = 13; 14 | 15 | endpackage 16 | 17 | `endif 18 | 19 | 20 | -------------------------------------------------------------------------------- /scripts/lint/config_1p_0f_0z_0lat_0c/cv32e40p_config_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef CV32E40P_CONFIG_PKG 2 | `define CV32E40P_CONFIG_PKG 3 | 4 | package cv32e40p_config_pkg; 5 | 6 | parameter bit COREV_PULP = 1; 7 | parameter bit COREV_CLUSTER = 0; 8 | parameter bit FPU = 0; 9 | parameter int FPU_ADDMUL_LAT = 0; 10 | parameter int FPU_OTHERS_LAT = 0; 11 | parameter bit ZFINX = 0; 12 | parameter int INSTR_ADDR_MEM_WIDTH = 13; 13 | parameter int DATA_ADDR_MEM_WIDTH = 13; 14 | 15 | endpackage 16 | 17 | `endif 18 | 19 | 20 | -------------------------------------------------------------------------------- /scripts/lint/config_1p_1f_0z_0lat_0c/cv32e40p_config_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef CV32E40P_CONFIG_PKG 2 | `define CV32E40P_CONFIG_PKG 3 | 4 | package cv32e40p_config_pkg; 5 | 6 | parameter bit COREV_PULP = 1; 7 | parameter bit COREV_CLUSTER = 0; 8 | parameter bit FPU = 1; 9 | parameter int FPU_ADDMUL_LAT = 0; 10 | parameter int FPU_OTHERS_LAT = 0; 11 | parameter bit ZFINX = 0; 12 | parameter int INSTR_ADDR_MEM_WIDTH = 13; 13 | parameter int DATA_ADDR_MEM_WIDTH = 13; 14 | 15 | endpackage 16 | 17 | `endif 18 | 19 | 20 | -------------------------------------------------------------------------------- /scripts/lint/config_1p_1f_0z_1lat_0c/cv32e40p_config_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef CV32E40P_CONFIG_PKG 2 | `define CV32E40P_CONFIG_PKG 3 | 4 | package cv32e40p_config_pkg; 5 | 6 | parameter bit COREV_PULP = 1; 7 | parameter bit COREV_CLUSTER = 0; 8 | parameter bit FPU = 1; 9 | parameter int FPU_ADDMUL_LAT = 1; 10 | parameter int FPU_OTHERS_LAT = 1; 11 | parameter bit ZFINX = 0; 12 | parameter int INSTR_ADDR_MEM_WIDTH = 13; 13 | parameter int DATA_ADDR_MEM_WIDTH = 13; 14 | 15 | endpackage 16 | 17 | `endif 18 | 19 | 20 | -------------------------------------------------------------------------------- /scripts/lint/config_1p_1f_0z_2lat_0c/cv32e40p_config_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef CV32E40P_CONFIG_PKG 2 | `define CV32E40P_CONFIG_PKG 3 | 4 | package cv32e40p_config_pkg; 5 | 6 | parameter bit COREV_PULP = 1; 7 | parameter bit COREV_CLUSTER = 0; 8 | parameter bit FPU = 1; 9 | parameter int FPU_ADDMUL_LAT = 2; 10 | parameter int FPU_OTHERS_LAT = 2; 11 | parameter bit ZFINX = 0; 12 | parameter int INSTR_ADDR_MEM_WIDTH = 13; 13 | parameter int DATA_ADDR_MEM_WIDTH = 13; 14 | 15 | endpackage 16 | 17 | `endif 18 | 19 | 20 | -------------------------------------------------------------------------------- /scripts/lint/config_1p_1f_1z_0lat_0c/cv32e40p_config_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef CV32E40P_CONFIG_PKG 2 | `define CV32E40P_CONFIG_PKG 3 | 4 | package cv32e40p_config_pkg; 5 | 6 | parameter bit COREV_PULP = 1; 7 | parameter bit COREV_CLUSTER = 0; 8 | parameter bit FPU = 1; 9 | parameter int FPU_ADDMUL_LAT = 0; 10 | parameter int FPU_OTHERS_LAT = 0; 11 | parameter bit ZFINX = 1; 12 | parameter int INSTR_ADDR_MEM_WIDTH = 13; 13 | parameter int DATA_ADDR_MEM_WIDTH = 13; 14 | 15 | endpackage 16 | 17 | `endif 18 | 19 | 20 | -------------------------------------------------------------------------------- /scripts/lint/config_1p_1f_1z_1lat_0c/cv32e40p_config_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef CV32E40P_CONFIG_PKG 2 | `define CV32E40P_CONFIG_PKG 3 | 4 | package cv32e40p_config_pkg; 5 | 6 | parameter bit COREV_PULP = 1; 7 | parameter bit COREV_CLUSTER = 0; 8 | parameter bit FPU = 1; 9 | parameter int FPU_ADDMUL_LAT = 1; 10 | parameter int FPU_OTHERS_LAT = 1; 11 | parameter bit ZFINX = 1; 12 | parameter int INSTR_ADDR_MEM_WIDTH = 13; 13 | parameter int DATA_ADDR_MEM_WIDTH = 13; 14 | 15 | endpackage 16 | 17 | `endif 18 | 19 | 20 | -------------------------------------------------------------------------------- /scripts/lint/config_1p_1f_1z_2lat_0c/cv32e40p_config_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef CV32E40P_CONFIG_PKG 2 | `define CV32E40P_CONFIG_PKG 3 | 4 | package cv32e40p_config_pkg; 5 | 6 | parameter bit COREV_PULP = 1; 7 | parameter bit COREV_CLUSTER = 0; 8 | parameter bit FPU = 1; 9 | parameter int FPU_ADDMUL_LAT = 2; 10 | parameter int FPU_OTHERS_LAT = 2; 11 | parameter bit ZFINX = 1; 12 | parameter int INSTR_ADDR_MEM_WIDTH = 13; 13 | parameter int DATA_ADDR_MEM_WIDTH = 13; 14 | 15 | endpackage 16 | 17 | `endif 18 | 19 | 20 | -------------------------------------------------------------------------------- /scripts/lint/config_1p_1f_1z_2lat_1c/cv32e40p_config_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef CV32E40P_CONFIG_PKG 2 | `define CV32E40P_CONFIG_PKG 3 | 4 | package cv32e40p_config_pkg; 5 | 6 | parameter bit COREV_PULP = 1; 7 | parameter bit COREV_CLUSTER = 1; 8 | parameter bit FPU = 1; 9 | parameter int FPU_ADDMUL_LAT = 2; 10 | parameter int FPU_OTHERS_LAT = 2; 11 | parameter bit ZFINX = 1; 12 | parameter int INSTR_ADDR_MEM_WIDTH = 13; 13 | parameter int DATA_ADDR_MEM_WIDTH = 13; 14 | 15 | endpackage 16 | 17 | `endif 18 | 19 | 20 | -------------------------------------------------------------------------------- /.readthedocs.yaml: -------------------------------------------------------------------------------- 1 | # Configuration file for ReadTheDocs, used to render the CV32E40P User Manual to 2 | # https://docs.openhwgroup.org/projects/cv32e40p-user-manual 3 | # SPDX-License-Identifier:Apache-2.0 WITH SHL-2.1 4 | 5 | version: 2 6 | 7 | build: 8 | os: "ubuntu-20.04" 9 | tools: 10 | python: "3.9" 11 | 12 | # Build from the docs/source directory with Sphinx 13 | sphinx: 14 | configuration: docs/source/conf.py 15 | 16 | formats: 17 | - htmlzip 18 | - pdf 19 | - epub 20 | 21 | # Explicitly set the Python requirements 22 | python: 23 | install: 24 | - requirements: docs/requirements.txt 25 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/task.md: -------------------------------------------------------------------------------- 1 | # Template for Task Issue 2 | Tasks are defined, assigned and tracked as GitHub Issues. 3 | 4 | ## Task Title 5 | A clear and concise description of the Task. This can go in the title bar. 6 | 7 | ### Task Outcome 8 | Provide a brief description of what is expected. If necessary point to a specification document. 9 | 10 | ### Background information 11 | If necessary point to a specification in an outside document. 12 | 13 | ### Completion Criteria 14 | Answer the question: how does the Assignee know they are done? 15 | 16 | ### Additional context 17 | Add any other context about the task here. 18 | -------------------------------------------------------------------------------- /scripts/lint/autocheck_common_rules.do: -------------------------------------------------------------------------------- 1 | autocheck enable 2 | autocheck disable -type ARITH_OVERFLOW_SUB 3 | autocheck disable -type ARITH_OVERFLOW_VAL 4 | autocheck disable -type CASE_DEFAULT 5 | autocheck disable -type DECLARATION_UNUSED_UNDRIVEN 6 | autocheck disable -type FUNCTION_INCOMPLETE_ASSIGN 7 | autocheck disable -type INDEX_UNREACHABLE 8 | autocheck disable -type INIT_X_OPTIMISM 9 | autocheck disable -type INIT_X_PESSIMISM 10 | autocheck disable -type INIT_X_UNRESOLVED 11 | autocheck disable -type INIT_X_UNRESOLVED_MEM 12 | autocheck disable -type REG_RACE 13 | autocheck disable -type REG_STUCK_AT 14 | configure message severity fatal -id elaboration-835 15 | -------------------------------------------------------------------------------- /ci/make-tmp.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright 2020 ETH Zurich 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | 17 | set -e 18 | cd "$(dirname "${BASH_SOURCE[0]}")/.." 19 | [ -d tmp ] || rm -rf tmp 20 | mkdir -p tmp 21 | -------------------------------------------------------------------------------- /.github/workflows/merge_dev_to_master.yml: -------------------------------------------------------------------------------- 1 | name: Merge dev to master 2 | 3 | on: 4 | workflow_run: 5 | workflows: [aws] 6 | types: 7 | - completed 8 | 9 | jobs: 10 | pull_request: 11 | if: github.event.workflow_run.conclusion == 'success' 12 | runs-on: ubuntu-latest 13 | steps: 14 | - uses: actions/checkout@v2 15 | - name: pull-request 16 | uses: repo-sync/pull-request@v2 17 | with: 18 | source_branch: "dev" 19 | destination_branch: "master" 20 | pr_title: "Automatic PR dev->master" 21 | pr_body: "AWS tests passed. `dev` branch can be merged to `master`." 22 | pr_reviewer: "davideschiavone" 23 | pr_allow_empty: true 24 | github_token: ${{ secrets.GITHUB_TOKEN }} 25 | -------------------------------------------------------------------------------- /example_tb/core/mem_stall/mem_stall.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 ETH Zurich 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | * 16 | */ 17 | 18 | // Header file for the memory stalls support 19 | void activate_random_stall(void); 20 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells.vendor.hjson: -------------------------------------------------------------------------------- 1 | // Copyright 2022 OpenHW Group 2 | // Solderpad Hardware License, Version 2.1, see LICENSE.md for details. 3 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 4 | { 5 | name: "pulp_platform_common_cells", 6 | target_dir: "pulp_platform_common_cells", 7 | 8 | upstream: { 9 | url: "https://github.com/pulp-platform/common_cells.git", 10 | rev: "6aeee85d0a34fedc06c14f04fd6363c9f7b4eeea", 11 | }, 12 | 13 | exclude_from_upstream: [ 14 | ".github", 15 | ".gitignore", 16 | ".gitlab-ci.yml", 17 | ".travis.yml", 18 | "ci/", 19 | "Bender.yml", 20 | "CHANGELOG.md", 21 | "LICENSE", 22 | "Makefile", 23 | "README.md", 24 | "ci", 25 | "formal", 26 | "ips_list.yml", 27 | "lint", 28 | "src_files.yml", 29 | "test" 30 | ] 31 | 32 | } 33 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/config.yml: -------------------------------------------------------------------------------- 1 | blank_issues_enabled: false 2 | contact_links: 3 | - name: Bug 4 | url: https://github.com/openhwgroup/cv32e40p/issues/new?template=bug.md 5 | about: For bugs in the RTL, Documentation, Verification environment or Tool and Build system. 6 | labels: "Type:Bug" 7 | - name: Task 8 | url: https://github.com/openhwgroup/cv32e40p/issues/new?template=task.md 9 | about: For any task except bug fixes. 10 | labels: "Type:Task" 11 | - name: Question 12 | url: https://github.com/openhwgroup/cv32e40p/issues/new?template=question.md 13 | about: For general questions. 14 | labels: "Type:Question" 15 | - name: Enhancement 16 | url: https://github.com/openhwgroup/cv32e40p/issues/new?template=enhancement.md 17 | about: For feature requests and enhancements. 18 | labels: "Type:Enhancement" 19 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_fpnew.vendor.hjson: -------------------------------------------------------------------------------- 1 | // Copyright 2022 OpenHW Group 2 | // Solderpad Hardware License, Version 2.1, see LICENSE.md for details. 3 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 4 | { 5 | name: "pulp_platform_fpnew", 6 | target_dir: "pulp_platform_fpnew", 7 | 8 | upstream: { 9 | url: "https://github.com/pulp-platform/fpnew.git", 10 | rev: "79e453139072df42c9ec8f697132ba485d74e23d", 11 | }, 12 | 13 | exclude_from_upstream: [ 14 | ".gitignore", 15 | ".gitmodules", 16 | "CITATION.cff", 17 | "README.md", 18 | "Bender.yml", 19 | "src/common_cells", 20 | "src/fpu_div_sqrt_mvp", 21 | "tb", 22 | "ips_list.yml", 23 | "src_files.yml" 24 | "docs" 25 | "util" 26 | "vendor/opene906.lock.hjson" 27 | "vendor/opene906.vendor.hjson" 28 | "vendor/opene906/README.md" 29 | "vendor/patches" 30 | ] 31 | } 32 | -------------------------------------------------------------------------------- /scripts/riscv_isa_formal/verif/cv32e40p/info.txt: -------------------------------------------------------------------------------- 1 | # Copyright 2024 Siemens 2 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | # 4 | # Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | # you may not use this file except in compliance with the License, or, 6 | # at your option, the Apache License version 2.0. 7 | # You may obtain a copy of the License at 8 | # 9 | # https://solderpad.org/licenses/SHL-2.1/ 10 | # 11 | # Unless required by applicable law or agreed to in writing, any work 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | 17 | github clone from https://github.com/openhwgroup/cv32e40p.git on the 24th of Jun 2024, tag cv32e40p_v1.8.0 is selected. 18 | -------------------------------------------------------------------------------- /example_tb/core/vsim.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2018 ETH Zurich and University of Bologna. 2 | # Copyright and related rights are licensed under the Solderpad Hardware 3 | # License, Version 0.51 (the "License"); you may not use this file except in 4 | # compliance with the License. You may obtain a copy of the License at 5 | # http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | # or agreed to in writing, software, hardware and materials distributed under 7 | # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | # CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | # specific language governing permissions and limitations under the License. 10 | 11 | # Author: Robert Balas (balasr@student.ethz.ch) 12 | # Description: TCL scripts to facilitate simulations 13 | 14 | set NoQuitOnFinish 1 15 | source software.tcl 16 | source waves.tcl 17 | run -all 18 | -------------------------------------------------------------------------------- /docs/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | pushd %~dp0 4 | 5 | REM Command file for Sphinx documentation 6 | 7 | if "%SPHINXBUILD%" == "" ( 8 | set SPHINXBUILD=sphinx-build 9 | ) 10 | set SOURCEDIR=source 11 | set BUILDDIR=build 12 | 13 | if "%1" == "" goto help 14 | 15 | %SPHINXBUILD% >NUL 2>NUL 16 | if errorlevel 9009 ( 17 | echo. 18 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 19 | echo.installed, then set the SPHINXBUILD environment variable to point 20 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 21 | echo.may add the Sphinx directory to PATH. 22 | echo. 23 | echo.If you don't have Sphinx installed, grab it from 24 | echo.http://sphinx-doc.org/ 25 | exit /b 1 26 | ) 27 | 28 | %SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% 29 | goto end 30 | 31 | :help 32 | %SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% 33 | 34 | :end 35 | popd 36 | -------------------------------------------------------------------------------- /ci/install-verilator.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 4 | cd $ROOT/tmp 5 | 6 | if [ -z ${NUM_JOBS} ]; then 7 | NUM_JOBS=1 8 | fi 9 | 10 | if [ ! -e "$VERILATOR_ROOT/bin/verilator" ]; then 11 | echo "Installing Verilator" 12 | rm -f verilator*.tgz 13 | wget https://www.veripool.org/ftp/verilator-4.018.tgz 14 | tar xzf verilator*.tgz 15 | rm -f verilator*.tgz 16 | cd verilator-4.018 17 | mkdir -p $VERILATOR_ROOT 18 | # copy scripts 19 | autoconf && ./configure --prefix="$VERILATOR_ROOT" && make -j${NUM_JOBS} 20 | make install 21 | # not obvious to me why these symlinks are missing 22 | ln -s $VERILATOR_ROOT/share/verilator/include $VERILATOR_ROOT/include 23 | ln -s $VERILATOR_ROOT/share/verilator/bin/verilator_includer \ 24 | $VERILATOR_ROOT/bin/verilator_includer 25 | make test 26 | else 27 | echo "Using Verilator from cached directory." 28 | fi 29 | -------------------------------------------------------------------------------- /docs/source/preface.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright 2024 OpenHW Group and Dolphin Design 3 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 4 | 5 | Licensed under the Solderpad Hardware License v 2.1 (the "License"); 6 | you may not use this file except in compliance with the License, or, 7 | at your option, the Apache License version 2.0. 8 | You may obtain a copy of the License at 9 | 10 | https://solderpad.org/licenses/SHL-2.1/ 11 | 12 | Unless required by applicable law or agreed to in writing, any work 13 | distributed under the License is distributed on an "AS IS" BASIS, 14 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | See the License for the specific language governing permissions and 16 | limitations under the License. 17 | 18 | Changelog 19 | ========= 20 | 21 | .. changelog:: 22 | :changelog-url: https://cv32e40p-user-manual.readthedocs.io/en/stable/#changelog 23 | :github: https://github.com/openhwgroup/cv32e40p/releases/ 24 | 25 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/unread.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Author: Florian Zaruba, ETH Zurich 12 | // Date: 29.10.2018 13 | // Description: Dummy circuit to mitigate Open Pin warnings 14 | 15 | /* verilator lint_off UNUSED */ 16 | module unread ( 17 | input logic d_i 18 | ); 19 | 20 | endmodule 21 | /* verilator lint_on UNUSED */ 22 | -------------------------------------------------------------------------------- /example_tb/core/custom_fp/matmulNxN.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 ETH Zurich 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | * 16 | */ 17 | 18 | void matmulNxN(float* matA, float* matB , float* matC, int N) 19 | { 20 | float tot; 21 | for (int i = 0; i < N; ++i) { 22 | for (int j = 0; j < N; ++j) { 23 | tot = 0; 24 | for (int k = 0; k < N; ++k) { 25 | tot = tot + matA[i*N+k] * matB[k*N+j]; 26 | } 27 | matC[i*N+j] = tot; 28 | } 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/binary_to_gray.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // Fabian Schuiki 13 | 14 | /// A binary to gray code converter. 15 | module binary_to_gray #( 16 | parameter int N = -1 17 | )( 18 | input logic [N-1:0] A, 19 | output logic [N-1:0] Z 20 | ); 21 | assign Z = A ^ (A >> 1); 22 | endmodule 23 | -------------------------------------------------------------------------------- /scripts/riscv_isa_formal/verif/cv32e40p/setup_mv.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2024 Siemens 2 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | # 4 | # Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | # you may not use this file except in compliance with the License, or, 6 | # at your option, the Apache License version 2.0. 7 | # You may obtain a copy of the License at 8 | # 9 | # https://solderpad.org/licenses/SHL-2.1/ 10 | # 11 | # Unless required by applicable law or agreed to in writing, any work 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | 17 | if {![info exists ::env(DESIGN_RTL_DIR)]} { 18 | set ::env(DESIGN_RTL_DIR) [pwd]/rtl 19 | } 20 | set_read_hdl_option -verilog_version sv2012 -pragma_ignore {translate_} 21 | vlog -sv -f cv32e40p_fpu_manifest.flist 22 | elaborate 23 | compile 24 | set_mode mv 25 | -------------------------------------------------------------------------------- /example_tb/core/custom/hello_world.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 ETH Zurich 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | * 16 | * Author: Robert Balas 17 | */ 18 | 19 | #include 20 | #include 21 | 22 | #include "mem_stall.h" 23 | 24 | int main(int argc, char *argv[]) 25 | { 26 | #ifdef RANDOM_MEM_STALL 27 | activate_random_stall(); 28 | #endif 29 | /* write something to stdout */ 30 | printf("hello world!\n"); 31 | return EXIT_SUCCESS; 32 | } 33 | -------------------------------------------------------------------------------- /util/git-diff.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # Copyright 2020 ETH Zurich and University of Bologna. 3 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 4 | # SPDX-License-Identifier: Apache-2.0 5 | import argparse 6 | from git import Repo 7 | 8 | 9 | def main(): 10 | repo = Repo(search_parent_directories=True) 11 | 12 | parser = argparse.ArgumentParser( 13 | description='Check for changes in repository') 14 | parser.add_argument('--error-msg', 15 | default='::error Files differ.', 16 | required=False, 17 | help='custom exit code string') 18 | args = parser.parse_args() 19 | 20 | diff_to_head = repo.head.commit.diff(None) 21 | 22 | # diff tree against working tree 23 | for diff in diff_to_head: 24 | print("::error file={}::Files differ ({})".format( 25 | diff.b_path, diff.change_type)) 26 | if len(diff_to_head) > 0: 27 | print(args.error_msg) 28 | exit(1) 29 | 30 | 31 | if __name__ == '__main__': 32 | main() -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/gray_to_binary.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // Fabian Schuiki 13 | 14 | /// A gray code to binary converter. 15 | module gray_to_binary #( 16 | parameter int N = -1 17 | )( 18 | input logic [N-1:0] A, 19 | output logic [N-1:0] Z 20 | ); 21 | for (genvar i = 0; i < N; i++) 22 | assign Z[i] = ^A[N-1:i]; 23 | endmodule 24 | -------------------------------------------------------------------------------- /example_tb/core/.clang-format: -------------------------------------------------------------------------------- 1 | --- 2 | BasedOnStyle: LLVM 3 | IndentWidth: 4 4 | UseTab: Never 5 | BreakBeforeBraces: Linux 6 | AlwaysBreakBeforeMultilineStrings: true 7 | AllowShortIfStatementsOnASingleLine: false 8 | AllowShortLoopsOnASingleLine: false 9 | AllowShortFunctionsOnASingleLine: false 10 | IndentCaseLabels: false 11 | AlignEscapedNewlinesLeft: false 12 | AlignTrailingComments: true 13 | AlignOperands: true 14 | AllowAllParametersOfDeclarationOnNextLine: false 15 | AlignAfterOpenBracket: true 16 | SpaceAfterCStyleCast: false 17 | MaxEmptyLinesToKeep: 2 18 | BreakBeforeBinaryOperators: NonAssignment 19 | BreakStringLiterals: false 20 | SortIncludes: false 21 | ContinuationIndentWidth: 4 22 | ColumnLimit: 80 23 | IndentPPDirectives: AfterHash 24 | BinPackArguments: true 25 | BinPackParameters: true 26 | ForEachMacros: 27 | - 'TAILQ_FOREACH' 28 | - 'TAILQ_FOREACH_REVERSE' 29 | BreakBeforeBinaryOperators: None 30 | MaxEmptyLinesToKeep: 1 31 | AlwaysBreakAfterDefinitionReturnType: None 32 | AlwaysBreakAfterReturnType: None 33 | AlwaysBreakBeforeMultilineStrings: false 34 | AlignConsecutiveAssignments: true 35 | ... 36 | -------------------------------------------------------------------------------- /scripts/riscv_isa_formal/verif/t.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # 3 | # Copyright 2024 Siemens 4 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 5 | # 6 | # Licensed under the Solderpad Hardware License v 2.1 (the "License"); 7 | # you may not use this file except in compliance with the License, or, 8 | # at your option, the Apache License version 2.0. 9 | # You may obtain a copy of the License at 10 | # 11 | # https://solderpad.org/licenses/SHL-2.1/ 12 | # 13 | # Unless required by applicable law or agreed to in writing, any work 14 | # distributed under the License is distributed on an "AS IS" BASIS, 15 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 | # See the License for the specific language governing permissions and 17 | # limitations under the License. 18 | 19 | # This script is a template representing a customization to integrate OneSpin 360 with VCS simulator 20 | # 21 | # onespin calls the script as follows: 22 | # template_vcs_flow.sh 23 | # 24 | # In this script you need to set up the environment for the simulator, 25 | # 26 | ARG1=$1 27 | 28 | vsim -64 -c -do "source ${ARG1}; quit -f" 29 | -------------------------------------------------------------------------------- /ci/download-pulp-gcc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright 2020 ETH Zurich 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | # 17 | # Author: Robert Balas 18 | 19 | set -o pipefail 20 | set -e 21 | 22 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 23 | VERSION="v1.0.16" 24 | 25 | # mkdir -p $RISCV 26 | 27 | wget https://github.com/pulp-platform/pulp-riscv-gnu-toolchain/releases/download/$VERSION/$VERSION-pulp-riscv-gcc-ubuntu-16.tar.bz2 28 | echo "unpacking pulp gcc" 29 | tar -xvf $VERSION-pulp-riscv-gcc-ubuntu-16.tar.bz2 30 | echo "moving pulp gcc to $RISCV" 31 | mv $VERSION-pulp-riscv-gcc-ubuntu-16.tar.bz2 "$RISCV" 32 | -------------------------------------------------------------------------------- /.github/workflows/aws.yml: -------------------------------------------------------------------------------- 1 | name: aws 2 | on: 3 | push: 4 | branches: 5 | - 'dev' 6 | 7 | jobs: 8 | aws: 9 | name: AWS Pipeline (private) 10 | if: ${{ (github.actor == 'davideschiavone' || github.actor == 'MikeOpenHWGroup' || github.actor == 'zarubaf') && github.event.label.name != 'Component:Doc' }} 11 | runs-on: ubuntu-latest 12 | # These permissions are needed to interact with GitHub's OIDC Token endpoint. 13 | permissions: 14 | id-token: write 15 | contents: read 16 | steps: 17 | - name: Configure AWS Credentials 18 | uses: aws-actions/configure-aws-credentials@v1 19 | with: 20 | role-to-assume: ${{ secrets.AWS_ROLE_TO_ASSUME }} 21 | aws-region: eu-west-1 22 | - name: Run AWS Pipeline 23 | uses: openhwgroup/aws-codebuild-run-build@master 24 | with: 25 | project-name: cv32e40p 26 | hide-log: true 27 | skip_aws: 28 | name: no AWS 29 | if: ${{ (github.actor == 'davideschiavone' || github.actor == 'MikeOpenHWGroup' || github.actor == 'zarubaf') && github.event.label.name == 'Component:Doc' }} 30 | runs-on: ubuntu-latest 31 | steps: 32 | - name: info 33 | run: echo "Documentation only, skipping LEC on AWS" 34 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/stream_filter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Stream filter: If `drop_i` is `1`, signal `ready` to the upstream regardless of the downstream, 12 | // and do not propagate `valid` downstream. Otherwise, connect upstream to downstream. 13 | module stream_filter ( 14 | input logic valid_i, 15 | output logic ready_o, 16 | 17 | input logic drop_i, 18 | 19 | output logic valid_o, 20 | input logic ready_i 21 | ); 22 | 23 | assign valid_o = drop_i ? 1'b0 : valid_i; 24 | assign ready_o = drop_i ? 1'b1 : ready_i; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /bhv/cv32e40p_sim_clock_gate.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // !!! cv32e40p_sim_clock_gate file is meant for simulation only !!! 12 | // !!! It must not be used for ASIC synthesis !!! 13 | // !!! It must not be used for FPGA synthesis !!! 14 | 15 | module cv32e40p_clock_gate ( 16 | input logic clk_i, 17 | input logic en_i, 18 | input logic scan_cg_en_i, 19 | output logic clk_o 20 | ); 21 | 22 | logic clk_en; 23 | 24 | always_latch begin 25 | if (clk_i == 1'b0) clk_en <= en_i | scan_cg_en_i; 26 | end 27 | 28 | assign clk_o = clk_i & clk_en; 29 | 30 | endmodule // cv32e40p_clock_gate 31 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/edge_propagator_rx.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module edge_propagator_rx ( 14 | input logic clk_i, 15 | input logic rstn_i, 16 | input logic valid_i, 17 | output logic ack_o, 18 | output logic valid_o 19 | ); 20 | 21 | pulp_sync_wedge i_sync_clkb ( 22 | .clk_i ( clk_i ), 23 | .rstn_i ( rstn_i ), 24 | .en_i ( 1'b1 ), 25 | .serial_i ( valid_i ), 26 | .r_edge_o ( valid_o ), 27 | .f_edge_o ( ), 28 | .serial_o ( ack_o ) 29 | ); 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /docs/source/index.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright 2024 OpenHW Group and Dolphin Design 3 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 4 | 5 | Licensed under the Solderpad Hardware License v 2.1 (the "License"); 6 | you may not use this file except in compliance with the License, or, 7 | at your option, the Apache License version 2.0. 8 | You may obtain a copy of the License at 9 | 10 | https://solderpad.org/licenses/SHL-2.1/ 11 | 12 | Unless required by applicable law or agreed to in writing, any work 13 | distributed under the License is distributed on an "AS IS" BASIS, 14 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | See the License for the specific language governing permissions and 16 | limitations under the License. 17 | 18 | OpenHW Group CV32E40P User Manual 19 | ================================= 20 | 21 | .. toctree:: 22 | :maxdepth: 3 23 | :caption: Contents: 24 | 25 | preface 26 | intro 27 | integration 28 | fpu 29 | verification 30 | corev_hw_loop 31 | instruction_set_extensions 32 | perf_counters 33 | control_status_registers 34 | exceptions_interrupts 35 | debug 36 | pipeline 37 | instruction_fetch 38 | load_store_unit 39 | register_file 40 | sleep 41 | core_versions 42 | glossary 43 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/cb_filter_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2019 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Wolfgang Roenninger 12 | 13 | /// Package with the struct definition for the seeds and an example. 14 | package cb_filter_pkg; 15 | typedef struct packed { 16 | int unsigned PermuteSeed; 17 | int unsigned XorSeed; 18 | } cb_seed_t; 19 | 20 | // example seeding struct 21 | localparam cb_seed_t [2:0] EgSeeds = '{ 22 | '{PermuteSeed: 32'd299034753, XorSeed: 32'd4094834 }, 23 | '{PermuteSeed: 32'd19921030, XorSeed: 32'd995713 }, 24 | '{PermuteSeed: 32'd294388, XorSeed: 32'd65146511 } 25 | }; 26 | endpackage 27 | -------------------------------------------------------------------------------- /scripts/slec/siemens/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | # Copyright 2006-Mentor Graphics Corporation 3 | # 4 | # THIS SOFTWARE AND RELATED DOCUMENTATION 5 | # ARE PROPRIETARY AND CONFIDENTIAL TO SIEMENS. 6 | # © 2023 Siemens 7 | 8 | INSTALL := $(shell qverify -install_path) 9 | VLIB = $(INSTALL)/modeltech/linux_x86_64/vlib 10 | VMAP = $(INSTALL)/modeltech/linux_x86_64/vmap 11 | VLOG = $(INSTALL)/modeltech/linux_x86_64/vlog 12 | VCOM = $(INSTALL)/modeltech/linux_x86_64/vcom 13 | 14 | run_sec_vl: clean run_sec 15 | 16 | run_sec: 17 | $(VLIB) work_ip_orig 18 | $(VLIB) work_ip_mod 19 | $(VMAP) work_spec work_ip_orig 20 | $(VMAP) work_impl work_ip_mod 21 | $(VLOG) -sv -f $(SPEC_FLIST) -work work_spec 22 | $(VLOG) -sv -f $(IMPL_FLIST) -work work_impl 23 | 24 | qverify -c -od log -do " \ 25 | onerror { exit 1 }; \ 26 | slec configure -spec -d $(TOP_MODULE) -work work_spec; \ 27 | slec configure -impl -d $(TOP_MODULE) -work work_impl; \ 28 | slec compile; \ 29 | slec verify -timeout 10m; \ 30 | exit" 31 | @cp log/slec_verify.log $(SUMMARY_LOG) 32 | 33 | 34 | debug: 35 | qverify log/slec.db 36 | 37 | clean: 38 | qverify_clean 39 | rm -rf log* work* *.rpt modelsim.ini .visualizer visualizer* 40 | 41 | 42 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/rstgen.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Davide Rossi 12 | 13 | module rstgen ( 14 | input logic clk_i, 15 | input logic rst_ni, 16 | input logic test_mode_i, 17 | output logic rst_no, 18 | output logic init_no 19 | ); 20 | 21 | rstgen_bypass i_rstgen_bypass ( 22 | .clk_i ( clk_i ), 23 | .rst_ni ( rst_ni ), 24 | .rst_test_mode_ni ( rst_ni ), 25 | .test_mode_i ( test_mode_i ), 26 | .rst_no ( rst_no ), 27 | .init_no ( init_no ) 28 | ); 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/sync.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module sync #( 14 | parameter int unsigned STAGES = 2 15 | ) ( 16 | input logic clk_i, 17 | input logic rst_ni, 18 | input logic serial_i, 19 | output logic serial_o 20 | ); 21 | 22 | logic [STAGES-1:0] reg_q; 23 | 24 | always_ff @(posedge clk_i, negedge rst_ni) begin 25 | if (!rst_ni) begin 26 | reg_q <= 'h0; 27 | end else begin 28 | reg_q <= {reg_q[STAGES-2:0], serial_i}; 29 | end 30 | end 31 | 32 | assign serial_o = reg_q[STAGES-1]; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/deprecated/pulp_sync.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module pulp_sync 14 | #( 15 | parameter STAGES = 2 16 | ) 17 | ( 18 | input logic clk_i, 19 | input logic rstn_i, 20 | input logic serial_i, 21 | output logic serial_o 22 | ); 23 | 24 | logic [STAGES-1:0] r_reg; 25 | 26 | always_ff @(posedge clk_i, negedge rstn_i) 27 | begin 28 | if(!rstn_i) 29 | r_reg <= 'h0; 30 | else 31 | r_reg <= {r_reg[STAGES-2:0], serial_i}; 32 | end 33 | 34 | assign serial_o = r_reg[STAGES-1]; 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /scripts/riscv_isa_formal/verif/core_checker.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Siemens 2 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | // 4 | // Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | // you may not use this file except in compliance with the License, or, 6 | // at your option, the Apache License version 2.0. 7 | // You may obtain a copy of the License at 8 | // 9 | // https://solderpad.org/licenses/SHL-2.1/ 10 | // 11 | // Unless required by applicable law or agreed to in writing, any work 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | 17 | /////////////////////////////////////////////////////////////////////////////// 18 | // // 19 | // RISC-V Checker // 20 | // // 21 | /////////////////////////////////////////////////////////////////////////////// 22 | 23 | 24 | 25 | 26 | This file is available only to Siemens Questa Processor customers and is available by submitting a request to Siemens support center to get it. 27 | -------------------------------------------------------------------------------- /scripts/formal/README.md: -------------------------------------------------------------------------------- 1 | ## CV32E40P Formal 2 | 3 | This folder contains the source and scripts used in the effort to justify waived code coverage holes using formal tools. 4 | 5 | Disclaimer: This has been developped and tested with Siemens Questa formal and the Makefile only support this tool. Porting to other tools should be straightforward as all source files are standard sva. 6 | 7 | ### Introduction 8 | To assist code coverage analysis we formally proved that some code was in our case unreachable. Each assertion correspond to one coverage holes. We tried to keep the constraints as minimal as possible. The only constraints we are using are: 9 | - OBI protocol constraints on both instructions and data interfaces 10 | - Disabling scan 11 | 12 | 13 | ### How to use 14 | 15 | Inside this folder, with ```vlog``` and ```qverify``` available in your PATH, run one of the following command. 16 | 17 | | Command | Description | 18 | |-----------------|-----------------------------------------------| 19 | |make run | Run default config (no corev_pulp, no FPU) | 20 | |make run_pulp | Run config corev_pulp withou FPU | 21 | |make run_pulp_F0 | Run config corev_pulp with FPU with latency 0 | 22 | |make clean | Remove all temporary file | 23 | 24 | All runs are in batch. At the end of the run, use ```qverify ``` to open the results in GUI. -------------------------------------------------------------------------------- /scripts/lint/README.md: -------------------------------------------------------------------------------- 1 | # RTL source Lint 2 | 3 | This folder contains LINT scripts that runs using SiemensEDA Questa AutoCheck tool. It requires SiemensEDA QuestaSim to first compile the design. 4 | 5 | Those scripts allow to check RTL coding quality using common guidelines and rules. It can find syntax errors or issues leading to bad/incorrect synthesis (like latches in combinational process). 6 | Common practice is to launch LINT check prior to committing RTL sources to git repository. 7 | 8 | As cv32e40p\_top has 5 parameters and to be able to check different parameters values, a new top level module (cv32e40p\_wrapper) has been created together with some predefined configuration packages (in config\_?p\_?f\_?z\_?lat\_??c directories). 9 | 10 | Configuration directory naming style is: 11 | - \_?p : PULP enabled or not (0 or 1) 12 | - \_?f : FPU enabled or not (0 or 1) 13 | - \_?z : ZFINX enabled or not (0 or 1) 14 | - \_?lat : FPU instructions latency (0, 1 or 2) 15 | - \_?c : PULP\_CLUSTER enabled or not (0 or 1) 16 | 17 | ### Running the script 18 | 19 | From a shell, please execute: 20 | 21 | ``` 22 | ./lint.sh 1p_0f_0z_0lat_0c 23 | ``` 24 | 25 | The script uses `../../rtl` as design sources to check. 26 | 27 | Intermediate logs are visible in `questa_autocheck/config_?p_?f_?z_?lat_?c` and `questa_autocheck/config_?p_?f_?z_?lat_?c/formal_lint_out` and final lint report in `questa_autocheck/config_?p_?f_?z_?lat_?c/formal_lint.rpt` 28 | 29 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/edge_detect.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Florian Zaruba 12 | // Description: Edge detector, clock needs to oversample for proper edge detection 13 | 14 | module edge_detect ( 15 | input logic clk_i, // Clock 16 | input logic rst_ni, // Asynchronous reset active low 17 | input logic d_i, // data stream in 18 | output logic re_o, // rising edge detected 19 | output logic fe_o // falling edge detected 20 | ); 21 | 22 | sync_wedge i_sync_wedge ( 23 | .clk_i ( clk_i ), 24 | .rst_ni ( rst_ni ), 25 | .en_i ( 1'b1 ), 26 | .serial_i ( d_i ), 27 | .r_edge_o ( re_o ), 28 | .f_edge_o ( fe_o ), 29 | .serial_o ( ) 30 | ); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /.github/workflows/lint.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2022 OpenHW Group 2 | # Solderpad Hardware License, Version 2.1, see LICENSE.md for details. 3 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 4 | 5 | # Run all lint checks 6 | name: lint 7 | on: [push, pull_request] 8 | 9 | env: 10 | VERIBLE_VERSION: 0.0-1149-g7eae750 11 | 12 | jobs: 13 | ################## 14 | # Verible Fromat # 15 | ################## 16 | format_verilog: 17 | name: Format Verilog Sources 18 | # This job runs on Linux (fixed ubuntu version) 19 | runs-on: ubuntu-20.04 20 | steps: 21 | - uses: actions/checkout@v2 22 | - uses: actions/setup-python@v2 23 | with: 24 | python-version: 3.9 25 | - name: Install requirements 26 | run: pip install -r python-requirements.txt 27 | - name: Install Verible 28 | run: | 29 | set -e 30 | mkdir -p build/verible 31 | cd build/verible 32 | curl -Ls -o verible.tar.gz https://github.com/google/verible/releases/download/v$VERIBLE_VERSION/verible-v$VERIBLE_VERSION-Ubuntu-18.04-bionic-x86_64.tar.gz 33 | sudo mkdir -p /tools/verible && sudo chmod 777 /tools/verible 34 | tar -C /tools/verible -xf verible.tar.gz --strip-components=1 35 | echo "PATH=$PATH:/tools/verible/bin" >> $GITHUB_ENV 36 | - name: Run Format 37 | run: | 38 | util/format-verible 39 | util/git-diff.py --error-msg "::error ::Found differences, run util/format-verible before committing." -------------------------------------------------------------------------------- /docs/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2020 OpenHW Group 3 | # 4 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # https://solderpad.org/licenses/ 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | # 16 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 17 | # 18 | ############################################################################### 19 | # 20 | # Minimal makefile for Sphinx documentation 21 | # 22 | 23 | # You can set these variables from the command line. 24 | SPHINXOPTS = 25 | SPHINXBUILD = sphinx-build 26 | SOURCEDIR = source 27 | BUILDDIR = build 28 | 29 | # Put it first so that "make" without argument is like "make help". 30 | help: 31 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 32 | 33 | .PHONY: help Makefile 34 | 35 | # Catch-all target: route all unknown targets to Sphinx using the new 36 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 37 | %: Makefile 38 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 39 | -------------------------------------------------------------------------------- /example_tb/core/hwlp_test/hwlp_test.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 ETH Zurich 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | * 16 | */ 17 | 18 | #include 19 | #include 20 | #include "mem_stall.h" 21 | #include "hwlp.h" 22 | 23 | int main(int argc, char *argv[]) 24 | { 25 | #ifdef RANDOM_MEM_STALL 26 | activate_random_stall(); 27 | #endif 28 | 29 | asm volatile("ecall" : : : "ra"); 30 | HWLP_TEST0; 31 | asm volatile("ebreak" : : : "ra"); 32 | HWLP_TEST1; 33 | asm volatile("ecall" : : : "ra"); 34 | HWLP_TEST2; 35 | asm volatile("ebreak" : : : "ra"); 36 | asm volatile("fence.i" : : : "ra"); 37 | asm volatile("ebreak" : : : "ra"); 38 | HWLP_TEST3; 39 | asm volatile("ecall" : : : "ra"); 40 | asm volatile("ecall" : : : "ra"); 41 | HWLP_TEST4; 42 | asm volatile("ecall" : : : "ra"); 43 | HWLP_TEST5; 44 | asm volatile("fence.i" : : : "ra"); 45 | HWLP_TEST6; 46 | 47 | return EXIT_SUCCESS; 48 | } 49 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/edge_propagator_tx.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module edge_propagator_tx ( 14 | input logic clk_i, 15 | input logic rstn_i, 16 | input logic valid_i, 17 | input logic ack_i, 18 | output logic valid_o 19 | ); 20 | 21 | logic [1:0] sync_a; 22 | 23 | logic r_input_reg; 24 | logic s_input_reg_next; 25 | 26 | assign s_input_reg_next = valid_i | (r_input_reg & ~sync_a[0]); 27 | 28 | always @(negedge rstn_i or posedge clk_i) begin 29 | if (~rstn_i) begin 30 | r_input_reg <= 1'b0; 31 | sync_a <= 2'b00; 32 | end else begin 33 | r_input_reg <= s_input_reg_next; 34 | sync_a <= {ack_i,sync_a[1]}; 35 | end 36 | end 37 | 38 | assign valid_o = r_input_reg; 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/ecc_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Author: Florian Zaruba 12 | // 13 | /// Contains common ECC definitions and helper functions. 14 | 15 | package ecc_pkg; 16 | 17 | // Calculate required ECC parity width: 18 | function automatic int unsigned get_parity_width (input int unsigned data_width); 19 | // data_width + cw_width + 1 <= 2**cw_width 20 | int unsigned cw_width = 2; 21 | while (unsigned'(2**cw_width) < cw_width + data_width + 1) cw_width++; 22 | return cw_width; 23 | endfunction 24 | 25 | // Calculate required ECC codeword width: 26 | function automatic int unsigned get_cw_width (input int unsigned data_width); 27 | // data width + parity width + one additional parity bit (for double error detection) 28 | return data_width + get_parity_width(data_width); 29 | endfunction 30 | 31 | endpackage 32 | -------------------------------------------------------------------------------- /ci/build-riscv-gcc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright 2020 ETH Zurich 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | 17 | # call with first argument = 0 to checkout only 18 | set -o pipefail 19 | set -e 20 | 21 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 22 | VERSION="a03290eab661e2aa58288ad164f908bbbcc2169c" 23 | 24 | mkdir -p $RISCV 25 | 26 | cd $RISCV 27 | 28 | if [ -z ${NUM_JOBS} ]; then 29 | NUM_JOBS=1 30 | fi 31 | 32 | 33 | if ! [ -e $RISCV/bin ]; then 34 | if ! [ -e $RISCV/riscv-gnu-toolchain ]; then 35 | git clone https://github.com/riscv/riscv-gnu-toolchain.git 36 | fi 37 | 38 | cd riscv-gnu-toolchain 39 | git checkout $VERSION 40 | git submodule update --init --recursive 41 | 42 | if [[ $1 -ne "0" || -z ${1} ]]; then 43 | echo "Compiling RISC-V Toolchain" 44 | ./configure --disable-linux --disable-multilib --disable-gdb --prefix=$RISCV --with-arch=rv32gc --with-abi=ilp32 45 | make -j${NUM_JOBS} | tail 46 | echo "Compilation Finished" 47 | fi 48 | fi 49 | -------------------------------------------------------------------------------- /ci/veri-run-openocd-compliance.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright 2020 ETH Zurich 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | # 17 | # Author: Robert Balas 18 | 19 | set -e 20 | 21 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 22 | 23 | if [ -z "${RISCV}" ] 24 | then 25 | echo "RISCV is empty" 26 | exit 1 27 | fi 28 | 29 | 30 | veri_out=$(mktemp) 31 | openocd_out=openocd.log 32 | 33 | make -C "${ROOT}"/tb/dm veri-run |& tee "${veri_out}"& 34 | # record veri pid/pgid to kill it if it survives this script 35 | veri_pid=$! 36 | veri_pgid=$(ps -o pgid= ${veri_pid} | grep -o [0-9]*) 37 | 38 | # block until we get "Listening on port" so that we are safe to connect openocd 39 | coproc grep -m 1 "Listening on port" 40 | tail -f -n0 "${veri_out}" --pid "$COPROC_PID" >&"${COPROC[1]}" 41 | 42 | echo "Starting openocd" 43 | "${RISCV}"/bin/openocd -f "${ROOT}"/tb/dm/pulpissimo_compliance_test.cfg |& tee "${openocd_out}" 44 | 45 | if grep -q "ALL TESTS PASSED" "${openocd_out}"; then 46 | exit 0 47 | fi 48 | exit 1 49 | 50 | -------------------------------------------------------------------------------- /CITATION.cff: -------------------------------------------------------------------------------- 1 | cff-version: 1.2.0 2 | message: "Please cite core-v-mcu as below." 3 | authors: 4 | - family-names: "Schiavone" 5 | given-names: "Pasquale Davide" 6 | - family-names: "Conti" 7 | given-names: "Francesco" 8 | - family-names: "Rossi" 9 | given-names: "Davide" 10 | - family-names: "Gautschi" 11 | given-names: "Michael" 12 | - family-names: "Pullini" 13 | given-names: "Antonio" 14 | - family-names: "Flamand" 15 | given-names: "Eric" 16 | - family-names: "Benini" 17 | given-names: "Luca" 18 | title: "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications" 19 | doi: 10.1109/PATMOS.2017.8106976 20 | date-released: 2017-11-16 21 | url: "https://ieeexplore.ieee.org/document/8106976" 22 | preferred-citation: 23 | authors: 24 | - family-names: "Gautschi" 25 | given-names: "Michael" 26 | - family-names: "Schiavone" 27 | given-names: "Pasquale Davide" 28 | - family-names: "Traber" 29 | given-names: "Andreas" 30 | - family-names: "Loi" 31 | given-names: "Igor" 32 | - family-names: "Pullini" 33 | given-names: "Antonio" 34 | - family-names: "Rossi" 35 | given-names: "Davide" 36 | - family-names: "Flamand" 37 | given-names: "Eric" 38 | - family-names: "Gurkaynak" 39 | given-names: "Frank" 40 | - family-names: "Benini" 41 | given-names: "Luca" 42 | journal: "IEEE Transactions on Very Large Scale Integration (VLSI) Systems" 43 | title: "Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices" 44 | doi: 10.1109/TVLSI.2017.2654506 45 | date-released: 2017-02-24 46 | url: "https://ieeexplore.ieee.org/document/7864441" 47 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/bug.md: -------------------------------------------------------------------------------- 1 | # Template for Bug Issue 2 | 3 | Please use this template if the issue that you are reporting is a (potential) bug in CV32E40P Documentation, RTL, Verification environment or Tools and Build system. 4 | 5 |
**Note**: Please file bugs related to the CV32E40P User Manual and RTL in https://github.com/openhwgroup/cv32e40p. 6 |
**Note**: Please file bugs related to the core-v-verif verification environment in https://github.com/openhwgroup/core-v-verif instead. 7 |
**Note**: Please file bugs related to the GNU GCC compiler in https://github.com/openhwgroup/corev-gcc instead. 8 |
**Note**: Please file bugs related to the LLVM compiler in https://github.com/openhwgroup/corev-llvm-project instead. 9 |
**Note**: Please file bugs related to the binary utils and gdb in https://github.com/openhwgroup/corev-binutils-gdb instead. 10 | 11 | ## Bug Title 12 | A clear and concise description of what the bug is. 13 | 14 | ### Component 15 | Indicate the component in which you found a problem (and we will add the appropriate label): 16 | 17 | **Component:Doc**: For issues in the Documentation (e.g. for README.md files) 18 | **Component:RTL**: For issues in the RTL (e.g. for files in the rtl directory) 19 | **Component:Verif**: For issues in the verification environment or test cases (e.g. for behavioral code, testbench, C code, etc.) 20 | **Component:Tool-and-build**: For issues in the tool and build flow (e.g. Makefile, FuseSoc, etc.) 21 | 22 | ### Steps to Reproduce 23 | Please provide: 24 | 1. git hash 25 | 2. Command line 26 | 3. Logfile and/or wave-dump info (screen shots can be useful) 27 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_fpnew/vendor/opene906/E906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v: -------------------------------------------------------------------------------- 1 | /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | module gated_clk_cell( 17 | clk_in, 18 | global_en, 19 | module_en, 20 | local_en, 21 | external_en, 22 | pad_yy_icg_scan_en, 23 | clk_out 24 | ); 25 | 26 | input clk_in; 27 | input global_en; 28 | input module_en; 29 | input local_en; 30 | input external_en; 31 | input pad_yy_icg_scan_en; 32 | output clk_out; 33 | 34 | wire clk_en_bf_latch; 35 | wire SE; 36 | 37 | assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ; 38 | 39 | // SE driven from primary input, held constant 40 | assign SE = pad_yy_icg_scan_en; 41 | 42 | // // &Connect( .clk_in (clk_in), @50 43 | // // .SE (SE), @51 44 | // // .external_en (clk_en_bf_latch), @52 45 | // // .clk_out (clk_out) @53 46 | // // ) ; @54 47 | 48 | assign clk_out = clk_in; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /ci/get-openocd.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright 2020 ETH Zurich 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | 17 | set -e 18 | 19 | VERSION="af3a034b57279d2a400d87e7508c9a92254ec165" 20 | 21 | mkdir -p $RISCV/ 22 | cd $RISCV 23 | 24 | check_version() { 25 | $1 --version | awk "NR==1 {if (\$NF>$2) {exit 0} exit 1}" || ( 26 | echo $3 requires at least version $2 of $1. Aborting. 27 | exit 1 28 | ) 29 | } 30 | 31 | 32 | if [ -z ${NUM_JOBS} ]; then 33 | NUM_JOBS=1 34 | fi 35 | 36 | if ! [ -e $RISCV/bin/openocd ]; then 37 | if ! [ -e $RISCV/riscv-openocd ]; then 38 | git clone https://github.com/riscv/riscv-openocd.git 39 | fi 40 | check_version automake 1.14 "OpenOCD build" 41 | check_version autoconf 2.64 "OpenOCD build" 42 | 43 | cd riscv-openocd 44 | git checkout $VERSION 45 | git submodule update --init --recursive 46 | 47 | echo "Compiling OpenOCD" 48 | ./bootstrap 49 | ./configure --prefix=$RISCV --disable-werror --disable-wextra --enable-remote-bitbang 50 | make -j${NUM_JOBS} 51 | make install 52 | echo "Compilation Finished" 53 | fi 54 | 55 | -------------------------------------------------------------------------------- /scripts/formal/cv32e40p_formal.flist: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Dolphin Design 2 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | // 4 | // Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | // you may not use this file except in compliance with the License, or, 6 | // at your option, the Apache License version 2.0. 7 | // You may obtain a copy of the License at 8 | // 9 | // https://solderpad.org/licenses/SHL-2.1/ 10 | // 11 | // Unless required by applicable law or agreed to in writing, any work 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | 17 | //////////////////////////////////////////////////////////////////////////////////// 18 | // // 19 | // Contributors: Yoann Pruvost, Dolphin Design // 20 | // // 21 | // Description: Filelist for CV32E40P formal code analysis // 22 | // // 23 | //////////////////////////////////////////////////////////////////////////////////// 24 | 25 | +incdir+./src 26 | src/insn_assert.sv 27 | src/data_assert.sv 28 | src/cv32e40p_assert.sv 29 | src/cv32e40p_ID_assert.sv 30 | src/cv32e40p_EX_assert.sv 31 | src/cv32e40p_controller_assert.sv 32 | src/fpnew_divsqrt_th_32_assert.sv 33 | src/cv32e40p_formal_top.sv 34 | src/cv32e40p_bind.sv -------------------------------------------------------------------------------- /scripts/formal/formal.do: -------------------------------------------------------------------------------- 1 | # Copyright 2024 Dolphin Design 2 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | # 4 | # Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | # you may not use this file except in compliance with the License, or, 6 | # at your option, the Apache License version 2.0. 7 | # You may obtain a copy of the License at 8 | # 9 | # https://solderpad.org/licenses/SHL-2.1/ 10 | # 11 | # Unless required by applicable law or agreed to in writing, any work 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | 17 | #////////////////////////////////////////////////////////////////////////////////// 18 | # // 19 | # Contributors: Yoann Pruvost, Dolphin Design // 20 | # // 21 | # Description: Formal script for CV32E40P // 22 | # // 23 | #////////////////////////////////////////////////////////////////////////////////// 24 | 25 | set top cv32e40p_formal_top 26 | 27 | #netlist clock clk_i -period 50 28 | 29 | #netlist constraint rst_ni -value 1'b1 -after_init 30 | 31 | #netlist port domain i_lint_grnt -clock i_clk 32 | 33 | formal compile -d cv32e40p_formal_top -cuname cv32e40p_bind 34 | 35 | formal verify -timeout 100m -jobs 4 -sanity_waveforms 36 | 37 | #exit 38 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/stream_demux.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | /// Connects the input stream (valid-ready) handshake to one of `N_OUP` output stream handshakes. 12 | /// 13 | /// This module has no data ports because stream data does not need to be demultiplexed: the data of 14 | /// the input stream can just be applied at all output streams. 15 | module stream_demux #( 16 | /// Number of connected outputs. 17 | parameter int unsigned N_OUP = 32'd1, 18 | /// Dependent parameters, DO NOT OVERRIDE! 19 | parameter int unsigned LOG_N_OUP = (N_OUP > 32'd1) ? unsigned'($clog2(N_OUP)) : 1'b1 20 | ) ( 21 | input logic inp_valid_i, 22 | output logic inp_ready_o, 23 | 24 | input logic [LOG_N_OUP-1:0] oup_sel_i, 25 | 26 | output logic [N_OUP-1:0] oup_valid_o, 27 | input logic [N_OUP-1:0] oup_ready_i 28 | ); 29 | 30 | always_comb begin 31 | oup_valid_o = '0; 32 | oup_valid_o[oup_sel_i] = inp_valid_i; 33 | end 34 | assign inp_ready_o = oup_ready_i[oup_sel_i]; 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /scripts/slec/cadence/sec.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2021 OpenHW Group 2 | # 3 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # https://solderpad.org/licenses/ 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | set summary_log $::env(summary_log) 15 | set top_module $::env(top_module) 16 | set report_dir $::env(report_dir) 17 | 18 | set_sec_disable_imp_assumption none 19 | 20 | check_sec -setup -spec_top $top_module -imp_top $top_module \ 21 | -spec_analyze "-sv -f ./golden.src"\ 22 | -imp_analyze "-sv -f ./revised.src"\ 23 | -spec_elaborate_opts "-parameter COREV_PULP 1"\ 24 | -imp_elaborate_opts "-parameter COREV_PULP 1"\ 25 | -auto_map_reset_x_values 26 | 27 | 28 | clock clk_i 29 | reset ~rst_ni 30 | 31 | check_sec -map -auto 32 | 33 | if {"$top_module" == "cv32e40p_core"} { 34 | check_sec -waive -waive_signals ex_stage_i.alu_i.ff_one_i.sel_nodes 35 | check_sec -waive -waive_signals cv32e40p_core_imp.ex_stage_i.alu_i.ff_one_i.sel_nodes 36 | 37 | check_sec -waive -waive_signals ex_stage_i.alu_i.ff_one_i.index_nodes 38 | check_sec -waive -waive_signals cv32e40p_core_imp.ex_stage_i.alu_i.ff_one_i.index_nodes 39 | } 40 | 41 | check_sec -prove 42 | 43 | check_sec -signoff -get_valid_status -summary -file $summary_log 44 | 45 | exit 0 46 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/onehot_to_bin.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Franceco Conti 12 | 13 | module onehot_to_bin #( 14 | parameter int unsigned ONEHOT_WIDTH = 16, 15 | // Do Not Change 16 | parameter int unsigned BIN_WIDTH = ONEHOT_WIDTH == 1 ? 1 : $clog2(ONEHOT_WIDTH) 17 | ) ( 18 | input logic [ONEHOT_WIDTH-1:0] onehot, 19 | output logic [BIN_WIDTH-1:0] bin 20 | ); 21 | 22 | for (genvar j = 0; j < BIN_WIDTH; j++) begin : jl 23 | logic [ONEHOT_WIDTH-1:0] tmp_mask; 24 | for (genvar i = 0; i < ONEHOT_WIDTH; i++) begin : il 25 | logic [BIN_WIDTH-1:0] tmp_i; 26 | assign tmp_i = i; 27 | assign tmp_mask[i] = tmp_i[j]; 28 | end 29 | assign bin[j] = |(tmp_mask & onehot); 30 | end 31 | 32 | // pragma translate_off 33 | `ifndef VERILATOR 34 | assert final ($onehot0(onehot)) else 35 | $fatal(1, "[onehot_to_bin] More than two bit set in the one-hot signal"); 36 | `endif 37 | // pragma translate_on 38 | endmodule 39 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/stream_intf.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | 12 | // Author: Florian Zaruba 13 | 14 | /// A stream interface with custom payload of type `payload_t`. 15 | /// Handshaking rules as defined in the AXI standard. 16 | interface STREAM_DV #( 17 | /// Custom payload type. 18 | parameter type payload_t = logic 19 | )( 20 | /// Interface clock. 21 | input logic clk_i 22 | ); 23 | payload_t data; 24 | logic valid; 25 | logic ready; 26 | 27 | modport In ( 28 | output ready, 29 | input valid, data 30 | ); 31 | 32 | modport Out ( 33 | output valid, data, 34 | input ready 35 | ); 36 | 37 | /// Passive modport for scoreboard and monitors. 38 | modport Passive ( 39 | input valid, ready, data 40 | ); 41 | 42 | // Make sure that the handshake and payload is stable 43 | // pragma translate_off 44 | `ifndef VERILATOR 45 | assert property (@(posedge clk_i) (valid && !ready |=> $stable(data))); 46 | assert property (@(posedge clk_i) (valid && !ready |=> valid)); 47 | `endif 48 | // pragma translate_on 49 | endinterface 50 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/counter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Florian Zaruba 12 | // Description: Generic up/down counter 13 | 14 | module counter #( 15 | parameter int unsigned WIDTH = 4, 16 | parameter bit STICKY_OVERFLOW = 1'b0 17 | )( 18 | input logic clk_i, 19 | input logic rst_ni, 20 | input logic clear_i, // synchronous clear 21 | input logic en_i, // enable the counter 22 | input logic load_i, // load a new value 23 | input logic down_i, // downcount, default is up 24 | input logic [WIDTH-1:0] d_i, 25 | output logic [WIDTH-1:0] q_o, 26 | output logic overflow_o 27 | ); 28 | delta_counter #( 29 | .WIDTH (WIDTH), 30 | .STICKY_OVERFLOW (STICKY_OVERFLOW) 31 | ) i_counter ( 32 | .clk_i, 33 | .rst_ni, 34 | .clear_i, 35 | .en_i, 36 | .load_i, 37 | .down_i, 38 | .delta_i({{WIDTH-1{1'b0}}, 1'b1}), 39 | .d_i, 40 | .q_o, 41 | .overflow_o 42 | ); 43 | endmodule 44 | -------------------------------------------------------------------------------- /rtl/include/cv32e40p_apu_core_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | //////////////////////////////////////////////////////////////////////////////// 12 | // Engineer: Michael Gautschi - gautschi@iis.ee.ethz.ch // 13 | // // 14 | // Design Name: APU-core package // 15 | // Project Name: RISC-V // 16 | // Language: SystemVerilog // 17 | // // 18 | // Description: core package of RISC-V core for shared APU // 19 | // // 20 | //////////////////////////////////////////////////////////////////////////////// 21 | 22 | package cv32e40p_apu_core_pkg; 23 | 24 | // APU interface 25 | parameter APU_NARGS_CPU = 3; 26 | parameter APU_WOP_CPU = 6; 27 | parameter APU_NDSFLAGS_CPU = 15; 28 | parameter APU_NUSFLAGS_CPU = 5; 29 | 30 | endpackage // cv32e40p_apu_core_pkg 31 | -------------------------------------------------------------------------------- /scripts/riscv_isa_formal/Makefile: -------------------------------------------------------------------------------- 1 | commonPath=../../verif 2 | PREPARE?=0 3 | RTL?=../../cv32e40p/ 4 | GUI?=0 5 | NAME?=noname 6 | 7 | ifeq ($(APP),) 8 | $(error APP is empty) 9 | endif 10 | ifeq ($(CONF),) 11 | $(error CONF is empty) 12 | endif 13 | ifeq ($(MODE),) 14 | $(error MODE is empty) 15 | endif 16 | 17 | $(info APP=$(APP)) 18 | $(info CONF=$(CONF)) 19 | $(info MODE=$(MODE)) 20 | 21 | ifeq ($(GUI), 1) 22 | flag="-i" 23 | else 24 | flag= 25 | endif 26 | 27 | dirname=$(NAME) 28 | 29 | ifeq ($(PREPARE), 1) 30 | script_name=ones_prepare_run 31 | else 32 | script_name=ones_run 33 | endif 34 | 35 | define ones_prepare_run 36 | @echo "====================================================" 37 | @echo "Preparing working area $(dirname)" 38 | @echo "====================================================" 39 | \mkdir -p cfgs/$(dirname)/logs 40 | \cd cfgs/$(dirname) && \cp -pf $(commonPath)/{other_bindings.sv,core_checker.sv,io.sv,setup.tcl,setup_mv.tcl,*.json,constraints.sv,t.sh,basics.tcl.obf} . && \cp -prfL $(commonPath)/vips . && \cp -prfL $(RTL) . 41 | @echo "====================================================" 42 | @echo "Running mode $(MODE) on configuration $(CONF) in $(dirname)" 43 | @echo "====================================================" 44 | \cd cfgs/$(dirname) && onespin -Q -l logs/$(APP)-cfg_$(CONF)-mode_$(MODE).log $(flag) setup.tcl $(CONF) $(MODE) $(APP) 45 | endef 46 | 47 | define ones_run 48 | @echo "====================================================" 49 | @echo "Running mode $(MODE) on configuration $(CONF) in $(dirname)" 50 | @echo "====================================================" 51 | \cd cfgs/$(dirname) && onespin -Q -l logs/$(APP)-cfg_$(CONF)-mode_$(MODE).log $(flag) setup.tcl $(CONF) $(MODE) $(APP) 52 | endef 53 | 54 | all: 55 | $(call $(script_name)) 56 | 57 | clean: 58 | rm -rf cfgs/$(dirname) 59 | 60 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/clk_div.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Florian Zaruba 12 | // Description: Divides the clock by an integer factor 13 | module clk_div #( 14 | parameter int unsigned RATIO = 4 15 | )( 16 | input logic clk_i, // Clock 17 | input logic rst_ni, // Asynchronous reset active low 18 | input logic testmode_i, // testmode 19 | input logic en_i, // enable clock divider 20 | output logic clk_o // divided clock out 21 | ); 22 | logic [RATIO-1:0] counter_q; 23 | logic clk_q; 24 | 25 | always_ff @(posedge clk_i or negedge rst_ni) begin 26 | if (~rst_ni) begin 27 | clk_q <= 1'b0; 28 | counter_q <= '0; 29 | end else begin 30 | clk_q <= 1'b0; 31 | if (en_i) begin 32 | if (counter_q == (RATIO[RATIO-1:0] - 1)) begin 33 | clk_q <= 1'b1; 34 | end else begin 35 | counter_q <= counter_q + 1; 36 | end 37 | end 38 | end 39 | end 40 | // output assignment - bypass in testmode 41 | assign clk_o = testmode_i ? clk_i : clk_q; 42 | endmodule 43 | -------------------------------------------------------------------------------- /.github/workflows/aws_cv32e40p.md: -------------------------------------------------------------------------------- 1 | # AWS Workflow for CV32E40P 2 | 3 | AWS is used to automate all activities which require access to the licenses provided by OpenHW Group's partners. 4 | 5 | For CV32E40P this currently means the licenses for Synopsys' Formality and Cadence's Conformal, to perform Logic Equivalence Check between a new version's candidate and a reference design (the `golden reference`). 6 | 7 | Some constraints: 8 | - AWS' credentials are available only in the context of the main repository. This means that an AWS job cannot be started from the context of a pull request. 9 | - As per license agreement, the tools can be used only by OpenHW Group's members. This means that their usage must triggered by OpenHW Group staff 10 | - `master` branch must always be clean (no experiments) 11 | 12 | ## Proposed workflow 13 | 14 | - The project has a development branch (`dev`) 15 | - Each PR must target `dev` 16 | - Each PR triggers the `check_target` action, which verifies that target branch 17 | - Each PR is checked and merged by an OpenHW Group member, resulting in a commit to `dev` 18 | - Each push to `dev` triggers the `aws` action, which starts the AWS CodeBuild job 19 | - A successful run of `aws` (and therefore of the related AWS CodeBuild) results in an automatic merge of the `dev` branch to `master` 20 | 21 | ## Notes, open points 22 | 23 | - What happens if `aws` fails? 24 | At the moment, nothing. The repository owner has to analyze the cause of the failure and decide whether to rerun the action or to revert the commit 25 | 26 | - Why not implementing an automatic revert upon failure? 27 | This idea could apparently make the workflow cleaner, but it could also make it much more complex. A CodeBuild job could fail for reasons which are independent from the quality of the code (e.g. licensing issues): in these cases, an autorevert would make the flow a bit more complex. -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/deprecated/pulp_sync_wedge.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module pulp_sync_wedge #( 14 | parameter int unsigned STAGES = 2 15 | ) ( 16 | input logic clk_i, 17 | input logic rstn_i, 18 | input logic en_i, 19 | input logic serial_i, 20 | output logic r_edge_o, 21 | output logic f_edge_o, 22 | output logic serial_o 23 | ); 24 | logic clk; 25 | logic serial, serial_q; 26 | 27 | assign serial_o = serial_q; 28 | assign f_edge_o = ~serial & serial_q; 29 | assign r_edge_o = serial & ~serial_q; 30 | 31 | pulp_sync #( 32 | .STAGES(STAGES) 33 | ) i_pulp_sync ( 34 | .clk_i, 35 | .rstn_i, 36 | .serial_i, 37 | .serial_o ( serial ) 38 | ); 39 | 40 | pulp_clock_gating i_pulp_clock_gating ( 41 | .clk_i, 42 | .en_i, 43 | .test_en_i ( 1'b0 ), 44 | .clk_o ( clk ) 45 | ); 46 | 47 | always_ff @(posedge clk, negedge rstn_i) begin 48 | if (!rstn_i) begin 49 | serial_q <= 1'b0; 50 | end else begin 51 | serial_q <= serial; 52 | end 53 | end 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/edge_propagator.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module edge_propagator ( 14 | input logic clk_tx_i, 15 | input logic rstn_tx_i, 16 | input logic edge_i, 17 | input logic clk_rx_i, 18 | input logic rstn_rx_i, 19 | output logic edge_o 20 | ); 21 | 22 | logic [1:0] sync_a; 23 | logic sync_b; 24 | 25 | logic r_input_reg; 26 | logic s_input_reg_next; 27 | 28 | assign s_input_reg_next = edge_i | (r_input_reg & (~sync_a[0])); 29 | 30 | always @(negedge rstn_tx_i or posedge clk_tx_i) begin 31 | if (~rstn_tx_i) begin 32 | r_input_reg <= 1'b0; 33 | sync_a <= 2'b00; 34 | end else begin 35 | r_input_reg <= s_input_reg_next; 36 | sync_a <= {sync_b,sync_a[1]}; 37 | end 38 | end 39 | 40 | pulp_sync_wedge i_sync_clkb ( 41 | .clk_i ( clk_rx_i ), 42 | .rstn_i ( rstn_rx_i ), 43 | .en_i ( 1'b1 ), 44 | .serial_i ( r_input_reg ), 45 | .r_edge_o ( edge_o ), 46 | .f_edge_o ( ), 47 | .serial_o ( sync_b ) 48 | ); 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/deprecated/sram.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2017, 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Date: 13.10.2017 12 | // Description: SRAM Behavioral Model 13 | 14 | module sram #( 15 | int unsigned DATA_WIDTH = 64, 16 | int unsigned NUM_WORDS = 1024 17 | )( 18 | input logic clk_i, 19 | 20 | input logic req_i, 21 | input logic we_i, 22 | input logic [$clog2(NUM_WORDS)-1:0] addr_i, 23 | input logic [DATA_WIDTH-1:0] wdata_i, 24 | input logic [DATA_WIDTH-1:0] be_i, 25 | output logic [DATA_WIDTH-1:0] rdata_o 26 | ); 27 | localparam ADDR_WIDTH = $clog2(NUM_WORDS); 28 | 29 | logic [DATA_WIDTH-1:0] ram [NUM_WORDS-1:0]; 30 | logic [ADDR_WIDTH-1:0] raddr_q; 31 | 32 | // 1. randomize array 33 | // 2. randomize output when no request is active 34 | always_ff @(posedge clk_i) begin 35 | if (req_i) begin 36 | if (!we_i) 37 | raddr_q <= addr_i; 38 | else 39 | for (int i = 0; i < DATA_WIDTH; i++) 40 | if (be_i[i]) ram[addr_i][i] <= wdata_i[i]; 41 | end 42 | end 43 | 44 | assign rdata_o = ram[raddr_q]; 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/sync_wedge.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module sync_wedge #( 14 | parameter int unsigned STAGES = 2 15 | ) ( 16 | input logic clk_i, 17 | input logic rst_ni, 18 | input logic en_i, 19 | input logic serial_i, 20 | output logic r_edge_o, 21 | output logic f_edge_o, 22 | output logic serial_o 23 | ); 24 | logic clk; 25 | logic serial, serial_q; 26 | 27 | assign serial_o = serial_q; 28 | assign f_edge_o = (~serial) & serial_q; 29 | assign r_edge_o = serial & (~serial_q); 30 | 31 | sync #( 32 | .STAGES (STAGES) 33 | ) i_sync ( 34 | .clk_i, 35 | .rst_ni, 36 | .serial_i, 37 | .serial_o ( serial ) 38 | ); 39 | 40 | pulp_clock_gating i_pulp_clock_gating ( 41 | .clk_i, 42 | .en_i, 43 | .test_en_i ( 1'b0 ), 44 | .clk_o ( clk ) 45 | ); 46 | 47 | always_ff @(posedge clk, negedge rst_ni) begin 48 | if (!rst_ni) begin 49 | serial_q <= 1'b0; 50 | end else begin 51 | if (en_i) begin 52 | serial_q <= serial; 53 | end 54 | end 55 | end 56 | endmodule 57 | -------------------------------------------------------------------------------- /ci/run-openocd-compliance.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # Copyright 2020 ETH Zurich 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | # 17 | # Author: Robert Balas 18 | 19 | set -e 20 | 21 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 22 | 23 | if [ -z "${RISCV}" ] 24 | then 25 | echo "RISCV is empty" 26 | exit 1 27 | fi 28 | 29 | function cleanup { 30 | echo "cleaning up processes and tmp files" 31 | sleep 2 32 | echo "vsim pid is:${vsim_pid} pgid:${vsim_pgid}" 33 | if ps -p "${vsim_pid}" > /dev/null 34 | then 35 | echo "vsim pid exists, killing it" 36 | kill -- -"${vsim_pgid}" 37 | fi 38 | rm "${vsim_out}" 39 | } 40 | 41 | trap cleanup EXIT 42 | 43 | vsim_out=$(mktemp) 44 | openocd_out=openocd.log 45 | 46 | make -C "${ROOT}"/tb/dm vsim-run &> "${vsim_out}"& 47 | # record vsim pid/pgid to kill it if it survives this script 48 | vsim_pid=$! 49 | vsim_pgid=$(ps -o pgid= ${vsim_pid} | grep -o [0-9]*) 50 | 51 | # block until we get "Listening on port" so that we are safe to connect openocd 52 | coproc grep -m 1 "Listening on port" 53 | tail -f -n0 "${vsim_out}" --pid "$COPROC_PID" >&"${COPROC[1]}" 54 | 55 | echo "Starting openocd" 56 | "${RISCV}"/bin/openocd -f "${ROOT}"/tb/dm/pulpissimo_compliance_test.cfg |& tee "${openocd_out}" 57 | 58 | 59 | if grep -q "ALL TESTS PASSED" "${openocd_out}"; then 60 | exit 0 61 | fi 62 | exit 1 63 | 64 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/mv_filter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Florian Zaruba 12 | 13 | module mv_filter #( 14 | parameter int unsigned WIDTH = 4, 15 | parameter int unsigned THRESHOLD = 10 16 | )( 17 | input logic clk_i, 18 | input logic rst_ni, 19 | input logic sample_i, 20 | input logic clear_i, 21 | input logic d_i, 22 | output logic q_o 23 | ); 24 | logic [WIDTH-1:0] counter_q, counter_d; 25 | logic d, q; 26 | 27 | assign q_o = q; 28 | 29 | always_comb begin 30 | counter_d = counter_q; 31 | d = q; 32 | 33 | if (counter_q >= THRESHOLD[WIDTH-1:0]) begin 34 | d = 1'b1; 35 | end else if (sample_i && d_i) begin 36 | counter_d = counter_q + 1; 37 | end 38 | 39 | // sync reset 40 | if (clear_i) begin 41 | counter_d = '0; 42 | d = 1'b0; 43 | end 44 | end 45 | 46 | always_ff @(posedge clk_i or negedge rst_ni) begin 47 | if (~rst_ni) begin 48 | counter_q <= '0; 49 | q <= 1'b0; 50 | end else begin 51 | counter_q <= counter_d; 52 | q <= d; 53 | end 54 | end 55 | endmodule 56 | -------------------------------------------------------------------------------- /scripts/slec/tb_src/cv32e40p_bind2.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Dolphin Design 2 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | // 4 | // Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | // you may not use this file except in compliance with the License, or, 6 | // at your option, the Apache License version 2.0. 7 | // You may obtain a copy of the License at 8 | // 9 | // https://solderpad.org/licenses/SHL-2.1/ 10 | // 11 | // Unless required by applicable law or agreed to in writing, any work 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | 17 | //////////////////////////////////////////////////////////////////////////////////// 18 | // // 19 | // Contributors: Yoann Pruvost, Dolphin Design // 20 | // Pascal Gouedo, Dolphin Design // 21 | // // 22 | // Description: CV32E40P binding for formal code analysis // 23 | // // 24 | //////////////////////////////////////////////////////////////////////////////////// 25 | 26 | bind cv32e40p_top insn_assert u_insn_assert ( 27 | .clk_i(clk_i), 28 | .rst_ni(rst_ni), 29 | 30 | .instr_req_o (instr_req_o), 31 | .instr_gnt_i (instr_gnt_i), 32 | .instr_rvalid_i(instr_rvalid_i) 33 | ); 34 | 35 | bind cv32e40p_top data_assert u_data_assert ( 36 | .clk_i(clk_i), 37 | .rst_ni(rst_ni), 38 | 39 | .data_req_o (data_req_o ), 40 | .data_gnt_i (data_gnt_i ), 41 | .data_rvalid_i(data_rvalid_i) 42 | ); 43 | -------------------------------------------------------------------------------- /scripts/formal/src/interrupt_assert.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Dolphin Design 2 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | // 4 | // Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | // you may not use this file except in compliance with the License, or, 6 | // at your option, the Apache License version 2.0. 7 | // You may obtain a copy of the License at 8 | // 9 | // https://solderpad.org/licenses/SHL-2.1/ 10 | // 11 | // Unless required by applicable law or agreed to in writing, any work 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | 17 | //////////////////////////////////////////////////////////////////////////////////// 18 | // // 19 | // Contributors: Yoann Pruvost, Dolphin Design // 20 | // // 21 | // Description: Debug interface constraints // 22 | // // 23 | //////////////////////////////////////////////////////////////////////////////////// 24 | 25 | module interrput_assert ( 26 | input logic clk_i, 27 | input logic rst_ni, 28 | // Interrupt inputs 29 | input logic [31:0] irq_i, 30 | input logic irq_ack_o, 31 | input logic [ 4:0] irq_id_o 32 | ); 33 | 34 | /********** 35 | * Assume * 36 | **********/ 37 | property no_interrupt; 38 | @(posedge clk_i) disable iff(!rst_ni) 39 | irq_i == '0; 40 | endproperty 41 | 42 | // Uncomment to disable interrupt interface 43 | // assume_no_interrupt: assume property(no_interrupt); 44 | 45 | 46 | endmodule -------------------------------------------------------------------------------- /example_tb/core/custom/crt0.S: -------------------------------------------------------------------------------- 1 | /* Copyright (c) 2017 SiFive Inc. All rights reserved. 2 | * Copyright (c) 2019 ETH Zürich and University of Bologna 3 | * This copyrighted material is made available to anyone wishing to use, 4 | * modify, copy, or redistribute it subject to the terms and conditions 5 | * of the FreeBSD License. This program is distributed in the hope that 6 | * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, 7 | * including the implied warranties of MERCHANTABILITY or FITNESS FOR 8 | * A PARTICULAR PURPOSE. A copy of this license is available at 9 | * http://www.opensource.org/licenses. 10 | */ 11 | 12 | /* Entry point for bare metal programs */ 13 | .section .text.start 14 | .global _start 15 | .type _start, @function 16 | 17 | _start: 18 | /* initialize global pointer */ 19 | .option push 20 | .option norelax 21 | 1: auipc gp, %pcrel_hi(__global_pointer$) 22 | addi gp, gp, %pcrel_lo(1b) 23 | .option pop 24 | 25 | /* initialize stack pointer */ 26 | la sp, _sp 27 | 28 | /* set vector table address and vectored mode */ 29 | la a0, __vector_start 30 | ori a0, a0, 0x1 31 | csrw mtvec, a0 32 | 33 | /* clear the bss segment */ 34 | la a0, __bss_start 35 | la a2, __bss_end 36 | sub a2, a2, a0 37 | li a1, 0 38 | call memset 39 | 40 | /* new-style constructors and destructors */ 41 | la a0, __libc_fini_array 42 | call atexit 43 | call __libc_init_array 44 | 45 | /* call main */ 46 | lw a0, 0(sp) /* a0 = argc */ 47 | addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */ 48 | li a2, 0 /* a2 = envp = NULL */ 49 | call main 50 | tail exit 51 | 52 | .size _start, .-_start 53 | 54 | .global _init 55 | .type _init, @function 56 | .global _fini 57 | .type _fini, @function 58 | _init: 59 | _fini: 60 | /* These don't have to do anything since we use init_array/fini_array. Prevent 61 | missing symbol error */ 62 | ret 63 | .size _init, .-_init 64 | .size _fini, .-_fini 65 | -------------------------------------------------------------------------------- /scripts/formal/src/debug_assert.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Dolphin Design 2 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | // 4 | // Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | // you may not use this file except in compliance with the License, or, 6 | // at your option, the Apache License version 2.0. 7 | // You may obtain a copy of the License at 8 | // 9 | // https://solderpad.org/licenses/SHL-2.1/ 10 | // 11 | // Unless required by applicable law or agreed to in writing, any work 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | 17 | //////////////////////////////////////////////////////////////////////////////////// 18 | // // 19 | // Contributors: Yoann Pruvost, Dolphin Design // 20 | // // 21 | // Description: Debug interface constraints // 22 | // // 23 | //////////////////////////////////////////////////////////////////////////////////// 24 | 25 | module debug_assert ( 26 | input logic clk_i, 27 | input logic rst_ni, 28 | // Debug Interface 29 | input logic debug_req_i, 30 | input logic debug_havereset_o, 31 | input logic debug_running_o, 32 | input logic debug_halted_o 33 | ); 34 | 35 | /********** 36 | * Assume * 37 | **********/ 38 | property no_debug; 39 | @(posedge clk_i) disable iff(!rst_ni) 40 | debug_req_i == '0; 41 | endproperty 42 | 43 | // Uncomment this line to disable debug interface 44 | // assume_no_debug: assume property(no_debug); 45 | 46 | endmodule -------------------------------------------------------------------------------- /scripts/formal/src/fpnew_divsqrt_th_32_assert.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Dolphin Design 2 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | // 4 | // Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | // you may not use this file except in compliance with the License, or, 6 | // at your option, the Apache License version 2.0. 7 | // You may obtain a copy of the License at 8 | // 9 | // https://solderpad.org/licenses/SHL-2.1/ 10 | // 11 | // Unless required by applicable law or agreed to in writing, any work 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | 17 | //////////////////////////////////////////////////////////////////////////////////// 18 | // // 19 | // Contributors: Yoann Pruvost, Dolphin Design // 20 | // // 21 | // Description: Assertion for unreachable code in CV32E40P div sqrt unit // 22 | // // 23 | //////////////////////////////////////////////////////////////////////////////////// 24 | 25 | module fpnew_divsqrt_th_32_assert ( 26 | input logic clk_i, 27 | input logic rst_ni, 28 | 29 | input logic op_starting , 30 | input logic unit_ready_q , 31 | input logic ex2_inst_wb , 32 | input logic ex2_inst_wb_vld_q 33 | ); 34 | 35 | property unreachable_divsqrt_th_288; 36 | @(posedge clk_i) disable iff(!rst_ni) 37 | (op_starting && unit_ready_q) |-> !(ex2_inst_wb && ex2_inst_wb_vld_q); 38 | endproperty 39 | 40 | assert_unreachable_divsqrt_th_288: assert property(unreachable_divsqrt_th_288); 41 | 42 | endmodule -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/stream_mux.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | /// Stream multiplexer: connects the output to one of `N_INP` data streams with valid-ready 12 | /// handshaking. 13 | 14 | module stream_mux #( 15 | parameter type DATA_T = logic, // Vivado requires a default value for type parameters. 16 | parameter integer N_INP = 0, // Synopsys DC requires a default value for value parameters. 17 | /// Dependent parameters, DO NOT OVERRIDE! 18 | parameter integer LOG_N_INP = $clog2(N_INP) 19 | ) ( 20 | input DATA_T [N_INP-1:0] inp_data_i, 21 | input logic [N_INP-1:0] inp_valid_i, 22 | output logic [N_INP-1:0] inp_ready_o, 23 | 24 | input logic [LOG_N_INP-1:0] inp_sel_i, 25 | 26 | output DATA_T oup_data_o, 27 | output logic oup_valid_o, 28 | input logic oup_ready_i 29 | ); 30 | 31 | always_comb begin 32 | inp_ready_o = '0; 33 | inp_ready_o[inp_sel_i] = oup_ready_i; 34 | end 35 | assign oup_data_o = inp_data_i[inp_sel_i]; 36 | assign oup_valid_o = inp_valid_i[inp_sel_i]; 37 | 38 | // pragma translate_off 39 | `ifndef VERILATOR 40 | initial begin: p_assertions 41 | assert (N_INP >= 1) else $fatal ("The number of inputs must be at least 1!"); 42 | end 43 | `endif 44 | // pragma translate_on 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /example_tb/core/software.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2020 ETH Zurich 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | # add fc execution trace 16 | set rvcores [find instances -recursive -bydu cv32e40p_core -nodu] 17 | set tracer [find instances -recursive -bydu cv32e40p_tracer -nodu] 18 | set fpuprivate [find instances -recursive -bydu fpu_private] 19 | 20 | if {$rvcores ne ""} { 21 | 22 | add wave -group "Software Debugging" $rvcores/clk_i 23 | add wave -group "Software Debugging" -divider "Instructions at ID stage, sampled half a cycle later" 24 | 25 | if {$tracer ne ""} { 26 | add wave -group "Software Debugging" $tracer/insn_disas 27 | add wave -group "Software Debugging" $tracer/insn_pc 28 | add wave -group "Software Debugging" $tracer/insn_val 29 | } 30 | 31 | add wave -group "Software Debugging" -divider "Program counter at ID and IF stage" 32 | add wave -group "Software Debugging" $rvcores/pc_id 33 | add wave -group "Software Debugging" $rvcores/pc_if 34 | add wave -group "Software Debugging" -divider "Register File contents" 35 | add wave -group "Software Debugging" $rvcores/id_stage_i/register_file_i/mem 36 | if {$fpuprivate ne ""} { 37 | add wave -group "Software Debugging" $rvcores/id_stage_i/register_file_i/mem_fp 38 | } 39 | 40 | } 41 | 42 | configure wave -namecolwidth 250 43 | configure wave -valuecolwidth 100 44 | configure wave -justifyvalue left 45 | configure wave -signalnamewidth 1 46 | configure wave -timelineunits ns 47 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/stream_join.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Authors: 12 | // - Andreas Kurth 13 | 14 | /// Stream join: Joins a parametrizable number of input streams (i.e., valid-ready handshaking with 15 | /// dependency rules as in AXI4) to a single output stream. The output handshake happens only once 16 | /// all inputs are valid. The data channel flows outside of this module. 17 | module stream_join #( 18 | /// Number of input streams 19 | parameter int unsigned N_INP = 32'd0 // Synopsys DC requires a default value for parameters. 20 | ) ( 21 | /// Input streams valid handshakes 22 | input logic [N_INP-1:0] inp_valid_i, 23 | /// Input streams ready handshakes 24 | output logic [N_INP-1:0] inp_ready_o, 25 | /// Output stream valid handshake 26 | output logic oup_valid_o, 27 | /// Output stream ready handshake 28 | input logic oup_ready_i 29 | ); 30 | 31 | assign oup_valid_o = (&inp_valid_i); 32 | for (genvar i = 0; i < N_INP; i++) begin : gen_inp_ready 33 | assign inp_ready_o[i] = oup_valid_o & oup_ready_i; 34 | end 35 | 36 | // pragma translate_off 37 | `ifndef VERILATOR 38 | initial begin: p_assertions 39 | assert (N_INP >= 1) else $fatal(1, "N_INP must be at least 1!"); 40 | end 41 | `endif 42 | // pragma translate_on 43 | endmodule 44 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/serial_deglitch.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Florian Zaruba 12 | // Description: Deglitches a serial line by taking multiple samples until 13 | // asserting the output high/low. 14 | 15 | module serial_deglitch #( 16 | parameter int unsigned SIZE = 4 17 | )( 18 | input logic clk_i, // clock 19 | input logic rst_ni, // asynchronous reset active low 20 | input logic en_i, // enable 21 | input logic d_i, // serial data in 22 | output logic q_o // filtered data out 23 | ); 24 | logic [SIZE-1:0] count_q; 25 | logic q; 26 | 27 | always_ff @(posedge clk_i or negedge rst_ni) begin 28 | if (~rst_ni) begin 29 | count_q <= '0; 30 | q <= 1'b0; 31 | end else begin 32 | if (en_i) begin 33 | if (d_i == 1'b1 && count_q != SIZE[SIZE-1:0]) begin 34 | count_q <= count_q + 1; 35 | end else if (d_i == 1'b0 && count_q != SIZE[SIZE-1:0]) begin 36 | count_q <= count_q - 1; 37 | end 38 | end 39 | end 40 | end 41 | 42 | // output process 43 | always_comb begin 44 | if (count_q == SIZE[SIZE-1:0]) begin 45 | q_o = 1'b1; 46 | end else if (count_q == 0) begin 47 | q_o = 1'b0; 48 | end 49 | end 50 | endmodule 51 | -------------------------------------------------------------------------------- /example_tb/core/firmware/stats.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 ETH Zurich 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | * 16 | */ 17 | 18 | #include "firmware.h" 19 | 20 | static void stats_print_dec(unsigned int val, int digits, bool zero_pad) 21 | { 22 | char buffer[32]; 23 | char *p = buffer; 24 | while (val || digits > 0) { 25 | if (val) 26 | *(p++) = '0' + val % 10; 27 | else 28 | *(p++) = zero_pad ? '0' : ' '; 29 | val = val / 10; 30 | digits--; 31 | } 32 | while (p != buffer) { 33 | if (p[-1] == ' ' && p[-2] == ' ') 34 | p[-1] = '.'; 35 | print_chr(*(--p)); 36 | } 37 | } 38 | 39 | void init_stats(void) 40 | { 41 | unsigned int zero = 0; 42 | unsigned int enable = 0xfffffff8; /* cycles and instr count enable */ 43 | __asm__ volatile("csrw 0xb00, %0" ::"r"(zero)); 44 | __asm__ volatile("csrw 0xb02, %0" ::"r"(zero)); 45 | __asm__ volatile("csrw 0x320, %0" ::"r"(enable)); 46 | } 47 | 48 | void stats(void) 49 | { 50 | unsigned int num_cycles, num_instr; 51 | __asm__ volatile("csrr %0, 0xb00" : "=r"(num_cycles)); 52 | __asm__ volatile("csrr %0, 0xb02" : "=r"(num_instr)); 53 | print_str("Cycle counter ........"); 54 | stats_print_dec(num_cycles, 8, false); 55 | print_str("\nInstruction counter .."); 56 | stats_print_dec(num_instr, 8, false); 57 | print_str("\nCPI: "); 58 | stats_print_dec((num_cycles / num_instr), 0, false); 59 | print_str("."); 60 | stats_print_dec(((100 * num_cycles) / num_instr) % 100, 2, true); 61 | print_str("\n"); 62 | } 63 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/shift_reg.sv: -------------------------------------------------------------------------------- 1 | 2 | // Copyright 2018 ETH Zurich and University of Bologna. 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // Author: 13 | // 14 | // Description: Simple shift register for arbitrary depth and types 15 | 16 | module shift_reg #( 17 | parameter type dtype = logic, 18 | parameter int unsigned Depth = 1 19 | )( 20 | input logic clk_i, // Clock 21 | input logic rst_ni, // Asynchronous reset active low 22 | input dtype d_i, 23 | output dtype d_o 24 | ); 25 | 26 | // register of depth 0 is a wire 27 | if (Depth == 0) begin : gen_pass_through 28 | assign d_o = d_i; 29 | // register of depth 1 is a simple register 30 | end else if (Depth == 1) begin : gen_register 31 | always_ff @(posedge clk_i or negedge rst_ni) begin 32 | if (~rst_ni) begin 33 | d_o <= '0; 34 | end else begin 35 | d_o <= d_i; 36 | end 37 | end 38 | // if depth is greater than 1 it becomes a shift register 39 | end else if (Depth > 1) begin : gen_shift_reg 40 | dtype [Depth-1:0] reg_d, reg_q; 41 | assign d_o = reg_q[Depth-1]; 42 | assign reg_d = {reg_q[Depth-2:0], d_i}; 43 | 44 | always_ff @(posedge clk_i or negedge rst_ni) begin 45 | if (~rst_ni) begin 46 | reg_q <= '0; 47 | end else begin 48 | reg_q <= reg_d; 49 | end 50 | end 51 | end 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /example_tb/core/include/perturbation_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | ////////////////////////////////////////////////////////////////////////////////////////////////////////////// 12 | // // 13 | // Author: Francesco Minervini - minervif@student.ethz.ch // 14 | // // 15 | // Additional contributions by: // 16 | // Design Name: Interrupt generator // 17 | // Project Name: RI5CY, Zeroriscy // 18 | // Language: SystemVerilog // 19 | // // 20 | // Description: Defines for the perturbation module // 21 | ////////////////////////////////////////////////////////////////////////////////////////////////////////////// 22 | 23 | package perturbation_pkg; 24 | 25 | parameter STANDARD = 32'h1; 26 | parameter RANDOM = 32'h2; 27 | parameter PC_TRIG = 32'h3; 28 | parameter SOFTWARE_DEFINED = 32'h4; 29 | 30 | endpackage 31 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/lfsr_8bit.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Igor Loi - University of Bologna 12 | // Author: Florian Zaruba, ETH Zurich 13 | // Date: 12.11.2017 14 | // Description: 8-bit LFSR 15 | 16 | /// 8 bit Linear Feedback Shift register 17 | module lfsr_8bit #( 18 | parameter logic [7:0] SEED = 8'b0, 19 | parameter int unsigned WIDTH = 8 20 | ) ( 21 | input logic clk_i, 22 | input logic rst_ni, 23 | input logic en_i, 24 | output logic [ WIDTH-1:0] refill_way_oh, 25 | output logic [$clog2(WIDTH)-1:0] refill_way_bin 26 | ); 27 | 28 | localparam int unsigned LogWidth = $clog2(WIDTH); 29 | 30 | logic [7:0] shift_d, shift_q; 31 | 32 | always_comb begin 33 | 34 | automatic logic shift_in; 35 | shift_in = !(shift_q[7] ^ shift_q[3] ^ shift_q[2] ^ shift_q[1]); 36 | 37 | shift_d = shift_q; 38 | 39 | if (en_i) shift_d = {shift_q[6:0], shift_in}; 40 | 41 | // output assignment 42 | refill_way_oh = 'b0; 43 | refill_way_oh[shift_q[LogWidth - 1:0]] = 1'b1; 44 | refill_way_bin = shift_q; 45 | end 46 | 47 | always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ 48 | if (~rst_ni) begin 49 | shift_q <= SEED; 50 | end else begin 51 | shift_q <= shift_d; 52 | end 53 | end 54 | 55 | //pragma translate_off 56 | initial begin 57 | assert (WIDTH <= 8) else $fatal(1, "WIDTH needs to be less than 8 because of the 8-bit LFSR"); 58 | end 59 | //pragma translate_on 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /Bender.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2020 ETH Zurich 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | package: 16 | name: riscv 17 | 18 | dependencies: 19 | fpnew: { git: "https://github.com/pulp-platform/fpnew.git", version: 0.6.1 } 20 | common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.16.4 } 21 | tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.1.1 } 22 | 23 | sources: 24 | include_dirs: 25 | - rtl/include 26 | files: 27 | - rtl/include/cv32e40p_apu_core_pkg.sv 28 | - rtl/include/cv32e40p_pkg.sv 29 | - rtl/cv32e40p_alu.sv 30 | - rtl/cv32e40p_alu_div.sv 31 | - rtl/cv32e40p_aligner.sv 32 | - rtl/cv32e40p_compressed_decoder.sv 33 | - rtl/cv32e40p_controller.sv 34 | - rtl/cv32e40p_cs_registers.sv 35 | - rtl/cv32e40p_decoder.sv 36 | - rtl/cv32e40p_int_controller.sv 37 | - rtl/cv32e40p_ex_stage.sv 38 | - rtl/cv32e40p_hwloop_controller.sv 39 | - rtl/cv32e40p_hwloop_regs.sv 40 | - rtl/cv32e40p_id_stage.sv 41 | - rtl/cv32e40p_if_stage.sv 42 | - rtl/cv32e40p_load_store_unit.sv 43 | - rtl/cv32e40p_mult.sv 44 | - rtl/cv32e40p_prefetch_buffer.sv 45 | - rtl/cv32e40p_obi_interface.sv 46 | - rtl/cv32e40p_core.sv 47 | - rtl/cv32e40p_apu_disp.sv 48 | - rtl/cv32e40p_fetch_fifo.sv 49 | - rtl/cv32e40p_popcnt.sv 50 | - rtl/cv32e40p_ff_one.sv 51 | - rtl/cv32e40p_sleep_unit.sv 52 | - target: asic 53 | files: 54 | - rtl/cv32e40p_register_file_latch.sv 55 | - target: not(asic) 56 | files: 57 | - rtl/cv32e40p_register_file_ff.sv 58 | - target: rtl 59 | files: 60 | - bhv/cv32e40p_sim_clock_gate.sv 61 | -------------------------------------------------------------------------------- /scripts/formal/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright 2024 Dolphin Design 2 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | # 4 | # Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | # you may not use this file except in compliance with the License, or, 6 | # at your option, the Apache License version 2.0. 7 | # You may obtain a copy of the License at 8 | # 9 | # https://solderpad.org/licenses/SHL-2.1/ 10 | # 11 | # Unless required by applicable law or agreed to in writing, any work 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | 17 | ################################################################################## 18 | # # 19 | # Contributors: Yoann Pruvost, Dolphin Design # 20 | # # 21 | # Description: Makefile for CV32E40P Formal code analysis # 22 | # # 23 | ################################################################################## 24 | 25 | export DESIGN_RTL_DIR = ../../rtl 26 | 27 | create_lib: 28 | rm -rf work 29 | vlib work 30 | 31 | compile_design: create_lib 32 | vlog -sv -f ../../cv32e40p_fpu_manifest.flist 33 | vlog -sv -mfcu -cuname cv32e40p_bind -f cv32e40p_formal.flist 34 | 35 | compile_design_pulp: create_lib 36 | vlog -sv +define+PULP -f ../../cv32e40p_fpu_manifest.flist 37 | vlog -sv +define+PULP -mfcu -cuname cv32e40p_bind -f cv32e40p_formal.flist 38 | 39 | compile_design_pulp_f0: create_lib 40 | vlog -sv +define+PULP_F0 -f ../../cv32e40p_fpu_manifest.flist 41 | vlog -sv +define+PULP_F0 -mfcu -cuname cv32e40p_bind -f cv32e40p_formal.flist 42 | 43 | run: compile_design 44 | qverify -c -do formal.do 45 | 46 | run_pulp: compile_design_pulp 47 | qverify -c -do formal.do 48 | 49 | run_pulp_F0: compile_design_pulp_f0 50 | qverify -c -do formal.do 51 | 52 | clean: 53 | qverify_clean 54 | rm -rf work -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/rstgen_bypass.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Florian Zaruba 12 | // Description: This module is a reset synchronizer with a dedicated reset bypass pin for testmode reset. 13 | // Pro Tip: The wise Dr. Schaffner recommends at least 4 registers! 14 | 15 | module rstgen_bypass #( 16 | parameter int unsigned NumRegs = 4 17 | ) ( 18 | input logic clk_i, 19 | input logic rst_ni, 20 | input logic rst_test_mode_ni, 21 | input logic test_mode_i, 22 | output logic rst_no, 23 | output logic init_no 24 | ); 25 | 26 | // internal reset 27 | logic rst_n; 28 | 29 | logic [NumRegs-1:0] synch_regs_q; 30 | // bypass mode 31 | always_comb begin 32 | if (test_mode_i == 1'b0) begin 33 | rst_n = rst_ni; 34 | rst_no = synch_regs_q[NumRegs-1]; 35 | init_no = synch_regs_q[NumRegs-1]; 36 | end else begin 37 | rst_n = rst_test_mode_ni; 38 | rst_no = rst_test_mode_ni; 39 | init_no = 1'b1; 40 | end 41 | end 42 | 43 | always @(posedge clk_i or negedge rst_n) begin 44 | if (~rst_n) begin 45 | synch_regs_q <= 0; 46 | end else begin 47 | synch_regs_q <= {synch_regs_q[NumRegs-2:0], 1'b1}; 48 | end 49 | end 50 | // pragma translate_off 51 | `ifndef VERILATOR 52 | initial begin : p_assertions 53 | if (NumRegs < 1) $fatal(1, "At least one register is required."); 54 | end 55 | `endif 56 | // pragma translate_on 57 | endmodule 58 | -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | # Contributing 2 | Contributors are encouraged to be a [member](https://www.openhwgroup.org/membership/) of the 3 | OpenHW Group. New members are always welcome. 4 | 5 | ## Getting Started 6 | The [OpenHW Work Flow](https://github.com/openhwgroup/programs/blob/master/TGs/verification-task-group/documents/presentations/OpenHWGroup_WorkFlow.pdf) document 7 | is required reading. You will find information about the implementation and usage of the CORE-V verification environments 8 | in the [Verification Strategy](https://docs.openhwgroup.org/projects/core-v-verif/en/latest/intro.html). 9 | 10 | ## Updating Copyright 11 | The files in this repository are open-source artifacts licensed under the terms of the Solderpad license, see [LICENSE](LICENSE). 12 | If you modify a file, a new copyright _may_ be added, but the existing copyright and license header _must not_ be removed or modified. 13 | If your contribution uses a newer version of the existing license, you are encouraged to declare that with a one-liner SPDX header. 14 | 15 | In the example below, a new copyright and updated license are added to an existing copyright and license: 16 | ``` 17 | // Copyright 2024 OpenHW Group and 18 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 19 | // Copyright 2018 ETH Zurich and University of Bologna. 20 | // Copyright and related rights are licensed under the Solderpad Hardware 21 | // License, Version 0.51 (the "License"); you may not use this file except in 22 | // compliance with the License. 23 | // ...remainder of original license header from ETHZ and UniBo. 24 | ``` 25 | 26 | ## The Mechanics 27 | 1. From GitHub: [fork](https://help.github.com/articles/fork-a-repo/) the [cv32e40p](https://github.com/openhwgroup/cv32e40p) repository 28 | 2. Clone repository: `git clone https://github.com/[your_github_username]/cv32e40p` 29 | 3. Create your feature branch: `git checkout -b .`
Please uniquify your branch name. See the [Git Cheats](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.md) 30 | for a useful nominclature. 31 | 4. Make your edits... 32 | 5. Commit your changes: `git commit -m 'Add some feature' -s`
Note: **-s**, is optional. 33 | 6. Push feature branch: `git push origin ` 34 | 7. From GitHub: submit a pull request 35 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/stream_arbiter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Stream arbiter: Arbitrates a parametrizable number of input streams (i.e., valid-ready 12 | // handshaking with dependency rules as in AXI4) to a single output stream. Once `oup_valid_o` is 13 | // asserted, `oup_data_o` remains invariant until the output handshake has occurred. The 14 | // arbitration scheme is round-robin with "look ahead", see the `rrarbiter` for details. 15 | 16 | module stream_arbiter #( 17 | parameter type DATA_T = logic, // Vivado requires a default value for type parameters. 18 | parameter integer N_INP = -1, // Synopsys DC requires a default value for parameters. 19 | parameter ARBITER = "rr" // "rr" or "prio" 20 | ) ( 21 | input logic clk_i, 22 | input logic rst_ni, 23 | 24 | input DATA_T [N_INP-1:0] inp_data_i, 25 | input logic [N_INP-1:0] inp_valid_i, 26 | output logic [N_INP-1:0] inp_ready_o, 27 | 28 | output DATA_T oup_data_o, 29 | output logic oup_valid_o, 30 | input logic oup_ready_i 31 | ); 32 | 33 | stream_arbiter_flushable #( 34 | .DATA_T (DATA_T), 35 | .N_INP (N_INP), 36 | .ARBITER (ARBITER) 37 | ) i_arb ( 38 | .clk_i (clk_i), 39 | .rst_ni (rst_ni), 40 | .flush_i (1'b0), 41 | .inp_data_i (inp_data_i), 42 | .inp_valid_i (inp_valid_i), 43 | .inp_ready_o (inp_ready_o), 44 | .oup_data_o (oup_data_o), 45 | .oup_valid_o (oup_valid_o), 46 | .oup_ready_i (oup_ready_i) 47 | ); 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /scripts/formal/src/cv32e40p_ID_assert.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Dolphin Design 2 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | // 4 | // Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | // you may not use this file except in compliance with the License, or, 6 | // at your option, the Apache License version 2.0. 7 | // You may obtain a copy of the License at 8 | // 9 | // https://solderpad.org/licenses/SHL-2.1/ 10 | // 11 | // Unless required by applicable law or agreed to in writing, any work 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | 17 | //////////////////////////////////////////////////////////////////////////////////// 18 | // // 19 | // Contributors: Yoann Pruvost, Dolphin Design // 20 | // // 21 | // Description: Assertion for unreachable code in CV32E40P ID stage // 22 | // // 23 | //////////////////////////////////////////////////////////////////////////////////// 24 | 25 | module cv32e40p_ID_assert import cv32e40p_pkg::*; 26 | ( 27 | input logic clk_i, 28 | input logic rst_ni, 29 | 30 | input logic [31:0] instr_rdata_i, 31 | input logic is_compressed_id_i, 32 | 33 | input logic [ 2:0] alu_op_a_mux_sel, 34 | input logic [ 2:0] alu_op_b_mux_sel, 35 | input logic [ 1:0] alu_op_c_mux_sel, 36 | input logic alu_bmask_b_mux_sel, 37 | input logic [ 1:0] ctrl_transfer_target_mux_sel 38 | ); 39 | 40 | property unreachable_id_872; 41 | @(posedge clk_i) disable iff(!rst_ni) 42 | (alu_op_c_mux_sel == OP_C_REGC_OR_FWD) && (~(alu_op_b_mux_sel == OP_B_BMASK) && ((alu_op_a_mux_sel != OP_A_REGC_OR_FWD) && (ctrl_transfer_target_mux_sel != JT_JALR)) && ~alu_bmask_b_mux_sel) |-> alu_op_b_mux_sel == OP_B_IMM; 43 | endproperty 44 | 45 | assert_unreachable_id_872: assert property(unreachable_id_872); 46 | endmodule -------------------------------------------------------------------------------- /scripts/lint/lint.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # Copyright 2023 OpenHW Group 4 | # Copyright 2023 Dolphin Design 5 | # 6 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # https://solderpad.org/licenses/ 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # 18 | # Contributor: Pascal Gouedo 19 | 20 | if [[ $# -eq 0 ]]; then 21 | CONFIG=config_0p_0f_0z_0lat_0c 22 | else 23 | CONFIG=config_$1 24 | if [[ ! -d $CONFIG ]]; then 25 | echo "Config $CONFIG does not exists." 26 | exit 27 | fi 28 | fi 29 | echo "Lint of $CONFIG" 30 | 31 | if [[ -d questa_autocheck/$CONFIG ]]; then 32 | rm -rf questa_autocheck/$CONFIG 33 | fi 34 | mkdir -p questa_autocheck/$CONFIG 35 | 36 | # Creating RTL file list 37 | if [[ $CONFIG == *1f* ]]; then 38 | MANIFEST=cv32e40p_fpu_manifest 39 | else 40 | MANIFEST=cv32e40p_manifest 41 | fi 42 | 43 | UPSTREAM_DIR=$(pwd)/../../rtl 44 | echo "$upstream_dir" 45 | sed -n '/^+incdir+/s:${DESIGN_RTL_DIR}:'"$UPSTREAM_DIR"':p' ../../$MANIFEST.flist > questa_autocheck/$CONFIG/inc_design.f 46 | sed -n '1,/cv32e40p_sim_clock_gate/{s:^${DESIGN_RTL_DIR}:'"$UPSTREAM_DIR"':p}' ../../$MANIFEST.flist > questa_autocheck/$CONFIG/src_design.f 47 | echo "$(pwd)/$CONFIG/cv32e40p_config_pkg.sv" >> questa_autocheck/$CONFIG/src_design.f 48 | echo "$(pwd)/cv32e40p_wrapper.sv" >> questa_autocheck/$CONFIG/src_design.f 49 | 50 | cd questa_autocheck/$CONFIG 51 | 52 | # Compiling Verilog / SystemVerilog RTL files 53 | vlog -64 -nologo -source -timescale "1 ns / 1 ps" -sv -f inc_design.f -f src_design.f -assertdebug -work design_lib |& tee compile_design.log 54 | 55 | # Launching formal lint analysis 56 | qverify -licq -c -od formal_lint_out -do ../../qverify_analysis.do |& tee formal_lint.log 57 | 58 | # Launching formal lint AutoCheck Summary 59 | qverify -licq -c -od formal_lint_out -do ../../qverify_autocheck.do 60 | 61 | -------------------------------------------------------------------------------- /docs/source/register_file.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright 2024 OpenHW Group and Dolphin Design 3 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 4 | 5 | Licensed under the Solderpad Hardware License v 2.1 (the "License"); 6 | you may not use this file except in compliance with the License, or, 7 | at your option, the Apache License version 2.0. 8 | You may obtain a copy of the License at 9 | 10 | https://solderpad.org/licenses/SHL-2.1/ 11 | 12 | Unless required by applicable law or agreed to in writing, any work 13 | distributed under the License is distributed on an "AS IS" BASIS, 14 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | See the License for the specific language governing permissions and 16 | limitations under the License. 17 | 18 | .. _register-file: 19 | 20 | Register File 21 | ============= 22 | 23 | Source files: :file:`rtl/cv32e40p_register_file_ff.sv` 24 | 25 | CV32E40P has 31 32-bit wide registers which form registers ``x1`` to ``x31``. 26 | Register ``x0`` is statically bound to 0 and can only be read, it does not 27 | contain any sequential logic. 28 | 29 | The register file has three read ports and two write ports. Register file reads are performed in the ID stage. 30 | Register file writes are performed in the WB stage. 31 | 32 | Floating-Point Register File 33 | ---------------------------- 34 | 35 | If the optional FPU is instantiated, unless ``ZFINX`` is configured, the register file is extended 36 | with an additional register bank of 32 registers ``f0``-``f31``. These registers 37 | are stacked on top of the existing register file and can be accessed 38 | concurrently with the limitation that a maximum of three operands per 39 | cycle can be read. Each of the three operands addresses is extended with 40 | an register file select signal which is generated in the instruction decoder 41 | when a FP instruction is decoded. This additional signals determines if 42 | the operand is located in the integer or the floating point register 43 | file. 44 | 45 | Forwarding paths, and write-back logic are shared for the integer and 46 | floating point operations and are not replicated. 47 | 48 | If ``ZFINX`` parameter is set, there is no additional register bank and FPU instructions are using 49 | the same register file than for integer instructions. 50 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/deprecated/generic_LFSR_8bit.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Igor Loi 12 | 13 | module generic_LFSR_8bit 14 | #( 15 | parameter OH_WIDTH = 4, 16 | parameter BIN_WIDTH = $clog2(OH_WIDTH), 17 | parameter SEED = 8'b00000000 18 | ) 19 | ( 20 | output logic [OH_WIDTH-1:0] data_OH_o, // One hot encoding 21 | output logic [BIN_WIDTH-1:0] data_BIN_o, // Binary encoding 22 | input logic enable_i, // 23 | input logic clk, // 24 | input logic rst_n // 25 | ); 26 | 27 | logic [7:0] out; 28 | logic linear_feedback; 29 | logic [BIN_WIDTH-1:0] temp_ref_way; 30 | 31 | 32 | //-------------Code Starts Here------- 33 | assign linear_feedback = !(out[7] ^ out[3] ^ out[2] ^ out[1]); // TAPS for XOR feedback 34 | 35 | assign data_BIN_o = temp_ref_way; 36 | 37 | always_ff @(posedge clk, negedge rst_n) 38 | begin 39 | if (rst_n == 1'b0) 40 | begin 41 | out <= SEED ; 42 | end 43 | else if (enable_i) 44 | begin 45 | out <= {out[6],out[5],out[4],out[3],out[2],out[1],out[0], linear_feedback}; 46 | end 47 | end 48 | 49 | generate 50 | 51 | if(OH_WIDTH == 2) 52 | assign temp_ref_way = out[1]; 53 | else 54 | assign temp_ref_way = out[BIN_WIDTH:1]; 55 | endgenerate 56 | 57 | // Bin to One Hot Encoder 58 | always_comb 59 | begin 60 | data_OH_o = '0; 61 | data_OH_o[temp_ref_way] = 1'b1; 62 | end 63 | 64 | endmodule 65 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/lfsr_16bit.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Florian Zaruba, ETH Zurich 12 | // Date: 5.11.2018 13 | // Description: 16-bit LFSR 14 | 15 | // -------------- 16 | // 16-bit LFSR 17 | // -------------- 18 | // 19 | // Description: Shift register 20 | // 21 | module lfsr_16bit #( 22 | parameter logic [15:0] SEED = 8'b0, 23 | parameter int unsigned WIDTH = 16 24 | )( 25 | input logic clk_i, 26 | input logic rst_ni, 27 | input logic en_i, 28 | output logic [WIDTH-1:0] refill_way_oh, 29 | output logic [$clog2(WIDTH)-1:0] refill_way_bin 30 | ); 31 | 32 | localparam int unsigned LogWidth = $clog2(WIDTH); 33 | 34 | logic [15:0] shift_d, shift_q; 35 | 36 | 37 | always_comb begin 38 | 39 | automatic logic shift_in; 40 | shift_in = !(shift_q[15] ^ shift_q[12] ^ shift_q[5] ^ shift_q[1]); 41 | 42 | shift_d = shift_q; 43 | 44 | if (en_i) 45 | shift_d = {shift_q[14:0], shift_in}; 46 | 47 | // output assignment 48 | refill_way_oh = 'b0; 49 | refill_way_oh[shift_q[LogWidth-1:0]] = 1'b1; 50 | refill_way_bin = shift_q; 51 | end 52 | 53 | always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ 54 | if(~rst_ni) begin 55 | shift_q <= SEED; 56 | end else begin 57 | shift_q <= shift_d; 58 | end 59 | end 60 | 61 | //pragma translate_off 62 | initial begin 63 | assert (WIDTH <= 16) 64 | else $fatal(1, "WIDTH needs to be less than 16 because of the 16-bit LFSR"); 65 | end 66 | //pragma translate_on 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/stream_register.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | /// Register with a simple stream-like ready/valid handshake. 12 | /// This register does not cut combinatorial paths on all control signals; if you need a complete 13 | /// cut, use the `spill_register`. 14 | module stream_register #( 15 | parameter type T = logic // Vivado requires a default value for type parameters. 16 | ) ( 17 | input logic clk_i, // Clock 18 | input logic rst_ni, // Asynchronous active-low reset 19 | input logic clr_i, // Synchronous clear 20 | input logic testmode_i, // Test mode to bypass clock gating 21 | // Input port 22 | input logic valid_i, 23 | output logic ready_o, 24 | input T data_i, 25 | // Output port 26 | output logic valid_o, 27 | input logic ready_i, 28 | output T data_o 29 | ); 30 | 31 | logic fifo_empty, 32 | fifo_full; 33 | 34 | fifo_v2 #( 35 | .FALL_THROUGH (1'b0), 36 | .DATA_WIDTH ($bits(T)), 37 | .DEPTH (1), 38 | .dtype (T) 39 | ) i_fifo ( 40 | .clk_i (clk_i), 41 | .rst_ni (rst_ni), 42 | .flush_i (clr_i), 43 | .testmode_i (testmode_i), 44 | .full_o (fifo_full), 45 | .empty_o (fifo_empty), 46 | .alm_full_o ( ), 47 | .alm_empty_o ( ), 48 | .data_i (data_i), 49 | .push_i (valid_i & ~fifo_full), 50 | .data_o (data_o), 51 | .pop_i (ready_i & ~fifo_empty) 52 | ); 53 | 54 | assign ready_o = ~fifo_full; 55 | assign valid_o = ~fifo_empty; 56 | 57 | endmodule 58 | -------------------------------------------------------------------------------- /example_tb/core/README.md: -------------------------------------------------------------------------------- 1 | Example testbench 2 | ---------------------- 3 | This is an example testbench that provides an example of running 'Hello World'. The 4 | actual testbench and verification environment for CV32E40P can be found in 5 | https://github.com/openhwgroup/core-v-verif 6 | 7 | Supported Compilers 8 | ---------------------- 9 | Note that this testbench requires either the upstream 10 | [riscv-gcc](https://github.com/riscv/riscv-gcc) or if you want to use our custom 11 | PULP instructions our PULP 12 | [riscv-gcc](https://github.com/pulp-platform/pulp-riscv-gcc) (recommended to be 13 | installed through our [sdk](https://github.com/pulp-platform/pulp-sdk)). 14 | 15 | Running your own programs 16 | --------------------- 17 | The `custom` folder has an example on a hello world program that can be run with 18 | the testbench. The relevant sections in the Makefile on how to compile and link 19 | this program can be found under `Running custom programs`. In order to compile 20 | it successfully you need gcc with RISC-V support and a fitting newlib installed. 21 | It is strongly recommended you use the [RISC-V GNU 22 | Toolchain](https://github.com/riscv/riscv-gnu-toolchain) for that (follow the 23 | `Installation (Newlib)` section) and point your `RISCV` environment variable to 24 | it. 25 | 26 | We have prepared a 'Hello World' program which you can run in the testbench. It 27 | demonstrates how you can run your own programs. Call `custom-vsim-run` to 28 | run it with `vsim`. 29 | 30 | Running the testbench with vsim 31 | ---------------------- 32 | Point you environment variable `RISCV` to your RISC-V toolchain. Call `make 33 | firmware-vsim-run` to build the testbench and the firmware, and run it. Use 34 | `VSIM_FLAGS` to configure the simulator e.g. `make custom-vsim-run 35 | VSIM_FLAGS="-gui -debugdb"`. 36 | 37 | Running with other simulators 38 | ---------------------- 39 | Other simulator and more extensive test cases are supported in https://github.com/openhwgroup/core-v-verif 40 | 41 | Options 42 | ---------------------- 43 | A few plusarg options are supported. 44 | * `+verbose` to show all memory read and writes and other miscellaneous information. 45 | 46 | * `+vcd` to produce a vcd file called `riscy_tb.vcd`. Verilator always produces 47 | a vcd file called `verilator_tb.vcd`. 48 | 49 | Examples 50 | ----------------------- 51 | Run all riscv-tests to completion and produce a vcd dump: 52 | `make firmware-vsim-run VSIM_FLAGS=+vcd` 53 | -------------------------------------------------------------------------------- /scripts/slec/cadence/lec.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2024 OpenHW Group and Dolphin Design 2 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | # 4 | # Licensed under the Solderpad Hardware License v 2.1 (the “License”); 5 | # you may not use this file except in compliance with the License, or, 6 | # at your option, the Apache License version 2.0. 7 | # You may obtain a copy of the License at 8 | # 9 | # https://solderpad.org/licenses/SHL-2.1/ 10 | # 11 | # Unless required by applicable law or agreed to in writing, any work 12 | # distributed under the License is distributed on an “AS IS” BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | 17 | set summary_log $::env(summary_log) 18 | set top_module $::env(top_module) 19 | set version $::env(version) 20 | set pulp_cfg $::env(pulp_cfg) 21 | set fpu_cfg $::env(fpu_cfg) 22 | set zfinx_cfg $::env(zfinx_cfg) 23 | set latency_cfg $::env(latency_cfg) 24 | 25 | if {"$version" == "v1"} { 26 | set golden_parameter_list "-parameter PULP_XPULP 0 -parameter FPU 0 -parameter PULP_ZFINX 0" 27 | } else { 28 | set golden_parameter_list "-parameter COREV_PULP $pulp_cfg -parameter FPU $fpu_cfg -parameter ZFINX $zfinx_cfg -parameter FPU_ADDMUL_LAT $latency_cfg -parameter FPU_OTHERS_LAT $latency_cfg" 29 | } 30 | 31 | read_design -SV09 -replace -noelaborate -golden -File ./golden.src 32 | 33 | elaborate_design -golden -root $top_module $golden_parameter_list 34 | 35 | read_design -SV09 -replace -noelaborate -revised -File ./revised.src 36 | 37 | elaborate_design -revised -root $top_module -parameter COREV_PULP $pulp_cfg -parameter FPU $fpu_cfg -parameter ZFINX $zfinx_cfg -parameter FPU_ADDMUL_LAT $latency_cfg -parameter FPU_OTHERS_LAT $latency_cfg 38 | 39 | report_design_data 40 | 41 | if {"$top_module" == "cv32e40p_core"} { 42 | add_ignored_outputs apu_req_o -Both 43 | add_ignored_outputs apu_operands_o* -Both 44 | add_ignored_outputs apu_op_o* -Both 45 | add_ignored_outputs apu_flags_o* -Both 46 | add_ignored_outputs apu_busy_o -Revised 47 | } 48 | 49 | write_hier_compare_dofile hier_compare_r2r.do -constraint -replace 50 | 51 | run_hier_compare hier_compare_r2r.do -ROOT_module $top_module $top_module 52 | 53 | report_hier_compare_result -all -usage > $summary_log 54 | report_verification -verbose -hier >> $summary_log 55 | report_hier_compare_result -NONEQuivalent -usage > $summary_log.noneq.rpt 56 | 57 | exit 0 58 | -------------------------------------------------------------------------------- /example_tb/core/mem_stall/mem_stall.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 ETH Zürich and University of Bologna 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | // This routine enables random stalls on both I-MEM and D-MEM 18 | void activate_random_stall(void) 19 | { 20 | // Address vector for rnd_stall_reg, to control memory stalls/interrupt 21 | volatile unsigned int *rnd_stall_reg_ptr[16]; 22 | 23 | // Setup the address vector 24 | rnd_stall_reg_ptr[0] = (unsigned int *) 0x16000000; 25 | for (int i = 1; i < 16; i++) { 26 | rnd_stall_reg_ptr[i] = rnd_stall_reg_ptr[i-1] + 1; // It is a pointer to int ("+ 1" means "the next int") 27 | } 28 | 29 | /* The interposition of the stall generator between CPU and MEM should happen BEFORE the stall generetor is active */ 30 | // Interpose the stall generator between CPU and D-MEM (rnd_stall_reg[1]) 31 | *rnd_stall_reg_ptr[1] = 0x01; 32 | // Interpose the stall generator between CPU and I-MEM (rnd_stall_reg[0]) 33 | *rnd_stall_reg_ptr[0] = 0x01; 34 | 35 | // DATA MEMORY 36 | // Set max n. stalls on both GNT and VALID for RANDOM mode (rnd_stall_reg[5]) 37 | *rnd_stall_reg_ptr[5] = 0x0a; 38 | // Set n. stalls on GNT (rnd_stall_reg[7]) 39 | *rnd_stall_reg_ptr[7] = 0x00; 40 | // Set n. stalls on VALID (rnd_stall_reg[9]) 41 | *rnd_stall_reg_ptr[9] = 0x00; 42 | 43 | // INSTRUCTION MEMORY 44 | // Set max n. stalls on both GNT and VALID for RANDOM mode (rnd_stall_reg[4]) 45 | *rnd_stall_reg_ptr[4] = 0x0a; 46 | // Set n. stalls on GNT (rnd_stall_reg[6]) 47 | *rnd_stall_reg_ptr[6] = 0x00; 48 | // Set n. stalls on VALID (rnd_stall_reg[8]) 49 | *rnd_stall_reg_ptr[8] = 0x00; 50 | 51 | /* Activating stalls on D and I Mem has to be done as last operation. Do not change the order. */ 52 | // Set stall mode on D-MEM (off=0, standard=1, random=2) (rnd_stall_reg[3]) 53 | *rnd_stall_reg_ptr[3] = 0x02; 54 | // Set stall mode on I-MEM (off=0, standard=1, random=2) (rnd_stall_reg[2]) 55 | *rnd_stall_reg_ptr[2] = 0x02; 56 | } 57 | -------------------------------------------------------------------------------- /scripts/lint/proc_dumpAutoCheckSummary.tcl: -------------------------------------------------------------------------------- 1 | proc dumpAutoCheckSummary { filename } { 2 | namespace import -force Autocheck::* 3 | if { [catch { set fp [open $filename a] } msg] } { 4 | puts "Unable to open $filename : $msg" 5 | exit 1 6 | } 7 | 8 | set typecnt 0 9 | #--------- Find types --------------------------------------- 10 | set checks [GetChecks] 11 | while { [set check [GetNext $checks]] != "" } { 12 | set type [GetType $check] 13 | set severity($type) [GetSeverity $check] 14 | lappend types $type 15 | } 16 | set types [lsort [lrmdups $types]] 17 | #--------- Collect data for each type ----------------------- 18 | foreach type $types { 19 | set cnt 0 20 | set cnt_waiv 0 21 | set cnt_viol 0 22 | set cnt_caut 0 23 | set cnt_inconcl 0 24 | set cnt_info 0 25 | set cnt_eval 0 26 | set cnt_off 0 27 | set cnt_def 0 28 | set checks [GetChecks] 29 | while { [set check [GetNext $checks]] != "" } { 30 | if {[GetType $check] == $type} { 31 | # debug 32 | #puts $fp "[GetType $check]" 33 | #puts $fp "[GetStatus $check]" 34 | #puts $fp "[GetSeverity $check]" 35 | ### DM ### increment different counters depending of status 36 | if {[GetStatus $check] == "Waived"} { 37 | incr cnt_waiv 38 | } else { 39 | set Severity [GetSeverity $check] 40 | switch $Severity { 41 | Violation {incr cnt_viol} 42 | Caution {incr cnt_caut} 43 | Inconclusive {incr cnt_inconcl} 44 | } 45 | ### DM ### add other (off, ...) if needed 46 | } 47 | } 48 | } 49 | 50 | ### DM ### only prints when waived exist / or when violation or inconclusive 51 | if {$cnt_waiv != 0} { 52 | puts $fp "# ** Waived:\t$type ($cnt_waiv)" 53 | puts "# ** Waived:\t$type ($cnt_waiv)" 54 | } 55 | if {$cnt_viol != 0} { 56 | puts $fp "# ** Violation:\t$type ($cnt_viol)" 57 | puts "# ** Violation:\t$type ($cnt_viol)" 58 | } 59 | if {$cnt_caut != 0} { 60 | puts $fp "# ** Caution:\t$type ($cnt_caut)" 61 | puts "# ** Caution:\t$type ($cnt_caut)" 62 | } 63 | if {$cnt_inconcl != 0} { 64 | puts $fp "# ** Inconclusive:\t$type ($cnt_inconcl)" 65 | puts "# ** Inconclusive:\t$type ($cnt_inconcl)" 66 | } 67 | ### DM ### add other (caution, off, ...) if needed 68 | 69 | } 70 | puts $fp "==============================================" 71 | puts $fp " [llength $types] Types; [GetCount $checks] Checks" 72 | close $fp 73 | } 74 | 75 | -------------------------------------------------------------------------------- /docs/source/glossary.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright 2024 OpenHW Group and Dolphin Design 3 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 4 | 5 | Licensed under the Solderpad Hardware License v 2.1 (the "License"); 6 | you may not use this file except in compliance with the License, or, 7 | at your option, the Apache License version 2.0. 8 | You may obtain a copy of the License at 9 | 10 | https://solderpad.org/licenses/SHL-2.1/ 11 | 12 | Unless required by applicable law or agreed to in writing, any work 13 | distributed under the License is distributed on an "AS IS" BASIS, 14 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | See the License for the specific language governing permissions and 16 | limitations under the License. 17 | 18 | .. _glossary: 19 | 20 | Glossary 21 | ======== 22 | 23 | * **ALU**: Arithmetic/Logic Unit 24 | * **ASIC**: Application-Specific Integrated Circuit 25 | * **Byte**: 8-bit data item 26 | * **CPU**: Central Processing Unit, processor 27 | * **CSR**: Control and Status Register 28 | * **Custom extension**: Non-Standard extension to the RISC-V base instruction set (RISC-V Instruction Set Manual, Volume I: User-Level ISA) 29 | * **EX**: Instruction Execute 30 | * **FPGA**: Field Programmable Gate Array 31 | * **FPU**: Floating Point Unit 32 | * **Halfword**: 16-bit data item 33 | * **Halfword aligned address**: An address is halfword aligned if it is divisible by 2 34 | * **ID**: Instruction Decode 35 | * **IF**: Instruction Fetch (:ref:`instruction-fetch`) 36 | * **ISA**: Instruction Set Architecture 37 | * **KGE**: kilo gate equivalents (NAND2) 38 | * **LSU**: Load Store Unit (:ref:`load-store-unit`) 39 | * **M-Mode**: Machine Mode (RISC-V Instruction Set Manual, Volume II: Privileged Architecture) 40 | * **OBI**: Open Bus Interface 41 | * **PC**: Program Counter 42 | * **PULP platform**: Parallel Ultra Low Power Platform () 43 | * **RV32C**: RISC-V Compressed (C extension) 44 | * **RV32F**: RISC-V Floating Point (F extension) 45 | * **SIMD**: Single Instruction/Multiple Data 46 | * **Standard extension**: Standard extension to the RISC-V base instruction set (RISC-V Instruction Set Manual, Volume I: User-Level ISA) 47 | * **WARL**: Write Any Values, Reads Legal Values 48 | * **WB**: Write Back of instruction results 49 | * **WLRL**: Write/Read Only Legal Values 50 | * **Word**: 32-bit data item 51 | * **Word aligned address**: An address is word aligned if it is divisible by 4 52 | * **WPRI**: Reserved Writes Preserve Values, Reads Ignore Values 53 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/fall_through_register.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Fall-through register with a simple stream-like ready/valid handshake. 12 | // This register does not cut combinatorial paths on any signals: in case the module at its output 13 | // is ready to accept data within the same clock cycle, they are forwarded. Use this module to get a 14 | // 'default ready' behavior towards the input. 15 | module fall_through_register #( 16 | parameter type T = logic // Vivado requires a default value for type parameters. 17 | ) ( 18 | input logic clk_i, // Clock 19 | input logic rst_ni, // Asynchronous active-low reset 20 | input logic clr_i, // Synchronous clear 21 | input logic testmode_i, // Test mode to bypass clock gating 22 | // Input port 23 | input logic valid_i, 24 | output logic ready_o, 25 | input T data_i, 26 | // Output port 27 | output logic valid_o, 28 | input logic ready_i, 29 | output T data_o 30 | ); 31 | 32 | logic fifo_empty, 33 | fifo_full; 34 | 35 | fifo_v2 #( 36 | .FALL_THROUGH (1'b1), 37 | .DATA_WIDTH ($size(T)), 38 | .DEPTH (1), 39 | .dtype (T) 40 | ) i_fifo ( 41 | .clk_i (clk_i), 42 | .rst_ni (rst_ni), 43 | .flush_i (clr_i), 44 | .testmode_i (testmode_i), 45 | .full_o (fifo_full), 46 | .empty_o (fifo_empty), 47 | .alm_full_o ( ), 48 | .alm_empty_o ( ), 49 | .data_i (data_i), 50 | .push_i (valid_i & ~fifo_full), 51 | .data_o (data_o), 52 | .pop_i (ready_i & ~fifo_empty) 53 | ); 54 | 55 | assign ready_o = ~fifo_full; 56 | assign valid_o = ~fifo_empty; 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /ci/Jenkinsfile: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 ETH Zurich 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | * 16 | */ 17 | 18 | node ('centos7' + ' && !vm1-centos7'){ 19 | try { 20 | stage('Preparation') { 21 | withEnv(['PATH+WHATEVER=/home/balasr/.local/bin:/home/balasr/.riscv/bin']) { 22 | checkout scm 23 | sh 'pip install --user junit-xml' 24 | sh 'git submodule update --init --recursive' 25 | dir("tb/core") { 26 | sh 'make fpnew/src/fpnew_pkg.sv' 27 | } 28 | } 29 | } 30 | stage('Build Firmware') { 31 | withEnv(['PATH+WHATEVER=/home/balasr/.local/bin:/home/balasr/.riscv/bin', 32 | 'RISCV=/home/balasr/.riscv']) { 33 | dir("tb/core") { 34 | sh "make firmware/firmware.hex" 35 | } 36 | dir("tb/dm") { 37 | sh "make prog/test.hex" 38 | } 39 | } 40 | } 41 | stage('Build RTL') { 42 | dir("tb/core") { 43 | sh "make vsim-all" 44 | } 45 | dir("tb/dm") { 46 | sh "make vsim-all" 47 | } 48 | } 49 | 50 | stage('Run Tests') { 51 | dir("tb/core") { 52 | sh "make firmware-vsim-run 2>&1 | tee test.log" 53 | } 54 | sh "./ci/rv32tests-to-junit.py -i tb/core/test.log -o rv32_test_report.xml" 55 | 56 | withEnv(['PATH+WHATEVER=/home/balasr/.local/bin:/home/balasr/.riscv/bin', 57 | 'RISCV=/home/balasr/.riscv']) { 58 | sh "./ci/run-openocd-compliance.sh" 59 | sh "./ci/openocd-to-junit.py -i openocd.log -o openocd_test_report.xml" 60 | 61 | } 62 | } 63 | 64 | } catch (e) { 65 | currentBuild.result = "FAILED" 66 | echo "SENDING E-MAIL" 67 | notifyFailed() 68 | throw e 69 | } finally { 70 | junit '*.xml' 71 | } 72 | } 73 | 74 | def notifyFailed() { 75 | emailext ( 76 | subject: "FAILED: Job '${env.JOB_NAME} [${env.BUILD_NUMBER}]'", 77 | body: """

FAILED: Job '${env.JOB_NAME} [${env.BUILD_NUMBER}]':

78 |

Check console output at "${env.JOB_NAME} [${env.BUILD_NUMBER}]"

""", 79 | recipientProviders: [[$class: 'DevelopersRecipientProvider']] 80 | ) 81 | } 82 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/deprecated/rrarbiter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Author: Michael Schaffner , ETH Zurich 12 | // Date: 16.08.2018 13 | // Description: Fair round robin arbiter with lock feature. 14 | // 15 | // The rrarbiter employs fair round robin arbitration - i.e. the priorities 16 | // rotate each cycle. 17 | // 18 | // The lock-in feature prevents the arbiter from changing the arbitration 19 | // decision when the arbiter is disabled. I.e., the index of the first request 20 | // that wins the arbitration will be locked until en_i is asserted again. 21 | // 22 | // Dependencies: relies on rr_arb_tree from common_cells. 23 | 24 | module rrarbiter #( 25 | parameter int unsigned NUM_REQ = 64, 26 | parameter bit LOCK_IN = 1'b0 27 | ) ( 28 | input logic clk_i, 29 | input logic rst_ni, 30 | 31 | input logic flush_i, // clears arbiter state 32 | input logic en_i, // arbiter enable 33 | input logic [NUM_REQ-1:0] req_i, // request signals 34 | 35 | output logic [NUM_REQ-1:0] ack_o, // acknowledge signals 36 | output logic vld_o, // request ack'ed 37 | output logic [$clog2(NUM_REQ)-1:0] idx_o // idx output 38 | ); 39 | 40 | logic req; 41 | assign vld_o = (|req_i) & en_i; 42 | 43 | rr_arb_tree #( 44 | .NumIn ( NUM_REQ ), 45 | .DataWidth ( 1 ), 46 | .LockIn ( LOCK_IN )) 47 | i_rr_arb_tree ( 48 | .clk_i ( clk_i ), 49 | .rst_ni ( rst_ni ), 50 | .flush_i ( flush_i ), 51 | .rr_i ( '0 ), 52 | .req_i ( req_i ), 53 | .gnt_o ( ack_o ), 54 | .data_i ( '0 ), 55 | .gnt_i ( en_i & req ), 56 | .req_o ( req ), 57 | .data_o ( ), 58 | .idx_o ( idx_o ) 59 | ); 60 | 61 | endmodule : rrarbiter 62 | -------------------------------------------------------------------------------- /scripts/riscv_isa_formal/README.md: -------------------------------------------------------------------------------- 1 | # RISC-V ISA Formal Verification 2 | 3 | RISC-V ISA Formal Verification methodology has been used with Siemens Questa Processor tool and its RISC-V ISA Processor Verification app. 4 | 5 | ## Configurations 6 | 7 | | Top Parameters | XP | XPF0 | XPF1 | XPF2 | XPZF0 | XPZF1 | XPZF2 | 8 | | :----------------- | :----: |:-------: | :------: | :------: | :-------: | :-------: | :-------: | 9 | | COREV_PULP | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 10 | | COREV_CLUSTER | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | | FPU | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 12 | | ZFINX | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 13 | | FPU_ADDMUL_LAT | 0 | 0 | 1 | 2 | 0 | 1 | 2 | 14 | | FPU_OTHERS_LAT | 0 | 0 | 1 | 2 | 0 | 1 | 2 | 15 | 16 | ## Tool apps 17 | 18 | - PRC : Property Checking 19 | - QTF : Quantify 20 | - VCI : Verification Coverage Integration 21 | 22 | ## Prove modes 23 | 24 | - DEF : Control path verification of all instructions and datapath verification of all instructions except multiplication, division or floating point ones 25 | - DPM : Data path verification of multiplication/ division instructions 26 | - DPF : Data path verification of floating-point instructions 27 | 28 | ## Directory Structure of this Repo 29 | 30 | - Makefile 31 | - launch_command_example 32 | 33 | ### verif 34 | Contains all files to create assertions and to launch different tool apps on different configurations and using different modes. 35 | 36 | > [!CAUTION] 37 | > core_checker.sv contains proprietary information and is only available to Siemens Questa Processor customers. 38 | > Once Questa Processor licenses have been purchased, this file can be requested to Siemens support center. 39 | 40 | ## How to launch a run 41 | 42 | > [!CAUTION] 43 | > Siemens Questa Processor 2024.2 and above must be used. 44 | 45 | - Locally clone cv32e40p github repository or make a symbolic link to an existing repo. 46 | - launch following command:
47 | make GUI=1 APP=PRC CONF=XP MODE=DEF NAME=v1_8_0 VERBOSE=1 PREPARE=1 all >&! run_gui-PRC-cfg_XP-mode_DEF-v1_8_0.log 48 | - or use launch_command_example to launch different runs in parallel. 49 | 50 | ## Commands to launch assertion checks for each configuration 51 | 52 | - XP : PRC app with DEF and DPM modes 53 | - XPF[0,1,2] and XPZF[0,1,2] : PRC app with DEF, DPM and DPF modes 54 | -------------------------------------------------------------------------------- /ci/rv32tests-to-junit.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # Copyright 2020 ETH Zurich 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | # 17 | # Author: Robert Balas 18 | 19 | import sys, getopt 20 | from junit_xml import * 21 | 22 | 23 | def main(argv): 24 | inputfile = '' 25 | outputfile = '' 26 | 27 | try: 28 | opts, args = getopt.getopt(argv,"hi:o:",["ifile=","ofile="]) 29 | except getopt.GetoptError: 30 | print ('rv32tests-to-junit.py -i -o ') 31 | sys.exit(2) 32 | for opt, arg in opts: 33 | if opt == '-h': 34 | print ('rv32tests-to-junit.py -i -o ') 35 | sys.exit() 36 | elif opt in ("-i", "--ifile"): 37 | inputfile = arg 38 | elif opt in ("-o", "--ofile"): 39 | outputfile = arg 40 | 41 | test_strings = defaultdict(list) 42 | current_testname = '' 43 | 44 | test_cases = [] 45 | current_test_case = None 46 | 47 | with open(inputfile, 'r') as infile: 48 | for line in infile: 49 | if 'Test Begin' in line: 50 | current_testname = line.split('#')[1] 51 | if 'Test End' in line: 52 | current_testname = "" 53 | if current_testname != "": 54 | test_strings[current_testname].append(line) 55 | 56 | for k,v in test_strings.items(): 57 | #test_cases.append(TestCase('Test1', stdout=''.join(v))) 58 | current_test_case = TestCase(k, stdout=''.join(v)) 59 | error_msg = "" 60 | for line in v: 61 | if 'Assertion violation' in line: 62 | error_msg += line; 63 | 64 | if error_msg: 65 | current_test_case.add_error_info(error_msg) 66 | 67 | test_cases.append(current_test_case) 68 | 69 | ts = TestSuite("riscv-compliance", test_cases) 70 | # pretty printing is on by default but can be disabled using prettyprint=False 71 | with open(outputfile, 'w') as outfile: 72 | TestSuite.to_file(outfile, [ts]) 73 | 74 | if __name__ == "__main__": 75 | main(sys.argv[1:]) 76 | -------------------------------------------------------------------------------- /example_tb/core/interrupt/isr.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 ETH Zurich 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | * 16 | */ 17 | 18 | #ifndef FIRMWARE_H 19 | #define FIRMWARE_H 20 | 21 | #include 22 | #include 23 | 24 | // irq.c 25 | uint32_t *irq(uint32_t *regs, uint32_t irqs); 26 | void timer_irq_handler(void); 27 | // print.c 28 | void print_chr(char ch); 29 | void print_str(const char *p); 30 | void print_dec(unsigned int val); 31 | void print_hex(unsigned int val, int digits); 32 | 33 | // sieve.c 34 | void sieve(void); 35 | 36 | // multest.c 37 | uint32_t hard_mul(uint32_t a, uint32_t b); 38 | uint32_t hard_mulh(uint32_t a, uint32_t b); 39 | uint32_t hard_mulhsu(uint32_t a, uint32_t b); 40 | uint32_t hard_mulhu(uint32_t a, uint32_t b); 41 | void multest(void); 42 | 43 | // stats.c 44 | void stats(void); 45 | 46 | //R/W 47 | static inline void writew(uint32_t val, volatile uint32_t *addr); 48 | 49 | void software_irq_handler(void) __attribute__ ((interrupt)); 50 | void timer_irq_handler(void) __attribute__ ((interrupt)); 51 | void external_irq_handler(void) __attribute__ ((interrupt)); 52 | 53 | void fast0_irq_handler(void) __attribute__ ((interrupt)); 54 | void fast1_irq_handler(void) __attribute__ ((interrupt)); 55 | void fast2_irq_handler(void) __attribute__ ((interrupt)); 56 | void fast3_irq_handler(void) __attribute__ ((interrupt)); 57 | void fast4_irq_handler(void) __attribute__ ((interrupt)); 58 | void fast5_irq_handler(void) __attribute__ ((interrupt)); 59 | void fast6_irq_handler(void) __attribute__ ((interrupt)); 60 | void fast7_irq_handler(void) __attribute__ ((interrupt)); 61 | void fast8_irq_handler(void) __attribute__ ((interrupt)); 62 | void fast9_irq_handler(void) __attribute__ ((interrupt)); 63 | void fast10_irq_handler(void) __attribute__ ((interrupt)); 64 | void fast11_irq_handler(void) __attribute__ ((interrupt)); 65 | void fast12_irq_handler(void) __attribute__ ((interrupt)); 66 | void fast13_irq_handler(void) __attribute__ ((interrupt)); 67 | void fast14_irq_handler(void) __attribute__ ((interrupt)); 68 | void fast14_irq_handler(void) __attribute__ ((interrupt)); 69 | void fast15_irq_handler(void) __attribute__ ((interrupt)); 70 | #endif 71 | -------------------------------------------------------------------------------- /scripts/riscv_isa_formal/launch_command_example: -------------------------------------------------------------------------------- 1 | # Setup tool and licenses 2 | #source SourceMe 3 | 4 | set instructions="v1_8_0"; set name_cmd="NAME=${instructions} ; 5 | 6 | set config=XP ; set config_cmd="CONF=${config}" 7 | set config=XPF0 ; set config_cmd="CONF=${config}" 8 | set config=XPF1 ; set config_cmd="CONF=${config}" 9 | set config=XPF2 ; set config_cmd="CONF=${config}" 10 | set config=XPZF0 ; set config_cmd="CONF=${config}" 11 | set config=XPZF1 ; set config_cmd="CONF=${config}" 12 | set config=XPZF2 ; set config_cmd="CONF=${config}" 13 | 14 | set app=PRC ; set app_cmd="APP=${app}" 15 | set app=QTF ; set app_cmd="APP=${app}" 16 | set app=VCI ; set app_cmd="APP=${app}" 17 | 18 | set mode=DEF ; set mode_cmd="MODE=${mode}" 19 | set mode=DPM ; set mode_cmd="MODE=${mode}" 20 | set mode=DPF ; set mode_cmd="MODE=${mode}" 21 | 22 | # Prepare the working directory (verif files and design copy) or reuse existing one (no copy) 23 | set prepare="" 24 | set prepare="PREPARE=1" 25 | 26 | set verbose="" 27 | set verbose="VERBOSE=1" 28 | 29 | set timeout="" 30 | set timeout="DBG=1800" 31 | 32 | # Interactive or batch run on local server 33 | set gui="gui" ; set gui_cmd="GUI=1" 34 | set gui="batch" ; set gui_cmd="" 35 | 36 | set my_time = `date '+%Y-%m-%d-%Hh%Mm%Ss'` ; set logname=run_${gui}-${app}-cfg_${config}-mode_${mode}-${instructions}-${my_time}.log ; echo "\n vi ${logname}\n" ; \ 37 | echo "make ${gui_cmd} ${app_cmd} ${config_cmd} ${mode_cmd} ${name_cmd} ${verbose} ${prepare} ${timeout} all\n" > ${logname} && echo "" >>& ${logname} ; \ 38 | /usr/bin/time make ${gui_cmd} ${app_cmd} ${config_cmd} ${mode_cmd} ${name_cmd} ${verbose} ${prepare} ${timeout} all >> & ! ${logname} & 39 | 40 | # Interactive or batch run on compute farm server using LSF 41 | set gui="lsf" ; set gui_cmd="" ; set queue="long" 42 | set gui="lsf_gui" ; set gui_cmd="GUI=1" ; set queue="gui -XF" 43 | set gui="lsf_gui" ; set gui_cmd="GUI=1" ; set queue="gui -XF -Is -tty" 44 | 45 | set nb_cpus="1" 46 | set nb_cpus="2" 47 | set nb_cpus="4" 48 | set nb_cpus="8" 49 | set nb_cpus="12" 50 | set nb_cpus="16" 51 | set nb_cpus="24" 52 | set nb_cpus="32" 53 | set nb_cpus="36" 54 | set nb_cpus="48" 55 | 56 | set my_time = `date '+%Y-%m-%d-%Hh%Mm%Ss'` ; set logname=run_${gui}-${app}-cfg_${config}-mode_${mode}-${instructions}-${my_time}.log ; echo "\n vi ${logname}\n" ; \ 57 | echo "make ${gui_cmd} ${app_cmd} ${config_cmd} ${mode_cmd} ${name_cmd} ${verbose} ${prepare} ${timeout} all\n" > ${logname} && echo "" >>& ${logname} ; \ 58 | bsub -J ${app}-cfg_${config}-mode_${mode}-${instructions} -P cv32e40p -q ${queue} -oo ${logname} -n ${nb_cpus} -R "select[cpuf>=15.0] span[hosts=1] rusage[mem=64G]" make ${gui_cmd} ${app_cmd} ${config_cmd} ${mode_cmd} ${name_cmd} ${verbose} ${prepare} ${timeout} all 59 | -------------------------------------------------------------------------------- /cv32e40p_manifest.flist: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Copyright 2020 OpenHW Group 4 | // 5 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // https://solderpad.org/licenses/ 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | // 17 | /////////////////////////////////////////////////////////////////////////////// 18 | // 19 | // Manifest for the CV32E40P RTL model. 20 | // - Intended to be used by both synthesis and simulation. 21 | // - Relevent synthesis and simulation scripts/Makefiles must set the shell 22 | // ENV variable DESIGN_RTL_DIR as required. 23 | // 24 | /////////////////////////////////////////////////////////////////////////////// 25 | 26 | +incdir+${DESIGN_RTL_DIR}/include 27 | +incdir+${DESIGN_RTL_DIR}/../bhv 28 | +incdir+${DESIGN_RTL_DIR}/../bhv/include 29 | +incdir+${DESIGN_RTL_DIR}/../sva 30 | 31 | ${DESIGN_RTL_DIR}/include/cv32e40p_apu_core_pkg.sv 32 | ${DESIGN_RTL_DIR}/include/cv32e40p_fpu_pkg.sv 33 | ${DESIGN_RTL_DIR}/include/cv32e40p_pkg.sv 34 | ${DESIGN_RTL_DIR}/cv32e40p_if_stage.sv 35 | ${DESIGN_RTL_DIR}/cv32e40p_cs_registers.sv 36 | ${DESIGN_RTL_DIR}/cv32e40p_register_file_ff.sv 37 | ${DESIGN_RTL_DIR}/cv32e40p_load_store_unit.sv 38 | ${DESIGN_RTL_DIR}/cv32e40p_id_stage.sv 39 | ${DESIGN_RTL_DIR}/cv32e40p_aligner.sv 40 | ${DESIGN_RTL_DIR}/cv32e40p_decoder.sv 41 | ${DESIGN_RTL_DIR}/cv32e40p_compressed_decoder.sv 42 | ${DESIGN_RTL_DIR}/cv32e40p_fifo.sv 43 | ${DESIGN_RTL_DIR}/cv32e40p_prefetch_buffer.sv 44 | ${DESIGN_RTL_DIR}/cv32e40p_hwloop_regs.sv 45 | ${DESIGN_RTL_DIR}/cv32e40p_mult.sv 46 | ${DESIGN_RTL_DIR}/cv32e40p_int_controller.sv 47 | ${DESIGN_RTL_DIR}/cv32e40p_ex_stage.sv 48 | ${DESIGN_RTL_DIR}/cv32e40p_alu_div.sv 49 | ${DESIGN_RTL_DIR}/cv32e40p_alu.sv 50 | ${DESIGN_RTL_DIR}/cv32e40p_ff_one.sv 51 | ${DESIGN_RTL_DIR}/cv32e40p_popcnt.sv 52 | ${DESIGN_RTL_DIR}/cv32e40p_apu_disp.sv 53 | ${DESIGN_RTL_DIR}/cv32e40p_controller.sv 54 | ${DESIGN_RTL_DIR}/cv32e40p_obi_interface.sv 55 | ${DESIGN_RTL_DIR}/cv32e40p_prefetch_controller.sv 56 | ${DESIGN_RTL_DIR}/cv32e40p_sleep_unit.sv 57 | ${DESIGN_RTL_DIR}/cv32e40p_core.sv 58 | 59 | ${DESIGN_RTL_DIR}/cv32e40p_top.sv 60 | 61 | ${DESIGN_RTL_DIR}/../bhv/cv32e40p_sim_clock_gate.sv 62 | ${DESIGN_RTL_DIR}/../bhv/include/cv32e40p_tracer_pkg.sv 63 | ${DESIGN_RTL_DIR}/../bhv/cv32e40p_tb_wrapper.sv 64 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/popcount.sv: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2013-2018 ETH Zurich, University of Bologna 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Manuel Eggimann 12 | 13 | // Description: This module calculates the hamming weight (number of ones) in 14 | // its input vector using a balanced binary adder tree. Recursive instantiation 15 | // is used to build the tree. Any unsigned INPUT_WIDTH larger or equal 2 is 16 | // legal. The module pads the signal internally to the next power of two. The 17 | // output result width is ceil(log2(INPUT_WIDTH))+1. 18 | 19 | module popcount #( 20 | parameter int unsigned INPUT_WIDTH = 256, 21 | localparam int unsigned PopcountWidth = $clog2(INPUT_WIDTH)+1 22 | ) ( 23 | input logic [INPUT_WIDTH-1:0] data_i, 24 | output logic [PopcountWidth-1:0] popcount_o 25 | ); 26 | 27 | localparam int unsigned PaddedWidth = 1 << $clog2(INPUT_WIDTH); 28 | 29 | logic [PaddedWidth-1:0] padded_input; 30 | logic [PopcountWidth-2:0] left_child_result, right_child_result; 31 | 32 | //Zero pad the input to next power of two 33 | always_comb begin 34 | padded_input = '0; 35 | padded_input[INPUT_WIDTH-1:0] = data_i; 36 | end 37 | 38 | //Recursive instantiation to build binary adder tree 39 | if (INPUT_WIDTH == 1) begin : single_node 40 | assign left_child_result = 1'b0; 41 | assign right_child_result = padded_input[0]; 42 | end else if (INPUT_WIDTH == 2) begin : leaf_node 43 | assign left_child_result = padded_input[1]; 44 | assign right_child_result = padded_input[0]; 45 | end else begin : non_leaf_node 46 | popcount #(.INPUT_WIDTH(PaddedWidth / 2)) 47 | left_child( 48 | .data_i(padded_input[PaddedWidth-1:PaddedWidth/2]), 49 | .popcount_o(left_child_result)); 50 | 51 | popcount #(.INPUT_WIDTH(PaddedWidth / 2)) 52 | right_child( 53 | .data_i(padded_input[PaddedWidth/2-1:0]), 54 | .popcount_o(right_child_result)); 55 | end 56 | 57 | //Output assignment 58 | assign popcount_o = left_child_result + right_child_result; 59 | 60 | endmodule : popcount 61 | -------------------------------------------------------------------------------- /ci/openocd-to-junit.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # Copyright 2020 ETH Zurich 4 | # 5 | # Licensed under the Apache License, Version 2.0 (the "License"); 6 | # you may not use this file except in compliance with the License. 7 | # You may obtain a copy of the License at 8 | # 9 | # http://www.apache.org/licenses/LICENSE-2.0 10 | # 11 | # Unless required by applicable law or agreed to in writing, software 12 | # distributed under the License is distributed on an "AS IS" BASIS, 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | # See the License for the specific language governing permissions and 15 | # limitations under the License. 16 | # 17 | # Author: Robert Balas 18 | 19 | import sys, getopt 20 | from junit_xml import * 21 | 22 | 23 | def main(argv): 24 | inputfile = '' 25 | outputfile = '' 26 | 27 | try: 28 | opts, args = getopt.getopt(argv,"hi:o:",["ifile=","ofile="]) 29 | except getopt.GetoptError: 30 | print ('openocd-to-junit.py -i -o ') 31 | sys.exit(2) 32 | for opt, arg in opts: 33 | if opt == '-h': 34 | print ('openocd-to-junit.py -i -o ') 35 | sys.exit() 36 | elif opt in ("-i", "--ifile"): 37 | inputfile = arg 38 | elif opt in ("-o", "--ofile"): 39 | outputfile = arg 40 | 41 | test_strings = defaultdict(list) 42 | test_timestamps = {} 43 | current_testname = '' 44 | 45 | test_cases = [] 46 | current_test_case = None 47 | 48 | ocd_stdout = '' 49 | 50 | with open(inputfile, 'r') as infile: 51 | for line in infile: 52 | if 'Info' in line and 'riscv013_test_compliance()' in line: 53 | print(line.split(' ')) 54 | current_testname = ' '.join(line.split(' ')[7:]) 55 | test_strings[current_testname].append(line) 56 | test_timestamps[current_testname] = line.split(' ')[3] 57 | 58 | ocd_stdout += line 59 | 60 | for k,v in test_strings.items(): 61 | current_test_case = TestCase(k, stdout=''.join(v), 62 | timestamp=test_timestamps[k]) 63 | error_msg = "" 64 | for line in v: 65 | if 'FAILED' in line: 66 | error_msg += line; 67 | 68 | if error_msg: 69 | current_test_case.add_error_info(error_msg) 70 | 71 | test_cases.append(current_test_case) 72 | 73 | ts = TestSuite("openocd-compliance", test_cases, stdout=ocd_stdout) 74 | # pretty printing is on by default but can be disabled using prettyprint=False 75 | with open(outputfile, 'w') as outfile: 76 | TestSuite.to_file(outfile, [ts]) 77 | 78 | if __name__ == "__main__": 79 | main(sys.argv[1:]) 80 | -------------------------------------------------------------------------------- /rtl/cv32e40p_popcnt.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | //////////////////////////////////////////////////////////////////////////////// 12 | // Engineer: Andreas Traber - atraber@student.ethz.ch // 13 | // // 14 | // Additional contributions by: // 15 | // Davide Schiavone - pschiavo@iis.ee.ethz.ch // 16 | // // 17 | // Design Name: cv32e40p_popcnt // 18 | // Project Name: RI5CY // 19 | // Language: SystemVerilog // 20 | // // 21 | // Description: Count the number of '1's in a word // 22 | // // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module cv32e40p_popcnt ( 26 | input logic [31:0] in_i, 27 | output logic [ 5:0] result_o 28 | ); 29 | 30 | logic [15:0][1:0] cnt_l1; 31 | logic [ 7:0][2:0] cnt_l2; 32 | logic [ 3:0][3:0] cnt_l3; 33 | logic [ 1:0][4:0] cnt_l4; 34 | 35 | genvar l, m, n, p; 36 | generate 37 | for (l = 0; l < 16; l++) begin : gen_cnt_l1 38 | assign cnt_l1[l] = {1'b0, in_i[2*l]} + {1'b0, in_i[2*l+1]}; 39 | end 40 | endgenerate 41 | 42 | generate 43 | for (m = 0; m < 8; m++) begin : gen_cnt_l2 44 | assign cnt_l2[m] = {1'b0, cnt_l1[2*m]} + {1'b0, cnt_l1[2*m+1]}; 45 | end 46 | endgenerate 47 | 48 | generate 49 | for (n = 0; n < 4; n++) begin : gen_cnt_l3 50 | assign cnt_l3[n] = {1'b0, cnt_l2[2*n]} + {1'b0, cnt_l2[2*n+1]}; 51 | end 52 | endgenerate 53 | 54 | generate 55 | for (p = 0; p < 2; p++) begin : gen_cnt_l4 56 | assign cnt_l4[p] = {1'b0, cnt_l3[2*p]} + {1'b0, cnt_l3[2*p+1]}; 57 | end 58 | endgenerate 59 | 60 | assign result_o = {1'b0, cnt_l4[0]} + {1'b0, cnt_l4[1]}; 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/max_counter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Up/down counter that tracks its maximum value 12 | 13 | module max_counter #( 14 | parameter int unsigned WIDTH = 4 15 | ) ( 16 | input logic clk_i, 17 | input logic rst_ni, 18 | input logic clear_i, // synchronous clear for counter 19 | input logic clear_max_i, // synchronous clear for maximum value 20 | input logic en_i, // enable the counter 21 | input logic load_i, // load a new value 22 | input logic down_i, // downcount, default is up 23 | input logic [WIDTH-1:0] delta_i, // counter delta 24 | input logic [WIDTH-1:0] d_i, 25 | output logic [WIDTH-1:0] q_o, 26 | output logic [WIDTH-1:0] max_o, 27 | output logic overflow_o, 28 | output logic overflow_max_o 29 | ); 30 | logic [WIDTH-1:0] max_d, max_q; 31 | logic overflow_max_d, overflow_max_q; 32 | 33 | delta_counter #( 34 | .WIDTH (WIDTH), 35 | .STICKY_OVERFLOW (1'b1) 36 | ) i_counter ( 37 | .clk_i, 38 | .rst_ni, 39 | .clear_i, 40 | .en_i, 41 | .load_i, 42 | .down_i, 43 | .delta_i, 44 | .d_i, 45 | .q_o, 46 | .overflow_o 47 | ); 48 | 49 | always_comb begin 50 | max_d = max_q; 51 | max_o = max_q; 52 | overflow_max_d = overflow_max_q; 53 | if (clear_max_i) begin 54 | max_d = '0; 55 | overflow_max_d = 1'b0; 56 | end else if (q_o > max_q) begin 57 | max_d = q_o; 58 | max_o = q_o; 59 | if (overflow_o) begin 60 | overflow_max_d = 1'b1; 61 | end 62 | end 63 | end 64 | 65 | assign overflow_max_o = overflow_max_q; 66 | 67 | always_ff @(posedge clk_i, negedge rst_ni) begin 68 | if (!rst_ni) begin 69 | max_q <= '0; 70 | overflow_max_q <= 1'b0; 71 | end else begin 72 | max_q <= max_d; 73 | overflow_max_q <= overflow_max_d; 74 | end 75 | end 76 | 77 | endmodule 78 | -------------------------------------------------------------------------------- /scripts/slec/tb_src/data_assert2.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Dolphin Design 2 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | // 4 | // Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | // you may not use this file except in compliance with the License, or, 6 | // at your option, the Apache License version 2.0. 7 | // You may obtain a copy of the License at 8 | // 9 | // https://solderpad.org/licenses/SHL-2.1/ 10 | // 11 | // Unless required by applicable law or agreed to in writing, any work 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | 17 | //////////////////////////////////////////////////////////////////////////////////// 18 | // // 19 | // Contributors: Yoann Pruvost, Dolphin Design // 20 | // Pascal Gouedo, Dolphin Design // 21 | // // 22 | // Description: OBI protocol emulation for CV32E40P data interface // 23 | // // 24 | //////////////////////////////////////////////////////////////////////////////////// 25 | 26 | module data_assert ( 27 | input logic clk_i, 28 | input logic rst_ni, 29 | 30 | // Data memory interface 31 | input logic data_req_o, 32 | input logic data_gnt_i, 33 | input logic data_rvalid_i 34 | ); 35 | 36 | /***************** 37 | * Helpers logic * 38 | *****************/ 39 | int s_outstanding_cnt; 40 | 41 | always_ff @(posedge clk_i or negedge rst_ni) begin 42 | if(!rst_ni) begin 43 | s_outstanding_cnt <= 0; 44 | end else if (data_req_o & data_gnt_i & data_rvalid_i) begin 45 | s_outstanding_cnt <= s_outstanding_cnt; 46 | end else if (data_req_o & data_gnt_i) begin 47 | s_outstanding_cnt <= s_outstanding_cnt + 1; 48 | end else if (data_rvalid_i) begin 49 | s_outstanding_cnt <= s_outstanding_cnt - 1; 50 | end 51 | end 52 | 53 | /********** 54 | * Assume * 55 | **********/ 56 | // Concerning lint_grnt 57 | property no_grnt_when_no_req; 58 | @(posedge clk_i) disable iff(!rst_ni) 59 | !data_req_o |-> !data_gnt_i; 60 | endproperty 61 | 62 | property no_rvalid_if_no_pending_req; 63 | @(posedge clk_i) disable iff(!rst_ni) 64 | s_outstanding_cnt < 1 |-> !data_rvalid_i; 65 | endproperty 66 | 67 | assume_no_grnt_when_no_req: assume property(no_grnt_when_no_req); 68 | assume_no_rvalid_if_no_pending_req: assume property(no_rvalid_if_no_pending_req); 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/stream_fifo.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Georg Rutishauser 12 | 13 | module stream_fifo #( 14 | /// FIFO is in fall-through mode 15 | parameter bit FALL_THROUGH = 1'b0, 16 | /// Default data width if the fifo is of type logic 17 | parameter int unsigned DATA_WIDTH = 32, 18 | /// Depth can be arbitrary from 0 to 2**32 19 | parameter int unsigned DEPTH = 8, 20 | parameter type T = logic [DATA_WIDTH-1:0], 21 | // DO NOT OVERWRITE THIS PARAMETER 22 | parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1 23 | ) ( 24 | input logic clk_i, // Clock 25 | input logic rst_ni, // Asynchronous reset active low 26 | input logic flush_i, // flush the fifo 27 | input logic testmode_i, // test_mode to bypass clock gating 28 | output logic [ADDR_DEPTH-1:0] usage_o, // fill pointer 29 | // input interface 30 | input T data_i, // data to push into the fifo 31 | input logic valid_i, // input data valid 32 | output logic ready_o, // fifo is not full 33 | // output interface 34 | output T data_o, // output data 35 | output logic valid_o, // fifo is not empty 36 | input logic ready_i // pop head from fifo 37 | ); 38 | 39 | logic push, pop; 40 | logic empty, full; 41 | 42 | assign push = valid_i & ~full; 43 | assign pop = ready_i & ~empty; 44 | assign ready_o = ~full; 45 | assign valid_o = ~empty; 46 | 47 | fifo_v3 #( 48 | .FALL_THROUGH (FALL_THROUGH), 49 | .DATA_WIDTH (DATA_WIDTH), 50 | .DEPTH (DEPTH), 51 | .dtype(T) 52 | ) fifo_i ( 53 | .clk_i, 54 | .rst_ni, 55 | .flush_i, 56 | .testmode_i, 57 | .full_o (full), 58 | .empty_o (empty), 59 | .usage_o, 60 | .data_i, 61 | .push_i (push), 62 | .data_o, 63 | .pop_i (pop) 64 | ); 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /scripts/slec/tb_src/insn_assert2.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Dolphin Design 2 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 3 | // 4 | // Licensed under the Solderpad Hardware License v 2.1 (the "License"); 5 | // you may not use this file except in compliance with the License, or, 6 | // at your option, the Apache License version 2.0. 7 | // You may obtain a copy of the License at 8 | // 9 | // https://solderpad.org/licenses/SHL-2.1/ 10 | // 11 | // Unless required by applicable law or agreed to in writing, any work 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | 17 | //////////////////////////////////////////////////////////////////////////////////// 18 | // // 19 | // Contributors: Yoann Pruvost, Dolphin Design // 20 | // Pascal Gouedo, Dolphin Design // 21 | // // 22 | // Description: OBI protocol emulation for CV32E40P data interface // 23 | // // 24 | //////////////////////////////////////////////////////////////////////////////////// 25 | 26 | module insn_assert ( 27 | input logic clk_i, 28 | input logic rst_ni, 29 | // Instruction memory interface 30 | input logic instr_req_o, 31 | input logic instr_gnt_i, 32 | input logic instr_rvalid_i 33 | ); 34 | 35 | /***************** 36 | * Helpers logic * 37 | *****************/ 38 | int s_outstanding_cnt; 39 | 40 | always_ff @(posedge clk_i or negedge rst_ni) begin 41 | if(!rst_ni) begin 42 | s_outstanding_cnt <= 0; 43 | end else if (instr_req_o & instr_gnt_i & instr_rvalid_i) begin 44 | s_outstanding_cnt <= s_outstanding_cnt; 45 | end else if (instr_req_o & instr_gnt_i) begin 46 | s_outstanding_cnt <= s_outstanding_cnt + 1; 47 | end else if (instr_rvalid_i) begin 48 | s_outstanding_cnt <= s_outstanding_cnt - 1; 49 | end 50 | end 51 | 52 | /********** 53 | * Assume * 54 | **********/ 55 | // Concerning lint_grnt 56 | property no_grnt_when_no_req; 57 | @(posedge clk_i) disable iff(!rst_ni) 58 | !instr_req_o |-> !instr_gnt_i; 59 | endproperty 60 | 61 | property no_rvalid_if_no_pending_req; 62 | @(posedge clk_i) disable iff(!rst_ni) 63 | s_outstanding_cnt < 1 |-> !instr_rvalid_i; 64 | endproperty 65 | 66 | assume_no_grnt_when_no_req: assume property(no_grnt_when_no_req); 67 | assume_no_rvalid_if_no_pending_req: assume property(no_rvalid_if_no_pending_req); 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /rtl/vendor/pulp_platform_common_cells/src/cf_math_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2016 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | /// cf_math_pkg: Constant Function Implementations of Mathematical Functions for HDL Elaboration 12 | /// 13 | /// This package contains a collection of mathematical functions that are commonly used when defining 14 | /// the value of constants in HDL code. These functions are implemented as Verilog constants 15 | /// functions. Introduced in Verilog 2001 (IEEE Std 1364-2001), a constant function (§ 10.3.5) is a 16 | /// function whose value can be evaluated at compile time or during elaboration. A constant function 17 | /// must be called with arguments that are constants. 18 | package cf_math_pkg; 19 | 20 | /// Ceiled Division of Two Natural Numbers 21 | /// 22 | /// Returns the quotient of two natural numbers, rounded towards plus infinity. 23 | function automatic integer ceil_div (input longint dividend, input longint divisor); 24 | automatic longint remainder; 25 | 26 | // pragma translate_off 27 | `ifndef VERILATOR 28 | if (dividend < 0) begin 29 | $fatal(1, "Dividend %0d is not a natural number!", dividend); 30 | end 31 | 32 | if (divisor < 0) begin 33 | $fatal(1, "Divisor %0d is not a natural number!", divisor); 34 | end 35 | 36 | if (divisor == 0) begin 37 | $fatal(1, "Division by zero!"); 38 | end 39 | `endif 40 | // pragma translate_on 41 | 42 | remainder = dividend; 43 | for (ceil_div = 0; remainder > 0; ceil_div++) begin 44 | remainder = remainder - divisor; 45 | end 46 | endfunction 47 | 48 | /// Index width required to be able to represent up to `num_idx` indices as a binary 49 | /// encoded signal. 50 | /// Ensures that the minimum width if an index signal is `1`, regardless of parametrization. 51 | /// 52 | /// Sample usage in type definition: 53 | /// As parameter: 54 | /// `parameter type idx_t = logic[cf_math_pkg::idx_width(NumIdx)-1:0]` 55 | /// As typedef: 56 | /// `typedef logic [cf_math_pkg::idx_width(NumIdx)-1:0] idx_t` 57 | function automatic integer unsigned idx_width (input integer unsigned num_idx); 58 | return (num_idx > 32'd1) ? unsigned'($clog2(num_idx)) : 32'd1; 59 | endfunction 60 | 61 | endpackage 62 | --------------------------------------------------------------------------------