├── .gitignore ├── .gitlab-ci.yml ├── LICENSE ├── README.md ├── TODO.txt ├── apu ├── busses │ ├── axi_adapter.sv │ ├── multicore_arbiter.sv │ └── wishbone_adapter.sv ├── clint │ ├── clint.sv │ └── clint_wrapper.sv └── plic │ ├── plic.sv │ ├── plic_cmptree.sv │ ├── plic_gateway.sv │ └── plic_wrapper.sv ├── core ├── common_components │ ├── clz.sv │ ├── cva5_fifo.sv │ ├── cycler.sv │ ├── lfsr.sv │ ├── one_hot_to_integer.sv │ ├── priority_encoder.sv │ ├── ram │ │ ├── lutram_1w_1r.sv │ │ ├── lutram_1w_mr.sv │ │ ├── sdp_ram.sv │ │ ├── sdp_ram_padded.sv │ │ └── tdp_ram.sv │ ├── round_robin.sv │ ├── set_clr_reg_with_rst.sv │ ├── toggle_memory.sv │ └── toggle_memory_set.sv ├── core_arbiter.sv ├── cva5.sv ├── decode_and_issue.sv ├── execution_units │ ├── alu_unit.sv │ ├── barrel_shifter.sv │ ├── branch_comparator.sv │ ├── branch_unit.sv │ ├── csr_unit.sv │ ├── custom_unit.sv │ ├── div_core.sv │ ├── div_unit.sv │ ├── fp_unit │ │ ├── divider │ │ │ ├── carry_save_shift.sv │ │ │ ├── fp_div_core.sv │ │ │ ├── on_the_fly.sv │ │ │ └── q_lookup.sv │ │ ├── fp_add.sv │ │ ├── fp_div.sv │ │ ├── fp_div_sqrt_wrapper.sv │ │ ├── fp_madd_wrapper.sv │ │ ├── fp_mul.sv │ │ ├── fp_normalize_rounding_top.sv │ │ ├── fp_prenormalize.sv │ │ ├── fp_preprocessing.sv │ │ ├── fp_roundup.sv │ │ ├── fp_rs_preprocess.sv │ │ ├── fp_special_case_detection.sv │ │ ├── fp_sqrt.sv │ │ ├── fp_sqrt_core.sv │ │ ├── fp_sticky_tracking.sv │ │ ├── fp_wb2fp_misc.sv │ │ ├── fp_wb2int_misc.sv │ │ └── fpu_top.sv │ ├── gc_unit.sv │ ├── load_store_unit │ │ ├── addr_hash.sv │ │ ├── amo_alu.sv │ │ ├── amo_unit.sv │ │ ├── dcache_inv.sv │ │ ├── dcache_noinv.sv │ │ ├── load_store_queue.sv │ │ ├── load_store_unit.sv │ │ └── store_queue.sv │ └── mul_unit.sv ├── fetch_stage │ ├── branch_predictor.sv │ ├── fetch.sv │ ├── icache.sv │ ├── icache_tag_banks.sv │ └── ras.sv ├── fp_writeback.sv ├── instruction_metadata_and_id_management.sv ├── memory_sub_units │ ├── avalon_master.sv │ ├── axi_master.sv │ ├── local_mem_sub_unit.sv │ └── wishbone_master.sv ├── mmu │ ├── dtlb.sv │ ├── itlb.sv │ ├── mmu.sv │ └── perms_check.sv ├── register_file.sv ├── register_free_list.sv ├── renamer.sv ├── types_and_interfaces │ ├── csr_types.sv │ ├── cva5_config.sv │ ├── cva5_types.sv │ ├── external_interfaces.sv │ ├── fpu_types.sv │ ├── internal_interfaces.sv │ ├── opcodes.sv │ └── riscv_types.sv └── writeback.sv ├── debug_module ├── debug_cfg_types.sv ├── debug_interfaces.sv ├── debug_module.sv ├── jtag_module.sv ├── jtag_register.sv └── jtag_registers.sv ├── docs └── FCCM_Presentation │ ├── CVA5.png │ └── CVA5_FCCM_Workshop.pptx ├── examples ├── litex │ └── litex_wrapper.sv ├── sw │ ├── main.c │ └── mem.mif └── xilinx │ ├── clint.tcl │ ├── cva5_top.v │ ├── cva5_wrapper.sv │ ├── nexys_sys.tcl │ ├── package_as_ip.tcl │ └── plic.tcl ├── test_benches └── verilator │ ├── AXIMem.cc │ ├── AXIMem.h │ ├── CVA5Tracer.cc │ ├── CVA5Tracer.h │ ├── SimMem.cc │ ├── SimMem.h │ ├── cva5_sim.cc │ ├── cva5_sim.sv │ └── sim_stats.sv └── tools ├── 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