├── bench ├── README ├── or1200_monitor.v └── or1200_monitor_defines.v ├── doc ├── Makefile ├── docbook-xsl.css ├── docbook.xsl ├── gen-docinfo.pl ├── img │ ├── addr_translation.gif │ ├── core_arch.gif │ ├── core_interfaces.gif │ ├── cpu_fpu_dsp.gif │ ├── data_cache_diag.gif │ ├── debug_unit_diag.gif │ ├── dev_interface_cycles.gif │ ├── inst_cache_diag.gif │ ├── inst_mmu_diag.gif │ ├── interrupt_controller.gif │ ├── or_family.gif │ ├── powerup_seq.gif │ ├── powerup_seq_gatedclk.gif │ ├── tlb_diag.gif │ ├── watchpoint_trigger.gif │ ├── wb_block_read.gif │ ├── wb_compatible.png │ ├── wb_read.gif │ ├── wb_rw.gif │ └── wb_write.gif ├── openrisc1200_spec.doc ├── openrisc1200_spec.odt ├── openrisc1200_spec.pdf ├── openrisc1200_spec.txt ├── openrisc1200_spec_0.7_jp.doc ├── openrisc1200_spec_0.7_jp.pdf ├── openrisc1200_supplementary_prm.odt ├── openrisc1200_supplementary_prm.pdf └── preprocess.pl ├── lib └── README ├── lint ├── bin │ ├── README │ └── run_lint ├── log │ └── README └── run │ └── README ├── rtl └── verilog │ ├── or1200_alu.v │ ├── or1200_amultp2_32x32.v │ ├── or1200_cfgr.v │ ├── or1200_cpu.v │ ├── or1200_ctrl.v │ ├── or1200_dc_fsm.v │ ├── or1200_dc_ram.v │ ├── or1200_dc_tag.v │ ├── or1200_dc_top.v │ ├── or1200_defines.v │ ├── or1200_dmmu_tlb.v │ ├── or1200_dmmu_top.v │ ├── or1200_dpram.v │ ├── or1200_dpram_256x32.v │ ├── or1200_dpram_32x32.v │ ├── or1200_du.v │ ├── or1200_except.v │ ├── or1200_fpu.v │ ├── or1200_fpu_addsub.v │ ├── or1200_fpu_arith.v │ ├── or1200_fpu_div.v │ ├── or1200_fpu_fcmp.v │ ├── or1200_fpu_intfloat_conv.v │ ├── or1200_fpu_intfloat_conv_except.v │ ├── or1200_fpu_mul.v │ ├── or1200_fpu_post_norm_addsub.v │ ├── or1200_fpu_post_norm_div.v │ ├── or1200_fpu_post_norm_intfloat_conv.v │ ├── or1200_fpu_post_norm_mul.v │ ├── or1200_fpu_pre_norm_addsub.v │ ├── or1200_fpu_pre_norm_div.v │ ├── or1200_fpu_pre_norm_mul.v │ ├── or1200_freeze.v │ ├── or1200_genpc.v │ ├── or1200_gmultp2_32x32.v │ ├── or1200_ic_fsm.v │ ├── or1200_ic_ram.v │ ├── or1200_ic_tag.v │ ├── or1200_ic_top.v │ ├── or1200_if.v │ ├── or1200_immu_tlb.v │ ├── or1200_immu_top.v │ ├── or1200_iwb_biu.v │ ├── or1200_lsu.v │ ├── or1200_mem2reg.v │ ├── or1200_mult_mac.v │ ├── or1200_operandmuxes.v │ ├── or1200_pic.v │ ├── or1200_pm.v │ ├── or1200_qmem_top.v │ ├── or1200_reg2mem.v │ ├── or1200_rf.v │ ├── or1200_rfram_generic.v │ ├── or1200_sb.v │ ├── or1200_sb_fifo.v │ ├── or1200_spram.v │ ├── or1200_spram_1024x32.v │ ├── or1200_spram_1024x32_bw.v │ ├── or1200_spram_1024x8.v │ ├── or1200_spram_128x32.v │ ├── or1200_spram_2048x32.v │ ├── or1200_spram_2048x32_bw.v │ ├── or1200_spram_2048x8.v │ ├── or1200_spram_256x21.v │ ├── or1200_spram_32_bw.v │ ├── or1200_spram_32x24.v │ ├── or1200_spram_512x20.v │ ├── or1200_spram_64x14.v │ ├── or1200_spram_64x22.v │ ├── or1200_spram_64x24.v │ ├── or1200_sprs.v │ ├── or1200_top.v │ ├── or1200_tpram_32x32.v │ ├── or1200_tt.v │ ├── or1200_wb_biu.v │ ├── or1200_wbmux.v │ ├── or1200_xcv_ram32x8d.v │ └── timescale.v ├── sim └── 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