├── bench ├── README ├── or1200_monitor.v └── or1200_monitor_defines.v ├── doc ├── Makefile ├── docbook-xsl.css ├── docbook.xsl ├── gen-docinfo.pl ├── img │ ├── addr_translation.gif │ ├── core_arch.gif │ ├── core_interfaces.gif │ ├── cpu_fpu_dsp.gif │ ├── data_cache_diag.gif │ ├── debug_unit_diag.gif │ ├── dev_interface_cycles.gif │ ├── inst_cache_diag.gif │ ├── inst_mmu_diag.gif │ ├── interrupt_controller.gif │ ├── or_family.gif │ ├── powerup_seq.gif │ ├── powerup_seq_gatedclk.gif │ ├── tlb_diag.gif │ ├── watchpoint_trigger.gif │ ├── wb_block_read.gif │ ├── wb_compatible.png │ ├── wb_read.gif │ ├── wb_rw.gif │ └── wb_write.gif ├── openrisc1200_spec.doc ├── openrisc1200_spec.odt ├── openrisc1200_spec.pdf ├── openrisc1200_spec.txt ├── openrisc1200_spec_0.7_jp.doc ├── openrisc1200_spec_0.7_jp.pdf ├── openrisc1200_supplementary_prm.odt ├── openrisc1200_supplementary_prm.pdf └── preprocess.pl ├── lib └── README ├── lint ├── bin │ ├── README │ └── run_lint ├── log │ └── README └── run │ └── README ├── rtl └── verilog │ ├── or1200_alu.v │ ├── or1200_amultp2_32x32.v │ ├── or1200_cfgr.v │ ├── or1200_cpu.v │ ├── or1200_ctrl.v │ ├── or1200_dc_fsm.v │ ├── or1200_dc_ram.v │ ├── or1200_dc_tag.v │ ├── or1200_dc_top.v │ ├── or1200_defines.v │ ├── or1200_dmmu_tlb.v │ ├── or1200_dmmu_top.v │ ├── or1200_dpram.v │ ├── or1200_dpram_256x32.v │ ├── or1200_dpram_32x32.v │ ├── or1200_du.v │ ├── or1200_except.v │ ├── or1200_fpu.v │ ├── or1200_fpu_addsub.v │ ├── or1200_fpu_arith.v │ ├── or1200_fpu_div.v │ ├── or1200_fpu_fcmp.v │ ├── or1200_fpu_intfloat_conv.v │ ├── or1200_fpu_intfloat_conv_except.v │ ├── or1200_fpu_mul.v │ ├── or1200_fpu_post_norm_addsub.v │ ├── or1200_fpu_post_norm_div.v │ ├── or1200_fpu_post_norm_intfloat_conv.v │ ├── or1200_fpu_post_norm_mul.v │ ├── or1200_fpu_pre_norm_addsub.v │ ├── or1200_fpu_pre_norm_div.v │ ├── or1200_fpu_pre_norm_mul.v │ ├── or1200_freeze.v │ ├── or1200_genpc.v │ ├── or1200_gmultp2_32x32.v │ ├── or1200_ic_fsm.v │ ├── or1200_ic_ram.v │ ├── or1200_ic_tag.v │ ├── or1200_ic_top.v │ ├── or1200_if.v │ ├── or1200_immu_tlb.v │ ├── or1200_immu_top.v │ ├── or1200_iwb_biu.v │ ├── or1200_lsu.v │ ├── or1200_mem2reg.v │ ├── or1200_mult_mac.v │ ├── or1200_operandmuxes.v │ ├── or1200_pic.v │ ├── or1200_pm.v │ ├── or1200_qmem_top.v │ ├── or1200_reg2mem.v │ ├── or1200_rf.v │ ├── or1200_rfram_generic.v │ ├── or1200_sb.v │ ├── or1200_sb_fifo.v │ ├── or1200_spram.v │ ├── or1200_spram_1024x32.v │ ├── or1200_spram_1024x32_bw.v │ ├── or1200_spram_1024x8.v │ ├── or1200_spram_128x32.v │ ├── or1200_spram_2048x32.v │ ├── or1200_spram_2048x32_bw.v │ ├── or1200_spram_2048x8.v │ ├── or1200_spram_256x21.v │ ├── or1200_spram_32_bw.v │ ├── or1200_spram_32x24.v │ ├── or1200_spram_512x20.v │ ├── or1200_spram_64x14.v │ ├── or1200_spram_64x22.v │ ├── or1200_spram_64x24.v │ ├── or1200_sprs.v │ ├── or1200_top.v │ ├── or1200_tpram_32x32.v │ ├── or1200_tt.v │ ├── or1200_wb_biu.v │ ├── or1200_wbmux.v │ ├── or1200_xcv_ram32x8d.v │ └── timescale.v ├── sim └── README └── syn └── synopsys ├── bin ├── README ├── read_design.inc ├── run_syn └── top.scr ├── log └── README ├── out └── README └── run └── README /bench/README: -------------------------------------------------------------------------------- 1 | Test bench for or1200 is available in opencores cvs under or1k/orp. 2 | -------------------------------------------------------------------------------- /bench/or1200_monitor_defines.v: -------------------------------------------------------------------------------- 1 | 2 | // 3 | // Top of TB 4 | // 5 | `define TB_TOP orpsoc_tb 6 | 7 | // 8 | // Top of DUT 9 | // 10 | `define DUT_TOP `TB_TOP.dut 11 | 12 | // 13 | // Top of OR1200 inside test bench 14 | // 15 | `define OR1200_TOP `DUT_TOP.or1200_top0 16 | 17 | // 18 | // Define to enable lookup file generation 19 | // 20 | //`define OR1200_MONITOR_LOOKUP 21 | 22 | // 23 | // Define to enable SPR access log file generation 24 | // 25 | `define OR1200_MONITOR_SPRS 26 | 27 | // 28 | // Enable logging of state during execution 29 | // 30 | `define OR1200_MONITOR_EXEC_STATE 31 | 32 | // 33 | // Enable disassembly of instructions in execution state log 34 | // 35 | //`define OR1200_MONITOR_EXEC_LOG_DISASSEMBLY 36 | 37 | // 38 | // Enable verbose report l.nops (to both general log file and stdout) 39 | // 40 | `define OR1200_MONITOR_VERBOSE_NOPS 41 | 42 | // 43 | // Enable monitoring of control and execution flow (experimental) 44 | // 45 | //`define OR1200_SYSTEM_CHECKER 46 | 47 | // Can either individually enable things above, or usually have the scripts 48 | // running the simulation pass the PROCESSOR_MONITOR_ENABLE_LOGS define to 49 | // enable them all. 50 | 51 | `ifdef PROCESSOR_MONITOR_ENABLE_LOGS 52 | `define OR1200_MONITOR_EXEC_STATE 53 | `define OR1200_MONITOR_SPRS 54 | `define OR1200_MONITOR_LOOKUP 55 | `endif 56 | 57 | // 58 | // Memory coherence checking (double check instruction in fetch stage against 59 | // what is in memory.) Useful for cache controller development. 60 | // 61 | //`define MEM_COHERENCE_CHECK 62 | 63 | // 64 | // Top of OR1200 inside test bench 65 | // 66 | `define CPU or1200 67 | `define CPU_cpu or1200_cpu 68 | `define CPU_rf or1200_rf 69 | `define CPU_except or1200_except 70 | `define CPU_ctrl or1200_ctrl 71 | `define CPU_sprs or1200_sprs 72 | `define CPU_immu_top or1200_immu_top 73 | `define CPU_immu_tlb or1200_immu_tlb 74 | `define CPU_CORE_CLK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk 75 | 76 | 77 | `define OR1K_OPCODE_POS 31:26 78 | `define OR1K_J_BR_IMM_POS 25:0 79 | `define OR1K_RD_POS 25:21 80 | `define OR1K_RA_POS 20:16 81 | `define OR1K_RB_POS 15:11 82 | `define OR1K_ALU_OP_POS 3:0 83 | 84 | `define OR1K_SHROT_OP_POS 7:6 85 | `define OR1K_SHROTI_IMM_POS 5:0 86 | `define OR1K_SF_OP 25:21 87 | 88 | `define OR1K_XSYNC_OP_POS 25:21 89 | -------------------------------------------------------------------------------- /doc/Makefile: -------------------------------------------------------------------------------- 1 | ASCIIDOC=asciidoc 2 | XSLTPROC=xsltproc 3 | DBLATEX=dblatex 4 | 5 | RM ?= rm -f 6 | CP ?= cp 7 | MV ?= mv 8 | CAT ?= cat 9 | GEN-DOCINFO=gen-docinfo.pl 10 | PREPROCESS=preprocess.pl 11 | 12 | ifndef PERL_PATH 13 | PERL_PATH = /usr/bin/perl 14 | endif 15 | 16 | ASCIIDOC_EXTRA += -a docinfo 17 | 18 | SPEC_TXT=openrisc1200_spec.txt 19 | SPEC_HTML=$(patsubst %.txt,%.html,$(SPEC_TXT)) 20 | SPEC_XML=$(patsubst %.txt,%.xml,$(SPEC_TXT)) 21 | SPEC_PDF=$(patsubst %.txt,%.pdf,$(SPEC_TXT)) 22 | 23 | SPEC_DOCINFO=$(patsubst %.txt,%-docinfo.xml,$(SPEC_TXT)) 24 | 25 | ifneq ($(findstring $(MAKEFLAGS),s),s) 26 | ifndef V 27 | QUIET_ASCIIDOC = @echo ' ' ASCIIDOC $@; 28 | QUIET_XSLTPROC = @echo ' ' XSLTPROC $@; 29 | QUIET_DBLATEX = @echo ' ' DBLATEX $@; 30 | QUIET_GEN-DOCINFO = @echo ' ' GEN-DOCINFO $@; 31 | QUIET_PREPROCESS = @echo ' ' PREPROCESS $<; 32 | export V 33 | endif 34 | endif 35 | 36 | all: html 37 | 38 | html: $(SPEC_HTML) 39 | pdf: $(SPEC_PDF) 40 | 41 | $(SPEC_DOCINFO): $(SPEC_TXT) $(GEN-DOCINFO) 42 | $(QUIET_GEN-DOCINFO)$(CAT) $< | \ 43 | $(PERL_PATH) -ne 'if (/__vstart__/../__vend__/) {print unless /__v(start|end)__/}' | \ 44 | $(PERL_PATH) $(GEN-DOCINFO) > $@ 45 | 46 | $(SPEC_TXT)+: $(SPEC_TXT) 47 | $(QUIET_PREPROCESS)$(PERL_PATH) $(PREPROCESS) $< > $@ 48 | 49 | $(SPEC_XML): $(SPEC_TXT)+ $(SPEC_DOCINFO) 50 | $(QUIET_ASCIIDOC)$(ASCIIDOC) $(ASCIIDOC_EXTRA) -b docbook $< 51 | 52 | XSLT = docbook.xsl 53 | XSLTOPTS = --xinclude --stringparam html.stylesheet docbook-xsl.css \ 54 | --stringparam section.autolabel 1 \ 55 | --stringparam section.label.includes.component.label 1 56 | 57 | $(SPEC_HTML): $(SPEC_XML) 58 | $(QUIET_XSLTPROC)$(RM) $@+ $@ && \ 59 | $(XSLTPROC) $(XSLTOPTS) -o $@+ $(XSLT) $< && \ 60 | $(MV) $@+ $@ 61 | 62 | DBLATEXOPTS = --param=doc.publisher.show=0 63 | 64 | $(SPEC_PDF): $(SPEC_XML) 65 | $(QUIET_DBLATEX)$(RM) $@+ $@ && \ 66 | $(DBLATEX) $(DBLATEXOPTS) -o $@+ \ 67 | -p /etc/asciidoc/dblatex/asciidoc-dblatex.xsl \ 68 | -s /etc/asciidoc/dblatex/asciidoc-dblatex.sty $< && \ 69 | $(MV) $@+ $@ 70 | 71 | clean: 72 | $(RM) *.xml *.xml+ *.html *.html+ 73 | $(RM) openrisc1200_spec.pdf+ openrisc1200_spec.txt+ 74 | 75 | .PHONY: all clean html 76 | -------------------------------------------------------------------------------- /doc/docbook-xsl.css: -------------------------------------------------------------------------------- 1 | /* 2 | CSS stylesheet for XHTML produced by DocBook XSL stylesheets. 3 | Tested with XSL stylesheets 1.61.2, 1.67.2 4 | */ 5 | 6 | span.strong { 7 | font-weight: bold; 8 | } 9 | 10 | body blockquote { 11 | margin-top: .75em; 12 | line-height: 1.5; 13 | margin-bottom: .75em; 14 | } 15 | 16 | html body { 17 | margin: 1em 5% 1em 5%; 18 | line-height: 1.2; 19 | font-family: sans-serif; 20 | } 21 | 22 | body div { 23 | margin: 0; 24 | } 25 | 26 | h1, h2, h3, h4, h5, h6, 27 | div.toc p b, 28 | div.list-of-figures p b, 29 | div.list-of-tables p b, 30 | div.abstract p.title 31 | { 32 | color: #527bbd; 33 | font-family: tahoma, verdana, sans-serif; 34 | } 35 | 36 | div.toc p:first-child, 37 | div.list-of-figures p:first-child, 38 | div.list-of-tables p:first-child, 39 | div.example p.title 40 | { 41 | margin-bottom: 0.2em; 42 | } 43 | 44 | body h1 { 45 | margin: .0em 0 0 -4%; 46 | line-height: 1.3; 47 | border-bottom: 2px solid silver; 48 | } 49 | 50 | body h2 { 51 | margin: 0.5em 0 0 -4%; 52 | line-height: 1.3; 53 | border-bottom: 2px solid silver; 54 | } 55 | 56 | body h3 { 57 | margin: .8em 0 0 -3%; 58 | line-height: 1.3; 59 | } 60 | 61 | body h4 { 62 | margin: .8em 0 0 -3%; 63 | line-height: 1.3; 64 | } 65 | 66 | body h5 { 67 | margin: .8em 0 0 -2%; 68 | line-height: 1.3; 69 | } 70 | 71 | body h6 { 72 | margin: .8em 0 0 -1%; 73 | line-height: 1.3; 74 | } 75 | 76 | body hr { 77 | border: none; /* Broken on IE6 */ 78 | } 79 | div.footnotes hr { 80 | border: 1px solid silver; 81 | } 82 | 83 | div.navheader th, div.navheader td, div.navfooter td { 84 | font-family: sans-serif; 85 | font-size: 0.9em; 86 | font-weight: bold; 87 | color: #527bbd; 88 | } 89 | div.navheader img, div.navfooter img { 90 | border-style: none; 91 | } 92 | div.navheader a, div.navfooter a { 93 | font-weight: normal; 94 | } 95 | div.navfooter hr { 96 | border: 1px solid silver; 97 | } 98 | 99 | body td { 100 | line-height: 1.2 101 | } 102 | 103 | body th { 104 | line-height: 1.2; 105 | } 106 | 107 | ol { 108 | line-height: 1.2; 109 | } 110 | 111 | ul, body dir, body menu { 112 | line-height: 1.2; 113 | } 114 | 115 | html { 116 | margin: 0; 117 | padding: 0; 118 | } 119 | 120 | body h1, body h2, body h3, body h4, body h5, body h6 { 121 | margin-left: 0 122 | } 123 | 124 | body pre { 125 | margin: 0.5em 10% 0.5em 1em; 126 | line-height: 1.0; 127 | color: navy; 128 | } 129 | 130 | tt.literal, code.literal { 131 | color: navy; 132 | font-family: sans-serif; 133 | } 134 | 135 | code.literal:before { content: "'"; } 136 | code.literal:after { content: "'"; } 137 | 138 | em { 139 | font-style: italic; 140 | color: #064; 141 | } 142 | 143 | div.literallayout p { 144 | padding: 0em; 145 | margin: 0em; 146 | } 147 | 148 | div.literallayout { 149 | font-family: monospace; 150 | margin: 0em; 151 | color: navy; 152 | border: 1px solid silver; 153 | background: #f4f4f4; 154 | padding: 0.5em; 155 | } 156 | 157 | .programlisting, .screen { 158 | border: 1px solid silver; 159 | background: #f4f4f4; 160 | margin: 0.5em 10% 0.5em 0; 161 | padding: 0.5em 1em; 162 | } 163 | 164 | div.sidebar { 165 | background: #ffffee; 166 | margin: 1.0em 10% 0.5em 0; 167 | padding: 0.5em 1em; 168 | border: 1px solid silver; 169 | } 170 | div.sidebar * { padding: 0; } 171 | div.sidebar div { margin: 0; } 172 | div.sidebar p.title { 173 | font-family: sans-serif; 174 | margin-top: 0.5em; 175 | margin-bottom: 0.2em; 176 | } 177 | 178 | div.bibliomixed { 179 | margin: 0.5em 5% 0.5em 1em; 180 | } 181 | 182 | div.glossary dt { 183 | font-weight: bold; 184 | } 185 | div.glossary dd p { 186 | margin-top: 0.2em; 187 | } 188 | 189 | dl { 190 | margin: .8em 0; 191 | line-height: 1.2; 192 | } 193 | 194 | dt { 195 | margin-top: 0.5em; 196 | } 197 | 198 | dt span.term { 199 | font-style: normal; 200 | color: navy; 201 | } 202 | 203 | div.variablelist dd p { 204 | margin-top: 0; 205 | } 206 | 207 | div.itemizedlist li, div.orderedlist li { 208 | margin-left: -0.8em; 209 | margin-top: 0.5em; 210 | } 211 | 212 | ul, ol { 213 | list-style-position: outside; 214 | } 215 | 216 | div.sidebar ul, div.sidebar ol { 217 | margin-left: 2.8em; 218 | } 219 | 220 | div.itemizedlist p.title, 221 | div.orderedlist p.title, 222 | div.variablelist p.title 223 | { 224 | margin-bottom: -0.8em; 225 | } 226 | 227 | div.revhistory table { 228 | border-collapse: collapse; 229 | border: none; 230 | } 231 | div.revhistory th { 232 | border: none; 233 | color: #527bbd; 234 | font-family: tahoma, verdana, sans-serif; 235 | } 236 | div.revhistory td { 237 | border: 1px solid silver; 238 | } 239 | 240 | /* Keep TOC and index lines close together. */ 241 | div.toc dl, div.toc dt, 242 | div.list-of-figures dl, div.list-of-figures dt, 243 | div.list-of-tables dl, div.list-of-tables dt, 244 | div.indexdiv dl, div.indexdiv dt 245 | { 246 | line-height: normal; 247 | margin-top: 0; 248 | margin-bottom: 0; 249 | } 250 | 251 | /* 252 | Table styling does not work because of overriding attributes in 253 | generated HTML. 254 | */ 255 | div.table table, 256 | div.informaltable table 257 | { 258 | margin-left: 0; 259 | margin-right: 5%; 260 | margin-bottom: 0.8em; 261 | } 262 | div.informaltable table 263 | { 264 | margin-top: 0.4em 265 | } 266 | div.table thead, 267 | div.table tfoot, 268 | div.table tbody, 269 | div.informaltable thead, 270 | div.informaltable tfoot, 271 | div.informaltable tbody 272 | { 273 | /* No effect in IE6. */ 274 | border-top: 2px solid #527bbd; 275 | border-bottom: 2px solid #527bbd; 276 | } 277 | div.table thead, div.table tfoot, 278 | div.informaltable thead, div.informaltable tfoot 279 | { 280 | font-weight: bold; 281 | } 282 | 283 | div.mediaobject img { 284 | border: 1px solid silver; 285 | margin-bottom: 0.8em; 286 | } 287 | div.figure p.title, 288 | div.table p.title 289 | { 290 | margin-top: 1em; 291 | margin-bottom: 0.4em; 292 | } 293 | 294 | @media print { 295 | div.navheader, div.navfooter { display: none; } 296 | } 297 | -------------------------------------------------------------------------------- /doc/docbook.xsl: -------------------------------------------------------------------------------- 1 | 3 | 4 | 5 | 6 | appendix nop 7 | article toc,title 8 | book toc,title,figure,table,example,equation 9 | part nop 10 | preface nop 11 | qandadiv nop 12 | qandaset nop 13 | reference toc,title 14 | section nop 15 | set toc 16 | 17 | 18 | -------------------------------------------------------------------------------- /doc/gen-docinfo.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | 3 | use warnings; 4 | use strict; 5 | 6 | my @keys = qw(number date author comment); 7 | my @revs; 8 | { 9 | local $/ = ''; 10 | 11 | while (<>) { 12 | my @values = split(/\|/); 13 | my %rev; 14 | foreach (@keys) { 15 | $rev{$_} = shift @values; 16 | $rev{$_} =~ s/^\s+|\s+$//g; 17 | } 18 | push @revs, \%rev; 19 | } 20 | } 21 | 22 | if (@revs) { 23 | print "\n"; 24 | foreach my $rev (@revs) { 25 | print " \n"; 26 | print " $rev->{number}\n"; 27 | print " $rev->{date}\n"; 28 | print " $rev->{author}\n"; 29 | print " \n"; 30 | print " $rev->{comment}\n"; 31 | print " \n"; 32 | print " \n"; 33 | } 34 | print "\n"; 35 | } 36 | 37 | -------------------------------------------------------------------------------- /doc/img/addr_translation.gif: -------------------------------------------------------------------------------- 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Preprocessing of the spec file. 3 | # So far the table with the instruction list is modified. 4 | # Output is printed to stdout. 5 | 6 | use warnings; 7 | use strict; 8 | use POSIX qw (ceil); 9 | 10 | if (@ARGV != 1) { 11 | print "Usage: preprocess.pl infile ('-' for stdin)\n"; 12 | exit 1; 13 | } 14 | 15 | my $infile = $ARGV[0]; 16 | 17 | if ($infile eq '-') { 18 | open(INPUT, '<-') or die $!; 19 | } else { 20 | open(INPUT, '<', $infile) or die $!; 21 | } 22 | 23 | my @inst_table; 24 | my $insts_per_col = 18; 25 | my $inst_line = 0; 26 | my $inst_header; 27 | my $inst_footer; 28 | 29 | while () { 30 | if (/^\| Instruction mnemonic/../^\|==/) { 31 | chomp; 32 | if (/^\| Instruction mnemonic/) { 33 | $inst_header = $_; 34 | next; 35 | } elsif (/^\|==/) { 36 | $inst_footer = $_; 37 | next; 38 | } 39 | if ($inst_line < $insts_per_col) { 40 | push @inst_table, $_; 41 | } else { 42 | $inst_table[$inst_line % $insts_per_col] .= "\t" . $_; 43 | } 44 | $inst_line++; 45 | } else { 46 | if (@inst_table) { 47 | # complete the rows that have their last column empty 48 | for (my $i = $inst_line % $insts_per_col; $i < $insts_per_col; $i++) { 49 | $inst_table[$i] .= "\t|\t|"; 50 | } 51 | my $cols = ceil($inst_line / $insts_per_col); 52 | print $inst_header x $cols . "\n"; 53 | print join("\n", @inst_table) . "\n"; 54 | print $inst_footer . "\n"; 55 | @inst_table = (); 56 | } 57 | print $_; 58 | } 59 | } 60 | close INPUT or die $!; 61 | -------------------------------------------------------------------------------- /lib/README: -------------------------------------------------------------------------------- 1 | This directory containts memory and standard cell libraries. However proprietary libraries are not in OpenCores CVS. -------------------------------------------------------------------------------- /lint/bin/README: -------------------------------------------------------------------------------- 1 | Linter script. For running linter, go to ../run. 2 | -------------------------------------------------------------------------------- /lint/bin/run_lint: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | nLint \ 3 | ../../rtl/verilog/or1200_alu.v \ 4 | ../../rtl/verilog/or1200_amultp2_32x32.v \ 5 | ../../rtl/verilog/or1200_cfgr.v \ 6 | ../../rtl/verilog/or1200_cpu.v \ 7 | ../../rtl/verilog/or1200_ctrl.v \ 8 | ../../rtl/verilog/or1200_dc_fsm.v \ 9 | ../../rtl/verilog/or1200_dc_ram.v \ 10 | ../../rtl/verilog/or1200_dc_tag.v \ 11 | ../../rtl/verilog/or1200_dc_top.v \ 12 | ../../rtl/verilog/or1200_defines.v \ 13 | ../../rtl/verilog/or1200_dmmu_tlb.v \ 14 | ../../rtl/verilog/or1200_dmmu_top.v \ 15 | ../../rtl/verilog/or1200_dpram_32x32.v \ 16 | ../../rtl/verilog/or1200_du.v \ 17 | ../../rtl/verilog/or1200_except.v \ 18 | ../../rtl/verilog/or1200_freeze.v \ 19 | ../../rtl/verilog/or1200_genpc.v \ 20 | ../../rtl/verilog/or1200_gmultp2_32x32.v \ 21 | ../../rtl/verilog/or1200_ic_fsm.v \ 22 | ../../rtl/verilog/or1200_ic_ram.v \ 23 | ../../rtl/verilog/or1200_ic_tag.v \ 24 | ../../rtl/verilog/or1200_ic_top.v \ 25 | ../../rtl/verilog/or1200_if.v \ 26 | ../../rtl/verilog/or1200_immu_tlb.v \ 27 | ../../rtl/verilog/or1200_immu_top.v \ 28 | ../../rtl/verilog/or1200_lsu.v \ 29 | ../../rtl/verilog/or1200_mem2reg.v \ 30 | ../../rtl/verilog/or1200_mult_mac.v \ 31 | ../../rtl/verilog/or1200_operandmuxes.v \ 32 | ../../rtl/verilog/or1200_pic.v \ 33 | ../../rtl/verilog/or1200_pm.v \ 34 | ../../rtl/verilog/or1200_reg2mem.v \ 35 | ../../rtl/verilog/or1200_rf.v \ 36 | ../../rtl/verilog/or1200_rfram_generic.v \ 37 | ../../rtl/verilog/or1200_sb.v \ 38 | ../../rtl/verilog/or1200_sb_fifo.v \ 39 | ../../rtl/verilog/or1200_spram_1024x32.v \ 40 | ../../rtl/verilog/or1200_spram_1024x8.v \ 41 | ../../rtl/verilog/or1200_spram_2048x32.v \ 42 | ../../rtl/verilog/or1200_spram_2048x8.v \ 43 | ../../rtl/verilog/or1200_spram_256x21.v \ 44 | ../../rtl/verilog/or1200_spram_512x20.v \ 45 | ../../rtl/verilog/or1200_spram_64x14.v \ 46 | ../../rtl/verilog/or1200_spram_64x22.v \ 47 | ../../rtl/verilog/or1200_spram_64x24.v \ 48 | ../../rtl/verilog/or1200_sprs.v \ 49 | ../../rtl/verilog/or1200_top.v \ 50 | ../../rtl/verilog/or1200_tpram_32x32.v \ 51 | ../../rtl/verilog/or1200_tt.v \ 52 | ../../rtl/verilog/or1200_wb_biu.v \ 53 | ../../rtl/verilog/or1200_wbmux.v \ 54 | ../../rtl/verilog/or1200_xcv_ram32x8d.v > ../log/nlint.log && \ 55 | mv nLintLog ../log & 56 | -------------------------------------------------------------------------------- /lint/log/README: -------------------------------------------------------------------------------- 1 | This directory will contain linter report after running linter. 2 | -------------------------------------------------------------------------------- /lint/run/README: -------------------------------------------------------------------------------- 1 | This directory is for running linter script. To run linter do the following: 2 | 3 | $ ../bin/run_lint 4 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_dc_ram.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's DC RAMs //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// Instatiation of DC RAM blocks. //// 10 | //// //// 11 | //// To Do: //// 12 | //// - make it smaller and faster //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // 45 | // $Log: or1200_dc_ram.v,v $ 46 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 47 | // Minor update: 48 | // Coding style changed. 49 | // 50 | 51 | // synopsys translate_off 52 | `include "timescale.v" 53 | // synopsys translate_on 54 | `include "or1200_defines.v" 55 | 56 | module or1200_dc_ram( 57 | // Reset and clock 58 | clk, rst, 59 | 60 | `ifdef OR1200_BIST 61 | // RAM BIST 62 | mbist_si_i, mbist_so_o, mbist_ctrl_i, 63 | `endif 64 | 65 | // Internal i/f 66 | addr, en, we, datain, dataout 67 | ); 68 | 69 | parameter dw = `OR1200_OPERAND_WIDTH; 70 | parameter aw = `OR1200_DCINDX; 71 | 72 | // 73 | // I/O 74 | // 75 | input clk; 76 | input rst; 77 | input [aw-1:0] addr; 78 | input en; 79 | input [3:0] we; 80 | input [dw-1:0] datain; 81 | output [dw-1:0] dataout; 82 | 83 | `ifdef OR1200_BIST 84 | // 85 | // RAM BIST 86 | // 87 | input mbist_si_i; 88 | input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control 89 | output mbist_so_o; 90 | `endif 91 | 92 | `ifdef OR1200_NO_DC 93 | 94 | // 95 | // Data cache not implemented 96 | // 97 | assign dataout = {dw{1'b0}}; 98 | `ifdef OR1200_BIST 99 | assign mbist_so_o = mbist_si_i; 100 | `endif 101 | 102 | `else 103 | 104 | // 105 | // Instantiation of RAM block 106 | // 107 | or1200_spram_32_bw # 108 | ( 109 | .aw(`OR1200_DCINDX), 110 | .dw(dw) 111 | ) 112 | dc_ram 113 | ( 114 | `ifdef OR1200_BIST 115 | // RAM BIST 116 | .mbist_si_i(mbist_si_i), 117 | .mbist_so_o(mbist_so_o), 118 | .mbist_ctrl_i(mbist_ctrl_i), 119 | `endif 120 | .clk(clk), 121 | .ce(en), 122 | .we(we), 123 | .addr(addr), 124 | .di(datain), 125 | .doq(dataout) 126 | ); 127 | `endif 128 | 129 | endmodule // or1200_dc_ram 130 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_dc_tag.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's DC TAG RAMs //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// Instatiation of data cache tag rams. //// 10 | //// //// 11 | //// To Do: //// 12 | //// - make it smaller and faster //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // $Log: or1200_dc_tag.v,v $ 45 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 46 | // Minor update: 47 | // Coding style changed. 48 | // 49 | 50 | // synopsys translate_off 51 | `include "timescale.v" 52 | // synopsys translate_on 53 | `include "or1200_defines.v" 54 | 55 | module or1200_dc_tag( 56 | // Clock and reset 57 | clk, rst, 58 | 59 | `ifdef OR1200_BIST 60 | // RAM BIST 61 | mbist_si_i, mbist_so_o, mbist_ctrl_i, 62 | `endif 63 | 64 | // Internal i/f 65 | addr, en, we, datain, tag_v, tag, dirty 66 | ); 67 | 68 | parameter dw = `OR1200_DCTAG_W+1; 69 | parameter aw = `OR1200_DCTAG; 70 | 71 | // 72 | // I/O 73 | // 74 | input clk; 75 | input rst; 76 | input [aw-1:0] addr; 77 | input en; 78 | input we; 79 | input [dw-1:0] datain; 80 | output tag_v; 81 | output [dw-3:0] tag; 82 | output dirty; 83 | 84 | 85 | `ifdef OR1200_BIST 86 | // 87 | // RAM BIST 88 | // 89 | input mbist_si_i; 90 | input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; 91 | output mbist_so_o; 92 | `endif 93 | 94 | `ifdef OR1200_NO_DC 95 | 96 | // 97 | // Data cache not implemented 98 | // 99 | assign tag = {dw-1{1'b0}}; 100 | assign tag_v = 1'b0; 101 | `ifdef OR1200_BIST 102 | assign mbist_so_o = mbist_si_i; 103 | `endif 104 | 105 | `else 106 | 107 | // 108 | // Instantiation of TAG RAM block 109 | // 110 | // Data widths are tag width plus one for valid 111 | or1200_spram # 112 | ( 113 | .aw(`OR1200_DCTAG), 114 | .dw(`OR1200_DCTAG_W + 1) 115 | ) 116 | dc_tag0 117 | ( 118 | `ifdef OR1200_BIST 119 | // RAM BIST 120 | .mbist_si_i(mbist_si_i), 121 | .mbist_so_o(mbist_so_o), 122 | .mbist_ctrl_i(mbist_ctrl_i), 123 | `endif 124 | .clk(clk), 125 | .ce(en), 126 | .we(we), 127 | .addr(addr), 128 | .di(datain), 129 | .doq({tag, tag_v, dirty}) 130 | ); 131 | `endif 132 | 133 | endmodule // or1200_dc_tag 134 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_dmmu_tlb.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's Data TLB //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://www.opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// Instantiation of DTLB. //// 10 | //// //// 11 | //// To Do: //// 12 | //// - make it smaller and faster //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // 45 | // $Log: or1200_dmmu_tlb.v,v $ 46 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 47 | // Minor update: 48 | // Bugs fixed, coding style changed. 49 | // 50 | 51 | // synopsys translate_off 52 | `include "timescale.v" 53 | // synopsys translate_on 54 | `include "or1200_defines.v" 55 | 56 | // 57 | // Data TLB 58 | // 59 | 60 | module or1200_dmmu_tlb( 61 | // Rst and clk 62 | clk, rst, 63 | 64 | // I/F for translation 65 | tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci, 66 | 67 | `ifdef OR1200_BIST 68 | // RAM BIST 69 | mbist_si_i, mbist_so_o, mbist_ctrl_i, 70 | `endif 71 | 72 | // SPR access 73 | spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o 74 | ); 75 | 76 | parameter dw = `OR1200_OPERAND_WIDTH; 77 | parameter aw = `OR1200_OPERAND_WIDTH; 78 | 79 | // 80 | // I/O 81 | // 82 | 83 | // 84 | // Clock and reset 85 | // 86 | input clk; 87 | input rst; 88 | 89 | // 90 | // I/F for translation 91 | // 92 | input tlb_en; 93 | input [aw-1:0] vaddr; 94 | output hit; 95 | output [31:`OR1200_DMMU_PS] ppn; 96 | output uwe; 97 | output ure; 98 | output swe; 99 | output sre; 100 | output ci; 101 | 102 | `ifdef OR1200_BIST 103 | // 104 | // RAM BIST 105 | // 106 | input mbist_si_i; 107 | input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; 108 | output mbist_so_o; 109 | `endif 110 | 111 | // 112 | // SPR access 113 | // 114 | input spr_cs; 115 | input spr_write; 116 | input [31:0] spr_addr; 117 | input [31:0] spr_dat_i; 118 | output [31:0] spr_dat_o; 119 | 120 | // 121 | // Internal wires and regs 122 | // 123 | wire [`OR1200_DTLB_TAG] vpn; 124 | wire v; 125 | wire [`OR1200_DTLB_INDXW-1:0] tlb_index; 126 | wire tlb_mr_en; 127 | wire tlb_mr_we; 128 | wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_in; 129 | wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_out; 130 | wire tlb_tr_en; 131 | wire tlb_tr_we; 132 | wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in; 133 | wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out; 134 | `ifdef OR1200_BIST 135 | // 136 | // RAM BIST 137 | // 138 | wire mbist_mr_so; 139 | wire mbist_tr_so; 140 | wire mbist_mr_si = mbist_si_i; 141 | wire mbist_tr_si = mbist_mr_so; 142 | assign mbist_so_o = mbist_tr_so; 143 | `endif 144 | 145 | // 146 | // Implemented bits inside match and translate registers 147 | // 148 | // dtlbwYmrX: vpn 31-19 v 0 149 | // dtlbwYtrX: ppn 31-13 swe 9 sre 8 uwe 7 ure 6 150 | // 151 | // dtlb memory width: 152 | // 19 bits for ppn 153 | // 13 bits for vpn 154 | // 1 bit for valid 155 | // 4 bits for protection 156 | // 1 bit for cache inhibit 157 | 158 | // 159 | // Enable for Match registers 160 | // 161 | assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_DTLB_TM_ADDR]); 162 | 163 | // 164 | // Write enable for Match registers 165 | // 166 | assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]; 167 | 168 | // 169 | // Enable for Translate registers 170 | // 171 | assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_DTLB_TM_ADDR]); 172 | 173 | // 174 | // Write enable for Translate registers 175 | // 176 | assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]; 177 | 178 | // 179 | // Output to SPRS unit 180 | // 181 | assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ? 182 | {vpn, tlb_index, {`OR1200_DTLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} : 183 | (spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ? 184 | {ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} : 185 | 32'h00000000; 186 | 187 | // 188 | // Assign outputs from Match registers 189 | // 190 | assign {vpn, v} = tlb_mr_ram_out; 191 | 192 | // 193 | // Assign to Match registers inputs 194 | // 195 | assign tlb_mr_ram_in = {spr_dat_i[`OR1200_DTLB_TAG], spr_dat_i[`OR1200_DTLBMR_V_BITS]}; 196 | 197 | // 198 | // Assign outputs from Translate registers 199 | // 200 | assign {ppn, swe, sre, uwe, ure, ci} = tlb_tr_ram_out; 201 | 202 | // 203 | // Assign to Translate registers inputs 204 | // 205 | assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_DMMU_PS], 206 | spr_dat_i[`OR1200_DTLBTR_SWE_BITS], 207 | spr_dat_i[`OR1200_DTLBTR_SRE_BITS], 208 | spr_dat_i[`OR1200_DTLBTR_UWE_BITS], 209 | spr_dat_i[`OR1200_DTLBTR_URE_BITS], 210 | spr_dat_i[`OR1200_DTLBTR_CI_BITS]}; 211 | 212 | // 213 | // Generate hit 214 | // 215 | assign hit = (vpn == vaddr[`OR1200_DTLB_TAG]) & v; 216 | 217 | // 218 | // TLB index is normally vaddr[18:13]. If it is SPR access then index is 219 | // spr_addr[5:0]. 220 | // 221 | assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX]; 222 | 223 | // 224 | // Instantiation of DTLB Match Registers 225 | // 226 | //or1200_spram_64x14 dtlb_mr_ram( 227 | or1200_spram # 228 | ( 229 | .aw(6), 230 | .dw(14) 231 | ) 232 | dtlb_ram 233 | ( 234 | .clk(clk), 235 | `ifdef OR1200_BIST 236 | // RAM BIST 237 | .mbist_si_i(mbist_mr_si), 238 | .mbist_so_o(mbist_mr_so), 239 | .mbist_ctrl_i(mbist_ctrl_i), 240 | `endif 241 | .ce(tlb_mr_en), 242 | .we(tlb_mr_we), 243 | .addr(tlb_index), 244 | .di(tlb_mr_ram_in), 245 | .doq(tlb_mr_ram_out) 246 | ); 247 | 248 | // 249 | // Instantiation of DTLB Translate Registers 250 | // 251 | //or1200_spram_64x24 dtlb_tr_ram( 252 | or1200_spram # 253 | ( 254 | .aw(6), 255 | .dw(24) 256 | ) 257 | dtlb_tr_ram 258 | ( 259 | .clk(clk), 260 | `ifdef OR1200_BIST 261 | // RAM BIST 262 | .mbist_si_i(mbist_tr_si), 263 | .mbist_so_o(mbist_tr_so), 264 | .mbist_ctrl_i(mbist_ctrl_i), 265 | `endif 266 | .ce(tlb_tr_en), 267 | .we(tlb_tr_we), 268 | .addr(tlb_index), 269 | .di(tlb_tr_ram_in), 270 | .doq(tlb_tr_ram_out) 271 | ); 272 | 273 | endmodule // or1200_dmmu_tlb 274 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_dpram.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Generic Double-Port Synchronous RAM //// 4 | //// //// 5 | //// This file is part of memory library available from //// 6 | //// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// 7 | //// //// 8 | //// Description //// 9 | //// This block is a wrapper with common double-port //// 10 | //// synchronous memory interface for different //// 11 | //// types of ASIC and FPGA RAMs. Beside universal memory //// 12 | //// interface it also provides behavioral model of generic //// 13 | //// double-port synchronous RAM. //// 14 | //// It should be used in all OPENCORES designs that want to be //// 15 | //// portable accross different target technologies and //// 16 | //// independent of target memory. //// 17 | //// //// 18 | //// Author(s): //// 19 | //// - Michael Unneback, unneback@opencores.org //// 20 | //// //// 21 | ////////////////////////////////////////////////////////////////////// 22 | //// //// 23 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 24 | //// //// 25 | //// This source file may be used and distributed without //// 26 | //// restriction provided that this copyright statement is not //// 27 | //// removed from the file and that any derivative work contains //// 28 | //// the original copyright notice and the associated disclaimer. //// 29 | //// //// 30 | //// This source file is free software; you can redistribute it //// 31 | //// and/or modify it under the terms of the GNU Lesser General //// 32 | //// Public License as published by the Free Software Foundation; //// 33 | //// either version 2.1 of the License, or (at your option) any //// 34 | //// later version. //// 35 | //// //// 36 | //// This source is distributed in the hope that it will be //// 37 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 38 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 39 | //// PURPOSE. See the GNU Lesser General Public License for more //// 40 | //// details. //// 41 | //// //// 42 | //// You should have received a copy of the GNU Lesser General //// 43 | //// Public License along with this source; if not, download it //// 44 | //// from http://www.opencores.org/lgpl.shtml //// 45 | //// //// 46 | ////////////////////////////////////////////////////////////////////// 47 | // 48 | // CVS Revision History 49 | // 50 | // $Log: or1200_dpram_32x32.v,v $ 51 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 52 | // New 53 | // 54 | 55 | // synopsys translate_off 56 | `include "timescale.v" 57 | // synopsys translate_on 58 | `include "or1200_defines.v" 59 | 60 | module or1200_dpram 61 | ( 62 | // Generic synchronous double-port RAM interface 63 | clk_a, ce_a, addr_a, do_a, 64 | clk_b, ce_b, we_b, addr_b, di_b 65 | ); 66 | 67 | // 68 | // Default address and data buses width 69 | // 70 | parameter aw = 5; 71 | parameter dw = 32; 72 | 73 | // 74 | // Generic synchronous double-port RAM interface 75 | // 76 | input clk_a; // Clock 77 | input ce_a; // Chip enable input 78 | input [aw-1:0] addr_a; // address bus inputs 79 | output [dw-1:0] do_a; // output data bus 80 | input clk_b; // Clock 81 | input ce_b; // Chip enable input 82 | input we_b; // Write enable input 83 | input [aw-1:0] addr_b; // address bus inputs 84 | input [dw-1:0] di_b; // input data bus 85 | 86 | // 87 | // Internal wires and registers 88 | // 89 | 90 | // 91 | // Generic double-port synchronous RAM model 92 | // 93 | 94 | // 95 | // Generic RAM's registers and wires 96 | // 97 | reg [dw-1:0] mem [(1< s_fractb_i; 97 | 98 | // check if its a subtraction or an addition operation 99 | assign s_addop = ((s_signa_i ^ s_signb_i) & !s_fpu_op_i) | 100 | ((s_signa_i ^~ s_signb_i) & s_fpu_op_i); 101 | 102 | // sign of result 103 | assign s_sign_o = ((s_fract_o == 28'd0) & !(s_signa_i & s_signb_i)) ? 0 : 104 | (!s_signa_i & (!fracta_gt_fractb & (fpu_op_i^s_signb_i)))| 105 | (s_signa_i & (fracta_gt_fractb | (fpu_op_i^s_signb_i))); 106 | 107 | // add/substract 108 | assign s_fract_o = s_addop ? 109 | (fracta_gt_fractb ? s_fracta_i - s_fractb_i : 110 | s_fractb_i - s_fracta_i) : 111 | s_fracta_i + s_fractb_i; 112 | 113 | 114 | endmodule // or1200_fpu_addsub 115 | 116 | 117 | 118 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_fpu_div.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// or1200_fpu_div //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// division entity for the division unit //// 10 | //// //// 11 | //// To Do: //// 12 | //// //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Original design (FPU100) - //// 16 | //// Jidan Al-eryani, jidan@gmx.net //// 17 | //// - Conv. to Verilog and inclusion in OR1200 - //// 18 | //// Julius Baxter, julius@opencores.org //// 19 | //// //// 20 | ////////////////////////////////////////////////////////////////////// 21 | // 22 | // Copyright (C) 2006, 2010 23 | // 24 | // This source file may be used and distributed without 25 | // restriction provided that this copyright statement is not 26 | // removed from the file and that any derivative work contains 27 | // the original copyright notice and the associated disclaimer. 28 | // 29 | // THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY 30 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 | // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 32 | // FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR 33 | // OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 34 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 | // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 | // GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 | // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 38 | // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 40 | // OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 | // POSSIBILITY OF SUCH DAMAGE. 42 | // 43 | 44 | module or1200_fpu_div 45 | ( 46 | clk_i, 47 | dvdnd_i, 48 | dvsor_i, 49 | sign_dvd_i, 50 | sign_div_i, 51 | start_i, 52 | ready_o, 53 | qutnt_o, 54 | rmndr_o, 55 | sign_o, 56 | div_zero_o 57 | ); 58 | 59 | parameter FP_WIDTH = 32; 60 | parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial 61 | parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial 62 | parameter FRAC_WIDTH = 23; 63 | parameter EXP_WIDTH = 8; 64 | parameter ZERO_VECTOR = 31'd0; 65 | parameter INF = 31'b1111111100000000000000000000000; 66 | parameter QNAN = 31'b1111111110000000000000000000000; 67 | parameter SNAN = 31'b1111111100000000000000000000001; 68 | 69 | 70 | input clk_i; 71 | input [2*(FRAC_WIDTH+2)-1:0] dvdnd_i; 72 | input [FRAC_WIDTH+3:0] dvsor_i; 73 | input sign_dvd_i; 74 | input sign_div_i; 75 | input start_i; 76 | output ready_o; 77 | output [FRAC_WIDTH+3:0] qutnt_o; 78 | output [FRAC_WIDTH+3:0] rmndr_o; 79 | output sign_o; 80 | output div_zero_o; 81 | 82 | parameter t_state_waiting = 1'b0, 83 | t_state_busy = 1'b1; 84 | 85 | reg [FRAC_WIDTH+3:0] s_qutnt_o; 86 | reg [FRAC_WIDTH+3:0] s_rmndr_o; 87 | reg [2*(FRAC_WIDTH+2)-1:0] s_dvdnd_i; 88 | reg [FRAC_WIDTH+3:0] s_dvsor_i; 89 | reg s_sign_dvd_i, s_sign_div_i; 90 | wire s_sign_o; 91 | wire s_div_zero_o; 92 | reg s_start_i; 93 | reg s_ready_o; 94 | reg s_state; 95 | reg [4:0] s_count; 96 | reg [FRAC_WIDTH+3:0] s_dvd; 97 | 98 | // Input Register 99 | always @(posedge clk_i) 100 | begin 101 | s_dvdnd_i <= dvdnd_i; 102 | s_dvsor_i <= dvsor_i; 103 | s_sign_dvd_i<= sign_dvd_i; 104 | s_sign_div_i<= sign_div_i; 105 | s_start_i <= start_i; 106 | end 107 | 108 | assign qutnt_o = s_qutnt_o; 109 | assign rmndr_o = s_rmndr_o; 110 | assign sign_o = s_sign_o; 111 | assign ready_o = s_ready_o; 112 | assign div_zero_o = s_div_zero_o; 113 | 114 | assign s_sign_o = sign_dvd_i ^ sign_div_i; 115 | assign s_div_zero_o = !(|s_dvsor_i) & (|s_dvdnd_i); 116 | 117 | 118 | always @(posedge clk_i) 119 | if (s_start_i) 120 | begin 121 | s_state <= t_state_busy; 122 | s_count <= 26; 123 | end 124 | else if (!(|s_count) & s_state==t_state_busy) 125 | begin 126 | s_state <= t_state_waiting; 127 | s_ready_o <= 1; 128 | s_count <=26; 129 | end 130 | else if (s_state==t_state_busy) 131 | s_count <= s_count - 1; 132 | else 133 | begin 134 | s_state <= t_state_waiting; 135 | s_ready_o <= 0; 136 | end 137 | 138 | wire [26:0] v_div; 139 | assign v_div = (s_count==26) ? {3'd0,s_dvdnd_i[49:26]} : s_dvd; 140 | wire [26:0] v_div_minus_s_dvsor_i; 141 | assign v_div_minus_s_dvsor_i = v_div - s_dvsor_i; 142 | 143 | 144 | always @(posedge clk_i) 145 | begin 146 | //Reset 147 | if (s_start_i) 148 | begin 149 | s_qutnt_o <= 0; 150 | s_rmndr_o <= 0; 151 | end 152 | else if (s_state==t_state_busy) 153 | begin 154 | 155 | if (v_div < s_dvsor_i) 156 | begin 157 | s_qutnt_o[s_count] <= 1'b0; 158 | s_dvd <= {v_div[25:0],1'b0}; 159 | end 160 | else 161 | begin 162 | s_qutnt_o[s_count] <= 1'b1; 163 | s_dvd <= {v_div_minus_s_dvsor_i[25:0],1'b0}; 164 | end 165 | 166 | s_rmndr_o <= v_div; 167 | 168 | end // if (s_state==t_state_busy) 169 | end // always @ (posedge clk_i) 170 | 171 | endmodule // or1200_fpu_div 172 | 173 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_fpu_fcmp.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// or1200_fpu_fcmp //// 4 | //// Single precision Floating Point Compare Unit //// 5 | //// //// 6 | //// Author: Rudolf Usselmann //// 7 | //// rudi@asics.ws //// 8 | //// //// 9 | ///////////////////////////////////////////////////////////////////// 10 | //// //// 11 | //// Copyright (C) 2000 Rudolf Usselmann //// 12 | //// rudi@asics.ws //// 13 | //// //// 14 | //// This source file may be used and distributed without //// 15 | //// restriction provided that this copyright statement is not //// 16 | //// removed from the file and that any derivative work contains //// 17 | //// the original copyright notice and the associated disclaimer.//// 18 | //// //// 19 | //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// 20 | //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// 21 | //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// 22 | //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// 23 | //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 24 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// 25 | //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// 26 | //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// 27 | //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// 28 | //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 29 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// 30 | //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// 31 | //// POSSIBILITY OF SUCH DAMAGE. //// 32 | //// //// 33 | ///////////////////////////////////////////////////////////////////// 34 | 35 | `timescale 1ns / 100ps 36 | 37 | 38 | module or1200_fpu_fcmp(opa, opb, unordered, altb, blta, aeqb, inf, zero); 39 | 40 | input [31:0] opa, opb; 41 | output unordered; 42 | output altb, blta, aeqb; 43 | output inf, zero; 44 | 45 | //////////////////////////////////////////////////////////////////////// 46 | // 47 | // Local Wire 48 | // 49 | 50 | reg altb, blta, aeqb; 51 | 52 | wire signa, signb; 53 | wire [7:0] expa, expb; 54 | wire [22:0] fracta, fractb; 55 | 56 | wire expa_ff, expb_ff, fracta_00, fractb_00; 57 | wire qnan_a, snan_a, qnan_b, snan_b, opa_inf, opb_inf, inf; 58 | wire qnan, snan, opa_zero, opb_zero; 59 | 60 | wire exp_eq, exp_gt, exp_lt; 61 | wire fract_eq, fract_gt, fract_lt; 62 | wire all_zero; 63 | 64 | //////////////////////////////////////////////////////////////////////// 65 | // 66 | // Aliases 67 | // 68 | 69 | assign signa = opa[31]; 70 | assign signb = opb[31]; 71 | assign expa = opa[30:23]; 72 | assign expb = opb[30:23]; 73 | assign fracta = opa[22:0]; 74 | assign fractb = opb[22:0]; 75 | 76 | //////////////////////////////////////////////////////////////////////// 77 | // 78 | // Exception Logic 79 | // 80 | 81 | assign expa_ff = &expa; 82 | assign expb_ff = &expb; 83 | 84 | assign fracta_00 = !(|fracta); 85 | assign fractb_00 = !(|fractb); 86 | 87 | assign qnan_a = fracta[22]; 88 | assign snan_a = !fracta[22] & |fracta[21:0]; 89 | assign qnan_b = fractb[22]; 90 | assign snan_b = !fractb[22] & |fractb[21:0]; 91 | 92 | assign opa_inf = (expa_ff & fracta_00); 93 | assign opb_inf = (expb_ff & fractb_00); 94 | assign inf = opa_inf | opb_inf; 95 | 96 | assign qnan = (expa_ff & qnan_a) | (expb_ff & qnan_b); 97 | assign snan = (expa_ff & snan_a) | (expb_ff & snan_b); 98 | assign unordered = qnan | snan; 99 | 100 | assign opa_zero = !(|expa) & fracta_00; 101 | assign opb_zero = !(|expb) & fractb_00; 102 | assign zero = opa_zero; 103 | 104 | 105 | //////////////////////////////////////////////////////////////////////// 106 | // 107 | // Comparison Logic 108 | // 109 | 110 | assign exp_eq = expa == expb; 111 | assign exp_gt = expa > expb; 112 | assign exp_lt = expa < expb; 113 | 114 | assign fract_eq = fracta == fractb; 115 | assign fract_gt = fracta > fractb; 116 | assign fract_lt = fracta < fractb; 117 | 118 | assign all_zero = opa_zero & opb_zero; 119 | 120 | always @( qnan or snan or opa_inf or opb_inf or signa or signb or exp_eq or exp_gt or 121 | exp_lt or fract_eq or fract_gt or fract_lt or all_zero) 122 | 123 | casez( {qnan, snan, opa_inf, opb_inf, signa, signb, exp_eq, exp_gt, exp_lt, fract_eq, fract_gt, fract_lt, all_zero}) 124 | //13'b??_??_??_???_???_?: {altb, blta, aeqb} = 3'b000; 125 | 126 | 13'b1?_??_??_???_???_?: {altb, blta, aeqb} = 3'b000; // qnan 127 | 13'b?1_??_??_???_???_?: {altb, blta, aeqb} = 3'b000; // snan 128 | 129 | 13'b00_11_00_???_???_?: {altb, blta, aeqb} = 3'b001; // both op INF comparisson 130 | 13'b00_11_01_???_???_?: {altb, blta, aeqb} = 3'b100; 131 | 13'b00_11_10_???_???_?: {altb, blta, aeqb} = 3'b010; 132 | 13'b00_11_11_???_???_?: {altb, blta, aeqb} = 3'b001; 133 | 134 | 13'b00_10_00_???_???_?: {altb, blta, aeqb} = 3'b100; // opa INF comparisson 135 | 13'b00_10_01_???_???_?: {altb, blta, aeqb} = 3'b100; 136 | 13'b00_10_10_???_???_?: {altb, blta, aeqb} = 3'b010; 137 | 13'b00_10_11_???_???_?: {altb, blta, aeqb} = 3'b010; 138 | 139 | 13'b00_01_00_???_???_?: {altb, blta, aeqb} = 3'b010; // opb INF comparisson 140 | 13'b00_01_01_???_???_?: {altb, blta, aeqb} = 3'b100; 141 | 13'b00_01_10_???_???_?: {altb, blta, aeqb} = 3'b010; 142 | 13'b00_01_11_???_???_?: {altb, blta, aeqb} = 3'b100; 143 | 144 | 13'b00_00_10_???_???_0: {altb, blta, aeqb} = 3'b010; //compare base on sign 145 | 13'b00_00_01_???_???_0: {altb, blta, aeqb} = 3'b100; //compare base on sign 146 | 147 | 13'b00_00_??_???_???_1: {altb, blta, aeqb} = 3'b001; //compare base on sign both are zero 148 | 149 | 13'b00_00_00_010_???_?: {altb, blta, aeqb} = 3'b100; // cmp exp, equal sign 150 | 13'b00_00_00_001_???_?: {altb, blta, aeqb} = 3'b010; 151 | 13'b00_00_11_010_???_?: {altb, blta, aeqb} = 3'b010; 152 | 13'b00_00_11_001_???_?: {altb, blta, aeqb} = 3'b100; 153 | 154 | 13'b00_00_00_100_010_?: {altb, blta, aeqb} = 3'b100; // compare fractions, equal sign, equal exp 155 | 13'b00_00_00_100_001_?: {altb, blta, aeqb} = 3'b010; 156 | 13'b00_00_11_100_010_?: {altb, blta, aeqb} = 3'b010; 157 | 13'b00_00_11_100_001_?: {altb, blta, aeqb} = 3'b100; 158 | 159 | 13'b00_00_00_100_100_?: {altb, blta, aeqb} = 3'b001; 160 | 13'b00_00_11_100_100_?: {altb, blta, aeqb} = 3'b001; 161 | 162 | default: {altb, blta, aeqb} = 3'bxxx; 163 | endcase 164 | 165 | endmodule // or1200_fpu_fcmp 166 | 167 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_fpu_intfloat_conv_except.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// or1200_fpu_intfloat_conv_except //// 4 | //// //// 5 | //// Author: Rudolf Usselmann //// 6 | //// rudi@asics.ws //// 7 | //// //// 8 | //// Modified by Julius Baxter, July, 2010 //// 9 | //// julius.baxter@orsoc.se //// 10 | //// //// 11 | //// //// 12 | ///////////////////////////////////////////////////////////////////// 13 | //// //// 14 | //// Copyright (C) 2000 Rudolf Usselmann //// 15 | //// rudi@asics.ws //// 16 | //// //// 17 | //// This source file may be used and distributed without //// 18 | //// restriction provided that this copyright statement is not //// 19 | //// removed from the file and that any derivative work contains //// 20 | //// the original copyright notice and the associated disclaimer.//// 21 | //// //// 22 | //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// 23 | //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// 24 | //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// 25 | //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// 26 | //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 27 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// 28 | //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// 29 | //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// 30 | //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// 31 | //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 32 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// 33 | //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// 34 | //// POSSIBILITY OF SUCH DAMAGE. //// 35 | //// //// 36 | ///////////////////////////////////////////////////////////////////// 37 | 38 | `timescale 1ns / 100ps 39 | 40 | module or1200_fpu_intfloat_conv_except 41 | ( 42 | clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan, 43 | opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn 44 | ); 45 | input clk; 46 | input [31:0] opa, opb; 47 | output inf, ind, qnan, snan, opa_nan, opb_nan; 48 | output opa_00, opb_00; 49 | output opa_inf, opb_inf; 50 | output opa_dn; 51 | output opb_dn; 52 | 53 | //////////////////////////////////////////////////////////////////////// 54 | // 55 | // Local Wires and registers 56 | // 57 | 58 | wire [7:0] expa, expb; // alias to opX exponent 59 | wire [22:0] fracta, fractb; // alias to opX fraction 60 | reg expa_ff, infa_f_r, qnan_r_a, snan_r_a; 61 | reg expb_ff, infb_f_r, qnan_r_b, snan_r_b; 62 | reg inf, ind, qnan, snan; // Output registers 63 | reg opa_nan, opb_nan; 64 | reg expa_00, expb_00, fracta_00, fractb_00; 65 | reg opa_00, opb_00; 66 | reg opa_inf, opb_inf; 67 | reg opa_dn, opb_dn; 68 | 69 | //////////////////////////////////////////////////////////////////////// 70 | // 71 | // Aliases 72 | // 73 | 74 | assign expa = opa[30:23]; 75 | assign expb = opb[30:23]; 76 | assign fracta = opa[22:0]; 77 | assign fractb = opb[22:0]; 78 | 79 | //////////////////////////////////////////////////////////////////////// 80 | // 81 | // Determine if any of the input operators is a INF or NAN or any other 82 | // special number 83 | // 84 | 85 | always @(posedge clk) 86 | expa_ff <= &expa; 87 | 88 | always @(posedge clk) 89 | expb_ff <= &expb; 90 | 91 | always @(posedge clk) 92 | infa_f_r <= !(|fracta); 93 | 94 | always @(posedge clk) 95 | infb_f_r <= !(|fractb); 96 | 97 | always @(posedge clk) 98 | qnan_r_a <= fracta[22]; 99 | 100 | always @(posedge clk) 101 | snan_r_a <= !fracta[22] & |fracta[21:0]; 102 | 103 | always @(posedge clk) 104 | qnan_r_b <= fractb[22]; 105 | 106 | always @(posedge clk) 107 | snan_r_b <= !fractb[22]; // & |fractb[21:0]; 108 | 109 | always @(posedge clk) 110 | ind <= (expa_ff & infa_f_r); // & (expb_ff & infb_f_r); 111 | 112 | always @(posedge clk) 113 | inf <= (expa_ff & infa_f_r); // | (expb_ff & infb_f_r); 114 | 115 | always @(posedge clk) 116 | qnan <= (expa_ff & qnan_r_a); // | (expb_ff & qnan_r_b); 117 | 118 | always @(posedge clk) 119 | snan <= (expa_ff & snan_r_a); // | (expb_ff & snan_r_b); 120 | 121 | always @(posedge clk) 122 | opa_nan <= &expa & (|fracta[22:0]); 123 | 124 | always @(posedge clk) 125 | opb_nan <= &expb & (|fractb[22:0]); 126 | 127 | always @(posedge clk) 128 | opa_inf <= (expa_ff & infa_f_r); 129 | 130 | always @(posedge clk) 131 | opb_inf <= (expb_ff & infb_f_r); 132 | 133 | always @(posedge clk) 134 | expa_00 <= !(|expa); 135 | 136 | always @(posedge clk) 137 | expb_00 <= !(|expb); 138 | 139 | always @(posedge clk) 140 | fracta_00 <= !(|fracta); 141 | 142 | always @(posedge clk) 143 | fractb_00 <= !(|fractb); 144 | 145 | always @(posedge clk) 146 | opa_00 <= expa_00 & fracta_00; 147 | 148 | always @(posedge clk) 149 | opb_00 <= expb_00 & fractb_00; 150 | 151 | always @(posedge clk) 152 | opa_dn <= expa_00; 153 | 154 | always @(posedge clk) 155 | opb_dn <= expb_00; 156 | 157 | endmodule // or1200_fpu_intfloat_conv_except 158 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_fpu_mul.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// or1200_fpu_mul //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// Serial multiplication entity for the multiplication unit //// 10 | //// //// 11 | //// To Do: //// 12 | //// //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Original design (FPU100) - //// 16 | //// Jidan Al-eryani, jidan@gmx.net //// 17 | //// - Conv. to Verilog and inclusion in OR1200 - //// 18 | //// Julius Baxter, julius@opencores.org //// 19 | //// //// 20 | ////////////////////////////////////////////////////////////////////// 21 | // 22 | // Copyright (C) 2006, 2010 23 | // 24 | // This source file may be used and distributed without 25 | // restriction provided that this copyright statement is not 26 | // removed from the file and that any derivative work contains 27 | // the original copyright notice and the associated disclaimer. 28 | // 29 | // THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY 30 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 | // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 32 | // FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR 33 | // OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 34 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 | // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 | // GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 | // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 38 | // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 40 | // OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 | // POSSIBILITY OF SUCH DAMAGE. 42 | // 43 | 44 | module or1200_fpu_mul 45 | ( 46 | clk_i, 47 | fracta_i, 48 | fractb_i, 49 | signa_i, 50 | signb_i, 51 | start_i, 52 | fract_o, 53 | sign_o, 54 | ready_o 55 | ); 56 | 57 | parameter FP_WIDTH = 32; 58 | parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial 59 | parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial 60 | parameter FRAC_WIDTH = 23; 61 | parameter EXP_WIDTH = 8; 62 | parameter ZERO_VECTOR = 31'd0; 63 | parameter INF = 31'b1111111100000000000000000000000; 64 | parameter QNAN = 31'b1111111110000000000000000000000; 65 | parameter SNAN = 31'b1111111100000000000000000000001; 66 | 67 | input clk_i; 68 | input [FRAC_WIDTH:0] fracta_i; 69 | input [FRAC_WIDTH:0] fractb_i; 70 | input signa_i; 71 | input signb_i; 72 | input start_i; 73 | output reg [2*FRAC_WIDTH+1:0] fract_o; 74 | output reg sign_o; 75 | output reg ready_o; 76 | 77 | parameter t_state_waiting = 1'b0, 78 | t_state_busy = 1'b1; 79 | 80 | reg [47:0] s_fract_o; 81 | reg [23:0] s_fracta_i; 82 | reg [23:0] s_fractb_i; 83 | reg s_signa_i, s_signb_i; 84 | wire s_sign_o; 85 | reg s_start_i; 86 | reg s_ready_o; 87 | reg s_state; 88 | reg [4:0] s_count; 89 | wire [23:0] s_tem_prod; 90 | 91 | // Input Register 92 | always @(posedge clk_i) 93 | begin 94 | s_fracta_i <= fracta_i; 95 | s_fractb_i <= fractb_i; 96 | s_signa_i<= signa_i; 97 | s_signb_i<= signb_i; 98 | s_start_i <= start_i; 99 | end 100 | 101 | // Output Register 102 | always @(posedge clk_i) 103 | begin 104 | fract_o <= s_fract_o; 105 | sign_o <= s_sign_o; 106 | ready_o <= s_ready_o; 107 | end 108 | 109 | assign s_sign_o = signa_i ^ signb_i; 110 | 111 | // FSM 112 | always @(posedge clk_i) 113 | if (s_start_i) 114 | begin 115 | s_state <= t_state_busy; 116 | s_count <= 0; 117 | end 118 | else if (s_count==23) 119 | begin 120 | s_state <= t_state_waiting; 121 | s_ready_o <= 1; 122 | s_count <=0; 123 | end 124 | else if (s_state==t_state_busy) 125 | s_count <= s_count + 1; 126 | else 127 | begin 128 | s_state <= t_state_waiting; 129 | s_ready_o <= 0; 130 | end 131 | 132 | assign s_tem_prod[0] = s_fracta_i[0] & s_fractb_i[s_count]; 133 | assign s_tem_prod[1] = s_fracta_i[1] & s_fractb_i[s_count]; 134 | assign s_tem_prod[2] = s_fracta_i[2] & s_fractb_i[s_count]; 135 | assign s_tem_prod[3] = s_fracta_i[3] & s_fractb_i[s_count]; 136 | assign s_tem_prod[4] = s_fracta_i[4] & s_fractb_i[s_count]; 137 | assign s_tem_prod[5] = s_fracta_i[5] & s_fractb_i[s_count]; 138 | assign s_tem_prod[6] = s_fracta_i[6] & s_fractb_i[s_count]; 139 | assign s_tem_prod[7] = s_fracta_i[7] & s_fractb_i[s_count]; 140 | assign s_tem_prod[8] = s_fracta_i[8] & s_fractb_i[s_count]; 141 | assign s_tem_prod[9] = s_fracta_i[9] & s_fractb_i[s_count]; 142 | assign s_tem_prod[10] = s_fracta_i[10] & s_fractb_i[s_count]; 143 | assign s_tem_prod[11] = s_fracta_i[11] & s_fractb_i[s_count]; 144 | assign s_tem_prod[12] = s_fracta_i[12] & s_fractb_i[s_count]; 145 | assign s_tem_prod[13] = s_fracta_i[13] & s_fractb_i[s_count]; 146 | assign s_tem_prod[14] = s_fracta_i[14] & s_fractb_i[s_count]; 147 | assign s_tem_prod[15] = s_fracta_i[15] & s_fractb_i[s_count]; 148 | assign s_tem_prod[16] = s_fracta_i[16] & s_fractb_i[s_count]; 149 | assign s_tem_prod[17] = s_fracta_i[17] & s_fractb_i[s_count]; 150 | assign s_tem_prod[18] = s_fracta_i[18] & s_fractb_i[s_count]; 151 | assign s_tem_prod[19] = s_fracta_i[19] & s_fractb_i[s_count]; 152 | assign s_tem_prod[20] = s_fracta_i[20] & s_fractb_i[s_count]; 153 | assign s_tem_prod[21] = s_fracta_i[21] & s_fractb_i[s_count]; 154 | assign s_tem_prod[22] = s_fracta_i[22] & s_fractb_i[s_count]; 155 | assign s_tem_prod[23] = s_fracta_i[23] & s_fractb_i[s_count]; 156 | 157 | wire [47:0] v_prod_shl; 158 | assign v_prod_shl = {24'd0,s_tem_prod} << s_count[4:0]; 159 | 160 | always @(posedge clk_i) 161 | if (s_state==t_state_busy) 162 | begin 163 | if (|s_count) 164 | s_fract_o <= v_prod_shl + s_fract_o; 165 | else 166 | s_fract_o <= v_prod_shl; 167 | end 168 | 169 | endmodule // or1200_fpu_mul 170 | 171 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_fpu_pre_norm_addsub.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// or1200_fpu_pre_norm_addsub //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// pre-normalization entity for the addition/subtraction unit //// 10 | //// //// 11 | //// To Do: //// 12 | //// //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Original design (FPU100) - //// 16 | //// Jidan Al-eryani, jidan@gmx.net //// 17 | //// - Conv. to Verilog and inclusion in OR1200 - //// 18 | //// Julius Baxter, julius@opencores.org //// 19 | //// //// 20 | ////////////////////////////////////////////////////////////////////// 21 | // 22 | // Copyright (C) 2006, 2010 23 | // 24 | // This source file may be used and distributed without 25 | // restriction provided that this copyright statement is not 26 | // removed from the file and that any derivative work contains 27 | // the original copyright notice and the associated disclaimer. 28 | // 29 | // THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY 30 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 | // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 32 | // FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR 33 | // OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 34 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 | // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 | // GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 | // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 38 | // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 40 | // OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 | // POSSIBILITY OF SUCH DAMAGE. 42 | // 43 | 44 | module or1200_fpu_pre_norm_addsub ( 45 | 46 | clk_i, 47 | opa_i, 48 | opb_i, 49 | fracta_28_o, 50 | fractb_28_o, 51 | exp_o 52 | ); 53 | 54 | parameter FP_WIDTH = 32; 55 | parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial 56 | parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial 57 | parameter FRAC_WIDTH = 23; 58 | parameter EXP_WIDTH = 8; 59 | parameter ZERO_VECTOR = 31'd0; 60 | parameter INF = 31'b1111111100000000000000000000000; 61 | parameter QNAN = 31'b1111111110000000000000000000000; 62 | parameter SNAN = 31'b1111111100000000000000000000001; 63 | 64 | 65 | input clk_i; 66 | input [FP_WIDTH-1:0] opa_i; 67 | input [FP_WIDTH-1:0] opb_i; 68 | // carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1) 69 | output reg [FRAC_WIDTH+4:0] fracta_28_o; 70 | output reg [FRAC_WIDTH+4:0] fractb_28_o; 71 | output reg [EXP_WIDTH-1:0] exp_o; 72 | 73 | reg [EXP_WIDTH-1 : 0] s_exp_o ; 74 | wire [FRAC_WIDTH+4 : 0] s_fracta_28_o, s_fractb_28_o ; 75 | wire [EXP_WIDTH-1 : 0] s_expa; 76 | wire [EXP_WIDTH-1 : 0] s_expb ; 77 | wire [FRAC_WIDTH-1 : 0] s_fracta; 78 | wire [FRAC_WIDTH-1 : 0] s_fractb ; 79 | wire [FRAC_WIDTH+4 : 0] s_fracta_28; 80 | 81 | wire [FRAC_WIDTH+4 : 0] s_fractb_28 ; 82 | 83 | wire [FRAC_WIDTH+4 : 0] s_fract_sm_28; 84 | wire [FRAC_WIDTH+4 : 0] s_fract_shr_28 ; 85 | 86 | reg [EXP_WIDTH-1 : 0] s_exp_diff ; 87 | reg [5 : 0] s_rzeros ; 88 | wire s_expa_eq_expb; 89 | wire s_expa_gt_expb; 90 | wire s_fracta_1; 91 | wire s_fractb_1; 92 | wire s_op_dn,s_opa_dn, s_opb_dn; 93 | wire [1 : 0] s_mux_diff ; 94 | wire s_mux_exp; 95 | wire s_sticky; 96 | 97 | 98 | assign s_expa = opa_i[30:23]; 99 | assign s_expb = opb_i[30:23]; 100 | assign s_fracta = opa_i[22:0]; 101 | assign s_fractb = opb_i[22:0]; 102 | 103 | always @(posedge clk_i) 104 | begin 105 | exp_o <= s_exp_o; 106 | fracta_28_o <= s_fracta_28_o; 107 | fractb_28_o <= s_fractb_28_o; 108 | end 109 | 110 | assign s_expa_eq_expb = (s_expa == s_expb); 111 | 112 | assign s_expa_gt_expb = (s_expa > s_expb); 113 | 114 | // '1' if fraction is not zero 115 | assign s_fracta_1 = |s_fracta; 116 | assign s_fractb_1 = |s_fractb; 117 | 118 | // opa or Opb is denormalized 119 | assign s_opa_dn = !(|s_expa); 120 | assign s_opb_dn = !(|s_expb); 121 | assign s_op_dn = s_opa_dn | s_opb_dn; 122 | 123 | // Output larger exponent 124 | assign s_mux_exp = s_expa_gt_expb; 125 | 126 | always @(posedge clk_i) 127 | s_exp_o <= s_mux_exp ? s_expa : s_expb; 128 | 129 | // convert to an easy to handle floating-point format 130 | assign s_fracta_28 = s_opa_dn ? 131 | {2'b00, s_fracta, 3'b000} : {2'b01, s_fracta, 3'b000}; 132 | assign s_fractb_28 = s_opb_dn ? 133 | {2'b00, s_fractb, 3'b000} : {2'b01, s_fractb, 3'b000}; 134 | 135 | assign s_mux_diff = {s_expa_gt_expb, s_opa_dn ^ s_opb_dn}; 136 | 137 | // calculate howmany postions the fraction will be shifted 138 | always @(posedge clk_i) 139 | begin 140 | case(s_mux_diff) 141 | 2'b00: s_exp_diff <= s_expb - s_expa; 142 | 2'b01: s_exp_diff <= s_expb - (s_expa + 8'd1); 143 | 2'b10: s_exp_diff <= s_expa - s_expb; 144 | 2'b11: s_exp_diff <= s_expa - (s_expb + 8'd1); 145 | endcase 146 | end 147 | 148 | assign s_fract_sm_28 = s_expa_gt_expb ? s_fractb_28 : s_fracta_28; 149 | 150 | // shift-right the fraction if necessary 151 | assign s_fract_shr_28 = s_fract_sm_28 >> s_exp_diff; 152 | 153 | // count the zeros from right to check if result is inexact 154 | always @(s_fract_sm_28) 155 | casez(s_fract_sm_28) // synopsys full_case parallel_case 156 | 28'b???????????????????????????1: s_rzeros = 0; 157 | 28'b??????????????????????????10: s_rzeros = 1; 158 | 28'b?????????????????????????100: s_rzeros = 2; 159 | 28'b????????????????????????1000: s_rzeros = 3; 160 | 28'b???????????????????????10000: s_rzeros = 4; 161 | 28'b??????????????????????100000: s_rzeros = 5; 162 | 28'b?????????????????????1000000: s_rzeros = 6; 163 | 28'b????????????????????10000000: s_rzeros = 7; 164 | 28'b???????????????????100000000: s_rzeros = 8; 165 | 28'b??????????????????1000000000: s_rzeros = 9; 166 | 28'b?????????????????10000000000: s_rzeros = 10; 167 | 28'b????????????????100000000000: s_rzeros = 11; 168 | 28'b???????????????1000000000000: s_rzeros = 12; 169 | 28'b??????????????10000000000000: s_rzeros = 13; 170 | 28'b?????????????100000000000000: s_rzeros = 14; 171 | 28'b????????????1000000000000000: s_rzeros = 15; 172 | 28'b???????????10000000000000000: s_rzeros = 16; 173 | 28'b??????????100000000000000000: s_rzeros = 17; 174 | 28'b?????????1000000000000000000: s_rzeros = 18; 175 | 28'b????????10000000000000000000: s_rzeros = 19; 176 | 28'b???????100000000000000000000: s_rzeros = 20; 177 | 28'b??????1000000000000000000000: s_rzeros = 21; 178 | 28'b?????10000000000000000000000: s_rzeros = 22; 179 | 28'b????100000000000000000000000: s_rzeros = 23; 180 | 28'b???1000000000000000000000000: s_rzeros = 24; 181 | 28'b??10000000000000000000000000: s_rzeros = 25; 182 | 28'b?100000000000000000000000000: s_rzeros = 26; 183 | 28'b1000000000000000000000000000: s_rzeros = 27; 184 | 28'b0000000000000000000000000000: s_rzeros = 28; 185 | endcase // casex (s_fract_sm_28) 186 | 187 | assign s_sticky = (s_exp_diff > {2'b00,s_rzeros}) & (|s_fract_sm_28); 188 | 189 | assign s_fracta_28_o = s_expa_gt_expb ? 190 | s_fracta_28 : 191 | {s_fract_shr_28[27:1],(s_sticky|s_fract_shr_28[0])}; 192 | 193 | assign s_fractb_28_o = s_expa_gt_expb ? 194 | {s_fract_shr_28[27:1],(s_sticky|s_fract_shr_28[0])} : 195 | s_fractb_28; 196 | 197 | endmodule // or1200_fpu_pre_norm_addsub 198 | 199 | 200 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_fpu_pre_norm_div.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// or1200_fpu_pre_norm_div //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// pre-normalization entity for the division unit //// 10 | //// //// 11 | //// To Do: //// 12 | //// //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Original design (FPU100) - //// 16 | //// Jidan Al-eryani, jidan@gmx.net //// 17 | //// - Conv. to Verilog and inclusion in OR1200 - //// 18 | //// Julius Baxter, julius@opencores.org //// 19 | //// //// 20 | ////////////////////////////////////////////////////////////////////// 21 | // 22 | // Copyright (C) 2006, 2010 23 | // 24 | // This source file may be used and distributed without 25 | // restriction provided that this copyright statement is not 26 | // removed from the file and that any derivative work contains 27 | // the original copyright notice and the associated disclaimer. 28 | // 29 | // THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY 30 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 | // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 32 | // FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR 33 | // OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 34 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 | // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 | // GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 | // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 38 | // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 40 | // OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 | // POSSIBILITY OF SUCH DAMAGE. 42 | // 43 | 44 | module or1200_fpu_pre_norm_div 45 | ( 46 | clk_i, 47 | opa_i, 48 | opb_i, 49 | exp_10_o, 50 | dvdnd_50_o, 51 | dvsor_27_o 52 | ); 53 | 54 | 55 | parameter FP_WIDTH = 32; 56 | parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial 57 | parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial 58 | parameter FRAC_WIDTH = 23; 59 | parameter EXP_WIDTH = 8; 60 | parameter ZERO_VECTOR = 31'd0; 61 | parameter INF = 31'b1111111100000000000000000000000; 62 | parameter QNAN = 31'b1111111110000000000000000000000; 63 | parameter SNAN = 31'b1111111100000000000000000000001; 64 | 65 | input clk_i; 66 | input [FP_WIDTH-1:0] opa_i; 67 | input [FP_WIDTH-1:0] opb_i; 68 | output reg [EXP_WIDTH+1:0] exp_10_o; 69 | output [2*(FRAC_WIDTH+2)-1:0] dvdnd_50_o; 70 | output [FRAC_WIDTH+3:0] dvsor_27_o; 71 | 72 | 73 | wire [EXP_WIDTH-1:0] s_expa; 74 | wire [EXP_WIDTH-1:0] s_expb; 75 | wire [FRAC_WIDTH-1:0] s_fracta; 76 | wire [FRAC_WIDTH-1:0] s_fractb; 77 | wire [2*(FRAC_WIDTH+2)-1:0] s_dvdnd_50_o; 78 | wire [FRAC_WIDTH+3:0] s_dvsor_27_o; 79 | reg [5:0] s_dvd_zeros; 80 | reg [5:0] s_div_zeros; 81 | reg [EXP_WIDTH+1:0] s_exp_10_o; 82 | 83 | reg [EXP_WIDTH+1:0] s_expa_in; 84 | reg [EXP_WIDTH+1:0] s_expb_in; 85 | wire s_opa_dn, s_opb_dn; 86 | 87 | wire [FRAC_WIDTH:0] s_fracta_24; 88 | wire [FRAC_WIDTH:0] s_fractb_24; 89 | 90 | 91 | assign s_expa = opa_i[30:23]; 92 | assign s_expb = opb_i[30:23]; 93 | assign s_fracta = opa_i[22:0]; 94 | assign s_fractb = opb_i[22:0]; 95 | assign dvdnd_50_o = s_dvdnd_50_o; 96 | assign dvsor_27_o = s_dvsor_27_o; 97 | 98 | // Output Register 99 | always @(posedge clk_i) 100 | exp_10_o <= s_exp_10_o; 101 | 102 | assign s_opa_dn = !(|s_expa); 103 | assign s_opb_dn = !(|s_expb); 104 | 105 | assign s_fracta_24 = {!s_opa_dn,s_fracta}; 106 | assign s_fractb_24 = {!s_opb_dn,s_fractb}; 107 | 108 | 109 | // count leading zeros 110 | //s_dvd_zeros <= count_l_zeros( s_fracta_24 ); 111 | always @(s_fracta_24) 112 | casez(s_fracta_24) // synopsys full_case parallel_case 113 | 24'b1???????????????????????: s_dvd_zeros = 0; 114 | 24'b01??????????????????????: s_dvd_zeros = 1; 115 | 24'b001?????????????????????: s_dvd_zeros = 2; 116 | 24'b0001????????????????????: s_dvd_zeros = 3; 117 | 24'b00001???????????????????: s_dvd_zeros = 4; 118 | 24'b000001??????????????????: s_dvd_zeros = 5; 119 | 24'b0000001?????????????????: s_dvd_zeros = 6; 120 | 24'b00000001????????????????: s_dvd_zeros = 7; 121 | 24'b000000001???????????????: s_dvd_zeros = 8; 122 | 24'b0000000001??????????????: s_dvd_zeros = 9; 123 | 24'b00000000001?????????????: s_dvd_zeros = 10; 124 | 24'b000000000001????????????: s_dvd_zeros = 11; 125 | 24'b0000000000001???????????: s_dvd_zeros = 12; 126 | 24'b00000000000001??????????: s_dvd_zeros = 13; 127 | 24'b000000000000001?????????: s_dvd_zeros = 14; 128 | 24'b0000000000000001????????: s_dvd_zeros = 15; 129 | 24'b00000000000000001???????: s_dvd_zeros = 16; 130 | 24'b000000000000000001??????: s_dvd_zeros = 17; 131 | 24'b0000000000000000001?????: s_dvd_zeros = 18; 132 | 24'b00000000000000000001????: s_dvd_zeros = 19; 133 | 24'b000000000000000000001???: s_dvd_zeros = 20; 134 | 24'b0000000000000000000001??: s_dvd_zeros = 21; 135 | 24'b00000000000000000000001?: s_dvd_zeros = 22; 136 | 24'b000000000000000000000001: s_dvd_zeros = 23; 137 | 24'b000000000000000000000000: s_dvd_zeros = 24; 138 | endcase 139 | 140 | //s_div_zeros <= count_l_zeros( s_fractb_24 ); 141 | always @(s_fractb_24) 142 | casez(s_fractb_24) // synopsys full_case parallel_case 143 | 24'b1???????????????????????: s_div_zeros = 0; 144 | 24'b01??????????????????????: s_div_zeros = 1; 145 | 24'b001?????????????????????: s_div_zeros = 2; 146 | 24'b0001????????????????????: s_div_zeros = 3; 147 | 24'b00001???????????????????: s_div_zeros = 4; 148 | 24'b000001??????????????????: s_div_zeros = 5; 149 | 24'b0000001?????????????????: s_div_zeros = 6; 150 | 24'b00000001????????????????: s_div_zeros = 7; 151 | 24'b000000001???????????????: s_div_zeros = 8; 152 | 24'b0000000001??????????????: s_div_zeros = 9; 153 | 24'b00000000001?????????????: s_div_zeros = 10; 154 | 24'b000000000001????????????: s_div_zeros = 11; 155 | 24'b0000000000001???????????: s_div_zeros = 12; 156 | 24'b00000000000001??????????: s_div_zeros = 13; 157 | 24'b000000000000001?????????: s_div_zeros = 14; 158 | 24'b0000000000000001????????: s_div_zeros = 15; 159 | 24'b00000000000000001???????: s_div_zeros = 16; 160 | 24'b000000000000000001??????: s_div_zeros = 17; 161 | 24'b0000000000000000001?????: s_div_zeros = 18; 162 | 24'b00000000000000000001????: s_div_zeros = 19; 163 | 24'b000000000000000000001???: s_div_zeros = 20; 164 | 24'b0000000000000000000001??: s_div_zeros = 21; 165 | 24'b00000000000000000000001?: s_div_zeros = 22; 166 | 24'b000000000000000000000001: s_div_zeros = 23; 167 | 24'b000000000000000000000000: s_div_zeros = 24; 168 | endcase 169 | 170 | // left-shift the dividend and divisor 171 | wire [FRAC_WIDTH:0] fracta_lshift_intermediate; 172 | wire [FRAC_WIDTH:0] fractb_lshift_intermediate; 173 | assign fracta_lshift_intermediate = s_fracta_24 << s_dvd_zeros; 174 | assign fractb_lshift_intermediate = s_fractb_24 << s_div_zeros; 175 | 176 | assign s_dvdnd_50_o = {fracta_lshift_intermediate,26'd0}; 177 | 178 | assign s_dvsor_27_o = {3'd0,fractb_lshift_intermediate}; 179 | 180 | always @(posedge clk_i) 181 | begin 182 | // pre-calculate exponent 183 | s_expa_in <= {2'd0,s_expa} + {9'd0,s_opa_dn}; 184 | s_expb_in <= {2'd0,s_expb} + {9'd0,s_opb_dn}; 185 | s_exp_10_o <= s_expa_in - s_expb_in + 10'b0001111111 - 186 | {4'd0,s_dvd_zeros} + {4'd0,s_div_zeros}; 187 | end 188 | 189 | 190 | endmodule // or1200_fpu_pre_norm_div 191 | 192 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_fpu_pre_norm_mul.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// or1200_fpu_pre_norm_mul //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// pre-normalization entity for the multiplication unit //// 10 | //// //// 11 | //// To Do: //// 12 | //// //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Original design (FPU100) - //// 16 | //// Jidan Al-eryani, jidan@gmx.net //// 17 | //// - Conv. to Verilog and inclusion in OR1200 - //// 18 | //// Julius Baxter, julius@opencores.org //// 19 | //// //// 20 | ////////////////////////////////////////////////////////////////////// 21 | // 22 | // Copyright (C) 2006, 2010 23 | // 24 | // This source file may be used and distributed without 25 | // restriction provided that this copyright statement is not 26 | // removed from the file and that any derivative work contains 27 | // the original copyright notice and the associated disclaimer. 28 | // 29 | // THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY 30 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 | // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 32 | // FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR 33 | // OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 34 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 | // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 | // GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 | // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 38 | // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 40 | // OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 | // POSSIBILITY OF SUCH DAMAGE. 42 | // 43 | 44 | module or1200_fpu_pre_norm_mul ( 45 | clk_i, 46 | opa_i, 47 | opb_i, 48 | exp_10_o, 49 | fracta_24_o, 50 | fractb_24_o 51 | ); 52 | 53 | parameter FP_WIDTH = 32; 54 | parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial 55 | parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial 56 | parameter FRAC_WIDTH = 23; 57 | parameter EXP_WIDTH = 8; 58 | parameter ZERO_VECTOR = 31'd0; 59 | parameter INF = 31'b1111111100000000000000000000000; 60 | parameter QNAN = 31'b1111111110000000000000000000000; 61 | parameter SNAN = 31'b1111111100000000000000000000001; 62 | 63 | 64 | input clk_i; 65 | input [FP_WIDTH-1:0] opa_i; 66 | input [FP_WIDTH-1:0] opb_i; 67 | output reg [EXP_WIDTH+1:0] exp_10_o; 68 | output [FRAC_WIDTH:0] fracta_24_o; 69 | output [FRAC_WIDTH:0] fractb_24_o; 70 | 71 | 72 | wire [EXP_WIDTH-1:0] s_expa; 73 | wire [EXP_WIDTH-1:0] s_expb; 74 | 75 | wire [FRAC_WIDTH-1:0] s_fracta; 76 | wire [FRAC_WIDTH-1:0] s_fractb; 77 | 78 | wire [EXP_WIDTH+1:0] s_exp_10_o; 79 | wire [EXP_WIDTH+1:0] s_expa_in; 80 | wire [EXP_WIDTH+1:0] s_expb_in; 81 | 82 | wire s_opa_dn, s_opb_dn; 83 | 84 | assign s_expa = opa_i[30:23]; 85 | assign s_expb = opb_i[30:23]; 86 | assign s_fracta = opa_i[22:0]; 87 | assign s_fractb = opb_i[22:0]; 88 | 89 | // Output Register 90 | always @(posedge clk_i) 91 | exp_10_o <= s_exp_10_o; 92 | 93 | // opa or opb is denormalized 94 | assign s_opa_dn = !(|s_expa); 95 | assign s_opb_dn = !(|s_expb); 96 | 97 | assign fracta_24_o = {!s_opa_dn, s_fracta}; 98 | assign fractb_24_o = {!s_opb_dn, s_fractb}; 99 | 100 | assign s_expa_in = {2'd0, s_expa} + {9'd0, s_opa_dn}; 101 | assign s_expb_in = {2'd0, s_expb} + {9'd0, s_opb_dn}; 102 | 103 | assign s_exp_10_o = s_expa_in + s_expb_in - 10'b0001111111; 104 | 105 | endmodule // or1200_fpu_pre_norm_mul 106 | 107 | 108 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_freeze.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's Freeze logic //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://www.opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// Generates all freezes and stalls inside RISC //// 10 | //// //// 11 | //// To Do: //// 12 | //// - make it smaller and faster //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // $Log: or1200_freeze.v,v $ 45 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 46 | // Minor update: 47 | // Bugs fixed. 48 | // 49 | 50 | // synopsys translate_off 51 | `include "timescale.v" 52 | // synopsys translate_on 53 | `include "or1200_defines.v" 54 | 55 | `define OR1200_NO_FREEZE 3'd0 56 | `define OR1200_FREEZE_BYDC 3'd1 57 | `define OR1200_FREEZE_BYMULTICYCLE 3'd2 58 | `define OR1200_WAIT_LSU_TO_FINISH 3'd3 59 | `define OR1200_WAIT_IC 3'd4 60 | 61 | // 62 | // Freeze logic (stalls CPU pipeline, ifetcher etc.) 63 | // 64 | module or1200_freeze 65 | ( 66 | // Clock and reset 67 | clk, rst, 68 | 69 | // Internal i/f 70 | multicycle, wait_on, flushpipe, extend_flush, lsu_stall, if_stall, 71 | lsu_unstall, du_stall, mac_stall, 72 | force_dslot_fetch, abort_ex, 73 | genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze, saving_if_insn, 74 | fpu_done, mtspr_done, 75 | icpu_ack_i, icpu_err_i 76 | ); 77 | 78 | // 79 | // I/O 80 | // 81 | input clk; 82 | input rst; 83 | input [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; 84 | input [`OR1200_WAIT_ON_WIDTH-1:0] wait_on; 85 | input flushpipe; 86 | input extend_flush; 87 | input lsu_stall; 88 | input if_stall; 89 | input lsu_unstall; 90 | input force_dslot_fetch; 91 | input abort_ex; 92 | input du_stall; 93 | input mac_stall; 94 | output genpc_freeze; 95 | output if_freeze; 96 | output id_freeze; 97 | output ex_freeze; 98 | output wb_freeze; 99 | input saving_if_insn; 100 | input fpu_done; 101 | input mtspr_done; 102 | input icpu_ack_i; 103 | input icpu_err_i; 104 | 105 | // 106 | // Internal wires and regs 107 | // 108 | wire multicycle_freeze; 109 | reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt; 110 | reg flushpipe_r; 111 | reg [`OR1200_WAIT_ON_WIDTH-1:0] waiting_on; 112 | 113 | // 114 | // Pipeline freeze 115 | // 116 | // Rules how to create freeze signals: 117 | // 1. Not overwriting pipeline stages: 118 | // Freeze signals at the beginning of pipeline (such as if_freeze) can be 119 | // asserted more often than freeze signals at the of pipeline (such as 120 | // wb_freeze). In other words, wb_freeze must never be asserted when ex_freeze 121 | // is not. ex_freeze must never be asserted when id_freeze is not etc. 122 | // 123 | // 2. Inserting NOPs in the middle of pipeline only if supported: 124 | // At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze 125 | // (and if_freeze) are asserted. 126 | // This way NOP is asserted from stage ID into EX stage. 127 | // 128 | 129 | assign genpc_freeze = (du_stall & !saving_if_insn) | flushpipe_r; 130 | assign if_freeze = id_freeze | extend_flush; 131 | 132 | assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze 133 | | (|waiting_on) | force_dslot_fetch) | du_stall; 134 | assign ex_freeze = wb_freeze; 135 | 136 | assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze 137 | | (|waiting_on)) | du_stall | abort_ex; 138 | 139 | // 140 | // registered flushpipe 141 | // 142 | always @(posedge clk or `OR1200_RST_EVENT rst) 143 | if (rst == `OR1200_RST_VALUE) 144 | flushpipe_r <= 1'b0; 145 | else if (icpu_ack_i | icpu_err_i) 146 | // else if (!if_stall) 147 | flushpipe_r <= flushpipe; 148 | else if (!flushpipe) 149 | flushpipe_r <= 1'b0; 150 | 151 | // 152 | // Multicycle freeze 153 | // 154 | assign multicycle_freeze = |multicycle_cnt; 155 | 156 | // 157 | // Multicycle counter 158 | // 159 | always @(posedge clk or `OR1200_RST_EVENT rst) 160 | if (rst == `OR1200_RST_VALUE) 161 | multicycle_cnt <= `OR1200_MULTICYCLE_WIDTH'd0; 162 | else if (|multicycle_cnt) 163 | multicycle_cnt <= multicycle_cnt - `OR1200_MULTICYCLE_WIDTH'd1; 164 | else if (|multicycle & !ex_freeze) 165 | multicycle_cnt <= multicycle; 166 | 167 | 168 | // 169 | // Waiting on generation 170 | // 171 | always @(posedge clk or `OR1200_RST_EVENT rst) 172 | if (rst == `OR1200_RST_VALUE) 173 | waiting_on <= 0; 174 | else if ((waiting_on == `OR1200_WAIT_ON_MULTMAC) & !mac_stall) 175 | waiting_on <= 0; 176 | else if ((waiting_on == `OR1200_WAIT_ON_FPU) & fpu_done) 177 | waiting_on <= 0; 178 | else if ((waiting_on == `OR1200_WAIT_ON_MTSPR) & mtspr_done) 179 | waiting_on <= 0; 180 | else if (!ex_freeze) 181 | waiting_on <= wait_on; 182 | 183 | 184 | endmodule 185 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_gmultp2_32x32.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Generic 32x32 multiplier //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://www.opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// Generic 32x32 multiplier with pipeline stages. //// 10 | //// //// 11 | //// To Do: //// 12 | //// - make it smaller and faster //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // CVS Revision History 45 | // 46 | // $Log: or1200_gmultp2_32x32.v,v $ 47 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 48 | // No update 49 | // 50 | 51 | // synopsys translate_off 52 | `include "timescale.v" 53 | // synopsys translate_on 54 | `include "or1200_defines.v" 55 | 56 | // 32x32 multiplier, no input/output registers 57 | // Registers inside Wallace trees every 8 full adder levels, 58 | // with first pipeline after level 4 59 | 60 | `ifdef OR1200_GENERIC_MULTP2_32X32 61 | 62 | `define OR1200_W 32 63 | `define OR1200_WW 64 64 | 65 | module or1200_gmultp2_32x32 ( X, Y, CLK, RST, P ); 66 | 67 | input [`OR1200_W-1:0] X; 68 | input [`OR1200_W-1:0] Y; 69 | input CLK; 70 | input RST; 71 | output [`OR1200_WW-1:0] P; 72 | 73 | reg [`OR1200_W-1:0] X_saved; 74 | reg [`OR1200_W-1:0] Y_saved; 75 | reg [`OR1200_WW-1:0] p1; 76 | integer xi; 77 | integer yi; 78 | 79 | // 80 | // Conversion unsigned to signed 81 | // 82 | always @(X_saved) 83 | xi = X_saved; 84 | 85 | // 86 | // Conversion unsigned to signed 87 | // 88 | always @(Y_saved) 89 | yi = Y_saved; 90 | 91 | // 92 | // First multiply stage 93 | // 94 | always @(posedge CLK or `OR1200_RST_EVENT RST) 95 | if (RST == `OR1200_RST_VALUE) begin 96 | X_saved <= `OR1200_W'b0; 97 | Y_saved <= `OR1200_W'b0; 98 | end 99 | else begin 100 | X_saved <= X; 101 | Y_saved <= Y; 102 | end 103 | 104 | // 105 | // Second multiply stage 106 | // 107 | always @(posedge CLK or `OR1200_RST_EVENT RST) 108 | if (RST == `OR1200_RST_VALUE) 109 | p1 <= `OR1200_WW'b0; 110 | else 111 | p1 <= xi * yi; 112 | 113 | assign P = p1; 114 | 115 | endmodule 116 | 117 | `endif 118 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_ic_ram.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's IC RAMs //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://www.opencores.org/cores/or1k/ //// 7 | //// //// 8 | //// Description //// 9 | //// Instantiation of Instruction cache data rams //// 10 | //// //// 11 | //// To Do: //// 12 | //// - make it smaller and faster //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // CVS Revision History 45 | // 46 | // $Log: or1200_ic_ram.v,v $ 47 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 48 | // Minor update: 49 | // Coding style changed. 50 | // 51 | 52 | // synopsys translate_off 53 | `include "timescale.v" 54 | // synopsys translate_on 55 | `include "or1200_defines.v" 56 | 57 | module or1200_ic_ram( 58 | // Clock and reset 59 | clk, rst, 60 | 61 | `ifdef OR1200_BIST 62 | // RAM BIST 63 | mbist_si_i, mbist_so_o, mbist_ctrl_i, 64 | `endif 65 | 66 | // Internal i/f 67 | addr, en, we, datain, dataout 68 | ); 69 | 70 | parameter dw = `OR1200_OPERAND_WIDTH; 71 | parameter aw = `OR1200_ICINDX; 72 | 73 | // 74 | // I/O 75 | // 76 | input clk; 77 | input rst; 78 | input [aw-1:0] addr; 79 | input en; 80 | input [3:0] we; 81 | input [dw-1:0] datain; 82 | output [dw-1:0] dataout; 83 | 84 | `ifdef OR1200_BIST 85 | // 86 | // RAM BIST 87 | // 88 | input mbist_si_i; 89 | input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; 90 | output mbist_so_o; 91 | `endif 92 | 93 | `ifdef OR1200_NO_IC 94 | 95 | // 96 | // Insn cache not implemented 97 | // 98 | assign dataout = {dw{1'b0}}; 99 | `ifdef OR1200_BIST 100 | assign mbist_so_o = mbist_si_i; 101 | `endif 102 | 103 | `else 104 | 105 | // 106 | // Instantiation of IC RAM block 107 | // 108 | or1200_spram # 109 | ( 110 | .aw(`OR1200_ICINDX), 111 | .dw(32) 112 | ) 113 | ic_ram0 114 | ( 115 | `ifdef OR1200_BIST 116 | // RAM BIST 117 | .mbist_si_i(mbist_si_i), 118 | .mbist_so_o(mbist_so_o), 119 | .mbist_ctrl_i(mbist_ctrl_i), 120 | `endif 121 | .clk(clk), 122 | .ce(en), 123 | .we(we[0]), 124 | //.oe(1'b1), 125 | .addr(addr), 126 | .di(datain), 127 | .doq(dataout) 128 | ); 129 | `endif 130 | 131 | endmodule 132 | 133 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_ic_tag.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's IC TAGs //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://www.opencores.org/cores/or1k/ //// 7 | //// //// 8 | //// Description //// 9 | //// Instatiation of instruction cache tag rams //// 10 | //// //// 11 | //// To Do: //// 12 | //// - make it smaller and faster //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // CVS Revision History 45 | // 46 | // $Log: or1200_ic_tag.v,v $ 47 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 48 | // Minor update: 49 | // Coding style changed. 50 | // 51 | 52 | // synopsys translate_off 53 | `include "timescale.v" 54 | // synopsys translate_on 55 | `include "or1200_defines.v" 56 | 57 | module or1200_ic_tag( 58 | // Clock and reset 59 | clk, rst, 60 | 61 | `ifdef OR1200_BIST 62 | // RAM BIST 63 | mbist_si_i, mbist_so_o, mbist_ctrl_i, 64 | `endif 65 | 66 | // Internal i/f 67 | addr, en, we, datain, tag_v, tag 68 | ); 69 | 70 | parameter dw = `OR1200_ICTAG_W; 71 | parameter aw = `OR1200_ICTAG; 72 | 73 | // 74 | // I/O 75 | // 76 | 77 | // 78 | // Clock and reset 79 | // 80 | input clk; 81 | input rst; 82 | 83 | `ifdef OR1200_BIST 84 | // 85 | // RAM BIST 86 | // 87 | input mbist_si_i; 88 | input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; 89 | output mbist_so_o; 90 | `endif 91 | 92 | // 93 | // Internal i/f 94 | // 95 | input [aw-1:0] addr; 96 | input en; 97 | input we; 98 | input [dw-1:0] datain; 99 | output tag_v; 100 | output [dw-2:0] tag; 101 | 102 | `ifdef OR1200_NO_IC 103 | 104 | // 105 | // Insn cache not implemented 106 | // 107 | assign tag = {dw-1{1'b0}}; 108 | assign tag_v = 1'b0; 109 | `ifdef OR1200_BIST 110 | assign mbist_so_o = mbist_si_i; 111 | `endif 112 | 113 | `else 114 | 115 | // 116 | // Instantiation of TAG RAM block 117 | // 118 | or1200_spram # 119 | ( 120 | .aw(`OR1200_ICTAG), 121 | .dw(`OR1200_ICTAG_W) 122 | ) 123 | ic_tag0 124 | ( 125 | `ifdef OR1200_BIST 126 | // RAM BIST 127 | .mbist_si_i(mbist_si_i), 128 | .mbist_so_o(mbist_so_o), 129 | .mbist_ctrl_i(mbist_ctrl_i), 130 | `endif 131 | .clk(clk), 132 | .ce(en), 133 | .we(we), 134 | //.oe(1'b1), 135 | .addr(addr), 136 | .di(datain), 137 | .doq({tag, tag_v}) 138 | ); 139 | `endif 140 | 141 | endmodule 142 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_if.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's instruction fetch //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://www.opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// PC, instruction fetch, interface to IC. //// 10 | //// //// 11 | //// To Do: //// 12 | //// - make it smaller and faster //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // $Log: or1200_if.v,v $ 45 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 46 | // Major update: 47 | // Structure reordered and bugs fixed. 48 | 49 | // synopsys translate_off 50 | `include "timescale.v" 51 | // synopsys translate_on 52 | `include "or1200_defines.v" 53 | 54 | module or1200_if( 55 | // Clock and reset 56 | clk, rst, 57 | 58 | // External i/f to IC 59 | icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i, 60 | 61 | // Internal i/f 62 | if_freeze, if_insn, if_pc, if_flushpipe, saving_if_insn, 63 | if_stall, no_more_dslot, genpc_refetch, rfe, 64 | except_itlbmiss, except_immufault, except_ibuserr 65 | ); 66 | 67 | // 68 | // I/O 69 | // 70 | 71 | // 72 | // Clock and reset 73 | // 74 | input clk; 75 | input rst; 76 | 77 | // 78 | // External i/f to IC 79 | // 80 | input [31:0] icpu_dat_i; 81 | input icpu_ack_i; 82 | input icpu_err_i; 83 | input [31:0] icpu_adr_i; 84 | input [3:0] icpu_tag_i; 85 | 86 | // 87 | // Internal i/f 88 | // 89 | input if_freeze; 90 | output [31:0] if_insn; 91 | output [31:0] if_pc; 92 | input if_flushpipe; 93 | output saving_if_insn; 94 | output if_stall; 95 | input no_more_dslot; 96 | output genpc_refetch; 97 | input rfe; 98 | output except_itlbmiss; 99 | output except_immufault; 100 | output except_ibuserr; 101 | 102 | // 103 | // Internal wires and regs 104 | // 105 | wire save_insn; 106 | wire if_bypass; 107 | reg if_bypass_reg; 108 | reg [31:0] insn_saved; 109 | reg [31:0] addr_saved; 110 | reg [2:0] err_saved; 111 | reg saved; 112 | 113 | assign save_insn = (icpu_ack_i | icpu_err_i) & if_freeze & !saved; 114 | assign saving_if_insn = !if_flushpipe & save_insn; 115 | 116 | // 117 | // IF bypass 118 | // 119 | assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe; 120 | 121 | always @(posedge clk or `OR1200_RST_EVENT rst) 122 | if (rst == `OR1200_RST_VALUE) 123 | if_bypass_reg <= 1'b0; 124 | else 125 | if_bypass_reg <= if_bypass; 126 | 127 | // 128 | // IF stage insn 129 | // 130 | assign if_insn = no_more_dslot | rfe | if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000}; 131 | assign if_pc = saved ? addr_saved : {icpu_adr_i[31:2], 2'h0}; 132 | assign if_stall = !icpu_err_i & !icpu_ack_i & !saved; 133 | assign genpc_refetch = saved & icpu_ack_i; 134 | assign except_itlbmiss = no_more_dslot ? 1'b0 : saved ? err_saved[0] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE); 135 | assign except_immufault = no_more_dslot ? 1'b0 : saved ? err_saved[1] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE); 136 | assign except_ibuserr = no_more_dslot ? 1'b0 : saved ? err_saved[2] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE); 137 | 138 | // 139 | // Flag for saved insn/address 140 | // 141 | always @(posedge clk or `OR1200_RST_EVENT rst) 142 | if (rst == `OR1200_RST_VALUE) 143 | saved <= 1'b0; 144 | else if (if_flushpipe) 145 | saved <= 1'b0; 146 | else if (save_insn) 147 | saved <= 1'b1; 148 | else if (!if_freeze) 149 | saved <= 1'b0; 150 | 151 | // 152 | // Store fetched instruction 153 | // 154 | always @(posedge clk or `OR1200_RST_EVENT rst) 155 | if (rst == `OR1200_RST_VALUE) 156 | insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000}; 157 | else if (if_flushpipe) 158 | insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000}; 159 | else if (save_insn) 160 | insn_saved <= icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i; 161 | else if (!if_freeze) 162 | insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000}; 163 | 164 | // 165 | // Store fetched instruction's address 166 | // 167 | always @(posedge clk or `OR1200_RST_EVENT rst) 168 | if (rst == `OR1200_RST_VALUE) 169 | addr_saved <= 32'h00000000; 170 | else if (if_flushpipe) 171 | addr_saved <= 32'h00000000; 172 | else if (save_insn) 173 | addr_saved <= {icpu_adr_i[31:2], 2'b00}; 174 | else if (!if_freeze) 175 | addr_saved <= {icpu_adr_i[31:2], 2'b00}; 176 | 177 | // 178 | // Store fetched instruction's error tags 179 | // 180 | always @(posedge clk or `OR1200_RST_EVENT rst) 181 | if (rst == `OR1200_RST_VALUE) 182 | err_saved <= 3'b000; 183 | else if (if_flushpipe) 184 | err_saved <= 3'b000; 185 | else if (save_insn) begin 186 | err_saved[0] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE); 187 | err_saved[1] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE); 188 | err_saved[2] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE); 189 | end 190 | else if (!if_freeze) 191 | err_saved <= 3'b000; 192 | 193 | 194 | endmodule 195 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_iwb_biu.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's WISHBONE BIU //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// Implements WISHBONE interface //// 10 | //// //// 11 | //// To Do: //// 12 | //// - if biu_cyc/stb are deasserted and wb_ack_i is asserted //// 13 | //// and this happens even before aborted_r is asssrted, //// 14 | //// wb_ack_i will be delivered even though transfer is //// 15 | //// internally considered already aborted. However most //// 16 | //// wb_ack_i are externally registered and delayed. Normally //// 17 | //// this shouldn't cause any problems. //// 18 | //// //// 19 | //// Author(s): //// 20 | //// - Damjan Lampret, lampret@opencores.org //// 21 | //// //// 22 | ////////////////////////////////////////////////////////////////////// 23 | //// //// 24 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 25 | //// //// 26 | //// This source file may be used and distributed without //// 27 | //// restriction provided that this copyright statement is not //// 28 | //// removed from the file and that any derivative work contains //// 29 | //// the original copyright notice and the associated disclaimer. //// 30 | //// //// 31 | //// This source file is free software; you can redistribute it //// 32 | //// and/or modify it under the terms of the GNU Lesser General //// 33 | //// Public License as published by the Free Software Foundation; //// 34 | //// either version 2.1 of the License, or (at your option) any //// 35 | //// later version. //// 36 | //// //// 37 | //// This source is distributed in the hope that it will be //// 38 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 39 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 40 | //// PURPOSE. See the GNU Lesser General Public License for more //// 41 | //// details. //// 42 | //// //// 43 | //// You should have received a copy of the GNU Lesser General //// 44 | //// Public License along with this source; if not, download it //// 45 | //// from http://www.opencores.org/lgpl.shtml //// 46 | //// //// 47 | ////////////////////////////////////////////////////////////////////// 48 | // 49 | // $Log: or1200_iwb_biu.v,v $ 50 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 51 | // Major update: 52 | // This module is obsolete. 53 | // 54 | 55 | // synopsys translate_off 56 | `include "timescale.v" 57 | // synopsys translate_on 58 | `include "or1200_defines.v" 59 | 60 | module or1200_iwb_biu(); 61 | 62 | // THIS MODULE IS OBSOLETE !!! 63 | // COMPLETELY REWRITTEN or1200_wb_biu.v IS USED INSTEAD !!! 64 | 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_operandmuxes.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's register file read operands mux //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://www.opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// Mux for two register file read operands. //// 10 | //// //// 11 | //// To Do: //// 12 | //// - make it smaller and faster //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // $Log: or1200_operandmuxes.v,v $ 45 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 46 | // Minor update: 47 | // Bugs fixed. 48 | 49 | // synopsys translate_off 50 | `include "timescale.v" 51 | // synopsys translate_on 52 | `include "or1200_defines.v" 53 | 54 | module or1200_operandmuxes( 55 | // Clock and reset 56 | clk, rst, 57 | 58 | // Internal i/f 59 | id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw, 60 | simm, sel_a, sel_b, operand_a, operand_b, muxed_a, muxed_b 61 | ); 62 | 63 | parameter width = `OR1200_OPERAND_WIDTH; 64 | 65 | // 66 | // I/O 67 | // 68 | input clk; 69 | input rst; 70 | input id_freeze; 71 | input ex_freeze; 72 | input [width-1:0] rf_dataa; 73 | input [width-1:0] rf_datab; 74 | input [width-1:0] ex_forw; 75 | input [width-1:0] wb_forw; 76 | input [width-1:0] simm; 77 | input [`OR1200_SEL_WIDTH-1:0] sel_a; 78 | input [`OR1200_SEL_WIDTH-1:0] sel_b; 79 | output [width-1:0] operand_a; 80 | output [width-1:0] operand_b; 81 | output [width-1:0] muxed_a; 82 | output [width-1:0] muxed_b; 83 | 84 | // 85 | // Internal wires and regs 86 | // 87 | reg [width-1:0] operand_a; 88 | reg [width-1:0] operand_b; 89 | reg [width-1:0] muxed_a; 90 | reg [width-1:0] muxed_b; 91 | reg saved_a; 92 | reg saved_b; 93 | 94 | // 95 | // Operand A register 96 | // 97 | always @(posedge clk or `OR1200_RST_EVENT rst) begin 98 | if (rst == `OR1200_RST_VALUE) begin 99 | operand_a <= 32'd0; 100 | saved_a <= 1'b0; 101 | end else if (!ex_freeze && id_freeze && !saved_a) begin 102 | operand_a <= muxed_a; 103 | saved_a <= 1'b1; 104 | end else if (!ex_freeze && !saved_a) begin 105 | operand_a <= muxed_a; 106 | end else if (!ex_freeze && !id_freeze) 107 | saved_a <= 1'b0; 108 | end 109 | 110 | // 111 | // Operand B register 112 | // 113 | always @(posedge clk or `OR1200_RST_EVENT rst) begin 114 | if (rst == `OR1200_RST_VALUE) begin 115 | operand_b <= 32'd0; 116 | saved_b <= 1'b0; 117 | end else if (!ex_freeze && id_freeze && !saved_b) begin 118 | operand_b <= muxed_b; 119 | saved_b <= 1'b1; 120 | end else if (!ex_freeze && !saved_b) begin 121 | operand_b <= muxed_b; 122 | end else if (!ex_freeze && !id_freeze) 123 | saved_b <= 1'b0; 124 | end 125 | 126 | // 127 | // Forwarding logic for operand A register 128 | // 129 | always @(ex_forw or wb_forw or rf_dataa or sel_a) begin 130 | `ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES 131 | casez (sel_a) // synopsys parallel_case infer_mux 132 | `else 133 | casez (sel_a) // synopsys parallel_case 134 | `endif 135 | `OR1200_SEL_EX_FORW: 136 | muxed_a = ex_forw; 137 | `OR1200_SEL_WB_FORW: 138 | muxed_a = wb_forw; 139 | default: 140 | muxed_a = rf_dataa; 141 | endcase 142 | end 143 | 144 | // 145 | // Forwarding logic for operand B register 146 | // 147 | always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin 148 | `ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES 149 | casez (sel_b) // synopsys parallel_case infer_mux 150 | `else 151 | casez (sel_b) // synopsys parallel_case 152 | `endif 153 | `OR1200_SEL_IMM: 154 | muxed_b = simm; 155 | `OR1200_SEL_EX_FORW: 156 | muxed_b = ex_forw; 157 | `OR1200_SEL_WB_FORW: 158 | muxed_b = wb_forw; 159 | default: 160 | muxed_b = rf_datab; 161 | endcase 162 | end 163 | 164 | endmodule 165 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_pic.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's Programmable Interrupt Controller //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://www.opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// PIC according to OR1K architectural specification. //// 10 | //// //// 11 | //// To Do: //// 12 | //// None //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // $Log: or1200_pic.v,v $ 45 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 46 | // 47 | 48 | // synopsys translate_off 49 | `include "timescale.v" 50 | // synopsys translate_on 51 | `include "or1200_defines.v" 52 | 53 | module or1200_pic( 54 | // RISC Internal Interface 55 | clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, 56 | pic_wakeup, intr, 57 | 58 | // PIC Interface 59 | pic_int 60 | ); 61 | 62 | // 63 | // RISC Internal Interface 64 | // 65 | input clk; // Clock 66 | input rst; // Reset 67 | input spr_cs; // SPR CS 68 | input spr_write; // SPR Write 69 | input [31:0] spr_addr; // SPR Address 70 | input [31:0] spr_dat_i; // SPR Write Data 71 | output [31:0] spr_dat_o; // SPR Read Data 72 | output pic_wakeup; // Wakeup to the PM 73 | output intr; // interrupt 74 | // exception request 75 | 76 | // 77 | // PIC Interface 78 | // 79 | input [`OR1200_PIC_INTS-1:0] pic_int;// Interrupt inputs 80 | 81 | `ifdef OR1200_PIC_IMPLEMENTED 82 | 83 | // 84 | // PIC Mask Register bits (or no register) 85 | // 86 | `ifdef OR1200_PIC_PICMR 87 | reg [`OR1200_PIC_INTS-1:2] picmr; // PICMR bits 88 | `else 89 | wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register 90 | `endif 91 | 92 | // 93 | // PIC Status Register bits (or no register) 94 | // 95 | `ifdef OR1200_PIC_PICSR 96 | reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits 97 | `else 98 | wire [`OR1200_PIC_INTS-1:0] picsr; // No PICSR register 99 | `endif 100 | 101 | // 102 | // Internal wires & regs 103 | // 104 | wire picmr_sel; // PICMR select 105 | wire picsr_sel; // PICSR select 106 | wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts 107 | reg [31:0] spr_dat_o; // SPR data out 108 | 109 | // 110 | // PIC registers address decoder 111 | // 112 | assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0; 113 | assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0; 114 | 115 | // 116 | // Write to PICMR 117 | // 118 | `ifdef OR1200_PIC_PICMR 119 | always @(posedge clk or `OR1200_RST_EVENT rst) 120 | if (rst == `OR1200_RST_VALUE) 121 | picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}}; 122 | else if (picmr_sel && spr_write) begin 123 | picmr <= spr_dat_i[`OR1200_PIC_INTS-1:2]; 124 | end 125 | `else 126 | assign picmr = (`OR1200_PIC_INTS)'b1; 127 | `endif 128 | 129 | // 130 | // Write to PICSR, both CPU and external ints 131 | // 132 | `ifdef OR1200_PIC_PICSR 133 | always @(posedge clk or `OR1200_RST_EVENT rst) 134 | if (rst == `OR1200_RST_VALUE) 135 | picsr <= {`OR1200_PIC_INTS{1'b0}}; 136 | else if (picsr_sel && spr_write) begin 137 | picsr <= spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints; 138 | end else 139 | picsr <= picsr | um_ints; 140 | `else 141 | assign picsr = pic_int; 142 | `endif 143 | 144 | // 145 | // Read PIC registers 146 | // 147 | always @(spr_addr or picmr or picsr) 148 | case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys parallel_case 149 | `ifdef OR1200_PIC_READREGS 150 | `OR1200_PIC_OFS_PICMR: begin 151 | spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b11}; 152 | `ifdef OR1200_PIC_UNUSED_ZERO 153 | spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}}; 154 | `endif 155 | end 156 | `endif 157 | default: begin 158 | spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr; 159 | `ifdef OR1200_PIC_UNUSED_ZERO 160 | spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}}; 161 | `endif 162 | end 163 | endcase 164 | 165 | // 166 | // Unmasked interrupts 167 | // 168 | assign um_ints = pic_int & {picmr, 2'b11}; 169 | 170 | // 171 | // Generate intr 172 | // 173 | assign intr = |um_ints; 174 | 175 | // 176 | // Assert pic_wakeup when intr is asserted 177 | // 178 | assign pic_wakeup = intr; 179 | 180 | `else 181 | 182 | // 183 | // When PIC is not implemented, drive all outputs as would when PIC is disabled 184 | // 185 | assign intr = pic_int[1] | pic_int[0]; 186 | assign pic_wakeup= intr; 187 | 188 | // 189 | // Read PIC registers 190 | // 191 | `ifdef OR1200_PIC_READREGS 192 | assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0; 193 | `ifdef OR1200_PIC_UNUSED_ZERO 194 | assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0; 195 | `endif 196 | `endif 197 | 198 | `endif 199 | 200 | endmodule 201 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_pm.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's Power Management //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://www.opencores.org/cores/or1k/ //// 7 | //// //// 8 | //// Description //// 9 | //// PM according to OR1K architectural specification. //// 10 | //// //// 11 | //// To Do: //// 12 | //// - add support for dynamic clock gating //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // CVS Revision History 45 | // 46 | // $Log: or1200_pm.v,v $ 47 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 48 | // No update 49 | // 50 | // Revision 1.1 2002/01/03 08:16:15 lampret 51 | // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. 52 | // 53 | // Revision 1.8 2001/10/21 17:57:16 lampret 54 | // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. 55 | // 56 | // Revision 1.7 2001/10/14 13:12:10 lampret 57 | // MP3 version. 58 | // 59 | // Revision 1.1.1.1 2001/10/06 10:18:35 igorm 60 | // no message 61 | // 62 | // Revision 1.2 2001/08/09 13:39:33 lampret 63 | // Major clean-up. 64 | // 65 | // Revision 1.1 2001/07/20 00:46:21 lampret 66 | // Development version of RTL. Libraries are missing. 67 | // 68 | // 69 | 70 | // synopsys translate_off 71 | `include "timescale.v" 72 | // synopsys translate_on 73 | `include "or1200_defines.v" 74 | 75 | module or1200_pm( 76 | // RISC Internal Interface 77 | clk, rst, pic_wakeup, spr_write, spr_addr, spr_dat_i, spr_dat_o, 78 | 79 | // Power Management Interface 80 | pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, 81 | pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt 82 | ); 83 | 84 | // 85 | // RISC Internal Interface 86 | // 87 | input clk; // Clock 88 | input rst; // Reset 89 | input pic_wakeup; // Wakeup from the PIC 90 | input spr_write; // SPR Read/Write 91 | input [31:0] spr_addr; // SPR Address 92 | input [31:0] spr_dat_i; // SPR Write Data 93 | output [31:0] spr_dat_o; // SPR Read Data 94 | 95 | // 96 | // Power Management Interface 97 | // 98 | input pm_cpustall; // Stall the CPU 99 | output [3:0] pm_clksd; // Clock Slowdown factor 100 | output pm_dc_gate; // Gate DCache clock 101 | output pm_ic_gate; // Gate ICache clock 102 | output pm_dmmu_gate; // Gate DMMU clock 103 | output pm_immu_gate; // Gate IMMU clock 104 | output pm_tt_gate; // Gate Tick Timer clock 105 | output pm_cpu_gate; // Gate main RISC/CPU clock 106 | output pm_wakeup; // Activate (de-gate) all clocks 107 | output pm_lvolt; // Lower operating voltage 108 | 109 | `ifdef OR1200_PM_IMPLEMENTED 110 | 111 | // 112 | // Power Management Register bits 113 | // 114 | reg [3:0] sdf; // Slow-down factor 115 | reg dme; // Doze Mode Enable 116 | reg sme; // Sleep Mode Enable 117 | reg dcge; // Dynamic Clock Gating Enable 118 | 119 | // 120 | // Internal wires 121 | // 122 | wire pmr_sel; // PMR select 123 | 124 | // 125 | // PMR address decoder (partial decoder) 126 | // 127 | `ifdef OR1200_PM_PARTIAL_DECODING 128 | assign pmr_sel = (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) ? 1'b1 : 1'b0; 129 | `else 130 | assign pmr_sel = ((spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) && 131 | (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_PM_OFS_PMR)) ? 1'b1 : 1'b0; 132 | `endif 133 | 134 | // 135 | // Write to PMR and also PMR[DME]/PMR[SME] reset when 136 | // pic_wakeup is asserted 137 | // 138 | always @(posedge clk or `OR1200_RST_EVENT rst) 139 | if (rst == `OR1200_RST_VALUE) 140 | {dcge, sme, dme, sdf} <= 7'b0; 141 | else if (pmr_sel && spr_write) begin 142 | sdf <= spr_dat_i[`OR1200_PM_PMR_SDF]; 143 | dme <= spr_dat_i[`OR1200_PM_PMR_DME]; 144 | sme <= spr_dat_i[`OR1200_PM_PMR_SME]; 145 | dcge <= spr_dat_i[`OR1200_PM_PMR_DCGE]; 146 | end 147 | else if (pic_wakeup) begin 148 | dme <= 1'b0; 149 | sme <= 1'b0; 150 | end 151 | 152 | // 153 | // Read PMR 154 | // 155 | `ifdef OR1200_PM_READREGS 156 | assign spr_dat_o[`OR1200_PM_PMR_SDF] = sdf; 157 | assign spr_dat_o[`OR1200_PM_PMR_DME] = dme; 158 | assign spr_dat_o[`OR1200_PM_PMR_SME] = sme; 159 | assign spr_dat_o[`OR1200_PM_PMR_DCGE] = dcge; 160 | `ifdef OR1200_PM_UNUSED_ZERO 161 | assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0; 162 | `endif 163 | `endif 164 | 165 | // 166 | // Generate pm_clksd 167 | // 168 | assign pm_clksd = sdf; 169 | 170 | // 171 | // Statically generate all clock gate outputs 172 | // TODO: add dynamic clock gating feature 173 | // 174 | assign pm_cpu_gate = (dme | sme) & ~pic_wakeup; 175 | assign pm_dc_gate = pm_cpu_gate; 176 | assign pm_ic_gate = pm_cpu_gate; 177 | assign pm_dmmu_gate = pm_cpu_gate; 178 | assign pm_immu_gate = pm_cpu_gate; 179 | assign pm_tt_gate = sme & ~pic_wakeup; 180 | 181 | // 182 | // Assert pm_wakeup when pic_wakeup is asserted 183 | // 184 | assign pm_wakeup = pic_wakeup; 185 | 186 | // 187 | // Assert pm_lvolt when pm_cpu_gate or pm_cpustall are asserted 188 | // 189 | assign pm_lvolt = pm_cpu_gate | pm_cpustall; 190 | 191 | `else 192 | 193 | // 194 | // When PM is not implemented, drive all outputs as would when PM is disabled 195 | // 196 | assign pm_clksd = 4'b0; 197 | assign pm_cpu_gate = 1'b0; 198 | assign pm_dc_gate = 1'b0; 199 | assign pm_ic_gate = 1'b0; 200 | assign pm_dmmu_gate = 1'b0; 201 | assign pm_immu_gate = 1'b0; 202 | assign pm_tt_gate = 1'b0; 203 | assign pm_wakeup = 1'b1; 204 | assign pm_lvolt = 1'b0; 205 | 206 | // 207 | // Read PMR 208 | // 209 | `ifdef OR1200_PM_READREGS 210 | assign spr_dat_o[`OR1200_PM_PMR_SDF] = 4'b0; 211 | assign spr_dat_o[`OR1200_PM_PMR_DME] = 1'b0; 212 | assign spr_dat_o[`OR1200_PM_PMR_SME] = 1'b0; 213 | assign spr_dat_o[`OR1200_PM_PMR_DCGE] = 1'b0; 214 | `ifdef OR1200_PM_UNUSED_ZERO 215 | assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0; 216 | `endif 217 | `endif 218 | 219 | `endif 220 | 221 | endmodule 222 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_reg2mem.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's reg2mem aligner //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://www.opencores.org/cores/or1k/ //// 7 | //// //// 8 | //// Description //// 9 | //// Aligns register data to memory alignment. //// 10 | //// //// 11 | //// To Do: //// 12 | //// - make it smaller and faster //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // CVS Revision History 45 | // 46 | // $Log: or1200_reg2mem.v,v $ 47 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 48 | // No update 49 | // 50 | // Revision 1.2 2002/03/29 15:16:56 lampret 51 | // Some of the warnings fixed. 52 | // 53 | // Revision 1.1 2002/01/03 08:16:15 lampret 54 | // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. 55 | // 56 | // Revision 1.9 2001/10/21 17:57:16 lampret 57 | // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. 58 | // 59 | // Revision 1.8 2001/10/19 23:28:46 lampret 60 | // Fixed some synthesis warnings. Configured with caches and MMUs. 61 | // 62 | // Revision 1.7 2001/10/14 13:12:10 lampret 63 | // MP3 version. 64 | // 65 | // Revision 1.1.1.1 2001/10/06 10:18:36 igorm 66 | // no message 67 | // 68 | // Revision 1.2 2001/08/09 13:39:33 lampret 69 | // Major clean-up. 70 | // 71 | // Revision 1.1 2001/07/20 00:46:21 lampret 72 | // Development version of RTL. Libraries are missing. 73 | // 74 | // 75 | 76 | // synopsys translate_off 77 | `include "timescale.v" 78 | // synopsys translate_on 79 | `include "or1200_defines.v" 80 | 81 | module or1200_reg2mem(addr, lsu_op, regdata, memdata); 82 | 83 | parameter width = `OR1200_OPERAND_WIDTH; 84 | 85 | // 86 | // I/O 87 | // 88 | input [1:0] addr; 89 | input [`OR1200_LSUOP_WIDTH-1:0] lsu_op; 90 | input [width-1:0] regdata; 91 | output [width-1:0] memdata; 92 | 93 | // 94 | // Internal regs and wires 95 | // 96 | reg [7:0] memdata_hh; 97 | reg [7:0] memdata_hl; 98 | reg [7:0] memdata_lh; 99 | reg [7:0] memdata_ll; 100 | 101 | assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll}; 102 | 103 | // 104 | // Mux to memdata[31:24] 105 | // 106 | always @(lsu_op or addr or regdata) begin 107 | casez({lsu_op, addr[1:0]}) // synopsys parallel_case 108 | {`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0]; 109 | {`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8]; 110 | default : memdata_hh = regdata[31:24]; 111 | endcase 112 | end 113 | 114 | // 115 | // Mux to memdata[23:16] 116 | // 117 | always @(lsu_op or addr or regdata) begin 118 | casez({lsu_op, addr[1:0]}) // synopsys parallel_case 119 | {`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16]; 120 | default : memdata_hl = regdata[7:0]; 121 | endcase 122 | end 123 | 124 | // 125 | // Mux to memdata[15:8] 126 | // 127 | always @(lsu_op or addr or regdata) begin 128 | casez({lsu_op, addr[1:0]}) // synopsys parallel_case 129 | {`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0]; 130 | default : memdata_lh = regdata[15:8]; 131 | endcase 132 | end 133 | 134 | // 135 | // Mux to memdata[7:0] 136 | // 137 | always @(regdata) 138 | memdata_ll = regdata[7:0]; 139 | 140 | endmodule 141 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_sb.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's Store Buffer //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://opencores.org/project,or1k //// 7 | //// //// 8 | //// Description //// 9 | //// Implements store buffer. //// 10 | //// //// 11 | //// To Do: //// 12 | //// - byte combining //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2002 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // 45 | // $Log: or1200_sb.v,v $ 46 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 47 | // Minor update: 48 | // Bugs fixed. 49 | 50 | // synopsys translate_off 51 | `include "timescale.v" 52 | // synopsys translate_on 53 | `include "or1200_defines.v" 54 | 55 | module or1200_sb( 56 | // RISC clock, reset 57 | clk, rst, 58 | 59 | // Internal RISC bus (SB) 60 | sb_en, 61 | 62 | // Internal RISC bus (DC<->SB) 63 | dcsb_dat_i, dcsb_adr_i, dcsb_cyc_i, dcsb_stb_i, dcsb_we_i, dcsb_sel_i, dcsb_cab_i, 64 | dcsb_dat_o, dcsb_ack_o, dcsb_err_o, 65 | 66 | // BIU bus 67 | sbbiu_dat_o, sbbiu_adr_o, sbbiu_cyc_o, sbbiu_stb_o, sbbiu_we_o, sbbiu_sel_o, sbbiu_cab_o, 68 | sbbiu_dat_i, sbbiu_ack_i, sbbiu_err_i 69 | ); 70 | 71 | parameter dw = `OR1200_OPERAND_WIDTH; 72 | parameter aw = `OR1200_OPERAND_WIDTH; 73 | 74 | // 75 | // RISC clock, reset 76 | // 77 | input clk; // RISC clock 78 | input rst; // RISC reset 79 | 80 | // 81 | // Internal RISC bus (SB) 82 | // 83 | input sb_en; // SB enable 84 | 85 | // 86 | // Internal RISC bus (DC<->SB) 87 | // 88 | input [dw-1:0] dcsb_dat_i; // input data bus 89 | input [aw-1:0] dcsb_adr_i; // address bus 90 | input dcsb_cyc_i; // WB cycle 91 | input dcsb_stb_i; // WB strobe 92 | input dcsb_we_i; // WB write enable 93 | input dcsb_cab_i; // CAB input 94 | input [3:0] dcsb_sel_i; // byte selects 95 | output [dw-1:0] dcsb_dat_o; // output data bus 96 | output dcsb_ack_o; // ack output 97 | output dcsb_err_o; // err output 98 | 99 | // 100 | // BIU bus 101 | // 102 | output [dw-1:0] sbbiu_dat_o; // output data bus 103 | output [aw-1:0] sbbiu_adr_o; // address bus 104 | output sbbiu_cyc_o; // WB cycle 105 | output sbbiu_stb_o; // WB strobe 106 | output sbbiu_we_o; // WB write enable 107 | output sbbiu_cab_o; // CAB input 108 | output [3:0] sbbiu_sel_o; // byte selects 109 | input [dw-1:0] sbbiu_dat_i; // input data bus 110 | input sbbiu_ack_i; // ack output 111 | input sbbiu_err_i; // err output 112 | 113 | `ifdef OR1200_SB_IMPLEMENTED 114 | 115 | // 116 | // Internal wires and regs 117 | // 118 | wire [4+dw+aw-1:0] fifo_dat_i; // FIFO data in 119 | wire [4+dw+aw-1:0] fifo_dat_o; // FIFO data out 120 | wire fifo_wr; 121 | wire fifo_rd; 122 | wire fifo_full; 123 | wire fifo_empty; 124 | wire sel_sb; 125 | reg sb_en_reg; 126 | reg outstanding_store; 127 | reg fifo_wr_ack; 128 | 129 | // 130 | // FIFO data in/out 131 | // 132 | assign fifo_dat_i = {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i}; 133 | assign {sbbiu_sel_o, sbbiu_dat_o, sbbiu_adr_o} = sel_sb ? fifo_dat_o : {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i}; 134 | 135 | // 136 | // Control 137 | // 138 | assign fifo_wr = dcsb_cyc_i & dcsb_stb_i & dcsb_we_i & ~fifo_full & ~fifo_wr_ack; 139 | assign fifo_rd = ~outstanding_store; 140 | assign dcsb_dat_o = sbbiu_dat_i; 141 | assign dcsb_ack_o = sel_sb ? fifo_wr_ack : sbbiu_ack_i; 142 | assign dcsb_err_o = sel_sb ? 1'b0 : sbbiu_err_i; // SB never returns error 143 | assign sbbiu_cyc_o = sel_sb ? outstanding_store : dcsb_cyc_i; 144 | assign sbbiu_stb_o = sel_sb ? outstanding_store : dcsb_stb_i; 145 | assign sbbiu_we_o = sel_sb ? 1'b1 : dcsb_we_i; 146 | assign sbbiu_cab_o = sel_sb ? 1'b0 : dcsb_cab_i; 147 | assign sel_sb = sb_en_reg & (~fifo_empty | (fifo_empty & outstanding_store)); 148 | 149 | // 150 | // SB enable 151 | // 152 | always @(posedge clk or `OR1200_RST_EVENT rst) 153 | if (rst == `OR1200_RST_VALUE) 154 | sb_en_reg <= 1'b0; 155 | else if (sb_en & ~dcsb_cyc_i) 156 | sb_en_reg <= 1'b1; // enable SB when there is no dcsb transfer in progress 157 | else if (~sb_en & (~fifo_empty | (fifo_empty & outstanding_store))) 158 | sb_en_reg <= 1'b0; // disable SB when there is no pending transfers from SB 159 | 160 | // 161 | // Store buffer FIFO instantiation 162 | // 163 | or1200_sb_fifo or1200_sb_fifo ( 164 | .clk_i(clk), 165 | .rst_i(rst), 166 | .dat_i(fifo_dat_i), 167 | .wr_i(fifo_wr), 168 | .rd_i(fifo_rd), 169 | .dat_o(fifo_dat_o), 170 | .full_o(fifo_full), 171 | .empty_o(fifo_empty) 172 | ); 173 | 174 | // 175 | // fifo_rd 176 | // 177 | always @(posedge clk or `OR1200_RST_EVENT rst) 178 | if (rst == `OR1200_RST_VALUE) 179 | outstanding_store <= 1'b0; 180 | else if (sbbiu_ack_i) 181 | outstanding_store <= 1'b0; 182 | else if (sel_sb | fifo_wr) 183 | outstanding_store <= 1'b1; 184 | 185 | // 186 | // fifo_wr_ack 187 | // 188 | always @(posedge clk or `OR1200_RST_EVENT rst) 189 | if (rst == `OR1200_RST_VALUE) 190 | fifo_wr_ack <= 1'b0; 191 | else if (fifo_wr) 192 | fifo_wr_ack <= 1'b1; 193 | else 194 | fifo_wr_ack <= 1'b0; 195 | 196 | `else // !OR1200_SB_IMPLEMENTED 197 | 198 | assign sbbiu_dat_o = dcsb_dat_i; 199 | assign sbbiu_adr_o = dcsb_adr_i; 200 | assign sbbiu_cyc_o = dcsb_cyc_i; 201 | assign sbbiu_stb_o = dcsb_stb_i; 202 | assign sbbiu_we_o = dcsb_we_i; 203 | assign sbbiu_cab_o = dcsb_cab_i; 204 | assign sbbiu_sel_o = dcsb_sel_i; 205 | assign dcsb_dat_o = sbbiu_dat_i; 206 | assign dcsb_ack_o = sbbiu_ack_i; 207 | assign dcsb_err_o = sbbiu_err_i; 208 | 209 | `endif 210 | 211 | endmodule 212 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_sb_fifo.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// OR1200's Store Buffer FIFO //// 4 | //// //// 5 | //// This file is part of the OpenRISC 1200 project //// 6 | //// http://www.opencores.org/cores/or1k/ //// 7 | //// //// 8 | //// Description //// 9 | //// Implementation of store buffer FIFO. //// 10 | //// //// 11 | //// To Do: //// 12 | //// - N/A //// 13 | //// //// 14 | //// Author(s): //// 15 | //// - Damjan Lampret, lampret@opencores.org //// 16 | //// //// 17 | ////////////////////////////////////////////////////////////////////// 18 | //// //// 19 | //// Copyright (C) 2002 Authors and OPENCORES.ORG //// 20 | //// //// 21 | //// This source file may be used and distributed without //// 22 | //// restriction provided that this copyright statement is not //// 23 | //// removed from the file and that any derivative work contains //// 24 | //// the original copyright notice and the associated disclaimer. //// 25 | //// //// 26 | //// This source file is free software; you can redistribute it //// 27 | //// and/or modify it under the terms of the GNU Lesser General //// 28 | //// Public License as published by the Free Software Foundation; //// 29 | //// either version 2.1 of the License, or (at your option) any //// 30 | //// later version. //// 31 | //// //// 32 | //// This source is distributed in the hope that it will be //// 33 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 34 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 35 | //// PURPOSE. See the GNU Lesser General Public License for more //// 36 | //// details. //// 37 | //// //// 38 | //// You should have received a copy of the GNU Lesser General //// 39 | //// Public License along with this source; if not, download it //// 40 | //// from http://www.opencores.org/lgpl.shtml //// 41 | //// //// 42 | ////////////////////////////////////////////////////////////////////// 43 | // 44 | // CVS Revision History 45 | // 46 | // $Log: or1200_sb_fifo.v,v $ 47 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 48 | // No update 49 | // 50 | // Revision 1.3 2002/11/06 13:53:41 simons 51 | // SB mem width fixed. 52 | // 53 | // Revision 1.2 2002/08/22 02:18:55 lampret 54 | // Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. 55 | // 56 | // Revision 1.1 2002/08/18 19:53:08 lampret 57 | // Added store buffer. 58 | // 59 | // 60 | 61 | // synopsys translate_off 62 | `include "timescale.v" 63 | // synopsys translate_on 64 | `include "or1200_defines.v" 65 | 66 | module or1200_sb_fifo( 67 | clk_i, rst_i, dat_i, wr_i, rd_i, dat_o, full_o, empty_o 68 | ); 69 | 70 | parameter dw = 68; 71 | parameter fw = `OR1200_SB_LOG; 72 | parameter fl = `OR1200_SB_ENTRIES; 73 | 74 | // 75 | // FIFO signals 76 | // 77 | input clk_i; // Clock 78 | input rst_i; // Reset 79 | input [dw-1:0] dat_i; // Input data bus 80 | input wr_i; // Write request 81 | input rd_i; // Read request 82 | output [dw-1:0] dat_o; // Output data bus 83 | output full_o; // FIFO full 84 | output empty_o;// FIFO empty 85 | 86 | // 87 | // Internal regs 88 | // 89 | reg [dw-1:0] mem [fl-1:0]; 90 | reg [dw-1:0] dat_o; 91 | reg [fw+1:0] cntr; 92 | reg [fw-1:0] wr_pntr; 93 | reg [fw-1:0] rd_pntr; 94 | reg empty_o; 95 | reg full_o; 96 | 97 | always @(posedge clk_i or `OR1200_RST_EVENT rst_i) 98 | if (rst_i == `OR1200_RST_VALUE) begin 99 | full_o <= 1'b0; 100 | empty_o <= 1'b1; 101 | wr_pntr <= {fw{1'b0}}; 102 | rd_pntr <= {fw{1'b0}}; 103 | cntr <= {fw+2{1'b0}}; 104 | dat_o <= {dw{1'b0}}; 105 | end 106 | else if (wr_i && rd_i) begin // FIFO Read and Write 107 | mem[wr_pntr] <= dat_i; 108 | if (wr_pntr >= fl-1) 109 | wr_pntr <= {fw{1'b0}}; 110 | else 111 | wr_pntr <= wr_pntr + 1'b1; 112 | if (empty_o) begin 113 | dat_o <= dat_i; 114 | end 115 | else begin 116 | dat_o <= mem[rd_pntr]; 117 | end 118 | if (rd_pntr >= fl-1) 119 | rd_pntr <= {fw{1'b0}}; 120 | else 121 | rd_pntr <= rd_pntr + 1'b1; 122 | end 123 | else if (wr_i && !full_o) begin // FIFO Write 124 | mem[wr_pntr] <= dat_i; 125 | cntr <= cntr + 1'b1; 126 | empty_o <= 1'b0; 127 | if (cntr >= (fl-1)) begin 128 | full_o <= 1'b1; 129 | cntr <= fl; 130 | end 131 | if (wr_pntr >= fl-1) 132 | wr_pntr <= {fw{1'b0}}; 133 | else 134 | wr_pntr <= wr_pntr + 1'b1; 135 | end 136 | else if (rd_i && !empty_o) begin // FIFO Read 137 | dat_o <= mem[rd_pntr]; 138 | cntr <= cntr - 1'b1; 139 | full_o <= 1'b0; 140 | if (cntr <= 1) begin 141 | empty_o <= 1'b1; 142 | cntr <= {fw+2{1'b0}}; 143 | end 144 | if (rd_pntr >= fl-1) 145 | rd_pntr <= {fw{1'b0}}; 146 | else 147 | rd_pntr <= rd_pntr + 1'b1; 148 | end 149 | 150 | endmodule 151 | -------------------------------------------------------------------------------- /rtl/verilog/or1200_spram.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Generic Single-Port Synchronous RAM //// 4 | //// //// 5 | //// This file is part of memory library available from //// 6 | //// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// 7 | //// //// 8 | //// Description //// 9 | //// This block is a wrapper with common single-port //// 10 | //// synchronous memory interface for different //// 11 | //// types of ASIC and FPGA RAMs. Beside universal memory //// 12 | //// interface it also provides behavioral model of generic //// 13 | //// single-port synchronous RAM. //// 14 | //// It should be used in all OPENCORES designs that want to be //// 15 | //// portable accross different target technologies and //// 16 | //// independent of target memory. //// 17 | //// //// 18 | //// Author(s): //// 19 | //// - Michael Unneback, unneback@opencores.org //// 20 | //// //// 21 | ////////////////////////////////////////////////////////////////////// 22 | //// //// 23 | //// Copyright (C) 2000 Authors and OPENCORES.ORG //// 24 | //// //// 25 | //// This source file may be used and distributed without //// 26 | //// restriction provided that this copyright statement is not //// 27 | //// removed from the file and that any derivative work contains //// 28 | //// the original copyright notice and the associated disclaimer. //// 29 | //// //// 30 | //// This source file is free software; you can redistribute it //// 31 | //// and/or modify it under the terms of the GNU Lesser General //// 32 | //// Public License as published by the Free Software Foundation; //// 33 | //// either version 2.1 of the License, or (at your option) any //// 34 | //// later version. //// 35 | //// //// 36 | //// This source is distributed in the hope that it will be //// 37 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 38 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 39 | //// PURPOSE. See the GNU Lesser General Public License for more //// 40 | //// details. //// 41 | //// //// 42 | //// You should have received a copy of the GNU Lesser General //// 43 | //// Public License along with this source; if not, download it //// 44 | //// from http://www.opencores.org/lgpl.shtml //// 45 | //// //// 46 | ////////////////////////////////////////////////////////////////////// 47 | // 48 | // CVS Revision History 49 | // 50 | // $Log: or1200_dpram_32x32.v,v $ 51 | // Revision 2.0 2010/06/30 11:00:00 ORSoC 52 | // New 53 | // 54 | 55 | // synopsys translate_off 56 | `include "timescale.v" 57 | // synopsys translate_on 58 | `include "or1200_defines.v" 59 | 60 | module or1200_spram 61 | ( 62 | `ifdef OR1200_BIST 63 | // RAM BIST 64 | mbist_si_i, mbist_so_o, mbist_ctrl_i, 65 | `endif 66 | // Generic synchronous single-port RAM interface 67 | clk, ce, we, addr, di, doq 68 | ); 69 | 70 | // 71 | // Default address and data buses width 72 | // 73 | parameter aw = 10; 74 | parameter dw = 32; 75 | 76 | `ifdef OR1200_BIST 77 | // 78 | // RAM BIST 79 | // 80 | input mbist_si_i; 81 | input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; 82 | output mbist_so_o; 83 | `endif 84 | 85 | // 86 | // Generic synchronous single-port RAM interface 87 | // 88 | input clk; // Clock 89 | input ce; // Chip enable input 90 | input we; // Write enable input 91 | //input oe; // Output enable input 92 | input [aw-1:0] addr; // address bus inputs 93 | input [dw-1:0] di; // input data bus 94 | output [dw-1:0] doq; // output data bus 95 | 96 | // 97 | // Internal wires and registers 98 | // 99 | 100 | // 101 | // Generic single-port synchronous RAM model 102 | // 103 | 104 | // 105 | // Generic RAM's registers and wires 106 | // 107 | `ifdef OR1200_GENERIC 108 | reg [dw-1:0] mem [(1< ../log/top.log 4 | mv command.log ../log 5 | -------------------------------------------------------------------------------- /syn/synopsys/bin/top.scr: -------------------------------------------------------------------------------- 1 | /* 2 | * Examples of Synopsys Design Compiler 3 | * synthesis script for OR1200 IP core 4 | * 5 | */ 6 | 7 | TOPLEVEL = or1200_top 8 | TECH = vs_umc18 /* vs_umc18, art_umc18 */ 9 | CLK = clk_i 10 | RST = rst_i 11 | CLK_PERIOD = 5 /* 200 MHz */ 12 | MAX_AREA = 0 /* Push hard */ 13 | DO_UNGROUP = no /* yes, no */ 14 | DO_VERIFY = no /* yes, no */ 15 | CLK_UNCERTAINTY = 0.1 /* 100 ps */ 16 | DFF_CKQ = 0.2 /* Clk to Q in technology time units */ 17 | DFF_SETUP = 0.1 /* Setup time in technology time units */ 18 | 19 | /* Starting timestamp */ 20 | sh date 21 | 22 | /* 23 | * Set some basic variables related to environment 24 | * 25 | */ 26 | 27 | /* Enable Verilog HDL preprocessor */ 28 | hdlin_enable_vpp = true 29 | 30 | /* Set log path */ 31 | LOG_PATH = "../log/" 32 | 33 | /* Set gate-level netlist path */ 34 | GATE_PATH = "../out/" 35 | 36 | /* Set RAMS_PATH */ 37 | RAMS_PATH = "../../../lib/" 38 | 39 | /* Set RTL source path */ 40 | RTL_PATH = { "../../../rtl/verilog/" } 41 | 42 | /* Optimize adders */ 43 | synlib_model_map_effort = high 44 | hlo_share_effort = low 45 | 46 | STAGE = final 47 | 48 | /* 49 | * Load libraries 50 | * 51 | */ 52 | 53 | /* Search paths */ 54 | search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \ 55 | { /libs/Artisan/aci/sc-x/symbols/synopsys/ } + \ 56 | { /libs/art_rams/ } + \ 57 | { /libs/vs_rams/ /usr/dc/libraries/syn/ } + \ 58 | { /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ } 59 | 60 | /* Synthetic libraries */ 61 | snps = get_unix_variable("SYNOPSYS") 62 | synthetic_library = { \ 63 | snps + "/libraries/syn/dw01.sldb" \ 64 | snps + "/libraries/syn/dw02.sldb" \ 65 | snps + "/libraries/syn/dw03.sldb" \ 66 | snps + "/libraries/syn/dw04.sldb" \ 67 | snps + "/libraries/syn/dw05.sldb" \ 68 | snps + "/libraries/syn/dw06.sldb" \ 69 | snps + "/libraries/syn/dw07.sldb" } 70 | 71 | /* Set Artisan Sage-X UMC 0.18u standard cell library */ 72 | if (TECH == "art_umc18") { 73 | target_library = { slow.db \ 74 | vs_hdsp_2048x32_wc_1.08V_125C.db \ 75 | vs_hdsp_2048x8_tc_1.2V_25C.db \ 76 | vs_hdsp_512x20_wc_1.08V_125C.db \ 77 | vs_hdsp_64x14_wc_1.08V_125C.db \ 78 | vs_hdsp_64x22_wc_1.08V_125C.db \ 79 | vs_hdsp_64x24_wc_1.08V_125C.db \ 80 | vs_hdtp_64x32_wc_1.08V_125C.db \ 81 | } 82 | symbol_library = { umc18.sdb } 83 | } 84 | 85 | /* Set Virtual Silicon UMC 0.18u standard cell library */ 86 | if (TECH == "vs_umc18") { 87 | target_library = { umcl18u250t2_wc.db \ 88 | vs_hdsp_2048x32_wc_1.08V_125C.db \ 89 | vs_hdsp_2048x8_wc_1.08V_125C.db \ 90 | vs_hdsp_512x20_wc_1.08V_125C.db \ 91 | vs_hdsp_64x14_wc_1.08V_125C.db \ 92 | vs_hdsp_64x22_wc_1.08V_125C.db \ 93 | vs_hdsp_64x24_wc_1.08V_125C.db \ 94 | vs_hdtp_64x32_wc_1.08V_125C.db \ 95 | } 96 | symbol_library = { umcl18u250t2.sdb } 97 | } 98 | 99 | link_library = target_library + synthetic_library 100 | 101 | 102 | /* 103 | * Load HDL source files 104 | * 105 | */ 106 | include ../bin/read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log 107 | 108 | /* Set design top */ 109 | current_design TOPLEVEL 110 | 111 | /* Link all blocks and uniquify them */ 112 | link 113 | uniquify 114 | check_design > LOG_PATH + check_design_ + TOPLEVEL + .log 115 | 116 | /* 117 | * Apply constraints 118 | * 119 | */ 120 | if (TECH == "vs_umc18") { 121 | DFF_CELL = DFFPQ2 122 | LIB_DFF_D = umcl18u250t2_wc/DFFPQ2/D 123 | OPER_COND = WORST 124 | } else if (TECH == "art_umc18") { 125 | DFF_CELL = DFFHQX2 126 | LIB_DFF_D = slow/DFFHQX2/D 127 | OPER_COND = slow 128 | } else { 129 | echo "Error: Unsupported technology" 130 | exit 131 | } 132 | 133 | 134 | /* Clocks constraints */ 135 | create_clock dwb_clk_i -period CLK_PERIOD 136 | create_clock iwb_clk_i -period CLK_PERIOD 137 | create_clock CLK -period CLK_PERIOD 138 | set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY 139 | set_dont_touch_network all_clocks() 140 | 141 | /* Reset constraints */ 142 | set_driving_cell -none RST 143 | set_drive 0 RST 144 | set_dont_touch_network RST 145 | 146 | /* All inputs except reset and clock */ 147 | all_inputs_wo_rst_clk = all_inputs() - CLK - RST 148 | 149 | /* Set output delays and load for output signals 150 | * 151 | * All outputs are assumed to go directly into 152 | * external flip-flops for the purpose of this 153 | * synthesis 154 | */ 155 | set_output_delay DFF_SETUP -clock CLK all_outputs() 156 | set_load load_of(LIB_DFF_D) * 4 all_outputs() 157 | 158 | /* Input delay and driving cell of all inputs 159 | * 160 | * All these signals are assumed to come directly from 161 | * flip-flops for the purpose of this synthesis 162 | * 163 | */ 164 | set_input_delay DFF_CKQ -clock CLK all_inputs_wo_rst_clk 165 | set_driving_cell -cell DFF_CELL -pin Q all_inputs_wo_rst_clk 166 | 167 | /* Set design fanout */ 168 | /* 169 | set_max_fanout 10 TOPLEVEL 170 | */ 171 | 172 | /* Optimize all near-critical paths to give extra slack for layout */ 173 | c_range = CLK_PERIOD * 0.10 174 | group_path -critical_range c_range -name CLK -to CLK 175 | 176 | /* Operating conditions */ 177 | set_operating_conditions OPER_COND 178 | 179 | /* Lets do basic synthesis */ 180 | if (DO_UNGROUP == "yes") { 181 | ungroup -all 182 | } 183 | 184 | set_ultra_optimization -f 185 | compile_new_optimization = true 186 | /* 187 | set_structure -boolean false -timing true 188 | set_flatten -effort medium -minimize single_output 189 | */ 190 | 191 | /* 192 | set_flatten false 193 | */ 194 | 195 | /* 196 | compile -boundary_optimization -map_effort medium -ungroup_all 197 | */ 198 | compile -boundary_optimization -map_effort high -auto_ungroup 199 | 200 | 201 | /* 202 | compile -map_effort low 203 | */ 204 | 205 | /* Save current design using synopsys format */ 206 | write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db 207 | 208 | /* Save current design using verilog format */ 209 | write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v 210 | 211 | /* Basic reports */ 212 | report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log 213 | report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log 214 | report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log 215 | report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log 216 | report_references > LOG_PATH + STAGE + _ + TOPLEVEL + _references.log 217 | report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log 218 | report_ultra_optimizations > LOG_PATH + STAGE + _ + TOPLEVEL + _ultra_optimizations.log 219 | /* 220 | report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log 221 | */ 222 | 223 | 224 | /* Verify design */ 225 | if (DO_VERIFY == "yes") { 226 | compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log 227 | } 228 | 229 | /* Finish */ 230 | sh date 231 | exit 232 | -------------------------------------------------------------------------------- /syn/synopsys/log/README: -------------------------------------------------------------------------------- 1 | This directory contains report files after synthesis run. 2 | -------------------------------------------------------------------------------- /syn/synopsys/out/README: -------------------------------------------------------------------------------- 1 | This directory contains verilog and db netlists after synthesis run. 2 | -------------------------------------------------------------------------------- /syn/synopsys/run/README: -------------------------------------------------------------------------------- 1 | This directory is working directory. Before synthesis verify that or1200_defines.v 2 | has correct defines enabled for ASIC target and that synthesis scripts in ../bin/ are 3 | up to date. To run synthesis, do the following: 4 | 5 | $ ../bin/run_syn & 6 | 7 | --------------------------------------------------------------------------------