├── .gitignore ├── .gitmodules ├── README.md ├── docs └── openvizsla_prd.txt ├── hardware ├── FPGA power v3.SchDoc ├── LICENSE ├── OpenVizsla footprints.PcbLib ├── OpenVizsla symbols.SchLib ├── Project Outputs for ov_ftdi │ ├── AutoCAD PCB │ │ └── ov_ftdi.DXF │ ├── BOM │ │ └── Bill of Materials-ov_ftdi.csv │ ├── Exporter Wrapper │ │ ├── ov_ftdi.PCB │ │ ├── ov_ftdi.Rep │ │ ├── power.log │ │ └── power.sch │ ├── Gerber │ │ ├── ov_ftdi.GBL │ │ ├── ov_ftdi.GBO │ │ ├── ov_ftdi.GBS │ │ ├── ov_ftdi.GKO │ │ ├── ov_ftdi.GM10 │ │ ├── ov_ftdi.GP1 │ │ ├── ov_ftdi.GP2 │ │ ├── ov_ftdi.GTL │ │ ├── ov_ftdi.GTO │ │ ├── ov_ftdi.GTP │ │ └── ov_ftdi.GTS │ ├── NC Drill │ │ └── ov_ftdi.TXT │ ├── Pick Place │ │ └── Pick Place for ov_ftdi.txt │ └── ov_ftdi.PDF ├── RAM and target USB.SchDoc ├── fpga.SchDoc ├── ibom │ └── ibom.html ├── migen.ttf ├── ov_ftdi.OutJob ├── ov_ftdi.PcbDoc ├── ov_ftdi.PrjPcb ├── ov_ftdi1 │ ├── SI_Models.silib │ ├── ov_ftdi.LibPkg │ ├── ov_ftdi.PcbLib │ └── ov_ftdi.SCHLIB ├── power.SchDoc └── usb.SchDoc └── software ├── fpga └── ov3 │ ├── .gitignore │ ├── 3rdparty │ └── .keep │ ├── LICENSE │ ├── Makefile │ ├── README.md │ ├── build.py │ ├── build │ └── .keep │ ├── ovhw │ ├── __init__.py │ ├── bus_interleave.py │ ├── buttons.py │ ├── cfilt.py │ ├── clocking.py │ ├── cmdproc.py │ ├── constants.py │ ├── csr_master.py │ ├── dummy_source.py │ ├── ftdi_bus.py │ ├── ftdi_lfsr_test.py │ ├── leds.py │ ├── ov_types.py │ ├── ovf_insert.py │ ├── perfcounter.py │ ├── sdram_bist.py │ ├── sdram_host_read.py │ ├── sdram_mux.py │ ├── sdram_sink.py │ ├── sdrambistcfg.py │ ├── sdramctl.py │ ├── top.py │ ├── ulpi.py │ ├── ulpicfg.py │ └── whacker │ │ ├── __init__.py │ │ ├── consumer.py │ │ ├── producer.py │ │ ├── util.py │ │ └── whacker.py │ ├── ovplatform │ ├── __init__.py │ ├── ov3.py │ └── sdram_params.py │ └── sim │ ├── __init__.py │ ├── sdram_test_util.py │ ├── test_cmdproc.py │ ├── test_consumer.py │ ├── test_leds.py │ ├── test_producer.py │ ├── test_sdram_bist.py │ ├── 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