├── .github └── workflows │ ├── build-SoC.yml │ └── build-verilog-examples.yml ├── .gitignore ├── .gitmodules ├── 50-orangecrab.rules ├── LICENCE.md ├── README.md ├── amaranth ├── .gitignore ├── README.md └── blink.py ├── litex ├── README-CircuitPython-Example.md ├── SoC-CircuitPython.py ├── combine.py ├── lxbuildenv.py └── modules │ ├── analog.py │ ├── csr_cdc.py │ ├── io_block.py │ └── rgb.py ├── riscv ├── blink │ ├── Makefile │ ├── README.md │ ├── generated │ │ ├── csr.h │ │ └── soc.h │ ├── hw │ │ └── common.h │ ├── main.c │ ├── sections.ld │ └── start.s └── button │ ├── Makefile │ ├── README.md │ ├── generated │ ├── csr.h │ └── soc.h │ ├── hw │ └── common.h │ ├── main.c │ ├── sections.ld │ └── start.s └── verilog ├── blink ├── Makefile ├── blink.v └── readme.md ├── blink_reset ├── Makefile ├── blink_reset.v └── readme.md ├── blink_reset_module ├── Makefile ├── blink_reset_module.v └── readme.md ├── orangecrab_r0.1.pcf ├── orangecrab_r0.2.1.pcf ├── orangecrab_r0.2.pcf ├── pll ├── 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