├── Course.md ├── README.md └── starting_code.tlv /Course.md: -------------------------------------------------------------------------------- 1 | # Getting Started with FPGAs Course 2 | 3 | # _This course is work-in-progress. (Sorry for the premature Linkedin post.) Come back soon!_ 4 | 5 | ## Virtual Lab Setup 6 | 7 | ### System requirements 8 | 9 | The virtual portions of this course can be run from any modern web browser. 10 | 11 | The physical FPGA flow requires: 12 | - Python3 13 | - Git 14 | - the standard software installation for your FPGA board 15 | 16 | ### Repository 17 | 18 | - First, clone the Virtual FPGA Lab repository: `git clone git@github.com:BalaDhinesh/Virtual-FPGA-Lab.git`. 19 | - And `cd Virtual-FPGA-Lab`. 20 | - Then perform the necessary installs: 21 | ```sh 22 | pip3 install sandpiper-saas makerchip-app 23 | ``` 24 | These are very light-weight installs that simply interface to web and cloud applications. 25 | 26 | ### Makerchip Starting Code Template 27 | 28 | - Open this [starting code template](http://www.makerchip.com/sandbox?code_url=https:%2F%2Fraw.githubusercontent.com%2Fos-fpga%2FGettingStartedWithFPGAs%2Fmaster%2Fstarting_code.tlv) in Makerchip. 29 | - Watch this short introduction to Makerchip. TODO: Video. 30 | The template contains a list of supported boards. 31 | - If you have one of these boards, you may choose it, or choose any board you like for the virtual lab. 32 | 33 | The template code is configured to enable LED output. 34 | We'll review the structure of this code soon enough. For now, let's code some logic. 35 | 36 | ### Simple Counter 37 | 38 | Let's drive the LED lights on the FPGA board with the bits of a free-running counter. Each LED will be one bit. 39 | You'll need to provide the logic for the free-running counter, connected to the LEDs. 40 | 41 | - Where the template code says: `Drive $Leds[15:0] here.`, paste this statement, which implements a free-running counter: `$Leds[15:0] <= $reset ? 16'b0 : $Leds + 1;` 42 | - Under the "E" menu in the EDITOR, select "Compile/Sim" (or press `-Enter`). 43 | - In the VIZ tab, step simulation (with the `>` arrow) to observe the LEDs showing incrementing binary values. 44 | 45 | Basys3_LED

46 | 47 | ### Running on the Physical FPGAs 48 | 49 | If you have a compatible FPGA board, let's try it. 50 | 51 | - Follow [the steps provided in the Virtual FPGA Lab repository](https://github.com/BalaDhinesh/Virtual-FPGA-Lab/tree/main/fpga#steps-to-run-fpga-setup). 52 | 53 | Supporting all FPGA boards is something that requires help from the community. If you found any issues, please submit a pull request. 54 | 55 | ### Seven-Segment Displays 56 | 57 | Most boards come with a seven-segment display, or have peripherals for them. Let's display our counter on the seven-segment display. 58 | 59 | First we'll do this the easy way. 60 | 61 | - Instantiate this macro TODO: TBD. 62 | - Compile/Sim and see that the count appears in VIZ on the 7-segment display. 63 | - If you have a physical FPGA board try that as well. 64 | 65 | ### How's This All Work? 66 | 67 | - Watch this video describing the various components of the source code. TODO: TBD. 68 | - Watch this video describing the various components of the physical FPGA flow. TODO: TBD. 69 | 70 | ### 7-Segment Display Interface 71 | 72 | Above, we used the XXX macro to drive the pins of the FPGA properly to display our output value (`$count`). Let's use this controller logic to get a feel for TL-Verilog. 73 | 74 | The 7-segment display is controlled by three output signals: 75 | 76 | ``` 77 | logic [3:0] digit; // Active low enables for digits of the display. 78 | logic [6:0] sseg; // The segments to illuminate of the enabled digits. 79 | logic dp; 80 | ``` 81 | 82 | The `digit` vector has a bit for each digit in the display. For each deasserted (0) bit, the corresponding digit is enable. 83 | 84 | The 7 `sseg` output bits, when deasserted (0), illuminate the corresponding segment of each enabled digit. The seven segments are shown below, labeled with their conrolling bit index. 85 | 86 | ``` 87 | ___ 88 | | 6 | 89 | 1|___|5 90 | | 0 | 91 | 2|___|4 92 | 3 93 | ``` 94 | 95 | Note that it is not possible to simultaneously display different digit values on different digits. But, we saw multi-digit count values on the 7-segment display, both virtually and physically. How is this possible? Well, on the virtual board, put simply, we were cheating. On the physical board, only one digit is displayed in each clock cycle. With a 100 MHz clock, our eyes do not detect the flickering, and the display appears to be showing all digits simultaneously. 96 | 97 | You can see this behavior cycle-by-cycle in simulation by changing the XXX argument to the XXX macro. 98 | 99 | ### Disecting the 7-Segment Controller 100 | 101 | Let's use the 7-segment conroller to get a feel for some basics of TL-Verilog. 102 | 103 | ... 104 | 105 | ### Writing Your Own Code 106 | 107 | - Use what you learned from the 7-segment controller to generate the behavior seen below. 108 | 109 | (TODO: Screen capture of dash moving right-to-left along the top segments, then left-to-right along the bottom) 110 | 111 | - Try running this on your physical FPGA board as well. 112 | 113 | ### Wrapping Up 114 | 115 | That's it. You did it! You wrote your own FPGA logic. So what's next? Here are some ideas: 116 | 117 | - Learn more about [TL-Verilog](https://redwoodeda.com/tl-verilog) and [Makerchip](https://makerchip.com). 118 | - Find other course offerings from the [OSFPGA](https://osfpga.org), [Redwood EDA](https://www.redwoodeda.com/publications), and [VSD](https://www.vlsisystemdesign.com/). 119 | 120 | It you found issues, take matters into your own hands by submitting a pull request. 121 | 122 | And, share your experience on social media in a post with the link to this repository. 123 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Getting Started with FPGAs 2 | 3 | **Brought to you by the [Open Source FPGA Foundation](https://www.chipsalliance.org/)** 4 | 5 |

6 | 7 |

8 | 9 | Led by [Steve Hoover](https://www.linkedin.com/in/steve-hoover-a44b607/), founder of [

](https://redwoodeda.com) and member of the [OSFPGA](https://www.chipsalliance.org/) Education and Training Committee. 10 | 11 | This free short-course takes you from your browser to your board in under an hour, using the [Makerchip](https://makerchip.com) IDE. 12 | 13 |

14 | EDGE_Artix7_LED => 15 | led_artix 16 |

17 | 18 | You'll develop a simple counter circuit and a 7-segment display controller in Verilog or Transaction-Level Verilog. Then, if you have any of several supported FPGA boards, you’ll be able to run your design on your own FPGA. From there, the sky’s the limit. 19 | 20 | Visit [OSFPGA.org](https://www.chipsalliance.org/) for further learning opportunities. 21 | 22 | Supported Boards: 23 | 24 | 1. Zedboard Zynq-7000 ARM/FPGA SoC Development Board ([Product Link](https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/)) 25 | 2. EDGE Artix 7 FPGA Development Board ([Product Link](https://allaboutfpga.com/product/edge-artix-7-fpga-development-board/)) 26 | 3. Basys 3 Artix-7 FPGA Trainer Board ([Product Link](https://store.digilentinc.com/basys-3-artix-7-fpga-beginner-board-recommended-for-introductory-users/)) 27 | 4. Icebreaker FPGA ([Product Link](https://1bitsquared.com/products/icebreaker)) 28 | 5. Nexys A7 ([Product Link](https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/)) 29 | 30 | [Start the course now!](./Course.md) ...well, not quite now... still a work-in-progress. 31 | 32 | ## Demos: 33 | ### 1. LED: 34 | __Counter Demo:__ https://makerchip.com/sandbox/0mZf5hLPG/0y8h64Z# 35 | 36 | __Output on Virtual Basys3 board:__ 37 | 38 | Basys3_LED

39 | 40 | __Output on Virtual Edge Artix7 board:__ 41 | 42 | EDGE_Artix7_LED

43 | 44 | ### 2. Seven Segment Display: 45 | __Counter Demo:__ https://makerchip.com/sandbox/0mZf5hLPG/0zmh8rV 46 | 47 | __Output on Virtual Basys3 board:__ 48 | 49 | 50 | Basys3_7seg

51 | 52 | 53 | __Output on Virtual Edge Artix7 board:__ 54 | 55 | EDGE_Artix7_7seg

56 | 57 | 58 | 59 | ## Run on FPGA: 60 | ### 1. LED: 61 | __Output on Basys3 board:__ 62 | 63 | Basys3_LED

64 | 65 | __Output on Edge Artix7 board:__ 66 | 67 | EDGE_Artix7_LED

68 | 69 | ### 2. Seven Segment Display: 70 | __Output on Basys3 board:__ 71 | 72 | Basys3_7seg

73 | 74 | __Output on Edge Artix7 board:__ 75 | 76 | EDGE_Artix7_7seg

77 | 78 | 79 | ## Credits 80 | 81 | Course creators: 82 | - Steve Hoover, founder Redwood EDA, LLC 83 | - Mayank Kabra, student at the International Institute of Information Technology, Bangalore 84 | - Shivani Shah, student at the International Institute of Information Technology, Bangalore 85 | 86 | Thanks also to [Bala Dhinesh](https://www.linkedin.com/in/bala-dhinesh/) for providing the [vitual lab environment](https://github.com/BalaDhinesh/Virtual-FPGA-Lab), with support from: 87 | 88 |

89 | 90 | 91 | 92 | 93 |

94 | -------------------------------------------------------------------------------- /starting_code.tlv: -------------------------------------------------------------------------------- 1 | \m4_TLV_version 1d -p verilog --bestsv --noline: tl-x.org 2 | \SV 3 | // Include the virtual lab library. 4 | m4_include_lib(['https://raw.githubusercontent.com/BalaDhinesh/Virtual-FPGA-Lab/main/tlv_lib/fpga_includes.tlv']) 5 | 6 | // The top-level module definition, either as required by Makerchip, or by the FPGA with led outputs. 7 | m4_ifelse_block(M4_MAKERCHIP, 1,[' 8 | m4_makerchip_module 9 | '],[' 10 | module top(input clk, input reset, output [15:0] led); 11 | ']) 12 | 13 | // A signal providing LED outputs. 14 | logic [15:0] led; 15 | logic [7:0] digit; 16 | logic [6:0] sseg; 17 | logic dp; 18 | /* SV version 19 | \SV_plus 20 | wire refresh = |fpga>>0$refresh; 21 | \SV 22 | always @(posedge clk) begin 23 | led = reset ? 16'b0 : 24 | refresh ? led + 1 : 25 | led; 26 | end 27 | */ 28 | \TLV 29 | |fpga 30 | @0 31 | m4+fpga_heartbeat($refresh, 1, 50000000) 32 | $reset = *reset; 33 | ?$refresh 34 | 35 | // ---------------------------- 36 | // Drive $Leds[15:0] here. 37 | $Leds[15:0] <= $reset ? 16'b0 : $Leds + 1; 38 | 39 | //$Leds[15:0] <= 40 | // $reset ? 16'b1 : 41 | // ($Leds == 16'b10000000) ? 16'b1 : 42 | // ($Leds << 1); 43 | // ---------------------------- 44 | 45 | *led = $Leds; 46 | 47 | // M4_BOARD numbering 48 | // 1 - Zedboard 49 | // 2 - Artix-7 50 | // 3 - Basys3 51 | // 4 - Icebreaker // TODO: fix 52 | // 5 - Nexys 53 | m4_define(M4_BOARD, 5) 54 | m4+fpga_init() 55 | m4+fpga_led(*led) 56 | m4+fpga_sseg(*digit, *sseg, *dp) 57 | \SV 58 | endmodule 59 | --------------------------------------------------------------------------------