├── .github ├── install_centos_dependencies_build.sh ├── install_ubuntu_dependencies_build.sh └── workflows │ └── main.yml ├── .gitmodules ├── CMakeLists.txt ├── LICENSE ├── README.md └── rapidsilicon ├── README.md ├── ip ├── ahb2axi_bridge │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── ahb2axi_bridge_gen.py │ │ ├── docs │ │ ├── AHB2AXI_Beta_Release.pdf │ │ ├── AHB2AXI_Beta_Release_.pdf │ │ └── ahb2axi.drawio.png │ │ ├── litex_wrapper │ │ └── ahb2axi_bridge_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── ahb_slave_if_tb.v │ │ └── axi_ram.v │ │ └── src │ │ ├── ahb2axi4.sv │ │ └── beh_lib.sv ├── ahb_sram │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── ahb_sram_gen.py │ │ ├── docs │ │ ├── AHB_SRAM.pdf │ │ └── ahb_sram.png │ │ ├── litex_wrapper │ │ └── ahb_sram_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── ahb_slave_if_tb.v │ │ └── src │ │ ├── ahb_slave_interface.sv │ │ ├── sram.sv │ │ ├── sram8x8k.sv │ │ └── sramc_top.sv ├── axi2ahb_bridge │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi2ahb_bridge_gen.py │ │ ├── docs │ │ ├── AXI2AHB.drawio.png │ │ └── AXI2AHB.pdf │ │ ├── litex_wrapper │ │ ├── __pycache__ │ │ │ └── axi2ahb_bridge_litex_wrapper.cpython-38.pyc │ │ └── axi2ahb_bridge_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ └── README.md │ │ └── src │ │ ├── axi2ahb.sv │ │ └── beh_lib.sv ├── axi2axilite_bridge │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi2axilite_bridge_gen.py │ │ ├── docs │ │ ├── axi2axilite_bridge.pdf │ │ └── axi2axilite_bridge_blackbox.png │ │ ├── litex_wrapper │ │ └── axi2axilite_bridge_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axi2axilite_bridge.py │ │ └── src │ │ ├── axi2axilite.v │ │ ├── axi_addr.v │ │ ├── sfifo.v │ │ └── skidbuffer.v ├── axi_async_fifo │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi_async_fifo_gen.py │ │ ├── docs │ │ ├── axi_Async_fifo.drawio.png │ │ └── axi_async_fifo_v1_0.pdf │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axi_async_fifo_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── README.md │ │ ├── bare_metal_stimulus │ │ │ ├── Makefile │ │ │ ├── build │ │ │ │ └── src │ │ │ │ │ ├── crt.d │ │ │ │ │ └── main.d │ │ │ ├── libs │ │ │ │ └── simple.ld │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── main.c │ │ ├── rtl │ │ │ ├── AXI_RAM_32.hex │ │ │ ├── VexRiscvAxi4.v │ │ │ ├── afifo.v │ │ │ ├── axi_async_fifo.v │ │ │ ├── axi_ram.v │ │ │ ├── axi_ram_per.v │ │ │ ├── dual_port_ram.v │ │ │ ├── synchronizer.v │ │ │ └── vex_soc.v │ │ └── testbench │ │ │ ├── testbench.v │ │ │ └── verilator_tb.cpp │ │ └── src │ │ ├── afifo.v │ │ ├── axi_async_fifo.v │ │ ├── dual_port_ram.v │ │ └── synchronizer.v ├── axi_cdma │ ├── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi_cdma_gen.py │ │ ├── docs │ │ │ ├── axi_cdma.pdf │ │ │ └── cdma1.png │ │ ├── litex_wrapper │ │ │ ├── README.md │ │ │ └── axi_cdma_litex_wrapper.py │ │ ├── sdc │ │ │ └── README.md │ │ ├── sim │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ └── test_axi_cdma.py │ │ └── src │ │ │ └── axi_cdma.v │ └── v2_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi_cdma_gen.py │ │ ├── docs │ │ ├── AXI_CDMA_V2.pdf │ │ └── cdma.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axi_cdma_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axi_cdma.py │ │ └── src │ │ ├── axi_cdma.v │ │ ├── sfifo.v │ │ └── skidbuffer.v ├── axi_crossbar │ ├── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi_crossbar_gen.py │ │ ├── docs │ │ │ ├── axi_crossbar.pdf │ │ │ └── axifullcrossbar1.png │ │ ├── litex_wrapper │ │ │ └── axi_crossbar_litex_wrapper.py │ │ ├── sdc │ │ │ └── README.md │ │ ├── sim │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ └── test_axi_crossbar.py │ │ └── src │ │ │ ├── arbiter.v │ │ │ ├── axi_crossbar.v │ │ │ ├── axi_crossbar_addr.v │ │ │ ├── axi_crossbar_rd.v │ │ │ ├── axi_crossbar_wr.v │ │ │ ├── axi_register_rd.v │ │ │ ├── axi_register_wr.v │ │ │ └── priority_encoder.v │ └── v2_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi_crossbar_gen.py │ │ ├── docs │ │ ├── axi_crossbar.pdf │ │ └── axicrossbar2.png │ │ ├── litex_wrapper │ │ └── axi_crossbar_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axi_crossbar.py │ │ └── src │ │ ├── afifo.v │ │ ├── arbiter.v │ │ ├── axi_cdc.v │ │ ├── axi_crossbar.v │ │ ├── axi_crossbar_addr.v │ │ ├── axi_crossbar_rd.v │ │ ├── axi_crossbar_wr.v │ │ ├── axi_register_rd.v │ │ ├── axi_register_wr.v │ │ ├── dual_port_ram.v │ │ ├── priority_encoder.v │ │ └── synchronizer.v ├── axi_dma │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi_dma_gen.py │ │ ├── docs │ │ ├── axi_dma.pdf │ │ └── axi_dma_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axi_dma_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axi_dma.py │ │ └── src │ │ ├── arbiter.v │ │ ├── axi_dma.v │ │ ├── axi_dma_desc_mux.v │ │ ├── axi_dma_rd.v │ │ ├── axi_dma_wr.v │ │ └── priority_encoder.v ├── axi_dpram │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi_dpram_gen.py │ │ ├── docs │ │ ├── axi_dpram.pdf │ │ └── axi_dpram_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axi_dp_ram_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axi_dp_ram.py │ │ └── src │ │ ├── axi_dp_ram.v │ │ ├── axi_ram_rd_if.v │ │ ├── axi_ram_wr_if.v │ │ └── axi_ram_wr_rd_if.v ├── axi_fifo │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi_fifo_gen.py │ │ ├── docs │ │ ├── AXI_FIFO_Beta_Release.pdf │ │ └── axi_fifo.drawio.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axi_fifo_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axi_fifo.py │ │ └── src │ │ ├── axi_fifo.v │ │ ├── axi_fifo_rd.v │ │ └── axi_fifo_wr.v ├── axi_interconnect │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi_interconnect_gen.py │ │ ├── docs │ │ ├── axi_interconnect.pdf │ │ └── axi_interconnect_blackbox.png │ │ ├── litex_wrapper │ │ └── axi_interconnect_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axi_interconnect.py │ │ └── src │ │ ├── arbiter.v │ │ ├── axi_interconnect.v │ │ └── priority_encoder.v ├── axi_ram │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi_ram_gen.py │ │ ├── docs │ │ ├── axi_ram.pdf │ │ └── axi_ram_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axi_ram_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axi_ram.py │ │ └── src │ │ └── axi_ram.v ├── axi_register │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi_register_gen.py │ │ ├── docs │ │ ├── axi_register.pdf │ │ └── axi_register_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axi_register_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axi_register.py │ │ └── src │ │ ├── axi_register.v │ │ ├── axi_register_rd.v │ │ └── axi_register_wr.v ├── axi_sdram │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axi_sdram_gen.py │ │ ├── docs │ │ ├── axi_sdram.png │ │ └── axi_sdram_v1_0.pdf │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axi_sdram_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axi_ram.py │ │ └── src │ │ ├── sdram_axi.v │ │ ├── sdram_axi_core.v │ │ └── sdram_axi_pmem.v ├── axil_crossbar │ ├── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axil_crossbar_gen.py │ │ ├── docs │ │ │ ├── axil_crossbar.pdf │ │ │ └── axilite_crossbar.png │ │ ├── litex_wrapper │ │ │ └── axil_crossbar_litex_wrapper.py │ │ ├── sdc │ │ │ └── README.md │ │ ├── sim │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ └── test_axil_crossbar.py │ │ └── src │ │ │ ├── arbiter.v │ │ │ ├── axil_crossbar.v │ │ │ ├── axil_crossbar_addr.v │ │ │ ├── axil_crossbar_rd.v │ │ │ ├── axil_crossbar_wr.v │ │ │ ├── axil_register_rd.v │ │ │ ├── axil_register_wr.v │ │ │ └── priority_encoder.v │ └── v2_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axil_crossbar_gen.py │ │ ├── docs │ │ ├── axi_crossbar_lite.pdf │ │ └── axilitecrosbarcdc.png │ │ ├── litex_wrapper │ │ └── axil_crossbar_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axil_crossbar.py │ │ └── src │ │ ├── afifo.v │ │ ├── arbiter.v │ │ ├── axi_cdc.v │ │ ├── axil_crossbar.v │ │ ├── axil_crossbar_addr.v │ │ ├── axil_crossbar_rd.v │ │ ├── axil_crossbar_wr.v │ │ ├── axil_register_rd.v │ │ ├── axil_register_wr.v │ │ ├── dual_port_ram.v │ │ ├── priority_encoder.v │ │ └── synchronizer.v ├── axil_eio │ └── v1_0 │ │ ├── LICENSE │ │ ├── axil_eio_gen.py │ │ ├── docs │ │ ├── eio.pdf │ │ └── eio.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axil_eio_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── eio_tb.sv │ │ └── src │ │ ├── axil_slave.v │ │ ├── eio_top.v │ │ └── ff_sync_eio.v ├── axil_gpio │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axil_gpio_gen.py │ │ ├── docs │ │ ├── axil_gpio.pdf │ │ └── axil_gpio_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axil_gpio_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ └── README.md │ │ └── src │ │ ├── axadrchsm.sv │ │ ├── axi4lite_gpio.sv │ │ ├── axi4liteif.sv │ │ ├── axrdch.sv │ │ ├── axwrch.sv │ │ └── gpcore.sv ├── axil_interconnect │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axil_interconnect_gen.py │ │ ├── docs │ │ ├── axil_interconnect.pdf │ │ └── axil_interconnect_blackbox.png │ │ ├── litex_wrapper │ │ └── axil_interconnect_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axil_interconnect.py │ │ └── src │ │ ├── arbiter.v │ │ ├── axil_interconnect.v │ │ └── priority_encoder.v ├── axil_quadspi │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axil_quadspi_architecture.png │ │ ├── axil_quadspi_gen.py │ │ ├── docs │ │ ├── axil_quadspi.drawio.png │ │ └── axil_quadspi_v10.pdf │ │ ├── litespi_generator.py │ │ └── sim │ │ ├── N25Q_sim.v │ │ ├── README.md │ │ ├── axil_quadspi_mem.init │ │ ├── firmware │ │ ├── Makefile │ │ ├── crt0.o │ │ ├── isr.c │ │ ├── linker.ld │ │ ├── main.c │ │ ├── main.o │ │ ├── spi_flash.c │ │ ├── spi_flash.h │ │ ├── spi_flash.o │ │ └── spi_flash_csr.h │ │ └── test_axil_quadspi.py ├── axil_tmp_sensor │ └── v1_0 │ │ ├── IP.log │ │ ├── LICENSE │ │ ├── axil_tmp_sensor_gen.py │ │ ├── docs │ │ ├── README.md │ │ ├── tmp_sensor.png │ │ └── tmp_sensor_user_guide.pdf │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axil_tmp_sensor_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── SOC_FPGA_TEMPERATURE.v │ │ ├── SOC_FPGA_TEMPERATURE_tb.v │ │ └── temp.dat │ │ └── src │ │ ├── TEMPERATURE_AXI_INTF.v │ │ └── fifo.v ├── axil_uart16550 │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axil_uart16550_gen.py │ │ ├── docs │ │ ├── axil_uart.pdf │ │ └── axil_uart_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axil_uart16550_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ └── README.md │ │ └── src │ │ ├── axi4lite_slave.v │ │ ├── axi4lite_uart_top.v │ │ ├── raminfr.v │ │ ├── timescale.v │ │ ├── uart_debug_if.v │ │ ├── uart_defines.vh │ │ ├── uart_receiver.v │ │ ├── uart_regs.v │ │ ├── uart_rfifo.v │ │ ├── uart_sync_flops.v │ │ ├── uart_tfifo.v │ │ └── uart_transmitter.v ├── axis_adapter │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axis_adapter_gen.py │ │ ├── docs │ │ ├── axis_adapter.pdf │ │ └── axis_adapter_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axis_adapter_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axis_adapter.py │ │ └── src │ │ └── axis_adapter.v ├── axis_async_fifo │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axis_async_fifo_gen.py │ │ ├── docs │ │ ├── AXIS_Async_FIFO_Beta_Release_.pdf │ │ └── axis_async_fifo.drawio.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axis_async_fifo_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axis_async_fifo.py │ │ └── src │ │ └── axis_async_fifo.v ├── axis_broadcast │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axis_broadcast_gen.py │ │ ├── docs │ │ ├── axis_broadcast.pdf │ │ └── axis_broadcast_blackbox.png │ │ ├── litex_wrapper │ │ └── axis_broadcast_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axis_broadcast.py │ │ └── src │ │ └── axis_broadcast.v ├── axis_fifo │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axis_fifo_gen.py │ │ ├── docs │ │ ├── AXIS_FIFO_Beta_Release.pdf │ │ └── axis_fifo.drawio.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axis_fifo_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axis_fifo.py │ │ └── src │ │ └── axis_fifo.v ├── axis_interconnect │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axis_interconnect_gen.py │ │ ├── docs │ │ ├── axis_interconnect.pdf │ │ └── axis_interconnect_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axis_interconnect_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── axis_ep.py │ │ ├── myhdl.vpi │ │ ├── test_axis_crosspoint_4x4.py │ │ └── test_axis_crosspoint_4x4.v │ │ └── src │ │ └── axis_crosspoint.v ├── axis_pipeline_register │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axis_pipeline_register_gen.py │ │ ├── docs │ │ ├── axis_pipeline_register.pdf │ │ └── axis_pipeline_register_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axis_pipeline_register_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axis_pipeline_register.py │ │ └── src │ │ ├── axis_pipeline_register.v │ │ └── axis_register.v ├── axis_ram_switch │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axis_ram_switch_gen.py │ │ ├── docs │ │ ├── axis_ram_switch.pdf │ │ └── axis_ram_switch_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axis_ram_switch_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axis_ram_switch.py │ │ └── src │ │ ├── arbiter.v │ │ ├── axis_adapter.v │ │ ├── axis_ram_switch.v │ │ └── priority_encoder.v ├── axis_switch │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axis_switch_gen.py │ │ ├── docs │ │ ├── axis_switch.pdf │ │ └── axis_switch_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axis_switch_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── test_axis_switch.py │ │ └── src │ │ ├── arbiter.v │ │ ├── axis_register.v │ │ ├── axis_switch.v │ │ └── priority_encoder.v ├── axis_uart │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── axis_uart_gen.py │ │ ├── docs │ │ ├── axis_uart.pdf │ │ └── axis_uart_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── axis_uart_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── axis_ep.py │ │ ├── myhdl.vpi │ │ ├── test_uart_rx.py │ │ ├── test_uart_rx.v │ │ ├── test_uart_tx.py │ │ ├── test_uart_tx.v │ │ └── uart_ep.py │ │ └── src │ │ ├── uart.v │ │ ├── uart_rx.v │ │ └── uart_tx.v ├── boot_clock │ └── v1_0 │ │ ├── boot_clock_gen.py │ │ ├── docs │ │ ├── boot_clock.drawio.png │ │ └── boot_clock.pdf │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── boot_clock_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ └── src │ │ └── BOOT_CLOCK.v ├── ddr_sdram │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── ddr_sdram_gen.py │ │ ├── docs │ │ ├── ddr.drawio.png │ │ └── ddr_sdram_v1_0-1.pdf │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── ddr_sdram_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── axi_self_test_master.v │ │ ├── micron_ddr_sdram_model.v │ │ ├── tb_ddr_sdram_ctrl.v │ │ └── tb_ddr_sdram_ctrl_run_iverilog.bat │ │ └── src │ │ └── ddr_sdram_ctrl.v ├── deskew │ └── v1_0 │ │ ├── LICENSE │ │ ├── deskew_gen.py │ │ ├── docs │ │ └── README.md │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── high_speed_comun_sys_tb.v │ │ ├── receiver │ │ │ ├── DLY_ADDR_CNTRL.v │ │ │ ├── DLY_CONFIG.v │ │ │ ├── Idly_Cntrl.v │ │ │ ├── deskew_cntrl.v │ │ │ ├── deskew_cntrl_wrap.v │ │ │ ├── deskew_wrapper_v1_0.v │ │ │ ├── io_configurator_v1_0.v │ │ │ └── receiver_top.v │ │ ├── top │ │ │ └── high_speed_comun_sys.v │ │ └── transmiter │ │ │ ├── DLY_ADDR_CNTRL_trans.v │ │ │ ├── DLY_CONFIG_trans.v │ │ │ ├── io_configurator_trans_v1_0.v │ │ │ └── transmiter_top.v │ │ └── src │ │ ├── Idly_Cntrl.v │ │ ├── deskew_cntrl.v │ │ └── deskew_cntrl_wrap.v ├── dsp_generator │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── docs │ │ ├── DSP_Generator.pdf │ │ └── dsp_generator_blackbox.png │ │ ├── dsp_generator_gen.py │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── dsp_litex_generator.py │ │ ├── sdc │ │ └── README.md │ │ └── sim │ │ ├── DSP38.v │ │ ├── Makefile │ │ ├── README.md │ │ └── dsp_test.v ├── ethernet_mac │ └── v1_0 │ │ ├── LICENSE │ │ ├── docs │ │ ├── eth_block.png │ │ └── ethernet_mac.pdf │ │ ├── ethernet_mac_gen.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── CLK_BUF.v │ │ ├── Makefile │ │ ├── O_DDR.v │ │ ├── test_top.py │ │ └── top.v │ │ └── src │ │ ├── axis_adapter.v │ │ ├── axis_async_fifo.v │ │ ├── axis_async_fifo_adapter.v │ │ ├── axis_gmii_rx.v │ │ ├── axis_gmii_tx.v │ │ ├── eth_mac_1g.v │ │ ├── eth_mac_1g_gmii.v │ │ ├── eth_mac_1g_gmii_fifo.v │ │ ├── eth_mac_1g_rgmii.v │ │ ├── eth_mac_1g_rgmii_fifo.v │ │ ├── gmii_phy_if.v │ │ ├── iddr.v │ │ ├── lfsr.v │ │ ├── mac_ctrl_rx.v │ │ ├── mac_ctrl_tx.v │ │ ├── mac_pause_ctrl_rx.v │ │ ├── mac_pause_ctrl_tx.v │ │ ├── oddr.v │ │ ├── rgmii_phy_if.v │ │ ├── ssio_ddr_in.v │ │ ├── ssio_sdr_in.v │ │ └── ssio_sdr_out.v ├── fifo_generator │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── docs │ │ ├── FIFO_Generator.pdf │ │ └── fifo_generator_blackbox.png │ │ ├── fifo_generator_gen.py │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── fifo_litex_generator.py │ │ ├── sdc │ │ └── README.md │ │ └── sim │ │ ├── FIFO18KX2.v │ │ ├── FIFO36K.v │ │ ├── Makefile │ │ ├── README.md │ │ ├── TDP_RAM18KX2.v │ │ ├── TDP_RAM36K.v │ │ └── testbench.v ├── fir_generator │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── docs │ │ ├── FIR_Generator.pdf │ │ └── fir_generator_blackbox.png │ │ ├── fir_generator_gen.py │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── fir_litex_generator.py │ │ ├── sdc │ │ └── README.md │ │ └── sim │ │ ├── DSP38.v │ │ ├── Makefile │ │ ├── README.md │ │ ├── fir_golden.v │ │ └── testbench.v ├── i2c_master │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── docs │ │ ├── i2c_master.pdf │ │ └── i2c_master_blackbox.png │ │ ├── i2c_master_gen.py │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── i2c_master_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── axil.py │ │ ├── i2c.py │ │ ├── myhdl.vpi │ │ ├── test_i2c.py │ │ ├── test_i2c_master_axil.py │ │ └── test_i2c_master_axil.v │ │ └── src │ │ ├── axis_fifo.v │ │ ├── i2c_master.v │ │ └── i2c_master_axil.v ├── i2c_slave │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── docs │ │ ├── i2c_slave.pdf │ │ └── i2c_slave_blackbox.png │ │ ├── i2c_slave_gen.py │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── i2c_slave_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── axil.py │ │ ├── i2c.py │ │ ├── myhdl.vpi │ │ ├── test_i2c.py │ │ ├── test_i2c_slave_axil_master.py │ │ └── test_i2c_slave_axil_master.v │ │ └── src │ │ ├── i2c_slave.v │ │ └── i2c_slave_axil_master.v ├── io_configurator │ └── v1_0 │ │ ├── LICENSE │ │ ├── docs │ │ ├── CLK_BUF.png │ │ ├── I_BUF.png │ │ ├── I_DDR.png │ │ ├── I_DELAY+I_DDR.png │ │ ├── I_DELAY+I_SERDES.png │ │ ├── I_DELAY.png │ │ ├── I_SERDES.png │ │ ├── O_BUF.png │ │ ├── O_DDR.png │ │ ├── O_DELAY+O_DDR.png │ │ ├── O_DELAY+O_SERDES.png │ │ ├── O_DELAY.png │ │ ├── O_SERDES.png │ │ └── io_configurator.pdf │ │ ├── io_configurator_gen.py │ │ ├── sdc │ │ ├── README.md │ │ └── constraint.txt │ │ ├── sim │ │ ├── BOOT_CLOCK.v │ │ ├── Makefile │ │ ├── O_BUFT.v │ │ ├── O_DELAY.v │ │ ├── O_SERDES.v │ │ ├── PLL.v │ │ ├── io_configurator_v1_0.v │ │ └── testbench.v │ │ └── src │ │ ├── DLY_ADDR_CNTRL.v │ │ ├── DLY_CONFIG.v │ │ └── header.vh ├── jtag_to_axi │ └── v1_0 │ │ ├── LICENSE │ │ ├── docs │ │ ├── jtag2axi.png │ │ └── jtag_to_axi.pdf │ │ ├── jtag_to_axi_gen.py │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── jtag_to_axi_litex_wrapper.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ └── README.md │ │ └── src │ │ ├── bscell.sv │ │ ├── ff_sync.sv │ │ ├── jtag_axi_wrap.sv │ │ ├── jtag_to_axi_top.sv │ │ ├── jtagreg.sv │ │ └── tap_top.sv ├── ocla │ └── v1_0 │ │ ├── docs │ │ ├── ocla.pdf │ │ └── ocla.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── ocla_litex_wrapper.py │ │ ├── ocla_gen.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── ocla_debug_tb.sv │ │ └── ocla_top.sv │ │ └── src │ │ ├── arbiter.v │ │ ├── axi2axilite.v │ │ ├── axi_addr.v │ │ ├── axil_interconnect.v │ │ ├── axil_slave.v │ │ ├── bscell.sv │ │ ├── eio_top.v │ │ ├── ff_sync.sv │ │ ├── ff_sync_eio.v │ │ ├── jtag_axi_wrap.sv │ │ ├── jtag_to_axi_top.sv │ │ ├── jtagreg.sv │ │ ├── ocla.sv │ │ ├── ocla_debug_subsystem.sv │ │ ├── priority_encoder.v │ │ ├── sfifo.v │ │ ├── skidbuffer.v │ │ └── tap_top.sv ├── on_chip_memory │ └── v1_0 │ │ ├── LICENSE │ │ ├── docs │ │ ├── ocm_blackbox.png │ │ └── on_chip_memory.pdf │ │ ├── litex_wrapper │ │ ├── on_chip_memory_litex_wrapper_asymmetric.py │ │ └── on_chip_memory_litex_wrapper_symmetric.py │ │ ├── on_chip_memory_gen.py │ │ ├── sdc │ │ └── README.md │ │ └── sim │ │ ├── Makefile │ │ ├── TDP_RAM36K.v │ │ ├── on_chip_memory_v1_0.v │ │ └── testbench.v ├── pll │ └── v1_0 │ │ ├── LICENSE │ │ ├── docs │ │ ├── PLL_v1_0_Beta_Release_.pdf │ │ └── pll.drawio.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── pll_litex_wrapper.py │ │ ├── pll_gen.py │ │ └── synth │ │ └── raptor.tcl ├── priority_encoder │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── docs │ │ ├── priority_encoder.pdf │ │ └── priority_encoder_blackbox.png │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── priority_encoder_litex_wrapper.py │ │ ├── priority_encoder_gen.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ └── README.md │ │ └── src │ │ └── priority_encoder.v ├── reset_release │ └── v1_0 │ │ ├── LICENSE │ │ ├── README.md │ │ ├── docs │ │ ├── reset_Release.drawio(1).png │ │ └── reset_release_v1_0.pdf │ │ ├── litex_wrapper │ │ ├── README.md │ │ └── reset_release_litex_wrapper.py │ │ ├── reset_release_gen.py │ │ ├── sdc │ │ └── README.md │ │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ └── testbench.v │ │ └── src │ │ └── reset_release.v └── vexriscv_cpu │ └── v1_0 │ ├── LICENSE │ ├── README.md │ ├── docs │ ├── vexriscv_blackbox.png │ └── vexriscv_cpu.pdf │ ├── litex_wrapper │ ├── REAMDE.md │ └── vexriscv_cpu_litex_wrapper.py │ ├── sdc │ └── README.md │ ├── sim │ ├── Makefile │ ├── README.md │ ├── encoding.h │ ├── jtag.h │ ├── linux │ │ ├── emulator │ │ │ └── emulator.bin │ │ └── rv32ima │ │ │ ├── Image │ │ │ ├── rootfs.cpio │ │ │ └── rv32.dtb │ └── main.cpp │ ├── src │ ├── vexriscv_cached_mmu.v │ ├── vexriscv_cached_mmu_plic_clint.v │ └── vexriscv_uncached_nommu.v │ └── vexriscv_cpu_gen.py └── lib └── common.py /.github/install_centos_dependencies_build.sh: -------------------------------------------------------------------------------- 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