├── .github ├── actions │ └── action.yml ├── bin │ ├── execute_parallel.py │ ├── run-clang-format.sh │ └── run-clang-tidy.sh ├── copy_arch.sh ├── pull_request_template.md └── workflows │ ├── Dockerfile │ ├── alert.yml │ ├── build_centos_image.yml │ ├── install_centos_dependencies_build.sh │ ├── install_litex_centos.sh │ ├── install_litex_ubuntu.sh │ ├── install_macos_dependencies_build.sh │ ├── install_ubuntu_dependencies_build.sh │ └── main.yml ├── .gitignore ├── .gitmodules ├── BUILD.md ├── CMakeLists.txt ├── INSTALL.md ├── LICENSE.md ├── Makefile ├── README.md ├── docs ├── Raptor_User_Guide.pdf └── raptor-features-screenshot.png ├── etc ├── Welcome_Page │ ├── WelcomeDescription.txt │ ├── WelcomeLogo.png │ └── copyrightDescription.txt ├── config.json ├── copyright.txt ├── device.xml ├── devices │ ├── custom_layout_template.xml │ └── mpw1 │ │ ├── TSMC22nm_openfpga.xml │ │ ├── TSMC22nm_vpr.xml │ │ ├── bitstream_annotation_empty.xml │ │ ├── fabric_key.xml │ │ ├── fixed_sim_openfpga.xml │ │ ├── pinmap_qlf_k6n10_tsmc22.csv │ │ ├── pinmap_qlf_k6n10_tsmc22.xml │ │ ├── power │ │ ├── bcpu.json │ │ ├── clocking.json │ │ ├── fabric_le.json │ │ ├── io.json │ │ ├── noc.json │ │ ├── power_data.json │ │ ├── puffcc.json │ │ ├── qspi.json │ │ ├── rc_osc.json │ │ ├── regulator.json │ │ └── sram.json │ │ └── repack_design_constraint.xml ├── help.txt ├── init │ ├── flow.tcl │ └── sim_helpers.tcl ├── package_pin_info.json ├── settings │ ├── messages │ │ ├── suppress-rel.json │ │ └── suppress.json │ └── settings_test.json └── vpr_e.bin ├── examples ├── AES_DECRYPT │ ├── AES_DECRYPT.ospr │ ├── AES_DECRYPT.srcs │ │ ├── constrs_1 │ │ │ └── aes_decrypt.sdc │ │ └── sources_1 │ │ │ ├── InvAddRoundKey.sv │ │ │ ├── InvMixCol_slice.sv │ │ │ ├── InvMixColumns.sv │ │ │ ├── InvSbox.sv │ │ │ ├── InvShiftRows.sv │ │ │ ├── InvSubBytes.sv │ │ │ ├── KeyExpand128.sv │ │ │ ├── KeyExpand192.sv │ │ │ ├── KeyExpand256.sv │ │ │ ├── KschBuffer.sv │ │ │ ├── RotWord.sv │ │ │ ├── Sbox.sv │ │ │ ├── SubWord.sv │ │ │ ├── aes_decrypt128.sv │ │ │ ├── aes_decrypt192.sv │ │ │ ├── aes_decrypt256.SV │ │ │ ├── aes_decrypt256.sv │ │ │ ├── decrypt.sv │ │ │ ├── generic_muxfx.v │ │ │ ├── gfmul.sv │ │ │ └── wrapper.v │ └── run_1 │ │ ├── AES_DECRYPT.srcs │ │ ├── constrs_1 │ │ │ └── aes_decrypt.sdc │ │ └── sources_1 │ │ │ ├── InvAddRoundKey.sv │ │ │ ├── InvMixCol_slice.sv │ │ │ ├── InvMixColumns.sv │ │ │ ├── InvSbox.sv │ │ │ ├── InvShiftRows.sv │ │ │ ├── InvSubBytes.sv │ │ │ ├── KeyExpand128.sv │ │ │ ├── KeyExpand192.sv │ │ │ ├── KeyExpand256.sv │ │ │ ├── KschBuffer.sv │ │ │ ├── RotWord.sv │ │ │ ├── Sbox.sv │ │ │ ├── SubWord.sv │ │ │ ├── aes_decrypt128.sv │ │ │ ├── aes_decrypt192.sv │ │ │ ├── aes_decrypt256.SV │ │ │ ├── aes_decrypt256.sv │ │ │ ├── decrypt.sv │ │ │ ├── generic_muxfx.v │ │ │ ├── gfmul.sv │ │ │ └── wrapper.v │ │ └── synth_1_1 │ │ ├── impl_1_1_1 │ │ └── impl_1_1_1_settings │ │ │ ├── Tasks_Placement.json │ │ │ └── Tasks_Timing Analysis.json │ │ └── synth_1_1_settings │ │ └── Tasks_Synthesis.json ├── and2_gemini │ ├── and2_gemini.ospr │ ├── and2_gemini.settings │ │ ├── Tasks_Placement.json │ │ ├── Tasks_Synthesis.json │ │ └── Tasks_Timing Analysis.json │ ├── and2_gemini.srcs │ │ ├── constrs_1 │ │ │ └── constraints.sdc │ │ ├── sim_1 │ │ │ └── testbench_and2.v │ │ └── sources_1 │ │ │ └── and2.v │ └── run_1 │ │ ├── and2_gemini.srcs │ │ ├── constrs_1 │ │ │ └── constraints.sdc │ │ ├── sim_1 │ │ │ └── testbench_and2.v │ │ └── sources_1 │ │ │ └── and2.v │ │ └── synth_1_1 │ │ ├── impl_1_1_1 │ │ └── impl_1_1_1_settings │ │ │ ├── Tasks_Placement.json │ │ │ └── Tasks_Timing Analysis.json │ │ └── synth_1_1_settings │ │ └── Tasks_Synthesis.json ├── incr_comp │ ├── incr_comp.ospr │ ├── incr_comp.srcs │ │ └── sources_1 │ │ │ └── tmp.v │ └── run_1 │ │ ├── incr_comp.srcs │ │ └── sources_1 │ │ │ └── tmp.v │ │ └── synth_1_1 │ │ ├── impl_1_1_1 │ │ └── impl_1_1_1_settings │ │ │ ├── Tasks_Placement.json │ │ │ └── Tasks_Timing Analysis.json │ │ └── synth_1_1_settings │ │ └── Tasks_Synthesis.json └── sasc_testcase │ ├── run_1 │ ├── sasc_testcase.srcs │ │ ├── constrs_1 │ │ │ └── constraints.sdc │ │ └── sources_1 │ │ │ ├── config.tcl │ │ │ ├── sasc.v │ │ │ ├── sasc_brg.v │ │ │ ├── sasc_fifo4.v │ │ │ ├── sdc.json │ │ │ └── timescale.v │ └── synth_1_1 │ │ ├── impl_1_1_1 │ │ └── impl_1_1_1_settings │ │ │ ├── Tasks_Placement.json │ │ │ └── Tasks_Timing Analysis.json │ │ └── synth_1_1_settings │ │ └── Tasks_Synthesis.json │ ├── sasc_testcase.ospr │ └── sasc_testcase.srcs │ ├── constrs_1 │ └── constraints.sdc │ └── sources_1 │ ├── config.tcl │ ├── sasc.v │ ├── sasc_brg.v │ ├── sasc_fifo4.v │ ├── sdc.json │ └── timescale.v ├── fetch_assets.py ├── gen_rel_device.py ├── lib ├── pnr │ ├── genesis │ │ └── primitives.v │ └── genesis3 │ │ └── primitives.v └── python3 │ └── tb_generator.py ├── licenses ├── agpl-1.0.xml ├── aladdin.xml ├── apache-2.0.xml ├── bsd-2-clause-freebsd.xml ├── bsd-2-clause-netbsd.xml ├── bsd-2-clause-patent.xml ├── bsd-2-clause.xml ├── bsd-3-clause-attribution.xml ├── bsd-3-clause-clear.xml ├── bsd-3-clause-lbnl.xml ├── bsd-3-clause-no-nuclear-license-2014.xml ├── bsd-3-clause.xml ├── bsd-4-clause-uc.xml ├── bsd-source-code.xml ├── bsl-1.0.xml ├── bzip2-1.0.5.xml ├── bzip2-1.0.6.xml ├── cc-by-3.0.xml ├── cc-by-sa-4.0.xml ├── cc0-1.0.xml ├── cecill-1.1.xml ├── cecill-2.1.xml ├── cecill-c.xml ├── condor-1.1.xml ├── ecl-2.0.xml ├── ecos-2.0.xml ├── gfdl-1.3-only.xml ├── gfdl-1.3-or-later.xml ├── gpl-2.0+.xml ├── gpl-2.0-only.xml ├── gpl-2.0-or-later.xml ├── gpl-2.0.xml ├── gpl-3.0+.xml ├── gpl-3.0-only.xml ├── gpl-3.0.xml ├── ibm-pibs.xml ├── icu.xml ├── imlib2.xml ├── intel.xml ├── interbase-1.0.xml ├── isc.xml ├── jasper-2.0.xml ├── json.xml ├── lgpl-2.0+.xml ├── lgpl-2.0-only.xml ├── lgpl-2.0-or-later.xml ├── lgpl-2.1+.xml ├── lgpl-2.1-only.xml ├── lgpl-2.1-or-later.xml ├── lgpl-2.1.xml ├── lgpl-3.0.xml ├── lppl-1.0.xml ├── mit-advertising.xml ├── mit-enna.xml ├── mit.xml ├── noassertion.xml ├── npl-1.1.xml ├── ofl-1.1.xml ├── postgresql.xml ├── rs-eula.txt ├── sleepycat.xml ├── tcl.xml ├── unlicense.xml ├── upl-1.0.xml ├── x11.xml ├── xnet.xml ├── zimbra-1.3.xml └── zlib.xml ├── ql_to_rs.sh ├── raptor_version.h.in ├── src ├── .raptorenv_lin64.sh ├── ConfigurationRaptor │ ├── CFGDeviceDatabase │ │ ├── CFGDeviceDatabase.cpp │ │ ├── CFGDeviceDatabase.h │ │ ├── CFGDeviceDatabase.py │ │ ├── CMakeLists.txt │ │ ├── Gemini │ │ │ └── config_attributes.mapping.json │ │ ├── Virgo │ │ │ ├── 1vg28_routing.py │ │ │ ├── config_attributes.mapping.json │ │ │ ├── gemini_compact_10x8_config_attributes.mapping.json │ │ │ ├── gemini_compact_22x4_config_attributes.mapping.json │ │ │ ├── gemini_compact_22x4_routing.py │ │ │ ├── gemini_compact_62x44_routing.py │ │ │ ├── icb_backdoor.py │ │ │ └── routing_library │ │ │ │ ├── __init__.py │ │ │ │ ├── function_library.py │ │ │ │ ├── gbox_fclk_mux.py │ │ │ │ ├── gbox_hp_40x2.py │ │ │ │ ├── gbox_hpio.py │ │ │ │ ├── gbox_hv_40x2.py │ │ │ │ ├── gbox_osc.py │ │ │ │ ├── gbox_pll.py │ │ │ │ ├── gbox_pll_refmux.py │ │ │ │ ├── gbox_root_bank_clkmux.py │ │ │ │ ├── gbox_top.py │ │ │ │ └── gemini_compact_22x4_gbox_hp_40x1.py │ │ ├── gearbox_block_diagrams │ │ │ └── 1vg28 │ │ │ │ ├── PLL.gv.pdf │ │ │ │ ├── Virgo.gv.pdf │ │ │ │ ├── gbox_fclk_mux.gv.pdf │ │ │ │ ├── gbox_hp_40x2.gv.pdf │ │ │ │ ├── gbox_hpio.gv.pdf │ │ │ │ ├── gbox_hv_40x2.gv.pdf │ │ │ │ ├── gbox_pll_refmux.gv.pdf │ │ │ │ ├── gbox_root_bank_clkmux.gv.pdf │ │ │ │ ├── gbox_top.gv.pdf │ │ │ │ └── rc_osc_50mhz.gv.pdf │ │ └── routing_configurator.py │ └── CMakeLists.txt ├── Main │ ├── MPW1Loader.cpp │ ├── MPW1Loader.h │ └── main.cpp ├── ProgrammerGui │ ├── CMakeLists.txt │ └── main.cpp ├── raptorenv_lin64.sh ├── to_be_raptor_checker └── to_be_raptor_linx ├── tests.mk └── tests ├── Arch ├── bitstream_annotation.xml ├── bitstream_annotation_empty.xml ├── fixed_sim_openfpga.xml ├── k6_N10_40nm_openfpga.xml ├── k6_frac_N10_tileable_40nm.xml └── repack_design_constraint.xml ├── Build ├── cache_104x68 │ ├── Src │ │ ├── and2.v │ │ └── testbench_and2.v │ └── run_raptor.tcl └── cache_10x8 │ ├── Src │ ├── and2.v │ └── testbench_and2.v │ ├── run_raptor.tcl │ └── run_raptor.tcl~ ├── TestBatch ├── oneff_clean │ ├── constraints.sdc │ ├── dut.v │ ├── pin_mapping.pin │ ├── raptor.tcl │ ├── sim_main.cpp │ └── syn_tb.v ├── test_compiler_batch.tcl └── test_compiler_mt.tcl ├── TestGui ├── gtkwave_cmds.tcl ├── gui_foedag.tcl ├── gui_run_incr_comp_project.tcl ├── test.v └── test.vcd ├── TestIP ├── axi2axilite_bridge │ └── v1_0 │ │ └── axi2axilite_bridge.tcl ├── axi_cdma │ └── v1_0 │ │ └── axi_cdma.tcl ├── axi_interconnect │ └── v1_0 │ │ └── axi_interconnect.tcl ├── axi_ram │ └── v1_0 │ │ └── axi_ram.tcl ├── axi_register │ └── v1_0 │ │ └── axi_register.tcl ├── axil_gpio │ └── v1_0 │ │ └── axil_gpio.tcl ├── axis_adapter │ └── v1_0 │ │ └── axis_adapter.tcl ├── axis_fifo │ └── v1_0 │ │ └── axis_fifo.tcl ├── ip_simulation │ └── axi_ram │ │ └── v1_0 │ │ └── axi_ram.tcl └── reset_release │ └── v1_0 │ └── reset_release.tcl ├── Testcases ├── aes_decrypt_fpga │ ├── InvAddRoundKey.sv │ ├── InvMixCol_slice.sv │ ├── InvMixColumns.sv │ ├── InvSbox.sv │ ├── InvShiftRows.sv │ ├── InvSubBytes.sv │ ├── KeyExpand128.sv │ ├── KeyExpand192.sv │ ├── KeyExpand256.sv │ ├── KschBuffer.sv │ ├── RotWord.sv │ ├── Sbox.sv │ ├── SubWord.sv │ ├── aes_decrypt.sdc │ ├── aes_decrypt.tcl │ ├── aes_decrypt128.sv │ ├── aes_decrypt192.sv │ ├── aes_decrypt256.sv │ ├── decrypt.sv │ ├── generic_muxfx.v │ ├── gfmul.sv │ ├── pin_constraints.pin │ └── wrapper.v ├── aes_decrypt_gate │ ├── aes_decrypt.blif │ ├── aes_decrypt.v │ ├── aes_decrypt_gate.sdc │ ├── aes_decrypt_gate.tcl │ └── aes_decrypt_ports.json ├── and2_10x8 │ ├── pin_mapping.pin │ ├── raptor.tcl │ └── rtl │ │ ├── and2.v │ │ └── testbench_and2.v ├── and2_2clks │ ├── Src │ │ ├── and2x2.v │ │ └── testbench_and2.v │ ├── constraints.sdc │ ├── gtkwave.tcl │ ├── pin_constraints.pin │ └── run_raptor.tcl ├── and2_compact │ ├── constraints.sdc │ ├── pin_mapping.pin │ ├── raptor.tcl │ └── rtl │ │ └── and2.v ├── and2_gemini │ ├── constraints.sdc │ ├── pin_mapping.pin │ ├── raptor.tcl │ └── rtl │ │ └── and2.v ├── and2_gemini_latest │ ├── constraints.sdc │ ├── pin_mapping.pin │ ├── raptor.tcl │ └── rtl │ │ └── and2.v ├── and2_gemini_no_pcf │ ├── constraints.sdc │ ├── raptor.tcl │ └── rtl │ │ └── and2.v ├── and2_hierarchical │ ├── gate.v │ └── raptor_gate.tcl ├── and2_legacy │ ├── constraints.sdc │ ├── pin_mapping.pin │ ├── pin_mapping.pin~ │ ├── raptor.tcl │ ├── raptor.tcl~ │ └── rtl │ │ └── and2.v ├── and2_pin_table_test │ ├── Src │ │ ├── and2.v │ │ └── testbench_and2.v │ ├── and2_part.xml │ ├── constraints.sdc │ ├── gtkwave.tcl │ ├── pin_mapping.pin │ ├── readme_and2_verilog.txt │ └── run_raptor.tcl ├── and2_reg │ ├── constraints.sdc │ ├── pin.sdc │ ├── pin_mapping.pin │ ├── raptor.tcl │ └── rtl │ │ ├── and2.sv │ │ ├── and2.sv~ │ │ └── and2.v ├── and2_repack_constraints │ ├── constraints.sdc │ ├── pin.sdc │ ├── pin_mapping.pin │ ├── raptor.tcl │ └── rtl │ │ ├── and2.sv │ │ ├── and2.sv~ │ │ └── and2.v ├── and2_testcase │ ├── constraints.sdc │ ├── raptor.tcl │ ├── rtl │ │ └── and2.v │ └── verilog.tcl ├── and2_testcase_no_pcf │ ├── constraints.sdc │ ├── raptor.tcl │ └── rtl │ │ └── and2.v ├── and2_vec │ ├── Src │ │ ├── and2.v │ │ └── testbench_and2.v │ ├── constraints.sdc │ ├── gtkwave.tcl │ ├── pin_mapping.pin │ ├── readme_and2_verilog.txt │ └── run_raptor.tcl ├── and2_verilog │ ├── Src │ │ ├── and2.v │ │ └── testbench_and2.v │ ├── and2_part.xml │ ├── constraints.sdc │ ├── gtkwave.tcl │ ├── pin_mapping.pin │ ├── readme_and2_verilog.txt │ └── run_raptor.tcl ├── and2_wio │ ├── Src │ │ ├── and2.v │ │ └── testbench_and2.v │ ├── constraints.sdc │ ├── gtkwave.tcl │ ├── pin_mapping.pin │ ├── readme_and2_verilog.txt │ └── run_raptor.tcl ├── auto_testbench │ ├── GJC1.v │ ├── raptor_lec.tcl │ └── raptor_tcl.tcl ├── constant │ ├── add__a_to_output.v │ ├── raptor.tcl │ └── tb.v ├── counter │ ├── constraints.sdc │ ├── counter.tcl │ └── counter.v ├── counter16 │ ├── counter16.tcl │ ├── counter16.v │ └── pin_mapping.pin ├── counter_mixed │ ├── UP_COUNTER.vhd │ ├── constraints.sdc │ ├── counter.v │ ├── pin_mapping.pin │ ├── raptor.tcl │ └── testbench.vhd ├── counter_vhdl │ ├── UP_COUNTER.vhd │ ├── constraints.sdc │ ├── pin_mapping.pin │ ├── raptor.tcl │ └── testbench.vhd ├── device_size_negative │ ├── constraints.sdc │ ├── raptor.tcl │ └── rtl │ │ └── and2.v ├── double_check │ ├── constraints.sdc │ ├── raptor.tcl │ ├── rtl │ │ └── param_up_counter.v │ └── sim_main.cpp ├── gen_clk │ ├── constraints.sdc │ ├── dut.v │ └── run_raptor.tcl ├── incr_comp │ ├── and2.v │ ├── and2_modified.v │ ├── copy.tcl │ └── raptor.tcl ├── ip_gen_axis_conv │ ├── raptor.tcl │ └── use_ip.v ├── keep_test │ ├── constraints.sdc │ ├── raptor.tcl │ └── rtl │ │ ├── and2.v │ │ └── top.v ├── lfsr │ ├── constraints.sdc │ ├── raptor.tcl │ └── top.sv ├── mult_gemini │ ├── constraints.sdc │ ├── mult.v │ └── raptor.tcl ├── oneff │ ├── constraints.sdc │ ├── dut.v │ ├── pin_mapping.pin │ ├── raptor.tcl │ ├── sim_main.cpp │ └── syn_tb.v ├── oneff_wio │ ├── constraints.sdc │ ├── dut.v │ ├── pin_mapping.pin │ ├── run_raptor.tcl │ ├── sim_main.cpp │ └── syn_tb.v ├── param_counter │ ├── constraints.sdc │ ├── raptor.tcl │ ├── rtl │ │ └── param_up_counter.v │ └── sim_main.cpp ├── partitioner_aes_verilog │ ├── Src │ │ ├── InvAddRoundKey.sv │ │ ├── InvMixCol_slice.sv │ │ ├── InvMixColumns.sv │ │ ├── InvSbox.sv │ │ ├── InvShiftRows.sv │ │ ├── InvSubBytes.sv │ │ ├── KeyExpand128.sv │ │ ├── KeyExpand192.sv │ │ ├── KeyExpand256.sv │ │ ├── KschBuffer.sv │ │ ├── MUXF7.v │ │ ├── MUXF8.v │ │ ├── RotWord.sv │ │ ├── Sbox.sv │ │ ├── SubWord.sv │ │ ├── aes_decrypt128.sv │ │ ├── aes_decrypt192.sv │ │ ├── aes_decrypt256.sv │ │ ├── decrypt.sv │ │ ├── decrypt_top.v │ │ └── gfmul.sv │ ├── constraints.sdc │ └── run_raptor.tcl ├── partitioner_and2_verilog │ ├── Src │ │ ├── and2.v │ │ └── testbench_and2.v │ ├── and2_part.xml │ ├── constraints.sdc │ ├── gtkwave.tcl │ ├── pin_mapping.pin │ ├── readme_and2_verilog.txt │ └── run_raptor.tcl ├── rom │ ├── raptor.tcl │ └── top.v ├── sasc_testcase │ ├── bitstream_annotation.xml │ ├── constraints.sdc │ ├── design_variables.yml │ ├── fabric_key.xml │ ├── fixed_sim_openfpga.xml │ ├── raptor.tcl │ ├── repack_design_constraint.xml │ └── rtl │ │ ├── config.tcl │ │ ├── sasc.v │ │ ├── sasc_brg.v │ │ ├── sasc_fifo4.v │ │ ├── sdc.json │ │ └── timescale.v ├── trivial │ ├── bottom.v │ ├── inc │ │ └── def.vh │ ├── test.tcl │ └── test.v ├── vex_soc │ ├── README.md │ ├── bare_metal_stimulus │ │ ├── Makefile │ │ ├── build │ │ │ └── src │ │ │ │ ├── crt.d │ │ │ │ └── main.d │ │ ├── libs │ │ │ └── simple.ld │ │ └── src │ │ │ ├── crt.S │ │ │ └── main.c │ ├── constraints.sdc │ ├── pin_constraints.pin │ ├── raptor_vex_100K.tcl │ ├── raptor_vex_compact.tcl │ ├── raptor_vex_no_carry.tcl │ ├── raptor_vex_soc.tcl │ ├── rtl │ │ ├── AXI_RAM_32.hex │ │ ├── VexRiscvAxi4.v │ │ ├── arbiter.v │ │ ├── axi4_interconnect.v │ │ ├── axi_interconnect.v │ │ ├── axi_ram.v │ │ ├── axi_ram_per.v │ │ ├── priority_encoder.v │ │ └── vex_soc.v │ └── sim │ │ ├── testbench.v │ │ └── verilator_tb.cpp └── xor5 │ ├── raptor_tcl.tcl │ └── rtl │ ├── private_key.pem │ └── xor5.v └── tcl_examples ├── aes_decrypt_gate ├── constraints.sdc ├── decrypt_top.v ├── raptor_cmd.tcl └── run_raptor.tcl ├── aes_decrypt_verilog ├── Src │ ├── InvAddRoundKey.sv │ ├── InvMixCol_slice.sv │ ├── InvMixColumns.sv │ ├── InvSbox.sv │ ├── InvShiftRows.sv │ ├── InvSubBytes.sv │ ├── KeyExpand128.sv │ ├── KeyExpand192.sv │ ├── KeyExpand256.sv │ ├── KschBuffer.sv │ ├── MUXF7.v │ ├── MUXF8.v │ ├── RotWord.sv │ ├── Sbox.sv │ ├── SubWord.sv │ ├── aes_decrypt128.sv │ ├── aes_decrypt192.sv │ ├── aes_decrypt256.sv │ ├── decrypt.sv │ ├── decrypt_top.v │ └── gfmul.sv ├── constraints.sdc └── run_raptor.tcl ├── and2_verilog ├── Src │ ├── and2.v │ └── testbench_and2.v ├── constraints.sdc ├── gtkwave.tcl ├── pin_mapping.pin ├── readme_and2_verilog.txt └── run_raptor.tcl ├── axi2axilite_bridge └── v1_0 │ └── axi2axilite_bridge.tcl ├── counter_verilog ├── Src │ └── counter.v ├── constraints.sdc ├── pin_mapping.pin └── run_raptor.tcl ├── counter_vhdl ├── Src │ ├── UP_COUNTER.vhd │ └── testbench.vhd ├── constraints.sdc ├── pin_mapping.pin └── run_raptor.tcl ├── oneff_verilog ├── constraints.sdc ├── dut.v ├── pin_mapping.pin ├── run_raptor.tcl ├── sim_main.cpp └── syn_tb.v ├── readme_raptor_examples.txt └── sasc_testcase ├── Src ├── sasc.v ├── sasc_brg.v ├── sasc_fifo4.v └── timescale.v ├── constraints.sdc └── run_raptor.tcl /.github/bin/run-clang-format.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Copyright 2021 The FOEDAG Team 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | FORMAT_OUT=${TMPDIR:-/tmp}/clang-format-diff.out 17 | 18 | # Run on all files except the ones that are generated. 19 | # TODO: have generator scripts run clang-format on their 20 | # output as well as last step, then we can exclude less 21 | # files here. 22 | find src -name "*.h" -o -name "*.cpp" \ 23 | | grep -v "path_to_skip" \ 24 | | xargs clang-format --style=Google -i 25 | 26 | # Check if we got any diff, then print it out in in the CI. 27 | # TODO: make these suggested diffs in the pull request. 28 | git diff > ${FORMAT_OUT} 29 | 30 | if [ -s ${FORMAT_OUT} ]; then 31 | echo "== There were changes running the formatter ==" 32 | cat ${FORMAT_OUT} 33 | echo "To locally fix, run .github/bin/run-clang-format.sh then commit and push." 34 | exit 1 35 | fi 36 | 37 | exit 0 38 | -------------------------------------------------------------------------------- /.github/pull_request_template.md: -------------------------------------------------------------------------------- 1 | > ### Motivate of the pull request 2 | > - [ ] To address an existing issue. If so, please add GH or Jira ID here: 3 | > - [ ] Breaking new feature. If so, please describe details in the description part. 4 | 5 | > ### Which submodule does this change impact ? 6 | > 7 | > - [ ] Backend 8 | > - [ ] FOEDAG_rs 9 | > - [ ] IP_Catalog 10 | > - [ ] Raptor_Tools 11 | > - [ ] yosys_verific_rs 12 | > - [ ] zephyr-rapidsi-dev 13 | > - [ ] Github CI 14 | 15 | > #### What does this pull request change? 16 | > 17 | 18 | > #### Verified that the following tests passed locally before PR was created. 19 | > - [ ] make tests/batch_all 20 | > - [ ] Describe or list testcases run specifically to verify these updates if not covered above. 21 | 22 | > ### Impact of the pull request 23 | > - [ ] Require a change on Quality of Results (QoR) 24 | > - [ ] Break back-compatibility. If so, please list who may be influenced. 25 | -------------------------------------------------------------------------------- /.github/workflows/Dockerfile: -------------------------------------------------------------------------------- 1 | FROM centos:7 2 | COPY .github/workflows/install_centos_dependencies_build.sh . 3 | RUN chmod +x install_centos_dependencies_build.sh 4 | RUN ls -la && bash install_centos_dependencies_build.sh 5 | RUN yum clean all 6 | ENV CC=/opt/rh/devtoolset-11/root/usr/bin/gcc 7 | ENV CXX=/opt/rh/devtoolset-11/root/usr/bin/g++ 8 | ENV QMAKE_CC='/opt/rh/devtoolset-11/root/usr/bin/gcc' 9 | ENV QMAKE_CXX='/opt/rh/devtoolset-11/root/usr/bin/g++' 10 | ENV PATH="/opt/python3.8/bin:/usr/local/Qt6.2.4/bin:/usr/lib/ccache:$PATH" 11 | ENV PREFIX=/tmp/raptor_gui-install 12 | ENV ADDITIONAL_CMAKE_OPTIONS='-DMY_CXX_WARNING_FLAGS="-W -Wall -Wextra -Wno-unused-parameter -Wno-unused-variable -Werror -UNDEBUG"' 13 | ENV RULE_MESSAGES=off 14 | ENV LC_ALL=en_US.utf-8 15 | ENV LANG=en_US.utf-8 16 | ENV PRODUCTION_DEVICES="" 17 | ENTRYPOINT ["/bin/bash"] 18 | -------------------------------------------------------------------------------- /.github/workflows/alert.yml: -------------------------------------------------------------------------------- 1 | name: 'Alert' 2 | on: 3 | workflow_dispatch: 4 | repository_dispatch: 5 | types: [raptor_public_update] 6 | # push: 7 | # branches: 8 | # - main 9 | jobs: 10 | alert: 11 | if: ${{ github.repository == 'os-fpga/Raptor' }} 12 | runs-on: ubuntu-latest 13 | steps: 14 | - uses: actions/checkout@v4 15 | with: 16 | ref: ${{ github.sha }} 17 | fetch-depth: '0' 18 | 19 | - name: Get Latest Commit ID 20 | run: | 21 | recent_sha=`git log -1 --pretty=format:"%h"` 22 | echo $recent_sha 23 | echo "LATEST_SHA=$recent_sha" >> $GITHUB_ENV 24 | 25 | - name: Alert 26 | uses: peter-evans/repository-dispatch@v2.1.2 27 | with: 28 | token: ${{ secrets.NEW_COMMIT_PUSHED }} 29 | repository: ${{ secrets.Alert }} 30 | event-type: raptor_public_update 31 | client-payload: '{"commitSHA": "${{ env.LATEST_SHA }}"}' 32 | -------------------------------------------------------------------------------- /.github/workflows/build_centos_image.yml: -------------------------------------------------------------------------------- 1 | name: Create and publish a CentOS 7 Docker image 2 | on: 3 | workflow_dispatch: 4 | push: 5 | paths: 6 | - .github/workflows/install_centos_dependencies_build.sh 7 | - .github/workflows/Dockerfile 8 | - .github/workflows/build_centos_image.yml 9 | env: 10 | REGISTRY: ghcr.io 11 | IMAGE_NAME: ${{ github.repository_owner }}/raptor 12 | 13 | jobs: 14 | build-and-push-image: 15 | runs-on: ubuntu-latest 16 | permissions: 17 | contents: read 18 | packages: write 19 | 20 | steps: 21 | 22 | - name: Checkout repository 23 | uses: actions/checkout@v4 24 | 25 | - name: Log in to the Container registry 26 | uses: docker/login-action@v3.0.0 27 | with: 28 | registry: ${{ env.REGISTRY }} 29 | username: ${{ github.actor }} 30 | password: ${{ secrets.GITHUB_TOKEN }} 31 | 32 | - name: Extract metadata (tags, labels) for Docker 33 | id: meta 34 | uses: docker/metadata-action@v5.0.0 35 | with: 36 | images: ${{ env.REGISTRY }}/${{ env.IMAGE_NAME }} 37 | 38 | - name: Build and push Docker image 39 | uses: docker/build-push-action@v5.0.0 40 | with: 41 | context: . 42 | file: .github/workflows/Dockerfile 43 | push: true 44 | tags: ${{ env.REGISTRY }}/${{ env.IMAGE_NAME }}:centos7latest 45 | labels: ${{ steps.meta.outputs.labels }} 46 | -------------------------------------------------------------------------------- /.github/workflows/install_litex_centos.sh: -------------------------------------------------------------------------------- 1 | # Install required dependencies for CentOS systems 2 | yum update -y 3 | yum install -y "Development Tools" 4 | yum install -y python3 which tree 5 | python3 -m pip install --upgrade pip 6 | python3 -m pip install pipenv 7 | python3 -m pip install wheel 8 | 9 | -------------------------------------------------------------------------------- /.github/workflows/install_litex_ubuntu.sh: -------------------------------------------------------------------------------- 1 | # Install required dependencies for Ubuntu systems 2 | sudo apt-get update 3 | sudo apt install -y cmake build-essential 4 | sudo apt install -y python3 python3-pip 5 | python3 -m pip install --upgrade pip 6 | python3 -m pip install pipenv wheel 7 | 8 | -------------------------------------------------------------------------------- /.github/workflows/install_macos_dependencies_build.sh: -------------------------------------------------------------------------------- 1 | # Install required dependencies for Mac OS systems 2 | brew install bison \ 3 | flex \ 4 | gawk \ 5 | libffi \ 6 | pkg-config \ 7 | bash \ 8 | readline \ 9 | ninja \ 10 | wget \ 11 | coreutils \ 12 | libusb 13 | export PATH="/usr/local/opt/qt@5/bin:$PATH" 14 | export LDFLAGS="-L/usr/local/opt/qt@5/lib" 15 | export CPPFLAGS="-I/usr/local/opt/qt@5/include" 16 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Compiled Object files 5 | *.slo 6 | *.lo 7 | *.o 8 | *.obj 9 | 10 | # Precompiled Headers 11 | *.gch 12 | *.pch 13 | 14 | # Compiled Dynamic libraries 15 | *.so 16 | *.dylib 17 | *.dll 18 | 19 | # Fortran module files 20 | *.mod 21 | *.smod 22 | 23 | # Compiled Static libraries 24 | *.lai 25 | *.la 26 | *.a 27 | *.lib 28 | 29 | # Executables 30 | *.exe 31 | *.out 32 | *.app 33 | 34 | #Raptor subfolders 35 | etc/devices/* 36 | etc/monaco-editor/ 37 | fetch_temp 38 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "yosys_verific_rs"] 2 | path = yosys_verific_rs 3 | url = https://github.com/os-fpga/yosys_verific_rs.git 4 | [submodule "FOEDAG_rs"] 5 | path = FOEDAG_rs 6 | url = https://github.com/os-fpga/FOEDAG_rs.git 7 | [submodule "tests/Jira_Testcase"] 8 | path = tests/Jira_Testcase 9 | url = https://github.com/os-fpga/Jira_Testcase.git 10 | [submodule "Backend"] 11 | path = Backend 12 | url = https://github.com/os-fpga/Backend.git 13 | [submodule "litex_reference_designs"] 14 | path = litex_reference_designs 15 | url = https://github.com/os-fpga/litex_reference_designs.git 16 | [submodule "zephyr-rapidsi-dev"] 17 | path = zephyr-rapidsi-dev 18 | url = https://github.com/os-fpga/zephyr-rapidsi-dev 19 | [submodule "Raptor_Tools"] 20 | path = Raptor_Tools 21 | url = https://github.com/os-fpga/Raptor_Tools.git 22 | [submodule "IP_Catalog"] 23 | path = IP_Catalog 24 | url = https://github.com/os-fpga/IP_Catalog.git 25 | -------------------------------------------------------------------------------- /docs/Raptor_User_Guide.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/docs/Raptor_User_Guide.pdf -------------------------------------------------------------------------------- /docs/raptor-features-screenshot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/docs/raptor-features-screenshot.png -------------------------------------------------------------------------------- /etc/Welcome_Page/WelcomeDescription.txt: -------------------------------------------------------------------------------- 1 | The industry's first and only commercial grade open-source development environment 2 | -------------------------------------------------------------------------------- /etc/Welcome_Page/WelcomeLogo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/etc/Welcome_Page/WelcomeLogo.png -------------------------------------------------------------------------------- /etc/Welcome_Page/copyrightDescription.txt: -------------------------------------------------------------------------------- 1 | Copyright © 2024 Rapid Silicon Inc. All rights reserved. 2 | -------------------------------------------------------------------------------- /etc/config.json: -------------------------------------------------------------------------------- 1 | { 2 | "general" : { 3 | "license-path" : "$HOME/.local/Rapidsilicon/raptor.lic", 4 | "user-guide" : "https://customerportal.rapidsilicon.com/hubfs/Raptor/User_Guide/Latest/Raptor_User_Guide.pdf", 5 | "release-notes" : "https://customerportal.rapidsilicon.com/hubfs/Raptor/Release_Notes/Latest/Raptor_Release_Notes.pdf" 6 | } 7 | } 8 | -------------------------------------------------------------------------------- /etc/copyright.txt: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | Copyright (c) 2022-2024 Rapid Silicon 3 | This source code contains proprietary information belonging to Rapid Silicon 4 | (the "licensor") released under license and non-disclosure agreement to the 5 | recipient (the "licensee"). 6 | 7 | The information shared and protected by the license and non-disclosure agreement 8 | includes but is not limited to the following: 9 | * operational algorithms of the product 10 | * logos, graphics, source code, and visual presentation of the product 11 | * confidential operational information of the licensor 12 | 13 | The recipient of this source code is NOT permitted to publicly disclose, 14 | re-use, archive beyond the period of the license agreement, transfer to a 15 | sub-licensee, or re-implement any portion of the content covered by the license 16 | and non-disclosure agreement without the prior written consent of the licensor. 17 | *********************************************************************************/ 18 | -------------------------------------------------------------------------------- /etc/devices/custom_layout_template.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /etc/devices/mpw1/bitstream_annotation_empty.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /etc/devices/mpw1/fixed_sim_openfpga.xml: -------------------------------------------------------------------------------- 1 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | -------------------------------------------------------------------------------- /etc/devices/mpw1/power/bcpu.json: -------------------------------------------------------------------------------- 1 | { 2 | "type": "bcpu", 3 | "coeffs": [ 4 | { "name": "BCPU_CLK_FACTOR" , "value": 0.0000321306659727 }, 5 | { "name": "BCPU_LOW_LOAD_FACTOR" , "value": 6.22030740524698E-06 }, 6 | { "name": "BCPU_MEDIUM_LOAD_FACTOR", "value": 7.03786731129023E-06 }, 7 | { "name": "BCPU_HIGH_LOAD_FACTOR" , "value": 0.0000105978995482262 } 8 | ], 9 | "static_power": [ 10 | { 11 | "rail_type": "Vcc_core (Config)", 12 | "domain": "SOC", 13 | "scenarios": [ 14 | { "type": "worse", "coeffs": [0.0000000001, -0.000000002, 0.000000004, 0.00002, 0.0007], "factor": 1.0 }, 15 | { "type": "typical", "coeffs": [0.0000000000005, -0.00000000002, 0.000000003, 0.0000002, 0.00001, 0.0013], "factor": 1.0 } 16 | ] 17 | } 18 | ] 19 | } 20 | -------------------------------------------------------------------------------- /etc/devices/mpw1/power/clocking.json: -------------------------------------------------------------------------------- 1 | { 2 | "type": "clocking", 3 | "coeffs": [ 4 | { "name": "CLK_CAP" , "value": 0.00001 }, 5 | { "name": "CLK_INT_CAP", "value": 0.00000003 }, 6 | { "name": "PLL_INT" , "value": 0.0009 }, 7 | { "name": "PLL_AUX" , "value": 0.01 } 8 | ], 9 | "static_power": [ 10 | { 11 | "rail_type": "Vcc_aux", 12 | "domain": "SOC", 13 | "scenarios": [ 14 | { "type": "worse", "coeffs": [0.00000001, -0.0000003, 0.00004, 0.0332], "factor": 0.555555555555556 }, 15 | { "type": "worse", "coeffs": [0.000000002, 0.0000004, 0.00002, 0.0133], "factor": 0.555555555555556 }, 16 | { "type": "typical", "coeffs": [0.000000003, 0.0000002, 0.00004, 0.0224], "factor": 0.555555555555556 }, 17 | { "type": "typical", "coeffs": [0.0000000004, 0.0000001, 0.000005, 0.0033], "factor": 0.555555555555556 } 18 | ] 19 | } 20 | ] 21 | } 22 | -------------------------------------------------------------------------------- /etc/devices/mpw1/power/fabric_le.json: -------------------------------------------------------------------------------- 1 | { 2 | "type": "fabric_le", 3 | "coeffs": [ 4 | { "name": "LUT_CAP" , "value": 0.0000003 }, 5 | { "name": "FF_CAP" , "value": 0.00000035 }, 6 | { "name": "FF_CLK_CAP" , "value": 2.91375291375291E-09 }, 7 | { "name": "LUT_INT_CAP", "value": 0.00000002 }, 8 | { "name": "FF_INT_CAP" , "value": 0.00000004 } 9 | ], 10 | "static_power": [ 11 | { 12 | "rail_type": "Vcc_core (CLB)", 13 | "domain": "Core", 14 | "scenarios": [ 15 | { "type": "worse", "coeffs": [0.000000000000002, -0.0000000000001, 0.00000000001, 0.0000000008, 0.00000006, 0.000002], "factor": 1.0 }, 16 | { "type": "typical", "coeffs": [0.0000000000003, -0.00000000001, 0.0000000001, 0.00000006, 0.0000007], "factor": 1.0 } 17 | ] 18 | } 19 | ] 20 | } 21 | -------------------------------------------------------------------------------- /etc/devices/mpw1/power/power_data.json: -------------------------------------------------------------------------------- 1 | { 2 | "components": [ 3 | { "$ref": "bcpu.json" }, 4 | { "$ref": "clocking.json" }, 5 | { "$ref": "fabric_le.json" }, 6 | { "$ref": "io.json" }, 7 | { "$ref": "noc.json" }, 8 | { "$ref": "puffcc.json" }, 9 | { "$ref": "qspi.json" }, 10 | { "$ref": "rc_osc.json" }, 11 | { "$ref": "regulator.json" }, 12 | { "$ref": "sram.json" } 13 | ] 14 | } 15 | -------------------------------------------------------------------------------- /etc/devices/mpw1/power/puffcc.json: -------------------------------------------------------------------------------- 1 | { 2 | "type": "puffcc", 3 | "static_power": [ 4 | { 5 | "rail_type": "VCC_PUF", 6 | "domain": "SOC", 7 | "scenarios": [ 8 | { "type": "worse", "coeffs": [0.001], "factor": 0.555555555555556 }, 9 | { "type": "typical", "coeffs": [0.0005], "factor": 0.555555555555556 } 10 | ] 11 | } 12 | ] 13 | } 14 | -------------------------------------------------------------------------------- /etc/devices/mpw1/power/qspi.json: -------------------------------------------------------------------------------- 1 | { 2 | "type": "spi", 3 | "coeffs": [ 4 | { "name": "QSPI_CLK_FACTOR" , "value": 0.0000154995864661654 }, 5 | { "name": "QSPI_SWITCHING_FACTOR", "value": 0.00156512937507589 }, 6 | { "name": "QSPI_IO_FACTOR" , "value": 0.0001270766 } 7 | ] 8 | } 9 | -------------------------------------------------------------------------------- /etc/devices/mpw1/power/rc_osc.json: -------------------------------------------------------------------------------- 1 | { 2 | "type": "rc_osc", 3 | "static_power": [ 4 | { 5 | "rail_type": "VCC_RC_OSC", 6 | "domain": "SOC", 7 | "scenarios": [ 8 | { "type": "worse", "coeffs": [0.0005], "factor": 0.555555555555556 }, 9 | { "type": "typical", "coeffs": [0.0001], "factor": 0.555555555555556 } 10 | ] 11 | } 12 | ] 13 | } 14 | -------------------------------------------------------------------------------- /etc/devices/mpw1/power/regulator.json: -------------------------------------------------------------------------------- 1 | { 2 | "type": "regulator", 3 | "coeffs": [ 4 | { "name": "VCC_CORE" , "value": 0.8 }, 5 | { "name": "VCC_AUX" , "value": 1.8 }, 6 | { "name": "VCC_BOOT_IO" , "value": 1.8 }, 7 | { "name": "VCC_DDR_IO" , "value": 0.8 }, 8 | { "name": "VCC_SOC_IO" , "value": 1.8 }, 9 | { "name": "VCC_GBE_IO" , "value": 0.8 }, 10 | { "name": "VCC_USB_IO" , "value": 0.8 }, 11 | { "name": "VCC_BOOT_AUX", "value": 1.8 }, 12 | { "name": "VCC_SOC_AUX" , "value": 1.8 }, 13 | { "name": "VCC_GBE_AUX" , "value": 1.8 }, 14 | { "name": "VCC_USB_AUX" , "value": 1.8 }, 15 | { "name": "VCC_PUF" , "value": 1.8 }, 16 | { "name": "VCC_RC_OSC" , "value": 1.8 } 17 | ] 18 | } 19 | -------------------------------------------------------------------------------- /etc/devices/mpw1/power/sram.json: -------------------------------------------------------------------------------- 1 | { 2 | "type": "sram", 3 | "coeffs": [ 4 | { "name": "SRAM_ACLK_FACTOR" , "value": 0.0000688892039916618 }, 5 | { "name": "SRAM_WRITE_FACTOR", "value": 0.000142810846268152 }, 6 | { "name": "SRAM_READ_FACTOR" , "value": 0.000140428615087023 } 7 | ] 8 | } 9 | -------------------------------------------------------------------------------- /etc/devices/mpw1/repack_design_constraint.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /etc/settings/messages/suppress-rel.json: -------------------------------------------------------------------------------- 1 | { 2 | "suppress" : [ 3 | "unconnected pin in architecture", 4 | "transistor to minimum width", 5 | "had no out-going switches", 6 | "has no fanin", 7 | "Found no more sample locations for", 8 | ": Model " 9 | ] 10 | } 11 | -------------------------------------------------------------------------------- /etc/settings/messages/suppress.json: -------------------------------------------------------------------------------- 1 | { 2 | "suppress" : [ 3 | 4 | ] 5 | } 6 | -------------------------------------------------------------------------------- /etc/vpr_e.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/etc/vpr_e.bin -------------------------------------------------------------------------------- /examples/AES_DECRYPT/AES_DECRYPT.srcs/constrs_1/aes_decrypt.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | create_clock -period 2.5 clk 3 | -------------------------------------------------------------------------------- /examples/AES_DECRYPT/AES_DECRYPT.srcs/sources_1/InvAddRoundKey.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module InvAddRoundKey( 4 | input [0:127] din0, 5 | input [0:127] din1, 6 | input [0:127] rkey, 7 | input S, 8 | output [0:127] dout); 9 | 10 | logic [0:127] tmp; 11 | 12 | always_comb 13 | tmp <= S? din1 : din0; 14 | 15 | assign dout = tmp ^ rkey; 16 | endmodule -------------------------------------------------------------------------------- /examples/AES_DECRYPT/AES_DECRYPT.srcs/sources_1/generic_muxfx.v: -------------------------------------------------------------------------------- 1 | // Technology independent version of MUXF7 and MUXF8. 2 | // 3 | // This file should not be included while targeting Xilinx so that 4 | // the MUXF7/MUXF8 primitives in the Xilinx simulation/synthesis 5 | // will be used instead. 6 | module MUXF7 (output O, input I0, input I1, input S); 7 | assign O = (S)? I1 : I0; 8 | endmodule 9 | 10 | module MUXF8 (output O, input I0, input I1, input S); 11 | assign O = (S)? I1 : I0; 12 | endmodule -------------------------------------------------------------------------------- /examples/AES_DECRYPT/AES_DECRYPT.srcs/sources_1/wrapper.v: -------------------------------------------------------------------------------- 1 | // Dirty wrapper necessary to decrease the number of pins to fit gemini 2 | module wrapper (input [0:127] ct, 3 | input ct_vld, 4 | output ct_rdy, 5 | 6 | input rkey_vld, 7 | output next_rkey, 8 | 9 | output [0:127] pt, 10 | output pt_vld, 11 | 12 | input [0:1] klen_sel, 13 | 14 | input clk, 15 | input rst); 16 | 17 | 18 | decrypt U1 ( 19 | ct, 20 | ct_vld, 21 | ct_rdy, 22 | 23 | ct , 24 | rkey_vld, 25 | next_rkey, 26 | 27 | pt, 28 | pt_vld, 29 | 30 | klen_sel, 31 | 32 | clk, 33 | rst 34 | ); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /examples/AES_DECRYPT/run_1/AES_DECRYPT.srcs/constrs_1/aes_decrypt.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | create_clock -period 2.5 clk 3 | -------------------------------------------------------------------------------- /examples/AES_DECRYPT/run_1/AES_DECRYPT.srcs/sources_1/InvAddRoundKey.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module InvAddRoundKey( 4 | input [0:127] din0, 5 | input [0:127] din1, 6 | input [0:127] rkey, 7 | input S, 8 | output [0:127] dout); 9 | 10 | logic [0:127] tmp; 11 | 12 | always_comb 13 | tmp <= S? din1 : din0; 14 | 15 | assign dout = tmp ^ rkey; 16 | endmodule -------------------------------------------------------------------------------- /examples/AES_DECRYPT/run_1/AES_DECRYPT.srcs/sources_1/generic_muxfx.v: -------------------------------------------------------------------------------- 1 | // Technology independent version of MUXF7 and MUXF8. 2 | // 3 | // This file should not be included while targeting Xilinx so that 4 | // the MUXF7/MUXF8 primitives in the Xilinx simulation/synthesis 5 | // will be used instead. 6 | module MUXF7 (output O, input I0, input I1, input S); 7 | assign O = (S)? I1 : I0; 8 | endmodule 9 | 10 | module MUXF8 (output O, input I0, input I1, input S); 11 | assign O = (S)? I1 : I0; 12 | endmodule -------------------------------------------------------------------------------- /examples/AES_DECRYPT/run_1/AES_DECRYPT.srcs/sources_1/wrapper.v: -------------------------------------------------------------------------------- 1 | // Dirty wrapper necessary to decrease the number of pins to fit gemini 2 | module wrapper (input [0:127] ct, 3 | input ct_vld, 4 | output ct_rdy, 5 | 6 | input rkey_vld, 7 | output next_rkey, 8 | 9 | output [0:127] pt, 10 | output pt_vld, 11 | 12 | input [0:1] klen_sel, 13 | 14 | input clk, 15 | input rst); 16 | 17 | 18 | decrypt U1 ( 19 | ct, 20 | ct_vld, 21 | ct_rdy, 22 | 23 | ct , 24 | rkey_vld, 25 | next_rkey, 26 | 27 | pt, 28 | pt_vld, 29 | 30 | klen_sel, 31 | 32 | clk, 33 | rst 34 | ); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /examples/AES_DECRYPT/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Placement.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Placement":{"pin_selection_radiobtn":{"userValue":"In Define Order"}}}} -------------------------------------------------------------------------------- /examples/AES_DECRYPT/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Timing Analysis.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Timing Analysis":{"engine_radiobtn":{"userValue":"Tatum"}}}} -------------------------------------------------------------------------------- /examples/AES_DECRYPT/run_1/synth_1_1/synth_1_1_settings/Tasks_Synthesis.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Synthesis":{"dsp_spinbox_ex":{"userValue":176},"bram_spinbox_ex":{"userValue":176},"carry_chain_spinbox_ex":{"userValue":528}}}} -------------------------------------------------------------------------------- /examples/and2_gemini/and2_gemini.settings/Tasks_Placement.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Placement":{"pin_selection_radiobtn":{"userValue":"In Define Order"}}}} -------------------------------------------------------------------------------- /examples/and2_gemini/and2_gemini.settings/Tasks_Synthesis.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Synthesis":{"bram_spinbox_ex":{"userValue":176},"dsp_spinbox_ex":{"userValue":176},"carry_chain_spinbox_ex":{"userValue":528}}}} -------------------------------------------------------------------------------- /examples/and2_gemini/and2_gemini.settings/Tasks_Timing Analysis.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Timing Analysis":{"engine_radiobtn":{"userValue":"Tatum"}}}} -------------------------------------------------------------------------------- /examples/and2_gemini/and2_gemini.srcs/constrs_1/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 200 MHz (5nS period) 4 | create_clock -period 5 clk 5 | set_input_delay -max 0 -clock clk [get_ports {a}] 6 | set_input_delay -max 0 -clock clk [get_ports {b}] 7 | set_input_delay -max 0 -clock clk [get_ports {reset}] 8 | set_output_delay -max 0 -clock clk [get_ports {c}] 9 | 10 | -------------------------------------------------------------------------------- /examples/and2_gemini/and2_gemini.srcs/sources_1/and2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // and2_verilog // 5 | // and2.v - Top-level file of simple 2-input AND gate // 6 | //////////////////////////////////////////////////////// 7 | 8 | module and2 ( 9 | input a, 10 | input b, 11 | input clk, 12 | input reset, 13 | output reg c = 1'b0 14 | ); 15 | 16 | reg a_reg, b_reg = 1'b0; 17 | 18 | always@(posedge clk) 19 | if (reset) begin 20 | a_reg <= 1'b0; 21 | b_reg <= 1'b0; 22 | c <= 1'b0; 23 | end else begin 24 | a_reg <= a; 25 | b_reg <= b; 26 | c <= a_reg & b_reg; 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /examples/and2_gemini/run_1/and2_gemini.srcs/constrs_1/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 200 MHz (5nS period) 4 | create_clock -period 5 clk 5 | set_input_delay -max 0 -clock clk [get_ports {a}] 6 | set_input_delay -max 0 -clock clk [get_ports {b}] 7 | set_input_delay -max 0 -clock clk [get_ports {reset}] 8 | set_output_delay -max 0 -clock clk [get_ports {c}] 9 | 10 | -------------------------------------------------------------------------------- /examples/and2_gemini/run_1/and2_gemini.srcs/sources_1/and2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // and2_verilog // 5 | // and2.v - Top-level file of simple 2-input AND gate // 6 | //////////////////////////////////////////////////////// 7 | 8 | module and2 ( 9 | input a, 10 | input b, 11 | input clk, 12 | input reset, 13 | output reg c = 1'b0 14 | ); 15 | 16 | reg a_reg, b_reg = 1'b0; 17 | 18 | always@(posedge clk) 19 | if (reset) begin 20 | a_reg <= 1'b0; 21 | b_reg <= 1'b0; 22 | c <= 1'b0; 23 | end else begin 24 | a_reg <= a; 25 | b_reg <= b; 26 | c <= a_reg & b_reg; 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /examples/and2_gemini/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Placement.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Placement":{"pin_selection_radiobtn":{"userValue":"In Define Order"}}}} -------------------------------------------------------------------------------- /examples/and2_gemini/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Timing Analysis.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Timing Analysis":{"engine_radiobtn":{"userValue":"Tatum"}}}} -------------------------------------------------------------------------------- /examples/and2_gemini/run_1/synth_1_1/synth_1_1_settings/Tasks_Synthesis.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Synthesis":{"dsp_spinbox_ex":{"userValue":176},"carry_chain_spinbox_ex":{"userValue":528},"bram_spinbox_ex":{"userValue":176}}}} -------------------------------------------------------------------------------- /examples/incr_comp/incr_comp.srcs/sources_1/tmp.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | one, 9 | sec, 10 | s); 11 | 12 | input wire one; 13 | input wire sec; 14 | output wire s; 15 | 16 | assign s = one & sec; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /examples/incr_comp/run_1/incr_comp.srcs/sources_1/tmp.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | one, 9 | sec, 10 | s); 11 | 12 | input wire one; 13 | input wire sec; 14 | output wire s; 15 | 16 | assign s = one & sec; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /examples/incr_comp/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Placement.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Placement":{"pin_selection_radiobtn":{"userValue":"In Define Order"}}}} -------------------------------------------------------------------------------- /examples/incr_comp/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Timing Analysis.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Timing Analysis":{"engine_radiobtn":{"userValue":"Tatum"}}}} -------------------------------------------------------------------------------- /examples/incr_comp/run_1/synth_1_1/synth_1_1_settings/Tasks_Synthesis.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Synthesis":{"bram_spinbox_ex":{"userValue":176},"dsp_spinbox_ex":{"userValue":176},"carry_chain_spinbox_ex":{"userValue":528}}}} -------------------------------------------------------------------------------- /examples/sasc_testcase/run_1/sasc_testcase.srcs/constrs_1/constraints.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 7.935999999999999 clk 2 | set_input_delay 1 -clock clk [get_ports {*}] 3 | set_output_delay 1 -clock clk [get_ports {*}] 4 | 5 | -------------------------------------------------------------------------------- /examples/sasc_testcase/run_1/sasc_testcase.srcs/sources_1/config.tcl: -------------------------------------------------------------------------------- 1 | set ::env(PROJECT_NAME) sasc 2 | set ::env(DESIGN_TOP) sasc 3 | set ::env(DESIGN_DIR) RTL_Benchmark/Verilog/iwls2005_designs/sasc/rtl 4 | set ::env(TOP_VERILOG) RTL_Benchmark/Verilog/iwls2005_designs/sasc/rtl/sasc.v 5 | set ::env(CLOCK_COUNT) 1 6 | set ::env(DOMAIN) controller 7 | -------------------------------------------------------------------------------- /examples/sasc_testcase/run_1/sasc_testcase.srcs/sources_1/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | -------------------------------------------------------------------------------- /examples/sasc_testcase/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Placement.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Placement":{"pin_selection_radiobtn":{"userValue":"In Define Order"}}}} -------------------------------------------------------------------------------- /examples/sasc_testcase/run_1/synth_1_1/impl_1_1_1/impl_1_1_1_settings/Tasks_Timing Analysis.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Timing Analysis":{"engine_radiobtn":{"userValue":"Tatum"}}}} -------------------------------------------------------------------------------- /examples/sasc_testcase/run_1/synth_1_1/synth_1_1_settings/Tasks_Synthesis.json: -------------------------------------------------------------------------------- 1 | {"Tasks":{"Synthesis":{"dsp_spinbox_ex":{"userValue":176},"bram_spinbox_ex":{"userValue":176},"carry_chain_spinbox_ex":{"userValue":528}}}} -------------------------------------------------------------------------------- /examples/sasc_testcase/sasc_testcase.srcs/constrs_1/constraints.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 7.935999999999999 clk 2 | set_input_delay 1 -clock clk [get_ports {*}] 3 | set_output_delay 1 -clock clk [get_ports {*}] 4 | 5 | -------------------------------------------------------------------------------- /examples/sasc_testcase/sasc_testcase.srcs/sources_1/config.tcl: -------------------------------------------------------------------------------- 1 | set ::env(PROJECT_NAME) sasc 2 | set ::env(DESIGN_TOP) sasc 3 | set ::env(DESIGN_DIR) RTL_Benchmark/Verilog/iwls2005_designs/sasc/rtl 4 | set ::env(TOP_VERILOG) RTL_Benchmark/Verilog/iwls2005_designs/sasc/rtl/sasc.v 5 | set ::env(CLOCK_COUNT) 1 6 | set ::env(DOMAIN) controller 7 | -------------------------------------------------------------------------------- /examples/sasc_testcase/sasc_testcase.srcs/sources_1/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | -------------------------------------------------------------------------------- /licenses/agpl-1.0.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/licenses/agpl-1.0.xml -------------------------------------------------------------------------------- /licenses/bsd-3-clause-no-nuclear-license-2014.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/licenses/bsd-3-clause-no-nuclear-license-2014.xml -------------------------------------------------------------------------------- /licenses/cecill-1.1.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/licenses/cecill-1.1.xml -------------------------------------------------------------------------------- /licenses/cecill-2.1.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/licenses/cecill-2.1.xml -------------------------------------------------------------------------------- /licenses/cecill-c.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/licenses/cecill-c.xml -------------------------------------------------------------------------------- /licenses/condor-1.1.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/licenses/condor-1.1.xml -------------------------------------------------------------------------------- /licenses/ibm-pibs.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 5 | 6 | http://git.denx.de/?p=u-boot.git;a=blob;f=arch/powerpc/cpu/ppc4xx/miiphy.c;h=297155fdafa064b955e53e9832de93bfb0cfb85b;hb=9fab4bf4cc077c21e43941866f3f2c196f28670d 7 | 8 | 9 | 10 |

This source code has been made available to you by IBM on an AS-IS basis. Anyone receiving this source is 11 | licensed under IBM copyrights to use it in any way he or she deems fit, including copying it, 12 | modifying it, compiling it, and redistributing it either with or without modifications. No license 13 | under IBM patents or patent applications is to be implied by the copyright license.

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Any user of this software should understand that IBM cannot provide technical support for this software 15 | and will not be responsible for any consequences resulting from the use of this software.

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Any person who transfers this source code or any derivative work must include the IBM copyright notice, 17 | this paragraph, and the preceding two paragraphs in the transferred software.

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COPYRIGHT I B M CORPORATION 2002 19 |
LICENSED MATERIAL - PROGRAM PROPERTY OF I B M 20 |

21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /licenses/interbase-1.0.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/licenses/interbase-1.0.xml -------------------------------------------------------------------------------- /licenses/noassertion.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/licenses/noassertion.xml -------------------------------------------------------------------------------- /ql_to_rs.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | sed -i "s/ql_/rs_/g" ./etc/devices/gemini/gemini_openfpga.xml 3 | sed -i "s/ql_/rs_/g" ./etc/devices/gemini/gemini_vpr.xml 4 | sed -i "s/ql_/rs_/g" ./etc/devices/gemini/bitstream_annotation.xml 5 | sed -i "s/ql_/rs_/g" ./tests/Arch/bitstream_annotation.xml 6 | sed -i "s/QL_/RS_/g" ./etc/devices/gemini/gemini_openfpga.xml 7 | sed -i "s/QL_/RS_/g" ./etc/devices/gemini/gemini_vpr.xml 8 | sed -i "s/QL_/RS_/g" ./etc/devices/gemini/bitstream_annotation.xml 9 | sed -i "s/QL_/RS_/g" ./tests/Arch/bitstream_annotation.xml 10 | -------------------------------------------------------------------------------- /raptor_version.h.in: -------------------------------------------------------------------------------- 1 | #define STR_VALUE(arg) #arg 2 | #define TO_C_STR(str) STR_VALUE(str) 3 | #define FOEDAG_BUILD @VERSION_MAJOR@.@VERSION_MINOR@.@VERSION_PATCH@ 4 | #define FOEDAG_GIT_HASH @GIT_HASH@ 5 | #define FOEDAG_BUILD_TYPE @BUILD_TYPE_STRING@ 6 | #define RELEASE_VERSION @RELEASE_VERSION@ 7 | #define FOEDAG_VERSION_COMPAT @VERSION_MAJOR_COM@.@VERSION_MINOR_COM@.@VERSION_PATCH_COM@ 8 | -------------------------------------------------------------------------------- /src/ConfigurationRaptor/CFGDeviceDatabase/CFGDeviceDatabase.h: -------------------------------------------------------------------------------- 1 | #ifndef CFGDeviceDatabase_H 2 | #define CFGDeviceDatabase_H 3 | 4 | #include "nlohmann_json/json.hpp" 5 | 6 | #endif 7 | -------------------------------------------------------------------------------- /src/ConfigurationRaptor/CFGDeviceDatabase/Virgo/routing_library/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/src/ConfigurationRaptor/CFGDeviceDatabase/Virgo/routing_library/__init__.py -------------------------------------------------------------------------------- /src/ConfigurationRaptor/CFGDeviceDatabase/Virgo/routing_library/function_library.py: -------------------------------------------------------------------------------- 1 | import os 2 | import sys 3 | current_dir = os.path.dirname(os.path.abspath(__file__)) 4 | if current_dir not in sys.path: 5 | sys.path.insert(0, current_dir) 6 | 7 | def get_gbox_top_name(index) : 8 | 9 | pn = "P" if (index % 2) == 0 else "N" 10 | return "gearbox_%s[%d]" % (pn, index//2) 11 | 12 | def get_location(type, bank, index) : 13 | 14 | pn = "P" if (index % 2) == 0 else "N" 15 | if index in [18, 19, 38, 39] : 16 | return "H%s_%d_CC_%d_%d%s" % (type, bank, index, index//2, pn) 17 | else : 18 | return "H%s_%d_%d_%d%s" % (type, bank, index, index//2, pn) 19 | -------------------------------------------------------------------------------- /src/ConfigurationRaptor/CFGDeviceDatabase/Virgo/routing_library/gbox_fclk_mux.py: -------------------------------------------------------------------------------- 1 | # Block 2 | create_block(name="gbox_fclk_mux") 3 | 4 | # Ports 5 | add_port(name="vco_clk", dir=DIR_IN, bit=2) 6 | add_port(name="rx_io_clk", dir=DIR_IN, bit=2) 7 | add_port(name="fast_clk", dir=DIR_OUT, bit=1) 8 | 9 | # Config 10 | add_config_mux(out="fast_clk", 11 | selection={0b000 : "vco_clk[0]", 12 | 0b001 : "vco_clk[1]", 13 | 0b100 : "rx_io_clk[0]", 14 | 0b110 : "rx_io_clk[1]"}, 15 | bits=[{"vco_clk_sel" : 1}, 16 | {"rx_fclkio_sel" : 1}, 17 | {"rxclk_phase_sel":1}]) 18 | -------------------------------------------------------------------------------- /src/ConfigurationRaptor/CFGDeviceDatabase/Virgo/routing_library/gbox_osc.py: -------------------------------------------------------------------------------- 1 | # Block 2 | create_block(name="rc_osc_50mhz") 3 | 4 | # Ports 5 | add_port(name="osc", dir=DIR_IN) 6 | add_port(name="o_osc", dir=DIR_OUT) 7 | 8 | # Connections 9 | add_connection(source="osc", destinations=["o_osc"]) 10 | -------------------------------------------------------------------------------- /src/ConfigurationRaptor/CFGDeviceDatabase/Virgo/routing_library/gbox_root_bank_clkmux.py: -------------------------------------------------------------------------------- 1 | # Block 2 | create_block(name="gbox_root_bank_clkmux") 3 | 4 | # Ports 5 | add_port(name="core_clk_in", dir=DIR_IN, bit=40) 6 | add_port(name="cdr_clk_in", dir=DIR_IN, bit=40) 7 | add_port(name="core_clk", dir=DIR_OUT, bit=2) 8 | add_port(name="cdr_clk", dir=DIR_OUT, bit=2) 9 | 10 | # Config 11 | core_clk_selection_A = {} 12 | core_clk_selection_B = {} 13 | cdr_clk_selection_A = {} 14 | cdr_clk_selection_B = {} 15 | for i in range(20) : 16 | core_clk_selection_A[i] = "core_clk_in[%d]" % i 17 | core_clk_selection_B[i] = "core_clk_in[%d]" % (20 + i) 18 | cdr_clk_selection_A[i] = "cdr_clk_in[%d]" % i 19 | cdr_clk_selection_B[i] = "cdr_clk_in[%d]" % (20 + i) 20 | add_config_mux(out="core_clk[0]", 21 | selection=core_clk_selection_A, 22 | bits=[{"CORE_CLK_ROOT_SEL_A" : 5}]) 23 | add_config_mux(out="core_clk[1]", 24 | selection=core_clk_selection_B, 25 | bits=[{"CORE_CLK_ROOT_SEL_B" : 5}]) 26 | add_config_mux(out="cdr_clk[0]", 27 | selection=cdr_clk_selection_A, 28 | bits=[{"CDR_CLK_ROOT_SEL_A" : 5}]) 29 | add_config_mux(out="cdr_clk[1]", 30 | selection=cdr_clk_selection_B, 31 | bits=[{"CDR_CLK_ROOT_SEL_B" : 5}]) -------------------------------------------------------------------------------- /src/ConfigurationRaptor/CFGDeviceDatabase/Virgo/routing_library/gbox_top.py: -------------------------------------------------------------------------------- 1 | # Block 2 | create_block(name="gbox_top") 3 | 4 | # Ports 5 | add_port(name="fast_clk", dir=DIR_IN) 6 | add_port(name="rx_in", dir=DIR_IN) 7 | add_port(name="core_clk", dir=DIR_OUT) 8 | add_port(name="cdr_clk", dir=DIR_OUT) 9 | add_port(name="tx_clk", dir=DIR_OUT) 10 | 11 | # Connections 12 | add_connection(source="fast_clk", destinations=["cdr_clk"]) 13 | 14 | # Config 15 | add_config_mux(out="core_clk", 16 | selection={ 17 | 0 : "fast_clk", 18 | 1 : "rx_in" 19 | }, 20 | bits=[{"RX_CLOCK_IO" : 1}]) 21 | add_config_mux(out="tx_clk", 22 | selection={ 23 | 1 : "fast_clk" 24 | }, 25 | bits=[{"TX_CLOCK_IO" : 1}]) 26 | -------------------------------------------------------------------------------- /src/ConfigurationRaptor/CFGDeviceDatabase/gearbox_block_diagrams/1vg28/PLL.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/src/ConfigurationRaptor/CFGDeviceDatabase/gearbox_block_diagrams/1vg28/PLL.gv.pdf -------------------------------------------------------------------------------- /src/ConfigurationRaptor/CFGDeviceDatabase/gearbox_block_diagrams/1vg28/Virgo.gv.pdf: -------------------------------------------------------------------------------- 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See the 16 | GNU General Public License for more details. 17 | 18 | You should have received a copy of the GNU General Public License 19 | along with this program. If not, see . 20 | */ 21 | #pragma once 22 | 23 | #include "PinAssignment/PackagePinsLoader.h" 24 | 25 | namespace FOEDAG { 26 | 27 | class MPW1Loader : public PackagePinsLoader { 28 | public: 29 | MPW1Loader(PackagePinsModel *model, QObject *parent = nullptr); 30 | std::pair load(const QString &fileName) override; 31 | }; 32 | 33 | } // namespace FOEDAG 34 | -------------------------------------------------------------------------------- /src/raptorenv_lin64.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Raptor environment setup script - 64-bit Linux 3 | # Copyright(c) 2022 Rapid Silicon 4 | # All licenses available in $RAPTOR_PATH/share/raptor/licenses 5 | # Version 1.0 6 | 7 | RETURN_PATH=`pwd` 8 | SCRIPT_PATH=`dirname $BASH_SOURCE` 9 | RAPTOR_PATH=`( cd "$SCRIPT_PATH" && pwd )` 10 | 11 | if [ -n "${PATH}" ]; then 12 | export PATH=$RAPTOR_PATH/bin:$PATH 13 | else 14 | export PATH=$RAPTOR_PATH/bin 15 | fi 16 | -------------------------------------------------------------------------------- /src/to_be_raptor_checker: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Raptor checker environment setup script - 64-bit Linux 3 | # Copyright(c) 2021-2024 Rapid Silicon 4 | # All licenses available in $RAPTOR_PATH/share/raptor/licenses 5 | # Version 1.0 6 | 7 | RETURN_PATH=`pwd` 8 | SCRIPT_PATH=`dirname $BASH_SOURCE` 9 | RAPTOR_PATH=`( cd "$SCRIPT_PATH" && pwd )` 10 | 11 | [ -f $RAPTOR_PATH/../.raptorenv_lin64.sh ] && source $RAPTOR_PATH/../.raptorenv_lin64.sh 12 | [ -f $RAPTOR_PATH/bin/default_lic_path ] && source $RAPTOR_PATH/bin/default_lic_path 13 | 14 | CHECKER_EXE=planning 15 | 16 | $RAPTOR_PATH/bin/$CHECKER_EXE "$@" 17 | -------------------------------------------------------------------------------- /src/to_be_raptor_linx: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Raptor environment setup script - 64-bit Linux 3 | # Copyright(c) 2021-2024 Rapid Silicon 4 | # All licenses available in $RAPTOR_PATH/share/raptor/licenses 5 | # Version 1.0 6 | 7 | RETURN_PATH=`pwd` 8 | SCRIPT_PATH=`dirname $BASH_SOURCE` 9 | RAPTOR_PATH=`( cd "$SCRIPT_PATH" && pwd )` 10 | 11 | [ -f $RAPTOR_PATH/../.raptorenv_lin64.sh ] && source $RAPTOR_PATH/../.raptorenv_lin64.sh 12 | [ -f $RAPTOR_PATH/bin/default_lic_path ] && source $RAPTOR_PATH/bin/default_lic_path 13 | 14 | 15 | iswsl() { 16 | if [[ -s /etc/wsl.conf ]] || \ 17 | grep -qi "wsl2" /proc/version || \ 18 | uname -r | grep -qi "wsl2" || \ 19 | [ -n "$WSL_DISTRO_NAME" ] || \ 20 | which powershell.exe &> /dev/null; then 21 | echo "WSL" 22 | else 23 | echo "" 24 | fi 25 | } 26 | 27 | # Function to detect the environment 28 | detect_environment() { 29 | # Check if running inside WSL 30 | result=$(iswsl) 31 | if [ "$result" == "WSL" ]; then 32 | echo "WSL" 33 | # Check if running inside Docker 34 | elif [ -f "/.dockerenv" ]; then 35 | echo "Docker" 36 | # Assume native Linux 37 | else 38 | echo "Native" 39 | fi 40 | } 41 | 42 | environment=$(detect_environment) 43 | if [ "$environment" == "Native" ]; then 44 | RAPTOR_EXE=raptor.mexe 45 | else 46 | RAPTOR_EXE=raptor.exe 47 | fi 48 | 49 | $RAPTOR_PATH/bin/$RAPTOR_EXE "$@" 50 | 51 | 52 | -------------------------------------------------------------------------------- /tests/Arch/bitstream_annotation.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /tests/Arch/bitstream_annotation_empty.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /tests/Arch/fixed_sim_openfpga.xml: -------------------------------------------------------------------------------- 1 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | -------------------------------------------------------------------------------- /tests/Arch/repack_design_constraint.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /tests/Build/cache_104x68/Src/and2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // and2_verilog // 5 | // and2.v - Top-level file of simple 2-input AND gate // 6 | //////////////////////////////////////////////////////// 7 | 8 | module and2 ( 9 | input a, 10 | input b, 11 | input clk, 12 | input reset, 13 | output reg c = 1'b0 14 | ); 15 | 16 | reg a_reg, b_reg = 1'b0; 17 | 18 | always@(posedge clk) 19 | if (reset) begin 20 | a_reg <= 1'b0; 21 | b_reg <= 1'b0; 22 | c <= 1'b0; 23 | end else begin 24 | a_reg <= a; 25 | b_reg <= b; 26 | c <= a_reg & b_reg; 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /tests/Build/cache_104x68/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # and2_verilog - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name and2_104x68 10 | 11 | puts "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file -V_2001 ./Src/and2.v 14 | set_top_module and2 15 | 16 | # Device target 17 | target_device GEMINI_COMPACT_104x68 18 | 19 | # Compilation 20 | puts "Compiling $project_name..." 21 | analyze 22 | synthesize delay 23 | simulate gate icarus 24 | packing 25 | place 26 | route 27 | sta 28 | bitstream write_cache 29 | 30 | puts "Completed $project_name...\n" 31 | -------------------------------------------------------------------------------- /tests/Build/cache_10x8/Src/and2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // and2_verilog // 5 | // and2.v - Top-level file of simple 2-input AND gate // 6 | //////////////////////////////////////////////////////// 7 | 8 | module and2 ( 9 | input a, 10 | input b, 11 | input clk, 12 | input reset, 13 | output reg c = 1'b0 14 | ); 15 | 16 | reg a_reg, b_reg = 1'b0; 17 | 18 | always@(posedge clk) 19 | if (reset) begin 20 | a_reg <= 1'b0; 21 | b_reg <= 1'b0; 22 | c <= 1'b0; 23 | end else begin 24 | a_reg <= a; 25 | b_reg <= b; 26 | c <= a_reg & b_reg; 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /tests/Build/cache_10x8/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # and2_verilog - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name and2_10x8 10 | 11 | puts "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file -V_2001 ./Src/and2.v 14 | set_top_module and2 15 | 16 | # Device target 17 | target_device GEMINI_COMPACT_10x8 18 | 19 | # Compilation 20 | puts "Compiling $project_name..." 21 | analyze 22 | synthesize delay 23 | simulate gate icarus 24 | packing 25 | place 26 | route 27 | sta 28 | bitstream write_cache 29 | 30 | puts "Completed $project_name...\n" 31 | -------------------------------------------------------------------------------- /tests/Build/cache_10x8/run_raptor.tcl~: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # and2_verilog - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name and2_104x68 10 | 11 | puts "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file -V_2001 ./Src/and2.v 14 | set_top_module and2 15 | 16 | # Device target 17 | target_device GEMINI_COMPACT_104x68 18 | 19 | # Compilation 20 | puts "Compiling $project_name..." 21 | analyze 22 | synthesize delay 23 | simulate gate icarus 24 | packing 25 | place 26 | route 27 | sta 28 | bitstream write_cache 29 | 30 | puts "Completed $project_name...\n" 31 | -------------------------------------------------------------------------------- /tests/TestBatch/oneff_clean/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 2.5 clock0 3 | set_input_delay 1 -clock clock0 [get_ports {d}] 4 | set_input_delay 1 -clock clock0 [get_ports {rstn}] 5 | set_output_delay 1 -clock clock0 [get_ports {q}] 6 | -------------------------------------------------------------------------------- /tests/TestBatch/oneff_clean/dut.v: -------------------------------------------------------------------------------- 1 | 2 | module dut (input d, 3 | input rstn, 4 | input clock0, 5 | output reg q); 6 | 7 | always @ (posedge clock0 or negedge rstn) 8 | begin 9 | if (!rstn) 10 | q <= 0; 11 | else 12 | q <= d; 13 | end 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /tests/TestBatch/oneff_clean/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_property mode Mode_BP_SDR_A_RX HR_1_0_0P 2 | set_pin_loc d HR_1_0_0P 3 | 4 | set_property mode Mode_BP_SDR_A_RX HR_3_0_0P 5 | set_pin_loc rstn HR_3_0_0P 6 | 7 | set_property mode Mode_BP_SDR_A_TX HR_3_8_4P 8 | set_pin_loc q HR_3_8_4P 9 | 10 | set_clock_pin -device_clock clk[0] -design_clock clock0 11 | 12 | -------------------------------------------------------------------------------- /tests/TestBatch/oneff_clean/sim_main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "Vsyn_tb.h" 4 | #include "verilated.h" 5 | 6 | #if VM_TRACE_VCD == 1 7 | #include "verilated_vcd_c.h" 8 | #else 9 | #include "verilated_fst_c.h" 10 | #endif 11 | 12 | double sc_time_stamp() { 13 | return 0; 14 | } 15 | 16 | int main(int argc, char** argv, char** env) { 17 | Verilated::commandArgs(argc, argv); 18 | Vsyn_tb* top = new Vsyn_tb; 19 | // init trace dump 20 | std::string waveformFile; 21 | if (argc > 1) { 22 | waveformFile = argv[1]; 23 | std::cout << "Waveform file: " << waveformFile << std::endl; 24 | } else { 25 | waveformFile = "syn_tb.fst"; 26 | } 27 | Verilated::traceEverOn(true); 28 | Verilated::assertOn(true); 29 | 30 | #if VM_TRACE_FST == 1 31 | VerilatedFstC* tfp = new VerilatedFstC; 32 | # else 33 | VerilatedVcdC* tfp = new VerilatedVcdC; 34 | #endif 35 | 36 | top->trace(tfp, 99); 37 | tfp->open(waveformFile.c_str()); 38 | top->rstn = 0; 39 | top->clk = 0; 40 | 41 | // run simulation for 20 clock periods 42 | // Only generate the clock in C, 43 | // the testbench is in Verilog 44 | for(int i = 0; i < 20; i++) { 45 | top->rstn = (i >= 2); 46 | for(int clk = 0; clk < 2; ++clk) { 47 | top->eval(); 48 | tfp->dump((2 * i) + clk); 49 | top->clk = !top->clk; 50 | } 51 | } 52 | tfp->close(); 53 | delete top; 54 | exit(0); 55 | } 56 | -------------------------------------------------------------------------------- /tests/TestBatch/oneff_clean/syn_tb.v: -------------------------------------------------------------------------------- 1 | module syn_tb(input logic rstn, 2 | input logic clk, 3 | output logic rtl_q); 4 | 5 | logic d; 6 | integer state = 0; 7 | 8 | // Stimulus + Model Checking 9 | always @ (posedge clk) begin 10 | if (state==0) begin 11 | d <= 0; 12 | state <= state+1; 13 | end 14 | else if (state==1) begin 15 | d <= 1; 16 | state <= state+1; 17 | end 18 | else if (state==2) begin 19 | d <= 1; 20 | state <= state+1; 21 | end 22 | else if (state==3) begin 23 | d <= 0; 24 | state <= state+1; 25 | end 26 | else if (state==4) begin 27 | d <= 0; 28 | state <= state+1; 29 | end 30 | else if (state==5) begin 31 | d <= 1; 32 | state <= state+1; 33 | end 34 | else if (state==6) begin 35 | d <= 0; 36 | state <= state+1; 37 | end 38 | else if (state==7) begin 39 | d <= 0; 40 | state <= state+1; 41 | end 42 | else if (state==8) begin 43 | d <= 0; 44 | state <= state+1; 45 | end 46 | $display("d = %0d, q = %0d", d, rtl_q); 47 | 48 | end 49 | 50 | dut rtl_model(d, rstn, clk, rtl_q); 51 | 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /tests/TestBatch/test_compiler_batch.tcl: -------------------------------------------------------------------------------- 1 | #Copyright 2021 The Foedag team 2 | 3 | #GPL License 4 | 5 | #Copyright (c) 2021 The Open-Source FPGA Foundation 6 | 7 | #This program is free software: you can redistribute it and/or modify 8 | #it under the terms of the GNU General Public License as published by 9 | #the Free Software Foundation, either version 3 of the License, or 10 | #(at your option) any later version. 11 | 12 | #This program is distributed in the hope that it will be useful, 13 | #but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | #MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | #GNU General Public License for more details. 16 | 17 | #You should have received a copy of the GNU General Public License 18 | #along with this program. If not, see . 19 | 20 | create_design test 21 | batch { 22 | ipgenerate 23 | synth 24 | packing 25 | globp 26 | place 27 | route 28 | sta 29 | power 30 | bitstream 31 | } 32 | 33 | after 22000 {set CONT 0} 34 | set CONT 1 35 | while {$CONT} { 36 | set a 0 37 | after 100 set a 1 38 | vwait a 39 | } 40 | exit 41 | -------------------------------------------------------------------------------- /tests/TestBatch/test_compiler_mt.tcl: -------------------------------------------------------------------------------- 1 | #Copyright 2021 The Foedag team 2 | 3 | #GPL License 4 | 5 | #Copyright (c) 2021 The Open-Source FPGA Foundation 6 | 7 | #This program is free software: you can redistribute it and/or modify 8 | #it under the terms of the GNU General Public License as published by 9 | #the Free Software Foundation, either version 3 of the License, or 10 | #(at your option) any later version. 11 | 12 | #This program is distributed in the hope that it will be useful, 13 | #but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | #MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | #GNU General Public License for more details. 16 | 17 | #You should have received a copy of the GNU General Public License 18 | #along with this program. If not, see . 19 | create_design test 20 | synthesize 21 | after 3000 {puts "Interrupted the command successfully: synthesize"; flush stdout ; stop} 22 | after 5000 {synthesize} 23 | after 16000 {packing} 24 | after 17000 {place} 25 | after 28000 {set CONT 0} 26 | set CONT 1 27 | while {$CONT} { 28 | set a 0 29 | after 100 set a 1 30 | vwait a 31 | } 32 | puts "PASSED" 33 | -------------------------------------------------------------------------------- /tests/TestGui/gui_foedag.tcl: -------------------------------------------------------------------------------- 1 | #Copyright 2021 The Foedag team 2 | 3 | #GPL License 4 | 5 | #Copyright (c) 2021 The Open-Source FPGA Foundation 6 | 7 | #This program is free software: you can redistribute it and/or modify 8 | #it under the terms of the GNU General Public License as published by 9 | #the Free Software Foundation, either version 3 of the License, or 10 | #(at your option) any later version. 11 | 12 | #This program is distributed in the hope that it will be useful, 13 | #but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | #MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | #GNU General Public License for more details. 16 | 17 | #You should have received a copy of the GNU General Public License 18 | #along with this program. If not, see . 19 | 20 | puts "GUI START" ; flush stdout ; gui_start 21 | puts "GUI STOP" ; flush stdout ; gui_stop 22 | puts "GUI START" ; flush stdout ; gui_start 23 | puts "TEXT EDITOR GUI OPENFILE" ; flush stdout ; openfile tests/TestGui/test.v 24 | puts "TEXT EDITOR GUI OPENFILE" ; flush stdout ; openfile tests/TestGui/test.v 25 | 26 | puts "NEW PROJECT START" ; flush stdout ; newproject_gui_open 27 | puts "NEXT" ; flush stdout ; next 28 | puts "NEXT" ; flush stdout ; next 29 | puts "NEXT" ; flush stdout ; next 30 | puts "NEXT" ; flush stdout ; next 31 | puts "NEXT" ; flush stdout ; next 32 | puts "NEW PROJECT STOP" ; flush stdout ; newproject_gui_close 33 | 34 | puts "GUI STOP" ; flush stdout ; gui_stop 35 | 36 | 37 | -------------------------------------------------------------------------------- /tests/TestGui/gui_run_incr_comp_project.tcl: -------------------------------------------------------------------------------- 1 | #Copyright 2021 The Foedag team 2 | 3 | #GPL License 4 | 5 | #Copyright (c) 2021 The Open-Source FPGA Foundation 6 | 7 | #This program is free software: you can redistribute it and/or modify 8 | #it under the terms of the GNU General Public License as published by 9 | #the Free Software Foundation, either version 3 of the License, or 10 | #(at your option) any later version. 11 | 12 | #This program is distributed in the hope that it will be useful, 13 | #but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | #MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | #GNU General Public License for more details. 16 | 17 | #You should have received a copy of the GNU General Public License 18 | #along with this program. If not, see . 19 | 20 | puts "RUNNING PROJECT" 21 | run_project examples/incr_comp/incr_comp.ospr 22 | set fp [open "raptor.log" r] 23 | set file_data [read $fp] 24 | close $fp 25 | # Report an error if project run wasn't successful 26 | set found [regexp "Project run successful" $file_data] 27 | if { !$found } { 28 | puts "TEST FAILED: incr_comp.ospr run failed." 29 | exit 1 30 | } 31 | 32 | puts "TEST SUCCEEDED" 33 | 34 | exit 0 35 | -------------------------------------------------------------------------------- /tests/TestGui/test.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ps/ 1 ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // Create Date: 2021-12-03 18:02:58 6 | // Design Name: 7 | // Module Name: test 8 | // Project Name: 9 | // Target Devices: 10 | // Tool Versions: 11 | // Description: 12 | // 13 | // Dependencies: 14 | // 15 | // Revision: 16 | // Additional Comments: 17 | // 18 | ////////////////////////////////////////////////////////////////////////////////// 19 | 20 | 21 | module test( 22 | 23 | ); 24 | endmodule 25 | -------------------------------------------------------------------------------- /tests/TestIP/axi2axilite_bridge/v1_0/axi2axilite_bridge.tcl: -------------------------------------------------------------------------------- 1 | create_design axi2axilite_bridge_prj 2 | 3 | target_device 1VG28 4 | 5 | #set path here 6 | 7 | set IP_PATH ./axi2axilite_bridge_prj/run_1/IPs/ 8 | 9 | #Configuring axi2axilite_bridge_v1_0 IP 10 | configure_ip axi2axilite_bridge_v1_0 -mod_name axi2axilite_bridge_wrapper -Pdata_width=64 -Paddr_width=8 -out_file $IP_PATH/axi2axilite_bridge_wrapper 11 | 12 | #Generate IP 13 | ipgenerate 14 | 15 | #Add generate IP as a design and synthesize it 16 | add_design_file $IP_PATH/rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_wrapper/src/axi2axilite_bridge_wrapper_v1_0.v 17 | add_library_path $IP_PATH/rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_wrapper/src/ 18 | set_top_module axi2axilite_bridge_wrapper 19 | analyze 20 | synth delay 21 | 22 | -------------------------------------------------------------------------------- /tests/TestIP/axi_cdma/v1_0/axi_cdma.tcl: -------------------------------------------------------------------------------- 1 | create_design axi_cdma_prj 2 | 3 | target_device 1GE100-ES1 4 | 5 | set IP_PATH ./axi_cdma_prj/run_1/IPs/ 6 | 7 | 8 | #Configuring axi_cdma_v1_0 IP 9 | configure_ip axi_cdma_v1_0 -mod_name axi_cdma_wrapper -Pdata_width=64 -Paddr_width=8 -out_file $IP_PATH/axi_cdma_wrapper 10 | 11 | #Generate IP 12 | ipgenerate 13 | 14 | #Add generate IP as a design and synthesize it 15 | add_design_file $IP_PATH/rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_wrapper/src/axi_cdma_wrapper_v1_0.v 16 | add_library_path $IP_PATH/rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_wrapper/src/ 17 | set_top_module axi_cdma_wrapper 18 | parser_type surelog 19 | synth_options -new_tdp36k 20 | synth delay 21 | 22 | -------------------------------------------------------------------------------- /tests/TestIP/axi_interconnect/v1_0/axi_interconnect.tcl: -------------------------------------------------------------------------------- 1 | create_design axi_interconnect_prj 2 | 3 | target_device 1GE100-ES1 4 | 5 | #Configuring axi_interconnect_v1_0 IP 6 | configure_ip axi_interconnect_v1_0 -mod_name axi_interconnect_wrapper -Pdata_width=32 -Paddr_width=32 -out_file ./axi_interconnect_prj/run_1/IPs/axi_interconnect_wrapper 7 | 8 | #Generate IP 9 | ipgenerate 10 | 11 | #Add generate IP as a design and synthesize it 12 | add_design_file ./axi_interconnect_prj/run_1/IPs/rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_wrapper/src/axi_interconnect_wrapper_v1_0.v 13 | add_design_file ./axi_interconnect_prj/run_1/IPs/rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_wrapper/src/axi_interconnect.v 14 | add_design_file ./axi_interconnect_prj/run_1/IPs/rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_wrapper/src/arbiter.v 15 | add_design_file ./axi_interconnect_prj/run_1/IPs/rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_wrapper/src/priority_encoder.v 16 | set_top_module axi_interconnect_wrapper 17 | parser_type surelog 18 | synth_options -new_tdp36k 19 | synth delay 20 | 21 | -------------------------------------------------------------------------------- /tests/TestIP/axi_ram/v1_0/axi_ram.tcl: -------------------------------------------------------------------------------- 1 | create_design axi_ram_prj 2 | 3 | target_device 1GE100-ES1 4 | 5 | 6 | set IP_PATH ./axi_ram_prj/axi_ram_prj.IPs 7 | 8 | configure_ip axi_ram_v1_0 -mod_name axi_ram_wrapper -Pdata_width=64 -Paddr_width=8 -Pid_width=8 -Ppip_out=1 -out_file $IP_PATH/axi_ram_wrapper 9 | ipgenerate 10 | 11 | add_design_file $IP_PATH/rapidsilicon/ip/axi_ram/v1_0/axi_ram_wrapper/src/axi_ram_wrapper_v1_0.v 12 | add_library_path $IP_PATH/rapidsilicon/ip/axi_ram/v1_0/axi_ram_wrapper/src/ 13 | set_top_module axi_ram_wrapper 14 | parser_type surelog 15 | synth_options -new_tdp36k 16 | synth delay 17 | 18 | -------------------------------------------------------------------------------- /tests/TestIP/axi_register/v1_0/axi_register.tcl: -------------------------------------------------------------------------------- 1 | create_design axi_register_prj 2 | 3 | target_device 1GE100-ES1 4 | set IP_PATH ./axi_register_prj/run_1/IPs/ 5 | 6 | 7 | #Configuring axi_register_v1_0 IP 8 | configure_ip axi_register_v1_0 -mod_name axi_register_wrapper -Pdata_width=64 -Paddr_width=8 -out_file $IP_PATH/axi_register_wrapper 9 | 10 | #Generate IP 11 | ipgenerate 12 | 13 | #Add generate IP as a design and synthesize it 14 | add_design_file $IP_PATH/rapidsilicon/ip/axi_register/v1_0/axi_register_wrapper/src/axi_register_wrapper_v1_0.v 15 | add_library_path $IP_PATH/rapidsilicon/ip/axi_register/v1_0/axi_register_wrapper/src/ 16 | set_top_module axi_register_wrapper 17 | parser_type surelog 18 | synth_options -new_tdp36k 19 | synth delay 20 | 21 | -------------------------------------------------------------------------------- /tests/TestIP/axil_gpio/v1_0/axil_gpio.tcl: -------------------------------------------------------------------------------- 1 | create_design axil_gpio_prj 2 | 3 | target_device 1GE100-ES1 4 | 5 | set IP_PATH ./axil_gpio_prj/run_1/IPs/ 6 | 7 | 8 | #Configuring axil_gpio_v1_0 IP 9 | configure_ip axil_gpio_v1_0 -mod_name axil_gpio_wrapper -Pdata_width=32 -Paddr_width=16 -out_file $IP_PATH/axil_gpio_wrapper 10 | 11 | #Generate IP 12 | ipgenerate 13 | 14 | #Add generate IP as a design and synthesize it 15 | add_design_file $IP_PATH/rapidsilicon/ip/axil_gpio/v1_0/axil_gpio_wrapper/src/axil_gpio_wrapper_v1_0.sv 16 | add_library_path $IP_PATH/rapidsilicon/ip/axil_gpio/v1_0/axil_gpio_wrapper/src/ 17 | add_include_path $IP_PATH/rapidsilicon/ip/axil_gpio/v1_0/axil_gpio_wrapper/src/ 18 | add_library_ext .v .sv 19 | 20 | set_top_module axil_gpio_wrapper 21 | parser_type surelog 22 | synth delay 23 | 24 | -------------------------------------------------------------------------------- /tests/TestIP/axis_adapter/v1_0/axis_adapter.tcl: -------------------------------------------------------------------------------- 1 | create_design axis_adapter_prj 2 | 3 | target_device 1GE100-ES1 4 | 5 | 6 | set IP_PATH ./axis_adapter_prj/run_1/IPs/ 7 | 8 | 9 | #Configuring axis_adapter_v1_0 IP 10 | configure_ip axis_adapter_v1_0 -mod_name axis_adapter_wrapper -Ps_data_width=32 -out_file $IP_PATH/axis_adapter_wrapper 11 | ipgenerate 12 | add_design_file $IP_PATH/rapidsilicon/ip/axis_adapter/v1_0/axis_adapter_wrapper/src/axis_adapter_wrapper_v1_0.v 13 | add_library_path $IP_PATH/rapidsilicon/ip/axis_adapter/v1_0/axis_adapter_wrapper/src/ 14 | set_top_module axis_adapter_wrapper 15 | parser_type surelog 16 | synth delay 17 | 18 | 19 | -------------------------------------------------------------------------------- /tests/TestIP/axis_fifo/v1_0/axis_fifo.tcl: -------------------------------------------------------------------------------- 1 | create_design axis_fifo_prj 2 | 3 | target_device 1GE100-ES1 4 | 5 | set IP_PATH ./axis_fifo_prj/axis_fifo_prj.IPs 6 | 7 | 8 | #Configuring axis_fifo_v1_0 IP 9 | configure_ip axis_fifo_v1_0 -mod_name axis_fifo_wrapper -Pdepth=4096 -Pdata_width=16 -out_file $IP_PATH/axis_fifo_wrapper 10 | 11 | #Generate IP 12 | ipgenerate 13 | 14 | #Add generate IP as a design and synthesize it 15 | add_design_file $IP_PATH/rapidsilicon/ip/axis_fifo/v1_0/axis_fifo_wrapper/src/axis_fifo_wrapper_v1_0.v 16 | add_library_path $IP_PATH/rapidsilicon/ip/axis_fifo/v1_0/axis_fifo_wrapper/src/ 17 | set_top_module axis_fifo_wrapper 18 | synth delay 19 | 20 | -------------------------------------------------------------------------------- /tests/TestIP/ip_simulation/axi_ram/v1_0/axi_ram.tcl: -------------------------------------------------------------------------------- 1 | create_design axi_ram_prj 2 | target_device 1GE100-ES1 3 | 4 | set IP_PATH ./axi_ram_prj/axi_ram_prj.IPs 5 | 6 | configure_ip axi_ram_v1_0 -mod_name axi_ram_wrapper -Pdata_width=64 -Paddr_width=8 -Pid_width=8 -Ppip_out=1 -out_file $IP_PATH/axi_ram_wrapper 7 | ipgenerate 8 | 9 | add_design_file $IP_PATH/rapidsilicon/ip/axi_ram/v1_0/axi_ram_wrapper/src/axi_ram_wrapper_v1_0.v 10 | add_library_path $IP_PATH/rapidsilicon/ip/axi_ram/v1_0/axi_ram_wrapper/src/ 11 | set_top_module axi_ram_wrapper 12 | 13 | simulate_ip axi_ram_wrapper 14 | 15 | set SUCCESS [file exists $IP_PATH/simulation/rapidsilicon/ip/axi_ram/v1_0/axi_ram_wrapper/axi_ram_wrapper.fst] 16 | if {$SUCCESS == 0} { 17 | error "File axi_ram_wrapper.fst not found" 18 | } 19 | -------------------------------------------------------------------------------- /tests/TestIP/reset_release/v1_0/reset_release.tcl: -------------------------------------------------------------------------------- 1 | create_design reset_release_prj 2 | 3 | target_device 1GE100-ES1 4 | 5 | set IP_PATH ./reset_release_prj/run_1/IPs/ 6 | 7 | 8 | #Configuring reset_release_v1_0 IP 9 | configure_ip reset_release_v1_0 -mod_name reset_release_wrapper -Pext_reset_width=7 -out_file $IP_PATH/reset_release_wrapper 10 | 11 | #Generate IP 12 | ipgenerate 13 | 14 | #Add generate IP as a design and synthesize it 15 | add_design_file $IP_PATH/rapidsilicon/ip/reset_release/v1_0/reset_release_wrapper/src/reset_release_wrapper_v1_0.v 16 | add_library_path $IP_PATH/rapidsilicon/ip/reset_release/v1_0/reset_release_wrapper/src/ 17 | set_top_module reset_release_wrapper 18 | parser_type surelog 19 | synth delay 20 | 21 | -------------------------------------------------------------------------------- /tests/Testcases/aes_decrypt_fpga/InvAddRoundKey.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module InvAddRoundKey( 4 | input [0:127] din0, 5 | input [0:127] din1, 6 | input [0:127] rkey, 7 | input S, 8 | output [0:127] dout); 9 | 10 | logic [0:127] tmp; 11 | 12 | always_comb 13 | tmp <= S? din1 : din0; 14 | 15 | assign dout = tmp ^ rkey; 16 | endmodule -------------------------------------------------------------------------------- /tests/Testcases/aes_decrypt_fpga/aes_decrypt.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | create_clock -period 2.5 clk 3 | -------------------------------------------------------------------------------- /tests/Testcases/aes_decrypt_fpga/aes_decrypt.tcl: -------------------------------------------------------------------------------- 1 | create_design AES_DECRYPT 2 | target_device 1VG28 3 | set_top_module wrapper 4 | add_design_file aes_decrypt128.sv aes_decrypt256.sv gfmul.sv InvMixCol_slice.sv InvSbox.sv InvSubBytes.sv KeyExpand192.sv KschBuffer.sv Sbox.sv aes_decrypt192.sv decrypt.sv InvAddRoundKey.sv InvMixColumns.sv InvShiftRows.sv KeyExpand128.sv KeyExpand256.sv RotWord.sv SubWord.sv -SV_2012 5 | add_design_file generic_muxfx.v wrapper.v 6 | 7 | add_constraint_file aes_decrypt.sdc 8 | synth_options -effort high 9 | analyze 10 | message_severity VERI-1209 IGNORE 11 | synthesize delay 12 | packing 13 | place 14 | route 15 | sta 16 | power 17 | bitstream 18 | -------------------------------------------------------------------------------- /tests/Testcases/aes_decrypt_fpga/generic_muxfx.v: -------------------------------------------------------------------------------- 1 | // Technology independent version of MUXF7 and MUXF8. 2 | // 3 | // This file should not be included while targeting Xilinx so that 4 | // the MUXF7/MUXF8 primitives in the Xilinx simulation/synthesis 5 | // will be used instead. 6 | module MUXF7 (output O, input I0, input I1, input S); 7 | assign O = (S)? I1 : I0; 8 | endmodule 9 | 10 | module MUXF8 (output O, input I0, input I1, input S); 11 | assign O = (S)? I1 : I0; 12 | endmodule -------------------------------------------------------------------------------- /tests/Testcases/aes_decrypt_fpga/pin_constraints.pin: -------------------------------------------------------------------------------- 1 | set_clock_pin -device_clock clk[0] -design_clock clk 2 | -------------------------------------------------------------------------------- /tests/Testcases/aes_decrypt_fpga/wrapper.v: -------------------------------------------------------------------------------- 1 | // Dirty wrapper necessary to decrease the number of pins to fit gemini 2 | module wrapper (input [0:127] ct, 3 | input ct_vld, 4 | output ct_rdy, 5 | 6 | input rkey_vld, 7 | output next_rkey, 8 | 9 | output [0:127] pt, 10 | output pt_vld, 11 | 12 | input [0:1] klen_sel, 13 | 14 | input clk, 15 | input rst); 16 | 17 | 18 | decrypt U1 ( 19 | ct, 20 | ct_vld, 21 | ct_rdy, 22 | 23 | ct , 24 | rkey_vld, 25 | next_rkey, 26 | 27 | pt, 28 | pt_vld, 29 | 30 | klen_sel, 31 | 32 | clk, 33 | rst 34 | ); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /tests/Testcases/aes_decrypt_gate/aes_decrypt_gate.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | create_clock -period 2.5 clk 3 | -------------------------------------------------------------------------------- /tests/Testcases/aes_decrypt_gate/aes_decrypt_gate.tcl: -------------------------------------------------------------------------------- 1 | # Gate level netlist input example 2 | 3 | # Specifc project type "gate-level" 4 | create_design AES_DECRYPT_GATE -type gate-level 5 | 6 | target_device 1VG28 7 | 8 | # Specific command to load a netlist file 9 | read_netlist aes_decrypt.v 10 | 11 | add_constraint_file aes_decrypt_gate.sdc 12 | 13 | # Analyze the Verilog netlist (Hierarchy) 14 | analyze 15 | 16 | # MUST: Synthesis only converts Verilog to Eblif for VPR (No optimization) 17 | synthesize 18 | 19 | packing 20 | place 21 | route 22 | sta 23 | power 24 | bitstream 25 | 26 | -------------------------------------------------------------------------------- /tests/Testcases/and2_10x8/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_pin_loc a HP_1_0_0P 2 | set_pin_loc b HP_1_1_0N 3 | set_pin_loc c HP_1_2_1P -------------------------------------------------------------------------------- /tests/Testcases/and2_10x8/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2_10x8 3 | add_design_file -V_2001 ./rtl/and2.v 4 | set_top_module and2 5 | add_constraint_file pin_mapping.pin 6 | 7 | # Simulation 8 | add_simulation_file ./rtl/testbench_and2.v 9 | set_top_testbench testbench_and2 10 | 11 | # Device target 12 | target_device GEMINI_COMPACT_22x4 13 | 14 | # RTL Simulation 15 | simulate rtl icarus 16 | 17 | # Analysis 18 | analyze 19 | 20 | # Synthesis 21 | synthesize delay 22 | 23 | # Gate-level simulation 24 | simulate gate icarus 25 | 26 | # Compilation 27 | packing 28 | place 29 | route 30 | 31 | # Post PnR simulation 32 | simulate pnr icarus 33 | 34 | sta 35 | power 36 | bitstream write_xml 37 | -------------------------------------------------------------------------------- /tests/Testcases/and2_10x8/rtl/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | a, 9 | b, 10 | c); 11 | 12 | input wire a; 13 | input wire b; 14 | output wire c; 15 | 16 | assign c = a & b; 17 | 18 | endmodule -------------------------------------------------------------------------------- /tests/Testcases/and2_2clks/Src/and2x2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // and2_verilog // 5 | // and2.v - Top-level file of simple 2-input AND gate // 6 | //////////////////////////////////////////////////////// 7 | 8 | module and2 ( 9 | input a, 10 | input b, 11 | input clk, 12 | input reset, 13 | output reg c = 1'b0 14 | ); 15 | 16 | reg a_reg, b_reg = 1'b0; 17 | 18 | always@(posedge clk) 19 | if (reset) begin 20 | a_reg <= 1'b0; 21 | b_reg <= 1'b0; 22 | c <= 1'b0; 23 | end else begin 24 | a_reg <= a; 25 | b_reg <= b; 26 | c <= a_reg & b_reg; 27 | end 28 | 29 | endmodule 30 | 31 | 32 | module and2x2 ( 33 | input a, 34 | input b, 35 | input clk1, 36 | input clk2, 37 | input reset, 38 | output wire c1, 39 | output wire c2 40 | ); 41 | 42 | and2 u1 (a,b, clk1, reset, c1); 43 | and2 u2 (a,b, clk2, reset, c2); 44 | 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /tests/Testcases/and2_2clks/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 200 MHz (5nS period) 4 | create_clock -period 5 [get_ports {clk1}] -name clk1 5 | create_clock -period 5 [get_ports {clk2}] -name clk2 6 | 7 | set_clock_groups -group [get_clocks {clk1}] -group [get_clocks {clk2}] -physically_exclusive 8 | create_clock -name clk3 -period 6 9 | set_false_path -from [get_clocks {clk1}] -to [get_clocks {clk2}] 10 | -------------------------------------------------------------------------------- /tests/Testcases/and2_2clks/pin_constraints.pin: -------------------------------------------------------------------------------- 1 | set_pin_loc a HP_1_0_0P 2 | set_pin_loc b HP_1_1_0N 3 | set_pin_loc c1 HP_1_2_1P 4 | set_pin_loc c2 HP_1_3_1N 5 | set_pin_loc clk1 HP_1_CC_18_9P 6 | set_pin_loc clk2 HP_1_CC_19_9N 7 | set_pin_loc reset HP_1_4_2P 8 | -------------------------------------------------------------------------------- /tests/Testcases/and2_2clks/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # and2_verilog - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name and2x2 10 | 11 | message "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file -V_2001 ./Src/and2x2.v 14 | # Top-module can automatically be indentified or implicitly specified here 15 | set_top_module and2x2 16 | add_constraint_file constraints.sdc 17 | add_constraint_file pin_constraints.pin 18 | # Simulation 19 | add_simulation_file ./Src/testbench_and2.v 20 | set_top_testbench testbench_and2 21 | # Device target 22 | target_device GEMINI_COMPACT_22x4 23 | 24 | # RTL Simulation 25 | simulate rtl icarus 26 | 27 | #wave_open and2/and2.vcd 28 | #wave_show reset 29 | #wave_show clk 30 | #wave_show a 31 | #wave_show b 32 | #wave_show a_delay_by_2 33 | #wave_show b_delay_by_2 34 | #wave_show c 35 | #wave_cmd gtkwave::/Time/Zoom/Zoom_Full 36 | 37 | # Compilation 38 | message "Compiling $project_name..." 39 | analyze 40 | #synth_options -inferred_io 41 | synthesize delay 42 | power 43 | simulate gate icarus 44 | 45 | packing 46 | place 47 | route 48 | sta 49 | simulate pnr icarus 50 | 51 | bitstream 52 | 53 | message "Completed $project_name...\n" 54 | -------------------------------------------------------------------------------- /tests/Testcases/and2_compact/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 10 clk 3 | set_input_delay 1 -clock clk [get_ports {*}] 4 | set_output_delay 1 -clock clk [get_ports {*}] 5 | -------------------------------------------------------------------------------- /tests/Testcases/and2_compact/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_property mode Mode_BP_SDR_A_RX HR_1_0_0P 2 | set_pin_loc a HR_1_0_0P 3 | 4 | set_property mode Mode_BP_SDR_A_RX HR_3_0_0P 5 | set_pin_loc b HR_3_0_0P 6 | 7 | set_property mode Mode_BP_SDR_A_TX HR_3_8_4P 8 | set_pin_loc c HR_3_8_4P 9 | -------------------------------------------------------------------------------- /tests/Testcases/and2_compact/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2_compact 3 | add_design_file -V_2001 ./rtl/and2.v 4 | set_top_module and2 5 | add_constraint_file pin_mapping.pin 6 | add_constraint_file constraints.sdc 7 | 8 | # Device target 9 | target_device GEMINI_COMPACT_10x8 10 | # Compilation 11 | analyze 12 | synthesize delay 13 | packing 14 | place 15 | route 16 | sta 17 | bitstream 18 | -------------------------------------------------------------------------------- /tests/Testcases/and2_compact/rtl/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | a, 9 | b, 10 | c, 11 | clk, 12 | reset); 13 | 14 | input wire a; 15 | input wire b; 16 | input wire clk; 17 | input wire reset; 18 | output c; 19 | 20 | wire d; 21 | reg c; 22 | 23 | assign d = a & b; 24 | 25 | always@(posedge clk or posedge reset) begin 26 | if (reset) 27 | c = 0; 28 | else 29 | c = d; 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /tests/Testcases/and2_gemini/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 10 clk 3 | set_input_delay 1 -clock clk [get_ports {*}] 4 | set_output_delay 1 -clock clk [get_ports {*}] 5 | -------------------------------------------------------------------------------- /tests/Testcases/and2_gemini/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | 2 | set_property mode Mode_BP_SDR_A_RX HR_1_CC_18_9P 3 | set_pin_loc a HR_1_CC_18_9P 4 | 5 | set_property mode Mode_BP_SDR_A_RX HP_1_26_13P 6 | set_pin_loc b HP_1_26_13P 7 | 8 | set_property mode Mode_BP_SDR_A_TX HP_1_24_12P 9 | set_pin_loc c HP_1_24_12P 10 | 11 | 12 | -------------------------------------------------------------------------------- /tests/Testcases/and2_gemini/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2_gemini 3 | add_design_file -V_2001 ./rtl/and2.v 4 | set_top_module and2 5 | add_constraint_file pin_mapping.pin 6 | add_constraint_file constraints.sdc 7 | 8 | # Device target 9 | target_device 1VG28 10 | # Compilation 11 | analyze 12 | synthesize delay 13 | packing 14 | place 15 | route 16 | sta 17 | bitstream 18 | -------------------------------------------------------------------------------- /tests/Testcases/and2_gemini/rtl/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | a, 9 | b, 10 | c, 11 | clk, 12 | reset); 13 | 14 | input wire a; 15 | input wire b; 16 | input wire clk; 17 | input wire reset; 18 | output c; 19 | 20 | wire d; 21 | reg c; 22 | 23 | assign d = a & b; 24 | 25 | always@(posedge clk or posedge reset) begin 26 | if (reset) 27 | c = 0; 28 | else 29 | c = d; 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /tests/Testcases/and2_gemini_latest/constraints.sdc: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /tests/Testcases/and2_gemini_latest/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_property mode Mode_BP_SDR_A_RX HP_1_CC_28_14P 2 | set_pin_loc a HP_1_CC_28_14P 3 | 4 | set_property mode Mode_BP_SDR_A_RX HP_1_26_13P 5 | set_pin_loc b HP_1_26_13P 6 | 7 | set_property mode Mode_BP_SDR_A_TX HP_1_24_12P 8 | set_pin_loc c HP_1_24_12P 9 | 10 | -------------------------------------------------------------------------------- /tests/Testcases/and2_gemini_latest/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2_gemini_latest 3 | add_design_file -V_2001 ./rtl/and2.v 4 | set_top_module and2 5 | add_constraint_file constraints.sdc 6 | add_constraint_file pin_mapping.pin 7 | 8 | # Device target 9 | target_device GEMINI_COMPACT_10x8 10 | 11 | # Compilation 12 | analyze 13 | synthesize delay 14 | packing 15 | place 16 | route 17 | sta 18 | bitstream 19 | -------------------------------------------------------------------------------- /tests/Testcases/and2_gemini_latest/rtl/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | a, 9 | b, 10 | c); 11 | 12 | input wire a; 13 | input wire b; 14 | output wire c; 15 | 16 | assign c = a & b; 17 | 18 | endmodule -------------------------------------------------------------------------------- /tests/Testcases/and2_gemini_no_pcf/constraints.sdc: -------------------------------------------------------------------------------- 1 | # intentionally provide no pin constraint here. 2 | # in such case, raptor should generate a default constraint file to make sure vpr only use legal pins in device to connect user's design ports. 3 | # legal pins are pins inside fpga which are actually wired to top level bump pin of device package. 4 | -------------------------------------------------------------------------------- /tests/Testcases/and2_gemini_no_pcf/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2_gemini 3 | add_design_file -V_2001 ./rtl/and2.v 4 | set_top_module and2 5 | add_constraint_file constraints.sdc 6 | 7 | # Device target 8 | target_device GEMINI_COMPACT_10x8 9 | 10 | # Compilation 11 | synthesize delay 12 | packing 13 | place 14 | route 15 | sta 16 | bitstream 17 | -------------------------------------------------------------------------------- /tests/Testcases/and2_gemini_no_pcf/rtl/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | a, 9 | b, 10 | c); 11 | 12 | input wire a; 13 | input wire b; 14 | output wire c; 15 | 16 | assign c = a & b; 17 | 18 | endmodule -------------------------------------------------------------------------------- /tests/Testcases/and2_hierarchical/raptor_gate.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2_compact_gate -type gate-level 3 | read_netlist gate.v 4 | set_top_module top 5 | 6 | # Device target 7 | target_device GEMINI_COMPACT_10x8 8 | # Compilation 9 | #analyze 10 | #synthesize delay 11 | packing 12 | place 13 | route 14 | sta opensta 15 | bitstream enable_simulation 16 | -------------------------------------------------------------------------------- /tests/Testcases/and2_legacy/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 10 clk 3 | set_input_delay 1 -clock clk [get_ports {*}] 4 | set_output_delay 1 -clock clk [get_ports {*}] 5 | -------------------------------------------------------------------------------- /tests/Testcases/and2_legacy/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_property mode Mode_BP_SDR_A_RX Bank_VL_1_19 2 | set_pin_loc a Bank_VL_1_19 3 | 4 | set_property mode Mode_BP_SDR_A_RX Bank_VL_1_21 5 | set_pin_loc b Bank_VL_1_21 6 | 7 | set_property mode Mode_BP_SDR_A_TX Bank_VL_1_23 8 | set_pin_loc c Bank_VL_1_23 -------------------------------------------------------------------------------- /tests/Testcases/and2_legacy/pin_mapping.pin~: -------------------------------------------------------------------------------- 1 | 2 | set_mode Mode_BP_SDR_A_RX HP_1_CC_28_14P 3 | set_pin_loc a HP_1_CC_28_14P 4 | 5 | set_mode Mode_BP_SDR_A_RX HP_1_26_13P 6 | set_pin_loc b HP_1_26_13P 7 | 8 | set_mode Mode_BP_SDR_A_TX HP_1_24_12P 9 | set_pin_loc c HP_1_24_12P 10 | 11 | 12 | -------------------------------------------------------------------------------- /tests/Testcases/and2_legacy/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2_gemini_legacy 3 | add_design_file -V_2001 ./rtl/and2.v 4 | set_top_module and2 5 | add_constraint_file pin_mapping.pin 6 | add_constraint_file constraints.sdc 7 | 8 | # Device target 9 | target_device MPW1 10 | # Compilation 11 | analyze 12 | synthesize delay 13 | packing 14 | place 15 | route 16 | sta opensta 17 | bitstream 18 | -------------------------------------------------------------------------------- /tests/Testcases/and2_legacy/raptor.tcl~: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2_gemini 3 | add_design_file -V_2001 ./rtl/and2.v 4 | set_top_module and2 5 | add_constraint_file pin_mapping.pin 6 | add_constraint_file constraints.sdc 7 | 8 | # Device target 9 | target_device GEMINI 10 | # Compilation 11 | analyze 12 | synthesize delay 13 | packing 14 | place 15 | route 16 | sta opensta 17 | bitstream 18 | -------------------------------------------------------------------------------- /tests/Testcases/and2_legacy/rtl/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | a, 9 | b, 10 | c, 11 | clk, 12 | reset); 13 | 14 | input wire a; 15 | input wire b; 16 | input wire clk; 17 | input wire reset; 18 | output c; 19 | 20 | wire d; 21 | reg c; 22 | 23 | assign d = a & b; 24 | 25 | always@(posedge clk or posedge reset) begin 26 | if (reset) 27 | c = 0; 28 | else 29 | c = d; 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /tests/Testcases/and2_pin_table_test/Src/and2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // and2_verilog // 5 | // and2.v - Top-level file of simple 2-input AND gate // 6 | //////////////////////////////////////////////////////// 7 | 8 | module Llatch( input D, input G, output reg Q); 9 | 10 | always @* 11 | if (G == 1'b1) 12 | Q <= D; 13 | else 14 | Q<=Q; 15 | 16 | endmodule 17 | 18 | module and2 ( 19 | input a, 20 | input b, 21 | input clk, 22 | input reset, 23 | output reg c = 1'b0, 24 | output wire Q 25 | ); 26 | 27 | reg a_reg, b_reg = 1'b0; 28 | 29 | Llatch my (a,b, Q); 30 | 31 | 32 | 33 | always@(posedge clk) 34 | if (reset) begin 35 | a_reg <= 1'b0; 36 | b_reg <= 1'b0; 37 | c <= 1'b0; 38 | end else begin 39 | a_reg <= a; 40 | b_reg <= b; 41 | c <= a_reg & b_reg; 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /tests/Testcases/and2_pin_table_test/and2_part.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /tests/Testcases/and2_pin_table_test/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 200 MHz (5nS period) 4 | create_clock -period 5 clk 5 | set_input_delay 0.8 -clock clk [get_ports {a}] 6 | set_input_delay 0.8 -clock clk [get_ports {b}] 7 | 8 | -------------------------------------------------------------------------------- /tests/Testcases/and2_pin_table_test/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_property mode Mode_BP_SDR_A_RX HR_1_0_0P 2 | set_pin_loc a HR_1_0_0P 3 | 4 | set_property mode Mode_BP_SDR_A_RX HR_1_12_6P 5 | set_pin_loc b HR_1_12_6P 6 | 7 | set_property mode Mode_BP_SDR_A_TX HR_1_14_7P 8 | set_pin_loc c HR_1_14_7P 9 | -------------------------------------------------------------------------------- /tests/Testcases/and2_pin_table_test/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # and2_verilog - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name and2 10 | 11 | puts "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file -V_2001 ./Src/and2.v 14 | # Top-module can automatically be indentified or implicitly specified here 15 | set_top_module and2 16 | add_constraint_file pin_mapping.pin 17 | add_constraint_file constraints.sdc 18 | # Simulation 19 | add_simulation_file -SV_2012 ./Src/testbench_and2.v 20 | set_top_testbench testbench_and2 21 | # Device target 22 | target_device GEMINI_COMPACT_10x8 23 | 24 | # RTL Simulation 25 | #simulate rtl icarus 26 | 27 | #wave_open and2/and2.vcd 28 | #wave_show reset 29 | #wave_show clk 30 | #wave_show a 31 | #wave_show b 32 | #wave_show a_delay_by_2 33 | #wave_show b_delay_by_2 34 | #wave_show c 35 | #wave_cmd gtkwave::/Time/Zoom/Zoom_Full 36 | 37 | # Compilation 38 | puts "Compiling $project_name..." 39 | parser_type surelog 40 | analyze 41 | #synth_options -inferred_io 42 | #parser_type surelog 43 | synthesize delay 44 | simulate gate icarus 45 | #pnr_options --read_vpr_constraints and2_part.xml 46 | packing 47 | place 48 | #route 49 | #sta 50 | #power 51 | #bitstream 52 | #simulate pnr icarus 53 | 54 | puts "Completed $project_name...\n" 55 | -------------------------------------------------------------------------------- /tests/Testcases/and2_reg/constraints.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 2.5 clki 2 | create_clock -period 2.5 clko 3 | set_input_delay 1 -clock clki [get_ports {reg_*}] 4 | set_output_delay 1 -clock clko [get_ports {Q}] 5 | -------------------------------------------------------------------------------- /tests/Testcases/and2_reg/pin.sdc: -------------------------------------------------------------------------------- 1 | set_property mode Mode_BP_SDR_A_RX HP_1_CC_28_14P 2 | set_pin_loc a HP_1_CC_28_14P 3 | 4 | set_property mode Mode_BP_SDR_A_RX HP_1_26_13P 5 | set_pin_loc b HP_1_26_13P 6 | 7 | set_property mode Mode_BP_SDR_A_TX HP_1_24_12P 8 | set_pin_loc c HP_1_24_12P 9 | -------------------------------------------------------------------------------- /tests/Testcases/and2_reg/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_property mode Mode_BP_SDR_A_RX HR_2_0_0P 2 | set_pin_loc reg_a HR_2_0_0P 3 | 4 | set_property mode Mode_BP_SDR_A_RX HR_3_0_0P 5 | set_pin_loc reg_b HR_3_0_0P 6 | 7 | set_property mode Mode_BP_SDR_A_TX HR_5_0_0P 8 | set_pin_loc Q HR_5_0_0P 9 | 10 | set_clock_pin -device_clock clk[8] -design_clock clki 11 | set_clock_pin -device_clock clk[9] -design_clock clko 12 | -------------------------------------------------------------------------------- /tests/Testcases/and2_reg/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2_reg_gemini 3 | add_design_file ./rtl/and2.sv 4 | set_top_module reg_and2 5 | add_constraint_file pin_mapping.pin 6 | add_constraint_file constraints.sdc 7 | 8 | # Device target 9 | target_device GEMINI_COMPACT_10x8 10 | # Compilation 11 | analyze 12 | synthesize delay 13 | packing 14 | place 15 | route 16 | sta 17 | bitstream 18 | -------------------------------------------------------------------------------- /tests/Testcases/and2_reg/rtl/and2.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module ff(D,clk,Q); 8 | input logic D, clk; 9 | output reg Q; 10 | always @(posedge clk) 11 | begin 12 | Q <= D; 13 | end 14 | endmodule 15 | 16 | module and2(a,b,c); 17 | input wire a, b; 18 | output wire c; 19 | 20 | assign c = a & b; 21 | 22 | endmodule 23 | 24 | 25 | module reg_and2(reg_a,reg_b,clki,clko,Q); 26 | input logic reg_a, reg_b, clki, clko; 27 | output reg Q; 28 | ff ff_a(reg_a, clki, a_ff); 29 | ff ff_b(reg_b, clki, b_ff); 30 | and2 a2 (a_ff, b_ff, c); 31 | ff ff_c(c, clko, Q); 32 | endmodule 33 | -------------------------------------------------------------------------------- /tests/Testcases/and2_reg/rtl/and2.sv~: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module ff(D,clk,Q); 8 | input logic D, clk; 9 | output reg Q; 10 | always @(posedge clk) 11 | begin 12 | Q <= D; 13 | end 14 | endmodule 15 | 16 | module and2(a,b,c); 17 | input wire a, b; 18 | output wire c; 19 | 20 | assign c = a & b; 21 | 22 | endmodule 23 | 24 | 25 | module reg_and2(reg_a,reg_b,clk,Q); 26 | input logic reg_a, reg_b, clk; 27 | output reg Q; 28 | ff ff_a(reg_a, clk, a_ff); 29 | ff ff_b(reg_b, clk, b_ff); 30 | and2 a2 (a_ff, b_ff, c); 31 | ff ff_c(c, clk, Q); 32 | endmodule 33 | -------------------------------------------------------------------------------- /tests/Testcases/and2_reg/rtl/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module ff(D,clk,Q); 8 | input logic D, clk; 9 | output reg Q; 10 | always @(posedge clk) 11 | begin 12 | Q <= D; 13 | end 14 | endmodule 15 | 16 | module and2(a,b,c); 17 | input wire a, b; 18 | output wire c; 19 | 20 | assign c = a & b; 21 | 22 | endmodule 23 | 24 | 25 | module reg_and2(reg_a,reg_b,clk,Q); 26 | input logic reg_a, reg_b, clk; 27 | output reg Q; 28 | ff ff_a(reg_a, clk, a_ff); 29 | ff ff_b(reg_b, clk, b_ff); 30 | and2 a2 (a_ff, b_ff, c); 31 | ff ff_c(c, clk, Q); 32 | endmodule 33 | -------------------------------------------------------------------------------- /tests/Testcases/and2_repack_constraints/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 2.5 clki 3 | create_clock -period 2.5 clko 4 | set_input_delay 1 -clock clki [get_ports {reg_*}] 5 | set_output_delay 1 -clock clko [get_ports {Q}] 6 | -------------------------------------------------------------------------------- /tests/Testcases/and2_repack_constraints/pin.sdc: -------------------------------------------------------------------------------- 1 | set_property mode Mode_BP_SDR_A_RX HP_1_CC_28_14P 2 | set_pin_loc a HP_1_CC_28_14P 3 | 4 | set_property mode Mode_BP_SDR_A_RX HP_1_26_13P 5 | set_pin_loc b HP_1_26_13P 6 | 7 | set_property mode Mode_BP_SDR_A_TX HP_1_24_12P 8 | set_pin_loc c HP_1_24_12P 9 | -------------------------------------------------------------------------------- /tests/Testcases/and2_repack_constraints/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_property mode Mode_BP_SDR_A_RX HR_2_0_0P 2 | set_pin_loc reg_a HR_2_0_0P 3 | 4 | set_property mode Mode_BP_SDR_A_RX HR_3_0_0P 5 | set_pin_loc reg_b HR_3_0_0P 6 | 7 | set_property mode Mode_BP_SDR_A_TX HR_5_0_0P 8 | set_pin_loc Q HR_5_0_0P 9 | 10 | set_clock_pin -device_clock clk[8] -design_clock clki 11 | set_clock_pin -device_clock clk[9] -design_clock clko 12 | -------------------------------------------------------------------------------- /tests/Testcases/and2_repack_constraints/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2_repack_constr 3 | add_design_file ./rtl/and2.sv 4 | set_top_module reg_and2 5 | add_constraint_file pin_mapping.pin 6 | add_constraint_file constraints.sdc 7 | 8 | # Device target 9 | target_device GEMINI_COMPACT_10x8 10 | # Compilation 11 | analyze 12 | synthesize delay 13 | packing 14 | place 15 | route 16 | sta 17 | bitstream 18 | -------------------------------------------------------------------------------- /tests/Testcases/and2_repack_constraints/rtl/and2.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module ff(D,clk,Q); 8 | input logic D, clk; 9 | output reg Q; 10 | always @(posedge clk) 11 | begin 12 | Q <= D; 13 | end 14 | endmodule 15 | 16 | module and2(a,b,c); 17 | input wire a, b; 18 | output wire c; 19 | 20 | assign c = a & b; 21 | 22 | endmodule 23 | 24 | 25 | module reg_and2(reg_a,reg_b,clki,clko,Q); 26 | input logic reg_a, reg_b, clki, clko; 27 | output reg Q; 28 | ff ff_a(reg_a, clki, a_ff); 29 | ff ff_b(reg_b, clki, b_ff); 30 | and2 a2 (a_ff, b_ff, c); 31 | ff ff_c(c, clko, Q); 32 | endmodule 33 | -------------------------------------------------------------------------------- /tests/Testcases/and2_repack_constraints/rtl/and2.sv~: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module ff(D,clk,Q); 8 | input logic D, clk; 9 | output reg Q; 10 | always @(posedge clk) 11 | begin 12 | Q <= D; 13 | end 14 | endmodule 15 | 16 | module and2(a,b,c); 17 | input wire a, b; 18 | output wire c; 19 | 20 | assign c = a & b; 21 | 22 | endmodule 23 | 24 | 25 | module reg_and2(reg_a,reg_b,clk,Q); 26 | input logic reg_a, reg_b, clk; 27 | output reg Q; 28 | ff ff_a(reg_a, clk, a_ff); 29 | ff ff_b(reg_b, clk, b_ff); 30 | and2 a2 (a_ff, b_ff, c); 31 | ff ff_c(c, clk, Q); 32 | endmodule 33 | -------------------------------------------------------------------------------- /tests/Testcases/and2_repack_constraints/rtl/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module ff(D,clk,Q); 8 | input logic D, clk; 9 | output reg Q; 10 | always @(posedge clk) 11 | begin 12 | Q <= D; 13 | end 14 | endmodule 15 | 16 | module and2(a,b,c); 17 | input wire a, b; 18 | output wire c; 19 | 20 | assign c = a & b; 21 | 22 | endmodule 23 | 24 | 25 | module reg_and2(reg_a,reg_b,clk,Q); 26 | input logic reg_a, reg_b, clk; 27 | output reg Q; 28 | ff ff_a(reg_a, clk, a_ff); 29 | ff ff_b(reg_b, clk, b_ff); 30 | and2 a2 (a_ff, b_ff, c); 31 | ff ff_c(c, clk, Q); 32 | endmodule 33 | -------------------------------------------------------------------------------- /tests/Testcases/and2_testcase/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | # create_clock -period 7.935999999999999 clk (actual clock) 3 | create_clock -period 7.935999999999999 clk 4 | set_input_delay 1 -clock clk [get_ports {*}] 5 | set_output_delay 1 -clock clk [get_ports {*}] 6 | 7 | -------------------------------------------------------------------------------- /tests/Testcases/and2_testcase/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2 3 | add_design_file -V_2001 ./rtl/and2.v 4 | set_top_module and2 5 | add_constraint_file constraints.sdc 6 | 7 | # Device target 8 | target_device MPW1 9 | set_device_size 4x4 10 | 11 | # Compilation 12 | synthesize delay 13 | packing 14 | place 15 | route 16 | sta 17 | bitstream force 18 | -------------------------------------------------------------------------------- /tests/Testcases/and2_testcase/rtl/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | a, 9 | b, 10 | c); 11 | 12 | input wire a; 13 | input wire b; 14 | output wire c; 15 | 16 | assign c = a & b; 17 | 18 | endmodule -------------------------------------------------------------------------------- /tests/Testcases/and2_testcase/verilog.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2VErilog 3 | add_design_file -V_2001 ./rtl/and2.v 4 | set_top_module and2 5 | add_constraint_file constraints.sdc 6 | 7 | # Device target 8 | target_device MPW1 9 | set_device_size 4x4 10 | 11 | # Compilation 12 | synthesize delay 13 | pnr_netlist_lang verilog 14 | packing 15 | place 16 | route 17 | sta 18 | bitstream force 19 | -------------------------------------------------------------------------------- /tests/Testcases/and2_testcase_no_pcf/constraints.sdc: -------------------------------------------------------------------------------- 1 | # intentionally provide no pin constraint here. 2 | # in such case, raptor should generate a default constraint file to make sure vpr only use legal pins in device to connect user's design ports. 3 | # legal pins are pins inside fpga which are actually wired to top level bump pin of device package. 4 | -------------------------------------------------------------------------------- /tests/Testcases/and2_testcase_no_pcf/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2 3 | add_design_file -V_2001 ./rtl/and2.v 4 | set_top_module and2 5 | add_constraint_file constraints.sdc 6 | 7 | # Device target 8 | target_device MPW1 9 | set_device_size 4x4 10 | 11 | # Compilation 12 | synthesize delay 13 | packing 14 | place 15 | route 16 | sta 17 | bitstream force 18 | -------------------------------------------------------------------------------- /tests/Testcases/and2_testcase_no_pcf/rtl/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | a, 9 | b, 10 | c); 11 | 12 | input wire a; 13 | input wire b; 14 | output wire c; 15 | 16 | assign c = a & b; 17 | 18 | endmodule -------------------------------------------------------------------------------- /tests/Testcases/and2_vec/Src/and2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // and2_verilog // 5 | // and2.v - Top-level file of simple 2-input AND gate // 6 | //////////////////////////////////////////////////////// 7 | 8 | module and2 ( 9 | input [1:0] a, 10 | input [1:0] b, 11 | input clk, 12 | input reset, 13 | output reg [1:0] c = 2'b0 14 | ); 15 | 16 | reg [1:0] a_reg = 2'b0; 17 | reg [1:0] b_reg = 2'b0; 18 | 19 | always@(posedge clk) 20 | if (reset) begin 21 | a_reg <= 2'b0; 22 | b_reg <= 2'b0; 23 | c <= 2'b0; 24 | end else begin 25 | a_reg <= a; 26 | b_reg <= b; 27 | c <= a_reg & b_reg; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /tests/Testcases/and2_vec/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 200 MHz (5nS period) 4 | create_clock -period 5 clk 5 | set_input_delay -max 0 -clock clk [get_ports {a}] 6 | set_input_delay -max 0 -clock clk [get_ports {b}] 7 | set_input_delay -max 0 -clock clk [get_ports {reset}] 8 | set_output_delay -max 0 -clock clk [get_ports {c}] 9 | 10 | -------------------------------------------------------------------------------- /tests/Testcases/and2_vec/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_pin_loc {a[0]} HP_1_1_0N 2 | set_pin_loc {b[0]} HP_1_2_1P 3 | set_pin_loc reset HP_1_3_1N 4 | set_pin_loc {c[0]} HP_1_2_1P 5 | set_pin_loc clk HP_1_CC_18_9P 6 | 7 | -------------------------------------------------------------------------------- /tests/Testcases/and2_vec/readme_and2_verilog.txt: -------------------------------------------------------------------------------- 1 | and2_verilog 2 | ============ 3 | 4 | Description 5 | ----------- 6 | This is a simple design consisting of a registered, 2-input AND-gate constrained to a 200 MHz clock. This example includes a Verilog testbench and executes an RTL simulation using the Icarus Verilog simulator prior to compiling design in the Raptor software. 7 | 8 | 9 | Files 10 | ----- 11 | Src/and2.v - Top-level design file containing and2 module 12 | Src/testbench_and2.v - Simulation testbench for and2 13 | constraints.sdc - Timing constraints file for and2 14 | run_raptor.tcl - TCL file to create and execute project 15 | gtkwave.tcl - TCL script to view simulation results in gtwwave viewer 16 | 17 | 18 | Running the Design 19 | ------------------ 20 | The design can be run in one of three ways: 21 | 22 | Intereactive GUI: 23 | raptor 24 | Then create the project using the following steps: 25 | New Project - Project Name: and2 26 | Type of Project: RTL Project 27 | Add Design Files: Add Src/and2.v 28 | Add Simulation Files: Add Src/testbench_and2.v 29 | Add Design Constraints: constraints.sdc 30 | Select target Design: Any device you like 31 | Start Compilation of the Design 32 | Once the run has completed, to view the simulation waveform: 33 | gtkwave -S gtkwave.tcl 34 | 35 | 36 | Automated GUI: 37 | raptor --script run_raptor.tcl 38 | Once the run has completed, to view the simulation waveform: 39 | gtkwave -S gtkwave.tcl 40 | 41 | 42 | Automated Command-line: 43 | raptor --script run_raptor.tcl --batch 44 | 45 | -------------------------------------------------------------------------------- /tests/Testcases/and2_vec/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # and2_verilog - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name and2_vec 10 | 11 | message "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file -V_2001 ./Src/and2.v 14 | # Top-module can automatically be indentified or implicitly specified here 15 | set_top_module and2 16 | add_constraint_file constraints.sdc 17 | add_constraint_file pin_mapping.pin 18 | # Simulation 19 | add_simulation_file ./Src/testbench_and2.v 20 | set_top_testbench testbench_and2 21 | # Device target 22 | target_device GEMINI_COMPACT_22x4 23 | 24 | # RTL Simulation 25 | simulate rtl icarus 26 | 27 | #wave_open and2/and2.vcd 28 | #wave_show reset 29 | #wave_show clk 30 | #wave_show a 31 | #wave_show b 32 | #wave_show a_delay_by_2 33 | #wave_show b_delay_by_2 34 | #wave_show c 35 | #wave_cmd gtkwave::/Time/Zoom/Zoom_Full 36 | 37 | # Compilation 38 | message "Compiling $project_name..." 39 | analyze 40 | 41 | synthesize delay 42 | 43 | # Gate Simulation 44 | simulate gate icarus 45 | 46 | packing 47 | place 48 | route 49 | 50 | # Post PnR Simulation 51 | simulate timed_pnr icarus 52 | 53 | sta 54 | power 55 | bitstream 56 | 57 | message "Completed $project_name...\n" 58 | -------------------------------------------------------------------------------- /tests/Testcases/and2_verilog/Src/and2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // and2_verilog // 5 | // and2.v - Top-level file of simple 2-input AND gate // 6 | //////////////////////////////////////////////////////// 7 | 8 | module Llatch( input D, input G, output reg Q); 9 | 10 | always @* 11 | if (G == 1'b1) 12 | Q <= D; 13 | else 14 | Q<=Q; 15 | 16 | endmodule 17 | 18 | module and2 ( 19 | input a, 20 | input b, 21 | input clk, 22 | input reset, 23 | output reg c = 1'b0, 24 | output wire Q 25 | ); 26 | 27 | reg a_reg, b_reg = 1'b0; 28 | 29 | Llatch my (a,b, Q); 30 | 31 | 32 | 33 | always@(posedge clk) 34 | if (reset) begin 35 | a_reg <= 1'b0; 36 | b_reg <= 1'b0; 37 | c <= 1'b0; 38 | end else begin 39 | a_reg <= a; 40 | b_reg <= b; 41 | c <= a_reg & b_reg; 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /tests/Testcases/and2_verilog/and2_part.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /tests/Testcases/and2_verilog/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 200 MHz (5nS period) 4 | create_clock -period 5 clk 5 | set_input_delay 0.8 -clock clk [get_ports {a}] 6 | set_input_delay 0.8 -clock clk [get_ports {b}] 7 | 8 | -------------------------------------------------------------------------------- /tests/Testcases/and2_verilog/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_property mode Mode_BP_SDR_A_RX HR_1_0_0P 2 | set_pin_loc a HR_1_0_0P 3 | 4 | set_property mode Mode_BP_SDR_A_RX HR_3_0_0P 5 | set_pin_loc b HR_3_0_0P 6 | 7 | set_property mode Mode_BP_SDR_A_TX HR_3_2_1P 8 | set_pin_loc c HR_3_2_1P 9 | -------------------------------------------------------------------------------- /tests/Testcases/and2_verilog/readme_and2_verilog.txt: -------------------------------------------------------------------------------- 1 | and2_verilog 2 | ============ 3 | 4 | Description 5 | ----------- 6 | This is a simple design consisting of a registered, 2-input AND-gate constrained to a 200 MHz clock. This example includes a Verilog testbench and executes an RTL simulation using the Icarus Verilog simulator prior to compiling design in the Raptor software. 7 | 8 | 9 | Files 10 | ----- 11 | Src/and2.v - Top-level design file containing and2 module 12 | Src/testbench_and2.v - Simulation testbench for and2 13 | constraints.sdc - Timing constraints file for and2 14 | run_raptor.tcl - TCL file to create and execute project 15 | gtkwave.tcl - TCL script to view simulation results in gtwwave viewer 16 | 17 | 18 | Running the Design 19 | ------------------ 20 | The design can be run in one of three ways: 21 | 22 | Intereactive GUI: 23 | raptor 24 | Then create the project using the following steps: 25 | New Project - Project Name: and2 26 | Type of Project: RTL Project 27 | Add Design Files: Add Src/and2.v 28 | Add Simulation Files: Add Src/testbench_and2.v 29 | Add Design Constraints: constraints.sdc 30 | Select target Design: Any device you like 31 | Start Compilation of the Design 32 | Once the run has completed, to view the simulation waveform: 33 | gtkwave -S gtkwave.tcl 34 | 35 | 36 | Automated GUI: 37 | raptor --script run_raptor.tcl 38 | Once the run has completed, to view the simulation waveform: 39 | gtkwave -S gtkwave.tcl 40 | 41 | 42 | Automated Command-line: 43 | raptor --script run_raptor.tcl --batch 44 | 45 | -------------------------------------------------------------------------------- /tests/Testcases/and2_verilog/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # and2_verilog - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name and2 10 | 11 | message "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file -V_2001 ./Src/and2.v 14 | # Top-module can automatically be indentified or implicitly specified here 15 | set_top_module and2 16 | add_constraint_file pin_mapping.pin 17 | add_constraint_file constraints.sdc 18 | # Simulation 19 | #add_simulation_file -SV_2012 ./Src/testbench_and2.v 20 | #set_top_testbench testbench_and2 21 | # Device target 22 | target_device GEMINI_COMPACT_10x8 23 | 24 | # RTL Simulation 25 | #simulate rtl icarus 26 | 27 | #wave_open and2/and2.vcd 28 | #wave_show reset 29 | #wave_show clk 30 | #wave_show a 31 | #wave_show b 32 | #wave_show a_delay_by_2 33 | #wave_show b_delay_by_2 34 | #wave_show c 35 | #wave_cmd gtkwave::/Time/Zoom/Zoom_Full 36 | 37 | # Compilation 38 | message "Compiling $project_name..." 39 | 40 | analyze 41 | #synth_options -inferred_io 42 | 43 | synthesize delay 44 | 45 | setup_lec_sim 20 46 | 47 | simulate gate icarus 48 | #pnr_options --read_vpr_constraints and2_part.xml 49 | packing 50 | place 51 | route 52 | sta 53 | power 54 | simulate timed_pnr icarus 55 | bitstream 56 | 57 | message "Completed $project_name...\n" 58 | -------------------------------------------------------------------------------- /tests/Testcases/and2_wio/Src/and2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // and2_verilog // 5 | // and2.v - Top-level file of simple 2-input AND gate // 6 | //////////////////////////////////////////////////////// 7 | 8 | module and2 ( 9 | input a, 10 | input b, 11 | input clk, 12 | input reset, 13 | output reg c = 1'b0 14 | ); 15 | 16 | reg a_reg, b_reg = 1'b0; 17 | 18 | always@(posedge clk) 19 | if (reset) begin 20 | a_reg <= 1'b0; 21 | b_reg <= 1'b0; 22 | c <= 1'b0; 23 | end else begin 24 | a_reg <= a; 25 | b_reg <= b; 26 | c <= a_reg & b_reg; 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /tests/Testcases/and2_wio/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 200 MHz (5nS period) 4 | create_clock -period 5 clk 5 | set_input_delay -max 0 -clock clk [get_ports {a}] 6 | set_input_delay -max 0 -clock clk [get_ports {b}] 7 | set_input_delay -max 0 -clock clk [get_ports {reset}] 8 | set_output_delay -max 0 -clock clk [get_ports {c}] 9 | 10 | -------------------------------------------------------------------------------- /tests/Testcases/and2_wio/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_pin_loc a HP_1_1_0N 2 | set_pin_loc b HP_1_2_1P 3 | set_pin_loc reset HP_1_3_1N 4 | set_pin_loc c HP_1_2_1P 5 | set_pin_loc clk HP_1_CC_18_9P 6 | -------------------------------------------------------------------------------- /tests/Testcases/and2_wio/readme_and2_verilog.txt: -------------------------------------------------------------------------------- 1 | and2_verilog 2 | ============ 3 | 4 | Description 5 | ----------- 6 | This is a simple design consisting of a registered, 2-input AND-gate constrained to a 200 MHz clock. This example includes a Verilog testbench and executes an RTL simulation using the Icarus Verilog simulator prior to compiling design in the Raptor software. 7 | 8 | 9 | Files 10 | ----- 11 | Src/and2.v - Top-level design file containing and2 module 12 | Src/testbench_and2.v - Simulation testbench for and2 13 | constraints.sdc - Timing constraints file for and2 14 | run_raptor.tcl - TCL file to create and execute project 15 | gtkwave.tcl - TCL script to view simulation results in gtwwave viewer 16 | 17 | 18 | Running the Design 19 | ------------------ 20 | The design can be run in one of three ways: 21 | 22 | Intereactive GUI: 23 | raptor 24 | Then create the project using the following steps: 25 | New Project - Project Name: and2 26 | Type of Project: RTL Project 27 | Add Design Files: Add Src/and2.v 28 | Add Simulation Files: Add Src/testbench_and2.v 29 | Add Design Constraints: constraints.sdc 30 | Select target Design: Any device you like 31 | Start Compilation of the Design 32 | Once the run has completed, to view the simulation waveform: 33 | gtkwave -S gtkwave.tcl 34 | 35 | 36 | Automated GUI: 37 | raptor --script run_raptor.tcl 38 | Once the run has completed, to view the simulation waveform: 39 | gtkwave -S gtkwave.tcl 40 | 41 | 42 | Automated Command-line: 43 | raptor --script run_raptor.tcl --batch 44 | 45 | -------------------------------------------------------------------------------- /tests/Testcases/and2_wio/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # and2_verilog - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name and2_wio 10 | 11 | message "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file -V_2001 ./Src/and2.v 14 | # Top-module can automatically be indentified or implicitly specified here 15 | set_top_module and2 16 | add_constraint_file constraints.sdc 17 | add_constraint_file pin_mapping.pin 18 | # Simulation 19 | add_simulation_file ./Src/testbench_and2.v 20 | set_top_testbench testbench_and2 21 | # Device target 22 | target_device GEMINI_COMPACT_22x4 23 | 24 | # RTL Simulation 25 | simulate rtl icarus 26 | 27 | #wave_open and2/and2.vcd 28 | #wave_show reset 29 | #wave_show clk 30 | #wave_show a 31 | #wave_show b 32 | #wave_show a_delay_by_2 33 | #wave_show b_delay_by_2 34 | #wave_show c 35 | #wave_cmd gtkwave::/Time/Zoom/Zoom_Full 36 | 37 | # Compilation 38 | message "Compiling $project_name..." 39 | analyze 40 | 41 | synth_options -inferred_io 42 | synthesize delay 43 | 44 | # Gate Simulation 45 | simulate gate icarus 46 | 47 | packing 48 | place 49 | route 50 | 51 | # Post PnR Simulation 52 | simulate pnr icarus 53 | 54 | sta 55 | power 56 | bitstream 57 | 58 | message "Completed $project_name...\n" 59 | -------------------------------------------------------------------------------- /tests/Testcases/auto_testbench/GJC1.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: flop to flop path 3 | // Author: George Chen 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | 8 | module GJC1( 9 | din, 10 | dout, 11 | clk); 12 | 13 | input din; 14 | input clk; 15 | output reg dout; 16 | 17 | reg q1 ; 18 | 19 | 20 | always @(posedge clk) 21 | begin 22 | q1 <= din ; 23 | end 24 | 25 | always @(posedge clk) 26 | begin 27 | dout <= q1 ; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /tests/Testcases/auto_testbench/raptor_lec.tcl: -------------------------------------------------------------------------------- 1 | create_design GJC1_design 2 | 3 | target_device GEMINI_COMPACT_22x4 4 | 5 | add_design_file GJC1.v 6 | set_top_module GJC1 7 | 8 | analyze 9 | 10 | synthesize delay 11 | 12 | # Setup simulation with auto-testbench "RTL vs gate" and "RTL vs pnr" 13 | setup_lec_sim 14 | 15 | # Simulate RTL vs gate 16 | simulation_options compilation icarus gate 17 | simulate gate icarus 18 | 19 | packing 20 | place 21 | route 22 | 23 | # Simulate RTL vs post-pnr 24 | simulation_options compilation icarus pnr 25 | simulate pnr icarus 26 | 27 | sta 28 | power 29 | bitstream 30 | -------------------------------------------------------------------------------- /tests/Testcases/auto_testbench/raptor_tcl.tcl: -------------------------------------------------------------------------------- 1 | create_design GJC1_design 2 | 3 | target_device GEMINI_COMPACT_22x4 4 | 5 | add_design_file GJC1.v 6 | set_top_module GJC1 7 | 8 | analyze 9 | 10 | synthesize delay 11 | 12 | # auto-testbench generation 13 | auto_testbench 14 | 15 | # Add simulation files 16 | # 1) Generated testbench: 17 | add_simulation_file ./sim/co_sim_tb/co_sim_[get_top_module].v 18 | # 2) RTL design: 19 | add_simulation_file GJC1.v 20 | 21 | # Set top testbench name to auto-generated name 22 | set_top_testbench co_sim_[get_top_module] 23 | 24 | # Edit post-synth netlist to run co-simulation RTL vs post-synth netlist 25 | rename_module_in_netlist post_synth 26 | 27 | # Simulate RTL vs gate 28 | simulation_options compilation icarus gate 29 | simulate gate icarus 30 | 31 | packing 32 | place 33 | route 34 | 35 | # Edit PnR wrapper netlist to run co-simulation RTL vs post-pnr netlist 36 | rename_module_in_netlist post_pnr 37 | 38 | # Simulate RTL vs post-pnr 39 | simulation_options compilation icarus pnr 40 | simulate pnr icarus 41 | 42 | sta 43 | power 44 | bitstream 45 | -------------------------------------------------------------------------------- /tests/Testcases/constant/add__a_to_output.v: -------------------------------------------------------------------------------- 1 | module add__a_to_output (output wire out); 2 | and_out a1(.a(1'b1),.b(1'b1),.out(out)); 3 | endmodule 4 | 5 | module and_out (input a,input b,output out); 6 | 7 | assign out=a & b; 8 | endmodule -------------------------------------------------------------------------------- /tests/Testcases/constant/raptor.tcl: -------------------------------------------------------------------------------- 1 | create_design add__a_to_output 2 | target_device GEMINI_COMPACT_10x8 3 | add_include_path ./rtl 4 | add_library_path ./rtl 5 | add_library_ext .v .sv 6 | add_design_file add__a_to_output.v 7 | set_top_module add__a_to_output 8 | synthesize delay 9 | 10 | 11 | add_simulation_file -SV_2012 tb.v 12 | set_top_testbench tb 13 | 14 | simulate gate icarus syn_tb_pnr.fst 15 | 16 | packing 17 | global_placement 18 | place 19 | route 20 | power 21 | simulate pnr icarus syn_tb_pnr.fst 22 | 23 | bitstream 24 | -------------------------------------------------------------------------------- /tests/Testcases/constant/tb.v: -------------------------------------------------------------------------------- 1 | module tb(); 2 | wire out; 3 | 4 | add__a_to_output dut(out); 5 | initial begin 6 | #1 7 | $display("out=%d", out); 8 | 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /tests/Testcases/counter/constraints.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 2.5 clock0 2 | set_input_delay 1 -clock clock0 [get_ports {*}] 3 | set_output_delay 1 -clock clock0 [get_ports {*}] 4 | -------------------------------------------------------------------------------- /tests/Testcases/counter/counter.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design counter 3 | add_design_file -V_2001 counter.v 4 | set_top_module counter 5 | add_constraint_file constraints.sdc 6 | 7 | # Device target 8 | target_device GEMINI_COMPACT_10x8 9 | 10 | analyze 11 | # Compilation 12 | synth_options -effort high -carry all 13 | synthesize delay 14 | pin_loc_assign_method free 15 | packing 16 | place 17 | route 18 | sta 19 | bitstream 20 | -------------------------------------------------------------------------------- /tests/Testcases/counter/counter.v: -------------------------------------------------------------------------------- 1 | module counter (clock0, reset, result); 2 | 3 | input clock0; 4 | input reset; 5 | output [31:0] result; 6 | 7 | reg [31:0] result; 8 | 9 | initial begin 10 | result <= 0; 11 | end 12 | 13 | always @(posedge clock0) 14 | begin 15 | if (reset) 16 | result = 0; 17 | else 18 | result = result + 1; 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /tests/Testcases/counter16/counter16.tcl: -------------------------------------------------------------------------------- 1 | # module load fpga_tools/raptor/latest 2 | # raptor --batch --script build.tcl 3 | create_design counter16 4 | add_design_file -V_2001 counter16.v 5 | set_top_module counter16 6 | add_constraint_file pin_mapping.pin 7 | 8 | target_device GEMINI_COMPACT_22x4 9 | 10 | analyze 11 | set_limits dsp 0 12 | synthesize delay 13 | packing 14 | place 15 | route 16 | sta 17 | #bitstream enable_simulation 18 | bitstream 19 | -------------------------------------------------------------------------------- /tests/Testcases/counter16/counter16.v: -------------------------------------------------------------------------------- 1 | module counter16 (clock0,reset,op,q); 2 | input clock0; 3 | input reset; 4 | input op; 5 | output [15:0] q; 6 | reg [15:0] q; 7 | 8 | always @ (posedge clock0) 9 | begin 10 | if (reset) 11 | q <= 'd0; 12 | else if (op=='d1) 13 | q <= q[7:0] * q[15:8]; 14 | else 15 | q <= q+'d1; 16 | end 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /tests/Testcases/counter16/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_pin_loc reset HP_1_1_0N 2 | set_pin_loc {q[0]} HP_1_2_1P 3 | set_pin_loc op HP_1_3_1N 4 | set_pin_loc clock0 HP_1_CC_18_9P 5 | -------------------------------------------------------------------------------- /tests/Testcases/counter_mixed/UP_COUNTER.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | -- FPGA projects using Verilog code VHDL code 5 | -- fpga4student.com: FPGA projects, Verilog projects, VHDL projects 6 | -- VHDL project: VHDL code for counters with testbench 7 | -- VHDL project: VHDL code for up counter 8 | entity UP_COUNTER is 9 | Port ( clock0: in std_logic; -- clock input 10 | reset: in std_logic; -- reset input 11 | counter: out std_logic_vector(3 downto 0) -- output 4-bit counter 12 | ); 13 | end UP_COUNTER; 14 | 15 | architecture Behavioral of UP_COUNTER is 16 | signal counter_up: std_logic_vector(3 downto 0); 17 | begin 18 | -- up counter 19 | process(clock0) 20 | begin 21 | if(rising_edge(clock0)) then 22 | if(reset='1') then 23 | counter_up <= x"0"; 24 | else 25 | counter_up <= counter_up + x"1"; 26 | end if; 27 | end if; 28 | end process; 29 | counter <= counter_up; 30 | 31 | end Behavioral; 32 | -------------------------------------------------------------------------------- /tests/Testcases/counter_mixed/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 2.5 clock0 3 | set_input_delay 1 -clock clock0 [get_ports {reset}] 4 | set_output_delay 1 -clock clock0 [get_ports {counter}] 5 | -------------------------------------------------------------------------------- /tests/Testcases/counter_mixed/counter.v: -------------------------------------------------------------------------------- 1 | module counter (input wire clock0, input wire reset, output wire [3:0] out); 2 | 3 | 4 | UP_COUNTER inst (clock0, reset, out); 5 | 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /tests/Testcases/counter_mixed/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_pin_loc {out[0]} HP_1_1_0N 2 | set_pin_loc {out[1]} HP_1_2_1P 3 | set_pin_loc {out[2]} HP_1_3_1N 4 | set_pin_loc {out[3]} HP_1_4_2P 5 | 6 | set_pin_loc reset HP_1_5_2N 7 | set_pin_loc clock0 HP_1_CC_18_9P 8 | 9 | -------------------------------------------------------------------------------- /tests/Testcases/counter_mixed/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design counter_mixed 3 | add_design_file -VHDL_1993 UP_COUNTER.vhd 4 | add_design_file -SV_2012 counter.v 5 | set_top_module counter 6 | add_constraint_file pin_mapping.pin 7 | add_constraint_file constraints.sdc 8 | 9 | # Testbench 10 | add_simulation_file -VHDL_1993 testbench.vhd 11 | set_top_testbench tb_counters 12 | 13 | # Device target 14 | target_device GEMINI_COMPACT_22x4 15 | 16 | # Compilation/Simulation 17 | analyze 18 | 19 | # RTL Simulation 20 | simulation_options "ghdl" "simulation" "--stop-time=1000ns" 21 | #simulate "rtl" "ghdl" syn_tb_rtl.fst 22 | 23 | # Synthesis 24 | parser_type ghdl 25 | #pnr_netlist_lang vhdl 26 | synthesize delay 27 | 28 | # Post-Synthesis gate-level Simulation 29 | #simulate "gate" "ghdl" syn_tb_gate.fst 30 | 31 | # Pack/Place/Route 32 | packing 33 | place 34 | route 35 | 36 | # Post-Route Simulation 37 | #simulate pnr ghdl syn_tb_pnr.fst 38 | 39 | # Static Timing Analysis 40 | sta 41 | 42 | # Bitstream Generation 43 | bitstream 44 | -------------------------------------------------------------------------------- /tests/Testcases/counter_mixed/testbench.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | -- FPGA projects using Verilog code VHDL code 4 | -- fpga4student.com: FPGA projects, Verilog projects, VHDL projects 5 | -- VHDL project: VHDL code for counters with testbench 6 | -- VHDL project: Testbench VHDL code for up counter 7 | entity tb_counters is 8 | end tb_counters; 9 | 10 | architecture Behavioral of tb_counters is 11 | 12 | component UP_COUNTER 13 | Port ( clock0: in std_logic; -- clock input 14 | reset: in std_logic; -- reset input 15 | counter: out std_logic_vector(3 downto 0) -- output 4-bit counter 16 | ); 17 | end component; 18 | signal reset,clk: std_logic; 19 | signal counter:std_logic_vector(3 downto 0); 20 | 21 | begin 22 | dut: UP_COUNTER port map (clock0 => clk, reset=>reset, counter => counter); 23 | -- Clock process definitions 24 | clock_process :process 25 | begin 26 | clk <= '0'; 27 | wait for 10 ns; 28 | clk <= '1'; 29 | wait for 10 ns; 30 | end process; 31 | 32 | 33 | -- Stimulus process 34 | stim_proc: process 35 | begin 36 | -- hold reset state for 100 ns. 37 | reset <= '1'; 38 | wait for 20 ns; 39 | reset <= '0'; 40 | wait; 41 | end process; 42 | end Behavioral; 43 | -------------------------------------------------------------------------------- /tests/Testcases/counter_vhdl/UP_COUNTER.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | -- FPGA projects using Verilog code VHDL code 5 | -- fpga4student.com: FPGA projects, Verilog projects, VHDL projects 6 | -- VHDL project: VHDL code for counters with testbench 7 | -- VHDL project: VHDL code for up counter 8 | entity UP_COUNTER is 9 | Port ( clock0: in std_logic; -- clock input 10 | reset: in std_logic; -- reset input 11 | counter: out std_logic_vector(3 downto 0) -- output 4-bit counter 12 | ); 13 | end UP_COUNTER; 14 | 15 | architecture Behavioral of UP_COUNTER is 16 | signal counter_up: std_logic_vector(3 downto 0); 17 | begin 18 | -- up counter 19 | process(clock0) 20 | begin 21 | if(rising_edge(clock0)) then 22 | if(reset='1') then 23 | counter_up <= x"0"; 24 | else 25 | counter_up <= counter_up + x"1"; 26 | end if; 27 | end if; 28 | end process; 29 | counter <= counter_up; 30 | 31 | end Behavioral; 32 | -------------------------------------------------------------------------------- /tests/Testcases/counter_vhdl/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 2.5 clock0 3 | set_input_delay 1 -clock clock0 [get_ports {reset}] 4 | set_output_delay 1 -clock clock0 [get_ports {counter}] 5 | -------------------------------------------------------------------------------- /tests/Testcases/counter_vhdl/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_pin_loc {counter[0]} HP_1_1_0N 2 | set_pin_loc {counter[1]} HP_1_2_1P 3 | set_pin_loc {counter[2]} HP_1_3_1N 4 | set_pin_loc {counter[3]} HP_1_4_2P 5 | 6 | set_pin_loc reset HP_1_5_2N 7 | set_pin_loc clock0 HP_1_CC_18_9P 8 | 9 | -------------------------------------------------------------------------------- /tests/Testcases/counter_vhdl/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design counter_vhdl_gemini 3 | add_design_file -VHDL_1993 UP_COUNTER.vhd 4 | set_top_module UP_COUNTER 5 | add_constraint_file pin_mapping.pin 6 | add_constraint_file constraints.sdc 7 | 8 | # Testbench 9 | add_simulation_file -VHDL_1993 testbench.vhd 10 | set_top_testbench tb_counters 11 | 12 | # Device target 13 | target_device GEMINI_COMPACT_22x4 14 | 15 | # Compilation/Simulation 16 | analyze 17 | 18 | # RTL Simulation 19 | simulation_options "ghdl" "simulation" "--stop-time=1000ns" 20 | simulate "rtl" "ghdl" syn_tb_rtl.fst 21 | 22 | # Synthesis 23 | parser_type ghdl 24 | pnr_netlist_lang vhdl 25 | synth_options -inferred_io 26 | synthesize delay 27 | 28 | # Post-Synthesis gate-level Simulation 29 | simulate "gate" "ghdl" syn_tb_gate.fst 30 | 31 | # Pack/Place/Route 32 | packing 33 | place 34 | route 35 | 36 | # Post-Route Simulation 37 | #simulate pnr ghdl syn_tb_pnr.fst 38 | 39 | # Static Timing Analysis 40 | sta 41 | 42 | # Bitstream Generation 43 | bitstream 44 | -------------------------------------------------------------------------------- /tests/Testcases/counter_vhdl/testbench.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | -- FPGA projects using Verilog code VHDL code 4 | -- fpga4student.com: FPGA projects, Verilog projects, VHDL projects 5 | -- VHDL project: VHDL code for counters with testbench 6 | -- VHDL project: Testbench VHDL code for up counter 7 | entity tb_counters is 8 | end tb_counters; 9 | 10 | architecture Behavioral of tb_counters is 11 | 12 | component UP_COUNTER 13 | Port ( clock0: in std_logic; -- clock input 14 | reset: in std_logic; -- reset input 15 | counter: out std_logic_vector(3 downto 0) -- output 4-bit counter 16 | ); 17 | end component; 18 | signal reset,clk: std_logic; 19 | signal counter:std_logic_vector(3 downto 0); 20 | 21 | begin 22 | dut: UP_COUNTER port map (clock0 => clk, reset=>reset, counter => counter); 23 | -- Clock process definitions 24 | clock_process :process 25 | begin 26 | clk <= '0'; 27 | wait for 10 ns; 28 | clk <= '1'; 29 | wait for 10 ns; 30 | end process; 31 | 32 | 33 | -- Stimulus process 34 | stim_proc: process 35 | begin 36 | -- hold reset state for 100 ns. 37 | reset <= '1'; 38 | wait for 20 ns; 39 | reset <= '0'; 40 | wait; 41 | end process; 42 | end Behavioral; 43 | -------------------------------------------------------------------------------- /tests/Testcases/device_size_negative/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 2.5 clk 3 | set_input_delay 1 -clock clk [get_ports {*}] 4 | set_output_delay 1 -clock clk [get_ports {*}] 5 | 6 | set_property mode Mode_BP_SDR_A_RX HP_1_CC_28_14P 7 | set_pin_loc a HP_1_CC_28_14P 8 | 9 | set_property mode Mode_BP_SDR_A_RX HP_1_26_13P 10 | set_pin_loc b HP_1_26_13P 11 | 12 | set_property mode Mode_BP_SDR_A_TX HP_1_24_12P 13 | set_pin_loc c HP_1_24_12P 14 | 15 | -------------------------------------------------------------------------------- /tests/Testcases/device_size_negative/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2_gemini 3 | # Device target 4 | target_device GEMINI_COMPACT_10x8 5 | set_device_size 42x43 6 | add_design_file -V_2001 ./rtl/and2.v 7 | set_top_module and2 8 | add_constraint_file constraints.sdc 9 | # Compilation 10 | synthesize delay 11 | packing 12 | place 13 | route 14 | sta 15 | bitstream 16 | -------------------------------------------------------------------------------- /tests/Testcases/device_size_negative/rtl/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | a, 9 | b, 10 | c); 11 | 12 | input wire a; 13 | input wire b; 14 | output wire c; 15 | 16 | assign c = a & b; 17 | 18 | endmodule -------------------------------------------------------------------------------- /tests/Testcases/double_check/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 0.1 clock0 3 | set_input_delay 0.1 -clock clock0 [get_ports rst_counter] 4 | set_output_delay 0.1 -clock clock0 [get_ports q_counter[0]] 5 | -------------------------------------------------------------------------------- /tests/Testcases/double_check/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design param_up_counter 3 | add_include_path ./rtl 4 | add_library_path ./rtl 5 | add_design_file -SV_2009 ./rtl/param_up_counter.v 6 | set_top_module param_up_counter 7 | add_constraint_file constraints.sdc 8 | 9 | # Device target 10 | target_device GEMINI_COMPACT_10x8 11 | 12 | # Synthesis 13 | synthesize delay 14 | synthesize delay 15 | 16 | # Pack/Place/Route 17 | packing 18 | packing 19 | place 20 | place 21 | route 22 | route 23 | 24 | # Static Timing Analysis 25 | sta opensta 26 | sta opensta 27 | 28 | # Bitstream Generation 29 | bitstream 30 | bitstream 31 | -------------------------------------------------------------------------------- /tests/Testcases/double_check/rtl/param_up_counter.v: -------------------------------------------------------------------------------- 1 | `define size 5 2 | 3 | module param_up_counter (input logic clock0, input logic rst_counter, output logic [`size-1:0] q_counter); 4 | 5 | always @ (posedge clock0) 6 | begin 7 | if(!rst_counter) 8 | q_counter <= 'b00000000; 9 | else 10 | q_counter <= q_counter + 1; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests/Testcases/double_check/sim_main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "Vparam_up_counter.h" 4 | #include "verilated.h" 5 | 6 | #if VM_TRACE_VCD == 1 7 | #include "verilated_vcd_c.h" 8 | #else 9 | #include "verilated_fst_c.h" 10 | #endif 11 | 12 | double sc_time_stamp() { 13 | return 0; 14 | } 15 | 16 | int main(int argc, char** argv, char** env) { 17 | Verilated::commandArgs(argc, argv); 18 | Vparam_up_counter* top = new Vparam_up_counter; 19 | // init trace dump 20 | std::string waveformFile; 21 | if (argc > 1) { 22 | waveformFile = argv[1]; 23 | std::cout << "Waveform file: " << waveformFile << std::endl; 24 | } else { 25 | waveformFile = "syn_tb.fst"; 26 | } 27 | Verilated::traceEverOn(true); 28 | Verilated::assertOn(true); 29 | 30 | #if VM_TRACE_FST == 1 31 | VerilatedFstC* tfp = new VerilatedFstC; 32 | # else 33 | VerilatedVcdC* tfp = new VerilatedVcdC; 34 | #endif 35 | 36 | top->trace(tfp, 99); 37 | tfp->open(waveformFile.c_str()); 38 | top->rst_counter = 0; 39 | top->clock0 = 0; 40 | 41 | for(int i = 0; i < 50; i++) { 42 | top->rst_counter = (i >= 2); 43 | for(int clk = 0; clk < 2; ++clk) { 44 | top->eval(); 45 | tfp->dump((2 * i) + clk); 46 | top->clock0 = !top->clock0; 47 | } 48 | } 49 | tfp->close(); 50 | delete top; 51 | exit(0); 52 | } 53 | -------------------------------------------------------------------------------- /tests/Testcases/gen_clk/constraints.sdc: -------------------------------------------------------------------------------- 1 | # External PLL Ref Clock 2 | create_clock -period 10 clk 3 | 4 | # PLL Clock output 5 | create_generated_clock -source [get_clocks clk] -divide_by 4 [get_nets clk_design] 6 | 7 | # Design clock divider 8 | create_generated_clock -source [get_clocks clk_design] -divide_by 2 [get_nets half_clk] 9 | -------------------------------------------------------------------------------- /tests/Testcases/gen_clk/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # gen_clk - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name gen_clk 10 | 11 | message "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file -V_2001 dut.v 14 | set_top_module dut 15 | add_constraint_file constraints.sdc 16 | #add_constraint_file pin_constraints.pin 17 | 18 | target_device GEMINI_COMPACT_22x4 19 | 20 | message "Compiling $project_name..." 21 | 22 | analyze 23 | synthesize delay 24 | 25 | setup_lec_sim 10 26 | 27 | # Simulate RTL vs gate 28 | simulate gate icarus 29 | 30 | packing 31 | place 32 | route 33 | 34 | # Simulate RTL vs post-pnr 35 | #simulate timed_pnr icarus 36 | simulate pnr icarus 37 | 38 | sta 39 | power 40 | bitstream 41 | 42 | message "Completed $project_name...\n" 43 | -------------------------------------------------------------------------------- /tests/Testcases/incr_comp/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | a, 9 | b, 10 | c); 11 | 12 | input wire a; 13 | input wire b; 14 | output wire c; 15 | 16 | assign c = a & b; 17 | 18 | endmodule -------------------------------------------------------------------------------- /tests/Testcases/incr_comp/and2_modified.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | one, 9 | sec, 10 | s); 11 | 12 | input wire one; 13 | input wire sec; 14 | output wire s; 15 | 16 | assign s = one & sec; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /tests/Testcases/incr_comp/copy.tcl: -------------------------------------------------------------------------------- 1 | # copy content for fileSource into fileDest. Files must exist 2 | proc copyContent {fileSource fileDest} { 3 | set fp [open $fileSource r] 4 | set file_data [read $fp] 5 | close $fp 6 | set fo [open $fileDest w] 7 | puts $fo $file_data 8 | close $fo 9 | } 10 | -------------------------------------------------------------------------------- /tests/Testcases/incr_comp/raptor.tcl: -------------------------------------------------------------------------------- 1 | set script_path [ file dirname [ file normalize [ info script ] ] ] 2 | source $script_path/copy.tcl 3 | 4 | set projName incr_comp 5 | set tempFile $projName/tmp.v 6 | 7 | create_design $projName 8 | target_device GEMINI_COMPACT_10x8 9 | 10 | file copy -force $script_path/and2.v $tempFile 11 | 12 | add_design_file $tempFile 13 | set_top_module and2 14 | # cleanup before test 15 | synthesize clean 16 | synthesize 17 | 18 | set blifPath $projName/run_1/synth_1_1/synthesis 19 | file copy -force $blifPath/incr_comp_post_synth.eblif $blifPath/incr_comp_post_synth.eblif1 20 | # wait 1 sec since mtime will be the same for $tempFile and *.blif 21 | after 1000 22 | copyContent $script_path/and2_modified.v $tempFile 23 | synthesize 24 | file copy -force $blifPath/incr_comp_post_synth.eblif $blifPath/incr_comp_post_synth.eblif2 25 | set diffresult [catch {exec sh -c "diff $blifPath/incr_comp_post_synth.eblif1 $blifPath/incr_comp_post_synth.eblif2"} diffresult] 26 | if {$diffresult == 0} { 27 | error "Synthesis didn't resynthesized" 28 | } 29 | -------------------------------------------------------------------------------- /tests/Testcases/ip_gen_axis_conv/raptor.tcl: -------------------------------------------------------------------------------- 1 | create_design ip_test 2 | target_device 1VG28 3 | configure_ip axis_width_converter_v1_0 -mod_name conv32_16 -version 1.0 -Pcore_in_width=32 -Pcore_out_width=16 -Pcore_reverse=0 -out_file rs_ips/conv32_16.v 4 | ipgenerate 5 | set_top_module use_ip 6 | add_design_file rs_ips/conv32_16.v use_ip.v 7 | synth delay 8 | packing 9 | place 10 | route 11 | sta 12 | 13 | -------------------------------------------------------------------------------- /tests/Testcases/ip_gen_axis_conv/use_ip.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ps/ 1 ps 2 | 3 | module use_ip( 4 | input wire axis_clk, 5 | input wire axis_rst, 6 | input wire axis_in_tvalid, 7 | input wire axis_in_tlast, 8 | output wire axis_in_tready, 9 | input wire [31:0] axis_in_tdata, 10 | output wire axis_out_tvalid, 11 | output wire axis_out_tlast, 12 | input wire axis_out_tready, 13 | output wire [15:0] axis_out_tdata 14 | ); 15 | 16 | conv32_16 U1 ( 17 | axis_clk, 18 | axis_rst, 19 | axis_in_tvalid, 20 | axis_in_tlast, 21 | axis_in_tready, 22 | axis_in_tdata, 23 | axis_out_tvalid, 24 | axis_out_tlast, 25 | axis_out_tready, 26 | axis_out_tdata); 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /tests/Testcases/keep_test/constraints.sdc: -------------------------------------------------------------------------------- 1 | 2 | keep internal 3 | 4 | set_property mode Mode_BP_SDR_A_RX HP_1_CC_28_14P 5 | set_pin_loc a HP_1_CC_28_14P 6 | 7 | set_property mode Mode_BP_SDR_A_RX HP_1_26_13P 8 | set_pin_loc b HP_1_26_13P 9 | 10 | set_property mode Mode_BP_SDR_A_TX HP_1_24_12P 11 | set_pin_loc c HP_1_24_12P 12 | 13 | -------------------------------------------------------------------------------- /tests/Testcases/keep_test/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design keep_test 3 | add_design_file -V_2001 ./rtl/top.v 4 | set_top_module top 5 | add_constraint_file constraints.sdc 6 | 7 | # Device target 8 | target_device GEMINI_COMPACT_10x8 9 | 10 | # Compilation 11 | synthesize 12 | packing 13 | -------------------------------------------------------------------------------- /tests/Testcases/keep_test/rtl/and2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////// 2 | // Functionality: 2-input AND 3 | // Author: Xifan Tang 4 | //////////////////////////////////////// 5 | // `timescale 1ns / 1ps 6 | 7 | module and2( 8 | a, 9 | b, 10 | c); 11 | 12 | input wire a; 13 | input wire b; 14 | output wire c; 15 | 16 | assign c = a & b; 17 | 18 | endmodule -------------------------------------------------------------------------------- /tests/Testcases/keep_test/rtl/top.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | a, 3 | b, 4 | c, 5 | o); 6 | 7 | input wire a; 8 | input wire b; 9 | input wire c; 10 | output wire o; 11 | 12 | wire internal; 13 | 14 | assign o = (c) ? internal : a; 15 | assign internal = (c) ? b : a; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /tests/Testcases/lfsr/constraints.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 1e-10 clk 2 | 3 | #create_clock -period 100e-9 clk 4 | -------------------------------------------------------------------------------- /tests/Testcases/lfsr/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design lfsr 3 | add_design_file top.sv 4 | set_top_module lfsr 5 | add_constraint_file constraints.sdc 6 | 7 | # Device target 8 | target_device GEMINI_COMPACT_10x8 9 | # Compilation 10 | analyze 11 | synthesize delay 12 | packing 13 | place 14 | route 15 | sta 16 | bitstream 17 | -------------------------------------------------------------------------------- /tests/Testcases/lfsr/top.sv: -------------------------------------------------------------------------------- 1 | module lfsr (out, clk, rst); 2 | 3 | output reg [3:0] out ; 4 | 5 | input clk, rst; 6 | 7 | wire feedback; 8 | 9 | assign feedback = ~(out[3] ^ out[2]); 10 | 11 | always @(posedge clk, posedge rst) 12 | begin 13 | if (rst) 14 | out = 4'b0; 15 | else 16 | out = {out[2:0],feedback}; 17 | end 18 | endmodule // lsfr 19 | 20 | -------------------------------------------------------------------------------- /tests/Testcases/mult_gemini/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 2.5 clk 3 | set_input_delay 1 -clock clk [get_ports {A[0]}] 4 | set_input_delay 1 -clock clk [get_ports {A[1]}] 5 | set_input_delay 1 -clock clk [get_ports {B[0]}] 6 | set_input_delay 1 -clock clk [get_ports {B[1]}] 7 | set_output_delay 0.5 -clock clk [get_ports {P[0]}] 8 | set_output_delay 0.5 -clock clk [get_ports {P[1]}] 9 | set_output_delay 0.5 -clock clk [get_ports {P[2]}] 10 | set_output_delay 0.5 -clock clk [get_ports {P[3]}] 11 | -------------------------------------------------------------------------------- /tests/Testcases/mult_gemini/mult.v: -------------------------------------------------------------------------------- 1 | module dsp_mult #(parameter A_WIDTH = 2, B_WIDTH = 2) (clk, reset, A, B, P); 2 | input clk, reset; 3 | input [A_WIDTH-1:0] A; 4 | input [B_WIDTH-1:0] B; 5 | output reg [A_WIDTH + B_WIDTH-1:0] P; 6 | reg signed [A_WIDTH-1:0] i1; 7 | reg signed [B_WIDTH-1:0] i2; 8 | reg [A_WIDTH + B_WIDTH-1:0] mul; 9 | always @(posedge clk) begin 10 | i1 <= A; 11 | i2 <= B; 12 | end 13 | 14 | always @(posedge clk) begin 15 | P <= mul; 16 | end 17 | 18 | always @ (*) begin 19 | mul = i1 * i2; 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /tests/Testcases/mult_gemini/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design and2_gemini_latest 3 | add_design_file -V_2001 mult.v 4 | set_top_module dsp_mult 5 | add_constraint_file constraints.sdc 6 | 7 | # Device target 8 | target_device GEMINI_COMPACT_10x8 9 | 10 | # Compilation 11 | analyze 12 | synthesize delay 13 | packing 14 | place 15 | route 16 | sta opensta 17 | bitstream 18 | -------------------------------------------------------------------------------- /tests/Testcases/oneff/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 2.5 clock0 3 | set_input_delay 1 -clock clock0 [get_ports {d}] 4 | set_input_delay 1 -clock clock0 [get_ports {rstn}] 5 | set_output_delay 1 -clock clock0 [get_ports {q}] 6 | -------------------------------------------------------------------------------- /tests/Testcases/oneff/dut.v: -------------------------------------------------------------------------------- 1 | 2 | module dut (input d, 3 | input rstn, 4 | input clock0, 5 | output reg q); 6 | 7 | always @ (posedge clock0 or negedge rstn) 8 | begin 9 | if (!rstn) 10 | q <= 0; 11 | else 12 | q <= d; 13 | end 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /tests/Testcases/oneff/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_pin_loc d HP_1_0_0P 2 | set_pin_loc rstn HP_1_1_0N 3 | set_pin_loc q HP_1_2_1P 4 | set_pin_loc clock0 HP_1_CC_18_9P 5 | -------------------------------------------------------------------------------- /tests/Testcases/oneff/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design oneff_gemini 3 | add_design_file -SV_2009 dut.v 4 | set_top_module dut 5 | add_constraint_file pin_mapping.pin 6 | add_constraint_file constraints.sdc 7 | 8 | # Testbench 9 | add_simulation_file -SV_2009 syn_tb.v 10 | add_simulation_file sim_main.cpp 11 | set_top_testbench syn_tb 12 | 13 | # Device target 14 | target_device GEMINI_COMPACT_22x4 15 | 16 | # Compilation/Simulation 17 | analyze 18 | 19 | # clean default flags for wrapper 20 | simulation_options verilator compilation rtl "" 21 | # RTL Simulation 22 | simulate rtl verilator syn_tb_rtl.fst 23 | 24 | # Synthesis 25 | synthesize delay 26 | 27 | # clean default flags for wrapper 28 | simulation_options verilator compilation gate "" 29 | # Post-Synthesis gate-level Simulation 30 | simulate gate verilator syn_tb_gate.fst 31 | 32 | # Pack/Place/Route 33 | packing 34 | place 35 | route 36 | 37 | # clean default flags for wrapper 38 | simulation_options verilator compilation pnr "" 39 | # Post-Route Simulation 40 | simulate pnr verilator syn_tb_pnr.fst 41 | 42 | # Static Timing Analysis 43 | sta 44 | 45 | # Bitstream Generation 46 | bitstream 47 | -------------------------------------------------------------------------------- /tests/Testcases/oneff/sim_main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "Vsyn_tb.h" 4 | #include "verilated.h" 5 | 6 | #if VM_TRACE_VCD == 1 7 | #include "verilated_vcd_c.h" 8 | #else 9 | #include "verilated_fst_c.h" 10 | #endif 11 | 12 | double sc_time_stamp() { 13 | return 0; 14 | } 15 | 16 | int main(int argc, char** argv, char** env) { 17 | Verilated::commandArgs(argc, argv); 18 | Vsyn_tb* top = new Vsyn_tb; 19 | // init trace dump 20 | std::string waveformFile; 21 | if (argc > 1) { 22 | waveformFile = argv[1]; 23 | std::cout << "Waveform file: " << waveformFile << std::endl; 24 | } else { 25 | waveformFile = "syn_tb.fst"; 26 | } 27 | Verilated::traceEverOn(true); 28 | Verilated::assertOn(true); 29 | 30 | #if VM_TRACE_FST == 1 31 | VerilatedFstC* tfp = new VerilatedFstC; 32 | # else 33 | VerilatedVcdC* tfp = new VerilatedVcdC; 34 | #endif 35 | 36 | top->trace(tfp, 99); 37 | tfp->open(waveformFile.c_str()); 38 | top->rstn = 0; 39 | top->clk = 0; 40 | 41 | // run simulation for 20 clock periods 42 | // Only generate the clock in C, 43 | // the testbench is in Verilog 44 | for(int i = 0; i < 20; i++) { 45 | top->rstn = (i >= 2); 46 | for(int clk = 0; clk < 2; ++clk) { 47 | top->eval(); 48 | tfp->dump((2 * i) + clk); 49 | top->clk = !top->clk; 50 | } 51 | } 52 | tfp->close(); 53 | delete top; 54 | exit(0); 55 | } 56 | -------------------------------------------------------------------------------- /tests/Testcases/oneff/syn_tb.v: -------------------------------------------------------------------------------- 1 | module syn_tb(input logic rstn, 2 | input logic clk, 3 | output logic rtl_q); 4 | 5 | logic d; 6 | integer state = 0; 7 | 8 | // Stimulus + Model Checking 9 | always @ (posedge clk) begin 10 | if (state==0) begin 11 | d <= 0; 12 | state <= state+1; 13 | end 14 | else if (state==1) begin 15 | d <= 1; 16 | state <= state+1; 17 | end 18 | else if (state==2) begin 19 | d <= 1; 20 | state <= state+1; 21 | end 22 | else if (state==3) begin 23 | d <= 0; 24 | state <= state+1; 25 | end 26 | else if (state==4) begin 27 | d <= 0; 28 | state <= state+1; 29 | end 30 | else if (state==5) begin 31 | d <= 1; 32 | state <= state+1; 33 | end 34 | else if (state==6) begin 35 | d <= 0; 36 | state <= state+1; 37 | end 38 | else if (state==7) begin 39 | d <= 0; 40 | state <= state+1; 41 | end 42 | else if (state==8) begin 43 | d <= 0; 44 | state <= state+1; 45 | end 46 | $display("d = %0d, q = %0d", d, rtl_q); 47 | 48 | end 49 | 50 | dut rtl_model(d, rstn, clk, rtl_q); 51 | 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /tests/Testcases/oneff_wio/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 2.5 clock0 3 | set_input_delay 1 -clock clock0 [get_ports {d}] 4 | set_input_delay 1 -clock clock0 [get_ports {rstn}] 5 | set_output_delay 1 -clock clock0 [get_ports {q}] 6 | -------------------------------------------------------------------------------- /tests/Testcases/oneff_wio/dut.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ///////////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // One flipflop example, with Verilator testbench // 5 | ///////////////////////////////////////////////////////////////// 6 | 7 | module dut (input d, 8 | input rstn, 9 | input clock0, 10 | output reg q); 11 | 12 | always @ (posedge clock0 or negedge rstn) 13 | begin 14 | if (!rstn) 15 | q <= 0; 16 | else 17 | q <= d; 18 | end 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /tests/Testcases/oneff_wio/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_pin_loc d HP_1_0_0P 2 | set_pin_loc rstn HP_1_1_0N 3 | set_pin_loc q HP_1_2_1P 4 | set_pin_loc clock0 HP_1_CC_18_9P 5 | -------------------------------------------------------------------------------- /tests/Testcases/oneff_wio/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design oneff_wio 3 | add_design_file -SV_2009 dut.v 4 | set_top_module dut 5 | add_constraint_file pin_mapping.pin 6 | add_constraint_file constraints.sdc 7 | 8 | # Testbench 9 | add_simulation_file -SV_2009 syn_tb.v 10 | add_simulation_file sim_main.cpp 11 | set_top_testbench syn_tb 12 | 13 | # Device target 14 | target_device GEMINI_COMPACT_22x4 15 | 16 | # Compilation/Simulation 17 | analyze 18 | 19 | # clean default flags for wrapper 20 | simulation_options verilator compilation rtl "" 21 | # RTL Simulation 22 | simulate rtl verilator syn_tb_rtl.fst 23 | 24 | # Synthesis 25 | synth_options -inferred_io 26 | synthesize delay 27 | 28 | # clean default flags for wrapper 29 | simulation_options verilator compilation gate "" 30 | # Post-Synthesis gate-level Simulation 31 | simulate gate verilator syn_tb_gate.fst 32 | 33 | # Pack/Place/Route 34 | packing 35 | place 36 | route 37 | 38 | # clean default flags for wrapper 39 | simulation_options verilator compilation pnr "" 40 | # Post-Route Simulation 41 | simulate pnr verilator syn_tb_pnr.fst 42 | 43 | # Static Timing Analysis 44 | sta 45 | # Power analysis 46 | power 47 | # Bitstream Generation 48 | bitstream 49 | -------------------------------------------------------------------------------- /tests/Testcases/oneff_wio/sim_main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "Vsyn_tb.h" 4 | #include "verilated.h" 5 | 6 | #if VM_TRACE_VCD == 1 7 | #include "verilated_vcd_c.h" 8 | #else 9 | #include "verilated_fst_c.h" 10 | #endif 11 | 12 | double sc_time_stamp() { 13 | return 0; 14 | } 15 | 16 | int main(int argc, char** argv, char** env) { 17 | Verilated::commandArgs(argc, argv); 18 | Vsyn_tb* top = new Vsyn_tb; 19 | // init trace dump 20 | std::string waveformFile; 21 | if (argc > 1) { 22 | waveformFile = argv[1]; 23 | std::cout << "Waveform file: " << waveformFile << std::endl; 24 | } else { 25 | waveformFile = "syn_tb.fst"; 26 | } 27 | Verilated::traceEverOn(true); 28 | Verilated::assertOn(true); 29 | 30 | #if VM_TRACE_FST == 1 31 | VerilatedFstC* tfp = new VerilatedFstC; 32 | # else 33 | VerilatedVcdC* tfp = new VerilatedVcdC; 34 | #endif 35 | 36 | top->trace(tfp, 99); 37 | tfp->open(waveformFile.c_str()); 38 | top->rstn = 0; 39 | top->clk = 0; 40 | 41 | // run simulation for 20 clock periods 42 | // Only generate the clock in C, 43 | // the testbench is in Verilog 44 | for(int i = 0; i < 20; i++) { 45 | top->rstn = (i >= 2); 46 | for(int clk = 0; clk < 2; ++clk) { 47 | top->eval(); 48 | tfp->dump((2 * i) + clk); 49 | top->clk = !top->clk; 50 | } 51 | } 52 | tfp->close(); 53 | delete top; 54 | exit(0); 55 | } 56 | -------------------------------------------------------------------------------- /tests/Testcases/oneff_wio/syn_tb.v: -------------------------------------------------------------------------------- 1 | module syn_tb(input logic rstn, 2 | input logic clk, 3 | output logic rtl_q); 4 | 5 | logic d; 6 | integer state = 0; 7 | 8 | // Stimulus + Model Checking 9 | always @ (posedge clk) begin 10 | if (state==0) begin 11 | d <= 0; 12 | state <= state+1; 13 | end 14 | else if (state==1) begin 15 | d <= 1; 16 | state <= state+1; 17 | end 18 | else if (state==2) begin 19 | d <= 1; 20 | state <= state+1; 21 | end 22 | else if (state==3) begin 23 | d <= 0; 24 | state <= state+1; 25 | end 26 | else if (state==4) begin 27 | d <= 0; 28 | state <= state+1; 29 | end 30 | else if (state==5) begin 31 | d <= 1; 32 | state <= state+1; 33 | end 34 | else if (state==6) begin 35 | d <= 0; 36 | state <= state+1; 37 | end 38 | else if (state==7) begin 39 | d <= 0; 40 | state <= state+1; 41 | end 42 | else if (state==8) begin 43 | d <= 0; 44 | state <= state+1; 45 | end 46 | $display("d = %0d, q = %0d", d, rtl_q); 47 | 48 | end 49 | 50 | dut rtl_model(d, rstn, clk, rtl_q); 51 | 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /tests/Testcases/param_counter/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 0.1 clock0 3 | set_input_delay 0.1 -clock clock0 [get_ports rst_counter] 4 | set_output_delay 0.1 -clock clock0 [get_ports q_counter[0]] 5 | -------------------------------------------------------------------------------- /tests/Testcases/param_counter/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design param_up_counter 3 | add_include_path ./rtl 4 | add_library_path ./rtl 5 | add_design_file -SV_2009 ./rtl/param_up_counter.v 6 | set_top_module param_up_counter 7 | add_constraint_file constraints.sdc 8 | 9 | # Testbench 10 | add_simulation_file sim_main.cpp 11 | set_top_testbench param_up_counter 12 | 13 | # Device target 14 | target_device GEMINI_COMPACT_10x8 15 | 16 | # clean default flags for wrapper 17 | simulation_options verilator compilation rtl "" 18 | # RTL Simulation 19 | simulate rtl verilator counter_rtl.fst 20 | 21 | # Synthesis 22 | synthesize delay 23 | 24 | # clean default flags for wrapper 25 | simulation_options verilator compilation gate "" 26 | # Post-Synthesis gate-level Simulation 27 | simulate gate verilator counter_gate.fst 28 | 29 | # Pack/Place/Route 30 | packing 31 | place 32 | route 33 | 34 | # clean default flags for wrapper 35 | simulation_options verilator compilation pnr "" 36 | # Post-Route Simulation 37 | simulate pnr verilator counter_pnr.fst 38 | 39 | # Static Timing Analysis 40 | sta opensta 41 | 42 | # Bitstream Generation 43 | bitstream 44 | -------------------------------------------------------------------------------- /tests/Testcases/param_counter/rtl/param_up_counter.v: -------------------------------------------------------------------------------- 1 | `define size 5 2 | 3 | module param_up_counter (input logic clock0, input logic rst_counter, output logic [`size-1:0] q_counter); 4 | 5 | always @ (posedge clock0) 6 | begin 7 | if(!rst_counter) 8 | q_counter <= 'b00000000; 9 | else 10 | q_counter <= q_counter + 1; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /tests/Testcases/param_counter/sim_main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "Vparam_up_counter.h" 4 | #include "verilated.h" 5 | 6 | #if VM_TRACE_VCD == 1 7 | #include "verilated_vcd_c.h" 8 | #else 9 | #include "verilated_fst_c.h" 10 | #endif 11 | 12 | double sc_time_stamp() { 13 | return 0; 14 | } 15 | 16 | int main(int argc, char** argv, char** env) { 17 | Verilated::commandArgs(argc, argv); 18 | Vparam_up_counter* top = new Vparam_up_counter; 19 | // init trace dump 20 | std::string waveformFile; 21 | if (argc > 1) { 22 | waveformFile = argv[1]; 23 | std::cout << "Waveform file: " << waveformFile << std::endl; 24 | } else { 25 | waveformFile = "syn_tb.fst"; 26 | } 27 | Verilated::traceEverOn(true); 28 | Verilated::assertOn(true); 29 | 30 | #if VM_TRACE_FST == 1 31 | VerilatedFstC* tfp = new VerilatedFstC; 32 | # else 33 | VerilatedVcdC* tfp = new VerilatedVcdC; 34 | #endif 35 | 36 | top->trace(tfp, 99); 37 | tfp->open(waveformFile.c_str()); 38 | top->rst_counter = 0; 39 | top->clock0 = 0; 40 | 41 | for(int i = 0; i < 50; i++) { 42 | top->rst_counter = (i >= 2); 43 | for(int clk = 0; clk < 2; ++clk) { 44 | top->eval(); 45 | tfp->dump((2 * i) + clk); 46 | top->clock0 = !top->clock0; 47 | } 48 | } 49 | tfp->close(); 50 | delete top; 51 | exit(0); 52 | } 53 | -------------------------------------------------------------------------------- /tests/Testcases/partitioner_aes_verilog/Src/InvAddRoundKey.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module InvAddRoundKey( 4 | input [0:127] din0, 5 | input [0:127] din1, 6 | input [0:127] rkey, 7 | input S, 8 | output [0:127] dout); 9 | 10 | logic [0:127] tmp; 11 | 12 | always_comb 13 | tmp <= S? din1 : din0; 14 | 15 | assign dout = tmp ^ rkey; 16 | endmodule -------------------------------------------------------------------------------- /tests/Testcases/partitioner_aes_verilog/Src/MUXF7.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module MUXF7 (output O, input I0, input I1, input S); 4 | assign O = (S)? I1 : I0; 5 | endmodule 6 | -------------------------------------------------------------------------------- /tests/Testcases/partitioner_aes_verilog/Src/MUXF8.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module MUXF8 (output O, input I0, input I1, input S); 4 | assign O = (S)? I1 : I0; 5 | endmodule 6 | -------------------------------------------------------------------------------- /tests/Testcases/partitioner_aes_verilog/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 100 MHz (10nS period) 4 | create_clock -period 10 clk 5 | -------------------------------------------------------------------------------- /tests/Testcases/partitioner_and2_verilog/Src/and2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // and2_verilog // 5 | // and2.v - Top-level file of simple 2-input AND gate // 6 | //////////////////////////////////////////////////////// 7 | 8 | module Llatch( input D, input G, output reg Q); 9 | 10 | always @* 11 | if (G == 1'b1) 12 | Q <= D; 13 | else 14 | Q<=Q; 15 | 16 | endmodule 17 | 18 | module and2 ( 19 | input a, 20 | input b, 21 | input clk, 22 | input reset, 23 | output reg c = 1'b0, 24 | output wire Q 25 | ); 26 | 27 | reg a_reg, b_reg = 1'b0; 28 | 29 | Llatch my (a,b, Q); 30 | 31 | 32 | 33 | always@(posedge clk) 34 | if (reset) begin 35 | a_reg <= 1'b0; 36 | b_reg <= 1'b0; 37 | c <= 1'b0; 38 | end else begin 39 | a_reg <= a; 40 | b_reg <= b; 41 | c <= a_reg & b_reg; 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /tests/Testcases/partitioner_and2_verilog/and2_part.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /tests/Testcases/partitioner_and2_verilog/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 200 MHz (5nS period) 4 | create_clock -period 5 clk 5 | set_input_delay 0.8 -clock clk [get_ports {a}] 6 | set_input_delay 0.8 -clock clk [get_ports {b}] 7 | 8 | -------------------------------------------------------------------------------- /tests/Testcases/partitioner_and2_verilog/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | 2 | set_property mode Mode_BP_SDR_A_RX HR_3_0_0P 3 | set_pin_loc a HR_3_0_0P 4 | 5 | set_property mode Mode_BP_SDR_A_RX HR_2_0_0P 6 | set_pin_loc b HR_2_0_0P 7 | 8 | set_property mode Mode_BP_SDR_A_TX HR_5_0_0P 9 | set_pin_loc c HR_5_0_0P 10 | 11 | -------------------------------------------------------------------------------- /tests/Testcases/partitioner_and2_verilog/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # and2_verilog - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name and2 10 | 11 | puts "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file -V_2001 ./Src/and2.v 14 | # Top-module can automatically be indentified or implicitly specified here 15 | set_top_module and2 16 | add_constraint_file pin_mapping.pin 17 | add_constraint_file constraints.sdc 18 | # Simulation 19 | add_simulation_file -SV_2012 ./Src/testbench_and2.v 20 | set_top_testbench testbench_and2 21 | # Device target 22 | target_device GEMINI_COMPACT_10x8 23 | 24 | # RTL Simulation 25 | simulate rtl icarus 26 | 27 | #wave_open and2/and2.vcd 28 | #wave_show reset 29 | #wave_show clk 30 | #wave_show a 31 | #wave_show b 32 | #wave_show a_delay_by_2 33 | #wave_show b_delay_by_2 34 | #wave_show c 35 | #wave_cmd gtkwave::/Time/Zoom/Zoom_Full 36 | 37 | # Compilation 38 | puts "Compiling $project_name..." 39 | analyze 40 | #synth_options -inferred_io 41 | #parser_type surelog 42 | synthesize delay 43 | simulate gate icarus 44 | pnr_options --target_ext_pin_util 0.2 --use_partitioning_in_pack on --number_of_molecules_in_partition 250 --alpha_clustering 0.1 45 | packing 46 | place 47 | route 48 | sta 49 | power 50 | bitstream 51 | #simulate pnr icarus 52 | 53 | puts "Completed $project_name...\n" 54 | -------------------------------------------------------------------------------- /tests/Testcases/rom/raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design rom 3 | add_design_file top.v 4 | set_top_module SBox 5 | 6 | # Device target 7 | target_device 1VG28 8 | # Compilation 9 | analyze 10 | synthesize delay 11 | 12 | setup_lec_sim 13 | simulate icarus gate 14 | 15 | packing 16 | place 17 | route 18 | 19 | simulate icarus timed_pnr 20 | 21 | sta 22 | power 23 | bitstream 24 | -------------------------------------------------------------------------------- /tests/Testcases/sasc_testcase/bitstream_annotation.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /tests/Testcases/sasc_testcase/constraints.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 7.935999999999999 clk 2 | set_input_delay 1 -clock clk [get_ports {*}] 3 | set_output_delay 1 -clock clk [get_ports {*}] 4 | 5 | -------------------------------------------------------------------------------- /tests/Testcases/sasc_testcase/design_variables.yml: -------------------------------------------------------------------------------- 1 | CCFF_BANKS: 1 2 | -------------------------------------------------------------------------------- /tests/Testcases/sasc_testcase/fixed_sim_openfpga.xml: -------------------------------------------------------------------------------- 1 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | -------------------------------------------------------------------------------- /tests/Testcases/sasc_testcase/raptor.tcl: -------------------------------------------------------------------------------- 1 | create_design sasc 2 | # Device setup 3 | target_device 1VG28 4 | # Design setup 5 | add_design_file -V_2001 ./rtl/timescale.v ./rtl/sasc_brg.v ./rtl/sasc_fifo4.v ./rtl/sasc.v 6 | set_top_module sasc 7 | add_constraint_file constraints.sdc 8 | # Compilation 9 | synthesize 10 | packing 11 | place 12 | route 13 | sta 14 | bitstream 15 | -------------------------------------------------------------------------------- /tests/Testcases/sasc_testcase/repack_design_constraint.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /tests/Testcases/sasc_testcase/rtl/config.tcl: -------------------------------------------------------------------------------- 1 | set ::env(PROJECT_NAME) sasc 2 | set ::env(DESIGN_TOP) sasc 3 | set ::env(DESIGN_DIR) RTL_Benchmark/Verilog/iwls2005_designs/sasc/rtl 4 | set ::env(TOP_VERILOG) RTL_Benchmark/Verilog/iwls2005_designs/sasc/rtl/sasc.v 5 | set ::env(CLOCK_COUNT) 1 6 | set ::env(DOMAIN) controller 7 | -------------------------------------------------------------------------------- /tests/Testcases/sasc_testcase/rtl/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | -------------------------------------------------------------------------------- /tests/Testcases/trivial/bottom.v: -------------------------------------------------------------------------------- 1 | module bottom (input logic [`P1:0] a, output logic [`P1:0] b); 2 | assign b = a; 3 | endmodule 4 | -------------------------------------------------------------------------------- /tests/Testcases/trivial/inc/def.vh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/os-fpga/Raptor/a783c38932019ce35721f5bac13eaf98980631fe/tests/Testcases/trivial/inc/def.vh -------------------------------------------------------------------------------- /tests/Testcases/trivial/test.tcl: -------------------------------------------------------------------------------- 1 | create_design test 2 | architecture ../../Arch/k6_frac_N10_tileable_40nm.xml ../../Arch/k6_N10_40nm_openfpga.xml 3 | set_macro P1=10 P2=20 4 | add_include_path inc/ 5 | add_design_file test.v bottom.v -SV_2012 6 | set_top_module top 7 | synth 8 | packing 9 | place 10 | route 11 | sta 12 | power 13 | #bitstream 14 | message "done!" 15 | 16 | 17 | -------------------------------------------------------------------------------- /tests/Testcases/trivial/test.v: -------------------------------------------------------------------------------- 1 | `include "def.vh" 2 | module top(input logic [`P2:0] a, output logic [`P2:0] b); 3 | bottom bot (a, b); 4 | 5 | 6 | endmodule // top 7 | 8 | -------------------------------------------------------------------------------- /tests/Testcases/vex_soc/bare_metal_stimulus/build/src/crt.d: -------------------------------------------------------------------------------- 1 | build/src/crt.o: src/crt.S 2 | -------------------------------------------------------------------------------- /tests/Testcases/vex_soc/bare_metal_stimulus/build/src/main.d: -------------------------------------------------------------------------------- 1 | build/src/main.o: src/main.c 2 | -------------------------------------------------------------------------------- /tests/Testcases/vex_soc/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clock and for actual clock -name option will not be used 2 | create_clock -period 1.5 clk 3 | set_input_delay 1 -clock clk [get_ports {reset}] -------------------------------------------------------------------------------- /tests/Testcases/vex_soc/pin_constraints.pin: -------------------------------------------------------------------------------- 1 | set_clock_pin -device_clock clk[0] -design_clock clk 2 | 3 | -------------------------------------------------------------------------------- /tests/Testcases/vex_soc/raptor_vex_100K.tcl: -------------------------------------------------------------------------------- 1 | create_design vex_100K 2 | target_device 1GE100-ES1 3 | add_include_path ./ 4 | add_library_path rtl/ 5 | add_library_ext .v .sv 6 | add_design_file rtl/vex_soc.v 7 | set_top_module vex_soc 8 | 9 | analyze 10 | synth_options -effort high -carry all 11 | synthesize delay 12 | packing 13 | global_placement 14 | place 15 | route 16 | sta 17 | #bitstream 18 | -------------------------------------------------------------------------------- /tests/Testcases/vex_soc/raptor_vex_compact.tcl: -------------------------------------------------------------------------------- 1 | create_design vex_soc 2 | target_device 1VG28 3 | add_include_path ./ 4 | add_library_path rtl/ 5 | add_library_ext .v .sv 6 | add_design_file rtl/vex_soc.v 7 | add_constraint_file pin_constraints.pin 8 | set_top_module vex_soc 9 | synth_options -effort high -carry all 10 | synthesize delay 11 | packing 12 | global_placement 13 | place 14 | route 15 | sta 16 | power 17 | bitstream 18 | -------------------------------------------------------------------------------- /tests/Testcases/vex_soc/raptor_vex_no_carry.tcl: -------------------------------------------------------------------------------- 1 | create_design vex_soc_no_carry 2 | target_device 1VG28 3 | add_library_path rtl/ 4 | add_library_ext .v .sv 5 | add_design_file rtl/vex_soc.v 6 | add_constraint_file constraints.sdc 7 | set_top_module vex_soc 8 | analyze 9 | synth_options -effort high -carry none 10 | synthesize delay 11 | packing 12 | place 13 | route 14 | sta opensta 15 | power 16 | bitstream 17 | -------------------------------------------------------------------------------- /tests/Testcases/vex_soc/raptor_vex_soc.tcl: -------------------------------------------------------------------------------- 1 | create_design vex_soc 2 | target_device 1GVTC 3 | add_include_path ./ 4 | add_library_path rtl/ 5 | add_library_ext .v .sv 6 | add_design_file rtl/vex_soc.v 7 | set_top_module vex_soc 8 | synth_options -effort high -carry all 9 | synthesize delay 10 | packing 11 | global_placement 12 | place 13 | route 14 | sta 15 | power 16 | bitstream 17 | -------------------------------------------------------------------------------- /tests/Testcases/vex_soc/sim/testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | 4 | module Tb; 5 | reg clock; 6 | reg reset; 7 | initial begin 8 | reset = 1'b1; 9 | clock = 1'b0; 10 | #5; 11 | reset = 1'b0; 12 | // #10; 13 | // reset =1'b1; 14 | // #10; 15 | // reset = 1'b0; 16 | end 17 | always #(2.5) clock = !clock; 18 | 19 | initial begin 20 | $dumpfile("tb.vcd"); 21 | $dumpvars; 22 | #7000 $finish; 23 | $display("FInish called from testbench"); 24 | end 25 | vex_soc soc(.clk(clock), 26 | .reset(reset)); 27 | endmodule 28 | -------------------------------------------------------------------------------- /tests/Testcases/vex_soc/sim/verilator_tb.cpp: -------------------------------------------------------------------------------- 1 | #include "../obj_dir/Vtestbench.h" 2 | int sc_main(int argc, char** argv){ 3 | Verilated::traceEverOn(true); 4 | new Vtestbench("top"); 5 | while (!Verilated::gotFinish()) { sc_start(1, SC_NS); } 6 | return 0; 7 | } 8 | -------------------------------------------------------------------------------- /tests/Testcases/xor5/raptor_tcl.tcl: -------------------------------------------------------------------------------- 1 | create_design xor5 2 | target_device GEMINI_COMPACT_10x8 3 | add_design_file rtl/xor5.v 4 | file copy -force rtl/private_key.pem xor5/private_key.pem 5 | set_top_module xor5 6 | #add_constraint_file : Sets SDC + location constraints 7 | #Constraints: set_pin_loc, set_region_loc, all SDC commands 8 | #batch { cmd1 ... cmdn } : Run compilation script using commands below 9 | #ipgenerate 10 | #ipgenerate 11 | pnr_netlist_lang verilog 12 | synthesize delay 13 | #pin_loc_assign_method free 14 | packing 15 | global_placement 16 | place 17 | route 18 | sta 19 | power 20 | bitstream force 21 | -------------------------------------------------------------------------------- /tests/Testcases/xor5/rtl/private_key.pem: -------------------------------------------------------------------------------- 1 | -----BEGIN RSA PRIVATE KEY----- 2 | MIICdwIBADANBgkqhkiG9w0BAQEFAASCAmEwggJdAgEAAoGBAORGrby5UnrjIZmo4mtY8ckBJ7nh 3 | 7fU/VQs0jDrBr0qI5yuu8f+tOrvBn3ErdjTHCZmM5+H+5/z36DAcFBYYwwyZmk+3oDeNHTygzRGY 4 | mnA4vh8CwUGRyAzsE4u3eCmlsdCtmvJHFdeTIUigFIkBhMa67il+Q7M0fs7TNQ3CF8zPAgMBAAEC 5 | gYBfj4LtjTsM/IY1WDCotYxKE/S4aO7/iqqkTTQi6K/j6Nm1PMBLww3iSZTggEw0ndnT8NuljNs6 6 | 1+DYOvjhoy4LDsDC9MvaB/V/FlowVyCWvuaHW7OWE9/ipG43+pt+C9FmPqdOjKgw6Kdh4io6vnFv 7 | SEZPFUN2NJH47Jnh/0JuEQJBAPpY95WvGFbSin+fxhVNOO7KlUGSVQuaye//IXdzm6PD/hH1Em2Z 8 | M1nv+XR+I1/LRpOJKrJfwSKozsKzzmbU/1cCQQDpbiLwmb8mUj6JaZ+q5PNwArCBNaAw6Lz8icwK 9 | x3nsjBQOYOpUKndVLIucwSv8qg9jwvKAgiHTgJGpjl7uh8tJAkEArsIuSvJIxksA3ah2CWa3yJHo 10 | cTaqYYhzUTLDdPRiAIcPtA9lBtb8LttDQxvOq89l/BWzlYMceopmkyobelNTzwJAVcEMPO9+dYmJ 11 | R9nxukpZ1DBov08ABne51dyZhOw7MldTluSrsTfYlwXCVFfy3ONsu+2GQQeNfbGh0XRoE6D3YQJB 12 | AOydhEuQmAxEeluZ4/5phvJuBczDssf38wQWWuOTsnvZTPQHp1oC4bDSD7YdpiGyks9tc0Wcvobu 13 | kcAfBkNnr6g= 14 | -----END RSA PRIVATE KEY----- -------------------------------------------------------------------------------- /tests/Testcases/xor5/rtl/xor5.v: -------------------------------------------------------------------------------- 1 | module xor5( 2 | a, 3 | out); 4 | 5 | input wire [4:0] a; 6 | output wire out; 7 | `pragma protect begin_protected 8 | `pragma protect author = "Verific" 9 | `pragma protect author_info = "Verific Corporation" 10 | `pragma protect data_method = "aes128-cbc" 11 | `pragma protect key_keyowner = "Verific" 12 | `pragma protect key_keyname = "key1" 13 | `pragma protect key_method = "rsa" 14 | `pragma protect encoding = (enctype = "base64", line_length = 64, bytes = 128), key_block 15 | F4u+vmSjeR5iyb8Gg0v/1UkRL44XXrhfLU1zPBxujxQ5YkNmhffzqSn6cqoDSzzM 16 | 6oq49VUbE7xlvv0ZP5wBwpDGNaI27wzaU2AJv6cHc7YpaJpRWTCFgjYOvSEfgJDi 17 | Z3oiUYm2Hdj9czIQcDa3BbQcUAqZGpmJUMWsnDVdkc0= 18 | `pragma protect encoding = (enctype = "base64", line_length = 64, bytes = 128), data_block 19 | adZ3bhMjiYoszIl8qAFwDKok8boWXomc5En3xbKsLET7vJh1+XVa8vX6nmiweMnm 20 | 0pnYRVSIG98KM7TsxMJcEQ== 21 | `pragma protect end_protected 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /tests/tcl_examples/aes_decrypt_gate/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 100 MHz (10nS period) 4 | create_clock -period 10 clk 5 | -------------------------------------------------------------------------------- /tests/tcl_examples/aes_decrypt_gate/raptor_cmd.tcl: -------------------------------------------------------------------------------- 1 | # /******************************************************************************* 2 | # Copyright (c) 2022-2024 Rapid Silicon 3 | # This source code contains proprietary information belonging to Rapid Silicon 4 | # (the "licensor") released under license and non-disclosure agreement to the 5 | # recipient (the "licensee"). 6 | # The information shared and protected by the license and non-disclosure agreement 7 | # includes but is not limited to the following: 8 | # * operational algorithms of the product 9 | # * logos, graphics, source code, and visual presentation of the product 10 | # * confidential operational information of the licensor 11 | # The recipient of this source code is NOT permitted to publicly disclose, 12 | # re-use, archive beyond the period of the license agreement, transfer to a 13 | # sub-licensee, or re-implement any portion of the content covered by the license 14 | # and non-disclosure agreement without the prior written consent of the licensor. 15 | # *********************************************************************************/ 16 | # Version : 2024.02 17 | # Build : 1.0.0 18 | # Hash : 28a24fb 19 | # Date : Feb 23 2024 20 | # Type : Engineering 21 | # Log Time : Sun Feb 25 05:15:29 2024 GMT 22 | source /home/alain/Neulink-Semi/Raptor/build/share/raptor/etc/init/flow.tcl 23 | gui_start 24 | gui_stop; exit 25 | gui_stop 26 | -------------------------------------------------------------------------------- /tests/tcl_examples/aes_decrypt_gate/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ######################################### 2 | # Rapid Silicon Design Example # 3 | # aes_decrypt_gate - Gate-level Design # 4 | # Raptor compilation TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ######################################### 7 | 8 | # Project name 9 | set project_name AES_DECRYPT_GATE 10 | 11 | message "Creating $project_name of type gate-level..." 12 | create_design $project_name -type gate-level 13 | target_device 1VG28 14 | read_netlist decrypt_top.v 15 | add_constraint_file constraints.sdc 16 | 17 | # Compilation 18 | message "Compiling $project_name..." 19 | 20 | analyze 21 | 22 | # Converts Verilog gate-level netlist to Eblif 23 | synthesize 24 | 25 | packing 26 | place 27 | route 28 | sta 29 | power 30 | bitstream 31 | 32 | message "Completed run_raptor.tcl\n" 33 | -------------------------------------------------------------------------------- /tests/tcl_examples/aes_decrypt_verilog/Src/InvAddRoundKey.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module InvAddRoundKey( 4 | input [0:127] din0, 5 | input [0:127] din1, 6 | input [0:127] rkey, 7 | input S, 8 | output [0:127] dout); 9 | 10 | logic [0:127] tmp; 11 | 12 | always_comb 13 | tmp <= S? din1 : din0; 14 | 15 | assign dout = tmp ^ rkey; 16 | endmodule -------------------------------------------------------------------------------- /tests/tcl_examples/aes_decrypt_verilog/Src/MUXF7.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module MUXF7 (output O, input I0, input I1, input S); 4 | assign O = (S)? I1 : I0; 5 | endmodule 6 | -------------------------------------------------------------------------------- /tests/tcl_examples/aes_decrypt_verilog/Src/MUXF8.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module MUXF8 (output O, input I0, input I1, input S); 4 | assign O = (S)? I1 : I0; 5 | endmodule 6 | -------------------------------------------------------------------------------- /tests/tcl_examples/aes_decrypt_verilog/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 100 MHz (10nS period) 4 | create_clock -period 10 clk 5 | -------------------------------------------------------------------------------- /tests/tcl_examples/and2_verilog/Src/and2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // and2_verilog // 5 | // and2.v - Top-level file of simple 2-input AND gate // 6 | //////////////////////////////////////////////////////// 7 | 8 | module and2 ( 9 | input a, 10 | input b, 11 | input clk, 12 | input reset, 13 | output reg c = 1'b0 14 | ); 15 | 16 | reg a_reg, b_reg = 1'b0; 17 | 18 | always@(posedge clk) 19 | if (reset) begin 20 | a_reg <= 1'b0; 21 | b_reg <= 1'b0; 22 | c <= 1'b0; 23 | end else begin 24 | a_reg <= a; 25 | b_reg <= b; 26 | c <= a_reg & b_reg; 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /tests/tcl_examples/and2_verilog/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 200 MHz (5nS period) 4 | #create_clock -period 5 clk 5 | #set_input_delay -max 0 -clock clk [get_ports {a}] 6 | #set_input_delay -max 0 -clock clk [get_ports {b}] 7 | #set_input_delay -max 0 -clock clk [get_ports {reset}] 8 | #set_output_delay -max 0 -clock clk [get_ports {c}] 9 | 10 | -------------------------------------------------------------------------------- /tests/tcl_examples/and2_verilog/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_pin_loc a HP_1_1_0N 2 | set_pin_loc b HP_1_2_1P 3 | set_pin_loc reset HP_1_3_1N 4 | set_pin_loc c HP_1_2_1P 5 | set_pin_loc clk HP_1_CC_18_9P 6 | -------------------------------------------------------------------------------- /tests/tcl_examples/and2_verilog/readme_and2_verilog.txt: -------------------------------------------------------------------------------- 1 | and2_verilog 2 | ============ 3 | 4 | Description 5 | ----------- 6 | This is a simple design consisting of a registered, 2-input AND-gate constrained to a 200 MHz clock. This example includes a Verilog testbench and executes an RTL simulation using the Icarus Verilog simulator prior to compiling design in the Raptor software. 7 | 8 | 9 | Files 10 | ----- 11 | Src/and2.v - Top-level design file containing and2 module 12 | Src/testbench_and2.v - Simulation testbench for and2 13 | constraints.sdc - Timing constraints file for and2 14 | run_raptor.tcl - TCL file to create and execute project 15 | gtkwave.tcl - TCL script to view simulation results in gtwwave viewer 16 | 17 | 18 | Running the Design 19 | ------------------ 20 | The design can be run in one of three ways: 21 | 22 | Intereactive GUI: 23 | raptor 24 | Then create the project using the following steps: 25 | New Project - Project Name: and2 26 | Type of Project: RTL Project 27 | Add Design Files: Add Src/and2.v 28 | Add Simulation Files: Add Src/testbench_and2.v 29 | Add Design Constraints: constraints.sdc 30 | Select target Design: Any device you like 31 | Start Compilation of the Design 32 | Once the run has completed, to view the simulation waveform: 33 | gtkwave -S gtkwave.tcl 34 | 35 | 36 | Automated GUI: 37 | raptor --script run_raptor.tcl 38 | Once the run has completed, to view the simulation waveform: 39 | gtkwave -S gtkwave.tcl 40 | 41 | 42 | Automated Command-line: 43 | raptor --script run_raptor.tcl --batch 44 | 45 | -------------------------------------------------------------------------------- /tests/tcl_examples/and2_verilog/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # and2_verilog - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name and2 10 | 11 | message "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file -V_2001 ./Src/and2.v 14 | # Top-module can automatically be indentified or implicitly specified here 15 | set_top_module and2 16 | add_constraint_file constraints.sdc 17 | add_constraint_file pin_mapping.pin 18 | # Simulation 19 | add_simulation_file ./Src/testbench_and2.v 20 | set_top_testbench testbench_and2 21 | # Device target 22 | target_device 1VG28 23 | 24 | # RTL Simulation 25 | simulate rtl icarus 26 | 27 | #wave_open and2/and2.vcd 28 | #wave_show reset 29 | #wave_show clk 30 | #wave_show a 31 | #wave_show b 32 | #wave_show a_delay_by_2 33 | #wave_show b_delay_by_2 34 | #wave_show c 35 | #wave_cmd gtkwave::/Time/Zoom/Zoom_Full 36 | 37 | # Compilation 38 | message "Compiling $project_name..." 39 | analyze 40 | 41 | synthesize delay 42 | 43 | # Gate Simulation 44 | simulate gate icarus 45 | 46 | packing 47 | place 48 | route 49 | 50 | # Post PnR Simulation 51 | simulate pnr icarus 52 | 53 | sta 54 | power 55 | bitstream 56 | 57 | message "Completed $project_name...\n" 58 | -------------------------------------------------------------------------------- /tests/tcl_examples/axi2axilite_bridge/v1_0/axi2axilite_bridge.tcl: -------------------------------------------------------------------------------- 1 | create_design axi2axilite_bridge_prj 2 | 3 | target_device 1VG28 4 | 5 | set IP_PATH ./axi2axilite_bridge_prj/run_1/IPs/ 6 | 7 | #Configuring axi2axilite_bridge_v1_0 IP 8 | configure_ip axi2axilite_bridge_v1_0 -mod_name axi2axilite_bridge_wrapper -Pdata_width=64 -Paddr_width=8 -out_file $IP_PATH/axi2axilite_bridge_wrapper 9 | 10 | #Generate IP 11 | ipgenerate 12 | 13 | #Add generate IP as a design and synthesize it 14 | add_design_file $IP_PATH/rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_wrapper/src/axi2axilite_bridge_wrapper_v1_0.v 15 | add_library_path $IP_PATH/rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_wrapper/src/ 16 | set_top_module axi2axilite_bridge_wrapper 17 | analyze 18 | synth delay 19 | 20 | packing 21 | place 22 | route 23 | 24 | sta 25 | power 26 | bitstream 27 | 28 | -------------------------------------------------------------------------------- /tests/tcl_examples/counter_verilog/Src/counter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ///////////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // counter_verilog // 5 | // counter.v - Top-level file of paramatizable 32-bit counter // 6 | ///////////////////////////////////////////////////////////////// 7 | 8 | module counter #( 9 | parameter counter_width = 32 10 | ) ( 11 | input clk, 12 | input reset, 13 | output reg [counter_width-1:0] result = {counter_width{1'b0}} 14 | ); 15 | 16 | always @(posedge clk) 17 | if (reset) 18 | result = {counter_width{1'b0}}; 19 | else 20 | result = result + 1'b1; 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /tests/tcl_examples/counter_verilog/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 200 MHz (5nS period) 4 | create_clock -period 5 clk 5 | -------------------------------------------------------------------------------- /tests/tcl_examples/counter_verilog/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | # Only pin out one result bit as an example. 2 | set_pin_loc {result[0]} HP_1_1_0N 3 | 4 | set_pin_loc reset HP_1_3_1N 5 | 6 | # Select a clock capable IO to bring in an external clock 7 | set_pin_loc clk HP_1_CC_18_9P 8 | -------------------------------------------------------------------------------- /tests/tcl_examples/counter_verilog/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | ## Rapid Silicon Design Example # 3 | ## counter_verilog - RTL design # 4 | ## Raptor execution TCL file # 5 | ## raptor --script run_raptor.tcl # 6 | ###################################### 7 | 8 | 9 | set project_name counter 10 | 11 | message "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file Src/counter.v 14 | # optional to specify top-level as it can be automatically detected 15 | set_top_module counter 16 | add_constraint_file constraints.sdc 17 | add_constraint_file pin_mapping.pin 18 | # Device target 19 | target_device 1VG28 20 | 21 | # Compilation 22 | message "Compiling $project_name..." 23 | analyze 24 | # Synthesize optimizing for delay 25 | synthesize delay 26 | 27 | # Setup simulation with auto-testbench "RTL vs gate" and "RTL vs pnr" 28 | setup_lec_sim 29 | 30 | # Simulate RTL vs gate 31 | simulation_options compilation icarus gate 32 | simulate gate icarus 33 | 34 | packing 35 | place 36 | route 37 | 38 | # Simulate RTL vs post-pnr 39 | simulation_options compilation icarus pnr 40 | simulate pnr icarus 41 | 42 | sta 43 | power 44 | bitstream 45 | 46 | message "Completed $project_name...\n" 47 | -------------------------------------------------------------------------------- /tests/tcl_examples/counter_vhdl/Src/UP_COUNTER.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 4 | -- FPGA projects using Verilog code VHDL code 5 | -- fpga4student.com: FPGA projects, Verilog projects, VHDL projects 6 | -- VHDL project: VHDL code for counters with testbench 7 | -- VHDL project: VHDL code for up counter 8 | entity UP_COUNTER is 9 | Port ( clock0: in std_logic; -- clock input 10 | reset: in std_logic; -- reset input 11 | counter: out std_logic_vector(3 downto 0) -- output 4-bit counter 12 | ); 13 | end UP_COUNTER; 14 | 15 | architecture Behavioral of UP_COUNTER is 16 | signal counter_up: std_logic_vector(3 downto 0); 17 | begin 18 | -- up counter 19 | process(clock0) 20 | begin 21 | if(rising_edge(clock0)) then 22 | if(reset='1') then 23 | counter_up <= x"0"; 24 | else 25 | counter_up <= counter_up + x"1"; 26 | end if; 27 | end if; 28 | end process; 29 | counter <= counter_up; 30 | 31 | end Behavioral; 32 | -------------------------------------------------------------------------------- /tests/tcl_examples/counter_vhdl/Src/testbench.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | -- FPGA projects using Verilog code VHDL code 4 | -- fpga4student.com: FPGA projects, Verilog projects, VHDL projects 5 | -- VHDL project: VHDL code for counters with testbench 6 | -- VHDL project: Testbench VHDL code for up counter 7 | entity tb_counters is 8 | end tb_counters; 9 | 10 | architecture Behavioral of tb_counters is 11 | 12 | component UP_COUNTER 13 | Port ( clock0: in std_logic; -- clock input 14 | reset: in std_logic; -- reset input 15 | counter: out std_logic_vector(3 downto 0) -- output 4-bit counter 16 | ); 17 | end component; 18 | signal reset,clk: std_logic; 19 | signal counter:std_logic_vector(3 downto 0); 20 | 21 | begin 22 | dut: UP_COUNTER port map (clock0 => clk, reset=>reset, counter => counter); 23 | -- Clock process definitions 24 | clock_process :process 25 | begin 26 | clk <= '0'; 27 | wait for 10 ns; 28 | clk <= '1'; 29 | wait for 10 ns; 30 | end process; 31 | 32 | 33 | -- Stimulus process 34 | stim_proc: process 35 | begin 36 | -- hold reset state for 100 ns. 37 | reset <= '1'; 38 | wait for 20 ns; 39 | reset <= '0'; 40 | wait; 41 | end process; 42 | end Behavioral; 43 | -------------------------------------------------------------------------------- /tests/tcl_examples/counter_vhdl/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 200 MHz (5nS period) 4 | create_clock -period 5 clock0 5 | -------------------------------------------------------------------------------- /tests/tcl_examples/counter_vhdl/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | # Only pin out one counter bit as an example. 2 | set_pin_loc {counter[0]} HP_1_1_0N 3 | 4 | set_pin_loc reset HP_1_3_1N 5 | 6 | # Select a clock capable IO to bring in an external clock 7 | set_pin_loc clock0 HP_1_CC_18_9P 8 | -------------------------------------------------------------------------------- /tests/tcl_examples/counter_vhdl/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # counter_vhdl - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name counter 10 | 11 | message "Creating $project_name..." 12 | create_design $project_name 13 | add_design_file -VHDL_1993 Src/UP_COUNTER.vhd 14 | set_top_module UP_COUNTER 15 | add_constraint_file constraints.sdc 16 | add_constraint_file pin_mapping.pin 17 | # Testbench 18 | add_simulation_file -VHDL_1993 Src/testbench.vhd 19 | set_top_testbench tb_counters 20 | # Device target 21 | target_device 1VG28 22 | 23 | # Compilation/Simulation 24 | message "Compiling $project_name..." 25 | analyze 26 | 27 | # RTL Simulation 28 | simulation_options "ghdl" "simulation" "--stop-time=1000ns" 29 | simulate "rtl" "ghdl" syn_tb_rtl.fst 30 | 31 | # Synthesis 32 | parser_type ghdl 33 | pnr_netlist_lang vhdl 34 | synthesize delay 35 | 36 | # Post-Synthesis gate-level Simulation 37 | simulate "gate" "ghdl" syn_tb_gate.fst 38 | 39 | # Pack/Place/Route 40 | packing 41 | place 42 | route 43 | 44 | # Post-Route Simulation 45 | # simulate pnr ghdl syn_tb_pnr.fst 46 | 47 | # Static Timing Analysis 48 | sta 49 | 50 | # Bitstream Generation 51 | # bitstream 52 | 53 | message "Completed $project_name...\n" 54 | -------------------------------------------------------------------------------- /tests/tcl_examples/oneff_verilog/constraints.sdc: -------------------------------------------------------------------------------- 1 | # -name is used for creating virtual clocks. For actual clock, do not use the -name option 2 | create_clock -period 2.5 clock0 3 | set_input_delay 1 -clock clock0 [get_ports {d}] 4 | set_input_delay 1 -clock clock0 [get_ports {rstn}] 5 | set_output_delay 1 -clock clock0 [get_ports {q}] 6 | -------------------------------------------------------------------------------- /tests/tcl_examples/oneff_verilog/dut.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ///////////////////////////////////////////////////////////// 3 | // Rapid Silicon Raptor Example Design // 4 | // One flipflop example, with Verilator testbench // 5 | ///////////////////////////////////////////////////////////////// 6 | 7 | module dut (input d, 8 | input rstn, 9 | input clock0, 10 | output reg q); 11 | 12 | always @ (posedge clock0 or negedge rstn) 13 | begin 14 | if (!rstn) 15 | q <= 0; 16 | else 17 | q <= d; 18 | end 19 | endmodule 20 | 21 | -------------------------------------------------------------------------------- /tests/tcl_examples/oneff_verilog/pin_mapping.pin: -------------------------------------------------------------------------------- 1 | set_pin_loc d HP_1_1_0N 2 | set_pin_loc rstn HP_1_2_1P 3 | set_pin_loc q HP_1_3_1N 4 | 5 | # Select a clock capable IO to bring in an external clock 6 | set_pin_loc clock0 HP_1_CC_18_9P 7 | -------------------------------------------------------------------------------- /tests/tcl_examples/oneff_verilog/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | # Design 2 | create_design oneff_gemini 3 | add_design_file -SV_2009 dut.v 4 | set_top_module dut 5 | add_constraint_file pin_mapping.pin 6 | add_constraint_file constraints.sdc 7 | 8 | # Testbench 9 | add_simulation_file -SV_2009 syn_tb.v 10 | add_simulation_file sim_main.cpp 11 | set_top_testbench syn_tb 12 | 13 | # Device target 14 | target_device 1VG28 15 | 16 | # Compilation/Simulation 17 | analyze 18 | 19 | # clean default flags for wrapper 20 | simulation_options verilator compilation rtl "" 21 | # RTL Simulation 22 | simulate rtl verilator syn_tb_rtl.fst 23 | 24 | # Synthesis 25 | synth_options -inferred_io 26 | synthesize delay 27 | 28 | # clean default flags for wrapper 29 | simulation_options verilator compilation gate "" 30 | # Post-Synthesis gate-level Simulation 31 | simulate gate verilator syn_tb_gate.fst 32 | 33 | # Pack/Place/Route 34 | packing 35 | place 36 | route 37 | 38 | # clean default flags for wrapper 39 | simulation_options verilator compilation pnr "" 40 | # Post-Route Simulation 41 | simulate pnr verilator syn_tb_pnr.fst 42 | 43 | # Static Timing Analysis 44 | sta 45 | 46 | # Bitstream Generation 47 | #bitstream 48 | -------------------------------------------------------------------------------- /tests/tcl_examples/oneff_verilog/sim_main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "Vsyn_tb.h" 4 | #include "verilated.h" 5 | 6 | #if VM_TRACE_VCD == 1 7 | #include "verilated_vcd_c.h" 8 | #else 9 | #include "verilated_fst_c.h" 10 | #endif 11 | 12 | double sc_time_stamp() { 13 | return 0; 14 | } 15 | 16 | int main(int argc, char** argv, char** env) { 17 | Verilated::commandArgs(argc, argv); 18 | Vsyn_tb* top = new Vsyn_tb; 19 | // init trace dump 20 | std::string waveformFile; 21 | if (argc > 1) { 22 | waveformFile = argv[1]; 23 | std::cout << "Waveform file: " << waveformFile << std::endl; 24 | } else { 25 | waveformFile = "syn_tb.fst"; 26 | } 27 | Verilated::traceEverOn(true); 28 | Verilated::assertOn(true); 29 | 30 | #if VM_TRACE_FST == 1 31 | VerilatedFstC* tfp = new VerilatedFstC; 32 | # else 33 | VerilatedVcdC* tfp = new VerilatedVcdC; 34 | #endif 35 | 36 | top->trace(tfp, 99); 37 | tfp->open(waveformFile.c_str()); 38 | top->rstn = 0; 39 | top->clk = 0; 40 | 41 | // run simulation for 20 clock periods 42 | // Only generate the clock in C, 43 | // the testbench is in Verilog 44 | for(int i = 0; i < 20; i++) { 45 | top->rstn = (i >= 2); 46 | for(int clk = 0; clk < 2; ++clk) { 47 | top->eval(); 48 | tfp->dump((2 * i) + clk); 49 | top->clk = !top->clk; 50 | } 51 | } 52 | tfp->close(); 53 | delete top; 54 | exit(0); 55 | } 56 | -------------------------------------------------------------------------------- /tests/tcl_examples/oneff_verilog/syn_tb.v: -------------------------------------------------------------------------------- 1 | module syn_tb(input logic rstn, 2 | input logic clk, 3 | output logic rtl_q); 4 | 5 | logic d; 6 | integer state = 0; 7 | 8 | // Stimulus + Model Checking 9 | always @ (posedge clk) begin 10 | if (state==0) begin 11 | d <= 0; 12 | state <= state+1; 13 | end 14 | else if (state==1) begin 15 | d <= 1; 16 | state <= state+1; 17 | end 18 | else if (state==2) begin 19 | d <= 1; 20 | state <= state+1; 21 | end 22 | else if (state==3) begin 23 | d <= 0; 24 | state <= state+1; 25 | end 26 | else if (state==4) begin 27 | d <= 0; 28 | state <= state+1; 29 | end 30 | else if (state==5) begin 31 | d <= 1; 32 | state <= state+1; 33 | end 34 | else if (state==6) begin 35 | d <= 0; 36 | state <= state+1; 37 | end 38 | else if (state==7) begin 39 | d <= 0; 40 | state <= state+1; 41 | end 42 | else if (state==8) begin 43 | d <= 0; 44 | state <= state+1; 45 | end 46 | $display("d = %0d, q = %0d", d, rtl_q); 47 | 48 | end 49 | 50 | dut rtl_model(d, rstn, clk, rtl_q); 51 | 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /tests/tcl_examples/sasc_testcase/Src/timescale.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | -------------------------------------------------------------------------------- /tests/tcl_examples/sasc_testcase/constraints.sdc: -------------------------------------------------------------------------------- 1 | # SDC file example 2 | 3 | # Setting a clock frequency of 200 MHz (5nS period) 4 | create_clock -period 5 clk 5 | -------------------------------------------------------------------------------- /tests/tcl_examples/sasc_testcase/run_raptor.tcl: -------------------------------------------------------------------------------- 1 | ##################################### 2 | # Rapid Silicon Design Example # 3 | # sasc_testcase - RTL design # 4 | # Raptor execution TCL file # 5 | # raptor --script run_raptor.tcl # 6 | ##################################### 7 | 8 | # Project name 9 | set project_name sasc 10 | 11 | message "Creating $project_name..." 12 | # Create Project 13 | create_design $project_name 14 | # Device setup 15 | target_device 1VG28 16 | # Design setup 17 | add_design_file ./Src/timescale.v ./Src/sasc_brg.v ./Src/sasc_fifo4.v ./Src/sasc.v 18 | add_constraint_file constraints.sdc 19 | set_top_module sasc 20 | 21 | # Compilation 22 | message "Compiling $project_name..." 23 | 24 | analyze 25 | synthesize 26 | 27 | setup_lec_sim 28 | 29 | # Simulate RTL vs gate 30 | simulation_options compilation verilator gate 31 | simulate gate verilator 32 | 33 | packing 34 | place 35 | route 36 | 37 | # Simulate RTL vs post-pnr 38 | simulation_options compilation verilator pnr 39 | simulate pnr verilator 40 | 41 | sta 42 | power 43 | bitstream 44 | 45 | message "Completed $project_name...\n" 46 | --------------------------------------------------------------------------------