├── .gitignore ├── MUXcomplexNto1 ├── .gitignore ├── EdaPlaygroundSimulation │ └── SimulationMUXcomplexNto1_tb_eda_playground.jpg ├── MUXcomplexNto1.xpr ├── component.xml ├── hdl │ ├── MUXcomplexNto1.tcl │ ├── MUXcomplexNto1_handComm.vhd │ ├── MUXcomplexNto1_synch.vhd │ ├── MUXcomplexNto1_wb.vhd │ ├── MUXcomplexNto1top.vhd │ └── mylib.vhd └── xgui │ └── MUXcomplexNto1_v1_0.tcl ├── MUXrealNto1 ├── .gitignore ├── GenerateBoringVivadoIPInputList.m ├── MUXrealNto1.xpr ├── component.xml ├── hdl │ ├── MUXrealNto1_handcomm.vhd │ ├── MUXrealNto1_synch.vhd │ ├── MUXrealNto1_wb.vhd │ ├── MUXrealNto1top.vhd │ ├── MUXrealNto1top.vhd.save │ └── mylib.vhd └── xgui │ └── MUXrealNto1_v1_0.tcl ├── README.md ├── ad9767 ├── ad9767.tcl ├── ad9767.xdc ├── component.xml ├── hdl │ └── ad9767.v └── xgui │ └── ad9767_v1_0.tcl ├── add_constComplex ├── component.xml ├── hdl │ ├── add_constComplex.vhd │ ├── add_constComplex_handComm.vhd │ ├── add_constComplex_logic.vhd │ ├── add_constComplex_rst.vhd │ ├── add_constComplex_synchronizer_vector.vhd │ └── wb_add_constComplex.vhd ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── top_add_constComplex.gtkw │ ├── top_add_constComplex_tb.py │ └── top_dut.vhd ├── simulation_signed_ext │ ├── .gitignore │ ├── Makefile │ ├── top_enable.gtkw │ └── top_enable_tb.vhd └── xgui │ └── add_constComplex_v1_0.tcl ├── add_constReal ├── add_constReal.xdc ├── add_constReal.xml ├── add_constReal_ooc.xdc ├── component.xml ├── hdl │ ├── add_constReal.vhd │ ├── add_constReal_handComm.vhd │ ├── add_constReal_logic.vhd │ ├── add_constReal_rst.vhd │ ├── add_constReal_synchronizer_vector.vhd │ └── wb_add_constReal.vhd ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── top_add_constReal.gtkw │ ├── top_add_constReal_tb.py │ └── top_dut.vhd └── xgui │ └── add_constReal_v1_0.tcl ├── adder_substracter_complex ├── component.xml ├── hdl │ └── adder_substracter_complex.vhd └── xgui │ └── adder_substracter_complex_v1_0.tcl ├── adder_substracter_real ├── component.xml ├── hdl │ └── adder_substracter_real.vhd └── xgui │ └── adder_substracter_real_v1_0.tcl ├── axiStreamToComplex ├── component.xml ├── hdl │ └── axiStreamToComplex.vhd └── xgui │ └── axiStreamToComplex_v1_0.tcl ├── axiStreamToReal ├── component.xml ├── hdl │ └── axiStreamToReal.vhd └── xgui │ └── axiStreamToReal_v1_0.tcl ├── axi_deltaSigma ├── axi_deltaSigma_constr.xdc ├── component.xml ├── hdl │ ├── axi_ctrlif.vhd │ ├── axi_deltaSigma.vhd │ ├── deltaSigma.v │ ├── deltaSigma_clkgen.vhd │ ├── deltaSigma_controller.vhd │ ├── deltaSigma_tx.vhd │ ├── dma_fifo.vhd │ └── pl330_dma_fifo.vhd ├── simu_deltaSigmaV │ ├── Makefile │ ├── top_cs4344.gtkw │ └── top_cs4344_tb.v ├── simu_dma_fifo │ ├── .gitignore │ ├── Makefile │ ├── top_dma_fifo.gtkw │ └── top_dma_fifo_tb.vhd └── xgui │ └── axi_deltaSigma_v1_0.tcl ├── axi_to_dac ├── axi_to_dac.xdc ├── axi_to_dac_hw.tcl ├── component.xml ├── hdl │ ├── axi_to_dac.vhd │ ├── axi_to_dac_handcomm.vhd │ ├── axi_to_dac_sync_vect.vhd │ └── wb_axi_to_dac.vhd └── xgui │ └── axi_to_dac_v1_0.tcl ├── boards.def ├── cacode ├── component.xml ├── hdl │ ├── cacode.vhd │ ├── cacode_g1_gen.vhd │ └── cacode_g2_gen.vhd ├── simuC │ └── main.c ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── cacode.m │ ├── test.m │ ├── top_cacode.gtkw │ └── top_cacode_tb.vhd └── xgui │ └── cacode_v1_0.tcl ├── check_valid_burst ├── component.xml ├── hdl │ ├── check_valid_burst.vhd │ ├── cvb_check_mean.vhd │ ├── cvb_cpt_en.vhd │ ├── cvb_dual_ram.vhd │ ├── cvb_gen_new_flow.vhd │ ├── cvb_handComm.vhd │ ├── cvb_logic.vhd │ ├── cvb_ram.vhd │ └── wb_cvb.vhd ├── simulation │ ├── Makefile │ ├── genOracle │ │ ├── .exrc │ │ ├── Makefile │ │ ├── main.c │ │ └── mergeData.sh │ ├── readComplexFromFile.vhd │ ├── readFromFile.vhd │ ├── real_data.dat │ ├── top_cvb.gtkw │ └── top_cvb_tb.vhd └── xgui │ └── check_valid_burst_v1_0.tcl ├── clkChangeComplex ├── component.xml ├── hdl │ └── clkChangeComplex.vhd └── xgui │ └── clkChangeComplex_v1_0.tcl ├── clock_prescaler ├── clock_prescaler.xpr ├── component.xml ├── hdl │ └── clock_prescaler.vhd ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── result.txt │ └── top_clock_prescaler_tb.vhd └── xgui │ └── clock_prescaler_v1_0.tcl ├── complexToAxiStream ├── component.xml ├── hdl │ └── complexToAxiStream.vhd └── xgui │ └── complexToAxiStream_v1_0.tcl ├── const_complex ├── component.xml ├── hdl │ └── const_complex.vhd └── xgui │ └── const_complex_v1_0.tcl ├── const_real ├── component.xml ├── const_real.xpr ├── hdl │ └── const_real.vhd └── xgui │ └── const_real_v1_0.tcl ├── convertComplexToReal ├── component.xml ├── convertComplexToReal.xml ├── hdl │ └── convertComplexToReal.vhd └── xgui │ └── convertComplexToReal_v1_0.tcl ├── convertRealToComplex ├── component.xml ├── hdl │ └── convertRealToComplex.vhd └── xgui │ └── convertRealToComplex_v1_0.tcl ├── cordicAtan ├── component.xml ├── hdl │ ├── cordicAtan.vhd │ └── cordicAtan_impl.vhd └── xgui │ └── cordicAtan_v1_0.tcl ├── cplx_conj ├── component.xml ├── hdl │ └── cplx_conj.v ├── simulation │ ├── Makefile │ ├── top_cplx_conj_simu.gtkw │ ├── top_cplx_conj_simu_tb.py │ └── top_dut.v └── xgui │ └── cplx_conj_v1_0.tcl ├── dataComplex_dma_direct ├── component.xml ├── hdl │ ├── axi_dataComplex_dma_direct.vhd │ ├── dataComplex_dma_direct.vhd │ ├── dataComplex_dma_direct_handCom.vhd │ ├── dataComplex_dma_direct_sync.vhd │ └── wb_dataComplex_dma_direct.vhd ├── simulation │ ├── Makefile │ ├── top_dataDma.gtkw │ ├── top_dataDma.vhd │ └── top_dataDma_tb.py └── xgui │ └── dataComplex_dma_direct_v1_0.tcl ├── dataComplex_to_ram ├── component.xml ├── dataComplex_to_ram.xdc ├── hdl │ ├── dataComplex_handCom.vhd │ ├── dataComplex_logic.vhd │ ├── dataComplex_resizer.vhd │ ├── dataComplex_storage.vhd │ ├── dataComplex_sync.vhd │ ├── dataComplex_to_ram.vhd │ ├── dataComplex_top.vhd │ └── wb_dataComplex.vhd ├── simulation │ ├── Makefile │ ├── top_data_subtop.gtkw │ └── top_data_subtop_tb.vhd └── xgui │ └── dataComplex_to_ram_v1_0.tcl ├── dataComplex_to_ram_pingpong ├── component.xml ├── dataComplex_to_ram_pingpong.xdc ├── hdl │ ├── dataComplex_handCom.vhd │ ├── dataComplex_logic.vhd │ ├── dataComplex_resizer.vhd │ ├── dataComplex_storage.vhd │ ├── dataComplex_to_ram_pingpong.vhd │ ├── dataComplex_top.vhd │ └── wb_dataComplex.vhd └── xgui │ └── dataComplex_to_ram_pingpong_v1_0.tcl ├── dataReal_dma_direct ├── component.xml ├── hdl │ ├── axi_dataReal_dma_direct.vhd │ ├── dataReal_dma_direct.vhd │ ├── dataReal_dma_direct_handCom.vhd │ ├── dataReal_dma_direct_sync.vhd │ └── wb_dataReal_dma_direct.vhd ├── simulation │ ├── Makefile │ ├── top_dataDma.gtkw │ ├── top_dataDma.vhd │ └── top_dataDma_tb.py └── xgui │ └── dataReal_dma_direct_v1_0.tcl ├── dataReal_to_ram ├── component.xml ├── dataReal_to_ram.xdc ├── hdl │ ├── dataReal_handCom.vhd │ ├── dataReal_logic.vhd │ ├── dataReal_resizer.vhd │ ├── dataReal_storage.vhd │ ├── dataReal_sync.vhd │ ├── dataReal_to_ram.vhd │ ├── dataReal_top.vhd │ └── wb_dataReal.vhd └── xgui │ └── dataReal_to_ram_v1_0.tcl ├── dataReal_to_ram_pingpong ├── component.xml ├── dataReal_to_ram_pingpong.xdc ├── hdl │ ├── dataReal_handCom.vhd │ ├── dataReal_logic.vhd │ ├── dataReal_resizer.vhd │ ├── dataReal_storage.vhd │ ├── dataReal_to_ram_pingpong.vhd │ ├── dataReal_top.vhd │ └── wb_dataReal.vhd ├── simulation │ ├── Makefile │ ├── top_data_subtop.gtkw │ └── top_data_subtop_tb.vhd └── xgui │ └── dataReal_to_ram_pingpong_v1_0.tcl ├── ddmtd ├── Makefile ├── README.md ├── conf.json ├── ddmtd.xdc ├── gen_hdl.py ├── package_ip.tcl └── src │ ├── ddmtd.py │ ├── deglitcher.py │ └── fast_counter.py ├── delayTempoReal_axi ├── component.xml ├── delayTempoReal_axi.xdc ├── hdl │ ├── delayTempoReal_axi.vhd │ ├── delayTempoReal_axi_comm.vhd │ ├── delayTempoReal_axi_handCom.vhd │ ├── delayTempoReal_axi_logic.vhd │ └── delayTempoReal_axi_sync_slv.vhd ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── top_delayTempo.gtkw │ └── top_delayTempo_tb.vhd └── xgui │ ├── delayTempoReal_axi_v1_0.tcl │ └── delay_v1_0.tcl ├── dfu_frm.mk ├── dupplComplex ├── component.xml ├── dupplComplex_hw.tcl ├── gen_dupplComplex.py ├── hdl │ └── dupplComplex.vhd └── xgui │ ├── dupplComplex_1_to_2_v1_0.tcl │ └── dupplComplex_v1_0.tcl ├── dupplComplex_1_to_2 ├── component.xml ├── hdl │ └── dupplComplex_1_to_2.vhd └── xgui │ └── dupplComplex_1_to_2_v1_0.tcl ├── dupplReal ├── component.xml ├── dupplReal_hw.tcl ├── gen_dupplReal.py ├── hdl │ └── dupplReal.vhd └── xgui │ ├── dupplComplex_v1_0.tcl │ ├── dupplReal_1_to_2_v1_0.tcl │ └── dupplReal_v1_0.tcl ├── dupplReal_1_to_2 ├── component.xml ├── dupplReal_1_to_2_hw.tcl ├── hdl │ └── dupplReal_1_to_2.vhd └── xgui │ └── dupplReal_1_to_2_v1_0.tcl ├── expanderComplex ├── component.xml ├── hdl │ └── expanderComplex.vhd ├── simulation │ ├── Makefile │ ├── top_expanderComplex.gtkw │ ├── top_expanderComplex.vhd │ └── top_expanderComplex_tb.py └── xgui │ └── expanderComplex_v1_0.tcl ├── expanderReal ├── component.xml ├── expanderReal_hw.tcl ├── hdl │ └── expanderReal.vhd ├── simulation │ ├── Makefile │ ├── top_expanderReal.gtkw │ ├── top_expanderReal.vhd │ ├── top_expanderReal_tb.py │ └── top_expanderreal └── xgui │ └── expanderReal_v1_0.tcl ├── extract_data_from_burst ├── component.xml ├── extract_ooc.xdc ├── hdl │ ├── edfb_handComm.vhd │ ├── extract_data_from_burst.vhd │ └── wb_edfb.vhd └── xgui │ └── extract_data_from_burst_v1_0.tcl ├── fft ├── component.xml ├── hdl │ ├── fft.vhd │ ├── fft_axi.vhd │ ├── fft_coeff_handler.vhd │ ├── fft_comp_butterfly.vhd │ ├── fft_comp_complex.vhd │ ├── fft_data_handler.vhd │ ├── fft_handCom.vhd │ ├── fft_loop_radix.vhd │ ├── fft_loop_stage.vhd │ ├── fft_ram.vhd │ ├── fft_ram_coeff.vhd │ ├── fft_top_logic.vhd │ └── fft_transfert.vhd ├── order.txt ├── simulation │ ├── .gitignore │ ├── data_in.txt │ ├── fft.prj │ ├── fft.wcfg │ ├── gen_data │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── gen_sin_cos.m │ │ └── main.c │ ├── ghdl │ │ ├── Makefile │ │ └── top_fft.gtkw │ ├── isim.sh │ ├── isim.tcl │ ├── plot_comp.m │ ├── ram_storage16.vhd │ ├── readComplexFromFile.vhd │ ├── readFromFile.vhd │ ├── testC │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── comp_res.m │ │ ├── fft.c │ │ ├── fft.h │ │ └── main.c │ └── top_fft_tb.vhd └── xgui │ └── fft_v1_0.tcl ├── firComplex ├── component.xml ├── hdl │ ├── firComplex.vhd │ ├── firComplex_axi.vhd │ ├── firComplex_handCom.vhd │ ├── firComplex_proc.vhd │ ├── firComplex_ram.vhd │ └── firComplex_top.vhd ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── data2q.dat │ ├── ram_storage16.vhd │ ├── readFromFile.vhd │ ├── testC │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── fir.c │ │ ├── fir.h │ │ └── main.c │ ├── top_enable.gtkw │ └── top_enable_tb.vhd └── xgui │ └── firComplex_v1_0.tcl ├── firReal ├── component.xml ├── firReal_hw.tcl ├── hdl │ ├── firReal.vhd │ ├── firReal_axi.vhd │ ├── firReal_handCom.vhd │ ├── firReal_proc.vhd │ ├── firReal_ram.vhd │ └── firReal_top.vhd ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── coeff.txt │ ├── coeff16.dat │ ├── data2q.dat │ ├── dataq.dat │ ├── fake_coeff.dat │ ├── ram_storage16.vhd │ ├── readFromFile.vhd │ ├── testC │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── fir.c │ │ ├── fir.h │ │ ├── fir.o │ │ ├── main.c │ │ └── main.o │ ├── testCConst │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── datai.dat │ │ ├── dataq.dat │ │ ├── fir.c │ │ ├── fir.h │ │ └── main.c │ ├── top_enable.gtkw │ ├── top_enable_tb.vhd │ └── vivado │ │ ├── clean.sh │ │ ├── data2q.dat │ │ ├── firReal.prj │ │ ├── firReal_options.tcl │ │ ├── script.sh │ │ └── vivado.sh └── xgui │ └── firReal_v1_0.tcl ├── fpga_ip.mk ├── gen_radar_prog ├── component.xml ├── gen_radar_prog.xdc ├── hdl │ ├── gen_radar_prog.vhd │ ├── gen_radar_prog_handComm.vhd │ ├── gen_radar_prog_logic.vhd │ └── wb_gen_radar_prog.vhd ├── simulation │ ├── Makefile │ ├── top_enable.gtkw │ └── top_enable_tb.vhd └── xgui │ └── gen_radar_prog_v1_0.tcl ├── iir_lpf_complex ├── component.xml ├── hdl │ └── iir_lpf_complex.vhd └── xgui │ └── iir_lpf_complex_v1_0.tcl ├── iir_lpf_real ├── component.xml ├── hdl │ ├── Makefile │ ├── iir_lpf_real.vhd │ ├── iir_lpf_real_tb.vhd │ └── run.sh ├── iir_lpf_freqz.m ├── iir_lpf_real.xpr └── xgui │ └── iir_lpf_real_v1_0.tcl ├── interfaces ├── complex_v1_0 │ ├── complex.xml │ └── complex_rtl.xml └── real_v1_0 │ ├── real.xml │ └── real_rtl.xml ├── ip.xml ├── ltc2145 ├── component.xml ├── hdl │ ├── ltc2145.vhd │ └── ltc2145_cmos_capture.vhd ├── ltc2145-redpy.xdc ├── ltc2145.tcl ├── ltc2145.xdc └── xgui │ └── ltc2145_v1_0.tcl ├── lutGeneratorComplex ├── component.xml ├── hdl │ ├── lutGeneratorComplex.vhd │ ├── lutGeneratorComplex_handComm.vhd │ ├── lutGeneratorComplex_logic.vhd │ ├── lutGeneratorComplex_storage.vhd │ ├── lutGeneratorComplex_sync_vect.vhd │ └── wb_lutGeneratorComplex.vhd ├── lutGeneratorComplex.xdc ├── output.png ├── output.svg ├── run.sh ├── simulation │ ├── Makefile │ ├── top_dut.vhd │ ├── top_lutGeneratorComplex.gtkw │ └── top_tb.py └── xgui │ └── lutGeneratorComplex_v1_0.tcl ├── magnitude ├── component.xml ├── hdl │ └── magnitude.v ├── simulation │ ├── Makefile │ ├── top_dut.v │ ├── top_magnitude_simu.gtkw │ └── top_magnitude_simu_tb.py └── xgui │ └── magnitude_v1_0.tcl ├── meanComplex ├── component.xml ├── hdl │ └── meanComplex.vhd ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── top_meanComplex.gtkw │ └── top_meanComplex_tb.vhd └── xgui │ └── meanComplex_v1_0.tcl ├── meanReal ├── component.xml ├── hdl │ └── meanReal.vhd ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── top_meanReal.gtkw │ └── top_meanReal_tb.vhd └── xgui │ └── meanReal_v1_0.tcl ├── mean_vector_axi ├── component.xml ├── hdl │ ├── mean_vector_axi.vhd │ ├── mean_vector_axi_handcomm.vhd │ ├── mean_vector_axi_logic.vhd │ ├── mean_vector_axi_ram.vhd │ ├── mean_vector_axi_shift.vhd │ ├── mva_synchronizer_vector.vhd │ └── wb_mean_vector_axi.vhd ├── simulation │ ├── Makefile │ ├── top_mean_vector.gtkw │ └── top_mean_vector_tb.vhd └── xgui │ └── mean_vector_axi_v1_0.tcl ├── mixerComplex_sin ├── component.xml ├── hdl │ ├── mixerComplex_redim.vhd │ └── mixerComplex_sin.vhd ├── simuC │ ├── Makefile │ └── main.c ├── simulation │ ├── Makefile │ ├── top_mixerComplex_sin.gtkw │ ├── top_mixerComplex_sin.vhd │ └── top_mixerComplex_sin_tb.py └── xgui │ └── mixerComplex_sin_v1_0.tcl ├── mixer_sin ├── component.xml ├── hdl │ ├── mixer_redim.vhd │ └── mixer_sin.vhd ├── simulation │ ├── Makefile │ ├── top_mixer_sin.gtkw │ ├── top_mixer_sin.vhd │ └── top_mixer_sin_tb.py └── xgui │ └── mixer_sin_v1_0.tcl ├── multiplierReal ├── component.xml ├── hdl │ ├── multiplierReal.vhd │ └── multiplierReal_redim.vhd ├── simulation │ ├── Makefile │ ├── top_multiplierReal.gtkw │ ├── top_multiplierReal.vhd │ └── top_multiplierReal_tb.py └── xgui │ └── multiplierReal_v1_0.tcl ├── nco_counter ├── component.xml ├── gen_rom │ ├── .gitignore │ ├── Makefile │ ├── gen_sin_cos.m │ └── main.c ├── hdl │ ├── nco_counter.vhd │ ├── nco_counter_cos_rom.vhd │ ├── nco_counter_cos_rom_a12_d16.vhd │ ├── nco_counter_cos_rom_a16_d16.vhd │ ├── nco_counter_cos_rom_a24_d16.vhd │ ├── nco_counter_handcomm.vhd │ ├── nco_counter_logic.vhd │ ├── nco_counter_synchronizer_bit.vhd │ ├── nco_counter_synchronizer_vector.vhd │ └── wb_nco_counter.vhd ├── nco_counter.xdc ├── nco_counter.xml ├── octave │ └── demo.m ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── plot_fft.m │ ├── plot_freq.m │ ├── top_nco_counter.gtkw │ └── top_nco_counter_tb.vhd └── xgui │ ├── nco_counter_v1_0.tcl │ └── nco_single_v1_0.tcl ├── pidv3_axi ├── component.xml ├── hdl │ ├── pidv3_axi.vhd │ ├── pidv3_axi_comm.vhd │ ├── pidv3_axi_handComm.vhd │ ├── pidv3_axi_logic.vhd │ ├── pidv3_axi_sync_bit.vhd │ └── pidv3_axi_sync_vector.vhd ├── pidv3_axi.xdc └── xgui │ └── pidv3_axi_v1_0.tcl ├── preset ├── de0nanoSoc_prj_preset.tcl ├── de0nanoSoc_qsys_preset.tcl ├── redpitaya.tcl ├── redpitaya12.tcl ├── redpitaya12_preset.xml ├── redpitaya16.tcl ├── redpitaya16_preset.xml └── redpitaya_preset.xml ├── prn20b ├── component.xml ├── hdl │ ├── prn20b.vhd │ ├── prn20b_bitSync.vhd │ ├── prn20b_handCom.vhd │ ├── prn20b_logic.vhd │ ├── prn20b_presc.vhd │ ├── prn20b_vectSync.vhd │ └── wb_prn20b.vhd ├── prn20b.xdc ├── prn20b_hw.tcl ├── simuC │ └── main.c ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── top_prn20b.gtkw │ └── top_prn20b_tb.vhd └── xgui │ └── prn20b_v1_0.tcl ├── prnGenerator ├── component.xml ├── hdl │ └── prnGenerator.vhd ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── result.txt │ ├── testC │ │ ├── Makefile │ │ ├── main.c │ │ ├── result.txt │ │ └── testCIC │ ├── top_prnGenerator.gtkw │ └── top_prnGenerator_tb.vhd └── xgui │ └── prnGenerator_v1_0.tcl ├── pwm_axi ├── component.xml ├── hdl │ ├── pwm_axi.vhd │ ├── pwm_comm.vhd │ ├── pwm_cpt.vhd │ ├── pwm_handCom.vhd │ ├── pwm_logic.vhd │ ├── pwm_sync_bit.vhd │ └── pwm_sync_vector.vhd ├── pwm_axi.xdc ├── pwm_axi.xml ├── pwm_axi_hw.tcl ├── simulation │ ├── Makefile │ ├── top_pwmAxi.gtkw │ ├── top_pwmAxi.vhd │ └── top_pwmAxi_tb.py └── xgui │ └── pwm_axi_v1_0.tcl ├── quartus.mk ├── ram_to_dataReal ├── component.xml ├── hdl │ ├── ram_to_dataReal.vhd │ ├── ram_to_dataReal_bitSync.vhd │ ├── ram_to_dataReal_handComm.vhd │ ├── ram_to_dataReal_logic.vhd │ ├── ram_to_dataReal_ram.vhd │ └── wb_ram_to_dataReal.vhd └── xgui │ └── ram_to_dataReal_v1_0.tcl ├── realToAxiStream ├── component.xml ├── hdl │ └── realToAxiStream.vhd └── xgui │ └── realToAxiStream_v1_0.tcl ├── redpitaya_adc_dac_clk ├── adc_dac_clk_ooc.xdc ├── component.xml ├── hdl │ └── redpitaya_adc_dac_clk.v ├── redpitaya_adc_dac_clk.tcl ├── redpitaya_clk_pin.xdc └── xgui │ └── redpitaya_adc_dac_clk_v1_0.tcl ├── redpitaya_converters ├── component.xml ├── hdl │ ├── ad9767.v │ ├── redpitaya_adc_cmos_capture.vhd │ ├── redpitaya_adc_dac_clk.v │ └── redpitaya_converters.vhd ├── redpitaya_converters.tcl ├── redpitaya_converters.xdc ├── redpitaya_converters_adc.xdc ├── redpitaya_converters_adc16.xdc ├── redpitaya_converters_if.xml ├── redpitaya_converters_if_rtl.xml ├── redpitaya_converters_ooc.xdc └── xgui │ └── redpitaya_converters_v1_0.tcl ├── redpitaya_converters_12 ├── component.xml ├── hdl │ ├── Si571_pll.v │ ├── ad9613.v │ ├── ad9746.v │ ├── adc_dac_spi_control.v │ ├── redpitaya_adc_dac_clk.v │ ├── redpitaya_converters_12.vhd │ ├── redpitaya_converters_12_comm.vhd │ ├── redpitaya_converters_12_handComm.vhd │ ├── redpitaya_converters_12_sync_bit.vhd │ ├── redpitaya_converters_12_sync_vector.vhd │ └── spi_master.vhd ├── redpitaya_converters_12.tcl ├── redpitaya_converters_12.xdc ├── redpitaya_converters_12_adc.xdc ├── redpitaya_converters_12_if.xml ├── redpitaya_converters_12_if_rtl.xml ├── redpitaya_converters_12_ooc.xdc └── xgui │ └── redpitaya_converters_12_v1_0.tcl ├── sampleCounterComplex ├── Makefile ├── component.xml ├── core_config.tcl ├── hdl │ └── sampleCounterComplex.vhd ├── simulation │ ├── Makefile │ ├── top_dut.vhd │ ├── top_sampleCounterComplex.gtkw │ └── top_tb.py └── xgui │ └── sampleCounterComplex_v1_0.tcl ├── sampleCounterReal ├── Makefile ├── component.xml ├── core_config.tcl ├── hdl │ └── sampleCounterReal.vhd ├── simulation │ ├── Makefile │ ├── top_dut.vhd │ ├── top_sampleCounterReal.gtkw │ └── top_tb.py └── xgui │ └── sampleCounterReal_v1_0.tcl ├── scripts ├── alt_create_prj.tcl ├── alt_gen.tcl ├── alt_prj.tcl ├── gen_module_generator_xml.tcl ├── gen_module_generator_xml_quartus.tcl ├── xil_create_prj.tcl ├── xil_gen.tcl └── xil_prj.tcl ├── setenv.sh ├── shifterComplex ├── component.xml ├── hdl │ └── shifterComplex.vhd └── xgui │ └── shifterComplex_v1_0.tcl ├── shifterComplex_dyn ├── component.xml ├── hdl │ ├── shifterComplex_dyn.vhd │ ├── shifterComplex_dyn_comm.vhd │ ├── shifterComplex_dyn_handcomm.vhd │ ├── shifterComplex_dyn_logic.vhd │ └── shifterComplex_dyn_synchronizer_vector.vhd ├── shifterComplex_dyn.xdc ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── top_shifterComplex_dyn.gtkw │ └── top_shifterComplex_dyn_tb.vhd └── xgui │ └── shifterComplex_dyn_v1_0.tcl ├── shifterReal ├── component.xml ├── hdl │ └── shifterReal.vhd ├── shifterReal.xml ├── shifterReal_hw.tcl └── xgui │ └── shifterReal_v1_0.tcl ├── shifterReal_dyn ├── component.xml ├── hdl │ ├── shifterReal_dyn.vhd │ ├── shifterReal_dyn_comm.vhd │ ├── shifterReal_dyn_handcomm.vhd │ ├── shifterReal_dyn_logic.vhd │ └── shifterReal_dyn_synchronizer_vector.vhd ├── shifterReal_dyn.xdc ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── top_shifterReal_dyn.gtkw │ └── top_shifterReal_dyn_tb.vhd └── xgui │ └── shifterReal_dyn_v1_0.tcl ├── slv_to_sl_axi ├── component.xml ├── hdl │ ├── slv_to_sl_axi.vhd │ ├── slv_to_sl_axi_comm.vhd │ ├── slv_to_sl_axi_handCom.vhd │ └── slv_to_sl_axi_sync_slv.vhd ├── simulation │ ├── Makefile │ ├── top_slv_to_sl_axi.gtkw │ └── top_slv_to_sl_axi_tb.vhd ├── slv_to_sl_axi.xdc └── xgui │ └── slv_to_sl_axi_v1_0.tcl ├── switchComplex ├── component.xml ├── hdl │ ├── switchComplex.vhd │ ├── switchComplex_handComm.vhd │ ├── switchComplex_synch.vhd │ └── switchComplex_wb.vhd ├── switchComplex.xdc └── xgui │ └── switchComplex_v1_0.tcl ├── switchReal ├── component.xml ├── hdl │ ├── switchReal.vhd │ ├── switchReal_handComm.vhd │ ├── switchReal_synch.vhd │ └── switchReal_wb.vhd ├── switchReal.xdc ├── switchReal_hw.tcl └── xgui │ └── switchReal_v1_0.tcl ├── syncTrigStream ├── component.xml ├── hdl │ ├── syncTrigStream.vhd │ ├── syncTrigStream_comm.vhd │ ├── syncTrigStream_handComm.vhd │ ├── syncTrigStream_logic.vhd │ ├── syncTrigStream_sync_bit.vhd │ └── syncTrigStream_sync_vector.vhd ├── simulation │ ├── Makefile │ ├── top_syncTrigStream.gtkw │ ├── top_syncTrigStream.vhd │ └── top_syncTrigStream_tb.py ├── syncTrigStream.xdc └── xgui │ └── syncTrigStream_v1_0.tcl ├── tools ├── README.md └── print_businterfaces.py ├── unwrap_phase_diff ├── component.xml ├── hdl │ ├── _old_unwrap_phase_diff.vhd │ ├── unwrap_phase_diff.vhd │ └── unwrap_phase_diff_tb.vhd ├── unwrap_phase_diff.xpr └── xgui │ └── unwrap_phase_diff_v1_0.tcl ├── vivado.mk ├── windowReal ├── component.xml ├── hdl │ ├── wb_windowReal.vhd │ ├── windowReal.vhd │ ├── windowReal_handComm.vhd │ ├── windowReal_logic.vhd │ └── windowReal_ram.vhd ├── simulation │ ├── .gitignore │ ├── datai.dat │ ├── ghdl │ │ ├── .gitignore │ │ ├── Makefile │ │ └── top_windowReal.gtkw │ ├── isim.sh │ ├── isim.tcl │ ├── ram_storage16.vhd │ ├── readFromFile.vhd │ ├── testC │ │ ├── .gitignore │ │ ├── Makefile │ │ └── main.c │ ├── top_windowReal_tb.vhd │ ├── windowReal.prj │ ├── windowReal.wcfg │ └── windowReal_tb.vhd └── xgui │ └── windowReal_v1_0.tcl ├── xcorr_prn_slow_complex ├── component.xml ├── hdl │ ├── xcorr_prn_slow_complex.vhd │ ├── xcorr_prn_slow_complex_correl.vhd │ ├── xcorr_prn_slow_complex_mux.vhd │ └── xcorr_prn_slow_complex_ram.vhd ├── simuC │ ├── .gitignore │ └── main.c ├── simulation │ ├── .gitignore │ ├── Makefile │ ├── isim │ │ ├── .gitignore │ │ ├── isim.sh │ │ ├── isim.tcl │ │ ├── xcorr_prn_slow_complex.prj │ │ └── xcorr_prn_slow_complex.wcfg │ ├── test.m │ ├── top_xcorr_prn_slow_complex.gtkw │ ├── top_xcorr_prn_slow_complex_tb.vhd │ └── xcorr_prn_slow_complex.m ├── xcorr_prn_slow_complex.xdc └── xgui │ └── xcorr_prn_slow_complex_v1_0.tcl └── xilinx.mk /.gitignore: -------------------------------------------------------------------------------- 1 | *.jou 2 | *.log 3 | simu 4 | *.swp 5 | -------------------------------------------------------------------------------- /MUXcomplexNto1/.gitignore: -------------------------------------------------------------------------------- 1 | /MUXcomplexNto1.cache/ 2 | /MUXcomplexNto1.cache/* 3 | /MUXcomplexNto1.hw/ 4 | /MUXcomplexNto1.hw/* 5 | vivado.* 6 | -------------------------------------------------------------------------------- /MUXcomplexNto1/EdaPlaygroundSimulation/SimulationMUXcomplexNto1_tb_eda_playground.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/fpga_ip/39826ecea776c999e17a28b686e99c4ad5b7d5f6/MUXcomplexNto1/EdaPlaygroundSimulation/SimulationMUXcomplexNto1_tb_eda_playground.jpg -------------------------------------------------------------------------------- /MUXcomplexNto1/hdl/mylib.vhd: -------------------------------------------------------------------------------- 1 | -- package declaration section 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | 5 | package mylib is 6 | type STD_LOGIC_VECTOR_ARRAY_T is array (natural range <>) of std_logic_vector; 7 | type STD_LOGIC_ARRAY_T is array(natural range <>) of std_logic; 8 | type PORT_IN_T is record 9 | data_i_i : std_logic_vector; 10 | data_q_i : std_logic_vector; 11 | data_en_i : std_logic; 12 | data_clk_i : std_logic; 13 | data_eof_i : std_logic; 14 | data_rst_i : std_logic; 15 | end record PORT_IN_T; 16 | type PORT_ARRAY_T is array (natural range <>) of PORT_IN_T; 17 | function log2_int( i : natural) return integer; 18 | end package; 19 | 20 | package body mylib is 21 | function log2_int( i : natural) return integer is 22 | variable temp : integer := i; 23 | variable ret_val : integer := 0; 24 | begin 25 | while temp > 1 loop 26 | ret_val := ret_val + 1; 27 | temp := temp / 2; 28 | end loop; 29 | return ret_val; 30 | end function; 31 | end package body; -------------------------------------------------------------------------------- /MUXrealNto1/.gitignore: -------------------------------------------------------------------------------- 1 | /MUXrealNto1.hw/ 2 | /MUXrealNto1.hw/* 3 | /MUXrealNto1.sim/ 4 | /MUXrealNto1.sim/* 5 | /MUXrealNto1.cache/ 6 | /MUXrealNto1.cache/* 7 | vivado* 8 | -------------------------------------------------------------------------------- /MUXrealNto1/GenerateBoringVivadoIPInputList.m: -------------------------------------------------------------------------------- 1 | % script to generate the boring list of inputs and generate statements for MUXrealNto1top.vhd 2 | clc, clear all 3 | N = 32 4 | 5 | for ii = 0:N - 1 6 | fprintf("\t\tdata_%d_i_i : in STD_LOGIC_VECTOR(DATA_SIZE -1 downto 0) := (others => '0');\n",ii) 7 | fprintf("\t\tdata_%d_en_i : in STD_LOGIC := '0';\n",ii) 8 | fprintf("\t\tdata_%d_clk_i : in STD_LOGIC := '0';\n",ii) 9 | fprintf("\t\tdata_%d_eof_i : in STD_LOGIC := '0';\n",ii) 10 | fprintf("\t\tdata_%d_rst_i : in STD_LOGIC := '0';\n\n",ii) 11 | end 12 | 13 | ii = 0 14 | fprintf ("data_i_s(%d) <= data_%d_i_i;\n",ii,ii); 15 | fprintf ("data_en_s(%d) <= data_%d_en_i;\n",ii,ii); 16 | fprintf ("data_clk_s(%d) <= data_%d_clk_i;\n",ii,ii); 17 | fprintf ("data_eof_s(%d) <= data_%d_eof_i;\n",ii,ii); 18 | fprintf ("data_rst_s(%d) <= data_%d_rst_i;\n",ii,ii); 19 | 20 | for ii = 1: N-1 21 | fprintf("\tinput%d: if INPUTS > %d generate\n",ii,ii) 22 | fprintf ("\t\tdata_i_s(%d) <= data_%d_i_i;\n",ii,ii); 23 | fprintf ("\t\tdata_en_s(%d) <= data_%d_en_i;\n",ii,ii); 24 | fprintf ("\t\tdata_clk_s(%d) <= data_%d_clk_i;\n",ii,ii); 25 | fprintf ("\t\tdata_eof_s(%d) <= data_%d_eof_i;\n",ii,ii); 26 | fprintf ("\t\tdata_rst_s(%d) <= data_%d_rst_i;\n",ii,ii); 27 | fprintf("\tend generate input%d;\n",ii); 28 | end 29 | 30 | 31 | 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /MUXrealNto1/hdl/mylib.vhd: -------------------------------------------------------------------------------- 1 | -- package declaration section 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | 5 | package mylib is 6 | type STD_LOGIC_VECTOR_ARRAY_T is array (natural range <>) of std_logic_vector; 7 | type STD_LOGIC_ARRAY_T is array(natural range <>) of std_logic; 8 | type PORT_IN_T is record 9 | data_i_i : std_logic_vector; 10 | data_q_i : std_logic_vector; 11 | data_en_i : std_logic; 12 | data_clk_i : std_logic; 13 | data_eof_i : std_logic; 14 | data_rst_i : std_logic; 15 | end record PORT_IN_T; 16 | type PORT_ARRAY_T is array (natural range <>) of PORT_IN_T; 17 | function log2_int( i : natural) return integer; 18 | end package; 19 | 20 | package body mylib is 21 | function log2_int( i : natural) return integer is 22 | variable temp : integer := i; 23 | variable ret_val : integer := 0; 24 | begin 25 | while temp > 1 loop 26 | ret_val := ret_val + 1; 27 | temp := temp / 2; 28 | end loop; 29 | return ret_val; 30 | end function; 31 | end package body; -------------------------------------------------------------------------------- /ad9767/ad9767.tcl: -------------------------------------------------------------------------------- 1 | ### DAC 2 | create_bd_port -dir O -from 13 -to 0 dac_dat_o_0 3 | create_bd_port -dir O dac_clk_o_0 4 | create_bd_port -dir O dac_rst_o_0 5 | create_bd_port -dir O dac_sel_o_0 6 | create_bd_port -dir O dac_wrt_o_0 7 | -------------------------------------------------------------------------------- /ad9767/ad9767.xdc: -------------------------------------------------------------------------------- 1 | ### DAC 2 | # data 3 | set_property IOSTANDARD LVCMOS33 [get_ports {dac_dat_o_0[*]}] 4 | set_property SLEW SLOW [get_ports {dac_dat_o_0[*]}] 5 | set_property DRIVE 4 [get_ports {dac_dat_o_0[*]}] 6 | 7 | set_property PACKAGE_PIN M19 [get_ports {dac_dat_o_0[0]}] 8 | set_property PACKAGE_PIN M20 [get_ports {dac_dat_o_0[1]}] 9 | set_property PACKAGE_PIN L19 [get_ports {dac_dat_o_0[2]}] 10 | set_property PACKAGE_PIN L20 [get_ports {dac_dat_o_0[3]}] 11 | set_property PACKAGE_PIN K19 [get_ports {dac_dat_o_0[4]}] 12 | set_property PACKAGE_PIN J19 [get_ports {dac_dat_o_0[5]}] 13 | set_property PACKAGE_PIN J20 [get_ports {dac_dat_o_0[6]}] 14 | set_property PACKAGE_PIN H20 [get_ports {dac_dat_o_0[7]}] 15 | set_property PACKAGE_PIN G19 [get_ports {dac_dat_o_0[8]}] 16 | set_property PACKAGE_PIN G20 [get_ports {dac_dat_o_0[9]}] 17 | set_property PACKAGE_PIN F19 [get_ports {dac_dat_o_0[10]}] 18 | set_property PACKAGE_PIN F20 [get_ports {dac_dat_o_0[11]}] 19 | set_property PACKAGE_PIN D20 [get_ports {dac_dat_o_0[12]}] 20 | set_property PACKAGE_PIN D19 [get_ports {dac_dat_o_0[13]}] 21 | 22 | # control 23 | set_property IOSTANDARD LVCMOS33 [get_ports dac_*_o_0] 24 | set_property SLEW FAST [get_ports dac_*_o_0] 25 | set_property DRIVE 8 [get_ports dac_*_o_0] 26 | 27 | set_property PACKAGE_PIN M17 [get_ports dac_wrt_o_0] 28 | set_property PACKAGE_PIN N16 [get_ports dac_sel_o_0] 29 | set_property PACKAGE_PIN M18 [get_ports dac_clk_o_0] 30 | set_property PACKAGE_PIN N15 [get_ports dac_rst_o_0] 31 | -------------------------------------------------------------------------------- /ad9767/xgui/ad9767_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /add_constComplex/hdl/add_constComplex_rst.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.ALL; 4 | 5 | entity add_constComplex_rst is 6 | port ( 7 | rst_i : in std_logic; 8 | clk_i : in std_logic; 9 | rst_o : out std_logic 10 | ); 11 | end add_constComplex_rst; 12 | 13 | architecture Behavioral of add_constComplex_rst is 14 | signal rst_sync_m1_s, rst_sync_s : std_logic; 15 | begin 16 | -- reset fpga_clk => processing_clk 17 | process(clk_i) begin 18 | if rising_edge(clk_i) then 19 | rst_sync_m1_s <= rst_i; 20 | rst_sync_s <= rst_sync_m1_s; 21 | rst_o <= rst_sync_s; 22 | end if; 23 | end process; 24 | end Behavioral; 25 | -------------------------------------------------------------------------------- /add_constComplex/hdl/add_constComplex_synchronizer_vector.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity add_constComplex_synchronizer_vector is 5 | generic (stages : natural := 3; 6 | DATA : natural := 16); 7 | port (clk_i : in std_logic; 8 | bit_i : in std_logic_vector(DATA-1 downto 0); 9 | bit_o : out std_logic_vector(DATA-1 downto 0) 10 | ); 11 | end entity add_constComplex_synchronizer_vector; 12 | 13 | architecture bhv of add_constComplex_synchronizer_vector is 14 | type data_tab is array (natural range <>) of std_logic_vector(DATA-1 downto 0); 15 | signal flipflops : data_tab(stages -1 downto 0) := 16 | (others => (others => '0')); 17 | attribute ASYNC_REG : string; 18 | attribute ASYNC_REG of flipflops: signal is "true"; 19 | begin 20 | bit_o <= flipflops(stages-1); 21 | 22 | sync_proc: process(clk_i) 23 | begin 24 | if rising_edge(clk_i) then 25 | flipflops <= flipflops(stages-2 downto 0) & bit_i; 26 | end if; 27 | end process; 28 | end bhv; 29 | -------------------------------------------------------------------------------- /add_constComplex/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | top_dut 3 | -------------------------------------------------------------------------------- /add_constComplex/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM ?= ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | 7 | VCD = sim_build/waveform.ghw 8 | 9 | VHDL_SOURCES = $(WPWD)/../hdl/add_constComplex_logic.vhd 10 | 11 | VHDL_SOURCES += $(WPWD)/top_dut.vhd 12 | 13 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 14 | TOPLEVEL=top_dut 15 | # MODULE is the name of the Python test file: 16 | MODULE=top_add_constComplex_tb 17 | 18 | PLUSARGS=--vcdgz=$(WPWD)/sim_build/waveform.vcdgz --wave=$(WPWD)/$(VCD) 19 | 20 | include $(shell cocotb-config --makefiles)/Makefile.sim 21 | 22 | view: 23 | gtkwave -a top_add_constComplex.gtkw $(VCD) 24 | -------------------------------------------------------------------------------- /add_constComplex/simulation_signed_ext/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | -------------------------------------------------------------------------------- /add_constReal/add_constReal.xdc: -------------------------------------------------------------------------------- 1 | #set_false_path -from [get_pins {wb_add_constReal_inst/offset_s_reg[*]/C}] -to [get_pins {add_constRealLogic/add_val_s_reg[*]/D}] 2 | set_false_path -from [get_pins -hier *offset_s*/C] 3 | -------------------------------------------------------------------------------- /add_constReal/add_constReal_ooc.xdc: -------------------------------------------------------------------------------- 1 | set_false_path -from [get_pins {wb_add_constReal_inst/offset_s_reg[*]/C}] -to [get_pins {add_constRealLogic/add_val_s_reg[*]/D}] 2 | -------------------------------------------------------------------------------- /add_constReal/hdl/add_constReal_rst.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.ALL; 4 | 5 | entity add_constReal_rst is 6 | port ( 7 | rst_i : in std_logic; 8 | clk_i : in std_logic; 9 | rst_o : out std_logic 10 | ); 11 | end add_constReal_rst; 12 | 13 | architecture Behavioral of add_constReal_rst is 14 | signal rst_sync_m1_s, rst_sync_s : std_logic; 15 | begin 16 | -- reset fpga_clk => processing_clk 17 | process(clk_i) begin 18 | if rising_edge(clk_i) then 19 | rst_sync_m1_s <= rst_i; 20 | rst_sync_s <= rst_sync_m1_s; 21 | rst_o <= rst_sync_s; 22 | end if; 23 | end process; 24 | end Behavioral; 25 | -------------------------------------------------------------------------------- /add_constReal/hdl/add_constReal_synchronizer_vector.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity add_constReal_synchronizer_vector is 5 | generic (stages : natural := 3; 6 | DATA : natural := 16); 7 | port (clk_i : in std_logic; 8 | bit_i : in std_logic_vector(DATA-1 downto 0); 9 | bit_o : out std_logic_vector(DATA-1 downto 0) 10 | ); 11 | end entity add_constReal_synchronizer_vector; 12 | 13 | architecture bhv of add_constReal_synchronizer_vector is 14 | type data_tab is array (natural range <>) of std_logic_vector(DATA-1 downto 0); 15 | signal flipflops : data_tab(stages -1 downto 0) := 16 | (others => (others => '0')); 17 | attribute ASYNC_REG : string; 18 | attribute ASYNC_REG of flipflops: signal is "true"; 19 | begin 20 | bit_o <= flipflops(stages-1); 21 | 22 | sync_proc: process(clk_i) 23 | begin 24 | if rising_edge(clk_i) then 25 | flipflops <= flipflops(stages-2 downto 0) & bit_i; 26 | end if; 27 | end process; 28 | end bhv; 29 | -------------------------------------------------------------------------------- /add_constReal/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | top_dut 2 | -------------------------------------------------------------------------------- /add_constReal/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM ?= ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | 7 | VCD = sim_build/waveform.ghw 8 | 9 | VHDL_SOURCES = $(WPWD)/../hdl/add_constReal_logic.vhd 10 | 11 | VHDL_SOURCES += $(WPWD)/top_dut.vhd 12 | 13 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 14 | TOPLEVEL=top_dut 15 | # MODULE is the name of the Python test file: 16 | MODULE=top_add_constReal_tb 17 | 18 | PLUSARGS=--vcdgz=$(WPWD)/sim_build/waveform.vcdgz --wave=$(WPWD)/$(VCD) 19 | 20 | include $(shell cocotb-config --makefiles)/Makefile.sim 21 | 22 | view: 23 | gtkwave -a top_add_constReal.gtkw $(VCD) 24 | -------------------------------------------------------------------------------- /axiStreamToComplex/hdl/axiStreamToComplex.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2016/09/22 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | use IEEE.numeric_std.all; 9 | 10 | Entity axiStreamToComplex is 11 | generic ( 12 | DATA_SIZE : natural := 32 13 | ); 14 | port ( 15 | -- output data 16 | data_i_o : out std_logic_vector(DATA_SIZE-1 downto 0); 17 | data_q_o : out std_logic_vector(DATA_SIZE-1 downto 0); 18 | data_en_o: out std_logic; 19 | data_clk_o: out std_logic; 20 | data_rst_o: out std_logic; 21 | -- input data 22 | s00_axis_aclk : in std_logic; 23 | s00_axis_reset : in std_logic; 24 | s00_axis_tdata : in std_logic_vector((2*DATA_SIZE)-1 downto 0); 25 | s00_axis_tready : out std_logic; 26 | s00_axis_tvalid : in std_logic 27 | ); 28 | end entity; 29 | 30 | --------------------------------------------------------------------------- 31 | Architecture axiStreamToComplex_1 of axiStreamToComplex is 32 | begin 33 | data_q_o <= s00_axis_tdata((2*DATA_SIZE)-1 downto DATA_SIZE); 34 | data_i_o <= s00_axis_tdata(DATA_SIZE-1 downto 0); 35 | data_en_o <= s00_axis_tvalid; 36 | data_clk_o <= s00_axis_aclk; 37 | s00_axis_tready <= '1'; 38 | data_rst_o <= s00_axis_reset; 39 | end architecture axiStreamToComplex_1; 40 | 41 | -------------------------------------------------------------------------------- /axiStreamToComplex/xgui/axiStreamToComplex_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | set DATA_SIZE [ipgui::add_param $IPINST -name "DATA_SIZE" -parent ${Page_0}] 7 | set_property tooltip {Size of Output data bus.} ${DATA_SIZE} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 13 | # Procedure called to update DATA_SIZE when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 17 | # Procedure called to validate DATA_SIZE 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.DATA_SIZE { MODELPARAM_VALUE.DATA_SIZE PARAM_VALUE.DATA_SIZE } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | set_property value [get_property value ${PARAM_VALUE.DATA_SIZE}] ${MODELPARAM_VALUE.DATA_SIZE} 25 | } 26 | 27 | -------------------------------------------------------------------------------- /axiStreamToReal/hdl/axiStreamToReal.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2016/10/27 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | use IEEE.numeric_std.all; 9 | 10 | Entity axiStreamToReal is 11 | generic ( 12 | DATA_SIZE : natural := 32 13 | ); 14 | port ( 15 | s00_axis_reset : in std_logic; 16 | -- output data 17 | data_o : out std_logic_vector(DATA_SIZE-1 downto 0); 18 | data_en_o: out std_logic; 19 | data_clk_o: out std_logic; 20 | data_rst_o: out std_logic; 21 | -- input data 22 | s00_axis_aclk : in std_logic; 23 | s00_axis_tdata : in std_logic_vector(DATA_SIZE-1 downto 0); 24 | s00_axis_tready : out std_logic; 25 | s00_axis_tvalid : in std_logic 26 | ); 27 | end entity; 28 | 29 | --------------------------------------------------------------------------- 30 | Architecture axiStreamToReal_1 of axiStreamToReal is 31 | begin 32 | data_o <= s00_axis_tdata; 33 | data_en_o <= s00_axis_tvalid; 34 | data_clk_o <= s00_axis_aclk; 35 | s00_axis_tready <= '1'; 36 | data_rst_o <= s00_axis_reset; 37 | end architecture axiStreamToReal_1; 38 | 39 | -------------------------------------------------------------------------------- /axiStreamToReal/xgui/axiStreamToReal_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "DATA_SIZE" -parent ${Page_0} 7 | 8 | 9 | } 10 | 11 | proc update_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 12 | # Procedure called to update DATA_SIZE when any of the dependent parameters in the arguments change 13 | } 14 | 15 | proc validate_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 16 | # Procedure called to validate DATA_SIZE 17 | return true 18 | } 19 | 20 | 21 | proc update_MODELPARAM_VALUE.DATA_SIZE { MODELPARAM_VALUE.DATA_SIZE PARAM_VALUE.DATA_SIZE } { 22 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 23 | set_property value [get_property value ${PARAM_VALUE.DATA_SIZE}] ${MODELPARAM_VALUE.DATA_SIZE} 24 | } 25 | 26 | -------------------------------------------------------------------------------- /axi_deltaSigma/axi_deltaSigma_constr.xdc: -------------------------------------------------------------------------------- 1 | set ctrl_clk [get_clocks -of_objects [get_ports s_axi_aclk]] 2 | set data_clk [get_clocks -of_objects [get_ports data_clk_i]] 3 | 4 | set_property ASYNC_REG TRUE \ 5 | [get_cells -hier cdc_sync_stage1_*_reg] \ 6 | [get_cells -hier cdc_sync_stage2_*_reg] 7 | 8 | set_false_path \ 9 | -from [get_cells -hier cdc_sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ 10 | -to [get_cells -hier cdc_sync_stage1_*_reg -filter {IS_SEQUENTIAL}] 11 | 12 | # Reset 13 | set_false_path \ 14 | -to [get_pins -hier data_reset_vec_reg*/PRE] 15 | -------------------------------------------------------------------------------- /axi_deltaSigma/hdl/deltaSigma.v: -------------------------------------------------------------------------------- 1 | /* 2 | * (c) Copyright: OscillatorIMP Digital 3 | * Author : Gwenhael Goavec-Merou 4 | * Creation date : 2019/02/01 5 | */ 6 | 7 | module deltaSigma #( 8 | parameter NB_BIT = 32 9 | ) ( 10 | input clk_i, 11 | input rst_i, 12 | input trig_i, 13 | input [NB_BIT-1:0] data_i, 14 | output dac_o 15 | ); 16 | 17 | localparam BIT_INT = NB_BIT+2; 18 | 19 | wire [BIT_INT-1:0] data_in_s = {2'b0, data_i}; 20 | 21 | wire [BIT_INT-1:0] deltaB; 22 | wire [BIT_INT-1:0] deltaAdder = $signed(data_in_s) + $signed(deltaB); 23 | 24 | reg [BIT_INT-1:0] sigmaLatch; 25 | 26 | wire [BIT_INT-1:0] sigmaAdder = $signed(deltaAdder) + $signed(sigmaLatch); 27 | 28 | always @(posedge clk_i) begin 29 | if (rst_i) 30 | sigmaLatch <= 0; 31 | else if (trig_i) 32 | sigmaLatch <= sigmaAdder; 33 | else 34 | sigmaLatch <= sigmaLatch; 35 | end 36 | 37 | wire out_bit_s = sigmaLatch[BIT_INT-1]; 38 | 39 | assign deltaB = {out_bit_s, out_bit_s, {NB_BIT{1'b0}}}; 40 | 41 | 42 | reg dac_out_s; 43 | 44 | always @(posedge clk_i) begin 45 | if (rst_i) 46 | dac_out_s <= 1'b0; 47 | else if (trig_i) 48 | dac_out_s <= out_bit_s; 49 | else 50 | dac_out_s <= dac_out_s; 51 | end 52 | 53 | assign dac_o = dac_out_s; 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /axi_deltaSigma/simu_deltaSigmaV/Makefile: -------------------------------------------------------------------------------- 1 | WAVE=gtkwave 2 | VCC=iverilog 3 | VEXEC=vvp 4 | SIMU_DIR=simu 5 | PROJECT=top_cs4344 6 | TESTBENCH_FILE=$(PROJECT)_tb.v 7 | GHDL_FLAGS= 8 | OBJS=../hdl/deltaSigma.v 9 | 10 | all: $(PROJECT) 11 | 12 | $(PROJECT): $(OBJS) $(TESTBENCH_FILE) 13 | echo "$(PROJECT)" >> time.txt 14 | date >> time.txt 15 | mkdir -p $(SIMU_DIR) 16 | $(VCC) -o $(SIMU_DIR)/$@ $^ 17 | $(VEXEC) $(SIMU_DIR)/$@ -lvcd 18 | echo "end $(PROJECT)" >> time.txt 19 | date >> time.txt 20 | 21 | ghdl-view : $(SIMU_DIR)/$(PROJECT)_tb.vcd 22 | $(WAVE) $< -a $(PROJECT).gtkw 23 | 24 | clean: 25 | -rm -rf $(SIMU_DIR) 26 | -rm time.txt 27 | -------------------------------------------------------------------------------- /axi_deltaSigma/simu_deltaSigmaV/top_cs4344.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.87 (w)1999-2017 BSI 3 | [*] Fri Feb 1 17:23:51 2019 4 | [*] 5 | [dumpfile] "/home/gwe/projets/pipistrello/libs/sound_gen/simu_deltaSigmaV/simu/top_cs4344_tb.vcd" 6 | [dumpfile_mtime] "Fri Feb 1 17:23:45 2019" 7 | [dumpfile_size] 616903 8 | [savefile] "/home/gwe/projets/pipistrello/libs/sound_gen/simu_deltaSigmaV/top_cs4344.gtkw" 9 | [timestart] 5480000 10 | [size] 1364 746 11 | [pos] -1 -1 12 | *-21.136065 187000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] top_cs4344_tb. 14 | [sst_width] 210 15 | [signals_width] 190 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 304 18 | @200 19 | -top 20 | @28 21 | top_cs4344_tb.clk 22 | top_cs4344_tb.rst_s 23 | top_cs4344_tb.data_en_s 24 | @24 25 | top_cs4344_tb.cpt_s[15:0] 26 | @22 27 | top_cs4344_tb.data_s[7:0] 28 | @28 29 | top_cs4344_tb.dac_s 30 | @200 31 | -deltaSigma 32 | @22 33 | top_cs4344_tb.dS_inst.data_in_s[9:0] 34 | top_cs4344_tb.dS_inst.deltaB[9:0] 35 | top_cs4344_tb.dS_inst.deltaAdder[9:0] 36 | @29 37 | top_cs4344_tb.dS_inst.dac_out_s 38 | [pattern_trace] 1 39 | [pattern_trace] 0 40 | -------------------------------------------------------------------------------- /axi_deltaSigma/simu_dma_fifo/.gitignore: -------------------------------------------------------------------------------- 1 | result.txt 2 | fir16 3 | *.log 4 | *.xmsgs 5 | *.cmd 6 | *.wdd 7 | *.wcfg 8 | isim 9 | *.wdb 10 | simu 11 | -------------------------------------------------------------------------------- /axi_deltaSigma/simu_dma_fifo/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_dma_fifo 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../hdl/dma_fifo.vhd 10 | 11 | SIMDIR=simu 12 | 13 | VIEW_CMD = gtkwave 14 | 15 | all : run 16 | 17 | # Run target 18 | run:$(SIMDIR)/$(SIMTOP).ghw 19 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 20 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 21 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 22 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 23 | 24 | # Targets to analyze libraries 25 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 26 | mkdir -p $(SIMDIR) 27 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 28 | 29 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 30 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 31 | 32 | clean: 33 | $(GHDL) --clean --workdir=simu 34 | -rm -rf simu 35 | force: 36 | -------------------------------------------------------------------------------- /axi_to_dac/axi_to_dac.xdc: -------------------------------------------------------------------------------- 1 | set_property ASYNC_REG TRUE \ 2 | [get_cells -hier flipflops_vect*_reg[0][*]] \ 3 | [get_cells -hier flipflops_vect*_reg[1][*]] 4 | set_false_path \ 5 | -from [get_cells -hier sync_vect_stage0_*_reg[*] -filter {IS_SEQUENTIAL}] \ 6 | -to [get_cells -hier flipflops_vect*_reg[0][*] -filter {IS_SEQUENTIAL}] 7 | -------------------------------------------------------------------------------- /axi_to_dac/hdl/axi_to_dac_sync_vect.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2015/04/08 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity axi_to_dac_sync_vect is 10 | generic (stages : natural := 3; 11 | DATA : natural := 16); 12 | port ( 13 | ref_clk_i : in std_logic; 14 | clk_i : in std_logic; 15 | bit_i : in std_logic_vector(DATA-1 downto 0); 16 | bit_o : out std_logic_vector(DATA-1 downto 0) 17 | ); 18 | end entity axi_to_dac_sync_vect; 19 | 20 | architecture bhv of axi_to_dac_sync_vect is 21 | signal sync_vect_stage0_s: std_logic_vector(DATA-1 downto 0); 22 | type data_tab is array (natural range <>) of std_logic_vector(DATA-1 downto 0); 23 | signal flipflops_vect : data_tab(stages -1 downto 0) := (others => (others => '0')); 24 | attribute ASYNC_REG : string; 25 | attribute ASYNC_REG of flipflops_vect: signal is "true"; 26 | begin 27 | ref_proc: process(ref_clk_i) begin 28 | if rising_edge(ref_clk_i) then 29 | sync_vect_stage0_s <= bit_i; 30 | end if; 31 | end process; 32 | 33 | sync_proc: process(clk_i) 34 | begin 35 | if rising_edge(clk_i) then 36 | flipflops_vect(0) <= sync_vect_stage0_s; 37 | flipflops_vect(stages-1 downto 1) 38 | <= flipflops_vect(stages-2 downto 0); 39 | end if; 40 | end process; 41 | bit_o <= flipflops_vect(stages-1); 42 | end bhv; 43 | -------------------------------------------------------------------------------- /boards.def: -------------------------------------------------------------------------------- 1 | # Fix some var according to 2 | # FPGA model and board 3 | ifeq ($(BOARD_NAME), de0nanosoc) 4 | OUT_BIN = rbf 5 | USE_QSYS = y 6 | FAMILY = "Cyclone V" 7 | PART = 5CSEMA4U23C6 8 | BD_PRESET = $(OSCIMP_DIGITAL_IP)/preset/de0nanoSoc_qsys_preset.tcl 9 | PRJ_PRESET = $(OSCIMP_DIGITAL_IP)/preset/de0nanoSoc_prj_preset.tcl 10 | TOOLS = quartus 11 | endif 12 | ifeq ($(BOARD_NAME), redpitaya) 13 | OUT_BIN = bit.bin 14 | USE_BD = y 15 | PART = "xc7z010clg400-1" 16 | PRJ_PRESET = "" 17 | BD_PRESET = "${OSCIMP_DIGITAL_IP}/preset/redpitaya_preset.xml" 18 | TOOLS = vivado 19 | endif 20 | ifeq ($(BOARD_NAME), redpitaya16) 21 | OUT_BIN = bit.bin 22 | USE_BD = y 23 | PART = "xc7z020clg400-1" 24 | PRJ_PRESET = "" 25 | BD_PRESET = "${OSCIMP_DIGITAL_IP}/preset/redpitaya16_preset.xml" 26 | TOOLS = vivado 27 | endif 28 | ifeq ($(BOARD_NAME), redpitaya12) 29 | OUT_BIN = bit.bin 30 | USE_BD = y 31 | PART = "xc7z020clg400-3" 32 | PRJ_PRESET = "" 33 | BD_PRESET = "${OSCIMP_DIGITAL_IP}/preset/redpitaya12_preset.xml" 34 | TOOLS = vivado 35 | endif 36 | ifeq ($(BOARD_NAME), zedboard) 37 | OUT_BIN = bit.bin 38 | USE_BD = y 39 | PART = "xc7z020clg484-1" 40 | PRJ_PRESET = "" 41 | BD_PRESET = "ZedBoard" 42 | TOOLS = vivado 43 | endif 44 | 45 | ifeq ($(BOARD_NAME),) 46 | all: fail_rule 47 | fail_rule: 48 | @echo $(BOARD_NAME) 49 | @echo "BOARD_NAME not known or missing" 50 | @/bin/false 51 | endif 52 | -------------------------------------------------------------------------------- /cacode/hdl/cacode_g1_gen.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.all; 4 | 5 | entity cacode_g1_gen is 6 | port ( 7 | clk : in std_logic; 8 | reset : in std_logic; 9 | tick_i : in std_logic; 10 | -- start 11 | prn_o : out std_logic_vector(9 downto 0); 12 | bit_o : out std_logic 13 | ); 14 | end entity; 15 | 16 | architecture rtl of cacode_g1_gen is 17 | signal lfsr_s, lfsr_next_s : std_logic_vector(9 downto 0) := (others => '1'); 18 | signal xor9_2 : std_logic; 19 | begin 20 | 21 | prn_o <= lfsr_s; 22 | 23 | xor9_2 <= lfsr_s(9) xor lfsr_s(2); 24 | lfsr_next_s <= lfsr_s(8 downto 0) & xor9_2; 25 | 26 | process(clk) 27 | begin 28 | if rising_edge(clk) then 29 | if reset = '1' then 30 | lfsr_s <= (others => '1'); 31 | elsif (tick_i = '1') then 32 | lfsr_s <= lfsr_next_s; 33 | else 34 | lfsr_s <= lfsr_s; 35 | end if; 36 | end if; 37 | end process; 38 | bit_o <= lfsr_s(9); 39 | 40 | end architecture rtl; 41 | -------------------------------------------------------------------------------- /cacode/hdl/cacode_g2_gen.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.all; 4 | 5 | entity cacode_g2_gen is 6 | port ( 7 | clk : in std_logic; 8 | reset : in std_logic; 9 | tick_i : in std_logic; 10 | -- start 11 | prn_o : out std_logic_vector(9 downto 0); 12 | bit_o : out std_logic 13 | ); 14 | end entity; 15 | 16 | architecture rtl of cacode_g2_gen is 17 | signal lfsr_s, lfsr_next_s : std_logic_vector(9 downto 0) := (others => '1'); 18 | signal xor_full : std_logic; 19 | begin 20 | 21 | prn_o <= lfsr_s; 22 | 23 | xor_full <= lfsr_s(9) xor lfsr_s(8) xor lfsr_s(7) 24 | xor lfsr_s(5) xor lfsr_s(2) xor lfsr_s(1); 25 | lfsr_next_s <= lfsr_s(8 downto 0) & xor_full; 26 | 27 | process(clk) 28 | begin 29 | if rising_edge(clk) then 30 | if reset = '1' then 31 | lfsr_s <= (others => '1'); 32 | elsif (tick_i = '1') then 33 | lfsr_s <= lfsr_next_s; 34 | else 35 | lfsr_s <= lfsr_s; 36 | end if; 37 | end if; 38 | end process; 39 | bit_o <= lfsr_s(9); 40 | 41 | end architecture rtl; 42 | -------------------------------------------------------------------------------- /cacode/simuC/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | #define SHIFT_AND_MASK(__val, __shift) ((0x01) & (__val >> __shift)) 6 | 7 | int main(void) 8 | { 9 | 10 | uint32_t start = 4005; 11 | uint32_t a = start; 12 | int i; 13 | uint16_t g1 = 0xffff, g2 = 0xffff; 14 | uint8_t xor; 15 | uint8_t s1; 16 | 17 | for(i = 0; i < start; i++) { 18 | s1 = (0x01 & (g1 >> 9)); 19 | xor = (0x01 & (g2 >> 1)) ^ 20 | (0x01 & (g2 >> 5)); 21 | xor = xor ^ s1; 22 | printf("%d\n", xor&0x01); 23 | 24 | /* g1 */ 25 | xor = (0x01 & (g1 >> 9)) ^ (0x01 & (g1 >> 2)); 26 | g1 = (g1 << 1) | xor; 27 | s1 = (0x01 & (g1 >> 9)); 28 | //printf("%u ", 0x3ff & g1); 29 | 30 | /* g2 */ 31 | xor = (0x01 & (g2 >> 9)) ^ 32 | (0x01 & (g2 >> 8)) ^ 33 | (0x01 & (g2 >> 7)) ^ 34 | (0x01 & (g2 >> 5)) ^ 35 | (0x01 & (g2 >> 2)) ^ 36 | (0x01 & (g2 >> 1)); 37 | g2 = (g2 << 1) | xor; 38 | //printf("%u ", 0x3ff&g2); 39 | 40 | 41 | 42 | } 43 | } 44 | -------------------------------------------------------------------------------- /cacode/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | -------------------------------------------------------------------------------- /cacode/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_cacode 2 | SIMTOP =$(PROJECT)_tb 3 | TESTBENCH_FILE=$(SIMTOP).vhd 4 | 5 | #GHDL=/home/gwe/apps/ghdl/bin/ghdl 6 | GHDL=ghdl 7 | GHDLFLAGS=--workdir=simu --work=work 8 | GHDLRUNFLAGS=--assert-level=error 9 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 10 | 11 | FILES=../hdl/cacode_g1_gen.vhd ../hdl/cacode_g2_gen.vhd ../hdl/cacode.vhd 12 | 13 | SIMDIR=simu 14 | 15 | VIEW_CMD = gtkwave 16 | 17 | all : run 18 | 19 | # Run target 20 | run:$(SIMDIR)/$(SIMTOP).ghw 21 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 22 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 23 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 24 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 25 | 26 | # Targets to analyze libraries 27 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 28 | mkdir -p $(SIMDIR) 29 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 30 | 31 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 32 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 33 | 34 | clean: 35 | $(GHDL) --clean --workdir=simu 36 | -rm -rf simu 37 | -rm -f result.txt 38 | force: 39 | -------------------------------------------------------------------------------- /cacode/simulation/test.m: -------------------------------------------------------------------------------- 1 | pkg load signal 2 | close all; 3 | %load result.txt 4 | res = load("../simuC/toto"); 5 | %res = load("result.txt"); 6 | 7 | %for k=1:32 8 | %for k=10:20 9 | %for k=21:32 10 | %x = cacode(k); 11 | %plot(xcorr(x-mean(x), res(:,k)-mean(res(:,k)))) 12 | %title(num2str(k)) 13 | %figure 14 | %end 15 | 16 | res = res(1:1023); 17 | res = res'; 18 | x = cacode(1); 19 | %plot(xcorr(x-mean(x), res(:,1)-mean(res(:,1)))) 20 | %plot(xcorr(x, res-mean(res))) 21 | plot(xcorr(x-mean(x), x-mean(x))) 22 | -------------------------------------------------------------------------------- /cacode/xgui/cacode_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | set PERIOD_LEN [ipgui::add_param $IPINST -name "PERIOD_LEN" -parent ${Page_0}] 7 | set_property tooltip {Period Length of bit.} ${PERIOD_LEN} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.PERIOD_LEN { PARAM_VALUE.PERIOD_LEN } { 13 | # Procedure called to update PERIOD_LEN when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.PERIOD_LEN { PARAM_VALUE.PERIOD_LEN } { 17 | # Procedure called to validate PERIOD_LEN 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.PERIOD_LEN { MODELPARAM_VALUE.PERIOD_LEN PARAM_VALUE.PERIOD_LEN } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | set_property value [get_property value ${PARAM_VALUE.PERIOD_LEN}] ${MODELPARAM_VALUE.PERIOD_LEN} 25 | } 26 | 27 | -------------------------------------------------------------------------------- /check_valid_burst/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_cvb 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../hdl/cvb_cpt_en.vhd ../hdl/cvb_gen_new_flow.vhd 10 | FILES+=../hdl/cvb_check_mean.vhd ../hdl/cvb_ram.vhd ../hdl/cvb_dual_ram.vhd 11 | FILES+=../hdl/cvb_logic.vhd 12 | FILES+=readComplexFromFile.vhd 13 | 14 | SIMDIR=simu 15 | 16 | VIEW_CMD = gtkwave 17 | 18 | all : run 19 | 20 | # Run target 21 | run:$(SIMDIR)/$(SIMTOP).ghw 22 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 23 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 24 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 25 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 26 | 27 | # Targets to analyze libraries 28 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 29 | mkdir -p $(SIMDIR) 30 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 31 | 32 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 33 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 34 | 35 | clean: 36 | $(GHDL) --clean --workdir=simu 37 | -rm -rf simu result.txt 38 | force: 39 | -------------------------------------------------------------------------------- /check_valid_burst/simulation/genOracle/.exrc: -------------------------------------------------------------------------------- 1 | if &cp | set nocp | endif 2 | let s:cpo_save=&cpo 3 | set cpo&vim 4 | inoremap  5 | inoremap pumvisible() ? "\" : "\" 6 | inoremap pumvisible() ? "\" : "\" 7 | inoremap pumvisible() ? "\" : "\" 8 | map Q gq 9 | nnoremap \d :YcmShowDetailedDiagnostic 10 | vmap gx NetrwBrowseXVis 11 | nmap gx NetrwBrowseX 12 | vnoremap NetrwBrowseXVis :call netrw#BrowseXVis() 13 | nnoremap NetrwBrowseX :call netrw#BrowseX(expand((exists("g:netrw_gx")? g:netrw_gx : '')),netrw#CheckIfRemote()) 14 | inoremap  pumvisible() ? "\" : "\ " 15 | let &cpo=s:cpo_save 16 | unlet s:cpo_save 17 | set background=dark 18 | set backspace=2 19 | set completefunc=youcompleteme#Complete 20 | set completeopt=preview,menuone 21 | set cpoptions=aAceFsB 22 | set fileencodings=ucs-bom,utf-8,default 23 | set hlsearch 24 | set nomodeline 25 | set omnifunc=youcompleteme#OmniComplete 26 | set pyxversion=2 27 | set ruler 28 | set shiftwidth=4 29 | set smartindent 30 | set suffixes=.bak,~,.o,.h,.info,.swp,.obj,.info,.aux,.log,.dvi,.bbl,.out,.o,.lo 31 | set tabstop=4 32 | set textwidth=80 33 | set updatetime=2000 34 | set viminfo='20,\"500 35 | " vim: set ft=vim : 36 | -------------------------------------------------------------------------------- /check_valid_burst/simulation/genOracle/Makefile: -------------------------------------------------------------------------------- 1 | CFLAGS+=-g -W -Wall 2 | LDFLAGS=-lm 3 | EXEC_NAME=genOracle 4 | OBJS=main.o 5 | 6 | all: $(EXEC_NAME) 7 | 8 | $(EXEC_NAME): $(OBJS) 9 | $(CC) -o $@ $^ $(LDFLAGS) 10 | 11 | %.o: %.c 12 | $(CC) $(CFLAGS) -o $@ -c $< 13 | 14 | clean: 15 | rm -rf $(OBJS) 16 | rm -f $(EXEC_NAME) 17 | rm -f *.c~ *.h~ Makefile~ 18 | rm -f *.dat 19 | 20 | .PHONY: clean 21 | 22 | 23 | -------------------------------------------------------------------------------- /check_valid_burst/simulation/genOracle/mergeData.sh: -------------------------------------------------------------------------------- 1 | cat data_good1_cos.dat > input_oracle_cos.dat 2 | cat data_good2_cos.dat >> input_oracle_cos.dat 3 | cat data_bad3_cos.dat >> input_oracle_cos.dat 4 | cat data_good4_cos.dat >> input_oracle_cos.dat 5 | cat ../real_data.dat | awk '{print $2}' >> input_oracle_cos.dat 6 | 7 | cat data_good1_sin.dat > input_oracle_sin.dat 8 | cat data_good2_sin.dat >> input_oracle_sin.dat 9 | cat data_bad3_sin.dat >> input_oracle_sin.dat 10 | cat data_good4_sin.dat >> input_oracle_sin.dat 11 | cat ../real_data.dat | awk '{print $1}' >> input_oracle_sin.dat 12 | 13 | cat oracle_data_good1.dat > oracle_data.dat 14 | echo "eof" >> oracle_data.dat 15 | cat oracle_data_good2.dat >> oracle_data.dat 16 | echo "eof" >> oracle_data.dat 17 | cat oracle_data_bad3.dat >> oracle_data.dat 18 | echo "eof" >> oracle_data.dat 19 | cat oracle_data_good4.dat >> oracle_data.dat 20 | echo "eof" >> oracle_data.dat 21 | cat ../real_data.dat >> oracle_data.dat 22 | echo "eof" >> oracle_data.dat 23 | -------------------------------------------------------------------------------- /clkChangeComplex/xgui/clkChangeComplex_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | set DATA_SIZE [ipgui::add_param $IPINST -name "DATA_SIZE" -parent ${Page_0}] 7 | set_property tooltip {Size of input data bus.} ${DATA_SIZE} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 13 | # Procedure called to update DATA_SIZE when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 17 | # Procedure called to validate DATA_SIZE 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.DATA_SIZE { MODELPARAM_VALUE.DATA_SIZE PARAM_VALUE.DATA_SIZE } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | set_property value [get_property value ${PARAM_VALUE.DATA_SIZE}] ${MODELPARAM_VALUE.DATA_SIZE} 25 | } 26 | 27 | -------------------------------------------------------------------------------- /clock_prescaler/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | -------------------------------------------------------------------------------- /clock_prescaler/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_clock_prescaler 2 | SIMTOP =$(PROJECT)_tb 3 | TESTBENCH_FILE=$(SIMTOP).vhd 4 | 5 | #GHDL=/home/gwe/apps/ghdl/bin/ghdl 6 | GHDL=ghdl 7 | GHDLFLAGS=--workdir=simu --work=work 8 | GHDLRUNFLAGS=--assert-level=error 9 | GHDL_SIMU_FLAGS = -fexplicit --ieee=synopsys --warn-no-vital-generic --warn-default-binding 10 | 11 | FILES=../hdl/clock_prescaler.vhd 12 | 13 | SIMDIR=simu 14 | 15 | VIEW_CMD = gtkwave 16 | 17 | all : run 18 | 19 | # Run target 20 | run:$(SIMDIR)/$(SIMTOP).ghw 21 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 22 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 23 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 24 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 25 | 26 | # Targets to analyze libraries 27 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 28 | mkdir -p $(SIMDIR) 29 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 30 | 31 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 32 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 33 | 34 | clean: 35 | $(GHDL) --clean --workdir=simu 36 | -rm -rf simu 37 | -rm -f result.txt 38 | force: 39 | -------------------------------------------------------------------------------- /clock_prescaler/simulation/result.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/fpga_ip/39826ecea776c999e17a28b686e99c4ad5b7d5f6/clock_prescaler/simulation/result.txt -------------------------------------------------------------------------------- /clock_prescaler/xgui/clock_prescaler_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "DIVISOR" -parent ${Page_0} 7 | 8 | 9 | } 10 | 11 | proc update_PARAM_VALUE.DIVISOR { PARAM_VALUE.DIVISOR } { 12 | # Procedure called to update DIVISOR when any of the dependent parameters in the arguments change 13 | } 14 | 15 | proc validate_PARAM_VALUE.DIVISOR { PARAM_VALUE.DIVISOR } { 16 | # Procedure called to validate DIVISOR 17 | return true 18 | } 19 | 20 | 21 | proc update_MODELPARAM_VALUE.DIVISOR { MODELPARAM_VALUE.DIVISOR PARAM_VALUE.DIVISOR } { 22 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 23 | set_property value [get_property value ${PARAM_VALUE.DIVISOR}] ${MODELPARAM_VALUE.DIVISOR} 24 | } 25 | 26 | -------------------------------------------------------------------------------- /complexToAxiStream/hdl/complexToAxiStream.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.all; 4 | 5 | Entity complexToAxiStream is 6 | generic ( 7 | DATA_SIZE : natural := 32 8 | ); 9 | port ( 10 | -- input data 11 | data_i_i : in std_logic_vector(DATA_SIZE-1 downto 0); 12 | data_q_i : in std_logic_vector(DATA_SIZE-1 downto 0); 13 | data_en_i: in std_logic; 14 | data_clk_i: in std_logic; 15 | data_rst_i: in std_logic; 16 | -- output data 17 | m00_axis_aclk : in std_logic; 18 | m00_axis_tdata : out std_logic_vector((2*DATA_SIZE)-1 downto 0); 19 | m00_axis_tready : in std_logic; 20 | m00_axis_tvalid : out std_logic 21 | ); 22 | end entity; 23 | 24 | --------------------------------------------------------------------------- 25 | Architecture complexToAxiStream_1 of complexToAxiStream is 26 | begin 27 | m00_axis_tdata <= data_q_i & data_i_i; 28 | m00_axis_tvalid <= data_en_i; 29 | end architecture complexToAxiStream_1; 30 | 31 | -------------------------------------------------------------------------------- /complexToAxiStream/xgui/complexToAxiStream_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | set DATA_SIZE [ipgui::add_param $IPINST -name "DATA_SIZE" -parent ${Page_0}] 7 | set_property tooltip {Size of input data bus.} ${DATA_SIZE} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 13 | # Procedure called to update DATA_SIZE when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 17 | # Procedure called to validate DATA_SIZE 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.DATA_SIZE { MODELPARAM_VALUE.DATA_SIZE PARAM_VALUE.DATA_SIZE } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | set_property value [get_property value ${PARAM_VALUE.DATA_SIZE}] ${MODELPARAM_VALUE.DATA_SIZE} 25 | } 26 | 27 | -------------------------------------------------------------------------------- /const_complex/hdl/const_complex.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity const_complex is 6 | generic( 7 | DATA_SIZE : natural := 16; 8 | INT_REAL_PART_OUT_VALUE : integer := 0; 9 | INT_IMAG_PART_OUT_VALUE : integer := 0 10 | ); 11 | port( 12 | --Syscon signals 13 | ref_clk_i : in std_logic; 14 | ref_rst_i : in std_logic; 15 | data_i_o : out std_logic_vector(DATA_SIZE - 1 downto 0); 16 | data_q_o : out std_logic_vector(DATA_SIZE - 1 downto 0); 17 | data_en_o : out std_logic; 18 | data_clk_o : out std_logic; 19 | data_rst_o : out std_logic 20 | ); 21 | end entity const_complex; 22 | architecture bhv of const_complex is 23 | begin 24 | data_i_o <= std_logic_vector(to_signed(INT_REAL_PART_OUT_VALUE,data_i_o'length)); 25 | data_q_o <= std_logic_vector(to_signed(INT_IMAG_PART_OUT_VALUE,data_q_o'length)); 26 | data_en_o <= '1'; 27 | data_clk_o <= ref_clk_i; 28 | data_rst_o <= ref_rst_i; 29 | end architecture bhv; 30 | -------------------------------------------------------------------------------- /const_real/hdl/const_real.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity const_real is 6 | generic( 7 | DATA_SIZE : natural := 16; 8 | INT_REAL_PART_OUT_VALUE : integer := 0 9 | ); 10 | port( 11 | --Syscon signals 12 | ref_clk_i : in std_logic; 13 | ref_rst_i : in std_logic; 14 | data_i_o : out std_logic_vector(DATA_SIZE - 1 downto 0); 15 | data_en_o : out std_logic; 16 | data_clk_o : out std_logic; 17 | data_rst_o : out std_logic 18 | ); 19 | end entity const_real; 20 | architecture bhv of const_real is 21 | begin 22 | data_i_o <= std_logic_vector(to_signed(INT_REAL_PART_OUT_VALUE,data_i_o'length)); 23 | data_en_o <= '1'; 24 | data_clk_o <= ref_clk_i; 25 | data_rst_o <= ref_rst_i; 26 | end architecture bhv; 27 | -------------------------------------------------------------------------------- /convertComplexToReal/hdl/convertComplexToReal.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.all; 4 | 5 | Entity convertComplexToReal is 6 | generic ( 7 | DATA_SIZE : natural := 8 8 | ); 9 | port ( 10 | -- output data 11 | data1_o : out std_logic_vector(DATA_SIZE-1 downto 0); 12 | data1_en_o: out std_logic; 13 | data1_eof_o: out std_logic; 14 | data1_clk_o: out std_logic; 15 | data1_rst_o: out std_logic; 16 | data2_o : out std_logic_vector(DATA_SIZE-1 downto 0); 17 | data2_en_o: out std_logic; 18 | data2_eof_o: out std_logic; 19 | data2_clk_o: out std_logic; 20 | data2_rst_o: out std_logic; 21 | -- input data 22 | data_i_i : in std_logic_vector(DATA_SIZE-1 downto 0); 23 | data_q_i : in std_logic_vector(DATA_SIZE-1 downto 0); 24 | data_eof_i : in std_logic; 25 | data_en_i : in std_logic; 26 | data_rst_i : in std_logic; 27 | data_clk_i : in std_logic 28 | ); 29 | end entity; 30 | 31 | --------------------------------------------------------------------------- 32 | Architecture convertComplexToReal_1 of convertComplexToReal is 33 | begin 34 | 35 | data1_o <= data_i_i; 36 | data2_o <= data_q_i; 37 | 38 | data1_en_o <= data_en_i; 39 | data2_en_o <= data_en_i; 40 | 41 | data1_eof_o <= data_eof_i; 42 | data2_eof_o <= data_eof_i; 43 | 44 | data1_clk_o <= data_clk_i; 45 | data2_clk_o <= data_clk_i; 46 | 47 | data1_rst_o <= data_rst_i; 48 | data2_rst_o <= data_rst_i; 49 | 50 | end architecture convertComplexToReal_1; 51 | 52 | -------------------------------------------------------------------------------- /convertComplexToReal/xgui/convertComplexToReal_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "DATA_SIZE" -parent ${Page_0} 7 | 8 | 9 | } 10 | 11 | proc update_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 12 | # Procedure called to update DATA_SIZE when any of the dependent parameters in the arguments change 13 | } 14 | 15 | proc validate_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 16 | # Procedure called to validate DATA_SIZE 17 | return true 18 | } 19 | 20 | 21 | proc update_MODELPARAM_VALUE.DATA_SIZE { MODELPARAM_VALUE.DATA_SIZE PARAM_VALUE.DATA_SIZE } { 22 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 23 | set_property value [get_property value ${PARAM_VALUE.DATA_SIZE}] ${MODELPARAM_VALUE.DATA_SIZE} 24 | } 25 | 26 | -------------------------------------------------------------------------------- /convertRealToComplex/xgui/convertRealToComplex_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | set DATA_SIZE [ipgui::add_param $IPINST -name "DATA_SIZE" -parent ${Page_0}] 7 | set_property tooltip {Size of data busses.} ${DATA_SIZE} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 13 | # Procedure called to update DATA_SIZE when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 17 | # Procedure called to validate DATA_SIZE 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.DATA_SIZE { MODELPARAM_VALUE.DATA_SIZE PARAM_VALUE.DATA_SIZE } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | set_property value [get_property value ${PARAM_VALUE.DATA_SIZE}] ${MODELPARAM_VALUE.DATA_SIZE} 25 | } 26 | 27 | -------------------------------------------------------------------------------- /cplx_conj/hdl/cplx_conj.v: -------------------------------------------------------------------------------- 1 | /*----------------------------------------------------------------------- 2 | * (c) Copyright: OscillatorIMP Digital 3 | * Author : Gwenhael Goavec-Merou 4 | * Creation date : 2017/05/27 5 | *-----------------------------------------------------------------------*/ 6 | module cplx_conj #( 7 | parameter DATA_SIZE = 16 8 | ) ( 9 | // input data 10 | input [DATA_SIZE-1:0] data_i_i, 11 | input [DATA_SIZE-1:0] data_q_i, 12 | input data_en_i, 13 | input data_sof_i, 14 | input data_eof_i, 15 | input data_rst_i, 16 | input data_clk_i, 17 | // output data 18 | output [DATA_SIZE-1:0] data_i_o, 19 | output [DATA_SIZE-1:0] data_q_o, 20 | output data_en_o, 21 | output data_sof_o, 22 | output data_eof_o, 23 | output data_rst_o, 24 | output data_clk_o 25 | ); 26 | 27 | assign data_i_o = data_i_i; 28 | assign data_q_o = -data_q_i; 29 | 30 | assign data_clk_o = data_clk_i; 31 | assign data_eof_o = data_eof_i; 32 | assign data_sof_o = data_sof_i; 33 | assign data_rst_o = data_rst_i; 34 | assign data_en_o = data_en_i; 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /cplx_conj/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= verilog 2 | 3 | PWD=$(shell pwd) 4 | WPWD=$(shell pwd) 5 | 6 | VERILOG_SOURCES = $(WPWD)/../hdl/cplx_conj.v 7 | 8 | VERILOG_SOURCES+=$(WPWD)/top_dut.v 9 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 10 | TOPLEVEL=top_dut 11 | # MODULE is the name of the Python test file: 12 | MODULE=top_cplx_conj_simu_tb 13 | include $(shell cocotb-config --makefiles)/Makefile.inc 14 | include $(shell cocotb-config --makefiles)/Makefile.sim 15 | 16 | view: 17 | gtkwave -a top_cplx_conj_simu.gtkw cplx_conj_simu_tb.vcd 18 | -------------------------------------------------------------------------------- /cplx_conj/simulation/top_cplx_conj_simu.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.106 (w)1999-2020 BSI 3 | [*] Sat Dec 5 06:58:17 2020 4 | [*] 5 | [dumpfile] "/home/gwe/projets/ggm_fpga_ip/lan8720/cplx_conj_simu/cplx_conj_simu_tb.vcd" 6 | [dumpfile_mtime] "Sat Dec 5 06:02:45 2020" 7 | [dumpfile_size] 12044 8 | [savefile] "/home/gwe/projets/ggm_fpga_ip/lan8720/cplx_conj_simu/top_cplx_conj_simu.gtkw" 9 | [timestart] 1007300 10 | [size] 1366 748 11 | [pos] -1 -1 12 | *-15.759605 13520000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] top_dut. 14 | [sst_width] 214 15 | [signals_width] 222 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 209 18 | @28 19 | top_dut.rst_i 20 | top_dut.clk_i 21 | top_dut.start_i 22 | top_dut.cplx_conj_inst.data_en_o 23 | @22 24 | top_dut.data8_o[7:0] 25 | @28 26 | top_dut.data8_en_o 27 | @29 28 | top_dut.sl_clk[1:0] 29 | [pattern_trace] 1 30 | [pattern_trace] 0 31 | -------------------------------------------------------------------------------- /cplx_conj/simulation/top_cplx_conj_simu_tb.py: -------------------------------------------------------------------------------- 1 | import random 2 | import logging 3 | 4 | import cocotb 5 | 6 | from cocotb.clock import Clock 7 | from cocotb.triggers import Timer, RisingEdge, FallingEdge 8 | 9 | clock_period = 10 10 | 11 | @cocotb.coroutine 12 | def reset_dut(reset_n, clk, duration): 13 | reset_n <= 1 14 | yield RisingEdge(clk) 15 | yield Timer(duration) 16 | yield RisingEdge(clk) 17 | reset_n <= 0 18 | reset_n._log.debug("Reset complete") 19 | 20 | 21 | @cocotb.test() 22 | def parallel_example(dut): 23 | dut.data_en_i <= 0 24 | 25 | reset_n = dut.rst_i 26 | 27 | cocotb.fork(Clock(dut.clk_i, 10, 'ns').start()) 28 | yield reset_dut(reset_n, dut.clk_i, 500) 29 | 30 | dut._log.debug("After reset") 31 | yield FallingEdge(dut.clk_i) 32 | yield FallingEdge(dut.clk_i) 33 | 34 | for i in range(200): 35 | dut.data_en_i <= 1 36 | dut.data_i_i <= i - 100 37 | dut.data_q_i <= i - 100 38 | yield FallingEdge(dut.clk_i) 39 | assert i - 100 == int(dut.data_i_o.value.signed_integer) 40 | assert -(i - 100) == int(dut.data_q_o.value.signed_integer) 41 | dut.data_en_i <= 0 42 | -------------------------------------------------------------------------------- /cplx_conj/simulation/top_dut.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 100ps 2 | 3 | module top_dut ( 4 | input clk_i, 5 | input rst_i, 6 | input [15:0] data_i_i, 7 | input [15:0] data_q_i, 8 | input data_en_i, 9 | output [15:0] data_i_o, 10 | output [15:0] data_q_o, 11 | output data_en_o 12 | 13 | ); 14 | cplx_conj #(.DATA_SIZE(16) 15 | ) cplx_conj_inst ( 16 | .data_clk_i(clk_i), .data_rst_i(rst_i), 17 | .data_i_i(data_i_i), .data_q_i(data_q_i), .data_en_i(data_en_i), 18 | .data_eof_i(1'b0), .data_sof_i(1'b0), 19 | .data_i_o(data_i_o), .data_q_o(data_q_o), .data_en_o(data_en_o), 20 | .data_eof_o(), .data_sof_o() 21 | ); 22 | 23 | `ifdef COCOTB_SIM 24 | initial begin 25 | $dumpfile("cplx_conj_simu_tb.vcd"); 26 | $dumpvars(0, top_dut); 27 | #1; 28 | end 29 | `endif 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /cplx_conj/xgui/cplx_conj_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | set DATA_SIZE [ipgui::add_param $IPINST -name "DATA_SIZE" -parent ${Page_0}] 7 | set_property tooltip {Size of data bus.} ${DATA_SIZE} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 13 | # Procedure called to update DATA_SIZE when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 17 | # Procedure called to validate DATA_SIZE 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.DATA_SIZE { MODELPARAM_VALUE.DATA_SIZE PARAM_VALUE.DATA_SIZE } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | set_property value [get_property value ${PARAM_VALUE.DATA_SIZE}] ${MODELPARAM_VALUE.DATA_SIZE} 25 | } 26 | 27 | -------------------------------------------------------------------------------- /dataComplex_dma_direct/hdl/dataComplex_dma_direct_sync.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity dataComplex_dma_direct_sync is 5 | generic (stages : natural := 3); 6 | port (clk_i : in std_logic; 7 | bit_i : in std_logic; 8 | bit_o : out std_logic 9 | ); 10 | end entity dataComplex_dma_direct_sync; 11 | 12 | architecture bhv of dataComplex_dma_direct_sync is 13 | signal flipflops : std_logic_vector(stages -1 downto 0) := (others => '0'); 14 | attribute ASYNC_REG : string; 15 | attribute ASYNC_REG of flipflops: signal is "true"; 16 | begin 17 | bit_o <= flipflops(stages-1); 18 | 19 | sync_proc: process(clk_i) 20 | begin 21 | if rising_edge(clk_i) then 22 | flipflops <= flipflops(stages-2 downto 0) & bit_i; 23 | end if; 24 | end process; 25 | end bhv; 26 | -------------------------------------------------------------------------------- /dataComplex_dma_direct/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM = ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | PLUSARGS=--vcdgz=$(WPWD)/build/waveform.vcdgz --wave=$(WPWD)/build/waveform.ghw 7 | 8 | VHDL_SOURCES=$(WPWD)/../hdl/axi_dataComplex_dma_direct.vhd \ 9 | $(WPWD)/../../pseudo_gen_trig/hdl/pseudo_gen_trig_logic.vhd \ 10 | $(WPWD)/../../pulseGenDelayed/hdl/pulseGenDelayed_logic.vhd \ 11 | $(WPWD)/../../genPulseTwoWayCplx/hdl/genPulseTwoWayCplx_logic.vhd 12 | 13 | VHDL_SOURCES+=$(WPWD)/top_dataDma.vhd 14 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 15 | TOPLEVEL=top_dut 16 | # MODULE is the name of the Python test file: 17 | MODULE=top_dataDma_tb 18 | include $(shell cocotb-config --makefiles)/Makefile.inc 19 | include $(shell cocotb-config --makefiles)/Makefile.sim 20 | 21 | view: 22 | gtkwave -a top_dataDma.gtkw build/waveform.ghw 23 | -------------------------------------------------------------------------------- /dataComplex_to_ram/dataComplex_to_ram.xdc: -------------------------------------------------------------------------------- 1 | set_property ASYNC_REG TRUE \ 2 | [get_cells -hier sync_stage1_*_reg] \ 3 | [get_cells -hier sync_stage2_*_reg] 4 | set_false_path \ 5 | -from [get_cells -hier sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ 6 | -to [get_cells -hier sync_stage1_*_reg -filter {IS_SEQUENTIAL}] 7 | -------------------------------------------------------------------------------- /dataComplex_to_ram/hdl/dataComplex_resizer.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2018/11/30 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | use IEEE.numeric_std.ALL; 9 | 10 | entity dataComplex_resizer is 11 | generic ( 12 | IN_SZ : natural := 32; 13 | OUT_SZ : natural := 32; 14 | DATA_FORMAT : string := "signed" 15 | ); 16 | port ( 17 | data_i_i : in std_logic_vector(IN_SZ-1 downto 0); 18 | data_q_i : in std_logic_vector(IN_SZ-1 downto 0); 19 | data_o : out std_logic_vector((2*OUT_SZ)-1 downto 0) 20 | ); 21 | end dataComplex_resizer; 22 | 23 | architecture bhv of dataComplex_resizer is 24 | begin 25 | 26 | same_size_gen : if IN_SZ = OUT_SZ generate 27 | data_o <= data_q_i & data_i_i; 28 | end generate same_size_gen; 29 | diff_size_gen : if IN_SZ < OUT_SZ generate 30 | data_signed : if DATA_FORMAT = "signed" generate 31 | data_o <= (OUT_SZ-1 downto IN_SZ => data_q_i(IN_SZ-1)) & data_q_i 32 | & 33 | (OUT_SZ-1 downto IN_SZ => data_i_i(IN_SZ-1)) & data_i_i; 34 | end generate data_signed; 35 | data_unsigned : if DATA_FORMAT = "unsigned" generate 36 | data_o <= (OUT_SZ-1 downto IN_SZ => '0') & data_q_i 37 | & 38 | (OUT_SZ-1 downto IN_SZ => '0') & data_i_i; 39 | end generate data_unsigned; 40 | end generate diff_size_gen; 41 | end architecture bhv; 42 | -------------------------------------------------------------------------------- /dataComplex_to_ram/hdl/dataComplex_sync.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2018/11/30 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity dataComplex_sync is 10 | generic (stages : natural := 3); 11 | port ( 12 | ref_clk_i : in std_logic; 13 | clk_i : in std_logic; 14 | bit_i : in std_logic; 15 | bit_o : out std_logic 16 | ); 17 | end entity dataComplex_sync; 18 | 19 | architecture bhv of dataComplex_sync is 20 | signal sync_stage0_s, sync_stage1_s: std_logic; 21 | signal sync_stage2_s, sync_stage3_s: std_logic; 22 | attribute ASYNC_REG : string; 23 | attribute ASYNC_REG of sync_stage1_s: signal is "true"; 24 | attribute ASYNC_REG of sync_stage2_s: signal is "true"; 25 | begin 26 | ref_proc: process(ref_clk_i) begin 27 | if rising_edge(ref_clk_i) then 28 | sync_stage0_s <= bit_i; 29 | end if; 30 | end process; 31 | 32 | sync_proc: process(clk_i) 33 | begin 34 | if rising_edge(clk_i) then 35 | sync_stage1_s <= sync_stage0_s; 36 | sync_stage2_s <= sync_stage1_s; 37 | sync_stage3_s <= sync_stage2_s; 38 | end if; 39 | end process; 40 | bit_o <= sync_stage3_s; 41 | end bhv; 42 | -------------------------------------------------------------------------------- /dataComplex_to_ram/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_data_subtop 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../hdl/dataComplex_sync.vhd \ 10 | ../hdl/dataComplex_resizer.vhd \ 11 | ../hdl/dataComplex_storage.vhd \ 12 | ../hdl/dataComplex_subtop.vhd 13 | 14 | SIMDIR=simu 15 | 16 | VIEW_CMD = gtkwave 17 | 18 | all : run 19 | 20 | # Run target 21 | run:$(SIMDIR)/$(SIMTOP).ghw 22 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 23 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 24 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 25 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 26 | 27 | # Targets to analyze libraries 28 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 29 | mkdir -p $(SIMDIR) 30 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 31 | 32 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 33 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 34 | 35 | clean: 36 | $(GHDL) --clean --workdir=simu 37 | -rm -rf simu 38 | force: 39 | -------------------------------------------------------------------------------- /dataComplex_to_ram_pingpong/dataComplex_to_ram_pingpong.xdc: -------------------------------------------------------------------------------- 1 | set_property RAM_STYLE block [get_cells {data32_top_inst/subtop_loop[0].data_subtop_inst/ram_msb/mem_ping_reg}] 2 | set_property RAM_STYLE block [get_cells {data32_top_inst/subtop_loop[0].data_subtop_inst/ram_msb/mem_pong_reg}] -------------------------------------------------------------------------------- /dataComplex_to_ram_pingpong/hdl/dataComplex_resizer.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.ALL; 4 | 5 | entity dataComplex_resizer is 6 | generic ( 7 | IN_SZ : natural := 32; 8 | OUT_SZ : natural := 32; 9 | DATA_FORMAT : string := "signed" 10 | ); 11 | port ( 12 | data_i_i : in std_logic_vector(IN_SZ-1 downto 0); 13 | data_q_i : in std_logic_vector(IN_SZ-1 downto 0); 14 | data_o : out std_logic_vector((2*OUT_SZ)-1 downto 0) 15 | ); 16 | end dataComplex_resizer; 17 | 18 | architecture bhv of dataComplex_resizer is 19 | begin 20 | 21 | same_size_gen : if IN_SZ = OUT_SZ generate 22 | data_o <= data_q_i & data_i_i; 23 | end generate same_size_gen; 24 | diff_size_gen : if IN_SZ < OUT_SZ generate 25 | data_signed : if DATA_FORMAT = "signed" generate 26 | data_o <= (OUT_SZ-1 downto IN_SZ => data_q_i(IN_SZ-1)) & data_q_i 27 | & 28 | (OUT_SZ-1 downto IN_SZ => data_i_i(IN_SZ-1)) & data_i_i; 29 | end generate data_signed; 30 | data_unsigned : if DATA_FORMAT = "unsigned" generate 31 | data_o <= (OUT_SZ-1 downto IN_SZ => '0') & data_q_i 32 | & 33 | (OUT_SZ-1 downto IN_SZ => '0') & data_i_i; 34 | end generate data_unsigned; 35 | end generate diff_size_gen; 36 | end architecture bhv; 37 | -------------------------------------------------------------------------------- /dataComplex_to_ram_pingpong/hdl/dataComplex_storage.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.all; 4 | 5 | entity dataComplex_to_ram_pingpong_storage is 6 | generic ( 7 | DATA : integer := 72; 8 | ADDR : integer := 10 9 | ); 10 | port ( 11 | clk_a : in std_logic; 12 | clk_b : in std_logic; 13 | rst_b : in std_logic; 14 | -- state machine interface 15 | we_a : in std_logic; 16 | addr_a: in std_logic_vector(ADDR-1 downto 0); 17 | din_a : in std_logic_vector(DATA-1 downto 0); 18 | addr_b: in std_logic_vector(ADDR-1 downto 0); 19 | dout_b: out std_logic_vector(DATA-1 downto 0) 20 | ); 21 | end entity; 22 | architecture rtl of dataComplex_to_ram_pingpong_storage is 23 | -- Shared memory 24 | type mem_type is array ( (2**ADDR)-1 downto 0 ) of std_logic_vector(DATA-1 downto 0); 25 | shared variable mem : mem_type; 26 | signal rd_addr_s : std_logic_vector(ADDR-1 downto 0); 27 | signal null_s : std_logic_vector(DATA-1 downto 0); 28 | begin 29 | 30 | -- Port A 31 | process(clk_a) 32 | begin 33 | if(rising_edge(clk_a)) then 34 | if(we_a='1') then 35 | mem(to_integer(unsigned(addr_a))) := din_a; 36 | end if; 37 | end if; 38 | end process; 39 | 40 | -- Port B 41 | process(clk_b) 42 | begin 43 | if(rising_edge(clk_b)) then 44 | if (rst_b = '1') then 45 | dout_b <= (others => '0'); 46 | else 47 | dout_b <= mem(to_integer(unsigned(addr_b))); 48 | end if; 49 | end if; 50 | end process; 51 | 52 | end architecture rtl; 53 | -------------------------------------------------------------------------------- /dataReal_dma_direct/hdl/dataReal_dma_direct_sync.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity dataReal_dma_direct_sync is 5 | generic (stages : natural := 3); 6 | port (clk_i : in std_logic; 7 | bit_i : in std_logic; 8 | bit_o : out std_logic 9 | ); 10 | end entity dataReal_dma_direct_sync; 11 | 12 | architecture bhv of dataReal_dma_direct_sync is 13 | signal flipflops : std_logic_vector(stages -1 downto 0) := (others => '0'); 14 | attribute ASYNC_REG : string; 15 | attribute ASYNC_REG of flipflops: signal is "true"; 16 | begin 17 | bit_o <= flipflops(stages-1); 18 | 19 | sync_proc: process(clk_i) 20 | begin 21 | if rising_edge(clk_i) then 22 | flipflops <= flipflops(stages-2 downto 0) & bit_i; 23 | end if; 24 | end process; 25 | end bhv; 26 | -------------------------------------------------------------------------------- /dataReal_dma_direct/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM = ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | PLUSARGS=--vcdgz=$(WPWD)/build/waveform.vcdgz --wave=$(WPWD)/build/waveform.ghw 7 | 8 | VHDL_SOURCES=$(WPWD)/../hdl/axi_dataReal_dma_direct.vhd \ 9 | $(WPWD)/../../pseudo_gen_trig/hdl/pseudo_gen_trig_logic.vhd \ 10 | $(WPWD)/../../pulseGenDelayed/hdl/pulseGenDelayed_logic.vhd \ 11 | $(WPWD)/../../genPulseTwoWayCplx/hdl/genPulseTwoWayCplx_logic.vhd 12 | 13 | VHDL_SOURCES+=$(WPWD)/top_dataDma.vhd 14 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 15 | TOPLEVEL=top_dut 16 | # MODULE is the name of the Python test file: 17 | MODULE=top_dataDma_tb 18 | include $(shell cocotb-config --makefiles)/Makefile.inc 19 | include $(shell cocotb-config --makefiles)/Makefile.sim 20 | 21 | view: 22 | gtkwave -a top_dataDma.gtkw build/waveform.ghw 23 | -------------------------------------------------------------------------------- /dataReal_to_ram/dataReal_to_ram.xdc: -------------------------------------------------------------------------------- 1 | set_property ASYNC_REG TRUE \ 2 | [get_cells -hier sync_stage1_*_reg] \ 3 | [get_cells -hier sync_stage2_*_reg] 4 | set_false_path \ 5 | -from [get_cells -hier sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ 6 | -to [get_cells -hier sync_stage1_*_reg -filter {IS_SEQUENTIAL}] 7 | -------------------------------------------------------------------------------- /dataReal_to_ram/hdl/dataReal_resizer.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2018/12/16 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | use IEEE.numeric_std.ALL; 9 | 10 | entity dataReal_resizer is 11 | generic ( 12 | IN_SZ : natural := 32; 13 | OUT_SZ : natural := 32; 14 | DATA_FORMAT : string := "signed" 15 | ); 16 | port ( 17 | data_i : in std_logic_vector(IN_SZ-1 downto 0); 18 | data_o : out std_logic_vector(OUT_SZ-1 downto 0) 19 | ); 20 | end dataReal_resizer; 21 | 22 | architecture bhv of dataReal_resizer is 23 | begin 24 | 25 | same_size_gen : if IN_SZ = OUT_SZ generate 26 | data_o <= data_i; 27 | end generate same_size_gen; 28 | diff_size_gen : if IN_SZ < OUT_SZ generate 29 | data_signed : if DATA_FORMAT = "signed" generate 30 | data_o <= (OUT_SZ-1 downto IN_SZ => data_i(IN_SZ-1)) & data_i; 31 | end generate data_signed; 32 | data_unsigned : if DATA_FORMAT = "unsigned" generate 33 | data_o <= (OUT_SZ-1 downto IN_SZ => '0') & data_i; 34 | end generate data_unsigned; 35 | end generate diff_size_gen; 36 | end architecture bhv; 37 | -------------------------------------------------------------------------------- /dataReal_to_ram/hdl/dataReal_sync.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2018/12/16 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity dataReal_sync is 10 | generic (stages : natural := 3); 11 | port ( 12 | ref_clk_i : in std_logic; 13 | clk_i : in std_logic; 14 | bit_i : in std_logic; 15 | bit_o : out std_logic 16 | ); 17 | end entity dataReal_sync; 18 | 19 | architecture bhv of dataReal_sync is 20 | signal sync_stage0_s, sync_stage1_s: std_logic; 21 | signal sync_stage2_s, sync_stage3_s: std_logic; 22 | attribute ASYNC_REG : string; 23 | attribute ASYNC_REG of sync_stage1_s: signal is "true"; 24 | attribute ASYNC_REG of sync_stage2_s: signal is "true"; 25 | begin 26 | ref_proc: process(ref_clk_i) begin 27 | if rising_edge(ref_clk_i) then 28 | sync_stage0_s <= bit_i; 29 | end if; 30 | end process; 31 | 32 | sync_proc: process(clk_i) 33 | begin 34 | if rising_edge(clk_i) then 35 | sync_stage1_s <= sync_stage0_s; 36 | sync_stage2_s <= sync_stage1_s; 37 | sync_stage3_s <= sync_stage2_s; 38 | end if; 39 | end process; 40 | bit_o <= sync_stage3_s; 41 | end bhv; 42 | -------------------------------------------------------------------------------- /dataReal_to_ram_pingpong/dataReal_to_ram_pingpong.xdc: -------------------------------------------------------------------------------- 1 | set_property RAM_STYLE block [get_cells {data32_top_inst/subtop_loop[0].data_subtop_inst/ram_msb/mem_ping_reg}] 2 | set_property RAM_STYLE block [get_cells {data32_top_inst/subtop_loop[0].data_subtop_inst/ram_msb/mem_pong_reg}] -------------------------------------------------------------------------------- /dataReal_to_ram_pingpong/hdl/dataReal_resizer.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2018/11/30 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | use IEEE.numeric_std.ALL; 9 | 10 | entity dataReal_resizer is 11 | generic ( 12 | IN_SZ : natural := 32; 13 | OUT_SZ : natural := 32; 14 | DATA_FORMAT : string := "signed" 15 | ); 16 | port ( 17 | data_i : in std_logic_vector(IN_SZ-1 downto 0); 18 | data_o : out std_logic_vector(OUT_SZ-1 downto 0) 19 | ); 20 | end dataReal_resizer; 21 | 22 | architecture bhv of dataReal_resizer is 23 | begin 24 | 25 | same_size_gen : if IN_SZ = OUT_SZ generate 26 | data_o <= data_i; 27 | end generate same_size_gen; 28 | diff_size_gen : if IN_SZ < OUT_SZ generate 29 | data_signed : if DATA_FORMAT = "signed" generate 30 | data_o <= (OUT_SZ-1 downto IN_SZ => data_i(IN_SZ-1)) & data_i; 31 | end generate data_signed; 32 | data_unsigned : if DATA_FORMAT = "unsigned" generate 33 | data_o <= (OUT_SZ-1 downto IN_SZ => '0') & data_i; 34 | end generate data_unsigned; 35 | end generate diff_size_gen; 36 | end architecture bhv; 37 | -------------------------------------------------------------------------------- /dataReal_to_ram_pingpong/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_data_subtop 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../hdl/dataReal_resizer.vhd \ 10 | ../hdl/dataReal_storage.vhd \ 11 | ../hdl/dataReal_logic.vhd 12 | 13 | SIMDIR=simu 14 | 15 | VIEW_CMD = gtkwave 16 | 17 | all : run 18 | 19 | # Run target 20 | run:$(SIMDIR)/$(SIMTOP).ghw 21 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 22 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 23 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 24 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 25 | 26 | # Targets to analyze libraries 27 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 28 | mkdir -p $(SIMDIR) 29 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 30 | 31 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 32 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 33 | 34 | clean: 35 | $(GHDL) --clean --workdir=simu 36 | -rm -rf simu 37 | force: 38 | -------------------------------------------------------------------------------- /ddmtd/Makefile: -------------------------------------------------------------------------------- 1 | VIVADO := vivado -mode batch -source 2 | IP_CORE_VERSION := 1.0 3 | 4 | configs = ip 5 | 6 | all: $(configs) 7 | 8 | $(configs): 9 | mkdir -p $@ 10 | ./gen_hdl.py $@/ddmtd 11 | cd $@ && IP_CORE_VERSION=$(IP_CORE_VERSION) $(VIVADO) ../package_ip.tcl 12 | 13 | clean: 14 | rm -rf $(configs) 15 | 16 | .PHONY: all clean $(configs) 17 | -------------------------------------------------------------------------------- /ddmtd/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | 'freq': 125e6, 3 | 'word_size': 32, 4 | 'mult': 8, 5 | 'div': 100 6 | } 7 | -------------------------------------------------------------------------------- /ddmtd/ddmtd.xdc: -------------------------------------------------------------------------------- 1 | # Set false path for Amaranth generated attributes 2 | set_false_path -to [get_cells -hier -filter {amaranth.vivado.false_path == "TRUE"}] 3 | -------------------------------------------------------------------------------- /ddmtd/gen_hdl.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import argparse 4 | import os 5 | import subprocess 6 | import sys 7 | 8 | from amaranth_boards.redpitaya_125_14 import RedPitaya14Platform 9 | from amaranth.build import Resource, Pins, Attrs 10 | import amaranth 11 | 12 | from src.ddmtd import DDMTD 13 | 14 | def parse_args(): 15 | parser = argparse.ArgumentParser() 16 | parser.add_argument( 17 | 'output_name', help='Output verilog file') 18 | parser.add_argument( 19 | '--conf_file', default='conf.json') 20 | return parser.parse_args() 21 | 22 | 23 | def main(): 24 | args = parse_args() 25 | conf = eval(open(args.conf_file, 'r').read()) 26 | top = DDMTD(**conf) 27 | platform = RedPitaya14Platform() 28 | with open(f'{args.output_name}.v', 'w') as f: 29 | f.write(amaranth.back.verilog.convert( 30 | top, platform=platform, ports=top.ports())) 31 | 32 | if __name__ == '__main__': 33 | main() 34 | -------------------------------------------------------------------------------- /ddmtd/package_ip.tcl: -------------------------------------------------------------------------------- 1 | # Package Maia SDR IP core 2 | 3 | create_project ddmtd . -force 4 | add_files ddmtd.v 5 | add_files -fileset constrs_1 -norecurse ../ddmtd.xdc 6 | set_property top top [current_fileset] 7 | load_features ipservices 8 | ipx::package_project -import_files -root_dir . -vendor oscimp -library user -force 9 | set_property name ddmtd [ipx::current_core] 10 | set_property library ddmtd [ipx::current_core] 11 | set_property display_name {DDMTD} [ipx::current_core] 12 | set_property description "DDMTD" [ipx::current_core] 13 | set_property vendor_display_name {OscimpDigital} [ipx::current_core] 14 | set_property version $::env(IP_CORE_VERSION) [ipx::current_core] 15 | 16 | # phase_clk interface 17 | ipx::add_bus_interface phase_clk [ipx::current_core] 18 | set_property abstraction_type_vlnv xilinx.com:signal:clock_rtl:1.0 \ 19 | [ipx::get_bus_interfaces phase_clk -of_objects [ipx::current_core]] 20 | set_property bus_type_vlnv xilinx.com:signal:clock:1.0 \ 21 | [ipx::get_bus_interfaces phase_clk -of_objects [ipx::current_core]] 22 | ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces phase_clk -of_objects [ipx::current_core]] 23 | 24 | ipx::create_xgui_files [ipx::current_core] 25 | ipx::save_core [ipx::current_core] 26 | -------------------------------------------------------------------------------- /delayTempoReal_axi/delayTempoReal_axi.xdc: -------------------------------------------------------------------------------- 1 | set_false_path -from [get_pins -hier *delay_s*/C] 2 | -------------------------------------------------------------------------------- /delayTempoReal_axi/hdl/delayTempoReal_axi_sync_slv.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity delayTempoReal_axi_sync_slv is 5 | generic (stages : natural := 3; 6 | DATA : natural := 16); 7 | port (clk_i : in std_logic; 8 | bit_i : in std_logic_vector(DATA-1 downto 0); 9 | bit_o : out std_logic_vector(DATA-1 downto 0) 10 | ); 11 | end entity delayTempoReal_axi_sync_slv; 12 | 13 | architecture bhv of delayTempoReal_axi_sync_slv is 14 | type data_tab is array (natural range <>) of std_logic_vector(DATA-1 downto 0); 15 | signal flipflops : data_tab(stages -1 downto 0) := 16 | (others => (others => '0')); 17 | attribute ASYNC_REG : string; 18 | attribute ASYNC_REG of flipflops: signal is "true"; 19 | begin 20 | bit_o <= flipflops(stages-1); 21 | 22 | sync_proc: process(clk_i) 23 | begin 24 | if rising_edge(clk_i) then 25 | flipflops <= flipflops(stages-2 downto 0) & bit_i; 26 | end if; 27 | end process; 28 | end bhv; 29 | -------------------------------------------------------------------------------- /delayTempoReal_axi/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | -------------------------------------------------------------------------------- /delayTempoReal_axi/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_delayTempo 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../hdl/delayTempoReal_axi_logic.vhd \ 10 | ../hdl/delayTempoReal_axi_comm.vhd \ 11 | ../hdl/delayTempoReal_axi_handCom.vhd \ 12 | ../hdl/delayTempoReal_axi_sync_slv.vhd \ 13 | ../hdl/delayTempoReal_axi.vhd 14 | 15 | SIMDIR=simu 16 | 17 | VIEW_CMD = gtkwave 18 | 19 | all : run 20 | 21 | # Run target 22 | run:$(SIMDIR)/$(SIMTOP).ghw 23 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 24 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 25 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 26 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 27 | 28 | # Targets to analyze libraries 29 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 30 | mkdir -p $(SIMDIR) 31 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 32 | 33 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 34 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 35 | 36 | clean: 37 | $(GHDL) --clean --workdir=simu 38 | -rm -rf simu 39 | force: 40 | -------------------------------------------------------------------------------- /dfu_frm.mk: -------------------------------------------------------------------------------- 1 | IP?=192.168.2.1 # must be changed in settings.sh 2 | 3 | OUTPUT_DIR=$(BR_DIR)/output 4 | export HOST_DIR=$(OUTPUT_DIR)/host 5 | IMG_DIR=$(OUTPUT_DIR)/images 6 | dirname = $(patsubst %/,%,$(dir $1)) 7 | DESIGN_DIR=$(notdir $(call dirname,$(CURDIR))) 8 | dirname = $(shell pwd) 9 | 10 | ifeq ($(BOARD_NAME), plutosdr) 11 | BIT_FILE=$(dirname)/*.runs/impl_1/*.bit 12 | else 13 | BIT_FILE=$(dirname)/tmp/*.runs/impl_1/*.bit 14 | endif 15 | 16 | test: 17 | echo $(BOARD_NAME) 18 | 19 | POST_SCRIPT=$(shell grep '^BR2_ROOTFS_POST_IMAGE_SCRIPT' $(BR_DIR)/.config 2>/dev/null | cut -d \" -f 2) 20 | IS_ABS_PATH=$(shell echo '${POST_SCRIPT}' | grep -o "\$\{.*\}") 21 | 22 | # if post_image refer to a variable -> br2_external 23 | ifneq ($(IS_ABS_PATH),) 24 | # include mk build by buildroot with all br2_external variables 25 | include $(OUTPUT_DIR)/.br*-external.mk 26 | endif 27 | ifeq ($(BOARD_NAME),plutosdr) 28 | POST_SCRIPT=$(BR2_EXTERNAL_PLUTOSDR_PATH)/board/pluto/post_image.sh 29 | endif 30 | 31 | .PHONY: image dfu_frm flash_dfu_frm 32 | image: 33 | mkdir -p image 34 | 35 | dfu_frm: |image 36 | cp $(IMG_DIR)/*.dtb $(IMG_DIR)/rootfs* $(IMG_DIR)/zImage $(BIT_FILE) ./image/ 37 | $(POST_SCRIPT) ./image 38 | 39 | flash_dfu_frm: 40 | ssh root@$(IP) "device_reboot sf"; sleep 10; 41 | sudo dfu-util -R -D image/*.dfu -a firmware.dfu 42 | -------------------------------------------------------------------------------- /dupplComplex_1_to_2/xgui/dupplComplex_1_to_2_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | #Adding Page 4 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 5 | set_property tooltip {Page 0} ${Page_0} 6 | ipgui::add_param $IPINST -name "Component_Name" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "DATA_SIZE" -parent ${Page_0} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 13 | # Procedure called to update DATA_SIZE when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 17 | # Procedure called to validate DATA_SIZE 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.DATA_SIZE { MODELPARAM_VALUE.DATA_SIZE PARAM_VALUE.DATA_SIZE } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | set_property value [get_property value ${PARAM_VALUE.DATA_SIZE}] ${MODELPARAM_VALUE.DATA_SIZE} 25 | } 26 | 27 | -------------------------------------------------------------------------------- /dupplReal_1_to_2/hdl/dupplReal_1_to_2.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2014/10/14 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | use IEEE.numeric_std.ALL; 9 | 10 | entity dupplReal_1_to_2 is 11 | generic ( 12 | DATA_SIZE : natural := 8 13 | ); 14 | port ( 15 | -- DATA in 16 | data_en_i : in std_logic; 17 | data_eof_i : in std_logic; 18 | data_clk_i : in std_logic; 19 | data_rst_i : in std_logic; 20 | data_i: in std_logic_vector(DATA_SIZE-1 downto 0); 21 | -- next 22 | data1_en_o : out std_logic; 23 | data1_eof_o : out std_logic; 24 | data1_clk_o : out std_logic; 25 | data1_rst_o : out std_logic; 26 | data1_o : out std_logic_vector(DATA_SIZE-1 downto 0); 27 | data2_en_o : out std_logic; 28 | data2_eof_o : out std_logic; 29 | data2_clk_o : out std_logic; 30 | data2_rst_o : out std_logic; 31 | data2_o : out std_logic_vector(DATA_SIZE-1 downto 0) 32 | ); 33 | end dupplReal_1_to_2; 34 | 35 | architecture Behavioral of dupplReal_1_to_2 is 36 | begin 37 | data1_o <= data_i; 38 | data1_en_o <= data_en_i; 39 | data1_eof_o <= data_eof_i; 40 | data1_clk_o <= data_clk_i; 41 | data1_rst_o <= data_rst_i; 42 | 43 | data2_o <= data_i; 44 | data2_en_o <= data_en_i; 45 | data2_eof_o <= data_eof_i; 46 | data2_clk_o <= data_clk_i; 47 | data2_rst_o <= data_rst_i; 48 | end Behavioral; 49 | 50 | -------------------------------------------------------------------------------- /dupplReal_1_to_2/xgui/dupplReal_1_to_2_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | #Adding Page 4 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 5 | set_property tooltip {Page 0} ${Page_0} 6 | ipgui::add_param $IPINST -name "Component_Name" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "DATA_SIZE" -parent ${Page_0} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 13 | # Procedure called to update DATA_SIZE when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 17 | # Procedure called to validate DATA_SIZE 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.DATA_SIZE { MODELPARAM_VALUE.DATA_SIZE PARAM_VALUE.DATA_SIZE } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | set_property value [get_property value ${PARAM_VALUE.DATA_SIZE}] ${MODELPARAM_VALUE.DATA_SIZE} 25 | } 26 | 27 | -------------------------------------------------------------------------------- /expanderComplex/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM = ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | PLUSARGS=--vcdgz=$(WPWD)/sim_build/waveform.vcdgz --wave=$(WPWD)/sim_build/waveform.ghw 7 | 8 | VHDL_SOURCES=$(WPWD)/../hdl/expanderComplex.vhd 9 | 10 | VHDL_SOURCES+=$(WPWD)/top_expanderComplex.vhd 11 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 12 | TOPLEVEL=top_shiftercomplex 13 | # MODULE is the name of the Python test file: 14 | MODULE=top_expanderComplex_tb 15 | include $(shell cocotb-config --makefiles)/Makefile.sim 16 | 17 | ghdl_view: 18 | gtkwave -a top_expanderComplex.gtkw build/waveform.ghw 19 | -------------------------------------------------------------------------------- /expanderComplex/simulation/top_expanderComplex.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.ALL; 4 | 5 | entity top_expandercomplex is 6 | port ( 7 | clk_i : in std_logic; 8 | rst_i : in std_logic; 9 | -- in 10 | data_en_i : in std_logic; 11 | data_i_i : in std_logic_vector(15 downto 0); 12 | data_q_i : in std_logic_vector(15 downto 0); 13 | -- out 14 | data_i_o : out std_logic_vector(7 downto 0); 15 | data_q_o : out std_logic_vector(7 downto 0); 16 | data_en_o : out std_logic 17 | ); 18 | end top_expandercomplex; 19 | 20 | architecture Behavioral of top_expandercomplex is 21 | begin 22 | shift_same_inst : entity work.expanderComplex 23 | generic map ( 24 | format => "signed", 25 | DATA_IN_SIZE => 16, 26 | DATA_OUT_SIZE => 8 27 | ) 28 | port map ( 29 | data_i_i => data_i_i, data_q_i => data_q_i, data_en_i => data_en_i, 30 | data_eof_i => '0', data_sof_i => '0', 31 | data_clk_i => clk_i, data_rst_i => rst_i, 32 | data_i_o => data_i_o, data_q_o => data_q_o, data_en_o => data_en_o, 33 | data_eof_o => open, data_sof_o => open, 34 | data_clk_o => open, data_rst_o => open 35 | ); 36 | 37 | end Behavioral; 38 | -------------------------------------------------------------------------------- /expanderComplex/simulation/top_expanderComplex_tb.py: -------------------------------------------------------------------------------- 1 | import random 2 | import logging 3 | 4 | import cocotb 5 | 6 | from cocotb.clock import Clock 7 | from cocotb.triggers import Timer, RisingEdge, FallingEdge 8 | 9 | @cocotb.coroutine 10 | def reset_dut(reset_n, clk, duration): 11 | reset_n <= 1 12 | yield RisingEdge(clk) 13 | yield Timer(duration) 14 | yield RisingEdge(clk) 15 | reset_n <= 0 16 | reset_n._log.debug("Reset complete") 17 | 18 | 19 | @cocotb.test() 20 | def parallel_example(dut): 21 | val = [i for i in range(-2**15, 2**15, 10)] 22 | 23 | val_max = 127 24 | val_min = -128 25 | 26 | dut.data_en_i <= 0 27 | 28 | reset_n = dut.rst_i 29 | 30 | cocotb.fork(Clock(dut.clk_i, 10, 'ns').start()) 31 | yield reset_dut(reset_n, dut.clk_i, 500) 32 | 33 | dut._log.debug("After reset") 34 | yield FallingEdge(dut.clk_i) 35 | yield FallingEdge(dut.clk_i) 36 | 37 | for i in val: 38 | dut.data_en_i <= 1 39 | dut.data_i_i <= i 40 | dut.data_q_i <= i 41 | yield FallingEdge(dut.clk_i) 42 | dut.data_en_i <= 0 43 | yield FallingEdge(dut.clk_i) 44 | if i < val_min: 45 | res = val_min 46 | elif i > val_max: 47 | res = val_max 48 | else: 49 | res = i 50 | print(f"{i} {res} {int(dut.data_i_o.value.signed_integer)}") 51 | assert res == int(dut.data_i_o.value.signed_integer) 52 | assert res == int(dut.data_q_o.value.signed_integer) 53 | dut.data_en_i <= 0 54 | -------------------------------------------------------------------------------- /expanderReal/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM = ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | PLUSARGS=--vcdgz=$(WPWD)/sim_build/waveform.vcdgz --wave=$(WPWD)/sim_build/waveform.ghw 7 | 8 | VHDL_SOURCES=$(WPWD)/../hdl/expanderReal.vhd 9 | 10 | VHDL_SOURCES+=$(WPWD)/top_expanderReal.vhd 11 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 12 | TOPLEVEL=top_expanderreal 13 | # MODULE is the name of the Python test file: 14 | MODULE=top_expanderReal_tb 15 | include $(shell cocotb-config --makefiles)/Makefile.sim 16 | 17 | ghdl_view: 18 | gtkwave -a top_expanderReal.gtkw build/waveform.ghw 19 | -------------------------------------------------------------------------------- /expanderReal/simulation/top_expanderReal.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.ALL; 4 | 5 | entity top_expanderreal is 6 | port ( 7 | clk_i : in std_logic; 8 | rst_i : in std_logic; 9 | -- in 10 | data_en_i : in std_logic; 11 | data_i : in std_logic_vector(15 downto 0); 12 | -- out 13 | data_o : out std_logic_vector(7 downto 0); 14 | data_en_o : out std_logic 15 | ); 16 | end top_expanderreal; 17 | 18 | architecture Behavioral of top_expanderreal is 19 | begin 20 | shift_same_inst : entity work.expanderReal 21 | generic map ( 22 | format => "signed", 23 | DATA_IN_SIZE => 16, 24 | DATA_OUT_SIZE => 8 25 | ) 26 | port map ( 27 | data_i => data_i, data_en_i => data_en_i, 28 | data_eof_i => '0', data_sof_i => '0', 29 | data_clk_i => clk_i, data_rst_i => rst_i, 30 | data_o => data_o, data_en_o => data_en_o, 31 | data_eof_o => open, data_sof_o => open, 32 | data_clk_o => open, data_rst_o => open 33 | ); 34 | 35 | end Behavioral; 36 | -------------------------------------------------------------------------------- /expanderReal/simulation/top_expanderReal_tb.py: -------------------------------------------------------------------------------- 1 | import random 2 | import logging 3 | 4 | import cocotb 5 | 6 | from cocotb.clock import Clock 7 | from cocotb.triggers import Timer, RisingEdge, FallingEdge 8 | 9 | @cocotb.coroutine 10 | def reset_dut(reset_n, clk, duration): 11 | reset_n <= 1 12 | yield RisingEdge(clk) 13 | yield Timer(duration) 14 | yield RisingEdge(clk) 15 | reset_n <= 0 16 | reset_n._log.debug("Reset complete") 17 | 18 | 19 | @cocotb.test() 20 | def parallel_example(dut): 21 | val = [i for i in range(-2**15, 2**15, 10)] 22 | 23 | val_max = 127 24 | val_min = -128 25 | 26 | dut.data_en_i <= 0 27 | 28 | reset_n = dut.rst_i 29 | 30 | cocotb.fork(Clock(dut.clk_i, 10, 'ns').start()) 31 | yield reset_dut(reset_n, dut.clk_i, 500) 32 | 33 | dut._log.debug("After reset") 34 | yield FallingEdge(dut.clk_i) 35 | yield FallingEdge(dut.clk_i) 36 | 37 | for i in val: 38 | dut.data_en_i <= 1 39 | dut.data_i <= i 40 | yield FallingEdge(dut.clk_i) 41 | dut.data_en_i <= 0 42 | yield FallingEdge(dut.clk_i) 43 | if i < val_min: 44 | res = val_min 45 | elif i > val_max: 46 | res = val_max 47 | else: 48 | res = i 49 | print(f"{i} {res} {int(dut.data_o.value.signed_integer)}") 50 | assert res == int(dut.data_o.value.signed_integer) 51 | dut.data_en_i <= 0 52 | -------------------------------------------------------------------------------- /expanderReal/simulation/top_expanderreal: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/fpga_ip/39826ecea776c999e17a28b686e99c4ad5b7d5f6/expanderReal/simulation/top_expanderreal -------------------------------------------------------------------------------- /fft/order.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/fpga_ip/39826ecea776c999e17a28b686e99c4ad5b7d5f6/fft/order.txt -------------------------------------------------------------------------------- /fft/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | *.dat 3 | result.txt 4 | debug.txt 5 | fft 6 | fft.wdb 7 | fuse.log 8 | fuse.xmsgs 9 | fuseRelaunch.cmd 10 | isim.log 11 | isim 12 | -------------------------------------------------------------------------------- /fft/simulation/fft.prj: -------------------------------------------------------------------------------- 1 | vhdl work ../hdl/fft_ram.vhd 2 | vhdl work ../hdl/fft_ram_coeff.vhd 3 | vhdl work ../hdl/fft_coeff_handler.vhd 4 | vhdl work ../hdl/fft_comp_complex.vhd 5 | vhdl work ../hdl/fft_data_handler.vhd 6 | vhdl work ../hdl/fft_comp_butterfly.vhd 7 | vhdl work ./readComplexFromFile.vhd 8 | vhdl work ./readFromFile.vhd 9 | vhdl work ./ram_storage16.vhd 10 | vhdl work ../hdl/fft_transfert.vhd 11 | vhdl work ../hdl/fft_loop_radix.vhd 12 | vhdl work ../hdl/fft_loop_stage.vhd 13 | vhdl work ../hdl/fft_top_logic.vhd 14 | vhdl work ./top_fft_tb.vhd 15 | -------------------------------------------------------------------------------- /fft/simulation/gen_data/.gitignore: -------------------------------------------------------------------------------- 1 | gen_data 2 | -------------------------------------------------------------------------------- /fft/simulation/gen_data/Makefile: -------------------------------------------------------------------------------- 1 | EXEC_NAME=gen_data 2 | SRC= $(wildcard *.c) 3 | OBJS= $(SRC:.c=.o) 4 | LDFLAGS=-lm -g -Wall 5 | 6 | all:$(EXEC_NAME) 7 | 8 | $(EXEC_NAME):$(OBJS) 9 | $(CC) -o $@ $^ $(LDFLAGS) 10 | 11 | %.o: %.c 12 | $(CC) $(CFLAGS) -o $@ -c $< 13 | 14 | clean: 15 | rm -rf $(OBJS) 16 | rm -f $(EXEC_NAME) 17 | rm -f *.c~ *.h~ Makefile~ 18 | -------------------------------------------------------------------------------- /fft/simulation/gen_data/gen_sin_cos.m: -------------------------------------------------------------------------------- 1 | SIZE=6*pi; 2 | STEP=2048; 3 | a = [0:SIZE/STEP:SIZE]; 4 | aa = cos(a)*(32768/2);%+127+0.5; 5 | bb = sin(a)*(32768/2);%+127+0.5; 6 | cos_val = int32(aa); 7 | sin_val = int32(bb); 8 | res = [cos_val sin_val]; 9 | hold off 10 | plot(cos_val, 'b') 11 | hold on 12 | plot(sin_val, 'r') 13 | %save -text "dds_coeff.dat" res; 14 | %save -text "dds_sin.dat" sin_val; 15 | save -text "data.dat" cos_val; 16 | %save -text "coeff_re.dat" cos_val; 17 | %save -text "coeff_im.dat" sin_val; 18 | 19 | -------------------------------------------------------------------------------- /fft/simulation/ghdl/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_fft 2 | TESTBENCH_FILE=../$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../../hdl/fft_ram.vhd ../../hdl/fft_ram_coeff.vhd \ 10 | ../../hdl/fft_coeff_handler.vhd ../../hdl/fft_comp_complex.vhd \ 11 | ../../hdl/fft_data_handler.vhd ../../hdl/fft_comp_butterfly.vhd \ 12 | ../readComplexFromFile.vhd ../readFromFile.vhd ../ram_storage16.vhd \ 13 | ../../hdl/fft_transfert.vhd\ 14 | ../../hdl/fft_loop_radix.vhd ../../hdl/fft_loop_stage.vhd ../../hdl/fft_top_logic.vhd 15 | 16 | SIMDIR=simu 17 | 18 | VIEW_CMD = gtkwave 19 | 20 | all : run 21 | 22 | # Run target 23 | run:$(SIMDIR)/$(SIMTOP).ghw 24 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 25 | $(GHDL) -c $(GHDLFLAGS) -v -e $(SIMTOP) 26 | $(GHDL) -c $(GHDLFLAGS) -v -r $(SIMTOP) $(GHDLRUNFLAGS) \ 27 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 28 | 29 | # Targets to analyze libraries 30 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 31 | mkdir -p $(SIMDIR) 32 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 33 | 34 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 35 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 36 | 37 | clean: 38 | $(GHDL) --clean --workdir=simu 39 | -rm -rf simu 40 | force: 41 | -------------------------------------------------------------------------------- /fft/simulation/isim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/csh -f 2 | echo Simulation Tool: ISIM 3 | fuse work.top_fft_tb -prj fft.prj -L unisim -L secureip -timeprecision_vhdl fs -o fft 4 | ./fft -gui -tclbatch isim.tcl -wdb fft.wdb 5 | echo done 6 | 7 | -------------------------------------------------------------------------------- /fft/simulation/isim.tcl: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | isim set radix hex 3 | #wave add /sim_tb_top/ 4 | wave add /top_fft_tb 5 | run 60 us 6 | quit 7 | -------------------------------------------------------------------------------- /fft/simulation/plot_comp.m: -------------------------------------------------------------------------------- 1 | a = load("result.txt"); 2 | re = a(:,1);%a([1:127],1); 3 | im = a(:,2);%a([1:127],2); 4 | plot(abs(re + i * im)); 5 | -------------------------------------------------------------------------------- /fft/simulation/testC/.gitignore: -------------------------------------------------------------------------------- 1 | test_fft 2 | *.txt 3 | -------------------------------------------------------------------------------- /fft/simulation/testC/Makefile: -------------------------------------------------------------------------------- 1 | EXEC_NAME=test_fft 2 | SRC= $(wildcard *.c) 3 | OBJS= $(SRC:.c=.o) 4 | HEADERS=fft.h 5 | LDFLAGS=-lm -g -Wall 6 | CFLAGS=$(LDFLAGS) 7 | 8 | all:$(EXEC_NAME) 9 | 10 | $(EXEC_NAME):$(OBJS) 11 | $(CC) -o $@ $^ $(LDFLAGS) 12 | 13 | %.o: %.c $(HEADERS) 14 | $(CC) $(CFLAGS) -o $@ -c $< 15 | 16 | clean: 17 | rm -rf $(OBJS) 18 | rm -f $(EXEC_NAME) 19 | rm -f *.c~ *.h~ Makefile~ 20 | rm -f *.txt *.dat 21 | -------------------------------------------------------------------------------- /fft/simulation/testC/comp_res.m: -------------------------------------------------------------------------------- 1 | input = load("../out_fpga_cordic1.dat"); 2 | %input = load("../gen_data/data.dat"); 3 | resComp = load("result.dat"); 4 | resVhd = load("../result.txt"); 5 | N=2048; 6 | input = input(1:2048); 7 | val_fft=abs(fft(input)); 8 | %val_comp = abs(resComp(:,1)+(i*resComp(:,2))); 9 | %val_vhd = abs(resVhd(:,1)+(i*resVhd(:,2))); 10 | val_comp = sqrt((resComp(:,1).^2) + (resComp(:,2).^2)); 11 | val_vhd = sqrt((resVhd(:,1).^2)+(resVhd(:,2).^2)); 12 | 13 | val_fft=val_fft(2:N/2); 14 | val_comp=val_comp(2:N/2); 15 | val_vhd=val_vhd(2:N/2); 16 | %plot(val_fft, 'r', val_comp, 'g', val_vhd, 'm'); 17 | %plot(val_fft, 'r', val_comp, 'g'); 18 | %plot(10*log10(val_fft), 'r', 10*log10(val_comp), 'g', 10*log10(val_vhd), 'm'); 19 | %plot(10*log10(val_fft), 'r', 10*log10(val_comp), 'g'); 20 | plot(10*log10(val_fft), 'r', 10*log10(val_vhd), 'm'); 21 | %plot(val_comp); 22 | %plot(10*log10(val_fft)-10*log10(val_vhd), 'r', 10*log10(val_fft)-10*log10(val_comp),'g'); 23 | %plot(10*log10(val_fft)-10*log10(val_comp)) 24 | %plot(10*log10(val_fft),'r', 10*log10(val_comp),'g') 25 | %plot(10*log10(val_comp)-10*log10(val_vhd)) 26 | %plot(10*log10(val_comp)) 27 | %plot(abs(abs(val_comp)-abs(val_fft))) 28 | -------------------------------------------------------------------------------- /fft/simulation/testC/fft.h: -------------------------------------------------------------------------------- 1 | #ifndef _FFT_H 2 | #define _FFT_H 3 | 4 | #include 5 | 6 | //#define SCALE_FACTOR 14 7 | //#define SCALE_FACTOR 15 8 | //#define SCALE_FACTOR 16 9 | //#define SCALE_FACTOR 7 10 | 11 | /*#define N_FFT 4096 12 | #define LOG_2_N_FFT 12 13 | */ 14 | 15 | /*#define N_FFT 128 16 | #define LOG_2_N_FFT 7 17 | */ 18 | /*#define N_FFT 2048 19 | #define LOG_2_N_FFT 11 20 | */ 21 | #if 0 22 | #define N_FFT 2048 23 | #define LOG_2_N_FFT 11 24 | 25 | #define N_FFT_DIV_2 (N_FFT/2) 26 | #define N_FFT_DIV_2_PLUS_1 (N_FFT+1) 27 | #define N_FFT_MINUS_1 (N_FFT-1) 28 | #endif 29 | 30 | //void fft_accum(int m_index, int64_t x_re, int64_t x_im); 31 | void fft_compute(int64_t *x_re, int64_t *x_im, 32 | int64_t *out_re, int64_t *out_im, int n_fft, 33 | int64_t * cosLUT, int64_t * sinLUT, int scale_factor, int nb_elem); 34 | void fft_compute_coeff(int64_t *coeffReal, int64_t *coeffImag, 35 | int scaleFactor, int nb_elem); 36 | //int64_t getValRe(int m_index); 37 | //int64_t getValIm(int m_index); 38 | #endif // _FFT_H 39 | -------------------------------------------------------------------------------- /firComplex/hdl/firComplex_ram.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.all; 4 | 5 | entity firComplex_ram is 6 | generic ( 7 | DATA : integer := 72; 8 | ADDR : integer := 10 9 | ); 10 | port ( 11 | clk_a : in std_logic; 12 | clk_b : in std_logic; 13 | -- state machine interface 14 | we_a : in std_logic; 15 | addr_a: in std_logic_vector(ADDR-1 downto 0); 16 | din_a : in std_logic_vector(DATA-1 downto 0); 17 | dout_a : out std_logic_vector(DATA-1 downto 0); 18 | addr_b: in std_logic_vector(ADDR-1 downto 0); 19 | dout_b: out std_logic_vector(DATA-1 downto 0) 20 | ); 21 | end entity; 22 | 23 | architecture rtl of firComplex_ram is 24 | -- Shared memory 25 | type mem_type is array ( (2**ADDR)-1 downto 0 ) of std_logic_vector(DATA-1 downto 0); 26 | signal mem : mem_type := (others => (others => '0')); 27 | attribute ram_style : string; 28 | attribute ram_style of mem : signal is "block"; 29 | begin 30 | 31 | -- Port A 32 | process(clk_a) 33 | begin 34 | if(clk_a'event and clk_a='1') then 35 | if(we_a='1') then 36 | mem(to_integer(unsigned(addr_a))) <= din_a; 37 | end if; 38 | dout_a <= mem(to_integer(unsigned(addr_a))); 39 | end if; 40 | end process; 41 | 42 | -- Port B 43 | process(clk_b) 44 | begin 45 | if(clk_b'event and clk_b='1') then 46 | dout_b <= mem(to_integer(unsigned(addr_b))); 47 | end if; 48 | end process; 49 | 50 | end architecture rtl; 51 | -------------------------------------------------------------------------------- /firComplex/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | result.txt 2 | fir16 3 | *.log 4 | *.xmsgs 5 | *.cmd 6 | *.wdd 7 | *.wcfg 8 | isim 9 | *.wdb 10 | simu 11 | fake_coeff.dat 12 | -------------------------------------------------------------------------------- /firComplex/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_enable 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../hdl/firComplex_ram.vhd ../hdl/firComplex_proc.vhd ../hdl/firComplex_top.vhd 10 | FILES+=ram_storage16.vhd readFromFile.vhd 11 | #FILES=../readFromFile.vhd ../ram_storage16.vhd \ 12 | # ../../hdl/firComplex_dspmanu.vhd \ 13 | # ../../hdl/firComplex_reg_delay.vhd \ 14 | # ../../hdl/firComplex_cpt.vhd \ 15 | # ../../hdl/firComplex_ram.vhd \ 16 | # ../../hdl/firComplex_proc.vhd \ 17 | # ../../hdl/firComplex_global.vhd \ 18 | # ../../hdl/firComplex_ng_top.vhd 19 | SIMDIR=simu 20 | 21 | VIEW_CMD = gtkwave 22 | 23 | all : run 24 | 25 | # Run target 26 | run:$(SIMDIR)/$(SIMTOP).ghw 27 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 28 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 29 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 30 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 31 | 32 | # Targets to analyze libraries 33 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 34 | mkdir -p $(SIMDIR) 35 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 36 | 37 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 38 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 39 | 40 | clean: 41 | -$(GHDL) --clean --workdir=simu 42 | -rm -rf simu 43 | -rm -rf result.txt 44 | force: 45 | -------------------------------------------------------------------------------- /firComplex/simulation/testC/.gitignore: -------------------------------------------------------------------------------- 1 | computeFir 2 | res*.dat 3 | res*.dat 4 | test*.txt 5 | -------------------------------------------------------------------------------- /firComplex/simulation/testC/Makefile: -------------------------------------------------------------------------------- 1 | CFLAGS+=-g -W -Wall 2 | LDFLAGS= 3 | EXEC_NAME=computeFir 4 | OBJS=main.o fir.o 5 | 6 | all: $(EXEC_NAME) 7 | 8 | $(EXEC_NAME): $(OBJS) 9 | $(CC) -o $@ $^ $(LDFLAGS) 10 | 11 | %.o: %.c 12 | $(CC) $(CFLAGS) -o $@ -c $< 13 | 14 | clean: 15 | rm -rf $(OBJS) 16 | rm -f $(EXEC_NAME) 17 | rm -f *.c~ *.h~ Makefile~ 18 | rm -f res*.dat 19 | rm -f test*.txt 20 | rm -f dump*.txt 21 | 22 | .PHONY: clean 23 | 24 | 25 | -------------------------------------------------------------------------------- /firComplex/simulation/testC/fir.h: -------------------------------------------------------------------------------- 1 | #ifndef __FIR_H__ 2 | #define __FIR_H__ 3 | void fir16_In8(short *coeff, int8_t *vali, int8_t *valq, int coeff_size, long data_size, 4 | int decim, int32_t *accumi, int32_t *accumq); 5 | void fir16(short *coeff, short *vali, short *valq, int coeff_size, long data_size, 6 | int decim, int64_t *accumi, int64_t *accumq); 7 | void mixer_square(short *data_input, long data_size, int period, short *vali, short *valq); 8 | #endif /*__FIR_H__*/ 9 | -------------------------------------------------------------------------------- /firReal/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | result.txt 2 | fir16 3 | *.log 4 | *.xmsgs 5 | *.cmd 6 | *.wdd 7 | *.wcfg 8 | isim 9 | *.wdb 10 | simu 11 | -------------------------------------------------------------------------------- /firReal/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_enable 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../hdl/firReal_ram.vhd ../hdl/firReal_proc.vhd ../hdl/firReal_top.vhd 10 | FILES+=ram_storage16.vhd readFromFile.vhd 11 | #FILES=../readFromFile.vhd ../ram_storage16.vhd \ 12 | # ../../hdl/firReal_dspmanu.vhd \ 13 | # ../../hdl/firReal_reg_delay.vhd \ 14 | # ../../hdl/firReal_cpt.vhd \ 15 | # ../../hdl/firReal_ram.vhd \ 16 | # ../../hdl/firReal_proc.vhd \ 17 | # ../../hdl/firReal_global.vhd \ 18 | # ../../hdl/firReal_ng_top.vhd 19 | SIMDIR=simu 20 | 21 | VIEW_CMD = gtkwave 22 | 23 | all : run 24 | 25 | # Run target 26 | run:$(SIMDIR)/$(SIMTOP).ghw 27 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 28 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 29 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 30 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 31 | 32 | # Targets to analyze libraries 33 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 34 | mkdir -p $(SIMDIR) 35 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 36 | 37 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 38 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 39 | 40 | clean: 41 | $(GHDL) --clean --workdir=simu 42 | -rm -rf simu 43 | force: 44 | -------------------------------------------------------------------------------- /firReal/simulation/coeff16.dat: -------------------------------------------------------------------------------- 1 | 0 2 | 0 3 | 0 4 | 0 5 | 0 6 | 0 7 | 0 8 | 0 9 | 0 10 | 0 11 | 0 12 | 0 13 | 0 14 | 0 15 | 12 16 | 43 17 | 85 18 | 140 19 | 208 20 | 293 21 | 397 22 | 521 23 | 669 24 | 841 25 | 1041 26 | 1270 27 | 1532 28 | 1826 29 | 2156 30 | 2524 31 | 2929 32 | 3374 33 | 3859 34 | 4385 35 | 4951 36 | 5557 37 | 6202 38 | 6885 39 | 7603 40 | 8355 41 | 9137 42 | 9946 43 | 10778 44 | 11629 45 | 12494 46 | 13367 47 | 14245 48 | 15120 49 | 15987 50 | 16839 51 | 17671 52 | 18476 53 | 19248 54 | 19981 55 | 20668 56 | 21305 57 | 21886 58 | 22405 59 | 22859 60 | 23244 61 | 23556 62 | 23792 63 | 23951 64 | 24031 65 | 24031 66 | 23951 67 | 23792 68 | 23556 69 | 23244 70 | 22859 71 | 22405 72 | 21886 73 | 21305 74 | 20668 75 | 19981 76 | 19248 77 | 18476 78 | 17671 79 | 16839 80 | 15987 81 | 15120 82 | 14245 83 | 13367 84 | 12494 85 | 11629 86 | 10778 87 | 9946 88 | 9137 89 | 8355 90 | 7603 91 | 6885 92 | 6202 93 | 5557 94 | 4951 95 | 4385 96 | 3859 97 | 3374 98 | 2929 99 | 2524 100 | 2156 101 | 1826 102 | 1532 103 | 1270 104 | 1041 105 | 841 106 | 669 107 | 521 108 | 397 109 | 293 110 | 208 111 | 140 112 | 85 113 | 43 114 | 12 115 | 0 116 | 0 117 | 0 118 | 0 119 | 0 120 | 0 121 | 0 122 | 0 123 | 0 124 | 0 125 | 0 126 | 0 127 | 0 128 | 0 129 | -------------------------------------------------------------------------------- /firReal/simulation/fake_coeff.dat: -------------------------------------------------------------------------------- 1 | 128 2 | 129 3 | 130 4 | 131 5 | 132 6 | 133 7 | 134 8 | 135 9 | 136 10 | 137 11 | 138 12 | 139 13 | 140 14 | 141 15 | 142 16 | 143 17 | 144 18 | 145 19 | 146 20 | 147 21 | 148 22 | 149 23 | 150 24 | 151 25 | 152 26 | 153 27 | 154 28 | 155 29 | 156 30 | 157 31 | 158 32 | 159 33 | 160 34 | 161 35 | 162 36 | 163 37 | 164 38 | 165 39 | 166 40 | 167 41 | 168 42 | 169 43 | 170 44 | 171 45 | 172 46 | 173 47 | 174 48 | 175 49 | 176 50 | 177 51 | 178 52 | 179 53 | 180 54 | 181 55 | 182 56 | 183 57 | 184 58 | 185 59 | 186 60 | 187 61 | 188 62 | 189 63 | 190 64 | 191 65 | 192 66 | 193 67 | 194 68 | 195 69 | 196 70 | 197 71 | 198 72 | 199 73 | 200 74 | 201 75 | 202 76 | 203 77 | 204 78 | 205 79 | 206 80 | 207 81 | 208 82 | 209 83 | 210 84 | 211 85 | 212 86 | 213 87 | 214 88 | 215 89 | 216 90 | 217 91 | 218 92 | 219 93 | 220 94 | 221 95 | 222 96 | 223 97 | 224 98 | 225 99 | 226 100 | 227 101 | 228 102 | 229 103 | 230 104 | 231 105 | 232 106 | 233 107 | 234 108 | 235 109 | 236 110 | 237 111 | 238 112 | 239 113 | 240 114 | 241 115 | 242 116 | 243 117 | 244 118 | 245 119 | 246 120 | 247 121 | 248 122 | 249 123 | 250 124 | 251 125 | 252 126 | 253 127 | 254 128 | 255 129 | -------------------------------------------------------------------------------- /firReal/simulation/testC/.gitignore: -------------------------------------------------------------------------------- 1 | computeFir 2 | res*.dat 3 | res*.dat 4 | test*.txt 5 | -------------------------------------------------------------------------------- /firReal/simulation/testC/Makefile: -------------------------------------------------------------------------------- 1 | CFLAGS+=-g -W -Wall 2 | LDFLAGS= 3 | EXEC_NAME=computeFir 4 | OBJS=main.o fir.o 5 | 6 | all: $(EXEC_NAME) 7 | 8 | $(EXEC_NAME): $(OBJS) 9 | $(CC) -o $@ $^ $(LDFLAGS) 10 | 11 | %.o: %.c 12 | $(CC) $(CFLAGS) -o $@ -c $< 13 | 14 | clean: 15 | rm -rf $(OBJS) 16 | rm -f $(EXEC_NAME) 17 | rm -f *.c~ *.h~ Makefile~ 18 | rm -f res*.dat 19 | rm -f test*.txt 20 | rm -f dump*.txt 21 | 22 | .PHONY: clean 23 | 24 | 25 | -------------------------------------------------------------------------------- /firReal/simulation/testC/fir.h: -------------------------------------------------------------------------------- 1 | #ifndef __FIR_H__ 2 | #define __FIR_H__ 3 | void fir16_In8(short *coeff, int8_t *vali, int8_t *valq, int coeff_size, long data_size, 4 | int decim, int32_t *accumi, int32_t *accumq); 5 | void fir16(short *coeff, short *vali, short *valq, int coeff_size, long data_size, 6 | int decim, int64_t *accumi, int64_t *accumq); 7 | void mixer_square(short *data_input, long data_size, int period, short *vali, short *valq); 8 | #endif /*__FIR_H__*/ 9 | -------------------------------------------------------------------------------- /firReal/simulation/testC/fir.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/fpga_ip/39826ecea776c999e17a28b686e99c4ad5b7d5f6/firReal/simulation/testC/fir.o -------------------------------------------------------------------------------- /firReal/simulation/testC/main.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/fpga_ip/39826ecea776c999e17a28b686e99c4ad5b7d5f6/firReal/simulation/testC/main.o -------------------------------------------------------------------------------- /firReal/simulation/testCConst/.gitignore: -------------------------------------------------------------------------------- 1 | computeFir 2 | res*.dat 3 | res*.dat 4 | test*.txt 5 | -------------------------------------------------------------------------------- /firReal/simulation/testCConst/Makefile: -------------------------------------------------------------------------------- 1 | CFLAGS+=-g -W -Wall 2 | LDFLAGS= 3 | EXEC_NAME=computeFir 4 | OBJS=main.o fir.o 5 | 6 | all: $(EXEC_NAME) 7 | 8 | $(EXEC_NAME): $(OBJS) 9 | $(CC) -o $@ $^ $(LDFLAGS) 10 | 11 | %.o: %.c 12 | $(CC) $(CFLAGS) -o $@ -c $< 13 | 14 | clean: 15 | rm -rf $(OBJS) 16 | rm -f $(EXEC_NAME) 17 | rm -f *.c~ *.h~ Makefile~ 18 | 19 | .PHONY: clean 20 | 21 | 22 | -------------------------------------------------------------------------------- /firReal/simulation/testCConst/fir.h: -------------------------------------------------------------------------------- 1 | #ifndef __FIR_H__ 2 | #define __FIR_H__ 3 | void fir16_In8(short *coeff, int8_t *vali, int8_t *valq, int coeff_size, long data_size, 4 | int decim, int32_t *accumi, int32_t *accumq); 5 | void fir16(short *coeff, short *vali, short *valq, int coeff_size, long data_size, 6 | int decim, int64_t *accumi, int64_t *accumq); 7 | void mixer_square(short *data_input, long data_size, int period, short *vali, short *valq); 8 | #endif /*__FIR_H__*/ 9 | -------------------------------------------------------------------------------- /firReal/simulation/vivado/clean.sh: -------------------------------------------------------------------------------- 1 | rm -f xelab* xsim.* xsim_* xvhdl.* *.log *.jour -r 2 | 3 | -------------------------------------------------------------------------------- /firReal/simulation/vivado/firReal.prj: -------------------------------------------------------------------------------- 1 | vhdl work ../../hdl/firReal_ram.vhd 2 | vhdl work ../../hdl/firReal_proc.vhd 3 | vhdl work ../../hdl/firReal_top.vhd 4 | vhdl work ../ram_storage16.vhd 5 | vhdl work ../readFromFile.vhd 6 | vhdl work ../top_enable_tb.vhd 7 | -------------------------------------------------------------------------------- /firReal/simulation/vivado/firReal_options.tcl: -------------------------------------------------------------------------------- 1 | add_wave -radix hex /top_enable_tb 2 | run 1000 us 3 | -------------------------------------------------------------------------------- /firReal/simulation/vivado/script.sh: -------------------------------------------------------------------------------- 1 | FILES="readComplexFromFile.vhd ../hdl/firReal_ram.vhd" 2 | FILES=$FILES" ../hdl/firReal_ram_coeff.vhd" 3 | FILES=$FILES" ../hdl/firReal_ram.vhd ../hdl/firReal_transfert.vhd" 4 | FILES=$FILES" ../hdl/firReal_coeff_handler.vhd ../hdl/firReal_data_handler.vhd" 5 | FILES=$FILES" ../hdl/firReal_comp_complex.vhd" 6 | FILES=$FILES" ../hdl/firReal_comp_butterfly.vhd ../hdl/firReal_loop_radix.vhd" 7 | 8 | FILES=$FILES" ../hdl/firReal_loop_stage.vhd ../hdl/firReal_top_logic.vhd" 9 | FILES=$FILES" top_firReal_tb.vhd" 10 | 11 | xvhdl $FILES 12 | xelab top_firReal_tb -debug typical -s top_sim 13 | xsim top_sim -gui 14 | #-t xsim_script.tcl 15 | -------------------------------------------------------------------------------- /firReal/simulation/vivado/vivado.sh: -------------------------------------------------------------------------------- 1 | #xvhdl $FILES 2 | xelab top_enable_tb -prj firReal.prj -debug typical -s top_sim 3 | #xsim top_sim -gui 4 | #-t xsim_script.tcl 5 | xsim -g -wdb top_sim.wdb top_sim 6 | 7 | ## juste pour compiler dans une fenetre tcl 8 | #xsim {top_sim} -wdb {top_sim.wdb} -autoloadwcfg 9 | -------------------------------------------------------------------------------- /fpga_ip.mk: -------------------------------------------------------------------------------- 1 | include $(OSCIMP_DIGITAL_IP)/boards.def 2 | 3 | # convert all files in absolute 4 | V_SRC = $(realpath $(V_LIST)) 5 | V_SRC += $(realpath $(V_LIST_$(BOARD_NAME))) 6 | VHDL_SRC = $(realpath $(VHDL_LIST)) 7 | VHDL_SRC += $(realpath $(VHDL_LIST_$(BOARD_NAME))) 8 | REAL_CONSTR = $(realpath $(CONSTR)) 9 | REAL_CONSTR += $(realpath $(CONSTR_$(BOARD_NAME))) 10 | TCL_SRC = $(realpath $(TCL_LIST)) 11 | TCL_SRC += $(realpath $(TCL_LIST_$(BOARD_NAME))) 12 | 13 | # files 14 | SRC = $(V_SRC) $(VHDL_SRC) 15 | 16 | # to generate ipx file with all IPs available 17 | # in all repositories we need to provides a list with ',' 18 | # to ip-make-ipx 19 | IP_REPO += $(OSCIMP_DIGITAL_IP) 20 | IP_TMP = $(shell realpath --relative-to=. $(IP_REPO)) 21 | IP_PATH = $(shell echo $(IP_TMP) | tr ' ' ',') 22 | 23 | INSTALL_DIR = $(OSCIMP_DIGITAL_NFS)/$(BOARD_NAME)/$(PRJ)/bitstreams/ 24 | 25 | -include $(OSCIMP_DIGITAL_IP)/$(TOOLS).mk 26 | 27 | tmp: 28 | mkdir -p $@ 29 | 30 | force_install: 31 | install:$(BIN_FILE) 32 | if [ ! -d $(INSTALL_DIR) ]; then mkdir -p $(INSTALL_DIR); fi 33 | cp $(TARGET_BIN) $(INSTALL_DIR) 34 | 35 | force_install: 36 | if [ ! -d $(INSTALL_DIR) ]; then mkdir -p $(INSTALL_DIR); fi 37 | cp $(TARGET_BIN) $(INSTALL_DIR) 38 | 39 | clean: 40 | @rm -rf tmp 41 | @rm -rf $(CLEAN_FILES) *.$(OUT_BIN) 42 | -------------------------------------------------------------------------------- /gen_radar_prog/gen_radar_prog.xdc: -------------------------------------------------------------------------------- 1 | set_property IOSTANDARD "LVCMOS33" [get_ports "switch_o"] 2 | set_property PACKAGE_PIN "Y11" [get_ports "switch_o"] 3 | set_property PIO_DIRECTION "OUTPUT" [get_ports "switch_o"] 4 | set_property IOSTANDARD "LVCMOS33" [get_ports "switchn_o"] 5 | set_property PACKAGE_PIN "AB11" [get_ports "switchn_o"] 6 | set_property PIO_DIRECTION "OUTPUT" [get_ports "switchn_o"] 7 | -------------------------------------------------------------------------------- /gen_radar_prog/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_enable 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | 10 | FILES=../hdl/gen_radar_prog_logic.vhd 11 | 12 | SIMDIR=simu 13 | 14 | VIEW_CMD = gtkwave 15 | 16 | all : run 17 | 18 | # Run target 19 | run:$(SIMDIR)/$(SIMTOP).ghw 20 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 21 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 22 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 23 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 24 | 25 | # Targets to analyze libraries 26 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 27 | mkdir -p $(SIMDIR) 28 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 29 | 30 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 31 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 32 | 33 | clean: 34 | $(GHDL) --clean --workdir=simu 35 | -rm -rf simu 36 | force: 37 | -------------------------------------------------------------------------------- /gen_radar_prog/simulation/top_enable.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI 3 | [*] Tue Jun 16 14:02:05 2015 4 | [*] 5 | [dumpfile] "/home/gwe/projets/fpga/zynq/gen_radar/simulation/simu/top_enable_tb.ghw" 6 | [dumpfile_mtime] "Tue Jun 16 14:02:02 2015" 7 | [dumpfile_size] 9895063 8 | [savefile] "/home/gwe/projets/fpga/zynq/gen_radar/simulation/top_enable.gtkw" 9 | [timestart] 98811800000 10 | [size] 1366 732 11 | [pos] -1 -1 12 | *-26.677189 305000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] top. 14 | [sst_width] 196 15 | [signals_width] 126 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 204 18 | @29 19 | top.top_enable_tb.adc_clk 20 | @28 21 | top.top_enable_tb.switchn_s 22 | top.top_enable_tb.switch_s 23 | top.top_enable_tb.result2_en_s 24 | top.top_enable_tb.result_eof_s 25 | top.top_enable_tb.result_en_s 26 | top.top_enable_tb.data_en_s 27 | [pattern_trace] 1 28 | [pattern_trace] 0 29 | -------------------------------------------------------------------------------- /iir_lpf_real/hdl/Makefile: -------------------------------------------------------------------------------- 1 | 2 | VHDL_SOURCES= iir_lpf_real.vhd iir_lpf_real_tb.vhd 3 | SIM_BUILD=sim_build 4 | RTL_LIBRARY ?= work 5 | CMD=/usr/bin/ghdl 6 | TOPLEVEL=iir_lpf_real_tb 7 | COCOTB_RESULTS_FILE=results.txt 8 | PLUSARGS=--vcdgz=sim_build/waveform.vcdgz --wave=sim_build/waveform.ghw 9 | SIM_ARGS=--assert-level=error 10 | 11 | all: $(COCOTB_RESULTS_FILE) 12 | 13 | $(SIM_BUILD): 14 | @mkdir -p $(SIM_BUILD) 15 | 16 | analyse: $(VHDL_SOURCES) $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD) 17 | $(foreach SOURCES_VAR, $(filter VHDL_SOURCES_%, $(.VARIABLES)), \ 18 | $(CMD) -i $(GHDL_ARGS) $(COMPILE_ARGS) --workdir=$(SIM_BUILD) --work=$(SOURCES_VAR:VHDL_SOURCES_%=%) $($(SOURCES_VAR)) && ) \ 19 | $(CMD) -i $(GHDL_ARGS) $(COMPILE_ARGS) --workdir=$(SIM_BUILD) --work=$(RTL_LIBRARY) $(VHDL_SOURCES) && \ 20 | $(CMD) -m $(GHDL_ARGS) $(COMPILE_ARGS) --workdir=$(SIM_BUILD) -P$(SIM_BUILD) --work=$(RTL_LIBRARY) $(TOPLEVEL) 21 | 22 | $(COCOTB_RESULTS_FILE): analyse $(CUSTOM_SIM_DEPS) 23 | -@rm -f $(COCOTB_RESULTS_FILE) 24 | 25 | MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \ 26 | $(SIM_CMD_PREFIX) $(CMD) -r $(GHDL_ARGS) --workdir=$(SIM_BUILD) -P$(SIM_BUILD) --work=$(RTL_LIBRARY) $(TOPLEVEL) --vpi=$(shell cocotb-config --lib-name-path vpi ghdl) $(SIM_ARGS) $(PLUSARGS) 27 | 28 | #$(call check_for_results_file) 29 | 30 | clean:: 31 | -@rm -rf $(SIM_BUILD) $(COCOTB_RESULTS_FILE) 32 | 33 | -------------------------------------------------------------------------------- /iir_lpf_real/hdl/run.sh: -------------------------------------------------------------------------------- 1 | PROJECT=iir_lpf_real 2 | 3 | ghdl -c ${PROJECT}.vhd 4 | ghdl -a ${PROJECT}.vhd 5 | ghdl -e ${PROJECT} 6 | 7 | ghdl -c ${PROJECT}_tb.vhd 8 | ghdl -a ${PROJECT}_tb.vhd 9 | ghdl -e ${PROJECT}_tb 10 | ghdl -r ${PROJECT}_tb --assert-level=error --vcd=${PROJECT}_tb.vcd 11 | -------------------------------------------------------------------------------- /iir_lpf_real/iir_lpf_freqz.m: -------------------------------------------------------------------------------- 1 | % octave 4.0.0 2 | % recursive filter 3 | %2^(-N)*z^(-1)/(1-(1-2^(-N)*z^-1)) 4 | clc, clear all, close all 5 | 6 | Fs = 125e+6 7 | figure%, subplot(2,1,1) 8 | c = {} 9 | for N = 10:2:20 10 | B = [2^-N, 0]; 11 | A= [-(1-2^(-N)), 1]; 12 | fp = -Fs*log(1-2^(-N))/(2*pi) 13 | wn = logspace(0,5,100)*pi/Fs; 14 | [H,W]=freqz(B,A,wn); 15 | hold on 16 | hl = semilogx(Fs*W/(2*pi),20*log10(abs(H))); 17 | c = [c,sprintf("N= %d",N)]; 18 | end 19 | hg = legend(c); 20 | grid on 21 | set([gca;hg;hl],'linewidth',2); 22 | set(gca,'fontsize',26); 23 | xlabel('frequency [Hz]'); 24 | ylabel('TF magnitude[dB]'); 25 | title("IIR lowpass filter, H(z) = 2^{-N}z^{-1}/(1-(1-2^{-N})z^{-1})","interpreter","tex") 26 | -------------------------------------------------------------------------------- /interfaces/complex_v1_0/complex.xml: -------------------------------------------------------------------------------- 1 | 2 | 5 | xilinx.com 6 | interface 7 | complex 8 | 1.0 9 | true 10 | false 11 | 1 12 | 1024 13 | Complex Interface 14 | 15 | -------------------------------------------------------------------------------- /interfaces/real_v1_0/real.xml: -------------------------------------------------------------------------------- 1 | 2 | 5 | xilinx.com 6 | interface 7 | real 8 | 1.0 9 | true 10 | false 11 | 1 12 | 1 13 | Real Interface 14 | 15 | -------------------------------------------------------------------------------- /ltc2145/ltc2145.tcl: -------------------------------------------------------------------------------- 1 | create_bd_port -dir I -from 13 -to 0 adc_data_a_i_0 2 | create_bd_port -dir I -from 13 -to 0 adc_data_b_i_0 3 | 4 | create_bd_port -dir O adc_cdcs_0 5 | -------------------------------------------------------------------------------- /ltc2145/ltc2145.xdc: -------------------------------------------------------------------------------- 1 | #create_clock -period 8.000 -name ltc2145_clk [get_ports adc_clk_i] 2 | 3 | #set_input_delay -clock ltc2145_clk 3.400 [get_ports adc_data_a_i[*]] 4 | #set_input_delay -clock ltc2145_clk 3.400 [get_ports adc_data_b_i[*]] 5 | 6 | -------------------------------------------------------------------------------- /ltc2145/xgui/ltc2145_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | #Adding Page 4 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 5 | ipgui::add_param $IPINST -name "Component_Name" -parent ${Page_0} 6 | ipgui::add_param $IPINST -name "CLOCK_DUTY_CYCLE_STABILIZER_EN" -parent ${Page_0} 7 | 8 | 9 | } 10 | 11 | proc update_PARAM_VALUE.CLOCK_DUTY_CYCLE_STABILIZER_EN { PARAM_VALUE.CLOCK_DUTY_CYCLE_STABILIZER_EN } { 12 | # Procedure called to update CLOCK_DUTY_CYCLE_STABILIZER_EN when any of the dependent parameters in the arguments change 13 | } 14 | 15 | proc validate_PARAM_VALUE.CLOCK_DUTY_CYCLE_STABILIZER_EN { PARAM_VALUE.CLOCK_DUTY_CYCLE_STABILIZER_EN } { 16 | # Procedure called to validate CLOCK_DUTY_CYCLE_STABILIZER_EN 17 | return true 18 | } 19 | 20 | 21 | proc update_MODELPARAM_VALUE.CLOCK_DUTY_CYCLE_STABILIZER_EN { MODELPARAM_VALUE.CLOCK_DUTY_CYCLE_STABILIZER_EN PARAM_VALUE.CLOCK_DUTY_CYCLE_STABILIZER_EN } { 22 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 23 | set_property value [get_property value ${PARAM_VALUE.CLOCK_DUTY_CYCLE_STABILIZER_EN}] ${MODELPARAM_VALUE.CLOCK_DUTY_CYCLE_STABILIZER_EN} 24 | } 25 | 26 | -------------------------------------------------------------------------------- /lutGeneratorComplex/lutGeneratorComplex.xdc: -------------------------------------------------------------------------------- 1 | set_property ASYNC_REG TRUE \ 2 | [get_cells -hier flipflops*_reg[0]] \ 3 | [get_cells -hier flipflops*_reg[1]] 4 | set_false_path \ 5 | -from [get_cells -hier sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ 6 | -to [get_cells -hier flipflops*_reg[0] -filter {IS_SEQUENTIAL}] 7 | 8 | set_property ASYNC_REG TRUE \ 9 | [get_cells -hier flipflops_vect*_reg[0][*]] \ 10 | [get_cells -hier flipflops_vect*_reg[1][*]] 11 | set_false_path \ 12 | -from [get_cells -hier sync_vect_stage0_*_reg[*] -filter {IS_SEQUENTIAL}] \ 13 | -to [get_cells -hier flipflops_vect*_reg[0][*] -filter {IS_SEQUENTIAL}] 14 | -------------------------------------------------------------------------------- /lutGeneratorComplex/output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/fpga_ip/39826ecea776c999e17a28b686e99c4ad5b7d5f6/lutGeneratorComplex/output.png -------------------------------------------------------------------------------- /lutGeneratorComplex/run.sh: -------------------------------------------------------------------------------- 1 | FILES="./hdl/lutGeneratorComplex_storage.vhd ./hdl/lutGeneratorComplex_logic.vhd" 2 | TOP="lutGeneratorComplex_logic" 3 | OPTS="--std=08 --no-formal -frelaxed" 4 | OPTS="$OPTS -gPRESC_SIZE=12 -gDATA_SIZE=16 -gADDR_SIZE=10" 5 | ghdl --synth --out=verilog $OPTS $FILES -e $TOP >> output.v 6 | 7 | yosys -p "prep -top $TOP; write_json output.json" output.v 8 | $HOME/misc/repo/netlistsvg/node_modules/netlistsvg/bin/netlistsvg.js output.json -o output.svg 9 | -------------------------------------------------------------------------------- /lutGeneratorComplex/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM = ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | PLUSARGS=--vcdgz=$(WPWD)/sim_build/waveform.vcdgz --wave=$(WPWD)/sim_build/waveform.ghw 7 | 8 | VHDL_SOURCES = $(WPWD)/../hdl/lutGeneratorComplex_logic.vhd 9 | VHDL_SOURCES += $(WPWD)/../hdl/lutGeneratorComplex_storage.vhd 10 | 11 | VHDL_SOURCES+=$(WPWD)/top_dut.vhd 12 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 13 | TOPLEVEL=top_dut 14 | # MODULE is the name of the Python test file: 15 | MODULE=top_tb 16 | include $(shell cocotb-config --makefiles)/Makefile.sim 17 | 18 | view: 19 | gtkwave -a top_lutGeneratorComplex.gtkw sim_build/waveform.ghw 20 | -------------------------------------------------------------------------------- /lutGeneratorComplex/simulation/top_dut.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.ALL; 4 | 5 | entity top_dut is 6 | port ( 7 | clk_i : in std_logic; 8 | rst_i : in std_logic; 9 | -- cfg 10 | prescaler_i : in std_logic_vector(11 downto 0); 11 | enable_i : in std_logic; 12 | ram_length_i : in std_logic_vector(9 downto 0); 13 | -- lut 14 | data_en_i : in std_logic; 15 | data_i_i : in std_logic_vector(15 downto 0); 16 | data_q_i : in std_logic_vector(15 downto 0); 17 | data_adr_i : in std_logic_vector( 9 downto 0); 18 | -- out 19 | data_i_o : out std_logic_vector(15 downto 0); 20 | data_q_o : out std_logic_vector(15 downto 0); 21 | data_en_o : out std_logic 22 | ); 23 | end top_dut; 24 | 25 | architecture Behavioral of top_dut is 26 | begin 27 | dut : entity work.lutGeneratorComplex_logic 28 | generic map ( 29 | PRESC_SIZE => 12, 30 | ADDR_SIZE => 10, 31 | DATA_SIZE => 16 32 | ) 33 | port map ( 34 | cpu_clk => clk_i, clk => clk_i, reset => rst_i, 35 | data_i_i => data_i_i, data_en_i_i => data_en_i, data_adr_i_i => data_adr_i, 36 | data_q_i => data_q_i, data_en_q_i => data_en_i, data_adr_q_i => data_adr_i, 37 | prescaler_i => prescaler_i, enable_i => enable_i, ram_length_i => ram_length_i, 38 | data_i_o => data_i_o, data_q_o => data_q_o, data_en_o => data_en_o, 39 | data_eof_o => open 40 | ); 41 | 42 | end Behavioral; 43 | -------------------------------------------------------------------------------- /magnitude/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= verilog 2 | 3 | PWD=$(shell pwd) 4 | WPWD=$(shell pwd) 5 | 6 | VERILOG_SOURCES = $(WPWD)/../hdl/magnitude.v 7 | 8 | VERILOG_SOURCES+=$(WPWD)/top_dut.v 9 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 10 | TOPLEVEL=top_dut 11 | # MODULE is the name of the Python test file: 12 | MODULE=top_magnitude_simu_tb 13 | include $(shell cocotb-config --makefiles)/Makefile.sim 14 | 15 | view: 16 | gtkwave -a top_magnitude_simu.gtkw magnitude_simu_tb.vcd 17 | -------------------------------------------------------------------------------- /magnitude/simulation/top_dut.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 100ps 2 | 3 | module top_dut ( 4 | input clk_i, 5 | input rst_i, 6 | input [9:0] data_i_i, 7 | input [9:0] data_q_i, 8 | input data_en_i, 9 | output [20:0] data_uns_o, 10 | output data_uns_en_o, 11 | output [20:0] data_sign_o, 12 | output data_sign_en_o 13 | ); 14 | magnitude #(.SIGN_CORRECTION(0), .DATA_SIZE(10) 15 | ) magnitude_uns ( 16 | .data_clk_i(clk_i), .data_rst_i(rst_i), 17 | .data_i_i(data_i_i), .data_q_i(data_q_i), .data_en_i(data_en_i), 18 | .data_eof_i(1'b0), .data_sof_i(1'b0), 19 | .data_o(data_uns_o), .data_en_o(data_uns_en_o), .data_eof_o(), .data_sof_o() 20 | ); 21 | 22 | magnitude #(.SIGN_CORRECTION(1), .DATA_SIZE(10) 23 | ) magnitude_sign ( 24 | .data_clk_i(clk_i), .data_rst_i(rst_i), 25 | .data_i_i(data_i_i), .data_q_i(data_q_i), .data_en_i(data_en_i), 26 | .data_eof_i(1'b0), .data_sof_i(1'b0), 27 | .data_o(data_sign_o), .data_en_o(data_sign_en_o), .data_eof_o(), .data_sof_o() 28 | ); 29 | 30 | `ifdef COCOTB_SIM 31 | initial begin 32 | $dumpfile("magnitude_simu_tb.vcd"); 33 | $dumpvars(0, top_dut); 34 | #1; 35 | end 36 | `endif 37 | endmodule 38 | 39 | -------------------------------------------------------------------------------- /meanComplex/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | -------------------------------------------------------------------------------- /meanReal/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | -------------------------------------------------------------------------------- /meanReal/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_meanReal 2 | SIMTOP =$(PROJECT)_tb 3 | TESTBENCH_FILE=$(SIMTOP).vhd 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../hdl/meanReal.vhd 10 | SIMDIR=simu 11 | 12 | VIEW_CMD = gtkwave 13 | 14 | all : run 15 | 16 | # Run target 17 | run:$(SIMDIR)/$(SIMTOP).ghw 18 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 19 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 20 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 21 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 22 | 23 | # Targets to analyze libraries 24 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 25 | mkdir -p $(SIMDIR) 26 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 27 | 28 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 29 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 30 | 31 | clean: 32 | $(GHDL) --clean --workdir=simu 33 | -rm -rf simu 34 | force: 35 | 36 | -------------------------------------------------------------------------------- /mean_vector_axi/hdl/mean_vector_axi_shift.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- 2013-2019 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | use IEEE.numeric_std.ALL; 9 | 10 | entity mean_vector_axi_shift is 11 | generic ( 12 | SHIFT_SIZE : natural := 10; 13 | DATA_I_SIZE: natural := 32; 14 | DATA_O_SIZE : natural := 34 15 | ); 16 | port ( 17 | shift_i : in std_logic_vector(SHIFT_SIZE-1 downto 0); 18 | data_i : in std_logic_vector(DATA_I_SIZE-1 downto 0); 19 | data_o : out std_logic_vector(DATA_O_SIZE-1 downto 0) 20 | ); 21 | end mean_vector_axi_shift; 22 | 23 | architecture Behavioral of mean_vector_axi_shift is 24 | constant MUX_SZ : natural := 2**SHIFT_SIZE; 25 | type mux_array is array (natural range 0 to MUX_SZ-1) of 26 | std_logic_vector(DATA_O_SIZE-1 downto 0); 27 | --std_logic_vector(data_o'range); 28 | signal array_val: mux_array; 29 | begin 30 | 31 | t : for i in 0 to MUX_SZ-1 generate 32 | array_val(i) <= data_i(DATA_O_SIZE+i-1 downto i); 33 | end generate t; 34 | 35 | data_o <= array_val(to_integer(unsigned(shift_i))); 36 | 37 | end architecture Behavioral; 38 | -------------------------------------------------------------------------------- /mean_vector_axi/hdl/mva_synchronizer_vector.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- 2013-2019 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity mva_synchronizer_vector is 10 | generic (stages : natural := 3; 11 | DATA : natural := 16); 12 | port (clk_i : in std_logic; 13 | bit_i : in std_logic_vector(DATA-1 downto 0); 14 | bit_o : out std_logic_vector(DATA-1 downto 0) 15 | ); 16 | end entity mva_synchronizer_vector; 17 | 18 | architecture bhv of mva_synchronizer_vector is 19 | type data_tab is array (natural range <>) of std_logic_vector(DATA-1 downto 0); 20 | signal flipflops : data_tab(stages -1 downto 0) := 21 | (others => (others => '0')); 22 | attribute ASYNC_REG : string; 23 | attribute ASYNC_REG of flipflops: signal is "true"; 24 | begin 25 | bit_o <= flipflops(stages-1); 26 | 27 | sync_proc: process(clk_i) 28 | begin 29 | if rising_edge(clk_i) then 30 | flipflops <= flipflops(stages-2 downto 0) & bit_i; 31 | end if; 32 | end process; 33 | end bhv; 34 | -------------------------------------------------------------------------------- /mean_vector_axi/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_mean_vector 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../hdl/mean_vector_axi_ram.vhd 10 | FILES+=../hdl/mean_vector_axi_shift.vhd 11 | FILES+=../hdl/mva_synchronizer_vector.vhd 12 | FILES+=../hdl/mean_vector_axi_logic.vhd 13 | 14 | SIMDIR=simu 15 | 16 | VIEW_CMD = gtkwave 17 | 18 | all : run 19 | 20 | # Run target 21 | run:$(SIMDIR)/$(SIMTOP).ghw 22 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 23 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 24 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 25 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 26 | 27 | # Targets to analyze libraries 28 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 29 | mkdir -p $(SIMDIR) 30 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 31 | 32 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 33 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 34 | 35 | clean: 36 | $(GHDL) --clean --workdir=simu 37 | -rm -rf simu 38 | force: 39 | -------------------------------------------------------------------------------- /mixerComplex_sin/simuC/Makefile: -------------------------------------------------------------------------------- 1 | CFLAGS+=-g -W -Wall 2 | LDFLAGS=-lm 3 | EXEC_NAME=computeWindow 4 | OBJS=main.o 5 | 6 | all: $(EXEC_NAME) 7 | 8 | $(EXEC_NAME): $(OBJS) 9 | $(CC) -o $@ $^ $(LDFLAGS) 10 | 11 | %.o: %.c 12 | $(CC) $(CFLAGS) -o $@ -c $< 13 | 14 | clean: 15 | rm -rf $(OBJS) 16 | rm -f $(EXEC_NAME) 17 | rm -f *.c~ *.h~ Makefile~ 18 | rm -f res*.dat 19 | rm -f test*.txt 20 | 21 | .PHONY: clean 22 | 23 | 24 | -------------------------------------------------------------------------------- /mixerComplex_sin/simuC/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | 7 | int main(void) 8 | { 9 | int data_size = 16; 10 | int nco_size = 16; 11 | int mult_size = data_size + nco_size; 12 | int shift = mult_size - data_size; 13 | 14 | int nco_i = 32767; 15 | int nco_q = -32768; 16 | 17 | int data_i = 1; 18 | int data_q = 10; 19 | 20 | int result_i = 0; 21 | int result_q = 0; 22 | 23 | int i; 24 | for (i=0; i < 10; i++) { 25 | printf("%d : ", i); 26 | printf("\t%d %d\n", data_i * nco_i, data_q * nco_q); 27 | printf("\t%d %d\n", data_q * nco_i, data_i * nco_q); 28 | result_i = data_i * nco_i - data_q * nco_q; 29 | result_q = data_i * nco_q + data_q * nco_i; 30 | printf("\t%d %d %d(%d) %d(%d)\n", data_i, data_q, 31 | result_i >> shift, result_i, result_q >> shift, result_q); 32 | 33 | data_q = data_i + 10; 34 | data_i = data_i + 1; 35 | } 36 | 37 | return EXIT_SUCCESS; 38 | } 39 | -------------------------------------------------------------------------------- /mixerComplex_sin/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM = ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | PLUSARGS=--vcdgz=$(WPWD)/build/waveform.vcdgz --wave=$(WPWD)/build/waveform.ghw 7 | 8 | VHDL_SOURCES=$(WPWD)/../hdl/mixerComplex_sin.vhd $(WPWD)/../hdl/mixerComplex_redim.vhd 9 | 10 | VHDL_SOURCES+=$(WPWD)/top_mixerComplex_sin.vhd 11 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 12 | TOPLEVEL=top_shiftercomplex 13 | # MODULE is the name of the Python test file: 14 | MODULE=top_mixerComplex_sin_tb 15 | include $(shell cocotb-config --makefiles)/Makefile.inc 16 | include $(shell cocotb-config --makefiles)/Makefile.sim 17 | 18 | ghdl_view: 19 | gtkwave -a top_mixerComplex_sin.gtkw build/waveform.ghw 20 | -------------------------------------------------------------------------------- /mixer_sin/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM = ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | PLUSARGS=--vcdgz=$(WPWD)/build/waveform.vcdgz --wave=$(WPWD)/build/waveform.ghw 7 | 8 | VHDL_SOURCES=$(WPWD)/../hdl/mixer_sin.vhd $(WPWD)/../hdl/mixer_redim.vhd 9 | 10 | VHDL_SOURCES+=$(WPWD)/top_mixer_sin.vhd 11 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 12 | TOPLEVEL=top_shiftercomplex 13 | # MODULE is the name of the Python test file: 14 | MODULE=top_mixer_sin_tb 15 | include $(shell cocotb-config --makefiles)/Makefile.inc 16 | include $(shell cocotb-config --makefiles)/Makefile.sim 17 | 18 | ghdl_view: 19 | gtkwave -a top_mixer_sin.gtkw build/waveform.ghw 20 | -------------------------------------------------------------------------------- /multiplierReal/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM = ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | PLUSARGS=--vcdgz=$(WPWD)/build/waveform.vcdgz --wave=$(WPWD)/build/waveform.ghw 7 | 8 | VHDL_SOURCES=$(WPWD)/../hdl/multiplierReal.vhd $(WPWD)/../hdl/multiplierReal_redim.vhd 9 | 10 | VHDL_SOURCES+=$(WPWD)/top_multiplierReal.vhd 11 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 12 | TOPLEVEL=top_multiplierreal 13 | # MODULE is the name of the Python test file: 14 | MODULE=top_multiplierReal_tb 15 | include $(shell cocotb-config --makefiles)/Makefile.inc 16 | include $(shell cocotb-config --makefiles)/Makefile.sim 17 | 18 | view: 19 | gtkwave -a top_multiplierReal.gtkw build/waveform.ghw 20 | -------------------------------------------------------------------------------- /nco_counter/gen_rom/.gitignore: -------------------------------------------------------------------------------- 1 | gen_rom 2 | *.dat 3 | cos_rom*.vhd 4 | -------------------------------------------------------------------------------- /nco_counter/gen_rom/Makefile: -------------------------------------------------------------------------------- 1 | CFLAGS+=-g -W -Wall 2 | LDFLAGS=-lm 3 | EXEC_NAME=gen_rom 4 | OBJS=main.o 5 | 6 | all: $(EXEC_NAME) 7 | 8 | $(EXEC_NAME): $(OBJS) 9 | $(CC) -o $@ $^ $(LDFLAGS) 10 | 11 | %.o: %.c 12 | $(CC) $(CFLAGS) -o $@ -c $< 13 | 14 | clean: 15 | rm -rf $(OBJS) 16 | rm -f $(EXEC_NAME) 17 | rm -f *.c~ *.h~ Makefile~ 18 | 19 | .PHONY: clean 20 | 21 | 22 | -------------------------------------------------------------------------------- /nco_counter/gen_rom/gen_sin_cos.m: -------------------------------------------------------------------------------- 1 | addr= 2^12 2 | a = [0:2*pi/addr:2*pi]; 3 | aa = cos(a)*(((2^(16-1))-1)/2);%+127+0.5; 4 | bb = sin(a)*((2^(16-1))/2)-1;%+127+0.5; 5 | cos_val = int32(aa); 6 | sin_val = int32(bb); 7 | res = [cos_val sin_val]; 8 | plot(cos_val, 'b') 9 | hold on 10 | plot(sin_val, 'r') 11 | %save -text "dds_coeff.dat" res; 12 | %save -text "dds_sin.dat" sin_val; 13 | save -text "dds_cos.dat" cos_val; 14 | 15 | -------------------------------------------------------------------------------- /nco_counter/hdl/nco_counter_cos_rom_a24_d16.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/fpga_ip/39826ecea776c999e17a28b686e99c4ad5b7d5f6/nco_counter/hdl/nco_counter_cos_rom_a24_d16.vhd -------------------------------------------------------------------------------- /nco_counter/hdl/nco_counter_synchronizer_bit.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2015/04/08 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity nco_counter_synchronizer_bit is 10 | generic (stages : natural := 3); 11 | port ( 12 | ref_clk_i : in std_logic; 13 | clk_i : in std_logic; 14 | bit_i : in std_logic; 15 | bit_o : out std_logic 16 | ); 17 | end entity nco_counter_synchronizer_bit; 18 | 19 | architecture bhv of nco_counter_synchronizer_bit is 20 | signal sync_stage0_s: std_logic; 21 | signal flipflops : std_logic_vector(stages -1 downto 0) := (others => '0'); 22 | attribute ASYNC_REG : string; 23 | attribute ASYNC_REG of flipflops: signal is "true"; 24 | begin 25 | ref_proc: process(ref_clk_i) begin 26 | if rising_edge(ref_clk_i) then 27 | sync_stage0_s <= bit_i; 28 | end if; 29 | end process; 30 | 31 | sync_proc: process(clk_i) 32 | begin 33 | if rising_edge(clk_i) then 34 | flipflops(0) <= sync_stage0_s; 35 | flipflops(stages-1 downto 1) 36 | <= flipflops(stages-2 downto 0); 37 | end if; 38 | end process; 39 | bit_o <= flipflops(stages-1); 40 | end bhv; 41 | -------------------------------------------------------------------------------- /nco_counter/nco_counter.xdc: -------------------------------------------------------------------------------- 1 | set_property ASYNC_REG TRUE \ 2 | [get_cells -hier flipflops*_reg[0]] \ 3 | [get_cells -hier flipflops*_reg[1]] 4 | set_false_path \ 5 | -from [get_cells -hier sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ 6 | -to [get_cells -hier flipflops*_reg[0] -filter {IS_SEQUENTIAL}] 7 | 8 | set_property ASYNC_REG TRUE \ 9 | [get_cells -hier flipflops_vect*_reg[0][*]] \ 10 | [get_cells -hier flipflops_vect*_reg[1][*]] 11 | set_false_path \ 12 | -from [get_cells -hier sync_vect_stage0_*_reg[*] -filter {IS_SEQUENTIAL}] \ 13 | -to [get_cells -hier flipflops_vect*_reg[0][*] -filter {IS_SEQUENTIAL}] 14 | -------------------------------------------------------------------------------- /nco_counter/octave/demo.m: -------------------------------------------------------------------------------- 1 | cpt_bit=32; 2 | freq_in=250e6; 3 | freq_out=10e6; 4 | 5 | % phase accum 6 | freq_step=freq_in/2^cpt_bit; 7 | incr=freq_out/freq_step; 8 | inc_int=int32(incr); 9 | 10 | % LUT 11 | addr= 2^12; 12 | a = [0:2*pi/addr:2*pi]; 13 | aa = cos(a)*((2^16-1)/2)-1; 14 | cos_val = int32(aa); 15 | 16 | clf; 17 | plot(aa, 'g'); 18 | hold on; 19 | plot(cos_val); 20 | 21 | step_int=int32([0:inc_int:2^32]./2^(cpt_bit-12)).+1; 22 | step=[0:incr:2^32]./2^(cpt_bit-12).+1; 23 | plot(step_int, cos_val(step_int),'r+'); 24 | plot(step, aa(int32(step)),'g+'); 25 | %plot([step step], [ones(1,length(step))*max(aa)' ones(1,length(step))*min(aa)'],'g'); 26 | hold off; 27 | 28 | plot(cos_val(1:int32(step):end), 'r', cos_val.+10, 'b') 29 | 30 | 31 | % LUT 32 | addr= 2^12; 33 | b = [0:2*pi/addr:2*pi*25]; 34 | bb = cos(b)*((2^16-1)/2)-1; 35 | cos_val_b = int32(bb); 36 | -------------------------------------------------------------------------------- /nco_counter/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | *.txt 2 | simu 3 | -------------------------------------------------------------------------------- /nco_counter/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_nco_counter 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDL_VERSION=$(shell ghdl --version |grep "code generator"|cut -d' ' -f2) 7 | ifeq ($(GHDL_VERSION),mcode) 8 | RUN_CMD=$(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) 9 | else ifeq ($(GHDL_VERSION),GCC) 10 | RUN_CMD=./$(SIMTOP) $(GHDLRUNFLAGS) 11 | endif 12 | GHDLFLAGS=--workdir=simu --work=work 13 | GHDLRUNFLAGS=--assert-level=error 14 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 15 | FILES=../hdl/nco_counter_cos_rom.vhd \ 16 | ../hdl/nco_counter_cos_rom_a12_d16.vhd \ 17 | ../hdl/nco_counter_cos_rom_a16_d16.vhd \ 18 | ../hdl/nco_counter_logic.vhd 19 | SIMDIR=simu 20 | 21 | VIEW_CMD = gtkwave 22 | 23 | all : run 24 | 25 | # Run target 26 | run:$(SIMDIR)/$(SIMTOP).ghw 27 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 28 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 29 | $(RUN_CMD) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 30 | 31 | # Targets to analyze libraries 32 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 33 | mkdir -p $(SIMDIR) 34 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 35 | 36 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 37 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 38 | 39 | clean: 40 | -$(GHDL) --clean --workdir=simu 41 | -rm -rf simu 42 | -rm -f *.txt 43 | force: 44 | -------------------------------------------------------------------------------- /nco_counter/simulation/plot_fft.m: -------------------------------------------------------------------------------- 1 | fs1=250e6; 2 | N=2048; 3 | f1=fs1*(0:N/2-1)/N; 4 | 5 | freq_out=10e6; 6 | addr=2^11; 7 | cos_fake = cos([0:2*pi/addr:2*pi]); 8 | cos_fake = cos_fake(1:N); 9 | 10 | a = load("result.txt"); 11 | im_val = a(:,1)(1:N); 12 | re_val = a(:,2)(1:N); 13 | rfs = cos_fake' .*im_val; 14 | ifs = cos_fake' .*re_val; 15 | plop = re_val + i * im_val; 16 | %plop=re_val .* re_val .+ im_val .* im_val; 17 | plot(f1, 10*log10(abs(fft(plop)(1:N/2)))) 18 | plop=rfs .* rfs .+ ifs .* ifs; 19 | plop = rfs + i * ifs; 20 | plot(f1, 10*log10(abs(fft(plop)(1:N/2)))) 21 | -------------------------------------------------------------------------------- /nco_counter/simulation/plot_freq.m: -------------------------------------------------------------------------------- 1 | F=125e6; 2 | load("result.txt"); 3 | q1=result(:,1);%(50:end); 4 | i1=result(:,2);%(50:end); 5 | l=i1 + i * q1; 6 | N=length(i1); 7 | fs=(([1:1:N]*F)/N)(1:N/2); 8 | ff1 = 10*log10(abs(fft(l))); 9 | 10 | load("result2.txt"); 11 | q2=result(:,1);%(50:end); 12 | i2=result(:,2);%(50:end); 13 | l2=i2 + i * q2; 14 | N=length(i2); 15 | fs=(([1:1:N]*F)/N)(1:N/2); 16 | ff2 = 10*log10(abs(fft(l2))); 17 | 18 | %plot(fs, ff1(1:N/2), fs, ff2(1:N/2)); 19 | plot(q1, 'r', i1, 'g', q2, 'b', i2, 'k'); 20 | 21 | -------------------------------------------------------------------------------- /pidv3_axi/hdl/pidv3_axi_sync_bit.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2015/04/08 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity pidv3_axi_sync_bit is 10 | generic (stages : natural := 3); 11 | port ( 12 | ref_clk_i : in std_logic; 13 | clk_i : in std_logic; 14 | bit_i : in std_logic; 15 | bit_o : out std_logic 16 | ); 17 | end entity pidv3_axi_sync_bit; 18 | 19 | architecture bhv of pidv3_axi_sync_bit is 20 | signal sync_stage0_s: std_logic; 21 | signal flipflops : std_logic_vector(stages -1 downto 0) := (others => '0'); 22 | attribute ASYNC_REG : string; 23 | attribute ASYNC_REG of flipflops: signal is "true"; 24 | begin 25 | ref_proc: process(ref_clk_i) begin 26 | if rising_edge(ref_clk_i) then 27 | sync_stage0_s <= bit_i; 28 | end if; 29 | end process; 30 | 31 | sync_proc: process(clk_i) 32 | begin 33 | if rising_edge(clk_i) then 34 | flipflops(0) <= sync_stage0_s; 35 | flipflops(stages-1 downto 1) 36 | <= flipflops(stages-2 downto 0); 37 | end if; 38 | end process; 39 | bit_o <= flipflops(stages-1); 40 | end bhv; 41 | -------------------------------------------------------------------------------- /pidv3_axi/hdl/pidv3_axi_sync_vector.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2016/05/25 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity pidv3_axi_sync_vector is 10 | generic (stages : natural := 3; 11 | DATA : natural := 16); 12 | port ( 13 | ref_clk_i : in std_logic; 14 | clk_i : in std_logic; 15 | bit_i : in std_logic_vector(DATA-1 downto 0); 16 | bit_o : out std_logic_vector(DATA-1 downto 0) 17 | ); 18 | end entity pidv3_axi_sync_vector; 19 | 20 | architecture bhv of pidv3_axi_sync_vector is 21 | signal sync_vect_stage0_s: std_logic_vector(DATA-1 downto 0); 22 | type data_tab is array (natural range <>) of std_logic_vector(DATA-1 downto 0); 23 | signal flipflops_vect : data_tab(stages -1 downto 0) := (others => (others => '0')); 24 | attribute ASYNC_REG : string; 25 | attribute ASYNC_REG of flipflops_vect: signal is "true"; 26 | begin 27 | ref_proc: process(ref_clk_i) begin 28 | if rising_edge(ref_clk_i) then 29 | sync_vect_stage0_s <= bit_i; 30 | end if; 31 | end process; 32 | 33 | sync_proc: process(clk_i) 34 | begin 35 | if rising_edge(clk_i) then 36 | flipflops_vect(0) <= sync_vect_stage0_s; 37 | flipflops_vect(stages-1 downto 1) 38 | <= flipflops_vect(stages-2 downto 0); 39 | end if; 40 | end process; 41 | bit_o <= flipflops_vect(stages-1); 42 | end bhv; 43 | -------------------------------------------------------------------------------- /pidv3_axi/pidv3_axi.xdc: -------------------------------------------------------------------------------- 1 | set_property ASYNC_REG TRUE \ 2 | [get_cells -hier flipflops*_reg[0]] \ 3 | [get_cells -hier flipflops*_reg[1]] 4 | set_false_path \ 5 | -from [get_cells -hier sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ 6 | -to [get_cells -hier flipflops*_reg[0] -filter {IS_SEQUENTIAL}] 7 | 8 | set_property ASYNC_REG TRUE \ 9 | [get_cells -hier flipflops_vect*_reg[0][*]] \ 10 | [get_cells -hier flipflops_vect*_reg[1][*]] 11 | set_false_path \ 12 | -from [get_cells -hier sync_vect_stage0_*_reg[*] -filter {IS_SEQUENTIAL}] \ 13 | -to [get_cells -hier flipflops_vect*_reg[0][*] -filter {IS_SEQUENTIAL}] 14 | -------------------------------------------------------------------------------- /prn20b/hdl/prn20b_bitSync.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2018/06/11 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity prn20b_bitSync is 10 | generic (stages : natural := 3); 11 | port (clk_i : in std_logic; 12 | bit_i : in std_logic; 13 | bit_o : out std_logic 14 | ); 15 | end entity prn20b_bitSync; 16 | 17 | architecture bhv of prn20b_bitSync is 18 | signal flipflops : std_logic_vector(stages -1 downto 0) := (others => '0'); 19 | attribute ASYNC_REG : string; 20 | attribute ASYNC_REG of flipflops: signal is "true"; 21 | begin 22 | bit_o <= flipflops(stages-1); 23 | 24 | sync_proc: process(clk_i) 25 | begin 26 | if rising_edge(clk_i) then 27 | flipflops <= flipflops(stages-2 downto 0) & bit_i; 28 | end if; 29 | end process; 30 | end bhv; 31 | -------------------------------------------------------------------------------- /prn20b/hdl/prn20b_logic.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2018/06/11 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | use IEEE.numeric_std.all; 9 | 10 | entity prn20b_logic is 11 | port ( 12 | clk : in std_logic; 13 | reset : in std_logic; 14 | tick_i : in std_logic; 15 | -- start 16 | prn_o : out std_logic_vector(19 downto 0); 17 | bit_o : out std_logic 18 | ); 19 | end entity; 20 | 21 | architecture rtl of prn20b_logic is 22 | signal lfsr_s, lfsr_next_s : std_logic_vector(19 downto 0) := (others => '1'); 23 | signal xor20_17 : std_logic; 24 | signal xorPlusOne : std_logic; 25 | begin 26 | 27 | prn_o <= lfsr_s; 28 | 29 | -- x^20+x^17+1 30 | xor20_17 <= lfsr_s(0) xor lfsr_s(3); 31 | xorPlusOne <= xor20_17 and '1'; 32 | lfsr_next_s <= xorPlusOne & lfsr_s(19 downto 1); 33 | 34 | process(clk) 35 | begin 36 | if rising_edge(clk) then 37 | if (tick_i = '1') then 38 | lfsr_s <= lfsr_next_s; 39 | else 40 | lfsr_s <= lfsr_s; 41 | end if; 42 | end if; 43 | end process; 44 | bit_o <= lfsr_s(0); 45 | 46 | end architecture rtl; 47 | -------------------------------------------------------------------------------- /prn20b/hdl/prn20b_vectSync.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2018/06/11 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity prn20b_vectSync is 10 | generic (stages : natural := 3; 11 | DATA : natural := 16); 12 | port (clk_i : in std_logic; 13 | bit_i : in std_logic_vector(DATA-1 downto 0); 14 | bit_o : out std_logic_vector(DATA-1 downto 0) 15 | ); 16 | end entity prn20b_vectSync; 17 | 18 | architecture bhv of prn20b_vectSync is 19 | type data_tab is array (natural range <>) of std_logic_vector(DATA-1 downto 0); 20 | signal flipflops : data_tab(stages -1 downto 0) := 21 | (others => (others => '0')); 22 | attribute ASYNC_REG : string; 23 | attribute ASYNC_REG of flipflops: signal is "true"; 24 | begin 25 | bit_o <= flipflops(stages-1); 26 | 27 | sync_proc: process(clk_i) 28 | begin 29 | if rising_edge(clk_i) then 30 | flipflops <= flipflops(stages-2 downto 0) & bit_i; 31 | end if; 32 | end process; 33 | end bhv; 34 | -------------------------------------------------------------------------------- /prn20b/prn20b.xdc: -------------------------------------------------------------------------------- 1 | set_false_path -from [get_pins -hier *prescaler_s*/C] 2 | -------------------------------------------------------------------------------- /prn20b/simuC/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | int main(void) 6 | { 7 | 8 | uint32_t start = 0xffffffff; 9 | uint32_t a = start; 10 | int i; 11 | for(i = 1; i < start; i++) { 12 | //int newbit = (((a >> 19) ^ (a >> 2)) & 1); 13 | int newbit = (((a >> 0) ^ (a >> 3)) & 1); 14 | a = ((a >> 1) | (newbit << 19)) & 0x0fffff; 15 | //printf("%d ", a&1); 16 | printf("%d\n", a); 17 | if (a == start) { 18 | printf("repetition period is %d\n", i); 19 | break; 20 | } 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /prn20b/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | -------------------------------------------------------------------------------- /prn20b/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_prn20b 2 | SIMTOP =$(PROJECT)_tb 3 | TESTBENCH_FILE=$(SIMTOP).vhd 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | 10 | FILES=../hdl/prn20b_logic.vhd ../hdl/prn20b_presc.vhd 11 | 12 | SIMDIR=simu 13 | 14 | VIEW_CMD = gtkwave 15 | 16 | all : run 17 | 18 | # Run target 19 | run:$(SIMDIR)/$(SIMTOP).ghw 20 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 21 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 22 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 23 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 24 | 25 | # Targets to analyze libraries 26 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 27 | mkdir -p $(SIMDIR) 28 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 29 | 30 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 31 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 32 | 33 | clean: 34 | $(GHDL) --clean --workdir=simu 35 | -rm -rf simu 36 | force: 37 | -------------------------------------------------------------------------------- /prnGenerator/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | -------------------------------------------------------------------------------- /prnGenerator/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_prnGenerator 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../hdl/prnGenerator.vhd 10 | 11 | SIMDIR=simu 12 | 13 | VIEW_CMD = gtkwave 14 | 15 | all : run 16 | 17 | # Run target 18 | run:$(SIMDIR)/$(SIMTOP).ghw 19 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 20 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 21 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 22 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 23 | 24 | # Targets to analyze libraries 25 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 26 | mkdir -p $(SIMDIR) 27 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 28 | 29 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 30 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 31 | 32 | clean: 33 | $(GHDL) --clean --workdir=simu 34 | -rm -rf simu 35 | -rm -rf result.txt 36 | force: 37 | -------------------------------------------------------------------------------- /prnGenerator/simulation/testC/Makefile: -------------------------------------------------------------------------------- 1 | EXEC_NAME=testCIC 2 | SRC= $(wildcard *.c) 3 | OBJS= $(SRC:.c=.o) 4 | LDFLAGS=-lm -g -Wall 5 | CFLAGS=-I./ -I ../ -g -Wall 6 | 7 | all:$(EXEC_NAME) 8 | 9 | $(EXEC_NAME):$(OBJS) 10 | $(CC) -o $@ $^ $(LDFLAGS) 11 | 12 | %.o: %.c 13 | $(CC) $(CFLAGS) -o $@ -c $< 14 | 15 | clean: 16 | rm -rf $(OBJS) 17 | rm -f $(EXEC_NAME) 18 | rm -f *.c~ *.h~ Makefile~ 19 | rm -f out*.dat 20 | -------------------------------------------------------------------------------- /prnGenerator/simulation/testC/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | int main(void) 6 | { 7 | uint8_t start = 0xff; 8 | uint8_t a = start; 9 | uint8_t period = 2; 10 | uint8_t ii; 11 | int i; 12 | for(i = 1; i < 1005/period; i++) { 13 | int newbit = (((a >> 6) ^ (a & 0x01)) & 1); 14 | for (ii = 0; ii < period; ii++) 15 | printf("%d\n", (unsigned char)(a & 0x01)); 16 | a = ((a << 1) | newbit) & 0x7f; 17 | } 18 | 19 | return EXIT_SUCCESS; 20 | } 21 | -------------------------------------------------------------------------------- /prnGenerator/simulation/testC/testCIC: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/fpga_ip/39826ecea776c999e17a28b686e99c4ad5b7d5f6/prnGenerator/simulation/testC/testCIC -------------------------------------------------------------------------------- /prnGenerator/simulation/top_prnGenerator.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.99 (w)1999-2019 BSI 3 | [*] Mon May 20 05:38:59 2019 4 | [*] 5 | [dumpfile] "/home/gwe/projets/ggm_fpga_ip/prnGenerator/simulation/simu/top_prnGenerator_tb.ghw" 6 | [dumpfile_mtime] "Mon May 20 05:37:44 2019" 7 | [dumpfile_size] 14774 8 | [savefile] "/home/gwe/projets/ggm_fpga_ip/prnGenerator/simulation/top_prnGenerator.gtkw" 9 | [timestart] 0 10 | [size] 1366 748 11 | [pos] -1 -1 12 | *-28.063171 31250000000 51270000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] top. 14 | [treeopen] top.top_prnGenerator_tb. 15 | [treeopen] top.top_prnGenerator_tb.dut. 16 | [sst_width] 196 17 | [signals_width] 219 18 | [sst_expanded] 1 19 | [sst_vpaned_height] 285 20 | @28 21 | top.top_prnGenerator_tb.clk 22 | top.top_prnGenerator_tb.reset 23 | top.top_prnGenerator_tb.prnGenerator_s 24 | @200 25 | -internal 26 | @29 27 | top.top_prnGenerator_tb.dut.period_s[0] 28 | @28 29 | top.top_prnGenerator_tb.dut.xor0_6 30 | top.top_prnGenerator_tb.dut.tick_int_s 31 | top.top_prnGenerator_tb.dut.prnGenerator_o 32 | top.top_prnGenerator_tb.dut.tick_i 33 | top.top_prnGenerator_tb.dut.reset 34 | top.top_prnGenerator_tb.dut.clk 35 | [pattern_trace] 1 36 | [pattern_trace] 0 37 | -------------------------------------------------------------------------------- /pwm_axi/hdl/pwm_cpt.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.all; 4 | 5 | Entity pwm_cpt is 6 | generic( 7 | CPT_SIZE : natural := 32 8 | ); 9 | port ( 10 | clk_i : in std_logic; 11 | reset_i : in std_logic; 12 | enable_i : in std_logic; 13 | max_cpt_i : in std_logic_vector(CPT_SIZE-1 downto 0); 14 | tick_o : out std_logic 15 | ); 16 | end entity pwm_cpt; 17 | 18 | Architecture bhv of pwm_cpt is 19 | signal cpt_s, max_cpt_s : unsigned(CPT_SIZE-1 downto 0); 20 | signal clr_cpt_s, rst_s : std_logic; 21 | begin 22 | max_cpt_s <= unsigned(max_cpt_i) - 1; 23 | rst_s <= '1' when (reset_i or not enable_i) = '1' else '0'; 24 | 25 | clr_cpt_s <= '1' when cpt_s = (CPT_SIZE-1 downto 0 => '0') else '0'; 26 | 27 | tick_o <= clr_cpt_s; 28 | prescaler : process(clk_i) 29 | begin 30 | if rising_edge(clk_i) then 31 | if (rst_s or clr_cpt_s) = '1' then 32 | cpt_s <= max_cpt_s; 33 | else 34 | cpt_s <= cpt_s - 1; 35 | end if; 36 | end if; 37 | end process prescaler; 38 | 39 | end architecture bhv; 40 | -------------------------------------------------------------------------------- /pwm_axi/hdl/pwm_logic.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.all; 4 | 5 | Entity pwm_logic is 6 | generic( 7 | COUNTER_SIZE : natural := 32 8 | ); 9 | port ( 10 | -- CANDR 11 | reset : in std_logic; 12 | clk : in std_logic; 13 | -- conf 14 | enable_i : in std_logic; 15 | invert_i : in std_logic; 16 | duty_i : in std_logic_vector(COUNTER_SIZE-1 downto 0); 17 | period_i : in std_logic_vector(COUNTER_SIZE-1 downto 0); 18 | prescaler_i : in std_logic_vector(COUNTER_SIZE-1 downto 0); 19 | -- out signals 20 | pwm_o : out std_logic 21 | ); 22 | end entity pwm_logic; 23 | 24 | Architecture bhv of pwm_logic is 25 | signal pwm_reg : std_logic; 26 | signal tick_s : std_logic; 27 | signal nb_tick_s : unsigned(COUNTER_SIZE-1 downto 0); 28 | begin 29 | pwm_o <= (pwm_reg xor invert_i) and enable_i; 30 | pwm_reg <= '1' when nb_tick_s < unsigned(duty_i) 31 | else '0'; 32 | 33 | process(clk) begin 34 | if rising_edge(clk) then 35 | if reset = '1' then 36 | nb_tick_s <= (others => '0'); 37 | elsif (tick_s = '1') then 38 | if nb_tick_s < unsigned(period_i) -1 then 39 | nb_tick_s <= nb_tick_s + 1; 40 | else 41 | nb_tick_s <= (others => '0'); 42 | end if; 43 | end if; 44 | end if; 45 | end process; 46 | 47 | pwm_cpt_inst : entity work.pwm_cpt 48 | generic map (CPT_SIZE => COUNTER_SIZE) 49 | port map (clk_i => clk, reset_i => reset, 50 | enable_i => enable_i, 51 | max_cpt_i => prescaler_i, tick_o => tick_s); 52 | end architecture bhv; 53 | 54 | -------------------------------------------------------------------------------- /pwm_axi/hdl/pwm_sync_bit.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2015/04/08 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity pwm_sync_bit is 10 | generic (stages : natural := 3); 11 | port ( 12 | ref_clk_i : in std_logic; 13 | clk_i : in std_logic; 14 | bit_i : in std_logic; 15 | bit_o : out std_logic 16 | ); 17 | end entity pwm_sync_bit; 18 | 19 | architecture bhv of pwm_sync_bit is 20 | signal sync_stage0_s: std_logic; 21 | signal flipflops : std_logic_vector(stages -1 downto 0) := (others => '0'); 22 | attribute ASYNC_REG : string; 23 | attribute ASYNC_REG of flipflops: signal is "true"; 24 | begin 25 | ref_proc: process(ref_clk_i) begin 26 | if rising_edge(ref_clk_i) then 27 | sync_stage0_s <= bit_i; 28 | end if; 29 | end process; 30 | 31 | sync_proc: process(clk_i) 32 | begin 33 | if rising_edge(clk_i) then 34 | flipflops(0) <= sync_stage0_s; 35 | flipflops(stages-1 downto 1) 36 | <= flipflops(stages-2 downto 0); 37 | end if; 38 | end process; 39 | bit_o <= flipflops(stages-1); 40 | end bhv; 41 | -------------------------------------------------------------------------------- /pwm_axi/hdl/pwm_sync_vector.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2015/04/08 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity pwm_sync_vector is 10 | generic (stages : natural := 3; 11 | DATA : natural := 16); 12 | port ( 13 | ref_clk_i : in std_logic; 14 | clk_i : in std_logic; 15 | bit_i : in std_logic_vector(DATA-1 downto 0); 16 | bit_o : out std_logic_vector(DATA-1 downto 0) 17 | ); 18 | end entity pwm_sync_vector; 19 | 20 | architecture bhv of pwm_sync_vector is 21 | signal sync_vect_stage0_s: std_logic_vector(DATA-1 downto 0); 22 | type data_tab is array (natural range <>) of std_logic_vector(DATA-1 downto 0); 23 | signal flipflops_vect : data_tab(stages -1 downto 0) := (others => (others => '0')); 24 | attribute ASYNC_REG : string; 25 | attribute ASYNC_REG of flipflops_vect: signal is "true"; 26 | begin 27 | ref_proc: process(ref_clk_i) begin 28 | if rising_edge(ref_clk_i) then 29 | sync_vect_stage0_s <= bit_i; 30 | end if; 31 | end process; 32 | 33 | sync_proc: process(clk_i) 34 | begin 35 | if rising_edge(clk_i) then 36 | flipflops_vect(0) <= sync_vect_stage0_s; 37 | flipflops_vect(stages-1 downto 1) 38 | <= flipflops_vect(stages-2 downto 0); 39 | end if; 40 | end process; 41 | bit_o <= flipflops_vect(stages-1); 42 | end bhv; 43 | -------------------------------------------------------------------------------- /pwm_axi/pwm_axi.xdc: -------------------------------------------------------------------------------- 1 | set_property ASYNC_REG TRUE \ 2 | [get_cells -hier flipflops*_reg[0]] \ 3 | [get_cells -hier flipflops*_reg[1]] 4 | set_false_path \ 5 | -from [get_cells -hier sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ 6 | -to [get_cells -hier flipflops*_reg[0] -filter {IS_SEQUENTIAL}] 7 | 8 | set_property ASYNC_REG TRUE \ 9 | [get_cells -hier flipflops_vect*_reg[0][*]] \ 10 | [get_cells -hier flipflops_vect*_reg[1][*]] 11 | set_false_path \ 12 | -from [get_cells -hier sync_vect_stage0_*_reg[*] -filter {IS_SEQUENTIAL}] \ 13 | -to [get_cells -hier flipflops_vect*_reg[0][*] -filter {IS_SEQUENTIAL}] 14 | -------------------------------------------------------------------------------- /pwm_axi/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM = ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | PLUSARGS=--vcdgz=$(WPWD)/build/waveform.vcdgz --wave=$(WPWD)/build/waveform.ghw 7 | 8 | VHDL_SOURCES=$(WPWD)/../hdl/pwm_logic.vhd $(WPWD)/../hdl/pwm_cpt.vhd 9 | VHDL_SOURCES+=$(WPWD)/top_pwmAxi.vhd 10 | 11 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 12 | TOPLEVEL=top_pwmaxi 13 | # MODULE is the name of the Python test file: 14 | MODULE=top_pwmAxi_tb 15 | include $(shell cocotb-config --makefiles)/Makefile.inc 16 | include $(shell cocotb-config --makefiles)/Makefile.sim 17 | 18 | view: 19 | gtkwave -a top_pwmAxi.gtkw build/waveform.ghw 20 | -------------------------------------------------------------------------------- /pwm_axi/simulation/top_pwmAxi.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.ALL; 4 | 5 | entity top_pwmaxi is 6 | port ( 7 | clk_i : in std_logic; 8 | rst_i : in std_logic; 9 | -- conf 10 | enable_i : in std_logic; 11 | duty_i : in std_logic_vector(31 downto 0); 12 | period_i : in std_logic_vector(31 downto 0); 13 | prescaler_i : in std_logic_vector(31 downto 0); 14 | -- out 15 | pwm1_o : out std_logic; 16 | pwm2_o : out std_logic 17 | ); 18 | end top_pwmaxi; 19 | 20 | architecture Behavioral of top_pwmaxi is 21 | begin 22 | dutInvertN : entity work.pwm_logic 23 | generic map (COUNTER_SIZE => 32 ) 24 | port map ( 25 | clk => clk_i, reset => rst_i, 26 | enable_i => enable_i, invert_i => '0', 27 | prescaler_i => prescaler_i, 28 | duty_i => duty_i, period_i => period_i, 29 | pwm_o => pwm1_o 30 | ); 31 | 32 | dutInvert : entity work.pwm_logic 33 | generic map (COUNTER_SIZE => 32) 34 | port map ( 35 | clk => clk_i, reset => rst_i, 36 | enable_i => enable_i, invert_i => '1', 37 | prescaler_i => prescaler_i, 38 | duty_i => duty_i, period_i => period_i, 39 | pwm_o => pwm2_o 40 | ); 41 | 42 | end Behavioral; 43 | -------------------------------------------------------------------------------- /ram_to_dataReal/hdl/ram_to_dataReal_bitSync.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity ram_to_dataReal_bitSync is 5 | generic (stages : natural := 3); 6 | port (clk_i : in std_logic; 7 | bit_i : in std_logic; 8 | bit_o : out std_logic 9 | ); 10 | end entity ram_to_dataReal_bitSync; 11 | 12 | architecture bhv of ram_to_dataReal_bitSync is 13 | signal flipflops : std_logic_vector(stages -1 downto 0) := (others => '0'); 14 | attribute ASYNC_REG : string; 15 | attribute ASYNC_REG of flipflops: signal is "true"; 16 | begin 17 | bit_o <= flipflops(stages-1); 18 | 19 | sync_proc: process(clk_i) 20 | begin 21 | if rising_edge(clk_i) then 22 | flipflops <= flipflops(stages-2 downto 0) & bit_i; 23 | end if; 24 | end process; 25 | end bhv; 26 | -------------------------------------------------------------------------------- /realToAxiStream/hdl/realToAxiStream.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.all; 4 | 5 | Entity realToAxiStream is 6 | generic ( 7 | DATA_SIZE : natural := 32 8 | ); 9 | port ( 10 | -- input data 11 | data_i : in std_logic_vector(DATA_SIZE-1 downto 0); 12 | data_en_i: in std_logic; 13 | data_clk_i: in std_logic; 14 | data_rst_i: in std_logic; 15 | -- output data 16 | m00_axis_aclk : in std_logic; 17 | m00_axis_tdata : out std_logic_vector(DATA_SIZE-1 downto 0); 18 | m00_axis_tready : in std_logic; 19 | m00_axis_tvalid : out std_logic 20 | ); 21 | end entity; 22 | 23 | --------------------------------------------------------------------------- 24 | Architecture realToAxiStream_1 of realToAxiStream is 25 | begin 26 | m00_axis_tdata <= data_i; 27 | m00_axis_tvalid <= data_en_i; 28 | end architecture realToAxiStream_1; 29 | 30 | -------------------------------------------------------------------------------- /realToAxiStream/xgui/realToAxiStream_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | set DATA_SIZE [ipgui::add_param $IPINST -name "DATA_SIZE" -parent ${Page_0}] 7 | set_property tooltip {Size of input data bus.} ${DATA_SIZE} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 13 | # Procedure called to update DATA_SIZE when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.DATA_SIZE { PARAM_VALUE.DATA_SIZE } { 17 | # Procedure called to validate DATA_SIZE 18 | return true 19 | } 20 | 21 | 22 | proc update_MODELPARAM_VALUE.DATA_SIZE { MODELPARAM_VALUE.DATA_SIZE PARAM_VALUE.DATA_SIZE } { 23 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 24 | set_property value [get_property value ${PARAM_VALUE.DATA_SIZE}] ${MODELPARAM_VALUE.DATA_SIZE} 25 | } 26 | 27 | -------------------------------------------------------------------------------- /redpitaya_adc_dac_clk/adc_dac_clk_ooc.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################ 2 | # Clock constraints # 3 | ############################################################################ 4 | #NET "adc_clk" TNM_NET = "adc_clk"; 5 | #TIMESPEC TS_adc_clk = PERIOD "adc_clk" 125 MHz; 6 | 7 | create_clock -period 8.000 -name adc_clk [get_ports adc_clk_p_i] 8 | 9 | set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_out] 10 | set_false_path -from [get_clocks dac_clk_out] -to [get_clocks dac_2clk_out] 11 | set_false_path -from [get_clocks dac_clk_out] -to [get_clocks dac_2ph_out] 12 | -------------------------------------------------------------------------------- /redpitaya_adc_dac_clk/redpitaya_adc_dac_clk.tcl: -------------------------------------------------------------------------------- 1 | create_bd_port -dir I adc_clk_p_i_0 2 | create_bd_port -dir I adc_clk_n_i_0 3 | -------------------------------------------------------------------------------- /redpitaya_adc_dac_clk/redpitaya_clk_pin.xdc: -------------------------------------------------------------------------------- 1 | set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports adc_clk_p_i_0] 2 | set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports adc_clk_n_i_0] 3 | set_property PACKAGE_PIN U18 [get_ports adc_clk_p_i_0] 4 | set_property PACKAGE_PIN U19 [get_ports adc_clk_n_i_0] 5 | -------------------------------------------------------------------------------- /redpitaya_adc_dac_clk/xgui/redpitaya_adc_dac_clk_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /redpitaya_converters/redpitaya_converters.tcl: -------------------------------------------------------------------------------- 1 | set phys_interface_0 [ create_bd_intf_port -mode slave \ 2 | -vlnv ggm:interface:redpitaya_converters_if_rtl:1.0 phys_interface_0 ] 3 | 4 | -------------------------------------------------------------------------------- /redpitaya_converters/redpitaya_converters_if.xml: -------------------------------------------------------------------------------- 1 | 2 | 5 | ggm 6 | interface 7 | redpitaya_converters_if 8 | 1.0 9 | false 10 | false 11 | 1 12 | 1 13 | Redpitaya Converters Physical interface 14 | 15 | -------------------------------------------------------------------------------- /redpitaya_converters/redpitaya_converters_ooc.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################ 2 | # Clock constraints # 3 | ############################################################################ 4 | #NET "adc_clk" TNM_NET = "adc_clk"; 5 | #TIMESPEC TS_adc_clk = PERIOD "adc_clk" 125 MHz; 6 | 7 | create_clock -period 8.000 -name adc_clk [get_ports adc_clk_p_i] 8 | 9 | set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_out] 10 | set_false_path -from [get_clocks dac_clk_out] -to [get_clocks dac_2clk_out] 11 | set_false_path -from [get_clocks dac_clk_out] -to [get_clocks dac_2ph_out] 12 | -------------------------------------------------------------------------------- /redpitaya_converters_12/hdl/ad9746.v: -------------------------------------------------------------------------------- 1 | module ad9746 ( 2 | // DAC clks 3 | input dac_clk_i, 4 | input dac_locked_i, 5 | 6 | // DAC 7 | output [ 14-1: 0] dac_dat_a_o, 8 | output [ 14-1: 0] dac_dat_b_o, 9 | output dac_rst_o, 10 | 11 | input dac_dat_a_en_i, 12 | input dac_dat_a_rst_i, 13 | input [ 14-1: 0] dac_dat_a_i, //!< DAC CHA data 14 | input dac_dat_b_en_i, 15 | input dac_dat_b_rst_i, 16 | input [ 14-1: 0] dac_dat_b_i //!< DAC CHB data 17 | 18 | ); 19 | 20 | //--------------------------------------------------------------------------------- 21 | // 22 | // Fast DAC - DDR interface 23 | 24 | reg [14-1: 0] dac_dat_a_o ; 25 | reg [14-1: 0] dac_dat_b_o ; 26 | reg [14-1: 0] dac_dat_a_s ; 27 | reg [14-1: 0] dac_dat_b_s ; 28 | reg dac_rst_o ; 29 | 30 | 31 | always @(posedge dac_clk_i) begin 32 | dac_dat_a_s <= dac_dat_a_s; 33 | dac_dat_b_s <= dac_dat_b_s; 34 | if (dac_dat_a_en_i == 1'b1) 35 | dac_dat_a_s <= dac_dat_a_i; 36 | if (dac_dat_b_en_i == 1'b1) 37 | dac_dat_b_s <= dac_dat_b_i; 38 | end 39 | 40 | always @(posedge dac_clk_i) begin 41 | dac_dat_a_o <= ~dac_dat_b_s; 42 | dac_dat_b_o <= ~dac_dat_a_s; 43 | dac_rst_o <= !dac_locked_i; 44 | end 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /redpitaya_converters_12/hdl/redpitaya_converters_12_sync_bit.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2015/04/08 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity redpitaya_converters_12_sync_bit is 10 | generic (stages : natural := 3); 11 | port ( 12 | ref_clk_i : in std_logic; 13 | clk_i : in std_logic; 14 | bit_i : in std_logic; 15 | bit_o : out std_logic 16 | ); 17 | end entity redpitaya_converters_12_sync_bit; 18 | 19 | architecture bhv of redpitaya_converters_12_sync_bit is 20 | signal sync_stage0_s: std_logic; 21 | signal flipflops : std_logic_vector(stages -1 downto 0) := (others => '0'); 22 | attribute ASYNC_REG : string; 23 | attribute ASYNC_REG of flipflops: signal is "true"; 24 | begin 25 | ref_proc: process(ref_clk_i) begin 26 | if rising_edge(ref_clk_i) then 27 | sync_stage0_s <= bit_i; 28 | end if; 29 | end process; 30 | 31 | sync_proc: process(clk_i) 32 | begin 33 | if rising_edge(clk_i) then 34 | flipflops(0) <= sync_stage0_s; 35 | flipflops(stages-1 downto 1) 36 | <= flipflops(stages-2 downto 0); 37 | end if; 38 | end process; 39 | bit_o <= flipflops(stages-1); 40 | end bhv; 41 | -------------------------------------------------------------------------------- /redpitaya_converters_12/redpitaya_converters_12.tcl: -------------------------------------------------------------------------------- 1 | set phys_interface_0 [ create_bd_intf_port -mode slave \ 2 | -vlnv ggm:interface:redpitaya_converters_12_if_rtl:1.0 phys_interface_0 ] 3 | 4 | -------------------------------------------------------------------------------- /redpitaya_converters_12/redpitaya_converters_12_if.xml: -------------------------------------------------------------------------------- 1 | 2 | 5 | ggm 6 | interface 7 | redpitaya_converters_12_if 8 | 1.0 9 | false 10 | false 11 | 1 12 | 1 13 | Redpitaya Converters 12 Physical interface 14 | 15 | -------------------------------------------------------------------------------- /redpitaya_converters_12/redpitaya_converters_12_ooc.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################ 2 | # Clock constraints # 3 | ############################################################################ 4 | #NET "adc_clk" TNM_NET = "adc_clk"; 5 | #TIMESPEC TS_adc_clk = PERIOD "adc_clk" 250 MHz; 6 | 7 | create_clock -period 100.000 -name pll_ref_i -waveform {0.000 50.000} [get_ports pll_ref_i] 8 | create_clock -period 4.000 -name adc_clk [get_ports adc_clk_p_i] 9 | 10 | set_clock_groups -asynchronous -group dac_clk_out -group adc_clk2d_out -group adc_clk 11 | set_clock_groups -asynchronous -group adc_clk2d_out -group pll_ref_i 12 | 13 | 14 | 15 | 16 | set_property ASYNC_REG TRUE \ 17 | [get_cells -hier flipflops*_reg[0]] \ 18 | [get_cells -hier flipflops*_reg[1]] 19 | set_false_path \ 20 | -from [get_cells -hier sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ 21 | -to [get_cells -hier flipflops*_reg[0] -filter {IS_SEQUENTIAL}] 22 | 23 | set_property ASYNC_REG TRUE \ 24 | [get_cells -hier flipflops_vect*_reg[0][*]] \ 25 | [get_cells -hier flipflops_vect*_reg[1][*]] 26 | set_false_path \ 27 | -from [get_cells -hier sync_vect_stage0_*_reg[*] -filter {IS_SEQUENTIAL}] \ 28 | -to [get_cells -hier flipflops_vect*_reg[0][*] -filter {IS_SEQUENTIAL}] 29 | 30 | -------------------------------------------------------------------------------- /sampleCounterComplex/Makefile: -------------------------------------------------------------------------------- 1 | M_DEPS += $(wildcard hdl/*.vhd) 2 | M_DEPS += $(wildcard hdl/*.v) 3 | 4 | 5 | M_VIVADO := vivado -mode batch -source 6 | 7 | M_FLIST := *.cache 8 | M_FLIST += *.data 9 | M_FLIST += *.xpr 10 | M_FLIST += *.log 11 | M_FLIST += *.jou 12 | M_FLIST += *.ip_user_files 13 | M_FLIST += *.srcs 14 | M_FLIST += *.hw 15 | M_FLIST += *.sim *.runs 16 | M_FLIST += *.zip 17 | M_FLIST += .Xil 18 | M_FLIST += tmp 19 | 20 | M_FLIST2 += component.xml 21 | M_FLIST2 += xgui 22 | 23 | .PHONY: all clean clean-all 24 | all: component.xml 25 | 26 | clean:clean-all 27 | 28 | clean-all: 29 | rm -rf $(M_FLIST) $(M_FLIST2) 30 | 31 | clean-trash: 32 | rm -rf $(M_FLIST) 33 | 34 | component.xml: $(M_DEPS) $(OSCIMP_DIGITAL_IP)/scripts/core_ip.tcl ./core_config.tcl 35 | -rm -rf $(M_FLIST) 36 | $(M_VIVADO) core_config.tcl 37 | 38 | -------------------------------------------------------------------------------- /sampleCounterComplex/core_config.tcl: -------------------------------------------------------------------------------- 1 | variable fpga_ip $::env(OSCIMP_DIGITAL_IP) 2 | 3 | source $fpga_ip/scripts/core_ip.tcl 4 | 5 | set ip_name {sampleCounterComplex} 6 | set version 1.0 7 | 8 | adi_ip_create $ip_name 9 | adi_ip_file $ip_name [list \ 10 | "./hdl/sampleCounterComplex.vhd"] 11 | 12 | package_and_set_default_properties $version $ip_name cogen \ 13 | ggm {Gwenhael Goavec-Merou} \ 14 | http://www.trabucayre.com 15 | 16 | core_parameter DATA_SIZE {Data Size} {input and output data size.} 17 | core_parameter SAMPLE_COUNTER_SIZE {Counter Size} {internal counter and output counter stream size} 18 | 19 | add_complex_bus "data_in" "slave" \ 20 | { 21 | {"data_i_i" "DATA_I"} \ 22 | {"data_q_i" "DATA_Q"} \ 23 | {"data_en_i" "DATA_EN"} \ 24 | {"data_eof_i" "DATA_EOF"} \ 25 | {"data_sof_i" "DATA_SOF"} \ 26 | {"data_clk_i" "DATA_CLK"} \ 27 | {"data_rst_i" "DATA_RST"} \ 28 | } 29 | 30 | add_complex_bus "data_out" "master" \ 31 | { 32 | {"data_i_o" "DATA_I"} \ 33 | {"data_q_o" "DATA_Q"} \ 34 | {"data_en_o" "DATA_EN"} \ 35 | {"data_eof_o" "DATA_EOF"} \ 36 | {"data_sof_o" "DATA_SOF"} \ 37 | {"data_clk_o" "DATA_CLK"} \ 38 | {"data_rst_o" "DATA_RST"} \ 39 | } 40 | 41 | add_real_bus "counter_out" "master" \ 42 | { 43 | {"counter_o" "DATA"} \ 44 | {"counter_en_o" "DATA_EN"} \ 45 | {"counter_eof_o" "DATA_EOF"} \ 46 | {"counter_sof_o" "DATA_SOF"} \ 47 | {"counter_clk_o" "DATA_CLK"} \ 48 | {"counter_rst_o" "DATA_RST"} \ 49 | } 50 | 51 | rename core_parameter {} 52 | 53 | package_save 54 | 55 | close_project 56 | -------------------------------------------------------------------------------- /sampleCounterComplex/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM = ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | PLUSARGS=--vcdgz=$(WPWD)/sim_build/waveform.vcdgz --wave=$(WPWD)/sim_build/waveform.ghw 7 | 8 | VHDL_SOURCES = $(WPWD)/../hdl/sampleCounterComplex.vhd 9 | 10 | VHDL_SOURCES+=$(WPWD)/top_dut.vhd 11 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 12 | TOPLEVEL=top_dut 13 | # MODULE is the name of the Python test file: 14 | MODULE=top_tb 15 | include $(shell cocotb-config --makefiles)/Makefile.sim 16 | 17 | view: 18 | gtkwave -a top_sampleCounterComplex.gtkw sim_build/waveform.ghw 19 | -------------------------------------------------------------------------------- /sampleCounterReal/Makefile: -------------------------------------------------------------------------------- 1 | M_DEPS += $(wildcard hdl/*.vhd) 2 | M_DEPS += $(wildcard hdl/*.v) 3 | 4 | 5 | M_VIVADO := vivado -mode batch -source 6 | 7 | M_FLIST := *.cache 8 | M_FLIST += *.data 9 | M_FLIST += *.xpr 10 | M_FLIST += *.log 11 | M_FLIST += *.jou 12 | M_FLIST += *.ip_user_files 13 | M_FLIST += *.srcs 14 | M_FLIST += *.hw 15 | M_FLIST += *.sim *.runs 16 | M_FLIST += *.zip 17 | M_FLIST += .Xil 18 | M_FLIST += tmp 19 | 20 | M_FLIST2 += component.xml 21 | M_FLIST2 += xgui 22 | 23 | .PHONY: all clean clean-all 24 | all: component.xml 25 | 26 | clean:clean-all 27 | 28 | clean-all: 29 | rm -rf $(M_FLIST) $(M_FLIST2) 30 | 31 | clean-trash: 32 | rm -rf $(M_FLIST) 33 | 34 | component.xml: $(M_DEPS) $(OSCIMP_DIGITAL_IP)/scripts/core_ip.tcl ./core_config.tcl 35 | -rm -rf $(M_FLIST) 36 | $(M_VIVADO) core_config.tcl 37 | 38 | -------------------------------------------------------------------------------- /sampleCounterReal/core_config.tcl: -------------------------------------------------------------------------------- 1 | variable fpga_ip $::env(OSCIMP_DIGITAL_IP) 2 | 3 | source $fpga_ip/scripts/core_ip.tcl 4 | 5 | set ip_name {sampleCounterReal} 6 | set version 1.0 7 | 8 | adi_ip_create $ip_name 9 | adi_ip_file $ip_name [list \ 10 | "./hdl/sampleCounterReal.vhd"] 11 | 12 | package_and_set_default_properties $version $ip_name cogen \ 13 | ggm {Gwenhael Goavec-Merou} \ 14 | http://www.trabucayre.com 15 | 16 | core_parameter DATA_SIZE {Data Size} {input and output data size.} 17 | core_parameter SAMPLE_COUNTER_SIZE {Counter Size} {internal counter and output counter stream size} 18 | 19 | add_real_bus "data_in" "slave" \ 20 | { 21 | {"data_i" "DATA"} \ 22 | {"data_en_i" "DATA_EN"} \ 23 | {"data_eof_i" "DATA_EOF"} \ 24 | {"data_sof_i" "DATA_SOF"} \ 25 | {"data_clk_i" "DATA_CLK"} \ 26 | {"data_rst_i" "DATA_RST"} \ 27 | } 28 | 29 | add_real_bus "data_out" "master" \ 30 | { 31 | {"data_o" "DATA"} \ 32 | {"data_en_o" "DATA_EN"} \ 33 | {"data_eof_o" "DATA_EOF"} \ 34 | {"data_sof_o" "DATA_SOF"} \ 35 | {"data_clk_o" "DATA_CLK"} \ 36 | {"data_rst_o" "DATA_RST"} \ 37 | } 38 | 39 | add_real_bus "counter_out" "master" \ 40 | { 41 | {"counter_o" "DATA"} \ 42 | {"counter_en_o" "DATA_EN"} \ 43 | {"counter_eof_o" "DATA_EOF"} \ 44 | {"counter_sof_o" "DATA_SOF"} \ 45 | {"counter_clk_o" "DATA_CLK"} \ 46 | {"counter_rst_o" "DATA_RST"} \ 47 | } 48 | 49 | rename core_parameter {} 50 | 51 | package_save 52 | 53 | close_project 54 | -------------------------------------------------------------------------------- /sampleCounterReal/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM = ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | PLUSARGS=--vcdgz=$(WPWD)/sim_build/waveform.vcdgz --wave=$(WPWD)/sim_build/waveform.ghw 7 | 8 | VHDL_SOURCES = $(WPWD)/../hdl/sampleCounterReal.vhd 9 | 10 | VHDL_SOURCES+=$(WPWD)/top_dut.vhd 11 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 12 | TOPLEVEL=top_dut 13 | # MODULE is the name of the Python test file: 14 | MODULE=top_tb 15 | include $(shell cocotb-config --makefiles)/Makefile.sim 16 | 17 | view: 18 | gtkwave -a top_sampleCounterReal.gtkw sim_build/waveform.ghw 19 | -------------------------------------------------------------------------------- /scripts/alt_gen.tcl: -------------------------------------------------------------------------------- 1 | set prj_name [lindex $argv 0] 2 | set use_qsys [lindex $argv 1] 3 | set family [lindex $argv 2] 4 | set part [lindex $argv 3] 5 | 6 | cd ./tmp 7 | package require ::quartus::project 8 | package require ::quartus::flow 9 | 10 | project_open $prj_name 11 | 12 | if {[string equal -nocase $use_qsys "y"]} { 13 | set QSYS_GEN [glob -join $quartus(quartus_rootpath) sopc_builder bin qsys-generate] 14 | exec -ignorestderr $QSYS_GEN ${prj_name}_qsys.qsys --synthesis=VHDL --family=$family --part=$part 15 | } 16 | 17 | execute_flow -compile 18 | project_close 19 | -------------------------------------------------------------------------------- /scripts/xil_gen.tcl: -------------------------------------------------------------------------------- 1 | set project_name [lindex $argv 0] 2 | 3 | # Project and block design creation 4 | open_project tmp/$project_name.xpr 5 | 6 | # set the current synth run 7 | current_run -synthesis [get_runs synth_1] 8 | reset_run synth_1 9 | 10 | set obj [get_runs impl_1] 11 | set_property AUTO_INCREMENTAL_CHECKPOINT 1 [get_runs impl_1] 12 | 13 | set_property "needs_refresh" "1" $obj 14 | 15 | # set the current impl run 16 | current_run -implementation [get_runs impl_1] 17 | 18 | puts "INFO: Project created: $project_name" 19 | 20 | launch_runs synth_1 -jobs 4 21 | wait_on_run synth_1 22 | ## do implementation 23 | launch_runs impl_1 -jobs 4 24 | wait_on_run impl_1 25 | ## make bit file 26 | launch_runs impl_1 -jobs 4 -to_step write_bitstream 27 | wait_on_run impl_1 28 | exit 29 | 30 | -------------------------------------------------------------------------------- /setenv.sh: -------------------------------------------------------------------------------- 1 | export OSCIMP_DIGITAL_IP=$(cd `dirname "${BASH_SOURCE[0]}"` && pwd) 2 | -------------------------------------------------------------------------------- /shifterComplex_dyn/shifterComplex_dyn.xdc: -------------------------------------------------------------------------------- 1 | set_property ASYNC_REG TRUE \ 2 | [get_cells -hier flipflops*_reg[0]] \ 3 | [get_cells -hier flipflops*_reg[1]] 4 | set_false_path \ 5 | -from [get_cells -hier sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ 6 | -to [get_cells -hier flipflops*_reg[0] -filter {IS_SEQUENTIAL}] 7 | 8 | set_property ASYNC_REG TRUE \ 9 | [get_cells -hier flipflops_vect*_reg[0][*]] \ 10 | [get_cells -hier flipflops_vect*_reg[1][*]] 11 | set_false_path \ 12 | -from [get_cells -hier sync_vect_stage0_*_reg[*] -filter {IS_SEQUENTIAL}] \ 13 | -to [get_cells -hier flipflops_vect*_reg[0][*] -filter {IS_SEQUENTIAL}] 14 | -------------------------------------------------------------------------------- /shifterComplex_dyn/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | -------------------------------------------------------------------------------- /shifterComplex_dyn/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_shifterComplex_dyn 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../hdl/shifterComplex_dyn_logic.vhd 10 | #FILES=../readFromFile.vhd ../ram_storage16.vhd \ 11 | # ../../hdl/shifterComplex_dyn_dspmanu.vhd \ 12 | # ../../hdl/shifterComplex_dyn_reg_delay.vhd \ 13 | # ../../hdl/shifterComplex_dyn_cpt.vhd \ 14 | # ../../hdl/shifterComplex_dyn_ram.vhd \ 15 | # ../../hdl/shifterComplex_dyn_proc.vhd \ 16 | # ../../hdl/shifterComplex_dyn_global.vhd \ 17 | # ../../hdl/shifterComplex_dyn_ng_top.vhd 18 | SIMDIR=simu 19 | 20 | VIEW_CMD = gtkwave 21 | 22 | all : run 23 | 24 | # Run target 25 | run:$(SIMDIR)/$(SIMTOP).ghw 26 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 27 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 28 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 29 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 30 | 31 | # Targets to analyze libraries 32 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 33 | mkdir -p $(SIMDIR) 34 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 35 | 36 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 37 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 38 | 39 | clean: 40 | $(GHDL) --clean --workdir=simu 41 | -rm -rf simu 42 | -------------------------------------------------------------------------------- /shifterReal/shifterReal.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | shifterReal 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | -------------------------------------------------------------------------------- /shifterReal_dyn/shifterReal_dyn.xdc: -------------------------------------------------------------------------------- 1 | set_property ASYNC_REG TRUE \ 2 | [get_cells -hier flipflops*_reg[0]] \ 3 | [get_cells -hier flipflops*_reg[1]] 4 | set_false_path \ 5 | -from [get_cells -hier sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ 6 | -to [get_cells -hier flipflops*_reg[0] -filter {IS_SEQUENTIAL}] 7 | 8 | set_property ASYNC_REG TRUE \ 9 | [get_cells -hier flipflops_vect*_reg[0][*]] \ 10 | [get_cells -hier flipflops_vect*_reg[1][*]] 11 | set_false_path \ 12 | -from [get_cells -hier sync_vect_stage0_*_reg[*] -filter {IS_SEQUENTIAL}] \ 13 | -to [get_cells -hier flipflops_vect*_reg[0][*] -filter {IS_SEQUENTIAL}] 14 | -------------------------------------------------------------------------------- /shifterReal_dyn/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | -------------------------------------------------------------------------------- /shifterReal_dyn/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_shifterReal_dyn 2 | TESTBENCH_FILE=$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../hdl/shifterReal_dyn_logic.vhd 10 | #FILES=../readFromFile.vhd ../ram_storage16.vhd \ 11 | # ../../hdl/shifterReal_dyn_dspmanu.vhd \ 12 | # ../../hdl/shifterReal_dyn_reg_delay.vhd \ 13 | # ../../hdl/shifterReal_dyn_cpt.vhd \ 14 | # ../../hdl/shifterReal_dyn_ram.vhd \ 15 | # ../../hdl/shifterReal_dyn_proc.vhd \ 16 | # ../../hdl/shifterReal_dyn_global.vhd \ 17 | # ../../hdl/shifterReal_dyn_ng_top.vhd 18 | SIMDIR=simu 19 | 20 | VIEW_CMD = gtkwave 21 | 22 | all : run 23 | 24 | # Run target 25 | run:$(SIMDIR)/$(SIMTOP).ghw 26 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 27 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 28 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 29 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 30 | 31 | # Targets to analyze libraries 32 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 33 | mkdir -p $(SIMDIR) 34 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 35 | 36 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 37 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 38 | 39 | clean: 40 | $(GHDL) --clean --workdir=simu 41 | -rm -rf simu 42 | -------------------------------------------------------------------------------- /slv_to_sl_axi/hdl/slv_to_sl_axi_sync_slv.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity slv_to_sl_axi_sync_slv is 5 | generic (stages : natural := 3; 6 | DATA : natural := 16); 7 | port (clk_i : in std_logic; 8 | bit_i : in std_logic_vector(DATA-1 downto 0); 9 | bit_o : out std_logic_vector(DATA-1 downto 0) 10 | ); 11 | end entity slv_to_sl_axi_sync_slv; 12 | 13 | architecture bhv of slv_to_sl_axi_sync_slv is 14 | type data_tab is array (natural range <>) of std_logic_vector(DATA-1 downto 0); 15 | signal flipflops : data_tab(stages -1 downto 0) := 16 | (others => (others => '0')); 17 | attribute ASYNC_REG : string; 18 | attribute ASYNC_REG of flipflops: signal is "true"; 19 | begin 20 | bit_o <= flipflops(stages-1); 21 | 22 | sync_proc: process(clk_i) 23 | begin 24 | if rising_edge(clk_i) then 25 | flipflops <= flipflops(stages-2 downto 0) & bit_i; 26 | end if; 27 | end process; 28 | end bhv; 29 | -------------------------------------------------------------------------------- /slv_to_sl_axi/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_slv_to_sl_axi 2 | SIMTOP =$(PROJECT)_tb 3 | TESTBENCH_FILE=$(SIMTOP).vhd 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | 10 | SIMDIR=simu 11 | 12 | VIEW_CMD = gtkwave 13 | 14 | all : run 15 | 16 | # Run target 17 | run:$(SIMDIR)/$(SIMTOP).ghw 18 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 19 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 20 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 21 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 22 | 23 | # Targets to analyze libraries 24 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 25 | mkdir -p $(SIMDIR) 26 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 27 | 28 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 29 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 30 | 31 | clean: 32 | $(GHDL) --clean --workdir=simu 33 | -rm -rf simu 34 | -rm -f result.txt 35 | force: 36 | -------------------------------------------------------------------------------- /slv_to_sl_axi/slv_to_sl_axi.xdc: -------------------------------------------------------------------------------- 1 | set_false_path -from [get_pins -hier *offset_s*/C] 2 | -------------------------------------------------------------------------------- /switchComplex/hdl/switchComplex_synch.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2015/04/08 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity switchComplex_synch is 10 | generic (stages : natural := 3); 11 | port ( 12 | ref_clk_i : in std_logic; 13 | clk_i : in std_logic; 14 | bit_i : in std_logic; 15 | bit_o : out std_logic 16 | ); 17 | end entity switchComplex_synch; 18 | 19 | architecture bhv of switchComplex_synch is 20 | signal sync_stage0_s: std_logic; 21 | signal flipflops : std_logic_vector(stages -1 downto 0) := (others => '0'); 22 | attribute ASYNC_REG : string; 23 | attribute ASYNC_REG of flipflops: signal is "true"; 24 | begin 25 | ref_proc: process(ref_clk_i) begin 26 | if rising_edge(ref_clk_i) then 27 | sync_stage0_s <= bit_i; 28 | end if; 29 | end process; 30 | 31 | sync_proc: process(clk_i) 32 | begin 33 | if rising_edge(clk_i) then 34 | flipflops(0) <= sync_stage0_s; 35 | flipflops(stages-1 downto 1) 36 | <= flipflops(stages-2 downto 0); 37 | end if; 38 | end process; 39 | bit_o <= flipflops(stages-1); 40 | end bhv; 41 | -------------------------------------------------------------------------------- /switchComplex/switchComplex.xdc: -------------------------------------------------------------------------------- 1 | set_property ASYNC_REG TRUE \ 2 | [get_cells -hier flipflops*_reg[0]] \ 3 | [get_cells -hier flipflops*_reg[1]] 4 | set_false_path \ 5 | -from [get_cells -hier sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ 6 | -to [get_cells -hier flipflops*_reg[0] -filter {IS_SEQUENTIAL}] 7 | -------------------------------------------------------------------------------- /switchReal/hdl/switchReal_synch.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | entity switchReal_synch is 5 | generic (stages : natural := 3); 6 | port (clk_i : in std_logic; 7 | bit_i : in std_logic; 8 | bit_o : out std_logic 9 | ); 10 | end entity switchReal_synch; 11 | 12 | architecture bhv of switchReal_synch is 13 | signal flipflops : std_logic_vector(stages -1 downto 0) := (others => '0'); 14 | attribute ASYNC_REG : string; 15 | attribute ASYNC_REG of flipflops: signal is "true"; 16 | begin 17 | bit_o <= flipflops(stages-1); 18 | 19 | sync_proc: process(clk_i) 20 | begin 21 | if rising_edge(clk_i) then 22 | flipflops <= flipflops(stages-2 downto 0) & bit_i; 23 | end if; 24 | end process; 25 | end bhv; 26 | -------------------------------------------------------------------------------- /switchReal/switchReal.xdc: -------------------------------------------------------------------------------- 1 | set_false_path -from [get_pins -hier *witchInput_s*/C] 2 | -------------------------------------------------------------------------------- /syncTrigStream/hdl/syncTrigStream_sync_bit.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2018/11/30 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity syncTrigStream_sync_bit is 10 | generic (stages : natural := 3); 11 | port ( 12 | ref_clk_i : in std_logic; 13 | clk_i : in std_logic; 14 | bit_i : in std_logic; 15 | bit_o : out std_logic 16 | ); 17 | end entity syncTrigStream_sync_bit; 18 | 19 | architecture bhv of syncTrigStream_sync_bit is 20 | signal sync_stage0_s, sync_stage1_s: std_logic; 21 | signal sync_stage2_s, sync_stage3_s: std_logic; 22 | attribute ASYNC_REG : string; 23 | attribute ASYNC_REG of sync_stage1_s: signal is "true"; 24 | attribute ASYNC_REG of sync_stage2_s: signal is "true"; 25 | begin 26 | ref_proc: process(ref_clk_i) begin 27 | if rising_edge(ref_clk_i) then 28 | sync_stage0_s <= bit_i; 29 | end if; 30 | end process; 31 | 32 | sync_proc: process(clk_i) 33 | begin 34 | if rising_edge(clk_i) then 35 | sync_stage1_s <= sync_stage0_s; 36 | sync_stage2_s <= sync_stage1_s; 37 | sync_stage3_s <= sync_stage2_s; 38 | end if; 39 | end process; 40 | bit_o <= sync_stage3_s; 41 | end bhv; 42 | -------------------------------------------------------------------------------- /syncTrigStream/hdl/syncTrigStream_sync_vector.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) Copyright: OscillatorIMP Digital 3 | -- Author : Gwenhael Goavec-Merou 4 | -- Creation date : 2016/05/25 5 | --------------------------------------------------------------------------- 6 | library IEEE; 7 | use IEEE.STD_LOGIC_1164.ALL; 8 | 9 | entity syncTrigStream_sync_vector is 10 | generic (stages : natural := 3; 11 | DATA : natural := 16); 12 | port ( 13 | ref_clk_i : in std_logic; 14 | clk_i : in std_logic; 15 | bit_i : in std_logic_vector(DATA-1 downto 0); 16 | bit_o : out std_logic_vector(DATA-1 downto 0) 17 | ); 18 | end entity syncTrigStream_sync_vector; 19 | 20 | architecture bhv of syncTrigStream_sync_vector is 21 | signal sync_vect_stage0_s: std_logic_vector(DATA-1 downto 0); 22 | type data_tab is array (natural range <>) of std_logic_vector(DATA-1 downto 0); 23 | signal flipflops_vect : data_tab(stages -1 downto 0) := (others => (others => '0')); 24 | attribute ASYNC_REG : string; 25 | attribute ASYNC_REG of flipflops_vect: signal is "true"; 26 | begin 27 | ref_proc: process(ref_clk_i) begin 28 | if rising_edge(ref_clk_i) then 29 | sync_vect_stage0_s <= bit_i; 30 | end if; 31 | end process; 32 | 33 | sync_proc: process(clk_i) 34 | begin 35 | if rising_edge(clk_i) then 36 | flipflops_vect(0) <= sync_vect_stage0_s; 37 | flipflops_vect(stages-1 downto 1) 38 | <= flipflops_vect(stages-2 downto 0); 39 | end if; 40 | end process; 41 | bit_o <= flipflops_vect(stages-1); 42 | end bhv; 43 | -------------------------------------------------------------------------------- /syncTrigStream/simulation/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL_LANG ?= vhdl 2 | SIM = ghdl 3 | 4 | PWD=$(shell pwd) 5 | WPWD=$(shell pwd) 6 | PLUSARGS=--vcdgz=$(WPWD)/build/waveform.vcdgz --wave=$(WPWD)/build/waveform.ghw 7 | 8 | VHDL_SOURCES=$(WPWD)/../hdl/syncTrigStream_logic.vhd 9 | 10 | VHDL_SOURCES+=$(WPWD)/top_syncTrigStream.vhd 11 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file: 12 | TOPLEVEL=top_genpulsetwowaycplx 13 | # MODULE is the name of the Python test file: 14 | MODULE=top_syncTrigStream_tb 15 | include $(shell cocotb-config --makefiles)/Makefile.inc 16 | include $(shell cocotb-config --makefiles)/Makefile.sim 17 | 18 | view: 19 | gtkwave -a top_syncTrigStream.gtkw build/waveform.ghw 20 | -------------------------------------------------------------------------------- /syncTrigStream/simulation/top_syncTrigStream_tb.py: -------------------------------------------------------------------------------- 1 | import random 2 | import logging 3 | 4 | import cocotb 5 | 6 | from cocotb.clock import Clock 7 | from cocotb.triggers import Timer, RisingEdge, FallingEdge 8 | 9 | from math import * 10 | 11 | clock_period = 100 12 | 13 | @cocotb.coroutine 14 | def reset_dut(reset_n, duration): 15 | reset_n <= 1 16 | yield Timer(duration) 17 | reset_n <= 0 18 | reset_n._log.debug("Reset complete") 19 | 20 | @cocotb.coroutine 21 | def clock_gen(signal, period=10000): 22 | while True: 23 | signal <= 0 24 | yield Timer(period/2) 25 | signal <= 1 26 | yield Timer(period/2) 27 | 28 | nb_sample = 2048 * 4 29 | 30 | @cocotb.test() 31 | def verif_lt(dut): 32 | reset_n = dut.rst_i 33 | dut.data_en_i <= 0 34 | dut.data1_i_i <= 0 35 | dut.data1_q_i <= 0 36 | dut.data2_i_i <= 0 37 | dut.data2_q_i <= 0 38 | dut.period_cnt_i <= 100 39 | dut.duty_cnt_i <= 10 40 | 41 | cocotb.fork(clock_gen(dut.clk_i, period=clock_period)) 42 | yield reset_dut(reset_n, 500) 43 | 44 | dut._log.debug("After reset") 45 | yield RisingEdge(dut.clk_i) 46 | yield RisingEdge(dut.clk_i) 47 | for i in range (0, nb_sample): 48 | dut.data1_i_i <= i 49 | dut.data1_q_i <= i+10 50 | dut.data2_i_i <= i+20 51 | dut.data2_q_i <= i+30 52 | dut.data_en_i <= 1 53 | yield RisingEdge(dut.clk_i) 54 | dut.data_en_i <= 0 55 | for ii in range (0, 3): 56 | yield RisingEdge(dut.clk_i) 57 | -------------------------------------------------------------------------------- /syncTrigStream/syncTrigStream.xdc: -------------------------------------------------------------------------------- 1 | set_property ASYNC_REG TRUE \ 2 | [get_cells -hier flipflops*_reg[0]] \ 3 | [get_cells -hier flipflops*_reg[1]] 4 | set_false_path \ 5 | -from [get_cells -hier sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ 6 | -to [get_cells -hier flipflops*_reg[0] -filter {IS_SEQUENTIAL}] 7 | 8 | set_property ASYNC_REG TRUE \ 9 | [get_cells -hier flipflops_vect*_reg[0][*]] \ 10 | [get_cells -hier flipflops_vect*_reg[1][*]] 11 | set_false_path \ 12 | -from [get_cells -hier sync_vect_stage0_*_reg[*] -filter {IS_SEQUENTIAL}] \ 13 | -to [get_cells -hier flipflops_vect*_reg[0][*] -filter {IS_SEQUENTIAL}] 14 | -------------------------------------------------------------------------------- /tools/README.md: -------------------------------------------------------------------------------- 1 | # Tools: 2 | 3 | ## print_businterfaces.py 4 | Tools to display IP (component.xml) parameters: 5 | - VLNV 6 | - parameters availables with default value 7 | - interfaces 8 | - ports 9 | 10 | ### Dependencies 11 | - ipyxact https://github.com/trabucayre/ipyxact fork 12 | - `git clone https://github.com/trabucayre/ipyxact.git` 13 | - `cd ipyxact` 14 | - `python3 setup.py install --user` 15 | - python3 colored package 16 | - `sudo apt-get install python3-colored` or 17 | - `pip3 install colored --user` 18 | 19 | ### How to use 20 | ```bash 21 | print_businterfaces.py /somewhere/fpga_ip/IPdirectory 22 | ``` 23 | IPdirectory is the root directory of an IP (where component.xml is stored). 24 | -------------------------------------------------------------------------------- /windowReal/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | out*.dat 2 | *.txt 3 | -------------------------------------------------------------------------------- /windowReal/simulation/ghdl/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | out*.dat 3 | -------------------------------------------------------------------------------- /windowReal/simulation/ghdl/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_windowReal 2 | TESTBENCH_FILE=../$(PROJECT)_tb.vhd 3 | SIMTOP =$(PROJECT)_tb 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | FILES=../readFromFile.vhd ../ram_storage16.vhd ../../hdl/windowReal_ram.vhd ../../hdl/windowReal_logic.vhd 10 | SIMDIR=simu 11 | 12 | VIEW_CMD = gtkwave 13 | 14 | all : run 15 | 16 | # Run target 17 | run:$(SIMDIR)/$(SIMTOP).ghw 18 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 19 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 20 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 21 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 22 | 23 | # Targets to analyze libraries 24 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 25 | mkdir -p $(SIMDIR) 26 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 27 | 28 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 29 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 30 | 31 | clean: 32 | $(GHDL) --clean --workdir=simu 33 | -rm -rf simu 34 | force: 35 | -------------------------------------------------------------------------------- /windowReal/simulation/isim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/csh -f 2 | echo Simulation Tool: ISIM 3 | fuse work.top_windowReal_tb -prj windowReal.prj -L unisim -L secureip -timeprecision_vhdl fs -o windowReal 4 | ./windowReal -gui -tclbatch isim.tcl -wdb windowReal.wdb 5 | echo done 6 | 7 | -------------------------------------------------------------------------------- /windowReal/simulation/isim.tcl: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | isim set radix hex 3 | #wave add /sim_tb_top/ 4 | wave add /top_windowReal_tb 5 | run 60 us 6 | quit 7 | -------------------------------------------------------------------------------- /windowReal/simulation/testC/.gitignore: -------------------------------------------------------------------------------- 1 | computeFir 2 | res*.dat 3 | res*.dat 4 | test*.txt 5 | -------------------------------------------------------------------------------- /windowReal/simulation/testC/Makefile: -------------------------------------------------------------------------------- 1 | CFLAGS+=-g -W -Wall 2 | LDFLAGS=-lm 3 | EXEC_NAME=computeWindow 4 | OBJS=main.o 5 | 6 | all: $(EXEC_NAME) 7 | 8 | $(EXEC_NAME): $(OBJS) 9 | $(CC) -o $@ $^ $(LDFLAGS) 10 | 11 | %.o: %.c 12 | $(CC) $(CFLAGS) -o $@ -c $< 13 | 14 | clean: 15 | rm -rf $(OBJS) 16 | rm -f $(EXEC_NAME) 17 | rm -f *.c~ *.h~ Makefile~ 18 | rm -f res*.dat 19 | rm -f test*.txt 20 | 21 | .PHONY: clean 22 | 23 | 24 | -------------------------------------------------------------------------------- /windowReal/simulation/windowReal.prj: -------------------------------------------------------------------------------- 1 | vhdl work top_windowReal_tb.vhd 2 | vhdl work ../hdl/windowReal_logic.vhd 3 | vhdl work readFromFile.vhd 4 | vhdl work ram_storage16.vhd 5 | vhdl work ../hdl/windowReal_ram.vhd 6 | 7 | -------------------------------------------------------------------------------- /xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex_correl.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.all; 4 | 5 | entity xcorr_prn_slow_complex_correl is 6 | generic ( 7 | IN_SIZE : natural := 16; 8 | OUT_SIZE : natural := 32 9 | ); 10 | port ( 11 | -- input 12 | end_cross_i : in std_logic; 13 | data_en_i : in std_logic; 14 | accum_i : in std_logic_vector(OUT_SIZE-1 downto 0); 15 | --data_i : in std_logic_vector(IN_SIZE-1 downto 0); 16 | data_pos_i : in std_logic_vector(IN_SIZE-1 downto 0); 17 | data_neg_i : in std_logic_vector(IN_SIZE-1 downto 0); 18 | prn_i : in std_logic; 19 | -- output 20 | data_en_o : out std_logic; 21 | data_end_o : out std_logic; 22 | data_o : out std_logic_vector(OUT_SIZE-1 downto 0) 23 | ); 24 | end entity; 25 | 26 | architecture rtl of xcorr_prn_slow_complex_correl is 27 | -- add/sub 28 | signal val_sub_s, val_add_s, val_s : signed(IN_SIZE-1 downto 0); 29 | begin 30 | val_add_s <= signed(data_pos_i); --signed(data_i); 31 | val_sub_s <= signed(data_neg_i); ---signed(data_i); 32 | val_s <= val_add_s when prn_i = '1' else val_sub_s; 33 | 34 | data_o <= std_logic_vector(signed(accum_i) + val_s); 35 | data_end_o <= data_en_i and end_cross_i; 36 | data_en_o <= data_en_i; 37 | 38 | end architecture rtl; 39 | -------------------------------------------------------------------------------- /xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex_ram.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.numeric_std.all; 4 | 5 | entity xcorr_prn_slow_complex_ram is 6 | generic ( 7 | DATA : integer := 72; 8 | ADDR : integer := 10 9 | ); 10 | port ( 11 | clk_a : in std_logic; 12 | clk_b : in std_logic; 13 | -- state machine interface 14 | we_a : in std_logic; 15 | addr_a: in std_logic_vector(ADDR-1 downto 0); 16 | din_a : in std_logic_vector(DATA-1 downto 0); 17 | addr_b: in std_logic_vector(ADDR-1 downto 0); 18 | dout_b: out std_logic_vector(DATA-1 downto 0) 19 | ); 20 | end entity; 21 | 22 | architecture rtl of xcorr_prn_slow_complex_ram is 23 | -- Shared memory 24 | type mem_type is array ( (2**ADDR)-1 downto 0 ) of std_logic_vector(DATA-1 downto 0); 25 | signal mem : mem_type := (others => (others => '0')); 26 | attribute ram_style : string; 27 | attribute ram_style of mem : signal is "block"; 28 | begin 29 | 30 | -- Port A 31 | process(clk_a) 32 | begin 33 | if(clk_a'event and clk_a='1') then 34 | if(we_a='1') then 35 | mem(to_integer(unsigned(addr_a))) <= din_a; 36 | end if; 37 | end if; 38 | end process; 39 | 40 | -- Port B 41 | process(clk_b) 42 | begin 43 | if(clk_b'event and clk_b='1') then 44 | dout_b <= mem(to_integer(unsigned(addr_b))); 45 | end if; 46 | end process; 47 | 48 | end architecture rtl; 49 | -------------------------------------------------------------------------------- /xcorr_prn_slow_complex/simuC/.gitignore: -------------------------------------------------------------------------------- 1 | *.txt 2 | main 3 | -------------------------------------------------------------------------------- /xcorr_prn_slow_complex/simulation/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | *.xmsgs 3 | *.cmd 4 | *.txt 5 | -------------------------------------------------------------------------------- /xcorr_prn_slow_complex/simulation/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT=top_xcorr_prn_slow_complex 2 | SIMTOP =$(PROJECT)_tb 3 | TESTBENCH_FILE=$(SIMTOP).vhd 4 | 5 | GHDL=ghdl 6 | GHDLFLAGS=--workdir=simu --work=work 7 | GHDLRUNFLAGS=--assert-level=error 8 | GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic --warn-default-binding 9 | 10 | FILES=../hdl/xcorr_prn_slow_complex_ram.vhd \ 11 | ../hdl/xcorr_prn_slow_complex_correl.vhd \ 12 | ../hdl/xcorr_prn_slow_complex_mux.vhd \ 13 | ../hdl/xcorr_prn_slow_complex.vhd 14 | FILES+=../../cacode/hdl/cacode_g1_gen.vhd ../../cacode/hdl/cacode_g2_gen.vhd ../../cacode/hdl/cacode.vhd 15 | 16 | SIMDIR=simu 17 | 18 | VIEW_CMD = gtkwave 19 | 20 | all : run 21 | 22 | # Run target 23 | run:$(SIMDIR)/$(SIMTOP).ghw 24 | $(SIMDIR)/$(SIMTOP).ghw: $(SIMDIR)/work-obj93.cf 25 | $(GHDL) -c $(GHDLFLAGS) -e $(SIMTOP) 26 | $(GHDL) -c $(GHDLFLAGS) -r $(SIMTOP) $(GHDLRUNFLAGS) \ 27 | --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz --wave=$(SIMDIR)/$(SIMTOP).ghw 28 | 29 | # Targets to analyze libraries 30 | $(SIMDIR)/work-obj93.cf:$(FILES) $(TESTBENCH_FILE) 31 | mkdir -p $(SIMDIR) 32 | $(GHDL) -a $(GHDLFLAGS) $(GHDL_SIMU_FLAGS) $(FILES) $(TESTBENCH_FILE) 33 | 34 | ghdl-view: $(SIMDIR)/$(SIMTOP).ghw 35 | $(VIEW_CMD) $(SIMDIR)/$(SIMTOP).ghw -a $(PROJECT).gtkw 36 | 37 | clean: 38 | $(GHDL) --clean --workdir=simu 39 | -rm -rf simu 40 | -rm -rf result.txt 41 | force: 42 | -------------------------------------------------------------------------------- /xcorr_prn_slow_complex/simulation/isim/.gitignore: -------------------------------------------------------------------------------- 1 | isim 2 | xcorr_prn_slow_complex 3 | xcorr_prn_slow_complex.wdb 4 | -------------------------------------------------------------------------------- /xcorr_prn_slow_complex/simulation/isim/isim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/csh -f 2 | echo Simulation Tool: ISIM 3 | fuse work.top_xcorr_prn_slow_complex_tb -prj xcorr_prn_slow_complex.prj -L unisim -L secureip -timeprecision_vhdl fs -o xcorr_prn_slow_complex 4 | ./xcorr_prn_slow_complex -gui -tclbatch isim.tcl -wdb xcorr_prn_slow_complex.wdb 5 | #./xcorr_prn_slow_complex -gui -tclbatch isim.tcl -wdb xcorr_prn_slow_complex.wdb 6 | echo done 7 | 8 | -------------------------------------------------------------------------------- /xcorr_prn_slow_complex/simulation/isim/isim.tcl: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | isim set radix hex 3 | #wave add /sim_tb_top/ 4 | wave add /top_xcorr_prn_slow_complex_tb 5 | run 60 us 6 | #quit 7 | -------------------------------------------------------------------------------- /xcorr_prn_slow_complex/simulation/isim/xcorr_prn_slow_complex.prj: -------------------------------------------------------------------------------- 1 | vhdl work ../../hdl/xcorr_prn_slow_complex_ram.vhd 2 | vhdl work ../../hdl/xcorr_prn_slow_complex_correl.vhd 3 | vhdl work ../../hdl/xcorr_prn_slow_complex_mux.vhd 4 | vhdl work ../../hdl/xcorr_prn_slow_complex.vhd 5 | vhdl work /home/gwe/oscimp/fpga_ip/cacode/hdl/cacode_g1_gen.vhd 6 | vhdl work /home/gwe/oscimp/fpga_ip/cacode/hdl/cacode_g2_gen.vhd 7 | vhdl work /home/gwe/oscimp/fpga_ip/cacode/hdl/cacode.vhd 8 | vhdl work ../top_xcorr_prn_slow_complex_tb.vhd 9 | -------------------------------------------------------------------------------- /xcorr_prn_slow_complex/simulation/test.m: -------------------------------------------------------------------------------- 1 | pkg load signal 2 | close all; 3 | %load result.txt 4 | %res = load("../simuC/toto"); 5 | res = load("result.txt"); 6 | 7 | %for k=1:32 8 | %for k=10:20 9 | for k=21:32 10 | x = xcorr_prn_slow_complex(k); 11 | plot(xcorr(x-mean(x), res(:,k)-mean(res(:,k)))) 12 | title(num2str(k)) 13 | figure 14 | end 15 | 16 | %x = xcorr_prn_slow_complex(1); 17 | %plot(xcorr(x-mean(x), res(:,1)-mean(res(:,1)))) 18 | %plot(xcorr(x, res-mean(res))) 19 | -------------------------------------------------------------------------------- /xcorr_prn_slow_complex/xcorr_prn_slow_complex.xdc: -------------------------------------------------------------------------------- 1 | set_false_path -from [get_pins -hier *ext_rst_s*/C] 2 | --------------------------------------------------------------------------------