├── .gitignore ├── .gitmodules ├── LICENSE.md ├── README.md ├── doc ├── .gitignore ├── IP │ ├── MUX_Nto1.md │ ├── README.md │ ├── add_const.md │ ├── adder_subtractor.md │ ├── axi_to_dac.md │ ├── data_to_ram.md │ ├── expander.md │ ├── fft.md │ ├── figures │ │ ├── add_const_reg_offset_h.json │ │ ├── add_const_reg_offset_h.svg │ │ ├── add_const_reg_offset_l.json │ │ ├── add_const_reg_offset_l.svg │ │ ├── adderComplex.json │ │ ├── adderComplex.svg │ │ ├── adderReal.json │ │ ├── adderReal.svg │ │ ├── axi_to_dac_en.json │ │ ├── axi_to_dac_en.svg │ │ ├── axi_to_dac_reg_conf.json │ │ ├── axi_to_dac_reg_conf.svg │ │ ├── axi_to_dac_reg_dataa.json │ │ ├── axi_to_dac_reg_dataa.svg │ │ ├── axi_to_dac_reg_datab.json │ │ ├── axi_to_dac_reg_datab.svg │ │ ├── axi_to_dac_reg_id.json │ │ ├── axi_to_dac_reg_id.svg │ │ ├── axi_to_dac_sync.json │ │ ├── axi_to_dac_sync.svg │ │ ├── cplx_toFrom_axiStream.json │ │ ├── cplx_toFrom_axiStream.svg │ │ ├── data_to_ram_reg_data.json │ │ ├── data_to_ram_reg_data.svg │ │ ├── data_to_ram_reg_start.json │ │ ├── data_to_ram_reg_start.svg │ │ ├── data_to_ram_reg_status.json │ │ ├── data_to_ram_reg_status.svg │ │ ├── dynamic_shifter.svg │ │ ├── expander.svg │ │ ├── expander2.svg │ │ ├── fft.png │ │ ├── fft_plot.png │ │ ├── howto │ │ ├── iir_lpf_real2.svg │ │ ├── lutGeneratorComplex.png │ │ ├── lutGeneratorComplex_reg_datai.json │ │ ├── lutGeneratorComplex_reg_datai.svg │ │ ├── lutGeneratorComplex_reg_dataq.json │ │ ├── lutGeneratorComplex_reg_dataq.svg │ │ ├── lutGeneratorComplex_reg_enable.json │ │ ├── lutGeneratorComplex_reg_enable.svg │ │ ├── lutGeneratorComplex_reg_prescaler.json │ │ ├── lutGeneratorComplex_reg_prescaler.svg │ │ ├── lutGeneratorComplex_reg_ram_length.json │ │ ├── lutGeneratorComplex_reg_ram_length.svg │ │ ├── lutGeneratorComplex_reg_rst_addr.json │ │ ├── lutGeneratorComplex_reg_rst_addr.svg │ │ ├── magnitude.json │ │ ├── magnitude.svg │ │ ├── mixerComplex_sin.json │ │ ├── mixerComplex_sin.svg │ │ ├── mixer_sin.json │ │ ├── mixer_sin.svg │ │ ├── pidv3_axi.fig │ │ ├── pidv3_axi.svg │ │ ├── real_toFrom_axiStream.json │ │ ├── real_toFrom_axiStream.svg │ │ ├── redpitaya_converters_12.png │ │ ├── redpitaya_converters_12_ws.png │ │ ├── sampleCounter.json │ │ ├── sampleCounter.svg │ │ ├── shifter.svg │ │ ├── shifter2.svg │ │ ├── shifter_dyn.svg │ │ ├── shifter_dyn2.svg │ │ ├── switchReal.json │ │ ├── switchReal.svg │ │ ├── switch_reg_id.json │ │ ├── switch_reg_id.svg │ │ ├── switch_reg_input.json │ │ ├── switch_reg_input.svg │ │ ├── unwrap_phase_diff_rewritten_logic.svg │ │ ├── windowReal.png │ │ └── windowReal_blackmanharris.png │ ├── fir.md │ ├── iir_lpf.md │ ├── lutGenerator.md │ ├── magnitude.md │ ├── mixer.md │ ├── mixer_multiplier.md │ ├── nco_counter.md │ ├── prn20b.md │ ├── realOrComplex_to_axiStream_and_axiStream_to_realOrComplex.md │ ├── redpitaya_converters_12.md │ ├── sampleCounter.md │ ├── shifter.md │ ├── switch.md │ ├── unwrap_phase_diff.md │ └── windowReal.md ├── conferences │ ├── fosdem2020 │ │ ├── 2xcorr_2PRN_NCO.pdf │ │ ├── 2xcorr_2PRN_NCO_crop.pdf │ │ ├── DSC_0108.jpg │ │ ├── DSC_0275.JPG │ │ ├── DSC_0279.JPG │ │ ├── RC_filter.pdf │ │ ├── cdma.fig │ │ ├── cdma.pdf │ │ ├── fig2.pdf │ │ ├── fosdem2020.pdf │ │ ├── fosdem2020.tex │ │ ├── imgsrc │ │ │ └── plutoSchema.fig │ │ ├── interfaceClose.png │ │ ├── interfaceOpen.png │ │ ├── plutoSchema.pdf │ │ ├── pluto_embedded_audio.png │ │ ├── pluto_gpio_connector.pdf │ │ ├── plutopluto-oscimpDigital-makerspace.pdf │ │ └── xcorr_pluto2.png │ ├── gnuradioDays2019 │ │ ├── DSC_0050.JPG │ │ ├── DSC_0091.JPG │ │ ├── IMG_20190118_125305.jpg │ │ ├── architecture.pdf │ │ ├── img │ │ │ ├── displayIf.png │ │ │ ├── oscimpDigital_github_qrcode.png │ │ │ ├── plutosdr_github_qrcode.png │ │ │ ├── redpitaya_github_qrcode.png │ │ │ ├── roadmap2019.pdf │ │ │ ├── schema_design.pdf │ │ │ ├── schema_zc706.pdf │ │ │ ├── sortie_affichage_resultat_radar.pdf │ │ │ ├── structApp.fig │ │ │ ├── structApp.pdf │ │ │ ├── structRepo.pdf │ │ │ ├── structRepo.png │ │ │ ├── structureEco.pdf │ │ │ ├── structureIp.pdf │ │ │ ├── tutorial3.xcf │ │ │ ├── tutorial3_ann.pdf │ │ │ ├── tutorial3_ann.png │ │ │ └── tutorial3_ann.svg │ │ ├── imgsrc │ │ │ ├── roadmap2019.fig │ │ │ ├── schema_zc706.fig │ │ │ ├── schema_zc706.pdf │ │ │ ├── screen_qt_usrp_quad_10MHz_SMA100_20180119_1525.png │ │ │ ├── structApp.xfig │ │ │ ├── structRepo.fig │ │ │ └── tutorial3.pdf │ │ ├── pnm_2_ch_noise_floor_setup2.pdf │ │ ├── pnm_2_ch_noise_floor_setup2.pdf_t │ │ ├── presentationEcoSystem_GRDays2019.pdf │ │ ├── presentationEcoSystem_GRDays2019.tex │ │ └── spi2.jpg │ ├── makerspace2019 │ │ ├── A4logos.png │ │ ├── cdma.fig │ │ ├── cdma.pdf │ │ ├── fig2.pdf │ │ ├── logo_femto.pdf │ │ ├── makerspace.pdf │ │ └── makerspace.tex │ └── teaching │ │ ├── DSC_0050.JPG │ │ └── teaching_fpga.tex ├── external_clock_and_undersampling_PCB │ ├── README.md │ ├── all.pdf │ ├── empty.kicad_wks │ ├── extension_clk_adc-backups │ │ └── extension_clk_adc-2024-11-01_094340.zip │ ├── extension_clk_adc-cache.lib │ ├── extension_clk_adc-rescue.kicad_sym │ ├── extension_clk_adc.brd │ ├── extension_clk_adc.kicad_pcb │ ├── extension_clk_adc.kicad_prl │ ├── extension_clk_adc.kicad_pro │ ├── extension_clk_adc.kicad_sch │ ├── extension_clk_adc.pretty │ │ ├── AT224-1A.kicad_mod │ │ ├── C0402.kicad_mod │ │ ├── C0603.kicad_mod │ │ ├── DBL6.kicad_mod │ │ ├── R0603.kicad_mod │ │ ├── SMA_BORD.kicad_mod │ │ └── SMD1,27-2,54.kicad_mod │ ├── extension_clk_adc.sch │ ├── fp-info-cache │ ├── go.m │ ├── report.pdf │ ├── report.tex │ └── sym-lib-table ├── install_bootgen.png ├── install_vivado.png ├── install_vivado_webpack.png └── tutorials │ ├── plutosdr │ ├── 1-adalmPluto_within_OscimpDigital │ │ ├── 1-adalmPluto_within_OscimpDigital.pdf │ │ ├── 1-adalmPluto_within_OscimpDigital.tex │ │ ├── Makefile │ │ ├── README.md │ │ ├── dfu_images │ │ │ ├── pluto_bitstream_with_AXI.dfu │ │ │ └── pluto_bitstream_without_AXI.dfu │ │ ├── figures │ │ │ ├── 1.png │ │ │ ├── 100kHz_250kHz.pdf │ │ │ ├── 2.png │ │ │ ├── 2019-02-12-165739_799x493_scrot.png │ │ │ ├── 2019-02-12-170033_876x543_scrot.png │ │ │ ├── 2019-02-12-171944_1482x789_scrot.png │ │ │ ├── 2019-02-12-171957_1072x583_scrot.png │ │ │ ├── 2019-03-07-091613_1058x562_scrot.png │ │ │ ├── 20190213_105039.jpg │ │ │ ├── 20190213_105039_320.jpg │ │ │ ├── 20190213_105039_640.jpg │ │ │ ├── 20190213_105142.jpg │ │ │ ├── 20190213_105142_320.jpg │ │ │ ├── 20190213_105142_640.jpg │ │ │ ├── NCO.pdf │ │ │ ├── address.png │ │ │ ├── beatnote_pluto_scheme.fig │ │ │ ├── beatnote_pluto_scheme.pdf │ │ │ ├── danger.pdf │ │ │ ├── gnuradio.png │ │ │ ├── iio_fft_iq_data.pdf │ │ │ ├── iio_iq_data.pdf │ │ │ ├── pluto-oscimpDigital-objective.fig │ │ │ └── pluto-oscimpDigital-objective.pdf │ │ ├── project1 │ │ │ ├── app │ │ │ │ ├── Makefile │ │ │ │ ├── data │ │ │ │ │ ├── NCO.eps.gz │ │ │ │ │ ├── data_050kHz.dat.gz │ │ │ │ │ ├── data_100kHz.dat.gz │ │ │ │ │ ├── data_200kHz.dat.gz │ │ │ │ │ ├── data_250kHz.dat.gz │ │ │ │ │ ├── data_NCO.dat.gz │ │ │ │ │ └── go.m │ │ │ │ ├── main.c │ │ │ │ ├── project1.dts │ │ │ │ └── project1_us.sh │ │ │ ├── design │ │ │ │ ├── Makefile │ │ │ │ ├── system_bd.tcl │ │ │ │ ├── system_constr.xdc │ │ │ │ ├── system_project.tcl │ │ │ │ └── system_top.v │ │ │ └── module_generator.xml │ │ └── project2 │ │ │ ├── app │ │ │ ├── Makefile │ │ │ ├── main.c │ │ │ └── project2.dts │ │ │ ├── design │ │ │ ├── Makefile │ │ │ ├── system_bd.tcl │ │ │ ├── system_constr.xdc │ │ │ ├── system_project.tcl │ │ │ └── system_top.v │ │ │ └── module_generator.xml │ ├── 2-PRN_on_PL │ │ ├── 190524gps_xcorr │ │ │ ├── cacode.m │ │ │ ├── go.m │ │ │ ├── gogps_bin.m │ │ │ ├── gps.bin │ │ │ ├── gps_bin.pdf │ │ │ ├── gps_bin100Hz.eps.gz │ │ │ ├── gps_bin100Hz.pdf │ │ │ ├── gps_bin500Hz.eps.gz │ │ │ ├── gps_bin500Hz.pdf │ │ │ ├── gps_plutosdr.eps.gz │ │ │ ├── gps_plutosdr.pdf │ │ │ ├── max_00.dat.gz │ │ │ ├── max_01.dat.gz │ │ │ ├── max_02.dat.gz │ │ │ ├── max_03.dat.gz │ │ │ ├── max_04.dat.gz │ │ │ ├── max_05.dat.gz │ │ │ ├── max_06.dat.gz │ │ │ ├── max_07.dat.gz │ │ │ ├── max_08.dat.gz │ │ │ ├── max_09.dat.gz │ │ │ ├── max_10.dat.gz │ │ │ ├── max_11.dat.gz │ │ │ ├── max_12.dat.gz │ │ │ ├── max_13.dat.gz │ │ │ ├── max_14.dat.gz │ │ │ ├── max_15.dat.gz │ │ │ ├── max_16.dat.gz │ │ │ ├── max_17.dat.gz │ │ │ ├── max_18.dat.gz │ │ │ ├── max_19.dat.gz │ │ │ ├── max_20.dat.gz │ │ │ ├── max_21.dat.gz │ │ │ ├── max_22.dat.gz │ │ │ ├── max_23.dat.gz │ │ │ ├── max_24.dat.gz │ │ │ ├── max_25.dat.gz │ │ │ ├── max_26.dat.gz │ │ │ ├── max_27.dat.gz │ │ │ ├── max_28.dat.gz │ │ │ ├── max_29.dat.gz │ │ │ ├── max_30.dat.gz │ │ │ ├── max_31.dat.gz │ │ │ └── read_complex_binary.m │ │ ├── 2-PRN_on_PL.pdf │ │ ├── 2-PRN_on_PL.tex │ │ ├── Makefile │ │ ├── README.md │ │ ├── images │ │ │ ├── 1xcorr_1PRN.bit │ │ │ ├── 1xcorr_1PRN.pdf │ │ │ ├── 1xcorr_1PRN_NCO.bit │ │ │ ├── 1xcorr_1PRN_NCO.pdf │ │ │ ├── 1xcorr_1PRN_NCO_crop.pdf │ │ │ ├── 1xcorr_1PRN_NCOconfig.png │ │ │ ├── 1xcorr_1PRN_config.png │ │ │ ├── 1xcorr_1PRN_crop.pdf │ │ │ ├── 2xcorr_2PRN_NCO.bit │ │ │ ├── 2xcorr_2PRN_NCO.pdf │ │ │ ├── 2xcorr_2PRN_NCO_crop.pdf │ │ │ ├── 2xcorr_2PRN_NCOconfig.png │ │ │ ├── 3all.bit │ │ │ ├── DSC_0275.JPG │ │ │ ├── DSC_0279.JPG │ │ │ ├── gps_plutosdr.png │ │ │ ├── pluto-oscimpDigital-objective.fig │ │ │ ├── pluto-oscimpDigital-objective.pdf │ │ │ ├── plutopluto-oscimpDigital-makerspace.fig │ │ │ ├── plutopluto-oscimpDigital-makerspace.pdf │ │ │ ├── xcorr_pluto.grc │ │ │ ├── xcorr_pluto1.png │ │ │ ├── xcorr_pluto2.png │ │ │ ├── xcorr_pluto3g.png │ │ │ ├── xcorr_pluto3ng.png │ │ │ ├── xcorr_plutogrc1.png │ │ │ └── xcorr_plutogrc2.png │ │ ├── project_gps │ │ │ ├── app │ │ │ │ ├── Makefile │ │ │ │ ├── go.m │ │ │ │ ├── main.c │ │ │ │ ├── project_gps.dts │ │ │ │ ├── top_block.py │ │ │ │ └── xcorr_pluto.grc │ │ │ ├── design │ │ │ │ ├── Makefile │ │ │ │ ├── system_bd.tcl │ │ │ │ ├── system_constr.xdc │ │ │ │ ├── system_project.tcl │ │ │ │ └── system_top.v │ │ │ └── project_gps.xml │ │ ├── project_prn │ │ │ ├── app │ │ │ │ ├── Makefile │ │ │ │ ├── main.c │ │ │ │ ├── prn_demo.grc │ │ │ │ ├── project_prn.dts │ │ │ │ └── xcorr_pluto.grc │ │ │ ├── design │ │ │ │ ├── Makefile │ │ │ │ ├── system_bd.tcl │ │ │ │ ├── system_constr.xdc │ │ │ │ ├── system_project.tcl │ │ │ │ └── system_top.v │ │ │ └── project_prn.xml │ │ └── results │ │ │ ├── data_closed1.bin │ │ │ ├── data_load1.bin │ │ │ ├── data_open1.bin │ │ │ ├── example1.eps.gz │ │ │ ├── example1.pdf │ │ │ ├── go1.m │ │ │ └── readme.jmf │ └── 99-gnuradio-audio │ │ ├── 1-gnuradio-audio.pdf │ │ ├── 1-gnuradio-audio.tex │ │ ├── Makefile │ │ ├── README.md │ │ ├── audio.dts │ │ ├── cpp_signal_to_audio │ │ ├── Makefile │ │ └── main.cpp │ │ ├── design │ │ ├── Makefile │ │ ├── system_bd.tcl │ │ ├── system_constr.xdc │ │ ├── system_project.tcl │ │ └── system_top.v │ │ ├── figures │ │ ├── DSC_0108.jpg │ │ ├── RC_filter.fig │ │ ├── RC_filter.jpg │ │ ├── RC_filter.pdf │ │ ├── pluto_audio_ann.fig │ │ ├── pluto_audio_ann.jpg │ │ ├── pluto_audio_ann.pdf │ │ ├── pluto_embedded_audio.png │ │ ├── pluto_embedded_signal_to_audio.png │ │ ├── pluto_gpio_connector.fig │ │ ├── pluto_gpio_connector.jpg │ │ ├── pluto_gpio_connector.pdf │ │ ├── pluto_gpio_connector_ann.jpg │ │ └── signal_to_audio.png │ │ ├── pluto_embedded_audio.grc │ │ ├── pluto_embedded_signal_to_audio.grc │ │ ├── radioFM │ │ ├── Makefile │ │ └── main.cpp │ │ └── top_block.py │ └── redpitaya │ ├── 2-PL │ ├── 2-PL.pdf │ ├── 2-PL.tex │ ├── 2-PL_french.tex │ ├── Makefile │ ├── README.html │ ├── README.md │ ├── design │ │ ├── Makefile │ │ └── tutorial2.tcl │ └── figures │ │ ├── ADC_DAC_delay_1MHz.jpg │ │ ├── ADC_DAC_delay_4MHz.jpg │ │ ├── addSources.png │ │ ├── base_project.pdf │ │ ├── block_design.pdf │ │ ├── combinedADC_DAC.png │ │ ├── createHDLWrapper.png │ │ ├── createProj1.png │ │ ├── createProj_selectPart.png │ │ ├── createProj_selectPart2019.png │ │ ├── createProj_selectType.png │ │ ├── createProj_summary.png │ │ ├── objective.fig │ │ ├── objective.pdf │ │ └── objective.png │ ├── 3-PLPS │ ├── 3-fpga_PLPS.pdf │ ├── 3-fpga_PLPS.tex │ ├── 3-fpga_PLPS_french.tex │ ├── Makefile │ ├── README.md │ ├── app │ │ ├── Makefile │ │ ├── main.c │ │ ├── tutorial3.dts │ │ └── tutorial3_us.sh │ ├── design │ │ ├── Makefile │ │ └── tutorial3.tcl │ ├── figures │ │ ├── adresses.png │ │ ├── combinedADC_DAC_data2ram.png │ │ ├── design_1.pdf │ │ ├── mesures.eps.gz │ │ ├── mesures.pdf │ │ ├── mesures.png │ │ ├── objective.fig │ │ ├── objective.pdf │ │ └── objective.png │ ├── module_generator.xml │ └── results │ │ ├── data001MHz_m6dBm_in1.bin │ │ ├── data006MHz_m6dBm_in1.bin │ │ ├── data124MHz_m6dBm_in1.bin │ │ ├── data125MHz_m6dBm_in1.bin │ │ └── go.m │ ├── 4-FIR │ ├── 4-fpga_FIR.pdf │ ├── 4-fpga_FIR.tex │ ├── Makefile │ ├── README.md │ ├── app │ │ ├── Makefile │ │ ├── coefs.txt │ │ ├── main.c │ │ ├── tutorial4.dts │ │ └── tutorial4_us.sh │ ├── design │ │ ├── Makefile │ │ └── tutorial4.tcl │ ├── figures │ │ ├── address.png │ │ ├── combinedADC_DAC_data2ram_FIR.pdf │ │ ├── combinedADC_DAC_data2ram_FIR.png │ │ ├── mesures.eps.gz │ │ ├── mesures.pdf │ │ ├── mesures.png │ │ ├── objective.fig │ │ ├── objective.pdf │ │ ├── objective.png │ │ ├── structs.pdf │ │ └── structs.png │ ├── module_generator.xml │ └── results │ │ ├── 1MHz_m6dBm_FIReq16x1.bin │ │ ├── 1MHz_m6dBm_FIReq1x16.bin │ │ ├── 1MHz_m6dBm_FIReq4x4.bin │ │ ├── 24x1_0500kHz.jpg │ │ ├── 24x1_1500kHz.jpg │ │ ├── 24x1_5200kHz.jpg │ │ ├── 24x1_7000kHz.jpg │ │ ├── 6MHz_m6dBm_FIReq16x1.bin │ │ ├── 6MHz_m6dBm_FIReq4x4.bin │ │ ├── DSC_0368_3.JPG │ │ ├── DSC_0368_3ann.JPG │ │ ├── go.m │ │ ├── model.eps.gz │ │ ├── model.m │ │ ├── model.pdf │ │ └── model.png │ ├── 5-NCO │ ├── 5-fpga_NCO.pdf │ ├── 5-fpga_NCO.tex │ ├── Makefile │ ├── README.md │ ├── app │ │ ├── Makefile │ │ ├── main.c │ │ └── tutorial5.dts │ ├── design │ │ ├── Makefile │ │ └── tutorial5.tcl │ ├── figures │ │ ├── 10MHz0_0dBm.pdf │ │ ├── 10MHz0_0dBm.png │ │ ├── 10MHz1_0dBm.pdf │ │ ├── 10MHz1_0dBm.png │ │ ├── 11MHz0_0dBm.pdf │ │ ├── 11MHz0_0dBm.png │ │ ├── address.png │ │ ├── design_1.pdf │ │ ├── mesures.eps.gz │ │ ├── mesures.pdf │ │ ├── objective.fig │ │ ├── objective.pdf │ │ ├── objective.png │ │ ├── tutorial5.pdf │ │ └── tutorial5.png │ ├── go.m │ ├── module_generator.xml │ └── results │ │ ├── 10MHz0_0dBm.bin │ │ ├── 10MHz0_0dBm.eps.gz │ │ ├── 10MHz0_0dBm.pdf │ │ ├── 10MHz1_0dBm.bin │ │ ├── 10MHz1_0dBm.eps.gz │ │ ├── 10MHz1_0dBm.pdf │ │ ├── 11MHz0_0dBm.bin │ │ ├── 11MHz0_0dBm.eps.gz │ │ ├── 11MHz0_0dBm.pdf │ │ └── go.m │ ├── 6_TCL │ ├── 6-TCL.pdf │ ├── 6-TCL.tex │ ├── README.md │ ├── design │ │ ├── Makefile │ │ └── tutorial6.tcl │ └── figures │ │ ├── objective.fig │ │ ├── objective.pdf │ │ ├── objective.png │ │ ├── tutorial6.pdf │ │ └── tutorial6.png │ ├── 7_ADC_DMA │ ├── 14bit │ │ └── adcChanADmaDirect │ │ │ ├── app │ │ │ ├── Makefile │ │ │ ├── adcChanADmaDirect.dts │ │ │ └── main.c │ │ │ └── design │ │ │ ├── Makefile │ │ │ └── adcChanADmaDirect_dual.tcl │ └── syllabus_ADC.pdf │ └── 8_PRN_portable │ ├── 8_PRN_portable.pdf │ ├── 8_PRN_portable.tex │ ├── Makefile │ ├── README.md │ ├── app │ ├── Makefile │ ├── coefs.txt │ ├── main.c │ ├── prn_fir.dts │ └── prn_fir_us.sh │ ├── design │ ├── Makefile │ ├── addr.tcl │ ├── prn_fir.tcl │ └── prn_fir_usage_ressources.txt │ ├── figures │ ├── address.png │ ├── carac_fir1.pdf │ ├── carac_fir1.png │ ├── carac_fir2.pdf │ ├── carac_fir2.png │ ├── design_1.pdf │ ├── design_1.png │ ├── schema.fig │ ├── schema.pdf │ └── schema.png │ ├── go.sh │ ├── module_generator.xml │ ├── res.txt │ └── results │ ├── carac_fir1.eps.gz │ ├── carac_fir2.eps.gz │ ├── data15fois16.bin │ ├── data4fois16.bin │ └── go.m └── settings.sh.sample /.gitignore: -------------------------------------------------------------------------------- 1 | *.swp 2 | *.swo 3 | *.bif 4 | *.o 5 | *.dtbo 6 | *_us 7 | *.sh 8 | vivado_*.* 9 | *.xpr 10 | *.cache 11 | *.hw 12 | *.runs 13 | *.srcs 14 | pluto.ip_user_files 15 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "app"] 2 | path = app 3 | url = https://github.com/oscimp/app.git 4 | [submodule "fpga_ip"] 5 | path = fpga_ip 6 | url = https://github.com/oscimp/fpga_ip.git 7 | [submodule "lib"] 8 | path = lib 9 | url = https://github.com/oscimp/lib.git 10 | [submodule "linux_driver"] 11 | path = linux_driver 12 | url = https://github.com/oscimp/linux_driver.git 13 | [submodule "doc/Base_Designs_tuto"] 14 | path = doc/Base_Designs_tuto 15 | url = https://github.com/sdenis6/Base_Designs_tuto 16 | -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | Copyright or © or Copr. OscillatorIMP (2020) 2 | 3 | {gwenhael.goavec,jmfriedt}@femto-st.fr 4 | 5 | This software is a computer program whose purpose is to [describe 6 | functionalities and technical features of your software]. 7 | 8 | This software is governed by the CeCILL license under French law and 9 | abiding by the rules of distribution of free software. You can use, 10 | modify and/ or redistribute the software under the terms of the CeCILL 11 | license as circulated by CEA, CNRS and INRIA at the following URL 12 | "http://www.cecill.info". 13 | 14 | As a counterpart to the access to the source code and rights to copy, 15 | modify and redistribute granted by the license, users are provided only 16 | with a limited warranty and the software's author, the holder of the 17 | economic rights, and the successive licensors have only limited 18 | liability. 19 | 20 | In this respect, the user's attention is drawn to the risks associated 21 | with loading, using, modifying and/or developing or reproducing the 22 | software by the user in light of its specific status of free software, 23 | that may mean that it is complicated to manipulate, and that also 24 | therefore means that it is reserved for developers and experienced 25 | professionals having in-depth computer knowledge. Users are therefore 26 | encouraged to load and test the software's suitability as regards their 27 | requirements in conditions enabling the security of their systems and/or 28 | data to be ensured and, more generally, to use and operate it in the 29 | same conditions as regards security. 30 | 31 | The fact that you are presently reading this means that you have had 32 | knowledge of the CeCILL license and that you accept its terms. 33 | -------------------------------------------------------------------------------- /doc/.gitignore: -------------------------------------------------------------------------------- 1 | *.jou 2 | *.log 3 | *.bit.bin 4 | *.out 5 | *.aux 6 | *.log 7 | *.nav 8 | *.snm 9 | *.toc 10 | *.vrb 11 | tmp 12 | -------------------------------------------------------------------------------- /doc/IP/README.md: -------------------------------------------------------------------------------- 1 | **IP documentation** 2 | 3 | These documentations aim at providing the developer with 4 | * organization of the address space withing each IP, and bitwise function of registers when relevant 5 | * calling and configuring the IP from a TCL script 6 | * associated linux driver if provided 7 | * usage example 8 | -------------------------------------------------------------------------------- /doc/IP/expander.md: -------------------------------------------------------------------------------- 1 | # expanderReal/expanderComplex 2 | 3 | Used to remove MSB or extend MSB by adding a serie of '0' when unsigned or 4 | copiying MSB from input data. If input and output size are the same data are 5 | left unmodified. 6 | 7 | Unlike shifter: values are unmodified, only the size is modified. 8 | 9 | **Warning: removing too many bits may have to effect to corrupts data.** 10 | 11 | [expander_scheme]: figures/expander.svg "expander_scheme" 12 | ![expander block internal scheme][expander_scheme] 13 | 14 | __figure1__: expander block principle: when **out** > **in**: additionals MSBs are added 15 | (may be '0' when unsigned or the input data's MSB when signed), when **out** < **in**: MSBs 16 | are removed to fit the output size. 17 | 18 | ### **Internal propagation delay** 19 | 20 | 0 clock cycle 21 | 22 | ## IP 23 | 24 | * **expanderReal**: extend or truncate input data for real interface 25 | * **expanderComplex**: extend or truncate input data for complex interface 26 | 27 | ## Generic 28 | 29 | * **format**: (string) `signed`/`unsigned`. With `unsigned` and output largest 30 | expansion is done using a serie of '0', when `signed` input MSB is copied. 31 | * **DATA_IN_SIZE**: (natural) input data stream bus size (default: 16). 32 | * **DATA_OUT_SIZE**: (natural) output data stream bus size (default: 16). 33 | 34 | ## Ports and interfaces 35 | * **data_in**: input data stream (complex type for *expanderComplex* or 36 | real type for *expanderReal*). Size is fixed by **DATA_IN_SIZE** 37 | * **data_out**: output data stream (complex type for *expanderComplex* or 38 | real type for *expanderReal[_dyn]*). Size is fixed by **DATA_OUT_SIZE** 39 | 40 | ## Registers 41 | 42 | **NA** 43 | 44 | ## TCL instanciation and connection 45 | 46 | ```tcl 47 | # add expander with input in 32 bits and output in 16 bits. data stream is 48 | # signed 49 | add_ip_and_conf expanderReal expander { 50 | format signed \ 51 | DATA_IN_SIZE 32 \ 52 | DATA_OUT_SIZE 16] $shift 53 | 54 | # connect expander to other blocks. 55 | connect_intf $previous_block data_out expander data_in 56 | connect_intf expander data_out $next_block data_in 57 | ``` 58 | 59 | ## Driver 60 | 61 | **NA** 62 | 63 | ## Functions to configure IP 64 | 65 | **NA** 66 | -------------------------------------------------------------------------------- /doc/IP/figures/add_const_reg_offset_h.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "OFFSET_H", "bits": 32, "attr": "RW" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/add_const_reg_offset_l.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "OFFSET_L", "bits": 32, "attr": "RW" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/adderComplex.json: -------------------------------------------------------------------------------- 1 | {"signal": [ 2 | { "name": "clk", "wave": "p......", "period":2}, 3 | ["input", 4 | { "name": "data_en_i", "wave": "lh.....", "period":2}, 5 | { "name": "data1_i_i", "wave": "x333333", "phase":0.8, "period":2, "data":["d1_i1", "d1_i2", "d1_i3","d1_i4", "d1_i5", "d1_i6"]}, 6 | { "name": "data1_q_i", "wave": "x333333", "phase":0.8, "period":2, "data":["d1_q1", "d1_q2", "d1_q3","d1_q4", "d1_q5", "d1_q6"]}, 7 | { "name": "data2_i_i", "wave": "x333333", "phase":0.8, "period":2, "data":["d2_i1", "d2_i2", "d2_i3","d2_i4", "d2_i5", "d2_i6"]}, 8 | { "name": "data2_q_i", "wave": "x333333", "phase":0.8, "period":2, "data":["d2_q1", "d2_q2", "d2_q3","d2_q4", "d2_q5", "d2_q6"]} 9 | ], 10 | ["output", 11 | { "name": "data_en_o", "wave": "l..h...", "period":2}, 12 | { "name": "data_i_o", "wave": "x..3333", "phase":0.8, "period":2, 13 | "data":["d1_i1+d2_i1", "d1_i2+d2_i2", "d1_i3+d2_i3", "d1_i4+d2_i4", "d1_i5+d2_i5", "d1_i6+d2_i6"]}, 14 | { "name": "data_q_o", "wave": "x..3333", "phase":0.8, "period":2, 15 | "data":["d1_q1+d2_q1", "d1_q2+d2_q2", "d1_q3+d2_q3", "d1_q4+d2_q4", "d1_q5+d2_q5", "d1_q6+d2_q6"]} 16 | ] 17 | ] 18 | } 19 | -------------------------------------------------------------------------------- /doc/IP/figures/adderReal.json: -------------------------------------------------------------------------------- 1 | {"signal": [ 2 | { "name": "clk", "wave": "p......", "period":2}, 3 | ["input", 4 | { "name": "data_en_i", "wave": "lh.....", "period":2}, 5 | { "name": "data1_i", "wave": "x333333", "phase":0.8, "period":2, "data":["d1_1", "d1_2", "d1_3","d1_4", "d1_5", "d1_6"]}, 6 | { "name": "data2_i", "wave": "x333333", "phase":0.8, "period":2, "data":["d2_1", "d2_2", "d2_3","d2_4", "d2_5", "d2_6"]} 7 | ], 8 | ["output", 9 | { "name": "data_en_o", "wave": "l..h...", "period":2}, 10 | { "name": "data_o", "wave": "x..3333", "phase":0.8, "period":2, 11 | "data":["d1_1+d2_1", "d1_2+d2_2", "d1_3+d2_3", "d1_4+d2_4", "d1_5+d2_5", "d1_6+d2_6"]} 12 | ] 13 | ] 14 | } 15 | -------------------------------------------------------------------------------- /doc/IP/figures/axi_to_dac_en.json: -------------------------------------------------------------------------------- 1 | {"signal": [ 2 | { "name": "clk", "wave": "p........."}, 3 | { "name": "reset", "wave": "10........"}, 4 | { "name": "dataA_en", "wave": "0.10.10..."}, 5 | { "name": "dataA_o", "wave": "x33..3....", "data":["0x00", "0x30", "0x02"]}, 6 | { "name": "dataB_en", "wave": "01........"}, 7 | { "name": "dataB_o", "wave": "x3..3...3.", "data":["0x00", "0x05", "0x0A"]} 8 | ]} 9 | -------------------------------------------------------------------------------- /doc/IP/figures/axi_to_dac_reg_conf.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "SEN", "bits": 1, "attr": "RW" }, 3 | { "name": "DAEH", "bits": 1, "attr": "RW" }, 4 | { "name": "DBEH", "bits": 1, "attr": "RW" }, 5 | { "bits": 29 } 6 | ] 7 | } 8 | -------------------------------------------------------------------------------- /doc/IP/figures/axi_to_dac_reg_dataa.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "DATAA_VAL", "bits": 32, "attr": "RW" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/axi_to_dac_reg_datab.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "DATAA_VAL", "bits": 32, "attr": "RW" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/axi_to_dac_reg_id.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "ID", "bits": 32, "attr": "R0" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/axi_to_dac_sync.json: -------------------------------------------------------------------------------- 1 | {"signal": [ 2 | { "name": "clk", "wave": "p........."}, 3 | { "name": "reset", "wave": "10........"}, 4 | { "name": "dataA_en", "wave": "0...10..10"}, 5 | { "name": "dataA_next", "wave": "x33..3....", "data":["0x00", "0x30", "0x02"]}, 6 | { "name": "dataA_o", "wave": "x3..3...3.", "data":["0x00", "0x30", "0x02"]}, 7 | { "name": "dataB_en", "wave": "0...10..10"}, 8 | { "name": "dataB_next", "wave": "x3.3...3..", "data":["0x00", "0x05", "0x0A"]}, 9 | { "name": "dataB_o", "wave": "x3..3...3.", "data":["0x00", "0x05", "0x0A"]} 10 | ]} 11 | -------------------------------------------------------------------------------- /doc/IP/figures/cplx_toFrom_axiStream.json: -------------------------------------------------------------------------------- 1 | {"signal": [ 2 | { "name": "clk", "wave": "p.........", "phase":0.5}, 3 | { "name": "reset", "wave": "10........"}, 4 | ["complex_to_axiStream", 5 | { "name": "data_en_i", "wave": "0..10.10.."}, 6 | { "name": "data_i_i", "wave": "x3.3..3...", "data":["0x00", "0x30", "0x02"]}, 7 | { "name": "data_q_i", "wave": "x3.3..3...", "data":["0x00", "0x50", "0x05"]}, 8 | { "name": "tvalid", "wave": "0..10.10.."}, 9 | { "name": "tdata", "wave": "x3.3..3...", "data":["0x0000", "0x5030", "0x0502"]} 10 | ], 11 | {}, 12 | ["axiStream_to_complex", 13 | { "name": "tvalid", "wave": "0..10.10.."}, 14 | { "name": "tdata", "wave": "x3.3..3...", "data":["0x0000", "0x5030", "0x0502"]}, 15 | { "name": "data_en_o", "wave": "0..10.10.."}, 16 | { "name": "data_i_o", "wave": "x3.3..3...", "data":["0x00", "0x30", "0x02"]}, 17 | { "name": "data_q_o", "wave": "x3.3..3...", "data":["0x00", "0x50", "0x05"]} 18 | ] 19 | ]} 20 | -------------------------------------------------------------------------------- /doc/IP/figures/data_to_ram_reg_data.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "DATA_VAL", "bits": 32, "attr": "R" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/data_to_ram_reg_start.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "start", "bits": 32, "attr": "W" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/data_to_ram_reg_status.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "BUSY", "bits": 1, "attr": "R" }, 3 | { "bits": 31 } 4 | ] 5 | } 6 | -------------------------------------------------------------------------------- /doc/IP/figures/fft.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/IP/figures/fft.png -------------------------------------------------------------------------------- /doc/IP/figures/fft_plot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/IP/figures/fft_plot.png -------------------------------------------------------------------------------- /doc/IP/figures/howto: -------------------------------------------------------------------------------- 1 | pip3 install wavedrom 2 | wavedrompy --input adderComplex.json --svg adderComplex.svg 3 | 4 | -------------------------------------------------------------------------------- /doc/IP/figures/lutGeneratorComplex.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/IP/figures/lutGeneratorComplex.png -------------------------------------------------------------------------------- /doc/IP/figures/lutGeneratorComplex_reg_datai.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "RAM_DATAI", "bits": 32, "attr": "RO" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/lutGeneratorComplex_reg_dataq.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "RAM_DATAQ", "bits": 32, "attr": "RO" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/lutGeneratorComplex_reg_enable.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "EN", "bits": 1, "attr": "RW" }, 3 | { "bits": 31} 4 | ] 5 | } 6 | -------------------------------------------------------------------------------- /doc/IP/figures/lutGeneratorComplex_reg_prescaler.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "PRESCALER", "bits": 32, "attr": "RW" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/lutGeneratorComplex_reg_ram_length.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "RAM_LENGTH", "bits": 32, "attr": "RW" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/lutGeneratorComplex_reg_rst_addr.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "bits": 32, "attr": "WO" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/magnitude.json: -------------------------------------------------------------------------------- 1 | {"signal": [ 2 | { "name": "clk", "wave": "p....", "period":4}, 3 | ["input", 4 | { "name": "data_en_i", "wave": "lh...", "period":4}, 5 | { "name": "data_i_i", "wave": "x333.", "phase":0.8, "period":4, "data":["nI1", "nI2", "nI3"]}, 6 | { "name": "data_q_i", "wave": "x333.", "phase":0.8, "period":4, "data":["nQ1", "nQ2", "nQ3"]} 7 | ], 8 | { "name": "data_i_s", "wave": "xx333", "phase":3.8, "period":4, "data":["nI1*nI1", "nI2*nI2", "nI3*nI3"]}, 9 | { "name": "data_q_s", "wave": "xx333", "phase":3.8, "period":4, "data":["nQ1*nQ1", "nQ2*nQ2", "nQ3*nQ3"]}, 10 | { "name": "data_s", "wave": "xx333", "phase":3.3, "period":4, "data":["nI1*nI1 + nQ1*nQ1", "nI2*nI2 + nQ2*nQ2", "nI3*nI3 + nQ3*nQ3"]}, 11 | ["output", 12 | { "name": "data_en_o", "wave": "l.h..", "period":4}, 13 | { "name": "data_o", "wave": "x.333", "period":4, 14 | "data":["nI1*nI1 + nQ1*nQ1", "nI2*nI2 + nQ2*nQ2", "nI3*nI3 + nQ3*nQ3"]} 15 | ] 16 | ] 17 | } 18 | -------------------------------------------------------------------------------- /doc/IP/figures/mixerComplex_sin.json: -------------------------------------------------------------------------------- 1 | {"signal": [ 2 | { "name": "clk", "wave": "p....", "period":3}, 3 | ["input", 4 | { "name": "data_en_i", "wave": "lh...", "period":3}, 5 | { "name": "data_i_i", "wave": "x3333", "phase":0.8, "period":3, 6 | "data":["dI1", "dI2", "dI3","d4"]}, 7 | { "name": "data_q_i", "wave": "x3333", "phase":0.8, "period":3, 8 | "data":["dQ1", "dQ2", "dQ3","d4"]}, 9 | { "name": "nco_i_i", "wave": "x3333", "phase":0.8, "period":3, 10 | "data":["nI1", "nI2", "nI3","nI4", "nI5", "nI6"]}, 11 | { "name": "nco_q_i", "wave": "x3333", "phase":0.8, "period":3, 12 | "data":["nQ1", "nQ2", "nQ3","nQ4"]} 13 | ], 14 | ["output", 15 | { "name": "data_en_o", "wave": "l..h.", "period":3}, 16 | { "name": "data_i_o", "wave": "x..33", "phase":0.8, "period":3, 17 | "data":["dI1*nI1-dQ1*nQ1", "dI2*nI2-dQ2*nQ2"]}, 18 | { "name": "data_q_o", "wave": "x..33", "phase":0.8,"period":3, 19 | "data":["dI1*nQ1+dQ1*nI1", "dI2*nQ2+dQ2*nI2"]} 20 | ] 21 | ] 22 | } 23 | -------------------------------------------------------------------------------- /doc/IP/figures/mixer_sin.json: -------------------------------------------------------------------------------- 1 | {"signal": [ 2 | { "name": "clk", "wave": "p......", "period":2}, 3 | ["input", 4 | { "name": "data_en_i", "wave": "lh.....", "period":2}, 5 | { "name": "data_i", "wave": "x333333", "phase":0.8, "period":2, "data":["d1", "d2", "d3","d4", "d5", "d6"]}, 6 | { "name": "nco_i_i", "wave": "x333333", "phase":0.8, "period":2, "data":["nI1", "nI2", "nI3","nI4", "nI5", "nI6"]}, 7 | { "name": "nco_q_i", "wave": "x333333", "phase":0.8, "period":2, "data":["nQ1", "nQ2", "nQ3","nQ4", "nQ5", "nQ6"]} 8 | ], 9 | ["output", 10 | { "name": "data_en_o", "wave": "l..h...", "period":2}, 11 | { "name": "data_i_o", "wave": "x..3333", "phase":0.8, "period":2, 12 | "data":["d1*nI1", "d2*nI2", "d3*nI3", "d4*nI4", "d5*nI5", "d6*nI6"]}, 13 | { "name": "data_q_o", "wave": "x..3333", "phase":0.8, "period":2, 14 | "data":["d1*nQ1", "d2*nQ2", "d3*nQ3", "d4*nQ4", "d5*nQ5", "d6*nQ6"]} 15 | ] 16 | ] 17 | } 18 | -------------------------------------------------------------------------------- /doc/IP/figures/real_toFrom_axiStream.json: -------------------------------------------------------------------------------- 1 | {"signal": [ 2 | { "name": "clk", "wave": "p.........", "period":1}, 3 | ["real_to_axiStream", 4 | { "name": "data_en_i", "wave": "0.10.10...", "node":"..a..e.......", "phase":0.5}, 5 | { "name": "data_i", "wave": "x33..3....", "data":["0x00", "0x30", "0x02"], "phase":0.5, "node":"..c..g....."}, 6 | { "name": "tvalid", "wave": "0.10.10...", "phase":0, "node":"..b..f....."}, 7 | { "name": "tdata", "wave": "x33..3....", "data":["0x00", "0x30", "0x02"], "phase":0, "node":"..d..h....."} 8 | ], 9 | {}, 10 | ["axiStream_to_real", 11 | { "name": "tvalid", "wave": "0.10.10...", "node":"..i..m.......", "phase":0.5}, 12 | { "name": "tdata", "wave": "x33..3....", "phase":0.5, "data":["0x00", "0x30", "0x02"], "phase":0.5, "node":"..k..o....."}, 13 | { "name": "data_en_o", "wave": "0.10.10...", "phase":0, "node":"..j..n....."}, 14 | { "name": "data_o", "wave": "x33..3....", "data":["0x00", "0x30", "0x02"], "phase":0, "node":"..l..p....."} 15 | ] 16 | ], 17 | "edge": [ 18 | "a~>b", "c~>d", "e~>f", "g~>h", "i~>j", "k~>l", "m~>n", "o~p" 19 | ] 20 | } 21 | -------------------------------------------------------------------------------- /doc/IP/figures/redpitaya_converters_12.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/IP/figures/redpitaya_converters_12.png -------------------------------------------------------------------------------- /doc/IP/figures/redpitaya_converters_12_ws.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/IP/figures/redpitaya_converters_12_ws.png -------------------------------------------------------------------------------- /doc/IP/figures/sampleCounter.json: -------------------------------------------------------------------------------- 1 | {"signal": [ 2 | { "name": "clk", "wave": "p........", "period":1}, 3 | ["sampleCounterReal", 4 | { "name": "int_count", "wave": "3.3.3.3..", "data": ["0", "1", "2", "3"], "node":".....u...."}, 5 | { "name": "data_en_i", "wave": "010.1010.", "node":".a........"}, 6 | { "name": "data_i", "wave": "x3..3.3..", "data":["0x30", "0x02", "0x04"], "node":"....e....."}, 7 | { "name": "data_en_o", "wave": "0.10.1010", "node":"..g......."}, 8 | { "name": "data_o", "wave": "x.3..3.3.", "data":["0x30", "0x02", "0x04"], "node":".....k...."}, 9 | { "name": "counter_en_o","wave": "0.10.1010", "node":"..m......."}, 10 | { "name": "counter_o", "wave": "x.3..3.3.", "data":["0", "1", "2"], "node":"........r."} 11 | ], 12 | {}, 13 | ["sampleCounterComplex", 14 | { "name": "int_count", "wave": "3.3.3.3..", "data": ["0", "1", "2", "3"] }, 15 | { "name": "data_en_i", "wave": "010.1010." }, 16 | { "name": "data_q_i", "wave": "x3..3.3..", "data":["0x30", "0x02", "0x04"]}, 17 | { "name": "data_q_o", "wave": "x3..3.3..", "data":["0x03", "0x20", "0x40"]}, 18 | { "name": "data_en_o", "wave": "0.10.1010" }, 19 | { "name": "data_q_o", "wave": "x.3..3.3.", "data":["0x30", "0x02", "0x04"]}, 20 | { "name": "data_i_o", "wave": "x.3..3.3.", "data":["0x03", "0x20", "0x40"]}, 21 | { "name": "counter_en_o","wave": "0.10.1010" }, 22 | { "name": "counter_o", "wave": "x.3..3.3.", "data":["0", "1", "2"] } 23 | ] 24 | ], 25 | "edge": [ 26 | "a~>g", "a~>m", "e~>k", "u~>r" 27 | ] 28 | } 29 | -------------------------------------------------------------------------------- /doc/IP/figures/switchReal.json: -------------------------------------------------------------------------------- 1 | {"signal": [ 2 | { "name": "clk", "wave": "p......", "period":2}, 3 | ["input", 4 | { "name": "data1_en_i", "wave": "lh.....", "period":2}, 5 | { "name": "data2_en_i", "wave": "lh.....", "period":2}, 6 | { "name": "data1_i", "wave": "x333333", "phase":0.8, "period":2, "data":["d1_1", "d1_2", "d1_3","d1_4", "d1_5", "d1_6"]}, 7 | { "name": "data2_i", "wave": "x333333", "phase":0.8, "period":2, "data":["d2_1", "d2_2", "d2_3","d2_4", "d2_5", "d2_6"]} 8 | ], 9 | ["output", 10 | { "name": "data_en_o", "wave": "l..h...", "period":2}, 11 | { "name": "data_o", "wave": "x..3333", "phase":0.8, "period":2, 12 | "data":["d1_1", "d1_2", "d1_3", "d1_4", "d1_5", "d1_6"]} 13 | ] 14 | ] 15 | } 16 | -------------------------------------------------------------------------------- /doc/IP/figures/switch_reg_id.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "ID", "bits": 32, "attr": "R0" } 3 | ] 4 | } 5 | -------------------------------------------------------------------------------- /doc/IP/figures/switch_reg_input.json: -------------------------------------------------------------------------------- 1 | {"reg":[ 2 | { "name": "INPUT", "bits": 1, "attr": "RW" }, 3 | { "bits": 31 } 4 | ] 5 | } 6 | -------------------------------------------------------------------------------- /doc/IP/figures/windowReal.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/IP/figures/windowReal.png -------------------------------------------------------------------------------- /doc/IP/figures/windowReal_blackmanharris.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/IP/figures/windowReal_blackmanharris.png -------------------------------------------------------------------------------- /doc/IP/iir_lpf.md: -------------------------------------------------------------------------------- 1 | # iir_lpf_real and iir_lpf_complex 2 | 3 | These IPs represent a recursive first-order lowpass filter. Input and output data streams 4 | are considered to be signed integers (twos complement). The data stream may be 5 | a real interface (**iir_lpf_real**) or a complex interface (**iir_lpf_complex**). 6 | 7 | Bit width of the integer values is defined by parameter DATA_WIDTH. 8 | Bit shift defining the feedback signal scaling is given by FILTER_COEFF_TWOS_POWER. 9 | * to prevent numerical instabilities and effects of feedback signal quantization, 10 | the internal signal bit width is increased to DATA_WIDTH + 2 x FILTER_COEFF_TWOS_POWER. 11 | Filter cutoff frequency is defined by sampling clock frequency and bit shift 12 | parameter FILTER_COEFF_TWOS_POWER according to the formula in figure [1](#iir_lpf_real2). 13 | 14 | [iir_lpf_real2]: figures/iir_lpf_real2.svg "iir_lpf_real" 15 | ![**iir_lpf_real** block diagram. ][iir_lpf_real2] 16 | __Figure1__: **iir_lpf_real** block diagram.signals *data_in* and *data_en_i* are from input real interface, 17 | signal *data_o* is from output real interface. Signal *data_en_o* is identical to the signal *en_i_1*. 18 | 19 | ## IP 20 | 21 | * **iir_lpf_real**: lowpass filters real data (data_in) 22 | * **iir_lpf_complex**: lowpass filters complex data (data_in) 23 | 24 | ## Generic 25 | 26 | * **DATA_WIDTH**: (natural) data stream bus size (default: 16). 27 | * **FILTER_COEFF_TWOS_POWER**: (natural) internal variable bit shift; along with sampling frequency 28 | determines the cutoff frequency (default: 16). 29 | 30 | ## Ports and interfaces 31 | 32 | * **data_in**: (real interface for *iir_lpf_real* and complex interface for 33 | *iir_lpf_complex*) input data stream 34 | * **data_out**: (real interface for *iir_lpf_real*)and (complex interface for *iir_lpf_complex*) output data stream. 35 | 36 | ## Registers 37 | 38 | **NA** 39 | 40 | ## TCL instanciation and connection 41 | 42 | ```tcl 43 | # add a real iir lowpass filter and configure it for a cutoff frequency of about 500 Hz at f_clk = 125MHz. 44 | set lowpass_filter_1 [create_bd_cell -type ip -vlnv ggm:cogen:iir_lpf_real:1.0 iir_lpf] 45 | set_property -dict [list \ 46 | CONFIG.DATA_WIDTH 16 \ 47 | CONFIG.FILTER_COEFF_TWOS_POWER 16] $lowpass_filter_1 48 | 49 | # connect data_in to an other block with a real data stream (ADC for instance) 50 | connect_bd_intf_net [get_bd_intf_pins $previous_block/data_out] 51 | [get_bd_intf_pins $lowpass_filter_1/data_in] 52 | ``` 53 | ## Driver 54 | 55 | **NA** 56 | 57 | ## Functions to configure IP 58 | 59 | **NA** 60 | -------------------------------------------------------------------------------- /doc/IP/magnitude.md: -------------------------------------------------------------------------------- 1 | # magnitude 2 | 3 | This IP is used to perform $$real \times real + imag \times imag$$ of the complex input stream 4 | 5 | [magnitude_output]: figures/magnitude.svg "magnitude_output" 6 | ![Magnitude block internal behaviour][magnitude_output] 7 | 8 | __figure1__: Magnitude block internal behaviour. 9 | 10 | **NOTE: output size is fixed to be (2 * DATA_SIZE) + 1. One have to add a shifter 11 | or an expander to adapts data bus size** 12 | 13 | **Internal propagation delay**: 1 clock cycle. 14 | ## IP 15 | 16 | * **magnitude**: convert a complex stream (data_in) to a real stream (data_out) 17 | 18 | ## Generic 19 | 20 | * **DATA_SIZE**: (natural) input data stream bus size (default: 16). 21 | * **SIGN_CORRECTION**: (bool) 0: output is unsigned, 1: output is <0 when q<0 22 | 23 | ## Ports and interfaces 24 | 25 | * **data_in**: (complex interface) input data stream 26 | * **data_out**: (real interface) output data stream 27 | 28 | ## Registers 29 | 30 | **NA** 31 | 32 | ## TCL instanciation and connection 33 | 34 | ```tcl 35 | # add a real mixer and configure it to propagate results with full resolution 36 | # change mixer_sin by mixerComplex_sin to use complex version 37 | add_ip_and_conf magnitude mag { 38 | DATA_SIZE 16} 39 | 40 | # connect data_in to an other block with a real data stream (ADC for instance) 41 | connect_intf $previous_block data_out mag data_in 42 | # connect nco_in to an other block with a complex data stream (NCO for instance) 43 | connect_intf mag data_out $next_block data_in 44 | 45 | 46 | ``` 47 | ## Driver 48 | 49 | **NA** 50 | 51 | ## Functions to configure IP 52 | 53 | **NA** 54 | -------------------------------------------------------------------------------- /doc/IP/prn20b.md: -------------------------------------------------------------------------------- 1 | # prn20b 2 | 3 | Generates a 20-bit long pseudo random sequence using a linear feedback shift 4 | register. 5 | * the full output bus prn_full_o is 20-bit wide 6 | * a single least significant bit is output on bit_o 7 | * a prescaler allows tuning the output bandwidth by generating a new value 8 | only once every prescaler value 9 | * the prescaler width is PRESC_SIZE=16 and the default prescaler value is 10 | DFLT_PRESC=15 11 | 12 | ## IP 13 | * **prn20b**: 20 bit pseudo random sequence generator 14 | 15 | ## Generic 16 | * **PRESC_SIZE**: (natural) prescaler size (default: 16). 17 | * **DFLT_PRESC**: (natural) default prescaler value (default: 15). 18 | 19 | ## Ports and interfaces 20 | * **prn_full_o**: 20-bit wide full width output 21 | * **bit_o**: single bit pseudo-random sequence output 22 | * **s00_axi**: axi interface to connect to the CPU wrapper 23 | * **s00_axi_reset**: reset signal in the **s00_axi** clock domain 24 | * **s00_axi_aclk**: clock signal used for everything related to CPU 25 | communication 26 | 27 | ## TCL instanciation and connection 28 | 29 | ```tcl 30 | # add prn20b 31 | -------------------------------------------------------------------------------- /doc/IP/sampleCounter.md: -------------------------------------------------------------------------------- 1 | # sampleCounterComplex/sampleCounterReal 2 | 3 | Used to associate a numeric value (counter) to each input sample. 4 | This counter has a fixed size (**SAMPLE_COUNTER_SIZE**). When the value is equal 5 | to $2^{SAMPLE_COUNTER_SIZE}-1), the counter restart with the value 0. 6 | 7 | *Note: counter output (**counter_out**) interface is always real* 8 | 9 | [sampleCounter_scheme]: figures/sampleCounter.svg "sampleCounter_scheme" 10 | ![sampleCounter block internal scheme][sampleCounter_scheme] 11 | 12 | __figure1__: sampleCounter block principle 13 | 14 | ### **Internal propagation delay** 15 | 16 | 1 clock cycle 17 | 18 | ## IP 19 | * **sampleCounterReal**: in and out real interfaces variant 20 | * **sampleCounterComplex**: in and out complex interfaces variant 21 | 22 | ## Generic 23 | * **SAMPLE_COUNTER_SIZE**: (natural) output counter size (default: 32). 24 | * **DATA_SIZE**: (natural) input/output data stream bus size (default: 16). 25 | 26 | ## Ports and interfaces 27 | * **data_in**: input data stream (complex type for *sampleCounterComplex* or 28 | real type for *sampleCounterReal*). Size fixed by **DATA_SIZE** 29 | * **data_out**: output data stream (complex type for *sampleCounterComplex* or 30 | real type for *sampleCounterReal*). Size fixed by **DATA_SIZE** 31 | * **counter_out**: output counter value (real type for both). Size fixed by 32 | **SAMPLE_COUNTER_SIZE** 33 | 34 | ## TCL instanciation and connection 35 | 36 | ### common 37 | 38 | ```tcl 39 | # add sampleCounterComplex with a 32 bits data stream and a 16 bits counter stream 40 | # replace sampleCounterComplex by sampleCounterReal 41 | add_ip_and_conf sampleCounterComplex sCnt { 42 | DATA_SIZE 32 \ 43 | SAMPLE_COUNTER_SIZE 16} 44 | 45 | # prev -> sampleCounter 46 | connect_intf $prevInst data_out sCnt data_in 47 | # sampleCounter (data) -> next 48 | connect_intf sCnt data_out $nextInst data_in 49 | # sampleCounter (counter) -> next 50 | connect_intf sCnt counter_out $anotherNextInst data_in 51 | ``` 52 | 53 | ## Registers 54 | 55 | **NA** 56 | 57 | ## Driver 58 | 59 | **NA** 60 | 61 | ## Functions to configure IP 62 | 63 | **NA** 64 | -------------------------------------------------------------------------------- /doc/conferences/fosdem2020/2xcorr_2PRN_NCO.pdf: -------------------------------------------------------------------------------- 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/doc/external_clock_and_undersampling_PCB/README.md: -------------------------------------------------------------------------------- 1 | ### PCB for reliable conexion of an external clock and direct connection to ADC inputs for undersampling 2 | 3 | Hardware modifications of the 14-bit Red Pitaya (also known as STEMlab 125-14) described 4 | in report.pdf, and the associated KiCAD files (courtesy of Gilles Martin, FEMTO-ST, France, 5 | translated from Eagle) for undersampling by getting rid of the unbalanced-balanced amplifier 6 | also acting as low pass filter. 7 | 8 | For external clocking (125 MHz), only populate the balun and channel closest to the border of the PCB. The 9 | other two channels are for undersampling by bypassing the unbalanced to balanced differential 10 | amplifiers. Follow 11 | [these instructions](https://redpitaya.readthedocs.io/en/latest/developerGuide/hardware/125-14/top.html#external-125-14) 12 | for wiring modifications (two resistors to be flipped) to disconnect the quartz crystal oscillator 13 | and connect the clock input to the PCLK external source pins. 14 | 15 | Replacing the active amplifier with a broadband balun (tested over the whole track-and-hold 16 | range up to 875 MHz input frequency) requires soldering three tiny wires (differential pair and Vref) 17 | on each channel at your own risks after removing the inductors connecting the differential 18 | amplifier output to the ADC inputs. The Vref signal trace must be cut before soldering a 19 | wire to the via pad whose varnish will have been removed with a sharp blade. 20 | -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/all.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/external_clock_and_undersampling_PCB/all.pdf -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/extension_clk_adc-backups/extension_clk_adc-2024-11-01_094340.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/external_clock_and_undersampling_PCB/extension_clk_adc-backups/extension_clk_adc-2024-11-01_094340.zip -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/extension_clk_adc.kicad_prl: -------------------------------------------------------------------------------- 1 | { 2 | "board": { 3 | "active_layer": 0, 4 | "active_layer_preset": "", 5 | "auto_track_width": true, 6 | "hidden_netclasses": [], 7 | "hidden_nets": [], 8 | "high_contrast_mode": 0, 9 | "net_color_mode": 1, 10 | "opacity": { 11 | "images": 0.6, 12 | "pads": 1.0, 13 | "tracks": 1.0, 14 | "vias": 1.0, 15 | "zones": 0.6 16 | }, 17 | "selection_filter": { 18 | "dimensions": true, 19 | "footprints": true, 20 | "graphics": true, 21 | "keepouts": true, 22 | "lockedItems": false, 23 | "otherItems": true, 24 | "pads": true, 25 | "text": true, 26 | "tracks": true, 27 | "vias": true, 28 | "zones": true 29 | }, 30 | "visible_items": [ 31 | 0, 32 | 1, 33 | 2, 34 | 3, 35 | 4, 36 | 5, 37 | 8, 38 | 9, 39 | 10, 40 | 11, 41 | 12, 42 | 13, 43 | 15, 44 | 16, 45 | 17, 46 | 18, 47 | 19, 48 | 20, 49 | 21, 50 | 22, 51 | 23, 52 | 24, 53 | 25, 54 | 26, 55 | 27, 56 | 28, 57 | 29, 58 | 30, 59 | 32, 60 | 33, 61 | 34, 62 | 35, 63 | 36, 64 | 39, 65 | 40 66 | ], 67 | "visible_layers": "fffffff_ffffffff", 68 | "zone_display_mode": 0 69 | }, 70 | "git": { 71 | "repo_password": "", 72 | "repo_type": "", 73 | "repo_username": "", 74 | "ssh_key": "" 75 | }, 76 | "meta": { 77 | "filename": "extension_clk_adc.kicad_prl", 78 | "version": 3 79 | }, 80 | "project": { 81 | "files": [] 82 | } 83 | } 84 | -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/extension_clk_adc.pretty/AT224-1A.kicad_mod: -------------------------------------------------------------------------------- 1 | (module AT224-1A (layer F.Cu) (tedit 0) 2 | (fp_text reference TR3 (at -2.54 2.54 90) (layer F.SilkS) 3 | (effects (font (size 0.9652 0.9652) (thickness 0.08128)) (justify left bottom)) 4 | ) 5 | (fp_text value TC1-1-13M (at 0 0) (layer F.SilkS) hide 6 | (effects (font (size 1.27 1.27) (thickness 0.15)) (justify right top)) 7 | ) 8 | (fp_line (start -1.905 -1.651) (end 1.905 -1.651) (layer F.SilkS) (width 0.1016)) 9 | (fp_line (start 1.905 -1.651) (end 1.905 1.651) (layer F.SilkS) (width 0.1016)) 10 | (fp_line (start 1.905 1.651) (end -1.905 1.651) (layer F.SilkS) (width 0.1016)) 11 | (fp_line (start -1.905 1.651) (end -1.905 -1.651) (layer F.SilkS) (width 0.1016)) 12 | (fp_circle (center -1.27 -1.016) (end -1.090397 -1.016) (layer F.SilkS) (width 0.1016)) 13 | (fp_line (start -1.397 -0.381) (end -1.397 0.381) (layer F.SilkS) (width 0.127)) 14 | (fp_line (start -1.397 0.381) (end -1.143 0.381) (layer F.SilkS) (width 0.127)) 15 | (fp_line (start -1.143 0.381) (end -1.143 -0.381) (layer F.SilkS) (width 0.127)) 16 | (fp_line (start -1.143 -0.381) (end -1.397 -0.381) (layer F.SilkS) (width 0.127)) 17 | (pad P$1 smd rect (at -1.27 -1.651 90) (size 1.651 0.762) (layers F.Cu F.Paste F.Mask) 18 | (solder_mask_margin 0.1016)) 19 | (pad P$2 smd rect (at 0 -1.651 90) (size 1.651 0.762) (layers F.Cu F.Paste F.Mask) 20 | (solder_mask_margin 0.1016)) 21 | (pad P$3 smd rect (at 1.27 -1.651 90) (size 1.651 0.762) (layers F.Cu F.Paste F.Mask) 22 | (solder_mask_margin 0.1016)) 23 | (pad P$4 smd rect (at 1.27 1.651 90) (size 1.651 0.762) (layers F.Cu F.Paste F.Mask) 24 | (solder_mask_margin 0.1016)) 25 | (pad P$6 smd rect (at -1.27 1.651 90) (size 1.651 0.762) (layers F.Cu F.Paste F.Mask) 26 | (solder_mask_margin 0.1016)) 27 | ) 28 | -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/extension_clk_adc.pretty/C0402.kicad_mod: -------------------------------------------------------------------------------- 1 | (module C0402 (layer F.Cu) (tedit 0) 2 | (descr CAPACITOR) 3 | (fp_text reference C9 (at -0.635 -0.635) (layer F.SilkS) 4 | (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right top)) 5 | ) 6 | (fp_text value 100nF (at -0.635 1.905) (layer F.Fab) 7 | (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right top)) 8 | ) 9 | (fp_line (start -0.245 -0.224) (end 0.245 -0.224) (layer F.Fab) (width 0.1524)) 10 | (fp_line (start 0.245 0.224) (end -0.245 0.224) (layer F.Fab) (width 0.1524)) 11 | (fp_line (start -1.473 -0.483) (end 1.473 -0.483) (layer Dwgs.User) (width 0.0508)) 12 | (fp_line (start 1.473 -0.483) (end 1.473 0.483) (layer Dwgs.User) (width 0.0508)) 13 | (fp_line (start 1.473 0.483) (end -1.473 0.483) (layer Dwgs.User) (width 0.0508)) 14 | (fp_line (start -1.473 0.483) (end -1.473 -0.483) (layer Dwgs.User) (width 0.0508)) 15 | (fp_poly (pts (xy -0.554 0.3048) (xy -0.254 0.3048) (xy -0.254 -0.2951) (xy -0.554 -0.2951)) (layer F.Fab) (width 0)) 16 | (fp_poly (pts (xy 0.2588 0.3048) (xy 0.5588 0.3048) (xy 0.5588 -0.2951) (xy 0.2588 -0.2951)) (layer F.Fab) (width 0)) 17 | (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) 18 | (pad 1 smd rect (at -0.65 0) (size 0.7 0.9) (layers F.Cu F.Paste F.Mask) 19 | (solder_mask_margin 0.1016)) 20 | (pad 2 smd rect (at 0.65 0) (size 0.7 0.9) (layers F.Cu F.Paste F.Mask) 21 | (solder_mask_margin 0.1016)) 22 | ) 23 | -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/extension_clk_adc.pretty/C0603.kicad_mod: -------------------------------------------------------------------------------- 1 | (module C0603 (layer F.Cu) (tedit 0) 2 | (descr CAPACITOR) 3 | (fp_text reference C7 (at -0.635 -0.635) (layer F.SilkS) 4 | (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) 5 | ) 6 | (fp_text value 100nF (at -0.635 1.905) (layer F.Fab) 7 | (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) 8 | ) 9 | (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) 10 | (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) 11 | (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) 12 | (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) 13 | (fp_line (start -0.356 -0.432) (end 0.356 -0.432) (layer F.Fab) (width 0.1016)) 14 | (fp_line (start -0.356 0.419) (end 0.356 0.419) (layer F.Fab) (width 0.1016)) 15 | (fp_poly (pts (xy -0.8382 0.4699) (xy -0.3381 0.4699) (xy -0.3381 -0.4801) (xy -0.8382 -0.4801)) (layer F.Fab) (width 0)) 16 | (fp_poly (pts (xy 0.3302 0.4699) (xy 0.8303 0.4699) (xy 0.8303 -0.4801) (xy 0.3302 -0.4801)) (layer F.Fab) (width 0)) 17 | (fp_poly (pts (xy -0.1999 0.3) (xy 0.1999 0.3) (xy 0.1999 -0.3) (xy -0.1999 -0.3)) (layer F.Adhes) (width 0)) 18 | (pad 1 smd rect (at -0.85 0) (size 1.1 1) (layers F.Cu F.Paste F.Mask) 19 | (solder_mask_margin 0.1016)) 20 | (pad 2 smd rect (at 0.85 0) (size 1.1 1) (layers F.Cu F.Paste F.Mask) 21 | (solder_mask_margin 0.1016)) 22 | ) 23 | -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/extension_clk_adc.pretty/DBL6.kicad_mod: -------------------------------------------------------------------------------- 1 | (module DBL6 (layer F.Cu) (tedit 0) 2 | (fp_text reference J5 (at -2.54 -4.445) (layer F.SilkS) 3 | (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) 4 | ) 5 | (fp_text value DBL_6 (at 0 0) (layer F.SilkS) hide 6 | (effects (font (size 1.27 1.27) (thickness 0.15))) 7 | ) 8 | (fp_line (start -2.54 -3.81) (end 2.54 -3.81) (layer F.SilkS) (width 0.127)) 9 | (fp_line (start 2.54 -3.81) (end 2.54 3.81) (layer F.SilkS) (width 0.127)) 10 | (fp_line (start 2.54 3.81) (end -2.54 3.81) (layer F.SilkS) (width 0.127)) 11 | (fp_line (start -2.54 3.81) (end -2.54 -3.81) (layer F.SilkS) (width 0.127)) 12 | (pad P$1 thru_hole rect (at -1.27 -2.54) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) 13 | (solder_mask_margin 0.1016)) 14 | (pad P$2 thru_hole circle (at 1.27 -2.54) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) 15 | (solder_mask_margin 0.1016)) 16 | (pad P$3 thru_hole circle (at -1.27 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) 17 | (solder_mask_margin 0.1016)) 18 | (pad P$4 thru_hole circle (at 1.27 0) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) 19 | (solder_mask_margin 0.1016)) 20 | (pad P$5 thru_hole circle (at -1.27 2.54) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) 21 | (solder_mask_margin 0.1016)) 22 | (pad P$6 thru_hole circle (at 1.27 2.54) (size 1.308 1.308) (drill 0.8) (layers *.Cu *.Mask) 23 | (solder_mask_margin 0.1016)) 24 | ) 25 | -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/extension_clk_adc.pretty/R0603.kicad_mod: -------------------------------------------------------------------------------- 1 | (module R0603 (layer F.Cu) (tedit 0) 2 | (descr RESISTOR) 3 | (fp_text reference R9 (at -0.635 -0.635) (layer F.SilkS) 4 | (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) 5 | ) 6 | (fp_text value 25 (at -0.635 1.905) (layer F.Fab) 7 | (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify left bottom)) 8 | ) 9 | (fp_line (start -0.432 0.356) (end 0.432 0.356) (layer F.Fab) (width 0.1524)) 10 | (fp_line (start 0.432 -0.356) (end -0.432 -0.356) (layer F.Fab) (width 0.1524)) 11 | (fp_line (start -1.473 -0.983) (end 1.473 -0.983) (layer Dwgs.User) (width 0.0508)) 12 | (fp_line (start 1.473 -0.983) (end 1.473 0.983) (layer Dwgs.User) (width 0.0508)) 13 | (fp_line (start 1.473 0.983) (end -1.473 0.983) (layer Dwgs.User) (width 0.0508)) 14 | (fp_line (start -1.473 0.983) (end -1.473 -0.983) (layer Dwgs.User) (width 0.0508)) 15 | (fp_poly (pts (xy 0.4318 0.4318) (xy 0.8382 0.4318) (xy 0.8382 -0.4318) (xy 0.4318 -0.4318)) (layer F.Fab) (width 0)) 16 | (fp_poly (pts (xy -0.8382 0.4318) (xy -0.4318 0.4318) (xy -0.4318 -0.4318) (xy -0.8382 -0.4318)) (layer F.Fab) (width 0)) 17 | (fp_poly (pts (xy -0.1999 0.4001) (xy 0.1999 0.4001) (xy 0.1999 -0.4001) (xy -0.1999 -0.4001)) (layer F.Adhes) (width 0)) 18 | (pad 1 smd rect (at -0.85 0) (size 1 1.1) (layers F.Cu F.Paste F.Mask) 19 | (solder_mask_margin 0.1016)) 20 | (pad 2 smd rect (at 0.85 0) (size 1 1.1) (layers F.Cu F.Paste F.Mask) 21 | (solder_mask_margin 0.1016)) 22 | ) 23 | -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/extension_clk_adc.pretty/SMA_BORD.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SMA_BORD (layer F.Cu) (tedit 0) 2 | (fp_text reference J3 (at 0.635 -6.35) (layer F.SilkS) 3 | (effects (font (size 1.6891 1.6891) (thickness 0.14224)) (justify left bottom)) 4 | ) 5 | (fp_text value "" (at 1.27 8.89) (layer F.Fab) 6 | (effects (font (size 1.6891 1.6891) (thickness 0.14224)) (justify left bottom)) 7 | ) 8 | (fp_line (start 0 -5.588) (end 0 5.588) (layer Edge.Cuts) (width 0.05)) 9 | (fp_line (start -1.55 4.523) (end -1.55 2) (layer F.SilkS) (width 0.2032)) 10 | (fp_line (start -1.55 2) (end -3.7 2) (layer F.SilkS) (width 0.2032)) 11 | (fp_line (start -3.7 2) (end -4.45 2.75) (layer F.SilkS) (width 0.2032)) 12 | (fp_line (start -4.45 2.75) (end -8.25 2.75) (layer F.SilkS) (width 0.2032)) 13 | (fp_line (start -8.25 2.75) (end -8.25 1.9) (layer F.SilkS) (width 0.2032)) 14 | (fp_line (start -8.25 1.9) (end -9.425 1.9) (layer F.SilkS) (width 0.2032)) 15 | (fp_line (start -9.425 1.9) (end -9.425 -1.9) (layer F.SilkS) (width 0.2032)) 16 | (fp_line (start -9.425 -1.9) (end -8.25 -1.9) (layer F.SilkS) (width 0.2032)) 17 | (fp_line (start -8.25 -1.9) (end -8.25 -2.75) (layer F.SilkS) (width 0.2032)) 18 | (fp_line (start -8.25 -2.75) (end -4.45 -2.75) (layer F.SilkS) (width 0.2032)) 19 | (fp_line (start -4.45 -2.75) (end -3.7 -2) (layer F.SilkS) (width 0.2032)) 20 | (fp_line (start -3.7 -2) (end -1.55 -2) (layer F.SilkS) (width 0.2032)) 21 | (fp_line (start -1.55 -2) (end -1.55 -4.523) (layer F.SilkS) (width 0.2032)) 22 | (fp_line (start -0.1 3.723) (end -0.1 -3.723) (layer F.SilkS) (width 0.2032)) 23 | (fp_line (start -1.55 -4.523) (end -0.1 -4.523) (layer F.SilkS) (width 0.2032)) 24 | (fp_line (start -0.1 4.523) (end -1.55 4.523) (layer F.SilkS) (width 0.2032)) 25 | (fp_line (start -1.55 -4.65) (end 4.65 -4.65) (layer F.Fab) (width 0.2032)) 26 | (fp_line (start 4.65 4.65) (end -1.55 4.65) (layer F.Fab) (width 0.2032)) 27 | (fp_line (start 4.65 4.65) (end 4.65 3.85) (layer F.Fab) (width 0.2032)) 28 | (fp_line (start 4.65 3.85) (end -0.1 3.85) (layer F.Fab) (width 0.2032)) 29 | (fp_line (start -0.1 -3.85) (end 4.65 -3.85) (layer F.Fab) (width 0.2032)) 30 | (fp_line (start 4.65 -3.85) (end 4.65 -4.65) (layer F.Fab) (width 0.2032)) 31 | (fp_poly (pts (xy -0.025 0.5) (xy 4.05 0.5) (xy 4.05 -0.5) (xy -0.025 -0.5)) (layer F.Fab) (width 0)) 32 | (pad 1 smd rect (at 1.27 0) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask) 33 | (solder_mask_margin 0.1016)) 34 | (pad G@1 smd rect (at 3.175 -4.064) (size 6.35 2.286) (layers F.Cu F.Paste F.Mask) 35 | (solder_mask_margin 0.1016)) 36 | (pad G@2 smd rect (at 3.175 4.064) (size 6.35 2.286) (layers F.Cu F.Paste F.Mask) 37 | (solder_mask_margin 0.1016)) 38 | (pad G@4 smd rect (at 3.2004 4.0386) (size 6.35 2.286) (layers B.Cu B.Paste B.Mask) 39 | (solder_mask_margin 0.1016)) 40 | (pad G@3 smd rect (at 3.2004 -4.0386) (size 6.35 2.286) (layers B.Cu B.Paste B.Mask) 41 | (solder_mask_margin 0.1016)) 42 | ) 43 | -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/extension_clk_adc.pretty/SMD1,27-2,54.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SMD1,27-2,54 (layer F.Cu) (tedit 0) 2 | (descr "SMD PAD") 3 | (fp_text reference VCM_2 (at -0.8 2.4 90) (layer F.SilkS) 4 | (effects (font (size 1.2065 1.2065) (thickness 0.1016)) (justify right top)) 5 | ) 6 | (fp_text value "" (at 0 0) (layer F.Fab) 7 | (effects (font (size 0.02413 0.02413) (thickness 0.002032)) (justify left bottom)) 8 | ) 9 | (pad 1 smd rect (at 0 0) (size 1.27 2.54) (layers F.Cu F.Paste F.Mask) 10 | (solder_mask_margin 0.1016)) 11 | ) 12 | -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/fp-info-cache: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/go.m: -------------------------------------------------------------------------------- 1 | %graphics_toolkit('fltk') 2 | leg=[]; 3 | fs=125; 4 | fr=linspace(-fs/2,fs/2,30000); 5 | filename=dir('d*.bin'); 6 | for filelist=1:length(filename) 7 | subplot(3,3,filelist) 8 | filename(filelist).name 9 | f=fopen(['./',filename(filelist).name]);d=fread(f,inf,'int16'); 10 | d1=d(1:2:end); 11 | d2=d(2:2:end); 12 | plot(d1(1:30000));hold on 13 | plot(d2(1:30000));hold on 14 | title(filename(filelist).name(23:end-4)) 15 | %subplot(313) 16 | % plot(fr,fftshift(abs(fft(d1(1:30000)))));hold on 17 | % plot(fr,fftshift(abs(fft(d2(1:30000)))));hold on 18 | leg=[leg,'''',filename(filelist).name(23:end-4),''',']; 19 | end 20 | %axis([-fs/2 fs/2 0 1e7]) 21 | %subplot(312) 22 | %eval(['legend(',leg(1:end-1),',''location'',''southeast'')']) 23 | %xlabel('sample number (no unit)') 24 | %ylabel('value (bits)') 25 | -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/report.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/external_clock_and_undersampling_PCB/report.pdf -------------------------------------------------------------------------------- /doc/external_clock_and_undersampling_PCB/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (version 7) 3 | (lib (name "extension_clk_adc-rescue")(type "KiCad")(uri "${KIPRJMOD}/extension_clk_adc-rescue.kicad_sym")(options "")(descr "")) 4 | ) 5 | -------------------------------------------------------------------------------- /doc/install_bootgen.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/install_bootgen.png -------------------------------------------------------------------------------- /doc/install_vivado.png: -------------------------------------------------------------------------------- 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/doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/Makefile: -------------------------------------------------------------------------------- 1 | all: 1-adalmPluto_within_OscimpDigital.pdf 2 | 3 | 1-adalmPluto_within_OscimpDigital.pdf: 1-adalmPluto_within_OscimpDigital.tex 4 | pdflatex $^ 5 | pdflatex $^ 6 | 7 | clean: 8 | rm *.log *.aux *.out *bak 1-adalmPluto_within_OscimpDigital.pdf 9 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/README.md: -------------------------------------------------------------------------------- 1 | Custom IP using the OscimpDigital framework to add functionalities to the bitstream provided by ADI. Two 2 | examples, one independent of the original AD9363 stream, demonstrates data transfer from the PL to the PS 3 | through the ComplexToRAM block. 4 | 5 | For those in a hurry, two DFU images ready for flashing the PlutoSDR are provided in the 6 | [dfu_images](dfu_images) directory. We use 7 | 8 | ```bash 9 | dfu-util -a firmware.dfu -D firmware_name.dfu 10 | ``` 11 | 12 | to flash the PlutoSDR. Original SDR functionality is kept since we only split the AXI stream 13 | to the custom interface. The firmware named pluto_bitstream_without_AXI.dfu only implements 14 | an NCO connected to a single data to RAM block, while the pluto_bitstream_with_AXI.dfu implements 15 | the AXI to complex block, mixing with an NCO programmed from the PS, and a 3-channel complex 16 | data to RAM with the NCO values, the raw values and the mixer output. 17 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/dfu_images/pluto_bitstream_with_AXI.dfu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/dfu_images/pluto_bitstream_with_AXI.dfu -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/dfu_images/pluto_bitstream_without_AXI.dfu: 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subplot(323);plot(x(3:6:end));hold on;plot(x(4:6:end)); 4 | subplot(325);plot(x(5:6:end));hold on;plot(x(6:6:end)); 5 | 6 | %x=load('data_200kHz.dat'); 7 | x=load('data_250kHz.dat'); 8 | %x=load('data_050kHz.dat'); 9 | subplot(322);plot(x(1:6:end));hold on;plot(x(2:6:end)); 10 | subplot(324);plot(x(3:6:end));hold on;plot(x(4:6:end)); 11 | subplot(326);plot(x(5:6:end));hold on;plot(x(6:6:end)); 12 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/project1/app/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | /* memory management */ 10 | #include 11 | #include 12 | #include 13 | 14 | #include 15 | 16 | #define ELEMENT_SIZE 1024 // Nb Sample 17 | 18 | #define CLK_FREQ 50000000 19 | #define MOD_FREQ 100000 20 | #define NCO_ACCUM_SIZE 28 21 | 22 | int main() 23 | { 24 | int16_t *rawData; 25 | int ramfd = 0, i; 26 | 27 | struct iio_device *dev, *phy; 28 | struct iio_context *ctx; 29 | struct iio_channel *rx0_i, *rx0_q; 30 | 31 | rawData = (int16_t *) malloc(2 * ELEMENT_SIZE * sizeof(int16_t)); 32 | 33 | ctx = iio_create_local_context(); 34 | 35 | dev = iio_context_find_device(ctx, "cf-ad9361-lpc"); 36 | phy = iio_context_find_device(ctx, "ad9361-phy"); 37 | 38 | iio_channel_attr_write_longlong(iio_device_find_channel(phy, "altvoltage1", true), 39 | "frequency", 2200000000); /* TX LO frequency 2.4GHz */ 40 | 41 | iio_channel_attr_write_longlong(iio_device_find_channel(phy, "altvoltage0", true), 42 | "frequency", 2200100000); /* RX LO frequency 2.4GHz + 100 kHz */ 43 | 44 | iio_channel_attr_write_longlong(iio_device_find_channel(phy, "voltage0", false), 45 | "sampling_frequency", CLK_FREQ); /* RX baseband rate 5 MSPS */ 46 | 47 | rx0_i = iio_device_find_channel(dev, "voltage0", 0); 48 | rx0_q = iio_device_find_channel(dev, "voltage1", 0); 49 | 50 | iio_channel_enable(rx0_i); 51 | iio_channel_enable(rx0_q); 52 | 53 | /* NCO configuration */ 54 | nco_counter_send_conf("/dev/nco00", CLK_FREQ, MOD_FREQ, 55 | NCO_ACCUM_SIZE, 0, 1, 1); // 0, 1, 1 => offset, PINC HW/SF, POFF HW/SF 56 | 57 | ramfd = open("/dev/data00", O_RDONLY); 58 | if (ramfd < 0) { 59 | perror("ram open error\n"); 60 | return EXIT_FAILURE; 61 | } 62 | read(ramfd, rawData, 2 * ELEMENT_SIZE * sizeof(int16_t)); 63 | FILE *fd = fopen("data.dat", "w"); 64 | for (i = 0; i < 2 * ELEMENT_SIZE; i+=2) 65 | fprintf(fd, "%d %d\n", rawData[i], rawData[i+1]); 66 | fclose(fd); 67 | close(ramfd); 68 | iio_context_destroy(ctx); 69 | free(rawData); 70 | return EXIT_SUCCESS; 71 | } 72 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/project1/app/project1.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /plugin/; 3 | 4 | / { 5 | compatible = "xlnx,zynq-7000"; 6 | 7 | fragment0 { 8 | target = <&fpga_axi>; 9 | #address-cells = <1>; 10 | #size-cells = <1>; 11 | __overlay__ { 12 | #address-cells = <1>; 13 | #size-cells = <1>; 14 | 15 | data00: data00@43c10000{ 16 | compatible = "ggm,dataToRam"; 17 | reg = <0x43c10000 0xffff>; 18 | }; 19 | 20 | nco00: nco00@43c00000{ 21 | compatible = "ggm,nco_counter"; 22 | reg = <0x43c00000 0xffff>; 23 | }; 24 | 25 | }; 26 | }; 27 | }; 28 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/project1/app/project1_us.sh: -------------------------------------------------------------------------------- 1 | CORE_MODULES_DIR=../../modules 2 | 3 | DTB_DIR=/sys/kernel/config/device-tree/overlays/fpga 4 | if [ -d $DTB_DIR ]; then 5 | rmdir $DTB_DIR 6 | fi 7 | mkdir $DTB_DIR 8 | cat project1.dtbo > $DTB_DIR/dtbo 9 | 10 | insmod ${CORE_MODULES_DIR}/data_to_ram_core.ko 11 | insmod ${CORE_MODULES_DIR}/nco_counter_core.ko 12 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/project1/design/Makefile: -------------------------------------------------------------------------------- 1 | #################################################################################### 2 | ## Copyright 2018(c) Analog Devices, Inc. 3 | ## Auto-generated, do not modify! 4 | #################################################################################### 5 | 6 | PROJECT_NAME := pluto 7 | 8 | M_DEPS += $(ADI_HDL_DIR)/library/xilinx/common/ad_iobuf.v 9 | M_DEPS += $(ADI_HDL_DIR)/library/axi_ad9361/axi_ad9361_delay.tcl 10 | 11 | LIB_DEPS += axi_ad9361 12 | LIB_DEPS += axi_dmac 13 | LIB_DEPS += util_fir_dec 14 | LIB_DEPS += util_fir_int 15 | 16 | default: $(PROJECT_NAME).runs/impl_1/system_top.bit 17 | 18 | include $(ADI_HDL_DIR)/projects/scripts/project-xilinx.mk 19 | 20 | $(PROJECT_NAME).runs/impl_1/system_top.bit: $(PROJECT_NAME).xpr 21 | 22 | # HL & NC: quiet.mk (just color) 23 | 24 | $(PROJECT_NAME).xpr: $(M_DEPS) |lib 25 | -rm -rf $(CLEAN_TARGET) 26 | @echo "xpr" 27 | $(call build, \ 28 | $(VIVADO) system_project.tcl -tclargs xpr, \ 29 | $(PROJECT_NAME)_vivado.log, \ 30 | $(HL)$(PROJECT_NAME)$(NC) project) 31 | 32 | $(PROJECT_NAME).runs/impl_1/system_top.bit: $(PROJECT_NAME).xpr 33 | @echo "bit" 34 | $(call build, \ 35 | $(VIVADO) system_project.tcl -tclargs bitstream, \ 36 | $(PROJECT_NAME)_vivado.log, \ 37 | $(HL)$(PROJECT_NAME)$(NC) bitstream) 38 | 39 | bit: $(PROJECT_NAME).runs/impl_1/system_top.bit 40 | xpr: $(PROJECT_NAME).xpr 41 | 42 | CLEAN_TARGET += image 43 | include $(OSCIMP_DIGITAL_IP)/dfu_frm.mk 44 | 45 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/project1/design/system_project.tcl: -------------------------------------------------------------------------------- 1 | variable adi_hdl_dir $::env(ADI_HDL_DIR) 2 | source $adi_hdl_dir/projects/scripts/adi_env.tcl 3 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 4 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 5 | 6 | set p_device "xc7z010clg225-1" 7 | 8 | # xpr creation and bitstream generation 9 | set action [lindex $argv 0] 10 | 11 | puts $action 12 | 13 | if {[string equal -nocase $action "xpr"]} { 14 | adi_project_xilinx pluto 15 | 16 | adi_project_files pluto [list \ 17 | "system_top.v" \ 18 | "system_constr.xdc" \ 19 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] 20 | 21 | set_property is_enabled false [get_files *system_sys_ps7_0.xdc] 22 | 23 | save_bd_design 24 | 25 | close_project 26 | 27 | } else { 28 | open_project pluto.xpr 29 | 30 | adi_project_run pluto 31 | source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl 32 | } 33 | 34 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/project1/module_generator.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 12 | 13 | 14 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/project2/app/Makefile: -------------------------------------------------------------------------------- 1 | BASE_NAME=project2 2 | USE_STATIC_LIB+=1 3 | LDFLAGS+=-liio 4 | CORE_MODULES_LIST = \ 5 | ${OSCIMP_DIGITAL_DRIVER}/data_to_ram_core/data_to_ram_core.ko \ 6 | ${OSCIMP_DIGITAL_DRIVER}/nco_counter_core/nco_counter_core.ko 7 | include $(OSCIMP_DIGITAL_APP)/Makefile.inc 8 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/project2/app/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | /* memory management */ 10 | #include 11 | #include 12 | 13 | #include 14 | 15 | #define ELEMENT_SIZE 1024 // Nb Sample 16 | 17 | #define CLK_FREQ 2000000 18 | #define MOD_FREQ 100000 19 | #define NCO_ACCUM_SIZE 28 20 | #define CHANNEL 3 21 | 22 | int main() 23 | { 24 | int16_t *rawData; 25 | int ramfd = 0, i, ii; 26 | 27 | rawData = (int16_t *) malloc(CHANNEL * 2 * ELEMENT_SIZE * sizeof(int16_t)); 28 | 29 | /* NCO configuration */ 30 | nco_counter_send_conf("/dev/nco00", CLK_FREQ, MOD_FREQ, 31 | NCO_ACCUM_SIZE, 0, 1, 1); // 0, 1, 1 => offset, PINC HW/SF, POFF HW/SF 32 | 33 | ramfd = open("/dev/data00", O_RDONLY); 34 | if (ramfd < 0) { 35 | perror("ram open error\n"); 36 | return EXIT_FAILURE; 37 | } 38 | read(ramfd, rawData, CHANNEL * 2 * ELEMENT_SIZE * sizeof(int16_t)); 39 | FILE *fd = fopen("data.dat", "w"); 40 | for (i = 0; i < CHANNEL * 2 * ELEMENT_SIZE; i+=(CHANNEL * 2)) { 41 | for (ii=0; ii < CHANNEL * 2; ii++) 42 | fprintf(fd, "%d ", rawData[i + ii]); 43 | fprintf(fd, "\n"); 44 | } 45 | 46 | fclose(fd); 47 | close(ramfd); 48 | free(rawData); 49 | return EXIT_SUCCESS; 50 | } 51 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/project2/app/project2.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /plugin/; 3 | 4 | / { 5 | compatible = "xlnx,zynq-7000"; 6 | 7 | fragment0 { 8 | target = <&fpga_axi>; 9 | #address-cells = <1>; 10 | #size-cells = <1>; 11 | __overlay__ { 12 | #address-cells = <1>; 13 | #size-cells = <1>; 14 | 15 | data00: data00@43c10000{ 16 | compatible = "ggm,dataToRam"; 17 | reg = <0x43c10000 0xffff>; 18 | }; 19 | 20 | nco00: nco00@43c00000{ 21 | compatible = "ggm,nco_counter"; 22 | reg = <0x43c00000 0xffff>; 23 | }; 24 | 25 | }; 26 | }; 27 | }; 28 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/project2/design/Makefile: -------------------------------------------------------------------------------- 1 | #################################################################################### 2 | ## Copyright 2018(c) Analog Devices, Inc. 3 | ## Auto-generated, do not modify! 4 | #################################################################################### 5 | 6 | PROJECT_NAME := pluto 7 | 8 | M_DEPS += $(ADI_HDL_DIR)/library/xilinx/common/ad_iobuf.v 9 | M_DEPS += $(ADI_HDL_DIR)/library/axi_ad9361/axi_ad9361_delay.tcl 10 | 11 | LIB_DEPS += axi_ad9361 12 | LIB_DEPS += axi_dmac 13 | LIB_DEPS += util_fir_dec 14 | LIB_DEPS += util_fir_int 15 | 16 | default: $(PROJECT_NAME).runs/impl_1/system_top.bit 17 | 18 | include $(ADI_HDL_DIR)/projects/scripts/project-xilinx.mk 19 | 20 | $(PROJECT_NAME).runs/impl_1/system_top.bit: $(PROJECT_NAME).xpr 21 | 22 | # HL & NC: quiet.mk (just color) 23 | 24 | $(PROJECT_NAME).xpr: $(M_DEPS) |lib 25 | -rm -rf $(CLEAN_TARGET) 26 | @echo "xpr" 27 | $(call build, \ 28 | $(VIVADO) system_project.tcl -tclargs xpr, \ 29 | $(PROJECT_NAME)_vivado.log, \ 30 | $(HL)$(PROJECT_NAME)$(NC) project) 31 | 32 | $(PROJECT_NAME).runs/impl_1/system_top.bit: $(PROJECT_NAME).xpr 33 | @echo "bit" 34 | $(call build, \ 35 | $(VIVADO) system_project.tcl -tclargs bitstream, \ 36 | $(PROJECT_NAME)_vivado.log, \ 37 | $(HL)$(PROJECT_NAME)$(NC) bitstream) 38 | 39 | bit: $(PROJECT_NAME).runs/impl_1/system_top.bit 40 | xpr: $(PROJECT_NAME).xpr 41 | 42 | CLEAN_TARGET += image 43 | include $(OSCIMP_DIGITAL_IP)/dfu_frm.mk 44 | 45 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/project2/design/system_project.tcl: -------------------------------------------------------------------------------- 1 | variable adi_hdl_dir $::env(ADI_HDL_DIR) 2 | source $adi_hdl_dir/projects/scripts/adi_env.tcl 3 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 4 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 5 | 6 | set p_device "xc7z010clg225-1" 7 | 8 | # xpr creation and bitstream generation 9 | set action [lindex $argv 0] 10 | 11 | puts $action 12 | 13 | if {[string equal -nocase $action "xpr"]} { 14 | adi_project_xilinx pluto 15 | 16 | adi_project_files pluto [list \ 17 | "system_top.v" \ 18 | "system_constr.xdc" \ 19 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] 20 | 21 | set_property is_enabled false [get_files *system_sys_ps7_0.xdc] 22 | 23 | save_bd_design 24 | 25 | close_project 26 | 27 | } else { 28 | open_project pluto.xpr 29 | 30 | adi_project_run pluto 31 | source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl 32 | } 33 | 34 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/1-adalmPluto_within_OscimpDigital/project2/module_generator.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 12 | 13 | 14 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/190524gps_xcorr/go.m: -------------------------------------------------------------------------------- 1 | filelist=dir("max*.dat.gz"); 2 | for k=1:length(filelist) 3 | a=load(filelist(k).name); 4 | d(:,k)=a; 5 | %figure() 6 | %plot(a) 7 | end 8 | imagesc(d); 9 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/190524gps_xcorr/gogps_bin.m: -------------------------------------------------------------------------------- 1 | close all;clear all; more off; set (0,"defaultaxesfontname","Helvetica") 2 | tic 3 | pkg load signal 4 | 5 | x=read_complex_binary('./gps.bin'); 6 | fs=1.023; % MHz 7 | freq0=[-1.0e4:500:1.0e4]-20000; 8 | 9 | x=x(1:2e5); 10 | time=[0:1/fs/1e6:length(x)/fs/1e6]';time=time(1:end-1); 11 | tic 12 | for m=[1:31] 13 | a=cacode(m,fs/1.023); a=a-mean(a); 14 | l=1; 15 | m 16 | for freq=freq0 % run through possible frequency offsets 17 | mysine=exp(j*2*pi*(-freq)*time); 18 | xx=x.*mysine; % frequency shift the signal 19 | [u(l,m),v(l,m)]=max(abs(xcorr(a,xx))); % check for cross correlation max. 20 | l=l+1; 21 | end 22 | %imagesc(abs(u)) 23 | %pause(0.01) 24 | end 25 | toc 26 | imagesc([1:31],-freq0-20000,abs(u)) 27 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/190524gps_xcorr/gps.bin: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 | % 2 | % Copyright 2001 Free Software Foundation, Inc. 3 | % 4 | % This file is part of GNU Radio 5 | % 6 | % GNU Radio is free software; you can redistribute it and/or modify 7 | % it under the terms of the GNU General Public License as published by 8 | % the Free Software Foundation; either version 3, or (at your option) 9 | % any later version. 10 | % 11 | % GNU Radio is distributed in the hope that it will be useful, 12 | % but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | % MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | % GNU General Public License for more details. 15 | % 16 | % You should have received a copy of the GNU General Public License 17 | % along with GNU Radio; see the file COPYING. If not, write to 18 | % the Free Software Foundation, Inc., 51 Franklin Street, 19 | % Boston, MA 02110-1301, USA. 20 | % 21 | 22 | function v = read_complex_binary (filename, count) 23 | 24 | %% usage: read_complex_binary (filename, [count]) 25 | %% 26 | %% open filename and return the contents as a column vector, 27 | %% treating them as 32 bit complex numbers 28 | %% 29 | 30 | m = nargchk (1,2,nargin); 31 | if (m) 32 | usage (m); 33 | end 34 | 35 | if (nargin < 2) 36 | count = Inf; 37 | end 38 | 39 | f = fopen (filename, 'rb'); 40 | if (f < 0) 41 | v = 0; 42 | else 43 | t = fread (f, [2, count], 'float'); 44 | fclose (f); 45 | v = t(1,:) + t(2,:)*i; 46 | [r, c] = size (v); 47 | v = reshape (v, c, r); 48 | end 49 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/2-PRN_on_PL.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/plutosdr/2-PRN_on_PL/2-PRN_on_PL.pdf -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/Makefile: -------------------------------------------------------------------------------- 1 | all: 2-PRN_on_PL.pdf 2 | 3 | 2-PRN_on_PL.pdf: 2-PRN_on_PL.tex 4 | pdflatex $^ 5 | pdflatex $^ 6 | 7 | clean: 8 | rm *.log *.aux *.out *bak 2-PRN_on_PL.pdf 9 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/README.md: -------------------------------------------------------------------------------- 1 | Following the second tutorial, we consider a practical application of performing 2 | some of the computation not taken care of by the AD9363 on the Zynq PL, namely 3 | correlations in a CMDA demonstration. 4 | 5 | For those in a hurry, two bitstreams ready for compiling the PlutoSDR DFU image are provided 6 | in the [images](images) directory. 7 | 8 | The TCL script for generating the final design is available in [design](design). Once the 9 | synthesis is complete, opening the pluto.xpr file to get back to the initial steps, or editing 10 | the TCL script to add step by step functionalities, allow for following step by step the 11 | tutorial text. 12 | 13 | At the end of the tutorial, adding a bias-T and a GPS antenna should allow to process 14 | all space-vehicle PRN pseudo-random sequence for all possible Doppler frequency shifts 15 | and map the visible satellites as strong correlation peaks as seen below. 16 | 17 | ![GPS acquisition](images/gps_plutosdr.png) 18 | 19 | See [K.Borre, D.M.Akos, N.Bertelsen, P.Rinder, S.H.Jensen, A Software-Defined GPS and 20 | Galileo Receiver -- A Single-Frequency Approach, Springer (2007) 21 | ](https://www.springer.com/gp/book/9780817643904) for the theoretical background of 22 | CDMA decoding and GPS acquisition phase. 23 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/images/1xcorr_1PRN.bit: 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CORE_MODULES_LIST = \ 5 | ${OSCIMP_DIGITAL_DRIVER}/fpgagen_core/fpgagen_core.ko \ 6 | ${OSCIMP_DIGITAL_DRIVER}/data_to_ram_core/data_to_ram_core.ko 7 | include $(OSCIMP_DIGITAL_APP)/Makefile.inc 8 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/project_gps/app/go.m: -------------------------------------------------------------------------------- 1 | filelist=dir("max*.dat"); 2 | for k=1:length(filelist) 3 | a=load(filelist(k).name); 4 | d(:,k)=a; 5 | %figure() 6 | %plot(a) 7 | end 8 | imagesc(d); 9 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/project_gps/app/project_gps.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /plugin/; 3 | 4 | / { 5 | compatible = "xlnx,zynq-7000"; 6 | 7 | fragment0 { 8 | target = <&fpga_axi>; 9 | #address-cells = <1>; 10 | #size-cells = <1>; 11 | __overlay__ { 12 | #address-cells = <1>; 13 | #size-cells = <1>; 14 | 15 | select_cacode: select_cacode@43c20000{ 16 | compatible = "ggm,fpgagen"; 17 | reg = <0x43c20000 0xffff>; 18 | }; 19 | 20 | data3200: data3200@43c30000{ 21 | compatible = "ggm,dataToRam"; 22 | reg = <0x43c30000 0xffff>; 23 | }; 24 | 25 | }; 26 | }; 27 | }; 28 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/project_gps/design/Makefile: -------------------------------------------------------------------------------- 1 | #################################################################################### 2 | ## Copyright 2018(c) Analog Devices, Inc. 3 | ## Auto-generated, do not modify! 4 | #################################################################################### 5 | 6 | PROJECT_NAME := pluto 7 | 8 | M_DEPS += $(ADI_HDL_DIR)/library/xilinx/common/ad_iobuf.v 9 | M_DEPS += $(ADI_HDL_DIR)/library/axi_ad9361/axi_ad9361_delay.tcl 10 | 11 | LIB_DEPS += axi_ad9361 12 | LIB_DEPS += axi_dmac 13 | LIB_DEPS += util_fir_dec 14 | LIB_DEPS += util_fir_int 15 | 16 | include $(ADI_HDL_DIR)/projects/scripts/project-xilinx.mk 17 | CLEAN_TARGET += image 18 | include $(OSCIMP_DIGITAL_IP)/dfu_frm.mk 19 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/project_gps/design/system_project.tcl: -------------------------------------------------------------------------------- 1 | variable adi_hdl_dir $::env(ADI_HDL_DIR) 2 | source $adi_hdl_dir/projects/scripts/adi_env.tcl 3 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 4 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 5 | 6 | set p_device "xc7z010clg225-1" 7 | adi_project_xilinx pluto 8 | 9 | adi_project_files pluto [list \ 10 | "system_top.v" \ 11 | "system_constr.xdc" \ 12 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] 13 | 14 | set_property is_enabled false [get_files *system_sys_ps7_0.xdc] 15 | adi_project_run pluto 16 | source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl 17 | 18 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/project_gps/project_gps.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 11 | 12 | 13 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/project_prn/app/Makefile: -------------------------------------------------------------------------------- 1 | BASE_NAME=project_prn 2 | USE_STATIC_LIB+=1 3 | CORE_MODULES_LIST = \ 4 | ${OSCIMP_DIGITAL_DRIVER}/nco_counter_core/nco_counter_core.ko \ 5 | ${OSCIMP_DIGITAL_DRIVER}/switch_core/switch_core.ko \ 6 | ${OSCIMP_DIGITAL_DRIVER}/data_to_ram_core/data_to_ram_core.ko 7 | include $(OSCIMP_DIGITAL_APP)/Makefile.inc 8 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/project_prn/app/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | 7 | #include 8 | #include 9 | 10 | #define USE_NCO 1 11 | #undef USE_NCO 12 | 13 | #define NUM_PRN 2 14 | 15 | int fpga_configure(); 16 | 17 | int main() 18 | { 19 | /* two input (x2) x 2048 sample complex (x2) */ 20 | int32_t c[2048 * 2 *NUM_PRN]; 21 | int fi, fo; 22 | 23 | fpga_configure(); 24 | usleep(1000); 25 | 26 | fi = open("/dev/data3200", O_RDWR); 27 | fo = open("/tmp/data.bin", O_WRONLY | O_CREAT); 28 | read(fi, c, 2048 * 2 * NUM_PRN * sizeof(int32_t)); 29 | write(fo, c, 2048 * 2 * NUM_PRN * sizeof(int32_t)); 30 | 31 | close(fi); 32 | close(fo); 33 | } 34 | 35 | int fpga_configure() 36 | { 37 | #ifdef USE_NCO 38 | int freq = 20000; 39 | int ret; 40 | ret = nco_counter_send_conf("/dev/nco", 1000000/*20000000*/, freq, 32, 0, 1, 1); 41 | if (ret == EXIT_FAILURE) return EXIT_FAILURE; 42 | return switch_send_conf("/dev/use_nco", 1); 43 | #else 44 | return switch_send_conf("/dev/use_nco", 0); 45 | #endif 46 | } 47 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/project_prn/app/project_prn.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /plugin/; 3 | 4 | / { 5 | compatible = "xlnx,zynq-7000"; 6 | 7 | fragment0 { 8 | target = <&fpga_axi>; 9 | #address-cells = <1>; 10 | #size-cells = <1>; 11 | __overlay__ { 12 | #address-cells = <1>; 13 | #size-cells = <1>; 14 | 15 | }; 16 | }; 17 | }; 18 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/project_prn/design/Makefile: -------------------------------------------------------------------------------- 1 | #################################################################################### 2 | ## Copyright 2018(c) Analog Devices, Inc. 3 | ## Auto-generated, do not modify! 4 | #################################################################################### 5 | 6 | PROJECT_NAME := pluto 7 | 8 | M_DEPS += $(ADI_HDL_DIR)/library/xilinx/common/ad_iobuf.v 9 | M_DEPS += $(ADI_HDL_DIR)/library/axi_ad9361/axi_ad9361_delay.tcl 10 | 11 | LIB_DEPS += axi_ad9361 12 | LIB_DEPS += axi_dmac 13 | LIB_DEPS += util_fir_dec 14 | LIB_DEPS += util_fir_int 15 | 16 | default: $(PROJECT_NAME).runs/impl_1/system_top.bit 17 | 18 | include $(ADI_HDL_DIR)/projects/scripts/project-xilinx.mk 19 | 20 | $(PROJECT_NAME).runs/impl_1/system_top.bit: $(PROJECT_NAME).xpr 21 | 22 | # HL & NC: quiet.mk (just color) 23 | 24 | $(PROJECT_NAME).xpr: $(M_DEPS) |lib 25 | -rm -rf $(CLEAN_TARGET) 26 | @echo "xpr" 27 | $(call build, \ 28 | $(VIVADO) system_project.tcl -tclargs xpr, \ 29 | $(PROJECT_NAME)_vivado.log, \ 30 | $(HL)$(PROJECT_NAME)$(NC) project) 31 | 32 | $(PROJECT_NAME).runs/impl_1/system_top.bit: $(PROJECT_NAME).xpr 33 | @echo "bit" 34 | $(call build, \ 35 | $(VIVADO) system_project.tcl -tclargs bitstream, \ 36 | $(PROJECT_NAME)_vivado.log, \ 37 | $(HL)$(PROJECT_NAME)$(NC) bitstream) 38 | 39 | bit: $(PROJECT_NAME).runs/impl_1/system_top.bit 40 | xpr: $(PROJECT_NAME).xpr 41 | 42 | CLEAN_TARGET += image 43 | include $(OSCIMP_DIGITAL_IP)/dfu_frm.mk 44 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/project_prn/design/system_project.tcl: -------------------------------------------------------------------------------- 1 | variable adi_hdl_dir $::env(ADI_HDL_DIR) 2 | source $adi_hdl_dir/projects/scripts/adi_env.tcl 3 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 4 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 5 | 6 | set p_device "xc7z010clg225-1" 7 | adi_project_xilinx pluto 8 | 9 | adi_project_files pluto [list \ 10 | "system_top.v" \ 11 | "system_constr.xdc" \ 12 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] 13 | 14 | set_property is_enabled false [get_files *system_sys_ps7_0.xdc] 15 | adi_project_run pluto 16 | source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl 17 | 18 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/project_prn/project_prn.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 11 | 12 | 13 | 15 | 16 | 17 | 19 | 20 | 21 | 22 | 23 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/results/data_closed1.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/plutosdr/2-PRN_on_PL/results/data_closed1.bin -------------------------------------------------------------------------------- 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| a=fread(fd, Inf, "int32"); 12 | prn1=a(1:2:end)+i*a(2:2:end); 13 | subplot(312) 14 | plot(20*(abs(prn1)), 'r'); 15 | xlabel('sample (a.u.)') 16 | ylabel('xcorr (a.u.)') 17 | legend('open') 18 | 19 | fd=fopen("data_load1.bin"); 20 | a=fread(fd, Inf, "int32"); 21 | prn1=a(1:2:end)+i*a(2:2:end); 22 | subplot(313) 23 | plot(20*(abs(prn1)), 'g'); 24 | xlabel('sample (a.u.)') 25 | ylabel('xcorr (a.u.)') 26 | legend('load') 27 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/2-PRN_on_PL/results/readme.jmf: -------------------------------------------------------------------------------- 1 | open = 200 2 | closed=90000 3 | 20*log10(86000/600)=53 dB 4 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/99-gnuradio-audio/1-gnuradio-audio.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/plutosdr/99-gnuradio-audio/1-gnuradio-audio.pdf -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/99-gnuradio-audio/Makefile: -------------------------------------------------------------------------------- 1 | all: 1-gnuradio-audio.pdf 2 | 3 | 1-gnuradio-audio.pdf: 1-gnuradio-audio.tex 4 | pdflatex $^ 5 | pdflatex $^ 6 | 7 | clean: 8 | rm *.log *.aux *.out *bak 9 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/99-gnuradio-audio/README.md: -------------------------------------------------------------------------------- 1 | Custom IP demonstration by including an ALSA-compatible sound card interface in the Zynq PL of the PlutoSDR. 2 | 3 | ![PlutoSDR embedded sound card demo](figures/DSC_0108.jpg) 4 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/99-gnuradio-audio/audio.dts: -------------------------------------------------------------------------------- 1 | audio_clock: audio_clock { 2 | compatible = "fixed-clock"; 3 | #clock-cells = <0>; 4 | clock-frequency = <24576000>; 5 | }; 6 | 7 | codec_out: spdif-transmitter { 8 | #sound-dai-cells = <0>; 9 | compatible = "ggm,fake_codec"; 10 | clocks = <&audio_clock>; 11 | clock-names = "mclk"; 12 | 13 | status = "okay"; 14 | }; 15 | 16 | axi_deltaSigma_0: axi-deltaSigma@43c00000 { 17 | #sound-dai-cells = <0>; 18 | compatible = "ggm,axi-deltaSigma"; 19 | reg = <0x43c00000 0x1000>; 20 | dmas = <&dmac_s 0>; 21 | dma-names = "tx"; 22 | clocks = <&clkc 15>, <&audio_clock>; 23 | clock-names = "axi", "ref"; 24 | }; 25 | 26 | pluto_sound { 27 | compatible = "simple-audio-card"; 28 | simple-audio-card,name = "PlutoSDR PWM"; 29 | simple-audio-card,widgets = "Line", "Line Out"; 30 | simple-audio-card,routing = 31 | "Line Out", "LOUT", 32 | "Line Out", "ROUT"; 33 | 34 | simple-audio-card,dai-link@0 { 35 | format = "i2s"; 36 | cpu { 37 | sound-dai = <&axi_deltaSigma_0>; 38 | frame-master; 39 | bitclock-master; 40 | }; 41 | codec { 42 | sound-dai = <&codec_out>; 43 | }; 44 | }; 45 | }; 46 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/99-gnuradio-audio/cpp_signal_to_audio/Makefile: -------------------------------------------------------------------------------- 1 | LINK=arm-linux-g++ 2 | PKGCONFIG=$(BR_DIR)/output/host/bin/pkg-config 3 | LIBS=$(shell $(PKGCONFIG) --libs gnuradio-analog gnuradio-filter gnuradio-audio) 4 | LIBS+= $(SUBLIBS) -lrt -ldl -lpthread 5 | LIBS+=-lgnuradio-runtime -lgnuradio-analog -lboost_system -lgnuradio-blocks 6 | 7 | CFLAGS = -O2 -Wall -W -D_REENTRANT -fPIE $(DEFINES) -std=gnu++11 8 | CXXFLAGS = -I$(BR_DIR)/output/staging/usr/include 9 | CXXFLAGS+= $(shell $(PKGCONFIG) --cflags gnuradio-analog gnuradio-filter gnuradio-audio) 10 | CXXFLAGS+= -Os -O2 -O3 -Wall -W -D_REENTRANT -fPIE $(DEFINES) $(INCPATH) -std=gnu++11 11 | 12 | TARGET=cpp_signal_to_audio 13 | SRC=$(wildcard *.cpp) 14 | OBJS=$(SRC:.cpp=.o) 15 | 16 | ALL: $(TARGET) 17 | 18 | $(TARGET):$(OBJS) 19 | $(LINK) $(LFLAGS) -o $(@) $< $(OBJCOMP) $(LIBS) 20 | 21 | %.o:%.cpp 22 | $(LINK) $(CXXFLAGS) -o $@ -c $< 23 | 24 | clean: 25 | rm -f $(TARGET) $(OBJS) 26 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/99-gnuradio-audio/cpp_signal_to_audio/main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include //sleep 10 | #include 11 | 12 | #include 13 | 14 | #include 15 | 16 | /* 17 | self.audio_sink_0 = audio.sink(48000, '', True) 18 | self.analog_sig_source_x_1 = analog.sig_source_f(samp_rate, analog.GR_SIN_WAVE, 1000, 1, 0) 19 | 20 | self.connect((self.analog_sig_source_x_1, 0), (self.audio_sink_0, 0)) 21 | 22 | */ 23 | 24 | int main(void) 25 | { 26 | double samp_rate = 48000; 27 | 28 | gr::top_block_sptr top_block; 29 | top_block = gr::make_top_block("Acquisition test"); 30 | 31 | boost::shared_ptr source = gr::analog::sig_source_f::make(samp_rate, 32 | gr::analog::GR_SIN_WAVE, 1000, 1, 0); 33 | 34 | boost::shared_ptraudio_sink = gr::audio::sink::make(samp_rate, "", true); 35 | 36 | top_block->connect(source, 0, audio_sink, 0); 37 | 38 | top_block->start(); // Start threads and wait 39 | printf("hit a key to stop app\n"); 40 | getchar(); 41 | top_block->stop(); 42 | top_block->wait(); 43 | 44 | return EXIT_SUCCESS; 45 | } 46 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/99-gnuradio-audio/design/Makefile: -------------------------------------------------------------------------------- 1 | #################################################################################### 2 | ## Copyright 2018(c) Analog Devices, Inc. 3 | ## Auto-generated, do not modify! 4 | #################################################################################### 5 | 6 | PROJECT_NAME := pluto 7 | 8 | M_DEPS += $(ADI_HDL_DIR)/library/xilinx/common/ad_iobuf.v 9 | M_DEPS += $(ADI_HDL_DIR)/library/axi_ad9361/axi_ad9361_delay.tcl 10 | 11 | LIB_DEPS += axi_ad9361 12 | LIB_DEPS += axi_dmac 13 | LIB_DEPS += util_fir_dec 14 | LIB_DEPS += util_fir_int 15 | 16 | include $(ADI_HDL_DIR)/projects/scripts/project-xilinx.mk 17 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/99-gnuradio-audio/design/system_project.tcl: -------------------------------------------------------------------------------- 1 | variable adi_hdl_dir $::env(ADI_HDL_DIR) 2 | source $adi_hdl_dir/projects/scripts/adi_env.tcl 3 | source $ad_hdl_dir/projects/scripts/adi_project.tcl 4 | source $ad_hdl_dir/projects/scripts/adi_board.tcl 5 | 6 | set p_device "xc7z010clg225-1" 7 | adi_project_xilinx pluto 8 | 9 | adi_project_files pluto [list \ 10 | "system_top.v" \ 11 | "system_constr.xdc" \ 12 | "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] 13 | 14 | set_property is_enabled false [get_files *system_sys_ps7_0.xdc] 15 | adi_project_run pluto 16 | source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl 17 | 18 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/99-gnuradio-audio/figures/DSC_0108.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/plutosdr/99-gnuradio-audio/figures/DSC_0108.jpg -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/99-gnuradio-audio/figures/RC_filter.fig: -------------------------------------------------------------------------------- 1 | #FIG 3.2 Produced by xfig version 3.2.6a 2 | Landscape 3 | Center 4 | Inches 5 | Letter 6 | 100.00 7 | Single 8 | -2 9 | 1200 2 10 | 6 1350 1125 1650 1500 11 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 12 | 1500 1302 1500 1431 13 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 14 | 1500 1260 1500 1125 15 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 16 | 1420 1260 1580 1260 17 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 18 | 1420 1302 1580 1302 19 | -6 20 | 6 1575 1125 1875 1500 21 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 22 | 1725 1302 1725 1431 23 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 24 | 1725 1260 1725 1125 25 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 26 | 1645 1260 1805 1260 27 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 28 | 1645 1302 1805 1302 29 | -6 30 | 6 975 900 1425 1050 31 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 32 | 1425 975 1324 975 33 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 34 | 1067 975 975 975 35 | 2 1 0 1 0 -1 0 0 -1 0.000 0 1 -1 0 0 7 36 | 1325 975 1299 940 1247 1010 1195 940 1143 1010 1091 940 37 | 1065 975 38 | -6 39 | 6 975 675 1425 825 40 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 41 | 1425 750 1324 750 42 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 43 | 1067 750 975 750 44 | 2 1 0 1 0 -1 0 0 -1 0.000 0 1 -1 0 0 7 45 | 1325 750 1299 715 1247 785 1195 715 1143 785 1091 715 46 | 1065 750 47 | -6 48 | 6 1501 1575 1677 1832 49 | 2 1 0 1 0 -1 0 0 -1 0.000 0 1 -1 0 0 2 50 | 1673 1746 1630 1832 51 | 2 1 0 1 0 -1 0 0 -1 0.000 0 1 -1 0 0 2 52 | 1630 1746 1587 1832 53 | 2 1 0 1 0 -1 0 0 -1 0.000 0 1 -1 0 0 2 54 | 1587 1746 1544 1832 55 | 2 1 0 1 0 -1 0 0 -1 0.000 0 1 -1 0 0 2 56 | 1544 1746 1501 1832 57 | 2 1 0 1 0 -1 0 0 -1 0.000 0 1 -1 0 0 2 58 | 1501 1746 1677 1746 59 | 2 1 0 1 0 -1 0 0 -1 0.000 0 0 -1 0 0 2 60 | 1587 1575 1587 1746 61 | -6 62 | 6 300 600 975 1050 63 | 4 0 0 50 -1 0 12 0.0000 4 165 540 375 750 left_in\001 64 | 4 0 0 50 -1 0 12 0.0000 4 180 660 300 975 right_in\001 65 | -6 66 | 6 2400 615 3165 1020 67 | 4 0 0 50 -1 0 12 0.0000 4 165 645 2400 750 left_out\001 68 | 4 0 0 50 -1 0 12 0.0000 4 180 765 2400 975 right_out\001 69 | -6 70 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 71 | 1725 1425 1725 1500 1575 1500 72 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 4 73 | 1500 1425 1500 1500 1587 1500 1587 1575 74 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 75 | 1425 750 2325 750 76 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 77 | 5 1 1.00 60.00 60.00 78 | 1500 1125 1500 936 79 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 80 | 1425 975 2325 975 81 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 82 | 5 1 1.00 30.00 60.00 83 | 1725 1125 1725 714 84 | 4 0 0 50 -1 0 12 0.0000 4 135 360 1050 600 3.3k\001 85 | 4 0 0 50 -1 0 12 0.0000 4 135 360 1050 1200 3.3k\001 86 | 4 0 0 50 -1 0 12 0.0000 4 135 510 900 1500 4.7 nF\001 87 | 4 0 0 50 -1 0 12 0.0000 4 135 510 1800 1500 4.7 nF\001 88 | -------------------------------------------------------------------------------- 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Inches 5 | Letter 6 | 100.00 7 | Single 8 | -2 9 | 1200 2 10 | 2 5 0 1 0 -1 50 -1 -1 0.000 0 0 -1 0 0 5 11 | 0 DSC_0108.jpg 12 | 975 1575 6735 1575 6735 4815 975 4815 975 1575 13 | 2 1 0 2 4 7 50 -1 -1 0.000 0 0 -1 1 0 2 14 | 1 0 1.00 60.00 120.00 15 | 4725 3975 4575 3525 16 | 2 1 0 2 4 7 50 -1 -1 0.000 0 0 -1 1 0 2 17 | 1 0 1.00 60.00 120.00 18 | 1875 2250 1800 4125 19 | 2 1 0 2 4 7 50 -1 -1 0.000 0 0 -1 1 0 2 20 | 1 0 1.00 60.00 120.00 21 | 1875 2250 2700 3225 22 | 2 1 0 2 4 7 50 -1 -1 0.000 0 0 -1 1 0 2 23 | 1 0 1.00 60.00 120.00 24 | 4125 1800 3900 1875 25 | 2 1 0 2 4 7 50 -1 -1 0.000 0 0 -1 1 0 2 26 | 1 0 1.00 60.00 120.00 27 | 5400 1950 5250 2175 28 | 4 0 4 50 -1 0 12 0.0000 4 180 1305 1350 2175 Stereo earphone\001 29 | 4 0 4 50 -1 0 12 0.0000 4 180 780 3750 1725 Left/right\001 30 | 4 0 4 50 -1 0 12 0.0000 4 180 900 4275 4125 Audio jack\001 31 | 4 0 4 50 -1 0 12 0.0000 4 135 750 5175 1875 RC Filter\001 32 | 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| Letter 6 | 100.00 7 | Single 8 | -2 9 | 1200 2 10 | 2 5 0 1 0 -1 50 -1 -1 0.000 0 0 -1 0 0 5 11 | 0 pluto_gpio_connector.jpg 12 | 525 525 3105 525 3105 1791 525 1791 525 525 13 | 2 1 0 1 4 7 50 -1 -1 0.000 0 0 -1 1 0 3 14 | 1 0 1.00 60.00 120.00 15 | 1800 1575 1425 1575 1275 1425 16 | 2 1 0 1 4 7 50 -1 -1 0.000 0 0 -1 1 0 3 17 | 1 0 1.00 60.00 120.00 18 | 1500 600 1125 600 975 825 19 | 2 1 0 1 4 7 50 -1 -1 0.000 0 0 -1 1 0 3 20 | 1 0 1.00 60.00 120.00 21 | 2925 1275 2925 1350 2700 1350 22 | 4 0 4 50 -1 2 12 0.0000 4 165 1215 1800 1650 Right Channel\001 23 | 4 0 4 50 -1 2 12 0.0000 4 135 1095 1575 675 Left Channel\001 24 | 4 0 4 50 -1 2 12 0.0000 4 135 420 2625 1200 GND\001 25 | -------------------------------------------------------------------------------- /doc/tutorials/plutosdr/99-gnuradio-audio/figures/pluto_gpio_connector.jpg: -------------------------------------------------------------------------------- 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-std=gnu++11 8 | CXXFLAGS = -I$(BR_DIR)/output/staging/usr/include 9 | CXXFLAGS+= $(shell $(PKGCONFIG) --cflags gnuradio-analog gnuradio-filter gnuradio-audio gnuradio-iio) 10 | CXXFLAGS+= -Os -O2 -O3 -Wall -W -D_REENTRANT -fPIE $(DEFINES) $(INCPATH) -std=gnu++11 11 | 12 | TARGET=radioFM 13 | SRC=$(wildcard *.cpp) 14 | OBJS=$(SRC:.cpp=.o) 15 | 16 | ALL: $(TARGET) 17 | 18 | $(TARGET):$(OBJS) 19 | $(LINK) $(LFLAGS) -o $(@) $< $(OBJCOMP) $(LIBS) 20 | 21 | %.o:%.cpp 22 | $(LINK) $(CXXFLAGS) -o $@ -c $< 23 | 24 | clean: 25 | rm -f $(TARGET) $(OBJS) 26 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/2-PL/2-PL.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/redpitaya/2-PL/2-PL.pdf -------------------------------------------------------------------------------- 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0 0 50 -1 0 12 0.0000 4 180 2370 4230 4635 GNU/Linux for FPGA config.\001 22 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/2-PL/figures/objective.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/redpitaya/2-PL/figures/objective.pdf -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/2-PL/figures/objective.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/redpitaya/2-PL/figures/objective.png -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/3-PLPS/3-fpga_PLPS.pdf: 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-------------------------------------------------------------------------------- /doc/tutorials/redpitaya/3-PLPS/app/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | int main() 7 | {int k; 8 | char c[16384]; 9 | int fi,fo; 10 | fi=open("/dev/data1600",O_RDWR); 11 | fo=open("/tmp/data.bin",O_WRONLY|O_CREAT); 12 | for (k=1;k<5;k++) 13 | {read(fi,c,16384); 14 | write(fo,c,16384); 15 | } 16 | close(fi); 17 | close(fo); 18 | } 19 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/3-PLPS/app/tutorial3.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /plugin/; 3 | 4 | / { 5 | compatible = "xlnx,zynq-7000"; 6 | 7 | fragment0 { 8 | target = <&fpga_full>; 9 | #address-cells = <1>; 10 | #size-cells = <1>; 11 | __overlay__ { 12 | #address-cells = <1>; 13 | #size-cells = <1>; 14 | 15 | firmware-name = "tutorial3_wrapper.bit.bin"; 16 | 17 | data1600: data1600@43c00000{ 18 | compatible = "ggm,dataToRam"; 19 | reg = <0x43c00000 0xffff>; 20 | }; 21 | 22 | }; 23 | }; 24 | }; 25 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/3-PLPS/app/tutorial3_us.sh: -------------------------------------------------------------------------------- 1 | CORE_MODULES_DIR=../../modules 2 | 3 | mkdir -p /lib/firmware 4 | cp ../bitstreams/tutorial3_wrapper.bit.bin /lib/firmware 5 | DTB_DIR=/sys/kernel/config/device-tree/overlays/fpga 6 | rmdir $DTB_DIR 7 | mkdir $DTB_DIR 8 | cat tutorial3.dtbo > $DTB_DIR/dtbo 9 | 10 | insmod ${CORE_MODULES_DIR}/data_to_ram_core.ko 11 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/3-PLPS/design/Makefile: -------------------------------------------------------------------------------- 1 | NAME=tutorial3 2 | BASE_TCL = ${NAME}.tcl 3 | 4 | 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4950 4590 18 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 19 | 4185 4410 6705 4410 20 | 4 0 0 50 -1 0 12 0.0000 4 135 405 4275 4230 ADC\001 21 | 4 0 0 50 -1 0 12 0.0000 4 135 405 6165 4230 DAC\001 22 | 4 0 0 50 -1 0 12 0.0000 4 135 285 3825 4230 PL:\001 23 | 4 0 0 50 -1 0 12 0.0000 4 135 270 3825 4635 PS:\001 24 | 4 0 0 50 -1 0 12 0.0000 4 180 1680 4995 4635 samples to userspace\001 25 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/3-PLPS/figures/objective.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/redpitaya/3-PLPS/figures/objective.pdf -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/3-PLPS/figures/objective.png: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /doc/tutorials/redpitaya/4-FIR/app/coefs.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 1 3 | 1 4 | 1 5 | 1 6 | 1 7 | 1 8 | 1 9 | 1 10 | 1 11 | 1 12 | 1 13 | 1 14 | 1 15 | 1 16 | 1 17 | 1 18 | 1 19 | 1 20 | 1 21 | 1 22 | 1 23 | 1 24 | 1 25 | 1 26 | 1 27 | 1 28 | 1 29 | 1 30 | 1 31 | 1 32 | 1 33 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/4-FIR/app/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include "fir_conf.h" // library for communicating with the FIR 7 | 8 | 9 | int main() 10 | {int k; 11 | char c[16384]; 12 | int fi,fo; 13 | fi=open("/dev/data1600",O_RDWR); 14 | fo=open("/tmp/data.bin",O_WRONLY|O_CREAT,S_IRWXU); 15 | fir_send_confSigned("/dev/fir00","coefs.txt",32); 16 | for (k=1;k<5;k++) 17 | {read(fi,c,16384); 18 | write(fo,c,16384); 19 | } 20 | close(fi); 21 | close(fo); 22 | return 0; 23 | } 24 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/4-FIR/app/tutorial4.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /plugin/; 3 | 4 | / { 5 | compatible = "xlnx,zynq-7000"; 6 | 7 | fragment0 { 8 | target = <&fpga_full>; 9 | #address-cells = <1>; 10 | #size-cells = <1>; 11 | __overlay__ { 12 | #address-cells = <1>; 13 | #size-cells = <1>; 14 | 15 | firmware-name = "tutorial4_wrapper.bit.bin"; 16 | 17 | data1600: data1600@43C00000{ 18 | compatible = "ggm,dataToRam"; 19 | reg = <0x43C00000 0xffff>; 20 | }; 21 | 22 | fir00: fir00@43C10000{ 23 | compatible = "ggm,fir"; 24 | reg = <0x43C10000 0xffff>; 25 | }; 26 | 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- 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0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 22 | 0 0 1.00 60.00 60.00 23 | 5400 4185 5400 4545 5490 4545 24 | 2 4 0 1 0 7 50 -1 -1 0.000 0 0 7 0 0 5 25 | 7245 4770 7245 3960 4185 3960 4185 4770 7245 4770 26 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4 27 | 0 0 1.00 60.00 60.00 28 | 6030 4500 6030 4320 5490 4320 5490 4185 29 | 4 0 0 50 -1 0 12 0.0000 4 135 285 3825 4230 PL:\001 30 | 4 0 0 50 -1 0 12 0.0000 4 135 270 3825 4635 PS:\001 31 | 4 0 0 50 -1 0 12 0.0000 4 135 405 4275 4140 ADC\001 32 | 4 0 0 50 -1 0 8 0.0000 4 90 675 5670 4292 coefficients\001 33 | 4 0 0 50 -1 0 12 0.0000 4 180 1680 5490 4635 samples to userspace\001 34 | 4 0 0 50 -1 0 12 0.0000 4 135 405 6750 4140 DAC\001 35 | 4 0 0 50 -1 0 12 0.0000 4 135 300 5265 4140 FIR\001 36 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/4-FIR/figures/objective.pdf: -------------------------------------------------------------------------------- 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/doc/tutorials/redpitaya/4-FIR/results/model.m: -------------------------------------------------------------------------------- 1 | N=32 2 | subplot(211) 3 | longueurs=[4 8 16 28]; 4 | for longueur=longueurs 5 | bt=[ones(1,longueur) zeros(1,N-longueur)]; 6 | length(bt) 7 | bf=fftshift(abs(fft(bt,4096))); 8 | bf=bf./max(bf); 9 | f=linspace(-125/2,125/2,length(bf)); 10 | plot(f,20*log10(bf));hold on 11 | end 12 | axis tight 13 | xlabel('freq (MHz)') 14 | ylabel('relative power (dB)') 15 | legend('4x1 + 28x0','8x1 + 24x0','16x1 + 16x0','28x1 + 4x0','location','southwest') 16 | 17 | subplot(212) 18 | longueurs=[16 24 26 28]; 19 | for longueur=longueurs 20 | bt=[ones(1,longueur) zeros(1,N-longueur)]; 21 | length(bt) 22 | bf=fftshift(abs(fft(bt,4096))); 23 | bf=bf./max(bf); 24 | f=linspace(-125/2,125/2,length(bf)); 25 | plot(f,20*log10(bf));hold on 26 | end 27 | axis([0 10 -45 0]) 28 | xlabel('relative power (dB)') 29 | ylabel('relative power (dB)') 30 | legend('16x1 + 16x0','24x1 + 8x0','26x1 + 6x0','28x1 + 4x0','location','southwest') 31 | 32 | % amplitude v.s frequency measurement 33 | freq=[0.1 0.5 1 1.5 2 2.5 3 4 5 6 7]; % MHz 34 | meas=[0130 0130 0128 0126 0122 0115 0110 0093 0070 0050 0027 ; % 16/16 35 | 0188 0186 0180 0170 0150 0133 0112 0066 0019 0037 0059 ; % 24/08 36 | 0200 0200 0190 0178 0155 0131 0109 0053 0020 0053 0064 ; % 26/06 37 | 0216 0213 0203 0186 0160 0130 0102 0035 0034 0064 0062]; % 28/04 38 | for k=1:4 39 | <<<<<<< HEAD 40 | plot(freq,10*log10(meas(k,:)/(max(meas(k,:)))),'o'); 41 | ======= 42 | plot(freq,20*log10(meas(k,:)/(max(meas(k,:)))),'o'); 43 | >>>>>>> 0d5c20b51512c84f13879f58a4d079e23c87988b 44 | % plot(freq,20*log10(meas(k,:)/(1500)),'o'); 45 | end 46 | 47 | % frequency at which the amplitude is lowest (notch position) 48 | line([7.8 7.8],[-50 0]) % 16x1 49 | line([5.2 5.2],[-50 0]) % 24x1 50 | line([4.8 4.8],[-50 0]) % 26x1 51 | line([4.5 4.5],[-50 0]) % 28x1 52 | line([8.9 8.9],[-50 0]) % 28x1 (second) 53 | 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-------------------------------------------------------------------------------- /doc/tutorials/redpitaya/5-NCO/app/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include "nco_conf.h" 6 | 7 | // 3 complex short = 6*2*2 bytes/measurement 8 | #define channels 12 9 | 10 | int main() 11 | {char c[4096*channels]; 12 | int fi,fo; 13 | fi=open("/dev/data1600",O_RDWR); 14 | fo=open("/tmp/data.bin",O_WRONLY|O_CREAT,0666); 15 | nco_counter_send_conf("/dev/datanco", 125000000, 10000000, 32, 0, 1, 1); 16 | // /dev f_ck=125M f_o=10M acc offs pinc poff 17 | read(fi,c,4096*channels); 18 | write(fo,c,4096*channels); 19 | close(fi); 20 | close(fo); 21 | } 22 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/5-NCO/app/tutorial5.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /plugin/; 3 | 4 | / { 5 | compatible = "xlnx,zynq-7000"; 6 | 7 | fragment0 { 8 | target = <&fpga_full>; 9 | #address-cells = <1>; 10 | #size-cells = <1>; 11 | __overlay__ { 12 | #address-cells = <1>; 13 | #size-cells = <1>; 14 | 15 | firmware-name = "tutorial5_wrapper.bit.bin"; 16 | 17 | data1600: data1600@43C10000{ 18 | compatible = "ggm,dataToRam"; 19 | reg = <0x43C10000 0xffff>; 20 | }; 21 | 22 | datanco: datanco@43C00000{ 23 | compatible = "ggm,nco_counter"; 24 | reg = <0x43C00000 0xffff>; 25 | }; 26 | 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/5-NCO/design/Makefile: -------------------------------------------------------------------------------- 1 | NAME=tutorial5 2 | BASE_TCL = ${NAME}.tcl 3 | 4 | include ${OSCIMP_DIGITAL_IP}/xilinx.mk 5 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/5-NCO/figures/10MHz0_0dBm.pdf: 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xlabel('frequency (Hz)') 21 | ylabel('FFT(ADC) (a.u.)') 22 | xlim([-10 10]) 23 | legend('2.5 MHz','3 MHz') 24 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/5-NCO/module_generator.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 7 | 8 | 9 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/5-NCO/results/10MHz0_0dBm.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/redpitaya/5-NCO/results/10MHz0_0dBm.bin -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/5-NCO/results/10MHz0_0dBm.eps.gz: -------------------------------------------------------------------------------- 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/doc/tutorials/redpitaya/5-NCO/results/go.m: -------------------------------------------------------------------------------- 1 | fs=125; % sampling frequency in MHz 2 | filelist=dir('./*MHz*.bin') 3 | for k=1:length(filelist) 4 | f=fopen(filelist(k).name); d=fread(f,inf,'int16'); fclose(f) 5 | figure 6 | subplot(211) 7 | adc=d(1:6:end); % 2 is same as 1 8 | mixed=d(3:6:end)+j*d(4:6:end); 9 | nco=d(5:6:end)+j*d(6:6:end); 10 | plot(real(nco(1:100)));hold on;plot(adc(1:100),'r'); 11 | xlabel('time (sample number)') 12 | ylabel('voltage (bits)') 13 | title(filelist(k).name) 14 | subplot(212) 15 | f=linspace(-fs/2,fs/2,length(adc));res=fftshift(abs(fft(adc))); 16 | plot(f,res/max(res));hold on 17 | f=linspace(-fs/2,fs/2,length(nco));res=fftshift(abs(fft(nco))); 18 | plot(f,res/max(res),'r'); 19 | f=linspace(-fs/2,fs/2,length(mixed));res=fftshift(abs(fft(mixed))); 20 | plot(f,res/max(res),'g'); 21 | legend('ADC','NCO','mixer output','location','northwest') 22 | xlabel('frequency (MHz)') 23 | ylabel('FFT(ADC) (a.u.)') 24 | xlim([-11.5 11.5]) 25 | % eval(['print -depsc ',num2str(k),'.eps']) 26 | end 27 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/6_TCL/6-TCL.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/redpitaya/6_TCL/6-TCL.pdf -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/6_TCL/design/Makefile: -------------------------------------------------------------------------------- 1 | NAME=tutorial6 2 | BASE_TCL = ${NAME}.tcl 3 | 4 | include ${OSCIMP_DIGITAL_IP}/xilinx.mk 5 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/6_TCL/figures/objective.pdf: -------------------------------------------------------------------------------- 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"xlnx,zynq-7000"; 6 | 7 | fragment0 { 8 | target = <&fpga_full>; 9 | #address-cells = <1>; 10 | #size-cells = <1>; 11 | __overlay__ { 12 | #address-cells = <1>; 13 | #size-cells = <1>; 14 | 15 | firmware-name = "adcChanADmaDirect_wrapper.bit.bin"; 16 | 17 | data00: data00@43C01000 { 18 | compatible = "ggm,dataDmaDirect"; 19 | reg = <0x40400000 0xffff>, 20 | <0x43C01000 0xfff>; 21 | interrupt-parent = <&intc>; 22 | interrupts = <0 29 1>; 23 | }; 24 | 25 | }; 26 | }; 27 | }; 28 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/7_ADC_DMA/14bit/adcChanADmaDirect/app/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | /* memory management */ 10 | #include 11 | #include 12 | #include 13 | #include 14 | 15 | #define ACQUIS_SIZE 1000000 16 | 17 | int main() 18 | { 19 | int ret = EXIT_FAILURE;; 20 | int16_t *content; 21 | 22 | FILE *fileout; 23 | 24 | int fd_data = open("/dev/data00", O_RDWR); 25 | if (fd_data < 0) { 26 | printf("erreur d'ouverture de /dev/data00\n"); 27 | return EXIT_FAILURE; 28 | } 29 | 30 | content = (int16_t *) malloc(ACQUIS_SIZE * sizeof(int16_t)); 31 | if (content == NULL) { 32 | printf("erreur d'allocation\n"); 33 | goto content_malloc_fail; 34 | } 35 | 36 | fileout = fopen("dump.bin", "w+"); 37 | if (fileout == NULL) { 38 | printf("erreur d'ouverture de dump.bin\n"); 39 | goto out; 40 | } 41 | 42 | read(fd_data, content, ACQUIS_SIZE * sizeof(int16_t)); 43 | fwrite(content, sizeof(int16_t), ACQUIS_SIZE, fileout); 44 | fflush(fileout); 45 | fclose(fileout); 46 | 47 | ret = EXIT_SUCCESS; 48 | out: 49 | free(content); 50 | content_malloc_fail: 51 | close(fd_data); 52 | return ret; 53 | } 54 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/7_ADC_DMA/14bit/adcChanADmaDirect/design/Makefile: -------------------------------------------------------------------------------- 1 | PRJ=adcChanADmaDirect 2 | 3 | TCL_LIST = $(PRJ).tcl 4 | CONSTR = $(OSCIMP_DIGITAL_IP)/redpitaya_converters/redpitaya_converters_adc.xdc 5 | CONSTR += $(OSCIMP_DIGITAL_IP)/redpitaya_converters/redpitaya_converters.xdc 6 | 7 | -include $(OSCIMP_DIGITAL_IP)/fpga_ip.mk 8 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/7_ADC_DMA/14bit/adcChanADmaDirect/design/adcChanADmaDirect_dual.tcl: -------------------------------------------------------------------------------- 1 | set_property -dict [ list CONFIG.PCW_IRQ_F2P_INTR 1 \ 2 | CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ 3 | CONFIG.PCW_USE_S_AXI_HP0 {1} ] $ps7 4 | 5 | # ADC 6 | add_ip_and_conf redpitaya_converters converters { 7 | DAC_EN false \ 8 | ADC_SIZE 14 } 9 | 10 | connect_proc_rst converters adc_rst_i 11 | connect_to_fpga_pins converters phys_interface phys_interface_0 12 | 13 | connect_intf converters clk_o ps7 S_AXI_HP0_ACLK 14 | 15 | #dataReal 16 | add_ip_and_conf dataReal_dma_direct dataReal { 17 | NB_INPUT 2 \ 18 | NB_SAMPLE 500000 \ 19 | SIGNED_FORMAT true \ 20 | DATA_SIZE 14 \ 21 | USE_SOF false \ 22 | STOP_ON_EOF false } 23 | 24 | connect_intf converters dataA_out dataReal data1_in 25 | connect_intf converters dataB_out dataReal data2_in 26 | connect_intf converters clk_o dataReal m00_axis_aclk 27 | connect_proc dataReal s00_axi 0x1000 28 | 29 | # axi dma 30 | add_ip_and_conf axi_dma axi_dma_x { 31 | c_include_sg false \ 32 | c_sg_length_width 24 \ 33 | c_include_mm2s false \ 34 | c_s2mm_burst_size 32} 35 | 36 | connect_intf dataReal m00_axis axi_dma_x s_axis_s2mm 37 | connect_intf axi_dma_x s2mm_introut ps7 irq_f2p 38 | 39 | apply_bd_automation -rule xilinx.com:bd_rule:axi4 \ 40 | -config {Master "/ps7/M_AXI_GP0" Clk "Auto" } \ 41 | [get_bd_intf_pins axi_dma_x/s_axi_lite] 42 | apply_bd_automation -rule xilinx.com:bd_rule:axi4 \ 43 | -config {Master "/axi_dma_x/M_AXI_S2MM" Clk "Auto"} \ 44 | [get_bd_intf_pins ps7/s_axi_hp0] 45 | 46 | connect_bd_net [get_bd_pins rst_converters_125M/peripheral_reset] [get_bd_pins dataReal/m00_axis_reset] 47 | save_bd_design 48 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/7_ADC_DMA/syllabus_ADC.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/redpitaya/7_ADC_DMA/syllabus_ADC.pdf -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/8_PRN_portable.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/redpitaya/8_PRN_portable/8_PRN_portable.pdf -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/Makefile: -------------------------------------------------------------------------------- 1 | all: 8_PRN_portable.pdf 2 | 3 | 8_PRN_portable.pdf: 8_PRN_portable.tex 4 | pdflatex $^ 5 | pdflatex $^ 6 | 7 | clean: 8 | rm *.log *.aux 8_PRN_portable.pdf *.out 9 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/app/Makefile: -------------------------------------------------------------------------------- 1 | BASE_NAME=prn_fir 2 | include $(OSCIMP_DIGITAL_APP)/Makefile.inc 3 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/app/coefs.txt: -------------------------------------------------------------------------------- 1 | 128 2 | 0 3 | 0 4 | 0 5 | 0 6 | 0 7 | 0 8 | 0 9 | 0 10 | 0 11 | 0 12 | 0 13 | 0 14 | 0 15 | 0 16 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/app/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include "fir_conf.h" // library for communicating with the FIR 9 | 10 | 11 | int main() 12 | {int k; 13 | char c[16384]; 14 | int fi,fo; 15 | fi=open("/dev/data00",O_RDWR); 16 | fo=open("/tmp/data.bin",O_WRONLY|O_CREAT,S_IRWXU); 17 | fir_send_conf("/dev/fir00", "coefs.txt", 32); 18 | 19 | for (k=1;k<5;k++) 20 | {read(fi,c,16384); 21 | write(fo,c,16384); 22 | } 23 | close(fi); 24 | close(fo); 25 | return EXIT_SUCCESS; 26 | } 27 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/app/prn_fir.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /plugin/; 3 | 4 | / { 5 | compatible = "xlnx,zynq-7000"; 6 | 7 | fragment0 { 8 | target = <&fpga_full>; 9 | #address-cells = <1>; 10 | #size-cells = <1>; 11 | __overlay__ { 12 | #address-cells = <1>; 13 | #size-cells = <1>; 14 | 15 | firmware-name = "prn_fir_wrapper.bit.bin"; 16 | 17 | data00: data00@43C20000{ 18 | compatible = "ggm,dataToRam"; 19 | reg = <0x43C20000 0xffff>; 20 | }; 21 | 22 | fir00: fir00@43C10000{ 23 | compatible = "ggm,fir"; 24 | reg = <0x43C10000 0xffff>; 25 | }; 26 | 27 | }; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/app/prn_fir_us.sh: -------------------------------------------------------------------------------- 1 | CORE_MODULES_DIR=../../modules 2 | 3 | mkdir -p /lib/firmware 4 | cp ../bitstreams/prn_fir_wrapper.bit.bin /lib/firmware 5 | DTB_DIR=/sys/kernel/config/device-tree/overlays/fpga 6 | rmdir $DTB_DIR 7 | mkdir $DTB_DIR 8 | cat prn_fir.dtbo > $DTB_DIR/dtbo 9 | 10 | insmod ${CORE_MODULES_DIR}/data_to_ram_core.ko 11 | insmod ${CORE_MODULES_DIR}/fir_core.ko 12 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/design/Makefile: -------------------------------------------------------------------------------- 1 | NAME=prn_fir 2 | BASE_TCL = ${NAME}.tcl 3 | 4 | include ${OSCIMP_DIGITAL_IP}/xilinx.mk 5 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/design/addr.tcl: -------------------------------------------------------------------------------- 1 | # vivado -mode batch -source addr.tcl | grep -A1 \ SEG 2 | open_project tmp/prn_fir.xpr 3 | open_bd_design tmp/prn_fir.srcs/sources_1/bd/prn_fir/prn_fir.bd 4 | set liste [get_bd_addr_segs] 5 | puts stdout $liste 6 | set max [llength $liste] 7 | puts stdout $max 8 | for {set i 0} {$i < $max} {incr i} { 9 | report_property -all [lindex [get_bd_addr_segs ] $i ] 10 | } 11 | 12 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/design/prn_fir_usage_ressources.txt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | ----------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2018.2.1 (lin64) Build 2288692 Thu Jul 26 18:23:50 MDT 2018 4 | | Date : Mon Jan 28 16:31:50 2019 5 | | Host : x230 running 64-bit Gentoo Base System release 2.6 6 | | Command : report_utilization -hierarchical -hierarchical_depth 1 -file prn_fir_usage_ressources.txt 7 | | Design : prn_fir_wrapper 8 | | Device : 7z010clg400-1 9 | | Design State : Routed 10 | ----------------------------------------------------------------------------------------------------------- 11 | 12 | Utilization Design Information 13 | 14 | Table of Contents 15 | ----------------- 16 | 1. Utilization by Hierarchy 17 | 18 | 1. Utilization by Hierarchy 19 | --------------------------- 20 | 21 | +-----------------+---------+------------+------------+---------+------+------+--------+--------+--------------+ 22 | | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks | 23 | +-----------------+---------+------------+------------+---------+------+------+--------+--------+--------------+ 24 | | prn_fir_wrapper | (top) | 763 | 701 | 0 | 62 | 1372 | 8 | 1 | 15 | 25 | | prn_fir_i | prn_fir | 763 | 701 | 0 | 62 | 1372 | 8 | 1 | 15 | 26 | +-----------------+---------+------------+------------+---------+------+------+--------+--------+--------------+ 27 | * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining 28 | 29 | 30 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/figures/address.png: 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Produced by xfig version 3.2.7a 2 | Landscape 3 | Center 4 | Metric 5 | A4 6 | 100.00 7 | Single 8 | -2 9 | 1200 2 10 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 11 | 0 0 1.00 60.00 120.00 12 | 5490 4680 6120 4680 13 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 14 | 0 0 1.00 60.00 120.00 15 | 7695 4680 8325 4680 16 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 17 | 0 0 1.00 60.00 120.00 18 | 7875 4680 7875 4950 10080 4950 19 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 20 | 0 0 1.00 60.00 120.00 21 | 8820 4680 9180 4680 22 | 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 23 | 0 0 1.00 60.00 120.00 24 | 9855 4680 10080 4680 25 | 4 0 0 50 -1 0 12 0.0000 4 180 1545 6120 4725 dupplReal_1_to_2\001 26 | 4 0 0 50 -1 0 12 0.0000 4 135 690 4680 4770 PRN20b\001 27 | 4 0 0 50 -1 0 12 0.0000 4 195 375 4860 4455 $prn\001 28 | 4 0 0 50 -1 0 8 0.0000 4 90 150 7965 4635 20\001 29 | 4 0 0 50 -1 0 8 0.0000 4 90 150 7965 4905 20\001 30 | 4 0 0 50 -1 0 12 0.0000 4 195 1515 6075 4455 $splitter_raw_data\001 31 | 4 0 0 50 -1 0 12 0.0000 4 165 285 8415 4455 $fir\001 32 | 4 0 0 50 -1 0 8 0.0000 4 90 150 8865 4635 22\001 33 | 4 0 0 50 -1 0 12 0.0000 4 135 510 9270 4725 shifter\001 34 | 4 0 0 50 -1 0 12 0.0000 4 165 1545 10080 4860 dataReal_to_RAM\001 35 | 4 0 0 50 -1 0 12 0.0000 4 135 300 8415 4725 FIR\001 36 | 4 0 0 50 -1 0 8 0.0000 4 90 150 9810 4635 20\001 37 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/figures/schema.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/redpitaya/8_PRN_portable/figures/schema.pdf -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/figures/schema.png: -------------------------------------------------------------------------------- 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string false SEG_data64_1_voie_to_ram_1_reg0 5 | OFFSET string false 0x43C40000 6 | -- 7 | NAME string false SEG_fir_0_reg0 8 | OFFSET string false 0x43C10000 9 | -- 10 | NAME string false SEG_fir_1_reg0 11 | OFFSET string false 0x43C20000 12 | -- 13 | NAME string false SEG_prn20b_0_reg0 14 | OFFSET string false 0x43C00000 15 | -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/results/carac_fir1.eps.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/oscimp/oscimpDigital/b78965cee7eb6a6fb0c00da5f99b69f8bdff8b83/doc/tutorials/redpitaya/8_PRN_portable/results/carac_fir1.eps.gz -------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/results/carac_fir2.eps.gz: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /doc/tutorials/redpitaya/8_PRN_portable/results/go.m: -------------------------------------------------------------------------------- 1 | f=fopen('data15fois16.bin');d=fread(f,inf,'int32'); 2 | x=d(1:2:end); z=zeros(1,length(x)); 3 | z(1:15)=1; 4 | subplot(211) 5 | u=(abs(fft(d(1:2:end)))); plot(u/max(u),'b'); hold on 6 | u=(abs(fft(z-mean(z)))); plot(u/max(u),'r'); 7 | 8 | subplot(212) 9 | f=fopen('data4fois16.bin');d=fread(f,inf,'int32'); 10 | z=zeros(1,length(x)); 11 | z(1:3)=1; 12 | u=(abs(fft(d(1:2:end)))); plot(u/max(u),'b'); hold on 13 | u=(abs(fft(z-mean(z)))); plot(u/max(u),'r'); 14 | print -depsc cara_fir.eps 15 | 16 | figure 17 | f=fopen('data15fois16.bin');d=fread(f,inf,'int32'); 18 | subplot(211) 19 | x=d(2:2:end); plot(abs(fft(x)),'b'); hold on 20 | x=d(1:2:end); plot(abs(fft(x)),'r'); 21 | 22 | subplot(212) 23 | f=fopen('data4fois16.bin');d=fread(f,inf,'int32'); 24 | x=d(2:2:end); plot(abs(fft(x)),'b'); hold on 25 | x=d(1:2:end); plot(abs(fft(x)),'r'); 26 | print -depsc cara_fir2.eps 27 | -------------------------------------------------------------------------------- /settings.sh.sample: -------------------------------------------------------------------------------- 1 | # define the board being used. Must be adapted to either: 2 | # plutosdr for the Xilinx Zynq-based ADI PlutoSDR board 3 | # redpitaya for the Xilinx Zynq-based 14-bit legacy Red Pitaya board 4 | # redpitaya16 for the new Xilinx Zynq-based 16-bit Red Pitaya board 5 | # de0nansoc for the Altera/Intel Terrasic DE0Nano SoC 6 | export BOARD_NAME= 7 | 8 | #define Buildroot location 9 | export BR_DIR= 10 | 11 | # define target IP 12 | # 192.168.0.10 for RedPitaya 13 | # 192.168.2.1 for PlutoSDR 14 | export IP= 15 | 16 | #only mandatory for plutosdr 17 | #export ADI_HDL_DIR= 18 | 19 | # define where to install apps, drivers, etc 20 | export OSCIMP_DIGITAL_NFS=/nfs 21 | 22 | OSCIMP_DIGITAL=$(cd `dirname "${BASH_SOURCE[0]}"` && pwd) 23 | source $OSCIMP_DIGITAL/app/setenv.sh # defines $OSCIMP_DIGITAL_APP 24 | source $OSCIMP_DIGITAL/fpga_ip/setenv.sh # defines OSCIMP_DIGITAL_IP 25 | source $OSCIMP_DIGITAL/lib/setenv.sh # OSCIMP_DIGITAL_LIB 26 | source $OSCIMP_DIGITAL/linux_driver/setenv.sh 27 | 28 | export PATH=$PATH:$OSCIMP_DIGITAL_APP/tools/module_generator:$OSCIMP_DIGITAL_IP/tools/:$OSCIMP_DIGITAL_APP/tools/webserver_generator/ 29 | 30 | # /!\ locale settings for Vivado (uses '.' as separator, as opposed to the French ',') 31 | export LANG=en_US.UTF-8 32 | # /!\ check /etc/locale.gen: en_US.UTF-8 UTF-8 must be UNcommented. If it was commented: 33 | # remove comment and execute as root locale-gen 34 | --------------------------------------------------------------------------------