├── .gitignore ├── README.md ├── images ├── apple-32.png ├── bluenoise-128.png ├── bluenoise-256.png ├── bluenoise-32.png ├── bluenoise-64.png ├── breadboard.jpg ├── led-sign.jpg ├── macplus-doom.jpg ├── multiboot.bin ├── pcb-3d.png ├── pcb-v0.jpg └── pcb.png ├── pcb ├── README.md ├── wrangler_v0.kicad_pcb ├── wrangler_v0.kicad_prl ├── wrangler_v0.kicad_pro ├── wrangler_v0.kicad_sch └── wrangler_v0.pdf └── verilog ├── Makefile ├── Makefile.icestorm ├── apple-32.hex ├── bluenoise-32.hex ├── bluenoise-64.hex ├── clocks.py ├── dither.v ├── dpram.v ├── edid.hex ├── fb-init.hex ├── hdmi.v ├── hdmi_pll.v ├── hdmi_pll_ddr.v ├── i2c.v ├── mac.v ├── mem.v ├── pixelwrangler_v0.pcf ├── pwm.v ├── tmds.v ├── top.v ├── train.v ├── uart.v ├── upduino_v2.pcf └── util.v /.gitignore: -------------------------------------------------------------------------------- 1 | .*.d 2 | *.asc 3 | *.bin 4 | *.json 5 | .*.sw[po] 6 | _autosave* 7 | *.gbr 8 | *-backups 9 | *.gbrjob 10 | *auto_saved* 11 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Pixel Wrangler: HDMI to whatever 2 | 3 | ![Two assembled v0 pixel wrangler boards](images/pcb-v0.jpg) 4 | 5 | The Pixel Wrangler is a tool for converting HDMI video into anything else. 6 | It uses an ice40up5k FPGA to decode the video stream and stores a section 7 | of it in the block RAM, which can then be clocked out of the 16 GPIO pins 8 | in any other format required. 9 | 10 | Since the FPGA has total flexibility in how it drives the output pins 11 | it is easily adaptable to different protocols. Some examples that are possible: 12 | 13 | * Classic CRT like the original Mac or Hercules monitors 14 | * LED matrices 15 | * Flip dots 16 | * LED strips (ws2812 or other protocols) 17 | * Lots of servos for "wooden mirrors" 18 | 19 | ## Does it work? 20 | 21 | ![Mac Plus "running" Doom](images/macplus-doom.jpg) 22 | 23 | Mostly! The EDID output is good enough to convince Linux to use it as 24 | a normal, if low-resolution, display. The `mac.bin` monitor mode has 25 | "*live dithering*" to convert the color display into 1-bit, which 26 | works well enough to [play Doom on a 9" Mac Plus](https://www.youtube.com/watch?v=UI3e4YboR_g)! 27 | 28 | With `xrandr` it is possible to 29 | have it use a small section of the primary monitor if you don't want a 30 | separate head: 31 | 32 | ``` 33 | xrandr --output HDMI-2 --pos 350x100 34 | ``` 35 | 36 | ![LED sign from a train with the Raspberry Pi boot image](images/led-sign.jpg) 37 | 38 | There are some [problems with the v0 boards](https://github.com/osresearch/pixel-wrangler/issues/22), 39 | one of which reqiures a bodge wire on the i2c lines. The 5v pullups on 40 | the source side of the HDMI i2c also might cause problems in the FPGA, 41 | so the boards need some redesign. 42 | 43 | The [TMDS D1 and D2 channels aren't working](https://github.com/osresearch/pixel-wrangler/issues/23), 44 | so right now only the blue data on channel D0 is used. 45 | This might be a clock phase issue or it might be a larger problem; 46 | more research is needed. 47 | 48 | The USB Micro is directly connected to the ice40up5k and the flash 49 | can be loaded with [TinyFPGA bootloader `pixelwrangler` branch](https://github.com/osresearch/TinyFPGA-Bootloader/tree/pixelwrangler) 50 | to allow new bit streams to be uploaded into the device. 51 | The [`multiboot.bin`](image/multiboot.bin) is prebuilt and can 52 | be flashed with your SPI flasher of choice and then the `bootmeta.json` 53 | and `boardmeta.json` can be written into the flash security pages. 54 | 55 | ## PCB design 56 | 57 | ![Early PCB layout with air wires](images/pcb.png) 58 | 59 | [v0 Schematic](pcb/wrangler_v0.pdf) is based on the [UPduino v3.0 by tinyvision.ai](https://www.tindie.com/products/tinyvision_ai/upduino-v31-low-cost-lattice-ice40-fpga-board/), 60 | heavily modified for this specific application. 61 | 62 | The HDMI connector has one differential pair carrying a 25 MHz clock and three differential 63 | pairs running at 250 MHz and carrying 10 bits per pixel. The clock *must* connect 64 | to the one pin on the ice40up5k that has a LVDS connection to the global clock buffer 65 | so that the pixel clock can be quickly fanned-out to the rest of the logic that uses it. 66 | The three data pairs are routed to the LVDS inputs; D0 and D1 are inverted so that they 67 | don't have to cross on the PCB and must be flipped in the logic. 68 | 69 | ## Limitations 70 | 71 | ![Rendering of the pre-production beta board](images/pcb-3d.png) 72 | 73 | * Only "baseline video" is supported 74 | * 640x480 @ 60Hz 75 | * 25 MHz maximum pixel clock 76 | * 1 Mib frame buffer memory in the ice40. Resolutions supported are: 77 | * 1024x1024x1 78 | * 512x512x4 79 | * 256x256x16 80 | * 256x128x24 81 | * 3.3V IO on GPIO pins 82 | * No protection against shorts or overcurrent. Be careful! 83 | * Boot loader requires button press to reset 84 | * There isn't any USB support in the bit stream tree yet. 85 | 86 | ## Dithering 87 | 88 | ![256x256 Blue Noise matrix](images/bluenoise-256.png) 89 | 90 | Dithering uses Ordered Blue Noise Dithering. Pattern is from [gao-duan](https://github.com/gao-duan/BlueNoise) (MIT Licensed). 91 | Currently limited to a 64x64 size pattern; ideally a larger RGB 92 | image could be loaded from the SPI flash at boot time, which would 93 | allow three channel dithering without repeating across the screen. 94 | 95 | ## Todo 96 | 97 | * [X] Finish board design -- ordered! 98 | * [X] EDID ROM and i2c interface 99 | * [X] DDR on input for ~~high-res~~ inputs 100 | * [X] Classic Mac mode -- working! 101 | * [ ] Fix TMDS channel D1 and D2 decoding 102 | * [ ] Documentation on writing new interfaces 103 | * [ ] LED strip mode 104 | * [ ] Load larger dithering pattern from flash? 105 | -------------------------------------------------------------------------------- /images/apple-32.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/osresearch/pixel-wrangler/a07d15a38b729e29851268b734bbaf6e8d8f6daf/images/apple-32.png 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/pcb/wrangler_v0.kicad_prl: -------------------------------------------------------------------------------- 1 | { 2 | "board": { 3 | "active_layer": 37, 4 | "active_layer_preset": "", 5 | "auto_track_width": true, 6 | "hidden_netclasses": [], 7 | "hidden_nets": [], 8 | "high_contrast_mode": 0, 9 | "net_color_mode": 1, 10 | "opacity": { 11 | "images": 0.6, 12 | "pads": 1.0, 13 | "tracks": 1.0, 14 | "vias": 1.0, 15 | "zones": 0.6 16 | }, 17 | "selection_filter": { 18 | "dimensions": true, 19 | "footprints": true, 20 | "graphics": true, 21 | "keepouts": true, 22 | "lockedItems": true, 23 | "otherItems": true, 24 | "pads": true, 25 | "text": true, 26 | "tracks": true, 27 | "vias": true, 28 | "zones": true 29 | }, 30 | "visible_items": [ 31 | 0, 32 | 1, 33 | 2, 34 | 3, 35 | 4, 36 | 5, 37 | 6, 38 | 9, 39 | 10, 40 | 11, 41 | 12, 42 | 13, 43 | 14, 44 | 15, 45 | 16, 46 | 17, 47 | 18, 48 | 19, 49 | 20, 50 | 21, 51 | 22, 52 | 23, 53 | 24, 54 | 25, 55 | 26, 56 | 27, 57 | 28, 58 | 29, 59 | 30, 60 | 32, 61 | 33, 62 | 34, 63 | 35, 64 | 36, 65 | 39, 66 | 40 67 | ], 68 | "visible_layers": "ffcfe30_fffffff8", 69 | "zone_display_mode": 0 70 | }, 71 | "meta": { 72 | "filename": "wrangler_v0.kicad_prl", 73 | "version": 3 74 | }, 75 | "project": { 76 | "files": [] 77 | } 78 | } 79 | -------------------------------------------------------------------------------- /pcb/wrangler_v0.kicad_pro: -------------------------------------------------------------------------------- 1 | { 2 | "board": { 3 | "3dviewports": [], 4 | "design_settings": { 5 | "defaults": { 6 | "board_outline_line_width": 0.049999999999999996, 7 | "copper_line_width": 0.15, 8 | "copper_text_italic": false, 9 | "copper_text_size_h": 1.5, 10 | "copper_text_size_v": 1.5, 11 | "copper_text_thickness": 0.3, 12 | "copper_text_upright": false, 13 | "courtyard_line_width": 0.049999999999999996, 14 | "dimension_precision": 4, 15 | "dimension_units": 3, 16 | "dimensions": { 17 | "arrow_length": 1270000, 18 | "extension_offset": 500000, 19 | "keep_text_aligned": true, 20 | "suppress_zeroes": false, 21 | "text_position": 0, 22 | "units_format": 1 23 | }, 24 | "fab_line_width": 0.09999999999999999, 25 | "fab_text_italic": false, 26 | "fab_text_size_h": 1.0, 27 | "fab_text_size_v": 1.0, 28 | "fab_text_thickness": 0.15, 29 | "fab_text_upright": false, 30 | "other_line_width": 0.09999999999999999, 31 | "other_text_italic": false, 32 | "other_text_size_h": 1.0, 33 | "other_text_size_v": 1.0, 34 | "other_text_thickness": 0.15, 35 | "other_text_upright": false, 36 | "pads": { 37 | "drill": 0.0, 38 | "height": 6.2, 39 | "width": 6.2 40 | }, 41 | "silk_line_width": 0.12, 42 | "silk_text_italic": false, 43 | "silk_text_size_h": 0.7999999999999999, 44 | "silk_text_size_v": 0.7999999999999999, 45 | "silk_text_thickness": 0.15, 46 | "silk_text_upright": false, 47 | "zones": { 48 | "min_clearance": 0.254 49 | } 50 | }, 51 | "diff_pair_dimensions": [ 52 | { 53 | "gap": 0.0, 54 | "via_gap": 0.0, 55 | "width": 0.0 56 | } 57 | ], 58 | "drc_exclusions": [], 59 | "meta": { 60 | "filename": "board_design_settings.json", 61 | "version": 2 62 | }, 63 | "rule_severities": { 64 | "annular_width": "error", 65 | "clearance": "error", 66 | "connection_width": "warning", 67 | "copper_edge_clearance": "error", 68 | "copper_sliver": "warning", 69 | "courtyards_overlap": "error", 70 | "diff_pair_gap_out_of_range": "error", 71 | "diff_pair_uncoupled_length_too_long": "error", 72 | "drill_out_of_range": "error", 73 | "duplicate_footprints": "warning", 74 | "extra_footprint": "warning", 75 | "footprint": "error", 76 | "footprint_type_mismatch": "ignore", 77 | "hole_clearance": "error", 78 | "hole_near_hole": "error", 79 | "invalid_outline": "error", 80 | "isolated_copper": "warning", 81 | "item_on_disabled_layer": "error", 82 | "items_not_allowed": "error", 83 | "length_out_of_range": "error", 84 | "lib_footprint_issues": "warning", 85 | "lib_footprint_mismatch": "warning", 86 | "malformed_courtyard": "error", 87 | "microvia_drill_out_of_range": "error", 88 | "missing_courtyard": "ignore", 89 | "missing_footprint": "warning", 90 | "net_conflict": "warning", 91 | "npth_inside_courtyard": "ignore", 92 | "padstack": "warning", 93 | "pth_inside_courtyard": "ignore", 94 | "shorting_items": "error", 95 | "silk_edge_clearance": "warning", 96 | "silk_over_copper": "warning", 97 | "silk_overlap": "warning", 98 | "skew_out_of_range": "error", 99 | "solder_mask_bridge": "error", 100 | "starved_thermal": "error", 101 | "text_height": "warning", 102 | "text_thickness": "warning", 103 | "through_hole_pad_without_hole": "error", 104 | "too_many_vias": "error", 105 | "track_dangling": "warning", 106 | "track_width": "error", 107 | "tracks_crossing": "error", 108 | "unconnected_items": "error", 109 | "unresolved_variable": "error", 110 | "via_dangling": "warning", 111 | "zones_intersect": "error" 112 | }, 113 | "rule_severitieslegacy_courtyards_overlap": true, 114 | "rule_severitieslegacy_no_courtyard_defined": false, 115 | "rules": { 116 | "max_error": 0.005, 117 | "min_clearance": 0.0, 118 | "min_connection": 0.0, 119 | "min_copper_edge_clearance": 0.024999999999999998, 120 | "min_hole_clearance": 0.25, 121 | "min_hole_to_hole": 0.25, 122 | "min_microvia_diameter": 0.19999999999999998, 123 | "min_microvia_drill": 0.09999999999999999, 124 | "min_resolved_spokes": 2, 125 | "min_silk_clearance": 0.0, 126 | "min_text_height": 0.7999999999999999, 127 | "min_text_thickness": 0.08, 128 | "min_through_hole_diameter": 0.3, 129 | "min_track_width": 0.15, 130 | "min_via_annular_width": 0.09999999999999999, 131 | "min_via_diameter": 0.3, 132 | "solder_mask_to_copper_clearance": 0.0, 133 | "use_height_for_length_calcs": true 134 | }, 135 | "teardrop_options": [ 136 | { 137 | "td_allow_use_two_tracks": true, 138 | "td_curve_segcount": 5, 139 | "td_on_pad_in_zone": false, 140 | "td_onpadsmd": true, 141 | "td_onroundshapesonly": false, 142 | "td_ontrackend": false, 143 | "td_onviapad": true 144 | } 145 | ], 146 | "teardrop_parameters": [ 147 | { 148 | "td_curve_segcount": 0, 149 | "td_height_ratio": 1.0, 150 | "td_length_ratio": 0.5, 151 | "td_maxheight": 2.0, 152 | "td_maxlen": 1.0, 153 | "td_target_name": "td_round_shape", 154 | "td_width_to_size_filter_ratio": 0.9 155 | }, 156 | { 157 | "td_curve_segcount": 0, 158 | "td_height_ratio": 1.0, 159 | "td_length_ratio": 0.5, 160 | "td_maxheight": 2.0, 161 | "td_maxlen": 1.0, 162 | "td_target_name": "td_rect_shape", 163 | "td_width_to_size_filter_ratio": 0.9 164 | }, 165 | { 166 | "td_curve_segcount": 0, 167 | "td_height_ratio": 1.0, 168 | "td_length_ratio": 0.5, 169 | "td_maxheight": 2.0, 170 | "td_maxlen": 1.0, 171 | "td_target_name": "td_track_end", 172 | "td_width_to_size_filter_ratio": 0.9 173 | } 174 | ], 175 | "track_widths": [ 176 | 0.0, 177 | 0.1524, 178 | 0.2, 179 | 0.2032, 180 | 0.254, 181 | 0.3, 182 | 0.4, 183 | 0.5, 184 | 0.6, 185 | 0.8, 186 | 1.0 187 | ], 188 | "via_dimensions": [ 189 | { 190 | "diameter": 0.0, 191 | "drill": 0.0 192 | }, 193 | { 194 | "diameter": 0.6, 195 | "drill": 0.3 196 | } 197 | ], 198 | "zones_allow_external_fillets": false 199 | }, 200 | "layer_presets": [], 201 | "viewports": [] 202 | }, 203 | "boards": [], 204 | "cvpcb": { 205 | "equivalence_files": [] 206 | }, 207 | "erc": { 208 | "erc_exclusions": [], 209 | "meta": { 210 | "version": 0 211 | }, 212 | "pin_map": [ 213 | [ 214 | 0, 215 | 0, 216 | 0, 217 | 0, 218 | 0, 219 | 0, 220 | 1, 221 | 0, 222 | 0, 223 | 0, 224 | 0, 225 | 2 226 | ], 227 | [ 228 | 0, 229 | 2, 230 | 0, 231 | 1, 232 | 0, 233 | 0, 234 | 1, 235 | 0, 236 | 2, 237 | 2, 238 | 2, 239 | 2 240 | ], 241 | [ 242 | 0, 243 | 0, 244 | 0, 245 | 0, 246 | 0, 247 | 0, 248 | 1, 249 | 0, 250 | 1, 251 | 0, 252 | 1, 253 | 2 254 | ], 255 | [ 256 | 0, 257 | 1, 258 | 0, 259 | 0, 260 | 0, 261 | 0, 262 | 1, 263 | 1, 264 | 2, 265 | 1, 266 | 1, 267 | 2 268 | ], 269 | [ 270 | 0, 271 | 0, 272 | 0, 273 | 0, 274 | 0, 275 | 0, 276 | 1, 277 | 0, 278 | 0, 279 | 0, 280 | 0, 281 | 2 282 | ], 283 | [ 284 | 0, 285 | 0, 286 | 0, 287 | 0, 288 | 0, 289 | 0, 290 | 0, 291 | 0, 292 | 0, 293 | 0, 294 | 0, 295 | 2 296 | ], 297 | [ 298 | 1, 299 | 1, 300 | 1, 301 | 1, 302 | 1, 303 | 0, 304 | 1, 305 | 1, 306 | 1, 307 | 1, 308 | 1, 309 | 2 310 | ], 311 | [ 312 | 0, 313 | 0, 314 | 0, 315 | 1, 316 | 0, 317 | 0, 318 | 1, 319 | 0, 320 | 0, 321 | 0, 322 | 0, 323 | 2 324 | ], 325 | [ 326 | 0, 327 | 2, 328 | 1, 329 | 2, 330 | 0, 331 | 0, 332 | 1, 333 | 0, 334 | 2, 335 | 2, 336 | 2, 337 | 2 338 | ], 339 | [ 340 | 0, 341 | 2, 342 | 0, 343 | 1, 344 | 0, 345 | 0, 346 | 1, 347 | 0, 348 | 2, 349 | 0, 350 | 0, 351 | 2 352 | ], 353 | [ 354 | 0, 355 | 2, 356 | 1, 357 | 1, 358 | 0, 359 | 0, 360 | 1, 361 | 0, 362 | 2, 363 | 0, 364 | 0, 365 | 2 366 | ], 367 | [ 368 | 2, 369 | 2, 370 | 2, 371 | 2, 372 | 2, 373 | 2, 374 | 2, 375 | 2, 376 | 2, 377 | 2, 378 | 2, 379 | 2 380 | ] 381 | ], 382 | "rule_severities": { 383 | "bus_definition_conflict": "error", 384 | "bus_entry_needed": "error", 385 | "bus_to_bus_conflict": "error", 386 | "bus_to_net_conflict": "error", 387 | "conflicting_netclasses": "error", 388 | "different_unit_footprint": "error", 389 | "different_unit_net": "error", 390 | "duplicate_reference": "error", 391 | "duplicate_sheet_names": "error", 392 | "endpoint_off_grid": "warning", 393 | "extra_units": "error", 394 | "global_label_dangling": "warning", 395 | "hier_label_mismatch": "error", 396 | "label_dangling": "error", 397 | "lib_symbol_issues": "warning", 398 | "missing_bidi_pin": "warning", 399 | "missing_input_pin": "warning", 400 | "missing_power_pin": "error", 401 | "missing_unit": "warning", 402 | "multiple_net_names": "warning", 403 | "net_not_bus_member": "warning", 404 | "no_connect_connected": "warning", 405 | "no_connect_dangling": "warning", 406 | "pin_not_connected": "error", 407 | "pin_not_driven": "error", 408 | "pin_to_pin": "warning", 409 | "power_pin_not_driven": "error", 410 | "similar_labels": "warning", 411 | "simulation_model_issue": "error", 412 | "unannotated": "error", 413 | "unit_value_mismatch": "error", 414 | "unresolved_variable": "error", 415 | "wire_dangling": "error" 416 | } 417 | }, 418 | "libraries": { 419 | "pinned_footprint_libs": [], 420 | "pinned_symbol_libs": [] 421 | }, 422 | "meta": { 423 | "filename": "wrangler_v0.kicad_pro", 424 | "version": 1 425 | }, 426 | "net_settings": { 427 | "classes": [ 428 | { 429 | "bus_width": 12, 430 | "clearance": 0.1524, 431 | "diff_pair_gap": 0.25, 432 | "diff_pair_via_gap": 0.25, 433 | "diff_pair_width": 0.2, 434 | "line_style": 0, 435 | "microvia_diameter": 0.3, 436 | "microvia_drill": 0.1, 437 | "name": "Default", 438 | "pcb_color": "rgba(0, 0, 0, 0.000)", 439 | "schematic_color": "rgba(0, 0, 0, 0.000)", 440 | "track_width": 0.15, 441 | "via_diameter": 0.6, 442 | "via_drill": 0.3, 443 | "wire_width": 6 444 | }, 445 | { 446 | "bus_width": 12, 447 | "clearance": 0.1524, 448 | "diff_pair_gap": 0.25, 449 | "diff_pair_via_gap": 0.25, 450 | "diff_pair_width": 0.2, 451 | "line_style": 0, 452 | "microvia_diameter": 0.3, 453 | "microvia_drill": 0.1, 454 | "name": "Power", 455 | "pcb_color": "rgba(0, 0, 0, 0.000)", 456 | "schematic_color": "rgba(0, 0, 0, 0.000)", 457 | "track_width": 0.254, 458 | "via_diameter": 0.8, 459 | "via_drill": 0.4, 460 | "wire_width": 6 461 | } 462 | ], 463 | "meta": { 464 | "version": 3 465 | }, 466 | "net_colors": null, 467 | "netclass_assignments": null, 468 | "netclass_patterns": [ 469 | { 470 | "netclass": "Default", 471 | "pattern": "/CDONE" 472 | }, 473 | { 474 | "netclass": "Default", 475 | "pattern": "/CLK_12M_EXT" 476 | }, 477 | { 478 | "netclass": "Default", 479 | "pattern": "/CLK_12M_FT" 480 | }, 481 | { 482 | "netclass": "Default", 483 | "pattern": "/CRESET_N" 484 | }, 485 | { 486 | "netclass": "Default", 487 | "pattern": "/EE_CLK" 488 | }, 489 | { 490 | "netclass": "Default", 491 | "pattern": "/EE_CS" 492 | }, 493 | { 494 | "netclass": "Default", 495 | "pattern": "/EE_DAT" 496 | }, 497 | { 498 | "netclass": "Default", 499 | "pattern": "/FLASH_MISO" 500 | }, 501 | { 502 | "netclass": "Default", 503 | "pattern": "/FLASH_MOSI" 504 | }, 505 | { 506 | "netclass": "Default", 507 | "pattern": "/FPGA_SI" 508 | }, 509 | { 510 | "netclass": "Default", 511 | "pattern": "/FPGA_SO" 512 | }, 513 | { 514 | "netclass": "Default", 515 | "pattern": "/FT_SCK" 516 | }, 517 | { 518 | "netclass": "Default", 519 | "pattern": "/FT_SSn" 520 | }, 521 | { 522 | "netclass": "Default", 523 | "pattern": "/FT_VCORE" 524 | }, 525 | { 526 | "netclass": "Default", 527 | "pattern": "/IOB_0A" 528 | }, 529 | { 530 | "netclass": "Default", 531 | "pattern": "/IOB_13B" 532 | }, 533 | { 534 | "netclass": "Default", 535 | "pattern": "/IOB_16A" 536 | }, 537 | { 538 | "netclass": "Default", 539 | "pattern": "/IOB_18A" 540 | }, 541 | { 542 | "netclass": "Default", 543 | "pattern": "/IOB_20A" 544 | }, 545 | { 546 | "netclass": "Default", 547 | "pattern": "/IOB_22A" 548 | }, 549 | { 550 | "netclass": "Default", 551 | "pattern": "/IOB_23B" 552 | }, 553 | { 554 | "netclass": "Default", 555 | "pattern": "/IOB_24A" 556 | }, 557 | { 558 | "netclass": "Default", 559 | "pattern": "/IOB_25B_G3" 560 | }, 561 | { 562 | "netclass": "Default", 563 | "pattern": "/IOB_29B" 564 | }, 565 | { 566 | "netclass": "Default", 567 | "pattern": "/IOB_2A" 568 | }, 569 | { 570 | "netclass": "Default", 571 | "pattern": "/IOB_31B" 572 | }, 573 | { 574 | "netclass": "Default", 575 | "pattern": "/IOB_3B_G6" 576 | }, 577 | { 578 | "netclass": "Default", 579 | "pattern": "/IOB_4A" 580 | }, 581 | { 582 | "netclass": "Default", 583 | "pattern": "/IOB_5B" 584 | }, 585 | { 586 | "netclass": "Default", 587 | "pattern": "/IOB_6A" 588 | }, 589 | { 590 | "netclass": "Default", 591 | "pattern": "/IOB_8A" 592 | }, 593 | { 594 | "netclass": "Default", 595 | "pattern": "/IOB_9B" 596 | }, 597 | { 598 | "netclass": "Default", 599 | "pattern": "/IOT_36B" 600 | }, 601 | { 602 | "netclass": "Default", 603 | "pattern": "/IOT_37A" 604 | }, 605 | { 606 | "netclass": "Default", 607 | "pattern": "/IOT_38B" 608 | }, 609 | { 610 | "netclass": "Default", 611 | "pattern": "/IOT_39A" 612 | }, 613 | { 614 | "netclass": "Default", 615 | "pattern": "/IOT_41A" 616 | }, 617 | { 618 | "netclass": "Default", 619 | "pattern": "/IOT_42B" 620 | }, 621 | { 622 | "netclass": "Default", 623 | "pattern": "/IOT_43A" 624 | }, 625 | { 626 | "netclass": "Default", 627 | "pattern": "/IOT_44B" 628 | }, 629 | { 630 | "netclass": "Default", 631 | "pattern": "/IOT_45A_G1" 632 | }, 633 | { 634 | "netclass": "Default", 635 | "pattern": "/IOT_46B_G0" 636 | }, 637 | { 638 | "netclass": "Default", 639 | "pattern": "/IOT_48B" 640 | }, 641 | { 642 | "netclass": "Default", 643 | "pattern": "/IOT_49A" 644 | }, 645 | { 646 | "netclass": "Default", 647 | "pattern": "/IOT_50B" 648 | }, 649 | { 650 | "netclass": "Default", 651 | "pattern": "/IOT_51A" 652 | }, 653 | { 654 | "netclass": "Default", 655 | "pattern": "/LED_B" 656 | }, 657 | { 658 | "netclass": "Default", 659 | "pattern": "/LED_G" 660 | }, 661 | { 662 | "netclass": "Default", 663 | "pattern": "/LED_R" 664 | }, 665 | { 666 | "netclass": "Default", 667 | "pattern": "/USB_M" 668 | }, 669 | { 670 | "netclass": "Default", 671 | "pattern": "/USB_P" 672 | }, 673 | { 674 | "netclass": "Default", 675 | "pattern": "Net-(C22-Pad1)" 676 | }, 677 | { 678 | "netclass": "Default", 679 | "pattern": "Net-(C24-Pad1)" 680 | }, 681 | { 682 | "netclass": "Default", 683 | "pattern": "Net-(C35-Pad1)" 684 | }, 685 | { 686 | "netclass": "Default", 687 | "pattern": "Net-(C4-Pad1)" 688 | }, 689 | { 690 | "netclass": "Default", 691 | "pattern": "Net-(J1-Pad4)" 692 | }, 693 | { 694 | "netclass": "Default", 695 | "pattern": "Net-(R1-Pad2)" 696 | }, 697 | { 698 | "netclass": "Default", 699 | "pattern": "Net-(R10-Pad2)" 700 | }, 701 | { 702 | "netclass": "Default", 703 | "pattern": "Net-(R14-Pad1)" 704 | }, 705 | { 706 | "netclass": "Default", 707 | "pattern": "Net-(R15-Pad1)" 708 | }, 709 | { 710 | "netclass": "Default", 711 | "pattern": "Net-(R3-Pad1)" 712 | }, 713 | { 714 | "netclass": "Default", 715 | "pattern": "Net-(SJ16-Pad1)" 716 | }, 717 | { 718 | "netclass": "Default", 719 | "pattern": "Net-(SJ35-Pad1)" 720 | }, 721 | { 722 | "netclass": "Default", 723 | "pattern": "Net-(SJ36-Pad1)" 724 | }, 725 | { 726 | "netclass": "Default", 727 | "pattern": "Net-(TP1-Pad1)" 728 | }, 729 | { 730 | "netclass": "Default", 731 | "pattern": "Net-(TP10-Pad1)" 732 | }, 733 | { 734 | "netclass": "Default", 735 | "pattern": "Net-(TP11-Pad1)" 736 | }, 737 | { 738 | "netclass": "Default", 739 | "pattern": "Net-(TP12-Pad1)" 740 | }, 741 | { 742 | "netclass": "Default", 743 | "pattern": "Net-(TP2-Pad1)" 744 | }, 745 | { 746 | "netclass": "Default", 747 | "pattern": "Net-(TP3-Pad1)" 748 | }, 749 | { 750 | "netclass": "Default", 751 | "pattern": "Net-(TP4-Pad1)" 752 | }, 753 | { 754 | "netclass": "Default", 755 | "pattern": "Net-(TP5-Pad1)" 756 | }, 757 | { 758 | "netclass": "Default", 759 | "pattern": "Net-(TP6-Pad1)" 760 | }, 761 | { 762 | "netclass": "Default", 763 | "pattern": "Net-(TP7-Pad1)" 764 | }, 765 | { 766 | "netclass": "Default", 767 | "pattern": "Net-(TP8-Pad1)" 768 | }, 769 | { 770 | "netclass": "Default", 771 | "pattern": "Net-(TP9-Pad1)" 772 | }, 773 | { 774 | "netclass": "Default", 775 | "pattern": "Net-(U3-Pad2)" 776 | }, 777 | { 778 | "netclass": "Default", 779 | "pattern": "Net-(U3-Pad39)" 780 | }, 781 | { 782 | "netclass": "Default", 783 | "pattern": "Net-(U6-Pad4)" 784 | }, 785 | { 786 | "netclass": "Default", 787 | "pattern": "Net-(U7-Pad4)" 788 | }, 789 | { 790 | "netclass": "Power", 791 | "pattern": "+1V2" 792 | }, 793 | { 794 | "netclass": "Power", 795 | "pattern": "+2V5" 796 | }, 797 | { 798 | "netclass": "Power", 799 | "pattern": "+3V3" 800 | }, 801 | { 802 | "netclass": "Power", 803 | "pattern": "+5VD" 804 | }, 805 | { 806 | "netclass": "Power", 807 | "pattern": "/+1.2V_CORE" 808 | }, 809 | { 810 | "netclass": "Power", 811 | "pattern": "/VCC_PLL" 812 | }, 813 | { 814 | "netclass": "Power", 815 | "pattern": "/VIO_BANK_0_2" 816 | }, 817 | { 818 | "netclass": "Power", 819 | "pattern": "/V_PHY" 820 | }, 821 | { 822 | "netclass": "Power", 823 | "pattern": "/V_PLL" 824 | }, 825 | { 826 | "netclass": "Power", 827 | "pattern": "/V_USB" 828 | }, 829 | { 830 | "netclass": "Power", 831 | "pattern": "GND" 832 | } 833 | ] 834 | }, 835 | "pcbnew": { 836 | "last_paths": { 837 | "gencad": "", 838 | "idf": "", 839 | "netlist": "wrangler_v0.net", 840 | "specctra_dsn": "", 841 | "step": "", 842 | "vrml": "" 843 | }, 844 | "page_layout_descr_file": "" 845 | }, 846 | "schematic": { 847 | "annotate_start_num": 0, 848 | "drawing": { 849 | "dashed_lines_dash_length_ratio": 12.0, 850 | "dashed_lines_gap_length_ratio": 3.0, 851 | "default_line_thickness": 6.0, 852 | "default_text_size": 50.0, 853 | "field_names": [], 854 | "intersheets_ref_own_page": false, 855 | "intersheets_ref_prefix": "", 856 | "intersheets_ref_short": false, 857 | "intersheets_ref_show": false, 858 | "intersheets_ref_suffix": "", 859 | "junction_size_choice": 3, 860 | "label_size_ratio": 0.25, 861 | "pin_symbol_size": 0.0, 862 | "text_offset_ratio": 0.08 863 | }, 864 | "legacy_lib_dir": "", 865 | "legacy_lib_list": [], 866 | "meta": { 867 | "version": 1 868 | }, 869 | "net_format_name": "", 870 | "page_layout_descr_file": "", 871 | "plot_directory": "./", 872 | "spice_adjust_passive_values": false, 873 | "spice_current_sheet_as_root": false, 874 | "spice_external_command": "spice \"%I\"", 875 | "spice_model_current_sheet_as_root": true, 876 | "spice_save_all_currents": false, 877 | "spice_save_all_voltages": false, 878 | "subpart_first_id": 65, 879 | "subpart_id_separator": 0 880 | }, 881 | "sheets": [ 882 | [ 883 | "5ef2e1d8-db1b-4f05-b1e6-93d7ceabe469", 884 | "" 885 | ] 886 | ], 887 | "text_variables": {} 888 | } 889 | -------------------------------------------------------------------------------- /pcb/wrangler_v0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/osresearch/pixel-wrangler/a07d15a38b729e29851268b734bbaf6e8d8f6daf/pcb/wrangler_v0.pdf -------------------------------------------------------------------------------- /verilog/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: mac.bin 3 | include Makefile.icestorm 4 | 5 | mac.json: bluenoise-32.hex bluenoise-64.hex bluenoise-128.hex bluenoise-256.hex 6 | 7 | %.hex: ../images/%.png 8 | convert $< gray:- \ 9 | | xxd -g1 -c1 \ 10 | | cut -d" " -f2 \ 11 | > $@ 12 | 13 | 14 | prog-%: %.bin 15 | tinyprog -p $< 16 | 17 | prog-meta: boardmeta.json 18 | tinyprog -a 1 --security $< 19 | 20 | # create a board meta file 21 | HARDWARE_VERSION ?= v0 22 | UUID ?= $(shell uuidgen) 23 | BOARD_NAME ?= Pixel Wrangler 24 | FPGA_NAME ?= $(DEVICE)-$(FOOTPRINT) 25 | 26 | boardmeta.json: FORCE 27 | echo > $@ \ 28 | '{"boardmeta":{'\ 29 | '"name":"$(BOARD_NAME)",'\ 30 | '"fpga":"$(FPGA_NAME)",'\ 31 | '"hver":"$(HARDWARE_VERSION)",'\ 32 | '"uuid":"$(UUID)"'\ 33 | '}}' 34 | 35 | -------------------------------------------------------------------------------- /verilog/Makefile.icestorm: -------------------------------------------------------------------------------- 1 | DEVICE-pixelwrangler ?= up5k 2 | FOOTPRINT-pixelwrangler ?= sg48 3 | PIN_SRC-pixelwrangler ?= pixelwrangler_v0.pcf 4 | 5 | USB_DEV ?= 1-1:1.0 6 | BOARD ?= pixelwrangler 7 | DEVICE := $(DEVICE-$(BOARD)) 8 | FOOTPRINT := $(FOOTPRINT-$(BOARD)) 9 | PIN_SRC := $(PIN_SRC-$(BOARD)) 10 | 11 | 12 | PNR ?= $(ICEPATH)nextpnr-ice40 -f 13 | .SECONDARY: 14 | 15 | # this works for the upduino; the pixelwrangler board uses tinyprog 16 | %.flash: %.bin 17 | $(ICEPATH)iceprog -e 128 # Force a reset 18 | $(ICEPATH)iceprog $< 19 | echo $(USB_DEV) | tee /sys/bus/usb/drivers/ftdi_sio/bind 20 | 21 | %.bin: %.asc 22 | $(ICEPATH)icepack $< $@ 23 | 24 | %.json: %.v 25 | $(ICEPATH)yosys \ 26 | -q \ 27 | -p 'read_verilog $<' \ 28 | -p 'synth_ice40 -top top -json $@' \ 29 | -E .$(basename $@).d \ 30 | 31 | %.asc: $(PIN_SRC) %.json 32 | $(PNR) \ 33 | --timing-allow-fail \ 34 | --$(DEVICE) \ 35 | --package $(FOOTPRINT) \ 36 | --asc $@ \ 37 | --pcf $(PIN_SRC) \ 38 | --json $(basename $@).json \ 39 | --pre-pack clocks.py \ 40 | 41 | %.gui: %.json 42 | $(PNR) --gui --$(DEVICE) --pcf $(PIN_SRC) --json $< 43 | 44 | # Generate a desired MHz pll 45 | pll_%.v: 46 | $(ICEPATH)icepll \ 47 | -i 48 \ 48 | -o $(subst pll_,,$(basename $@)) \ 49 | -m \ 50 | -n $(basename $@) \ 51 | -f $@ 52 | 53 | 54 | define make-test = 55 | $1: $1.vvp 56 | vvp $$< 57 | endef 58 | 59 | test: $(TEST-y) 60 | $(foreach t,$(TEST-y),$(eval $(call make-test,$t))) 61 | %.vvp: 62 | iverilog -o $@ -s $(basename $@) $^ 63 | 64 | clean: 65 | $(RM) *.blif *.asc *.bin *.json .*.d 66 | 67 | .PHONY: all prog clean FORCE 68 | FORCE: 69 | 70 | -include .*.d 71 | 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2026 | a8 2027 | b7 2028 | 91 2029 | ca 2030 | 34 2031 | 75 2032 | 85 2033 | 7f 2034 | 9f 2035 | 47 2036 | dc 2037 | 25 2038 | 34 2039 | 90 2040 | 45 2041 | 67 2042 | c4 2043 | 76 2044 | 98 2045 | 4f 2046 | 45 2047 | b2 2048 | 0e 2049 | 9f 2050 | 8d 2051 | b2 2052 | 90 2053 | 39 2054 | f2 2055 | 64 2056 | 44 2057 | 63 2058 | 96 2059 | d2 2060 | c6 2061 | a6 2062 | c5 2063 | a2 2064 | 72 2065 | ab 2066 | bd 2067 | 22 2068 | a3 2069 | e6 2070 | a9 2071 | 73 2072 | 1e 2073 | d4 2074 | 7f 2075 | 99 2076 | c6 2077 | 3b 2078 | 8a 2079 | 24 2080 | 87 2081 | 77 2082 | 28 2083 | ce 2084 | 8d 2085 | 5a 2086 | 32 2087 | 87 2088 | 52 2089 | a1 2090 | 2e 2091 | 68 2092 | 68 2093 | 53 2094 | ad 2095 | 9a 2096 | ac 2097 | 56 2098 | 22 2099 | 79 2100 | 71 2101 | a1 2102 | d7 2103 | 7e 2104 | 69 2105 | a7 2106 | 1a 2107 | ce 2108 | 42 2109 | a3 2110 | 91 2111 | e8 2112 | 4d 2113 | bb 2114 | 3d 2115 | 3d 2116 | cc 2117 | 0d 2118 | 5d 2119 | cb 2120 | a2 2121 | 86 2122 | 5d 2123 | 42 2124 | 71 2125 | 5f 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2326 | 6f 2327 | 57 2328 | e0 2329 | 59 2330 | 42 2331 | 3f 2332 | 7c 2333 | 2b 2334 | b6 2335 | a8 2336 | 37 2337 | 99 2338 | cf 2339 | 7d 2340 | 25 2341 | 4c 2342 | 92 2343 | 61 2344 | de 2345 | a8 2346 | 6c 2347 | 40 2348 | 31 2349 | 31 2350 | b3 2351 | d1 2352 | a5 2353 | 3b 2354 | da 2355 | 73 2356 | 22 2357 | 8f 2358 | ce 2359 | 47 2360 | 91 2361 | a0 2362 | 70 2363 | 59 2364 | 29 2365 | c2 2366 | 92 2367 | 70 2368 | 14 2369 | 58 2370 | a3 2371 | 64 2372 | 36 2373 | a9 2374 | 57 2375 | 9d 2376 | 6b 2377 | 28 2378 | 7c 2379 | 5a 2380 | 5d 2381 | c7 2382 | 73 2383 | 2e 2384 | 5c 2385 | 58 2386 | d9 2387 | 9e 2388 | 47 2389 | b3 2390 | 39 2391 | 27 2392 | d7 2393 | 8c 2394 | b7 2395 | e5 2396 | b2 2397 | 9c 2398 | 3b 2399 | e0 2400 | 8a 2401 | a8 2402 | 1c 2403 | bb 2404 | 9b 2405 | dd 2406 | b3 2407 | 22 2408 | 55 2409 | 91 2410 | 59 2411 | 96 2412 | da 2413 | d0 2414 | 33 2415 | 70 2416 | 9e 2417 | 9a 2418 | 6a 2419 | 55 2420 | d7 2421 | 60 2422 | a0 2423 | 76 2424 | 69 2425 | c9 2426 | 25 2427 | 9d 2428 | ac 2429 | 84 2430 | 43 2431 | 95 2432 | ed 2433 | 58 2434 | 3a 2435 | bb 2436 | c7 2437 | 6a 2438 | 3f 2439 | eb 2440 | 82 2441 | aa 2442 | ea 2443 | 6e 2444 | 38 2445 | b6 2446 | 82 2447 | 96 2448 | 67 2449 | cd 2450 | 4f 2451 | 83 2452 | 8f 2453 | 5a 2454 | f0 2455 | 6c 2456 | a3 2457 | 5a 2458 | 34 2459 | 35 2460 | 8f 2461 | 58 2462 | 5b 2463 | 83 2464 | ad 2465 | 73 2466 | 49 2467 | 73 2468 | b3 2469 | 31 2470 | 7a 2471 | a8 2472 | 43 2473 | 57 2474 | c0 2475 | 86 2476 | 85 2477 | 78 2478 | 75 2479 | 37 2480 | cf 2481 | 17 2482 | 35 2483 | b8 2484 | c3 2485 | 1a 2486 | 4b 2487 | eb 2488 | 2e 2489 | 7f 2490 | bc 2491 | 83 2492 | c9 2493 | 57 2494 | 96 2495 | 2a 2496 | b8 2497 | 5c 2498 | 71 2499 | 92 2500 | 5e 2501 | 80 2502 | c4 2503 | 4e 2504 | ac 2505 | 22 2506 | 46 2507 | b0 2508 | bf 2509 | 61 2510 | 55 2511 | e6 2512 | 50 2513 | 87 2514 | 9c 2515 | 45 2516 | c7 2517 | 3c 2518 | 84 2519 | 9b 2520 | 1f 2521 | d1 2522 | 92 2523 | 9b 2524 | b4 2525 | 5b 2526 | b5 2527 | 3c 2528 | 7f 2529 | 2e 2530 | c0 2531 | 8f 2532 | 62 2533 | 3f 2534 | e0 2535 | a5 2536 | a3 2537 | c6 2538 | 8c 2539 | 27 2540 | 65 2541 | 9e 2542 | ba 2543 | 6b 2544 | 8a 2545 | c2 2546 | 84 2547 | 96 2548 | 44 2549 | 7d 2550 | 65 2551 | ae 2552 | 95 2553 | 24 2554 | 55 2555 | 76 2556 | 46 2557 | 66 2558 | bc 2559 | 8c 2560 | 97 2561 | 88 2562 | e7 2563 | 34 2564 | 6a 2565 | c8 2566 | 41 2567 | 1e 2568 | 66 2569 | a3 2570 | 72 2571 | bd 2572 | 3c 2573 | 6e 2574 | 92 2575 | 1b 2576 | a5 2577 | 74 2578 | 7b 2579 | 3c 2580 | af 2581 | 9c 2582 | 3b 2583 | 80 2584 | a7 2585 | 71 2586 | 72 2587 | 1b 2588 | b7 2589 | 77 2590 | db 2591 | 4c 2592 | 92 2593 | a7 2594 | 91 2595 | d2 2596 | 31 2597 | 77 2598 | 67 2599 | 32 2600 | 8b 2601 | 52 2602 | 57 2603 | d6 2604 | 21 2605 | 83 2606 | 4d 2607 | 9e 2608 | 3c 2609 | bc 2610 | 88 2611 | b0 2612 | 45 2613 | e7 2614 | 61 2615 | 60 2616 | b6 2617 | bc 2618 | 80 2619 | 90 2620 | ba 2621 | 89 2622 | 77 2623 | 72 2624 | 49 2625 | bd 2626 | 7b 2627 | 9f 2628 | 21 2629 | 61 2630 | e7 2631 | b1 2632 | 81 2633 | b3 2634 | 89 2635 | 73 2636 | 17 2637 | a1 2638 | b6 2639 | d4 2640 | 42 2641 | c2 2642 | 46 2643 | f2 2644 | 8a 2645 | 5b 2646 | 9b 2647 | 61 2648 | 5c 2649 | d1 2650 | 4f 2651 | a5 2652 | 58 2653 | 54 2654 | 39 2655 | 7f 2656 | ac 2657 | 47 2658 | 81 2659 | 3e 2660 | b6 2661 | de 2662 | 91 2663 | 69 2664 | a1 2665 | 46 2666 | a4 2667 | 8e 2668 | 62 2669 | cf 2670 | db 2671 | 0e 2672 | 90 2673 | 76 2674 | 52 2675 | 4c 2676 | 66 2677 | bf 2678 | 89 2679 | 92 2680 | 19 2681 | da 2682 | 76 2683 | 49 2684 | 78 2685 | 49 2686 | 86 2687 | d4 2688 | 4e 2689 | 32 2690 | 5c 2691 | d0 2692 | cb 2693 | 6a 2694 | 76 2695 | 8a 2696 | 7a 2697 | 4e 2698 | a8 2699 | c4 2700 | 91 2701 | b9 2702 | 6a 2703 | 25 2704 | a2 2705 | 1f 2706 | a7 2707 | 76 2708 | 39 2709 | 5f 2710 | c9 2711 | c5 2712 | 51 2713 | a1 2714 | a0 2715 | a9 2716 | 8d 2717 | a6 2718 | d3 2719 | 97 2720 | 6c 2721 | ba 2722 | 84 2723 | 3d 2724 | 5f 2725 | 57 2726 | 9e 2727 | 46 2728 | bb 2729 | 8b 2730 | a0 2731 | de 2732 | 65 2733 | 40 2734 | 71 2735 | b3 2736 | 96 2737 | bf 2738 | 25 2739 | b3 2740 | c5 2741 | 23 2742 | ca 2743 | 28 2744 | 93 2745 | 4e 2746 | 48 2747 | c1 2748 | b7 2749 | 56 2750 | 2e 2751 | c0 2752 | 69 2753 | af 2754 | 33 2755 | 8a 2756 | 30 2757 | cf 2758 | 47 2759 | 55 2760 | 9b 2761 | 1b 2762 | 72 2763 | 53 2764 | 1a 2765 | ae 2766 | 4c 2767 | 83 2768 | d0 2769 | 88 2770 | 7b 2771 | 9c 2772 | 38 2773 | a7 2774 | 89 2775 | 14 2776 | ae 2777 | 1b 2778 | 7e 2779 | 2a 2780 | a7 2781 | 4d 2782 | 58 2783 | 87 2784 | 27 2785 | 99 2786 | 32 2787 | d9 2788 | a9 2789 | 5b 2790 | c2 2791 | 87 2792 | 3c 2793 | a9 2794 | 09 2795 | 31 2796 | 66 2797 | e8 2798 | 39 2799 | 6a 2800 | 7d 2801 | 50 2802 | ca 2803 | 59 2804 | 9d 2805 | 88 2806 | 5e 2807 | 53 2808 | b6 2809 | b7 2810 | 8d 2811 | 92 2812 | 71 2813 | a7 2814 | ba 2815 | 2a 2816 | b3 2817 | ca 2818 | 87 2819 | 30 2820 | b8 2821 | 7b 2822 | 79 2823 | 9a 2824 | 71 2825 | e3 2826 | 9b 2827 | bb 2828 | 9d 2829 | 56 2830 | e4 2831 | 3c 2832 | 87 2833 | 6c 2834 | 3d 2835 | e8 2836 | 75 2837 | c0 2838 | b9 2839 | 50 2840 | 69 2841 | a8 2842 | eb 2843 | 54 2844 | 82 2845 | 76 2846 | 4a 2847 | c6 2848 | 71 2849 | b8 2850 | a0 2851 | 88 2852 | b9 2853 | 36 2854 | 2e 2855 | b9 2856 | 44 2857 | ac 2858 | e1 2859 | 62 2860 | 8f 2861 | 99 2862 | 68 2863 | 4d 2864 | cf 2865 | 65 2866 | b5 2867 | 41 2868 | 6c 2869 | 43 2870 | c6 2871 | 84 2872 | c6 2873 | 3f 2874 | 81 2875 | 4c 2876 | 3d 2877 | 72 2878 | a5 2879 | 76 2880 | 92 2881 | 1f 2882 | cb 2883 | 55 2884 | da 2885 | 48 2886 | 53 2887 | db 2888 | 50 2889 | 75 2890 | 7d 2891 | 6b 2892 | 3c 2893 | ae 2894 | 98 2895 | 3b 2896 | d8 2897 | 96 2898 | b6 2899 | 63 2900 | 60 2901 | 35 2902 | 58 2903 | 8d 2904 | c0 2905 | 66 2906 | a3 2907 | 31 2908 | cf 2909 | a5 2910 | b9 2911 | 7b 2912 | 23 2913 | 8b 2914 | 59 2915 | 58 2916 | 6d 2917 | 77 2918 | a6 2919 | a5 2920 | 85 2921 | 87 2922 | 4d 2923 | 74 2924 | b5 2925 | 40 2926 | c2 2927 | ce 2928 | 28 2929 | 82 2930 | 48 2931 | a9 2932 | 7a 2933 | b8 2934 | a1 2935 | 89 2936 | 47 2937 | 12 2938 | d4 2939 | 9c 2940 | e7 2941 | 6b 2942 | 3b 2943 | c0 2944 | 52 2945 | a8 2946 | 90 2947 | 89 2948 | 42 2949 | c9 2950 | 53 2951 | b3 2952 | 43 2953 | 4e 2954 | 93 2955 | 3e 2956 | c2 2957 | 9c 2958 | 3b 2959 | 69 2960 | 37 2961 | 69 2962 | 53 2963 | 29 2964 | b2 2965 | 64 2966 | 75 2967 | d3 2968 | 14 2969 | b0 2970 | 70 2971 | 8e 2972 | 1e 2973 | 77 2974 | 91 2975 | 4a 2976 | d7 2977 | b7 2978 | 0e 2979 | e1 2980 | 1d 2981 | ef 2982 | 34 2983 | a0 2984 | 40 2985 | b9 2986 | 85 2987 | 87 2988 | 94 2989 | 7e 2990 | 50 2991 | 9e 2992 | 76 2993 | 63 2994 | e1 2995 | 95 2996 | 72 2997 | 47 2998 | 6f 2999 | 65 3000 | 7c 3001 | c7 3002 | 65 3003 | 5d 3004 | 63 3005 | bf 3006 | 48 3007 | 87 3008 | 4b 3009 | 66 3010 | 23 3011 | d6 3012 | 93 3013 | 26 3014 | 9e 3015 | a9 3016 | 6a 3017 | c0 3018 | b9 3019 | 81 3020 | a0 3021 | 32 3022 | a3 3023 | f0 3024 | b7 3025 | 6a 3026 | a6 3027 | be 3028 | d6 3029 | 72 3030 | e1 3031 | 85 3032 | 50 3033 | 53 3034 | 62 3035 | a8 3036 | d6 3037 | 6f 3038 | 38 3039 | 93 3040 | 93 3041 | 82 3042 | a3 3043 | 98 3044 | 5f 3045 | c9 3046 | 92 3047 | 5b 3048 | 9d 3049 | 31 3050 | 71 3051 | 4d 3052 | ea 3053 | 51 3054 | 39 3055 | 88 3056 | 94 3057 | b7 3058 | 27 3059 | 5c 3060 | 65 3061 | a4 3062 | 32 3063 | c2 3064 | 89 3065 | bc 3066 | 8f 3067 | 35 3068 | 9a 3069 | 39 3070 | 92 3071 | 9f 3072 | f0 3073 | af 3074 | 74 3075 | 37 3076 | 8c 3077 | d0 3078 | 3a 3079 | a9 3080 | 55 3081 | 53 3082 | 49 3083 | 9a 3084 | 6e 3085 | cb 3086 | 82 3087 | 4e 3088 | 34 3089 | d3 3090 | 56 3091 | 40 3092 | 76 3093 | 27 3094 | 3c 3095 | ba 3096 | 58 3097 | 93 3098 | b6 3099 | 2b 3100 | bb 3101 | 27 3102 | c2 3103 | c8 3104 | 28 3105 | 81 3106 | 50 3107 | 22 3108 | ab 3109 | c6 3110 | 63 3111 | 07 3112 | df 3113 | ce 3114 | a3 3115 | 42 3116 | 24 3117 | 94 3118 | c3 3119 | c6 3120 | 4d 3121 | 72 3122 | 69 3123 | c0 3124 | c8 3125 | bf 3126 | 91 3127 | 3b 3128 | b1 3129 | 37 3130 | 6a 3131 | e2 3132 | 5c 3133 | a3 3134 | 79 3135 | 6a 3136 | 55 3137 | 3b 3138 | b3 3139 | 6c 3140 | a2 3141 | 41 3142 | 25 3143 | e1 3144 | 5d 3145 | d7 3146 | 7f 3147 | 94 3148 | 1b 3149 | 4b 3150 | 26 3151 | b2 3152 | 38 3153 | 98 3154 | ba 3155 | 85 3156 | 6f 3157 | e0 3158 | 47 3159 | 75 3160 | d7 3161 | 81 3162 | bb 3163 | 60 3164 | a6 3165 | 65 3166 | 68 3167 | 91 3168 | 3c 3169 | 7a 3170 | d5 3171 | d0 3172 | 58 3173 | 5d 3174 | 2a 3175 | c0 3176 | 58 3177 | 8a 3178 | 79 3179 | 89 3180 | a6 3181 | b2 3182 | 5a 3183 | 3a 3184 | 90 3185 | 69 3186 | 8a 3187 | 82 3188 | 37 3189 | 53 3190 | b7 3191 | 6e 3192 | 6d 3193 | 87 3194 | 45 3195 | 9d 3196 | 22 3197 | e2 3198 | b1 3199 | 3a 3200 | 94 3201 | 84 3202 | d4 3203 | 26 3204 | c7 3205 | d6 3206 | 76 3207 | 99 3208 | 27 3209 | 5b 3210 | ae 3211 | 50 3212 | ea 3213 | 8e 3214 | c7 3215 | e2 3216 | 85 3217 | 25 3218 | b9 3219 | 2e 3220 | 8e 3221 | 91 3222 | b3 3223 | 79 3224 | 59 3225 | 68 3226 | 21 3227 | cc 3228 | 24 3229 | 8a 3230 | c9 3231 | a1 3232 | 54 3233 | db 3234 | 3c 3235 | 92 3236 | 83 3237 | 5c 3238 | 9c 3239 | cb 3240 | 3f 3241 | 93 3242 | 1d 3243 | de 3244 | 6d 3245 | 53 3246 | 84 3247 | a3 3248 | 47 3249 | bb 3250 | c1 3251 | 2f 3252 | 58 3253 | 5f 3254 | 95 3255 | a6 3256 | 45 3257 | 61 3258 | de 3259 | aa 3260 | 7f 3261 | 64 3262 | 25 3263 | 88 3264 | e2 3265 | 15 3266 | 83 3267 | a0 3268 | 5a 3269 | 57 3270 | 8b 3271 | b6 3272 | 25 3273 | f2 3274 | 81 3275 | 48 3276 | 98 3277 | 8f 3278 | 55 3279 | 64 3280 | 5f 3281 | 82 3282 | 75 3283 | 9a 3284 | 69 3285 | 51 3286 | a1 3287 | 29 3288 | 61 3289 | 91 3290 | a2 3291 | 77 3292 | 9f 3293 | de 3294 | 2d 3295 | 1c 3296 | b4 3297 | 7a 3298 | 5f 3299 | 56 3300 | 4f 3301 | 91 3302 | e0 3303 | 7c 3304 | 75 3305 | b5 3306 | 51 3307 | 6b 3308 | c7 3309 | 64 3310 | 6e 3311 | be 3312 | 86 3313 | 8f 3314 | 44 3315 | c3 3316 | b4 3317 | b0 3318 | 38 3319 | b7 3320 | b6 3321 | b3 3322 | 6b 3323 | 29 3324 | 8c 3325 | 8b 3326 | ac 3327 | 47 3328 | 96 3329 | cb 3330 | 4b 3331 | 34 3332 | a3 3333 | 3a 3334 | 92 3335 | ac 3336 | 6d 3337 | 88 3338 | 2c 3339 | c7 3340 | 86 3341 | 0d 3342 | ce 3343 | 2d 3344 | 9e 3345 | dd 3346 | ac 3347 | 36 3348 | da 3349 | 4a 3350 | e1 3351 | 5f 3352 | bb 3353 | d9 3354 | 51 3355 | 40 3356 | 6a 3357 | a4 3358 | 52 3359 | 85 3360 | d0 3361 | 55 3362 | b5 3363 | 95 3364 | d6 3365 | 48 3366 | 8a 3367 | 3e 3368 | 2d 3369 | 8e 3370 | b7 3371 | 61 3372 | a8 3373 | 33 3374 | 60 3375 | 86 3376 | 3f 3377 | 79 3378 | 4a 3379 | 76 3380 | af 3381 | 8d 3382 | 56 3383 | 42 3384 | 64 3385 | 56 3386 | ad 3387 | a4 3388 | 68 3389 | 7b 3390 | c3 3391 | b7 3392 | 3b 3393 | 79 3394 | a8 3395 | e6 3396 | 73 3397 | bf 3398 | 35 3399 | 44 3400 | cf 3401 | a1 3402 | 44 3403 | 87 3404 | 86 3405 | 53 3406 | bb 3407 | b9 3408 | 44 3409 | 6b 3410 | 39 3411 | 87 3412 | 97 3413 | 9d 3414 | 2e 3415 | 92 3416 | 8f 3417 | 56 3418 | a1 3419 | 52 3420 | 9c 3421 | 6b 3422 | c3 3423 | 7f 3424 | 4a 3425 | 52 3426 | b5 3427 | 1a 3428 | 8a 3429 | 67 3430 | 9c 3431 | bc 3432 | 5b 3433 | dd 3434 | 6c 3435 | 1c 3436 | ac 3437 | 95 3438 | c0 3439 | 61 3440 | d9 3441 | 9a 3442 | 9c 3443 | c8 3444 | 3b 3445 | 45 3446 | d3 3447 | b8 3448 | 20 3449 | a6 3450 | 1e 3451 | 86 3452 | 41 3453 | b2 3454 | 1e 3455 | 5b 3456 | 80 3457 | 73 3458 | c4 3459 | 34 3460 | 5e 3461 | b8 3462 | d8 3463 | 9f 3464 | 1c 3465 | 6e 3466 | a3 3467 | 9b 3468 | af 3469 | 5d 3470 | 6a 3471 | 62 3472 | 97 3473 | 9d 3474 | 8e 3475 | 95 3476 | 2e 3477 | c2 3478 | 42 3479 | a5 3480 | 29 3481 | aa 3482 | 97 3483 | 87 3484 | bc 3485 | 93 3486 | 30 3487 | a2 3488 | c8 3489 | 6a 3490 | c1 3491 | 58 3492 | be 3493 | 4a 3494 | 2d 3495 | c7 3496 | 56 3497 | 8e 3498 | 84 3499 | c9 3500 | 58 3501 | b9 3502 | 7a 3503 | a5 3504 | 66 3505 | 32 3506 | 59 3507 | 55 3508 | 6f 3509 | 4d 3510 | cc 3511 | 75 3512 | 92 3513 | d0 3514 | a7 3515 | b1 3516 | a6 3517 | 91 3518 | 9a 3519 | 9d 3520 | b1 3521 | 27 3522 | 45 3523 | 9c 3524 | 71 3525 | 41 3526 | 1c 3527 | 6a 3528 | a2 3529 | db 3530 | 61 3531 | 3a 3532 | 41 3533 | cf 3534 | f6 3535 | 26 3536 | 50 3537 | c1 3538 | 31 3539 | c7 3540 | 6d 3541 | 62 3542 | cd 3543 | 48 3544 | 5e 3545 | d2 3546 | 23 3547 | 82 3548 | 4f 3549 | 22 3550 | 9d 3551 | 53 3552 | 6c 3553 | 37 3554 | c8 3555 | 60 3556 | 87 3557 | da 3558 | 8f 3559 | 54 3560 | 37 3561 | e3 3562 | 45 3563 | 6e 3564 | 41 3565 | 70 3566 | 35 3567 | 35 3568 | 83 3569 | 95 3570 | ae 3571 | cb 3572 | 71 3573 | 3a 3574 | c2 3575 | 24 3576 | 72 3577 | 6d 3578 | 64 3579 | 64 3580 | 7b 3581 | 34 3582 | 56 3583 | 9c 3584 | 6d 3585 | 82 3586 | 93 3587 | ab 3588 | 86 3589 | c7 3590 | bb 3591 | 9c 3592 | 28 3593 | 86 3594 | 5d 3595 | d8 3596 | 89 3597 | 34 3598 | 89 3599 | 83 3600 | a2 3601 | a4 3602 | 4f 3603 | 41 3604 | d6 3605 | 48 3606 | 9a 3607 | e8 3608 | 3e 3609 | bf 3610 | 2e 3611 | dd 3612 | aa 3613 | f5 3614 | 3d 3615 | b1 3616 | df 3617 | 54 3618 | 58 3619 | 2d 3620 | 94 3621 | 12 3622 | ea 3623 | 82 3624 | af 3625 | 2a 3626 | 9e 3627 | 36 3628 | ee 3629 | ae 3630 | 81 3631 | a5 3632 | d6 3633 | 55 3634 | 46 3635 | d4 3636 | b3 3637 | 83 3638 | dd 3639 | 42 3640 | c5 3641 | ba 3642 | 1a 3643 | 5b 3644 | bf 3645 | c9 3646 | 29 3647 | cd 3648 | a7 3649 | bd 3650 | 48 3651 | cb 3652 | 53 3653 | 1a 3654 | 63 3655 | e5 3656 | 74 3657 | a8 3658 | a4 3659 | 7e 3660 | b9 3661 | 40 3662 | 50 3663 | ba 3664 | 65 3665 | 3e 3666 | 93 3667 | d5 3668 | 71 3669 | 9e 3670 | 24 3671 | 7c 3672 | bb 3673 | 7b 3674 | 6d 3675 | 67 3676 | 5e 3677 | 60 3678 | b1 3679 | 38 3680 | 86 3681 | 89 3682 | 8e 3683 | de 3684 | c5 3685 | 4b 3686 | 6f 3687 | c2 3688 | 28 3689 | 92 3690 | b2 3691 | ad 3692 | 95 3693 | 31 3694 | c5 3695 | 48 3696 | d6 3697 | 27 3698 | 89 3699 | 42 3700 | 1f 3701 | 66 3702 | 6c 3703 | 4c 3704 | 6b 3705 | 93 3706 | 86 3707 | a3 3708 | b2 3709 | 61 3710 | 9f 3711 | 67 3712 | 2b 3713 | 36 3714 | 73 3715 | c2 3716 | 4e 3717 | ba 3718 | 65 3719 | 81 3720 | 3f 3721 | 2b 3722 | 4c 3723 | 43 3724 | 5d 3725 | b7 3726 | 56 3727 | ed 3728 | 4d 3729 | af 3730 | 8e 3731 | 84 3732 | 2e 3733 | 68 3734 | 6f 3735 | be 3736 | 4d 3737 | 40 3738 | b5 3739 | 80 3740 | 3d 3741 | b3 3742 | b1 3743 | 77 3744 | 33 3745 | b0 3746 | 5e 3747 | c7 3748 | 8a 3749 | 1f 3750 | 65 3751 | 86 3752 | cd 3753 | 62 3754 | 59 3755 | 7d 3756 | 24 3757 | 97 3758 | 89 3759 | 52 3760 | 53 3761 | 85 3762 | ce 3763 | 46 3764 | b9 3765 | c9 3766 | 5e 3767 | 6b 3768 | b1 3769 | 98 3770 | 4a 3771 | b0 3772 | 6a 3773 | 9c 3774 | 1c 3775 | a8 3776 | ba 3777 | c6 3778 | 82 3779 | 88 3780 | 3b 3781 | a5 3782 | c1 3783 | 47 3784 | d9 3785 | 96 3786 | 90 3787 | b9 3788 | bf 3789 | 90 3790 | 23 3791 | a2 3792 | 35 3793 | 9b 3794 | 56 3795 | 3f 3796 | d1 3797 | 6f 3798 | c1 3799 | 42 3800 | 54 3801 | cc 3802 | 8f 3803 | ab 3804 | 6f 3805 | 25 3806 | 69 3807 | 94 3808 | c6 3809 | 35 3810 | 53 3811 | 49 3812 | 33 3813 | a8 3814 | b7 3815 | 77 3816 | 82 3817 | 3a 3818 | d7 3819 | b3 3820 | 29 3821 | 69 3822 | e1 3823 | 71 3824 | 4a 3825 | db 3826 | 85 3827 | 70 3828 | e8 3829 | 44 3830 | 9f 3831 | a5 3832 | ce 3833 | 3f 3834 | 7d 3835 | 46 3836 | 46 3837 | 5b 3838 | b8 3839 | a5 3840 | 4a 3841 | 40 3842 | a3 3843 | 5e 3844 | a9 3845 | 58 3846 | 4d 3847 | a6 3848 | 70 3849 | f4 3850 | 6f 3851 | 42 3852 | 59 3853 | c1 3854 | b0 3855 | 41 3856 | 8e 3857 | ce 3858 | 87 3859 | 95 3860 | d5 3861 | 84 3862 | 9d 3863 | 74 3864 | ae 3865 | 5e 3866 | 87 3867 | 78 3868 | d0 3869 | 4f 3870 | e3 3871 | 35 3872 | 69 3873 | b8 3874 | ab 3875 | 49 3876 | f3 3877 | 97 3878 | 65 3879 | 3e 3880 | c0 3881 | 30 3882 | a6 3883 | 42 3884 | a6 3885 | 67 3886 | 9b 3887 | a6 3888 | 35 3889 | 97 3890 | 2f 3891 | 81 3892 | 48 3893 | 7a 3894 | 2e 3895 | 94 3896 | 2e 3897 | 5e 3898 | 82 3899 | bc 3900 | b6 3901 | 80 3902 | 64 3903 | ce 3904 | 3c 3905 | a2 3906 | ae 3907 | 2e 3908 | b0 3909 | 65 3910 | cf 3911 | 37 3912 | 30 3913 | 8c 3914 | 72 3915 | 8d 3916 | 2a 3917 | 7e 3918 | 62 3919 | bd 3920 | 37 3921 | ab 3922 | 1d 3923 | 3b 3924 | 37 3925 | 58 3926 | 30 3927 | af 3928 | 82 3929 | 7f 3930 | 10 3931 | 45 3932 | ad 3933 | 9e 3934 | 74 3935 | 90 3936 | 6a 3937 | cc 3938 | 94 3939 | 64 3940 | b9 3941 | 3b 3942 | cd 3943 | 5d 3944 | d8 3945 | 5f 3946 | 70 3947 | ba 3948 | d1 3949 | a9 3950 | 1f 3951 | cf 3952 | 8e 3953 | 6e 3954 | cc 3955 | 63 3956 | bb 3957 | 83 3958 | 6a 3959 | c1 3960 | 5a 3961 | c5 3962 | b8 3963 | 6b 3964 | ad 3965 | b3 3966 | 56 3967 | 5a 3968 | a3 3969 | 43 3970 | d3 3971 | 34 3972 | 94 3973 | 9c 3974 | 72 3975 | a9 3976 | 58 3977 | 48 3978 | b5 3979 | 63 3980 | d5 3981 | b1 3982 | 37 3983 | a7 3984 | a2 3985 | 51 3986 | da 3987 | 98 3988 | c0 3989 | bf 3990 | 77 3991 | 95 3992 | 6a 3993 | b7 3994 | d2 3995 | 56 3996 | ce 3997 | 44 3998 | 95 3999 | 2f 4000 | 67 4001 | c8 4002 | 17 4003 | 83 4004 | 4b 4005 | 79 4006 | 43 4007 | 78 4008 | 5a 4009 | 8a 4010 | 9c 4011 | 36 4012 | 89 4013 | 28 4014 | 56 4015 | 90 4016 | 0f 4017 | 81 4018 | 89 4019 | 5b 4020 | 61 4021 | a6 4022 | b6 4023 | 41 4024 | 82 4025 | c0 4026 | 35 4027 | 39 4028 | 53 4029 | 25 4030 | 53 4031 | c2 4032 | 8c 4033 | 61 4034 | 9e 4035 | 5c 4036 | d7 4037 | 62 4038 | 46 4039 | ce 4040 | 74 4041 | d8 4042 | 25 4043 | cf 4044 | 73 4045 | 5a 4046 | 46 4047 | c1 4048 | 7e 4049 | 4c 4050 | 98 4051 | 84 4052 | 71 4053 | b3 4054 | 41 4055 | 12 4056 | df 4057 | 48 4058 | 2f 4059 | a9 4060 | 72 4061 | 17 4062 | ad 4063 | f3 4064 | 44 4065 | 52 4066 | 3e 4067 | c1 4068 | d2 4069 | 7a 4070 | 90 4071 | aa 4072 | b5 4073 | 46 4074 | ac 4075 | 4d 4076 | 76 4077 | c1 4078 | b4 4079 | df 4080 | 57 4081 | db 4082 | b3 4083 | 97 4084 | 2e 4085 | 72 4086 | cc 4087 | 54 4088 | 87 4089 | 93 4090 | 6d 4091 | 91 4092 | d8 4093 | d2 4094 | 60 4095 | ae 4096 | 2e 4097 | -------------------------------------------------------------------------------- /verilog/clocks.py: -------------------------------------------------------------------------------- 1 | ctx.addClock("hdmi_clk", 25) 2 | ctx.addClock("hdmi_bit_clk", 125) 3 | ctx.addClock("display_.clk_16mhz_", 16) 4 | 5 | -------------------------------------------------------------------------------- /verilog/dither.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Blue-Noise dithering of the HDMI signal into a 1bpp, 3 | * along with clock-crossing to make it usable by an externaly 4 | * clocked video output. 5 | */ 6 | 7 | module hdmi_dither( 8 | // inputs in the hdmi_clk domain 9 | input hdmi_clk, 10 | input hdmi_vsync, 11 | input [11:0] hdmi_xaddr, 12 | input [11:0] hdmi_yaddr, 13 | input hdmi_valid, 14 | input [7:0] hdmi_r, 15 | input [7:0] hdmi_g, 16 | input [7:0] hdmi_b, 17 | 18 | // outputs in the clk domain 19 | input mono_clk, 20 | output [15:0] mono_bits, 21 | output [11:0] mono_xaddr, // base address of the 16 bits 22 | output [11:0] mono_yaddr, 23 | output mono_bits_ready, 24 | output mono_vsync 25 | ); 26 | parameter DITHER_BITS = 6; 27 | parameter X_OFFSET = 64; 28 | parameter Y_OFFSET = 128; 29 | parameter WIDTH = 512; 30 | parameter HEIGHT = 342; 31 | 32 | reg [15:0] hdmi_bits; 33 | reg [15:0] mono_bits; 34 | 35 | reg bits_ready; 36 | reg mono_bits_ready; 37 | reg [11:0] mono_xaddr; 38 | reg [11:0] mono_yaddr; 39 | 40 | wire mono_vsync; 41 | 42 | wire vsync_falling_edge; 43 | edge_detect vsync_edge(hdmi_clk, hdmi_vsync, vsync_falling_edge); 44 | 45 | clock_cross_strobe 46 | ready_strobe(hdmi_clk, bits_ready, mono_clk, mono_bits_ready); 47 | clock_cross_strobe 48 | vsync_strobe(hdmi_clk, vsync_falling_edge, mono_clk, mono_vsync); 49 | 50 | wire dither_bit; 51 | dither #( 52 | .ADDR_BITS(DITHER_BITS) 53 | ) dither_i( 54 | .clk(hdmi_clk), 55 | .r(hdmi_r), 56 | .b(hdmi_b), 57 | .g(hdmi_g), 58 | .x(hdmi_xaddr[DITHER_BITS-1:0]), 59 | .y(hdmi_yaddr[DITHER_BITS-1:0]), 60 | .out(dither_bit) 61 | ); 62 | 63 | wire [11:0] out_xaddr = hdmi_xaddr - X_OFFSET; 64 | wire [11:0] out_yaddr = hdmi_yaddr - Y_OFFSET; 65 | 66 | wire hdmi_in_window = 1 67 | && X_OFFSET <= hdmi_xaddr && hdmi_xaddr < X_OFFSET + WIDTH 68 | && Y_OFFSET <= hdmi_yaddr && hdmi_yaddr < Y_OFFSET + HEIGHT + 1; 69 | 70 | wire [15:0] hdmi_bits_next = { hdmi_bits[14:0], dither_bit }; 71 | 72 | always @(posedge hdmi_clk) 73 | begin 74 | bits_ready <= 0; 75 | 76 | // accumulate the hdmi bits as they come in 77 | // dither bit is delayed by one clock, but that's ok 78 | // since it just shifts the display by a pixel 79 | if (hdmi_valid) 80 | hdmi_bits <= hdmi_bits_next; 81 | 82 | // clock crossing flag for the full shift register 83 | if (hdmi_valid && out_xaddr[3:0] == 4'b0000) 84 | begin 85 | // full shift register, store the base address 86 | // of the X register and the bits 87 | // do not signal if outside of the active window 88 | bits_ready <= hdmi_in_window; 89 | mono_bits <= hdmi_bits; 90 | mono_xaddr <= { out_xaddr[11:4]-1, 4'b0000 }; 91 | mono_yaddr <= out_yaddr; 92 | end 93 | end 94 | endmodule 95 | 96 | /* 97 | * Blue Noise dithering uses two block RAMs to store the 32x32x8 image 98 | * and thresholds the sum to determine if this pixel is black or white 99 | */ 100 | module dither( 101 | input clk, 102 | input [7:0] r, 103 | input [7:0] g, 104 | input [7:0] b, 105 | input [ADDR_BITS-1:0] x, 106 | input [ADDR_BITS-1:0] y, 107 | output out 108 | ); 109 | parameter ADDR_BITS = 5; 110 | parameter NOISE_FILE = 111 | ADDR_BITS == 5 ? "bluenoise-32.hex" : 112 | ADDR_BITS == 6 ? "bluenoise-64.hex" : 113 | ADDR_BITS == 7 ? "bluenoise-128.hex" : 114 | ADDR_BITS == 8 ? "bluenoise-256.hex" : 115 | "unknown-noise-value"; 116 | 117 | reg [7:0] noise[0:(1 << (2*ADDR_BITS)) - 1]; 118 | initial $readmemh(NOISE_FILE, noise); 119 | wire [2*ADDR_BITS-1:0] noise_addr = { x, y }; 120 | reg [7:0] noise_value0; 121 | reg [7:0] noise_value1; 122 | reg [7:0] noise_value2; 123 | 124 | reg out; 125 | 126 | // this may need to be adjusted once all three channels 127 | // are available. the plus one ensures that 255 -> 256 128 | // for a pure white and avoids a larger comparison in 129 | // the clocked block. 130 | //wire [9:0] sum = r + g + b + noise_value + 1; 131 | wire [8:0] r_sum = r + noise_value0 + 1; 132 | wire [8:0] b_sum = b + noise_value0 + 1; 133 | wire [8:0] g_sum = g + noise_value0 + 1; 134 | 135 | // r is not full range? 136 | wire r_dither = (r_sum > 9'd256); 137 | wire b_dither = (b_sum > 9'd256); 138 | wire g_dither = (g_sum > 9'd256); 139 | 140 | wire dither_bit = 0 141 | | r_dither 142 | | b_dither 143 | | g_dither 144 | ; 145 | 146 | always @(posedge clk) 147 | begin 148 | // track the last few noise values 149 | // so that R, G, and B have slightly different patterns 150 | noise_value2 <= noise_value1; 151 | noise_value1 <= noise_value0; 152 | noise_value0 <= noise[noise_addr]; 153 | 154 | out <= dither_bit; 155 | end 156 | endmodule 157 | -------------------------------------------------------------------------------- /verilog/dpram.v: -------------------------------------------------------------------------------- 1 | `ifndef _dpram_v_ 2 | `define _dpram_v_ 3 | 4 | /* 5 | * write 2-bits at a time, read 16-bits. 6 | * This allows the block ram to be used as 7 | * a clock-crossing shift register. 8 | */ 9 | module dpram_2x16( 10 | // read domain 11 | input rd_clk, 12 | input [7:0] rd_addr, 13 | output [15:0] rd_data, 14 | // write domain 15 | input wr_clk, 16 | input wr_enable, 17 | input [10:0] wr_addr, 18 | input [1:0] wr_data 19 | ); 20 | `define RAM4k 21 | `ifdef RAM4k 22 | // RAM port mappings from https://github.com/YosysHQ/nextpnr/issues/1118 23 | // the weird shuffling might have something to do with how the tiles 24 | // are physically routed? 25 | wire [10:0] RADDR = {3'b000, rd_addr[7:0]}; 26 | wire [10:0] WADDR = {wr_addr[0], wr_addr[1], wr_addr[2], wr_addr[10:3]}; 27 | 28 | wire [15:0] RDATA = { 29 | rd_data[15], rd_data[ 7], rd_data[11], rd_data[ 3], 30 | rd_data[13], rd_data[ 5], rd_data[ 9], rd_data[ 1], 31 | rd_data[14], rd_data[ 6], rd_data[10], rd_data[ 2], 32 | rd_data[12], rd_data[ 4], rd_data[ 8], rd_data[ 0] 33 | }; 34 | 35 | wire [15:0] WDATA = { 36 | 1'b0, 1'b0, 1'b0, 1'b0, 37 | wr_data[1], 1'b0, 1'b0, 1'b0, 38 | 1'b0, 1'b0, 1'b0, 1'b0, 39 | wr_data[0], 1'b0, 1'b0, 1'b0 40 | }; 41 | 42 | parameter LOCATION=""; 43 | (* BEL=LOCATION *) 44 | SB_RAM40_4K #( 45 | .WRITE_MODE(3), // x2 46 | .READ_MODE(0) // x16 47 | ) ram256x16_0 ( 48 | .RDATA(RDATA), 49 | .RADDR(RADDR), 50 | .RCLK(rd_clk), 51 | .RCLKE(1'b1), 52 | .RE(1'b1), 53 | .WADDR(WADDR), 54 | .WCLK(wr_clk), 55 | .WCLKE(wr_enable), // 1'b1), 56 | .WE(1'b1), // wr_enable), 57 | .WDATA(WDATA) 58 | ); 59 | `else 60 | // this is the non-primitive version, just in case 61 | reg [1:0] ram[0:2047]; 62 | reg [15:0] rd_data; 63 | 64 | always @(posedge wr_clk) 65 | if (wr_clk) 66 | ram[wr_addr] <= wr_data; 67 | always @(posedge rd_clk) 68 | rd_data <= { 69 | ram[{rd_addr, 3'b111}], 70 | ram[{rd_addr, 3'b110}], 71 | ram[{rd_addr, 3'b101}], 72 | ram[{rd_addr, 3'b100}], 73 | ram[{rd_addr, 3'b011}], 74 | ram[{rd_addr, 3'b010}], 75 | ram[{rd_addr, 3'b001}], 76 | ram[{rd_addr, 3'b000}] 77 | }; 78 | `endif 79 | endmodule 80 | 81 | `endif 82 | -------------------------------------------------------------------------------- /verilog/edid.hex: -------------------------------------------------------------------------------- 1 | 00 ff ff ff ff ff ff 00 43 0c 01 00 2 | 40 ce 01 00 ff 21 01 04 a2 40 30 78 3 | 06 ee 95 a3 54 4c 99 26 0f 50 54 20 4 | 00 00 01 01 01 01 01 01 01 01 01 01 5 | 01 01 01 01 01 01 d5 09 80 a0 20 e0 6 | 2d 10 10 60 a2 00 00 00 00 00 00 18 7 | 00 00 00 fc 00 50 69 78 65 6c 57 72 8 | 61 6e 67 6c 65 72 00 00 00 00 00 00 9 | 00 00 00 00 00 00 00 00 00 00 00 00 10 | 00 00 00 00 00 00 00 00 00 00 00 00 11 | 00 00 00 00 00 00 00 e5 12 | -------------------------------------------------------------------------------- /verilog/fb-init.hex: -------------------------------------------------------------------------------- 1 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2 | 00 00 00 00 00 00 00 00 00 3a 40 00 00 00 00 00 3 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 | 00 00 00 00 00 00 00 00 08 d2 35 00 00 00 00 00 11 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 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82 f1 8c 60 66 6b 162 | 7a 8f 6d 00 00 59 ff f5 06 00 00 00 00 00 00 c4 163 | ff ff f3 fa 79 02 89 ff ff fc 84 05 00 00 e6 ff 164 | ff ff b5 1d 00 00 c8 ff 7d 00 00 00 00 9e ff ff 165 | fd 8a 07 00 00 00 23 78 a4 ef d7 77 6e 66 5f 5f 166 | 71 86 bf e1 7b 0a 00 00 00 00 00 00 00 5d ff ff 167 | ff f1 69 57 ff ff a6 02 03 6f e4 30 00 00 00 00 168 | 00 c5 ff fd b4 70 63 b6 db 2a 00 00 00 00 00 00 169 | 00 00 00 00 00 00 00 12 d5 ff ff ff ff ff fc dd 170 | 9e 46 00 00 00 9f f0 81 00 00 00 00 00 00 00 89 171 | ff ff cf 35 00 00 a7 ff cf 34 00 00 00 00 df ff 172 | e3 55 00 00 00 10 fc ce 2b 00 00 00 00 a6 ff c3 173 | 35 00 00 00 00 2b e6 ff ff ff ff ff ff ff ff fc 174 | de a6 55 06 00 00 00 00 00 00 00 00 00 56 ff ff 175 | a9 1b 00 11 e6 ff ff e5 ea a1 15 00 00 00 00 00 176 | 0a f9 ff ff ff ff fe a3 10 00 00 00 00 00 00 00 177 | 00 00 00 00 00 00 00 11 22 22 22 22 1e 0d 00 00 178 | 00 00 00 00 00 45 09 00 00 00 00 00 00 00 00 12 179 | 93 60 04 00 00 00 53 58 04 00 00 00 00 00 54 66 180 | 0c 00 00 00 00 1b 31 00 00 00 00 00 00 41 52 00 181 | 00 00 00 00 00 23 33 33 33 2c 22 22 1a 11 11 06 182 | 00 00 00 00 00 00 00 00 00 00 00 00 00 0e 7f 3a 183 | 00 00 00 00 1b 7f 8a 60 16 00 00 00 00 00 00 00 184 | 43 ff f8 51 68 61 25 00 00 00 00 00 00 00 00 00 185 | 01 03 04 06 07 09 0a 0b 0d 0e 10 11 12 13 15 16 186 | 18 19 1a 1c 1d 1f 20 22 23 24 26 27 29 2a 2c 2d 187 | 2e 30 31 33 34 36 37 38 3a 3b 3d 3e 40 41 42 44 188 | 45 47 48 4a 4b 4c 4e 4f 51 52 54 55 56 58 59 5b 189 | 5c 5d 5e 60 61 62 64 65 67 68 6a 6b 6c 6e 6f 71 190 | 72 74 75 76 78 79 7b 7c 7e 7f 80 82 83 85 86 88 191 | 89 8a 8c 8d 8f 90 92 93 94 96 97 99 9a 9c 9d 9e 192 | d1 ff ea a4 a6 a7 a8 aa ab ac ad af b0 b2 b3 b5 193 | 02 04 06 08 0a 0c 0e 10 12 14 16 18 19 1b 1d 1f 194 | 21 23 25 27 29 2b 2d 2f 31 33 35 37 39 3b 3d 3f 195 | 41 43 45 47 49 4b 4d 4f 51 53 55 57 59 5b 5d 5f 196 | 61 63 65 67 69 6b 6d 6f 71 73 75 77 79 7b 7d 7f 197 | 81 83 84 86 88 8a 8c 8e 90 92 94 96 98 9a 9c 9e 198 | a0 a2 a4 a6 a8 aa ac ae b0 b2 b4 b6 b8 ba bc be 199 | c0 c2 c4 c6 c8 ca cc ce d0 d2 d4 d6 d8 da dc de 200 | f8 ff f3 e6 e8 ea ec ee f0 f1 f3 f5 f7 f9 fb fd 201 | 02 04 06 08 0a 0c 0e 10 12 14 16 18 19 1b 1d 1f 202 | 21 23 25 27 29 2b 2d 2f 31 33 35 37 39 3b 3d 3f 203 | 41 43 45 47 49 4b 4d 4f 51 53 55 57 59 5b 5d 5f 204 | 61 63 65 67 69 6b 6d 6f 71 73 75 77 79 7b 7d 7f 205 | 81 83 84 86 88 8a 8c 8e 90 92 94 96 98 9a 9c 9e 206 | a0 a2 a4 a6 a8 aa ac ae b0 b2 b4 b6 b8 ba bc be 207 | c0 c2 c4 c6 c8 ca cc ce d0 d2 d4 d6 d8 da dc df 208 | fe ff ed e6 e8 ea ec ee f0 f1 f3 f5 f7 f9 fb fd 209 | 02 04 06 08 0a 0c 0e 10 12 14 16 18 19 1b 1d 1f 210 | 21 23 25 27 29 2b 2d 2f 31 33 35 37 39 3b 3d 3f 211 | 41 43 45 47 49 4b 4d 4f 51 53 55 57 59 5b 5d 5f 212 | 61 63 65 67 69 6b 6d 6f 71 73 75 77 79 7b 7d 7f 213 | 81 83 84 86 88 8a 8c 8e 90 92 94 96 98 9a 9c 9e 214 | a0 a2 a4 a6 a8 aa ac ae b0 b2 b4 b6 b8 ba bc be 215 | c0 c2 c4 c6 c8 ca cc ce d0 d2 d4 d6 d8 da dc e6 216 | ff ff e7 e6 e8 ea ec ee f0 f1 f3 f5 f7 f9 fb fd 217 | 02 04 06 08 0a 0c 0e 10 12 14 16 18 19 1b 1d 1f 218 | 21 23 25 27 29 2b 2d 2f 31 33 35 37 39 3b 3d 3f 219 | 41 43 45 47 49 4b 4d 4f 51 53 55 57 59 5b 5d 5f 220 | 61 63 65 67 69 6b 6d 6f 71 73 75 77 79 7b 7d 7f 221 | 81 83 84 86 88 8a 8c 8e 90 92 94 96 98 9a 9c 9e 222 | a0 a2 a4 a6 a8 aa ac ae b0 b2 b4 b6 b8 ba bc be 223 | c0 c2 c4 c6 c8 ca cc ce d0 d2 d4 d6 d8 da dc ee 224 | ff fb e4 e6 e8 ea ec ee f0 f1 f3 f5 f7 f9 fb fd 225 | 02 04 06 08 0a 0c 0e 10 12 14 16 18 19 1b 1d 1f 226 | 21 23 25 27 29 2b 2d 2f 31 33 35 37 39 3b 3d 3f 227 | 41 43 45 47 49 4b 4d 4f 51 53 55 57 59 5b 5d 5f 228 | 61 63 65 67 69 6b 6d 6f 71 73 75 77 79 7b 7d 7f 229 | 81 83 84 86 88 8a 8c 8e 90 92 94 96 98 9a 9c 9e 230 | a0 a2 a4 a6 a8 aa ac ae b0 b2 b4 b6 b8 ba bc be 231 | c0 c2 c4 c6 c8 ca cc ce d0 d2 d4 d6 d8 da dc f7 232 | ff f5 e4 e6 e8 ea ec ee f0 f1 f3 f5 f7 f9 fb fd 233 | 02 04 06 08 0a 0c 0e 10 12 14 16 18 19 1b 1d 1f 234 | 21 23 25 27 29 2b 2d 2f 31 33 35 37 39 3b 3d 3f 235 | 41 43 45 47 49 4b 4d 4f 51 53 55 57 59 5b 5d 5f 236 | 61 63 65 67 69 6b 6d 6f 71 73 75 77 79 7b 7d 7f 237 | 81 83 84 86 88 8a 8c 8e 90 92 94 96 98 9a 9c 9e 238 | a0 a2 a4 a6 a8 aa ac ae b0 b2 b4 b6 b8 ba bc be 239 | c0 c2 c4 c6 c8 ca cc ce d0 d2 d4 d6 d8 e4 f2 fe 240 | ff f7 f0 f0 ef eb ec ee f0 f1 f3 f5 f7 f9 fb fd 241 | 02 04 06 08 0a 0c 0e 10 12 14 16 18 19 1b 1d 1f 242 | 21 23 25 27 29 2b 2d 2f 31 33 35 37 39 3b 3d 3f 243 | 41 43 45 47 49 4b 4d 4f 51 53 55 57 59 5b 5d 5f 244 | 61 63 65 67 69 6b 6d 6f 71 73 75 77 79 7b 7d 7f 245 | 81 83 84 86 88 8a 8c 8e 90 92 94 96 98 9a 9c 9e 246 | a0 a2 a4 a6 a8 aa ac ae b0 b2 b4 b6 b8 ba bc be 247 | c0 c2 c4 c6 c8 ca cc ce d0 d2 d4 d6 d9 eb ef f0 248 | f1 f2 f4 f4 ee ea ec ee f0 f1 f3 f5 f7 f9 fb fd 249 | 02 04 06 08 0a 0c 0e 10 12 14 16 18 19 1b 1d 1f 250 | 21 23 25 27 29 2b 2d 2f 31 33 35 37 39 3b 3d 3f 251 | 41 43 45 47 49 4b 4d 4f 51 53 55 57 59 5b 5d 5f 252 | 61 63 65 67 69 6b 6d 6f 71 73 75 77 79 7b 7d 7f 253 | 81 83 84 86 88 8a 8c 8e 90 92 94 96 98 9a 9c 9e 254 | a0 a2 a4 a6 a8 aa ac ae b0 b2 b4 b6 b8 ba bc be 255 | c0 c2 c4 c6 c8 ca cc ce d0 d2 d4 d6 d8 da dc de 256 | e0 e2 e4 e6 e8 ea ec ee f0 f1 f3 f5 f7 f9 fb fd 257 | -------------------------------------------------------------------------------- /verilog/hdmi.v: -------------------------------------------------------------------------------- 1 | /* 2 | * HDMI frame buffer and streaming interface. 3 | * 4 | * This uses the decoded data from the tmds_decoder to 5 | * produce pixels. It can either write them into a frame 6 | * buffer, or make them available as a streaming interface 7 | * in the hdmi_clk domain. 8 | * 9 | * Requires a 5x or 10x PLL from the pixel clock. 10 | * Clock input should use a global buffer input 11 | * -- app note says " Global Buffer Input 7 (GBIN7) is the only one that supports differential clock inputs." 12 | * -- but experimentally only 37 works. 13 | * 14 | * Pair Inputs must use negative pin of differential pairs. 15 | * The positive pin *must not be mentioned* as an input. 16 | * 17 | * The bit clock and pixel clock have a constant, but unknown phase. 18 | * We should have a "tracking" function that tries to ensure it lines up. 19 | * 20 | * https://www.analog.com/en/design-notes/video-display-signals-and-the-max9406-dphdmidvi-level-shifter8212part-i.html 21 | * V+H sync and audio header on Blue (D0) 22 | * Audio data on Red and Green 23 | * Data island period is encoded with TERC4; can we ignore it? 24 | * 25 | * sync pulses are active low 26 | * H sync keeps pulsing while V is low (twice) 27 | * V sync is 63 usec, every 60 Hz 28 | * H sync is 4 usec, every 32 usec 29 | * 30 | * 640x480 frame is actually sent as an 800x525 frame. 31 | * hbi goes 80 into X, vbi goes 22 into y 32 | */ 33 | `include "mem.v" 34 | 35 | module hdmi_stream( 36 | input hdmi_clk, 37 | input valid, 38 | input [1:0] sync, 39 | input [7:0] d0, 40 | input [7:0] d1, 41 | input [7:0] d2, 42 | 43 | // up to a 4k address output, 44 | // although we only support 640x480 45 | output [11:0] xaddr, 46 | output [11:0] yaddr, 47 | output rgb_valid, 48 | output [7:0] r, 49 | output [7:0] g, 50 | output [7:0] b, 51 | output vsync, 52 | output hsync 53 | ); 54 | reg vsync; 55 | reg hsync; 56 | reg last_hsync; 57 | reg last_vsync; 58 | 59 | reg [11:0] xaddr; 60 | reg [11:0] yaddr; 61 | 62 | reg rgb_valid; 63 | reg [7:0] r; 64 | reg [7:0] g; 65 | reg [7:0] b; 66 | 67 | wire data_valid = 1; // todo: determine data island period etc 68 | 69 | always @(posedge hdmi_clk) 70 | begin 71 | rgb_valid <= 0; 72 | r <= d2; 73 | g <= d1; 74 | b <= d0; 75 | 76 | hsync <= sync[0]; 77 | last_hsync <= hsync; 78 | 79 | last_vsync <= sync[1]; 80 | vsync <= last_vsync || sync[1]; // two clocks at least 81 | 82 | if (!valid) 83 | begin 84 | // literally nothing to do 85 | end else 86 | if (!vsync) 87 | begin 88 | // edge triggered, but we can hold this as long as we need to 89 | yaddr <= 0; 90 | xaddr <= 0; 91 | end else 92 | if (!hsync) begin 93 | // only advance the y on the falling edge of hsync 94 | if (last_hsync) 95 | yaddr <= yaddr + 1; 96 | xaddr <= 0; 97 | end else 98 | if (data_valid) begin 99 | rgb_valid <= 1; 100 | xaddr <= xaddr + 1; 101 | end 102 | end 103 | endmodule 104 | 105 | 106 | /* 107 | * Store a small window of the HDMI display for retrieval 108 | * WIDTH *must* be a power of 2. 109 | * 110 | * Read addresses are in framebuffer space, not HDMI space. 111 | */ 112 | module hdmi_framebuffer( 113 | // hdmi interface 114 | input hdmi_clk, 115 | input [11:0] xaddr, 116 | input [11:0] yaddr, 117 | input rgb_valid, 118 | input [7:0] r, 119 | input [7:0] g, 120 | input [7:0] b, 121 | output in_window, 122 | 123 | // reader inteface 124 | input clk, 125 | input [11:0] xaddr_r, 126 | input [11:0] yaddr_r, 127 | output [7:0] r_out, 128 | output [7:0] g_out, 129 | output [7:0] b_out 130 | ); 131 | parameter ADDR_WIDTH = 13; 132 | parameter [11:0] MIN_X = 50; 133 | parameter [11:0] MIN_Y = 50; 134 | parameter [11:0] WIDTH = 128; 135 | parameter [11:0] HEIGHT = 100; 136 | 137 | wire [11:0] xoffset = xaddr - MIN_X; 138 | wire [11:0] yoffset = yaddr - MIN_Y; 139 | wire in_window = (xoffset < WIDTH) && (yoffset < HEIGHT); 140 | 141 | reg [ADDR_WIDTH-1:0] waddr; 142 | reg wen = 0; 143 | 144 | ram #( 145 | .ADDR_WIDTH(ADDR_WIDTH), 146 | .DATA_WIDTH(8) 147 | ) fb_r( 148 | .wr_clk(hdmi_clk), 149 | .wr_enable(wen), 150 | .wr_addr(waddr), 151 | .wr_data(r), 152 | .rd_clk(clk), 153 | .rd_addr(raddr), 154 | .rd_data(r_out) 155 | ); 156 | 157 | ram #( 158 | .ADDR_WIDTH(ADDR_WIDTH), 159 | .DATA_WIDTH(8) 160 | ) fb_g( 161 | .wr_clk(hdmi_clk), 162 | .wr_enable(wen), 163 | .wr_addr(waddr), 164 | .wr_data(g), 165 | .rd_clk(clk), 166 | .rd_addr(raddr), 167 | .rd_data(g_out) 168 | ); 169 | 170 | ram #( 171 | .ADDR_WIDTH(ADDR_WIDTH), 172 | .DATA_WIDTH(8) 173 | ) fb_b( 174 | .wr_clk(hdmi_clk), 175 | .wr_enable(wen), 176 | .wr_addr(waddr), 177 | .wr_data(b), 178 | .rd_clk(clk), 179 | .rd_addr(raddr), 180 | .rd_data(b_out) 181 | ); 182 | 183 | wire [ADDR_WIDTH-1:0] raddr = xaddr_r | (yaddr_r * WIDTH); 184 | 185 | always @(posedge hdmi_clk) 186 | begin 187 | wen <= rgb_valid && in_window; 188 | waddr <= (xoffset) | (yoffset * WIDTH); 189 | end 190 | endmodule 191 | -------------------------------------------------------------------------------- /verilog/hdmi_pll.v: -------------------------------------------------------------------------------- 1 | /** 2 | * PLL configuration 3 | * 4 | * This Verilog module was generated automatically 5 | * using the icepll tool from the IceStorm project. 6 | * Use at your own risk. 7 | * 8 | * Given input frequency: 25.000 MHz 9 | * Requested output frequency: 250.000 MHz 10 | * Achieved output frequency: 250.000 MHz 11 | */ 12 | 13 | module hdmi_pll( 14 | input clock_in, 15 | output clock_out, 16 | output locked, 17 | input [3:0] delay 18 | ); 19 | 20 | SB_PLL40_CORE #( 21 | .FEEDBACK_PATH("SIMPLE"), 22 | .DIVR(4'b0000), // DIVR = 0 23 | .DIVF(7'b0100111), // DIVF = 39 24 | .DIVQ(3'b010), // DIVQ = 2 25 | .FILTER_RANGE(3'b010), // FILTER_RANGE = 2 26 | //.DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC") 27 | //.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), 28 | //.FDA_RELATIVE(15) // 3 sometimes works? 29 | ) uut ( 30 | .LOCK(locked), 31 | .RESETB(1'b1), 32 | .BYPASS(1'b0), 33 | .REFERENCECLK(clock_in), 34 | .PLLOUTGLOBAL(clock_out), 35 | //.DYNAMICDELAY({4'b0000, delay}) 36 | //.DYNAMICDELAY({delay, 4'b0000}) 37 | ); 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /verilog/hdmi_pll_ddr.v: -------------------------------------------------------------------------------- 1 | /** 2 | * PLL configuration 3 | * 4 | * This Verilog module was generated automatically 5 | * using the icepll tool from the IceStorm project. 6 | * Use at your own risk. 7 | * 8 | * Given input frequency: 25.000 MHz 9 | * Requested output frequency: 125.000 MHz 10 | * Achieved output frequency: 125.000 MHz 11 | */ 12 | 13 | // things to try for later 14 | //.FEEDBACK_PATH("PHASE_AND_DELAY"), 15 | //.DIVF(7'h4), // DIVF = 4 for non-simple 16 | //.DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"), 17 | 18 | //.DYNAMICDELAY(delay) 19 | //.DYNAMICDELAY(7'h11) 20 | //input [7:0] delay 21 | 22 | // 125 MHz == 8 ns/clock 23 | // 16 * 150ps per delay == 2.4 ns 24 | // maximum phase delay is 1/4 clock 25 | // guessing at a value seems to work well? 26 | 27 | module hdmi_pll( 28 | input clock_in, 29 | output clock_out, 30 | output locked, 31 | input reset 32 | ); 33 | 34 | // total guess that seems to work well 35 | parameter DELAY = 4'd8; 36 | 37 | SB_PLL40_CORE #( 38 | .FEEDBACK_PATH("SIMPLE"), 39 | .DIVR(4'b0000), // DIVR = 0 40 | .DIVF(7'd39), // DIVF = 4 for non-simple 41 | .DIVQ(3'b011), // DIVQ = 3 42 | .FILTER_RANGE(3'b010), // FILTER_RANGE = 2 43 | .FDA_FEEDBACK(DELAY), 44 | .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED") 45 | ) uut ( 46 | .LOCK(locked), 47 | .RESETB(~reset), 48 | .BYPASS(1'b0), 49 | .REFERENCECLK(clock_in), 50 | .PLLOUTGLOBAL(clock_out) 51 | ); 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /verilog/i2c.v: -------------------------------------------------------------------------------- 1 | /* 2 | * i2c device interface. 3 | * 4 | * This could probably be done with a ice40 SB_I2C block, although 5 | * folks seems to recommend against it. 6 | * 7 | * Requires 4.7k pullups to 3.3v. Do not pull up to HDMI 5v line! 8 | * 9 | * The read address is set by a write command that doesn't include any data. 10 | * 11 | * States: 12 | * Idle -> ADDR_BITS -> ADDR_ACK 13 | * ADDR_ACK -> ACTIVE -> ACTIVE_ACK 14 | */ 15 | module i2c_device( 16 | input clk, 17 | input reset, 18 | input scl_in, 19 | input sda_in, 20 | output sda_out, 21 | output sda_enable, 22 | 23 | // register interface for reads and writes 24 | output [7:0] data_addr, 25 | input [7:0] rd_data, 26 | output [7:0] wr_data, 27 | output wr_strobe 28 | ); 29 | parameter DEVICE_ADDR = 7'h50; 30 | 31 | parameter IDLE = 0; 32 | parameter SHIFT_IN = 1; 33 | parameter SHIFT_IN_ACK = 2; 34 | parameter SHIFT_OUT = 3; 35 | parameter SHIFT_OUT_ACK = 4; 36 | parameter ADDR_ACK = 5; 37 | parameter WRITE_ADDR = 6; 38 | parameter WRITE_DATA = 7; 39 | parameter READ_DATA = 8; 40 | parameter READ_ACK = 9; 41 | 42 | reg [3:0] state = IDLE; 43 | reg [3:0] next_state = IDLE; 44 | 45 | reg sda, sda0, sda1; 46 | reg scl, scl0, scl1; 47 | reg last_sda, last_scl; 48 | 49 | wire scl_rising = !last_scl && scl; 50 | wire scl_falling = last_scl && !scl; 51 | wire sda_rising = !last_sda && sda; 52 | wire sda_falling = last_sda && !sda; 53 | 54 | // buffer the SDA and SCL to avoid glitches 55 | // and tracking rising/falling edges 56 | always @(posedge clk) 57 | begin 58 | last_scl <= scl; 59 | last_sda <= sda; 60 | 61 | scl <= scl1; 62 | sda <= sda1; 63 | 64 | scl1 <= scl0; 65 | sda1 <= sda0; 66 | 67 | sda0 <= sda_in; 68 | scl0 <= scl_in; 69 | end 70 | 71 | reg [2:0] bit_counter; 72 | reg [7:0] shift_reg; 73 | reg [7:0] data_addr; 74 | reg sda_enable = 0; 75 | reg wr_strobe = 0; 76 | assign sda_out = 0; // always pull low 77 | assign wr_data = shift_reg; 78 | 79 | 80 | always @(posedge clk) 81 | begin 82 | wr_strobe <= 0; 83 | 84 | if (reset) 85 | begin 86 | sda_enable <= 0; 87 | state <= IDLE; 88 | end else 89 | if (scl && sda_falling) 90 | begin 91 | // start or restart command -- SDA falls before SCL 92 | state <= SHIFT_IN; 93 | next_state <= ADDR_ACK; 94 | bit_counter <= 0; 95 | end else 96 | if (scl && sda_rising) 97 | begin 98 | // stop command -- SDA should not change while SCL is high 99 | state <= IDLE; 100 | sda_enable <= 0; 101 | end else 102 | if (state == IDLE) 103 | begin 104 | sda_enable <= 0; 105 | end else 106 | 107 | /* shift in 8 bits of data, and then hand control to the next state */ 108 | if (state == SHIFT_IN && scl_rising) 109 | begin 110 | // bytes are sent MSB first 111 | shift_reg <= { shift_reg[6:0], sda }; 112 | if (bit_counter == 7) 113 | state <= next_state; 114 | bit_counter <= bit_counter + 1; 115 | end else 116 | if (state == SHIFT_IN && scl_falling) 117 | begin 118 | // release any ACKs that we might hold 119 | sda_enable <= 0; 120 | end else 121 | if (state == SHIFT_IN_ACK && scl_rising) 122 | begin 123 | // hold the ack line and start a normal shift in 124 | // on the next falling edge 125 | state <= SHIFT_IN; 126 | bit_counter <= 0; 127 | end else 128 | 129 | /* check device address; bottom bit is read / !write */ 130 | if (state == ADDR_ACK && scl_falling) 131 | begin 132 | if (shift_reg[7:1] == DEVICE_ADDR) 133 | begin 134 | // ack that we are handling it 135 | sda_enable <= 1; 136 | 137 | if (shift_reg[0]) begin 138 | // read mode, pre-read the current byte 139 | state <= READ_DATA; 140 | shift_reg <= rd_data; 141 | end else begin 142 | // write mode 143 | state <= SHIFT_IN_ACK; 144 | next_state <= WRITE_ADDR; 145 | end 146 | end else begin 147 | // not for us, so go back to idle state 148 | state <= IDLE; 149 | end 150 | end else 151 | 152 | /* write phases */ 153 | if (state == WRITE_ADDR && scl_falling) 154 | begin 155 | // this is after a full byte has been received with SHIFT_IN 156 | // ack that we have received the address 157 | sda_enable <= 1; 158 | 159 | // store the write address 160 | data_addr <= shift_reg; 161 | 162 | // start shifting in a data byte 163 | state <= SHIFT_IN_ACK; 164 | next_state <= WRITE_DATA; 165 | end else 166 | if (state == WRITE_DATA && scl_falling) 167 | begin 168 | // this is after a full byte has been received 169 | // ack the we have received the byte 170 | // and write it to the address 171 | sda_enable <= 1; 172 | wr_strobe <= 1; 173 | end else 174 | if (state == WRITE_DATA && scl_rising) 175 | begin 176 | // our write ack is done, move to the next address 177 | // and start shifting in a new byte 178 | sda_enable <= 0; 179 | data_addr <= data_addr + 1; 180 | state <= SHIFT_IN; 181 | next_state <= WRITE_DATA; 182 | end else 183 | 184 | /* read phases */ 185 | if (state == READ_DATA && scl_falling) 186 | begin 187 | // shift out 8 bits on the *falling edge* so that 188 | // the data is stable during the high time 189 | sda_enable = ~shift_reg[7]; // 0 == pull down 190 | shift_reg <= { shift_reg[6:0], 1'b0 }; 191 | if (bit_counter == 7) 192 | state <= SHIFT_OUT_ACK; 193 | bit_counter <= bit_counter + 1; 194 | end else 195 | if (state == SHIFT_OUT_ACK && scl_falling) 196 | begin 197 | // let the controller send us a ~ACK / NAK on the 9th clock 198 | sda_enable <= 0; 199 | state <= READ_ACK; 200 | 201 | // start the read of the next byte 202 | data_addr <= data_addr + 1; 203 | end 204 | if (state == READ_ACK && scl_rising) 205 | begin 206 | if (sda) 207 | begin 208 | // they NAK'ed us, so we go back to idle 209 | state <= IDLE; 210 | end else begin 211 | // they want more. 212 | // the next byte should be ready now 213 | shift_reg <= rd_data; 214 | state <= READ_DATA; 215 | bit_counter <= 0; 216 | end 217 | end 218 | end 219 | endmodule 220 | -------------------------------------------------------------------------------- /verilog/mac.v: -------------------------------------------------------------------------------- 1 | /* 2 | * HDMI interface for a classic Mac 3 | * 4 | */ 5 | `default_nettype none 6 | `define WRANGLER_LED 7 | `define WRANGLER_SWITCH 8 | `include "top.v" 9 | `include "dither.v" 10 | 11 | module display( 12 | input clk_48mhz, 13 | input clk, // system clock, probably 12 or 24 Mhz 14 | input sw1, // user switch 15 | 16 | // Streaming HDMI interface (in 25 MHz hdmi_clk domain) 17 | input hdmi_clk, 18 | input hdmi_bit_clk, 19 | input hdmi_valid, 20 | output hdmi_reset, 21 | input vsync, 22 | input hsync, 23 | input rgb_valid, 24 | input [7:0] r, 25 | input [7:0] g, 26 | input [7:0] b, 27 | input [11:0] hdmi_xaddr, 28 | input [11:0] hdmi_yaddr, 29 | 30 | // GPIO banks for output 31 | output [7:0] gpio_bank_0, 32 | output [7:0] gpio_bank_1, 33 | 34 | // RGB led on the board with PWM 35 | output [7:0] led_r, 36 | output [7:0] led_g, 37 | output [7:0] led_b 38 | ); 39 | wire reset = 0; 40 | assign hdmi_reset = !sw1; 41 | 42 | // pulse the RGB led. shinputould do something with state here 43 | assign led_r = hdmi_reset ? 8'hFF : 8'h00; 44 | assign led_g = rgb_valid ? 8'h30 : 8'h00; 45 | assign led_b = hdmi_valid ? 8'h00 : 8'hf0; 46 | 47 | assign gpio_bank_1[3] = vsync; 48 | 49 | //wire [7:0] rate_r = 8'h0F; 50 | //wire [7:0] rate_g = 8'h1F; 51 | //wire [7:0] rate_b = 8'h3F; 52 | 53 | //breath breath_r(clk, rate_r, led_r); 54 | //breath breath_g(clk, rate_g, led_g); 55 | //breath breath_b(clk, rate_b, led_b); 56 | 57 | // produce a 16 MHz clock from the 48 Mhz clock 58 | wire clk_16mhz_raw; 59 | clk_div3 div3(clk_48mhz, reset, clk_16mhz_raw); 60 | 61 | // produce a 15.625 MHz from the HDMI clock (maybe) 62 | reg [2:0] clk_div; 63 | wire clk_15mhz = clk_div[2]; 64 | always @(posedge hdmi_bit_clk) 65 | clk_div <= clk_div + 1; 66 | 67 | //wire clk_16mhz = hdmi_valid ? clk_15mhz : clk_16mhz_raw; 68 | wire clk_16mhz = clk_16mhz_raw; 69 | 70 | /* 71 | wire [9:0] fb_xaddr; 72 | wire [8:0] fb_yaddr; 73 | reg [7:0] fb[0:1023]; 74 | initial $readmemh("apple-32.hex", fb); 75 | wire [9:0] fb_addr = { fb_yaddr[6:2], fb_xaddr[6:2] }; 76 | wire fb_data = fb[fb_addr] > 127; 77 | */ 78 | 79 | wire [15:0] mono_bits; 80 | wire [11:0] mono_xaddr; 81 | wire [11:0] mono_yaddr; 82 | wire mono_bits_ready; 83 | wire mono_vsync; 84 | 85 | hdmi_dither #( 86 | .X_OFFSET(64), 87 | .Y_OFFSET(128) 88 | ) dither( 89 | .hdmi_clk(hdmi_clk), 90 | .hdmi_valid(hdmi_valid && rgb_valid), 91 | .hdmi_vsync(vsync), 92 | .hdmi_xaddr(hdmi_xaddr), 93 | .hdmi_yaddr(hdmi_yaddr), 94 | .hdmi_r(r), 95 | .hdmi_g(g), 96 | .hdmi_b(b), 97 | 98 | .mono_clk(clk_16mhz), 99 | .mono_bits(mono_bits), 100 | .mono_xaddr(mono_xaddr), 101 | .mono_yaddr(mono_yaddr), 102 | .mono_bits_ready(mono_bits_ready), 103 | .mono_vsync(mono_vsync) 104 | ); 105 | 106 | reg [9:0] fb_xaddr; 107 | reg [8:0] fb_yaddr; 108 | reg [15:0] fb_bits; 109 | 110 | reg [13:0] rd_addr; 111 | //reg video_bit; 112 | 113 | reg mono_bits_ready_delay = 0; 114 | 115 | //wire reader_active = fb_xaddr[3:0] == 4'b1111; 116 | reg reader_active; 117 | 118 | // xaddr bottom 4 bits are all zero since there are 16-bits 119 | // returned at a time. xaddr only goes to 511 120 | wire [13:0] wd_addr = { mono_yaddr[8:0], mono_xaddr[8:4] }; 121 | 122 | reg fb_wen; 123 | 124 | // every 16 pixels cache the next 16 pixels worth of data 125 | wire [15:0] rd_data; 126 | 127 | // video comes from the read buffer on the clock immediately 128 | // after a read, otherwise it comes from the shift register 129 | wire video_bit = last_read_active ? rd_data[15] : fb_bits[15]; 130 | 131 | reg last_read_active; 132 | always @(posedge clk_16mhz) 133 | begin 134 | fb_wen <= 0; 135 | last_read_active <= 0; 136 | mono_bits_ready_delay <= 0; 137 | 138 | if (fb_xaddr[3:0] == 4'b0000) begin 139 | // need to read a new set of pixels 140 | last_read_active <= 1; 141 | rd_addr <= { fb_yaddr[8:0], fb_xaddr[8:4] }; 142 | 143 | // delay any writes that might be happening 144 | // since reading from the frame buffer has 145 | // real-time priority 146 | mono_bits_ready_delay <= mono_bits_ready; 147 | end else begin 148 | // allow any writes or delayed writes to happen 149 | // when they are in the active part of the display 150 | // mono_bits_ready is only set if we're in the window 151 | fb_wen <= mono_bits_ready || mono_bits_ready_delay; 152 | end 153 | 154 | // refresh the buffer from the read or shift the buffer 155 | if (last_read_active) 156 | fb_bits[15:0] <= { rd_data[14:0], 1'b0 }; 157 | else 158 | fb_bits[15:0] <= { fb_bits[14:0], 1'b0 }; 159 | end 160 | 161 | 162 | // 512x512x1 fits in a single ice40up5k SPRAM 163 | spram_32k framebuffer( 164 | .clk(clk_16mhz), 165 | .wen(fb_wen), 166 | .wr_addr(wd_addr), 167 | .wr_data(mono_bits), 168 | .rd_addr(rd_addr), 169 | .rd_data(rd_data) 170 | ); 171 | 172 | mac_display crt( 173 | .clk_16mhz(clk_16mhz), 174 | .reset(reset), 175 | .hsync(gpio_bank_1[1]), 176 | .vsync(gpio_bank_1[2]), 177 | .out(gpio_bank_1[0]), 178 | .xaddr(fb_xaddr), 179 | .yaddr(fb_yaddr), 180 | .fb_data(video_bit) 181 | ); 182 | 183 | 184 | endmodule 185 | 186 | 187 | module mac_display( 188 | input reset, 189 | input clk_16mhz, 190 | output [9:0] xaddr, 191 | output [8:0] yaddr, 192 | input fb_data, 193 | output vsync, 194 | output hsync, 195 | output out 196 | ); 197 | parameter ACTIVE_WIDTH = 512; 198 | parameter ACTIVE_HEIGHT = 342; 199 | parameter ACTIVE_XOFFSET = 192; 200 | parameter ACTIVE_YOFFSET = 48; 201 | 202 | parameter TOTAL_WIDTH = 720; 203 | parameter TOTAL_HEIGHT = ACTIVE_HEIGHT + ACTIVE_YOFFSET + 1; //384; 204 | parameter VSYNC_LINES = 6; // how many hsyncs during vsync low 205 | parameter VSYNC_OFFSET = 128; // edge of vsync relative to hsync 206 | parameter HSYNC_OFFSET = 294; // rising edge of the hsync line 207 | 208 | reg hsync; 209 | reg vsync; 210 | reg out; 211 | 212 | reg [9:0] xscan; 213 | reg [8:0] yscan; 214 | wire [9:0] xaddr = xscan - ACTIVE_XOFFSET; 215 | wire [8:0] yaddr = yscan - ACTIVE_YOFFSET; 216 | 217 | // note that the "in active window" triggers one pixel 218 | // *after* xscan enters it, since xaddr is a request for 219 | // a pixel and it takes one clock for the framebuffer to be ready 220 | wire in_active_window = 1 221 | && ACTIVE_XOFFSET < xscan 222 | && xscan <= ACTIVE_XOFFSET + ACTIVE_WIDTH 223 | && ACTIVE_YOFFSET < yscan 224 | && yscan <= ACTIVE_YOFFSET + ACTIVE_HEIGHT; 225 | 226 | always @(posedge clk_16mhz) 227 | if (reset) 228 | begin 229 | xscan <= 0; 230 | yscan <= 0; 231 | vsync <= 1; 232 | hsync <= 1; 233 | end else begin 234 | // 45 usec per hsync * 16 MHz == 720 total X addresses 235 | // = 180 hsync + 512 active + 28? 236 | // vsync offset from hsync 237 | xscan <= xscan + 1; 238 | if (xscan == TOTAL_WIDTH-1) 239 | begin 240 | xscan <= 0; 241 | 242 | if (yscan == TOTAL_HEIGHT-1) 243 | yscan <= 0; 244 | else 245 | yscan <= yscan + 1; 246 | end 247 | 248 | if (yscan == 0 && xscan == VSYNC_OFFSET) 249 | vsync <= 0; 250 | else 251 | if (yscan == VSYNC_LINES && xscan == VSYNC_OFFSET) 252 | vsync <= 1; 253 | 254 | if (xscan == 0) 255 | hsync <= 0; 256 | else 257 | if (xscan == HSYNC_OFFSET) 258 | hsync <= 1; 259 | 260 | if (in_active_window) 261 | out <= ~fb_data; 262 | else 263 | out <= 1; // idle high 264 | end 265 | endmodule 266 | -------------------------------------------------------------------------------- /verilog/mem.v: -------------------------------------------------------------------------------- 1 | /* Ensure RAM-like behaviour */ 2 | module ram( 3 | // read domain 4 | input rd_clk, 5 | input [ADDR_WIDTH-1:0] rd_addr, 6 | output [DATA_WIDTH-1:0] rd_data, 7 | // write domain 8 | input wr_clk, 9 | input wr_enable, 10 | input [ADDR_WIDTH-1:0] wr_addr, 11 | input [DATA_WIDTH-1:0] wr_data, 12 | ); 13 | parameter ADDR_WIDTH=8; 14 | parameter DATA_WIDTH=8; 15 | parameter NUM_WORDS = 1 << ADDR_WIDTH; 16 | 17 | reg [DATA_WIDTH-1:0] mem[0:NUM_WORDS-1]; 18 | reg [DATA_WIDTH-1:0] rd_data; 19 | 20 | //initial $readmemh("packed0.hex", mem); 21 | initial $readmemh("fb-init.hex", mem); 22 | 23 | always @(posedge rd_clk) 24 | rd_data <= mem[rd_addr]; 25 | //assign rd_data = mem[rd_addr]; 26 | 27 | always @(posedge wr_clk) 28 | if (wr_enable) 29 | mem[wr_addr] <= wr_data; 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /verilog/pixelwrangler_v0.pcf: -------------------------------------------------------------------------------- 1 | # The LED pins are using the current controlled outputs 2 | # and are negative logic (write a 0 to turn on). 3 | set_io -nowarn led_r 41 4 | set_io -nowarn led_g 39 5 | set_io -nowarn led_b 40 6 | 7 | set_io -nowarn spi_cs 16 # Drive high to ensure that the SPI flash is disabled 8 | set_io -nowarn spi_sck 15 9 | set_io -nowarn spi_mosi 14 10 | set_io -nowarn spi_msio 17 11 | 12 | set_io -nowarn pin_usbp 4 # IOB_8A 13 | set_io -nowarn pin_usbn 3 # IOB_9B 14 | set_io -nowarn pin_usb_pu 6 # IOB_13B 15 | 16 | set_io -nowarn sw1 2 # IOB_6A 17 | 18 | # HDMI input 19 | set_io -nowarn tmds_d0p 25 # IOT_36B; needs inversion 20 | set_io -nowarn tmds_d0n 23 # IOT_37A 21 | set_io -nowarn tmds_d1p 27 # IOT_38B; needs inversion 22 | set_io -nowarn tmds_d1n 26 # IOT_39A 23 | set_io -nowarn tmds_d2p 32 # IOT_43A 24 | set_io -nowarn tmds_d2n 31 # IOT_42B 25 | set_io -nowarn tmds_clkp 37 # IOT_45A_G1 26 | set_io -nowarn tmds_clkn 34 # IOT_44b 27 | set_io -nowarn hdmi_sda 35 # IOT_46B_G0 28 | set_io -nowarn hdmi_scl 36 # IOT_48b 29 | 30 | # GPIO bank 0, bottom side 31 | set_io -nowarn gpio_0_0 10 # IOB_18A 32 | set_io -nowarn gpio_0_1 11 # IOB_20A 33 | set_io -nowarn gpio_0_2 12 # IOB_22A 34 | set_io -nowarn gpio_0_3 13 # IOB_24A 35 | set_io -nowarn gpio_0_4 18 # IOB_31B 36 | set_io -nowarn gpio_0_5 19 # IOB_29B 37 | set_io -nowarn gpio_0_6 20 # IOB_25B_G 38 | set_io -nowarn gpio_0_7 21 # IOB_23B 39 | 40 | # GPIO bank 1, top side 41 | set_io -nowarn gpio_1_0 48 # IOB_4A 42 | set_io -nowarn gpio_1_1 47 # IOB_2A 43 | set_io -nowarn gpio_1_2 46 # IOB_0A 44 | set_io -nowarn gpio_1_3 45 # IOB_5B 45 | set_io -nowarn gpio_1_4 44 # IOB_3B_G6 46 | set_io -nowarn gpio_1_5 43 # IOB_49A 47 | set_io -nowarn gpio_1_6 42 # IOB_51A 48 | set_io -nowarn gpio_1_7 38 # IOB_50B 49 | -------------------------------------------------------------------------------- /verilog/pwm.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Logarithmic response curve for an LED. 3 | * Turns an 8-bit value into something that 4 | * looks linear for the LEDs. 5 | */ 6 | `ifndef _pwm_v_ 7 | `define _pwm_v_ 8 | 9 | module pwm_map8( 10 | input clk, 11 | input [7:0] in, 12 | output [10:0] out 13 | ); 14 | reg [10:0] out; 15 | 16 | always @(posedge clk) 17 | if (in[7:7] == 7'b1111111) out <= 11'h7FF; else 18 | if (in[7:6] == 6'b111111) out <= 11'h5c0 + (in[1:0] << 7); else 19 | if (in[7:5] == 5'b11111) out <= 11'h4c0 + (in[2:0] << 6); else 20 | if (in[7:4] == 4'b1111) out <= 11'h3C0 + (in[3:0] << 5); else 21 | if (in[7:5] == 3'b111) out <= 11'h2C0 + (in[4:0] << 4); else 22 | if (in[7:6] == 2'b11) out <= 11'h1C0 + (in[5:0] << 3); else 23 | if (in[7:7] == 1'b1) out <= 11'h0C0 + (in[6:0] << 2); else 24 | if (in[7:6] == 1'b01) out <= 11'h040 + (in[5:0] << 1); else 25 | out <= in[5:0]; 26 | endmodule 27 | 28 | module breath( 29 | input clk, 30 | input [7:0] rate, 31 | output [7:0] bright 32 | ); 33 | parameter INVERT = 0; 34 | 35 | reg [20:0] counter = 0; 36 | reg [8:0] tick = 0; 37 | reg [7:0] bright = 0; 38 | 39 | always @(posedge clk) 40 | begin 41 | if (counter[20:13] > rate) 42 | begin 43 | counter <= 0; 44 | tick <= tick + 1; 45 | end else 46 | counter <= counter + 1; 47 | 48 | // bright up from 0-255 and down from 256-511 49 | if (tick < 256) 50 | bright <= tick; 51 | else 52 | bright <= 511 - tick; 53 | end 54 | endmodule 55 | 56 | 57 | /* 58 | * Use this instead of driving the RGB led directly 59 | * to avoid over-volting the red LED. 60 | * 61 | * The 8-bit input is expanded to a 11-bit exponential scale 62 | * so that the LED feels more linear across the range. 63 | */ 64 | module rgb_drv( 65 | input clk, 66 | input enable, 67 | input [7:0] bright_r, 68 | input [7:0] bright_g, 69 | input [7:0] bright_b, 70 | output [2:0] out 71 | ); 72 | wire [10:0] exp_r; 73 | wire [10:0] exp_g; 74 | wire [10:0] exp_b; 75 | pwm_map8 map_r(clk, bright_r, exp_r); 76 | pwm_map8 map_b(clk, bright_b, exp_b); 77 | pwm_map8 map_g(clk, bright_g, exp_g); 78 | 79 | reg [2:0] out; 80 | reg [2:0] pwm; 81 | reg [10:0] counter = 0; 82 | 83 | always @(posedge clk) 84 | begin 85 | counter <= counter + 1; 86 | pwm[0] <= counter < exp_r; 87 | pwm[1] <= counter < exp_g; 88 | pwm[2] <= counter < exp_b; 89 | end 90 | 91 | /* ice40up5k doesn't have SB_LED_DRV_CUR? 92 | wire ledpu; 93 | SB_LED_DRV_CUR ledpu_drv( 94 | .EN(enable), 95 | .LEDPU(ledpu) 96 | ); 97 | */ 98 | SB_RGBA_DRV #( 99 | // upduino board has the pins in the order GRB 100 | .RGB1_CURRENT("0b000011"), // 8mA: red needs barely any 101 | .RGB0_CURRENT("0b001111"), // 16mA: green needs some 102 | .RGB2_CURRENT("0b111111") // 24mA: blue is a thirsty boy 103 | ) RGB_DRV( 104 | .RGBLEDEN(enable), 105 | .CURREN(1'b1), 106 | .RGB0PWM(pwm[1]), // g 107 | .RGB1PWM(pwm[2]), // r 108 | .RGB2PWM(pwm[0]), // b 109 | // these are ignored? the connections are hard wired 110 | .RGB0(out[0]), 111 | .RGB1(out[1]), 112 | .RGB2(out[2]) 113 | ); 114 | endmodule 115 | 116 | `endif 117 | -------------------------------------------------------------------------------- /verilog/tmds.v: -------------------------------------------------------------------------------- 1 | /* TMDS interface and decoder. 2 | * 3 | * Instantiate a tmds_decoder with the four differential pairs 4 | * as inputs and receives as outputs the pixel clock, three data 5 | * channels, and video sync signals. 6 | * 7 | * Optionally there is a locked signal for when the video is 8 | * detected and the 10X (or 5X with DDR) bit clock. 9 | * 10 | * Audio and other TERC4 data is not yet handled. 11 | */ 12 | 13 | /* 14 | * Decode the TMDS and TERC4 encoded data in the HDMI stream. 15 | * This processes pixels in the HDMI TMDS clock domain. 16 | * 17 | * Only Channel 0 (Blue) has the synchronization bits and the 18 | * TERC4 data during the data island period. 19 | */ 20 | `include "hdmi_pll_ddr.v" 21 | `include "dpram.v" 22 | 23 | module tmds_8b10b_decoder( 24 | input hdmi_clk, 25 | input [9:0] in, 26 | output data_valid, 27 | output sync_valid, 28 | output ctrl_valid, 29 | output [7:0] data, 30 | output [1:0] sync, // hsync/vsync 31 | output [3:0] ctrl // audio header? 32 | ); 33 | // the sync control bits are encoded with four specific patterns 34 | parameter CTRL_00 = 10'b1101010100; // 354 35 | parameter CTRL_01 = 10'b0010101011; // 0AB 36 | parameter CTRL_10 = 10'b0101010100; // 154 37 | parameter CTRL_11 = 10'b1010101011; // 2AB 38 | 39 | // the control channel data 40 | parameter TERC4_0 = 10'b1010011100; 41 | parameter TERC4_1 = 10'b1001100011; 42 | parameter TERC4_2 = 10'b1011100100; 43 | parameter TERC4_3 = 10'b1011100010; 44 | parameter TERC4_4 = 10'b0101110001; 45 | parameter TERC4_5 = 10'b0100011110; 46 | parameter TERC4_6 = 10'b0110001110; 47 | parameter TERC4_7 = 10'b0100111100; 48 | parameter TERC4_8 = 10'b1011001100; 49 | parameter TERC4_9 = 10'b0100111001; 50 | parameter TERC4_A = 10'b0110011100; 51 | parameter TERC4_B = 10'b1011000110; 52 | parameter TERC4_C = 10'b1010001110; 53 | parameter TERC4_D = 10'b1001110001; 54 | parameter TERC4_E = 10'b0101100011; 55 | parameter TERC4_F = 10'b1011000011; 56 | 57 | // first two of the 10 bits encodes the how the other bits 58 | // are encoded (either inverted and either xor or xnor) 59 | // see page 83 of HDMI 1.3 spec 60 | wire invert = in[9]; 61 | wire use_xor = in[8]; 62 | 63 | wire [7:0] in_bits = invert ? ~in[7:0] : in; 64 | wire [7:0] in_xor = { in_bits[6:0] ^ in_bits[7:1], in_bits[0] }; 65 | wire [7:0] in_xnor = { in_bits[6:0] ^~ in_bits[7:1], in_bits[0] }; 66 | wire [7:0] data_out = use_xor ? in_xor : in_xnor; 67 | 68 | reg data_valid; 69 | reg sync_valid; 70 | reg ctrl_valid; 71 | reg [7:0] data; 72 | reg [1:0] sync; 73 | reg [3:0] ctrl; 74 | 75 | always @(posedge hdmi_clk) 76 | begin 77 | sync_valid <= 0; 78 | ctrl_valid <= 0; 79 | data_valid <= 0; 80 | 81 | data <= data_out; 82 | 83 | case(in) 84 | CTRL_00: { sync_valid, sync } = { 1'b1, 2'b00 }; 85 | CTRL_01: { sync_valid, sync } = { 1'b1, 2'b01 }; 86 | CTRL_10: { sync_valid, sync } = { 1'b1, 2'b10 }; 87 | CTRL_11: { sync_valid, sync } = { 1'b1, 2'b11 }; 88 | 89 | TERC4_0: { ctrl_valid, ctrl } = { 1'b1, 4'h0 }; 90 | TERC4_1: { ctrl_valid, ctrl } = { 1'b1, 4'h1 }; 91 | TERC4_2: { ctrl_valid, ctrl } = { 1'b1, 4'h2 }; 92 | TERC4_3: { ctrl_valid, ctrl } = { 1'b1, 4'h3 }; 93 | TERC4_4: { ctrl_valid, ctrl } = { 1'b1, 4'h4 }; 94 | TERC4_5: { ctrl_valid, ctrl } = { 1'b1, 4'h5 }; 95 | TERC4_6: { ctrl_valid, ctrl } = { 1'b1, 4'h6 }; 96 | TERC4_7: { ctrl_valid, ctrl } = { 1'b1, 4'h7 }; 97 | TERC4_8: { ctrl_valid, ctrl } = { 1'b1, 4'h8 }; 98 | TERC4_9: { ctrl_valid, ctrl } = { 1'b1, 4'h9 }; 99 | TERC4_A: { ctrl_valid, ctrl } = { 1'b1, 4'hA }; 100 | TERC4_B: { ctrl_valid, ctrl } = { 1'b1, 4'hB }; 101 | TERC4_C: { ctrl_valid, ctrl } = { 1'b1, 4'hC }; 102 | TERC4_D: { ctrl_valid, ctrl } = { 1'b1, 4'hD }; 103 | TERC4_E: { ctrl_valid, ctrl } = { 1'b1, 4'hE }; 104 | TERC4_F: { ctrl_valid, ctrl } = { 1'b1, 4'hF }; 105 | 106 | default: 107 | data_valid <= 1; 108 | endcase 109 | /* 110 | if (in == CTRL_00) { sync_valid, sync } = { 1'b1, 2'b00 }; else 111 | if (in == CTRL_01) { sync_valid, sync } = { 1'b1, 2'b01 }; else 112 | if (in == CTRL_10) { sync_valid, sync } = { 1'b1, 2'b10 }; else 113 | if (in == CTRL_11) { sync_valid, sync } = { 1'b1, 2'b11 }; else 114 | data_valid <= 1; 115 | */ 116 | end 117 | endmodule 118 | 119 | 120 | /* 121 | * Inverting differential input with latches. 122 | */ 123 | module lvds_ddr_input( 124 | input clk, 125 | input in_p, 126 | output [1:0] out 127 | ); 128 | reg [1:0] out; 129 | wire [1:0] in; 130 | 131 | SB_IO #( 132 | .PIN_TYPE(6'b000000), 133 | .IO_STANDARD("SB_LVDS_INPUT") 134 | ) diff_io ( 135 | .PACKAGE_PIN(in_p), 136 | .INPUT_CLK(clk), 137 | .D_IN_0(in[0]), // pos edge of bit_clk 138 | .D_IN_1(in[1]) // neg edge of bit_clk 139 | ); 140 | 141 | // invert both of them so that there is a constant delay 142 | // between the inputs and the latches. also seems to 143 | // produce a better timing result, so leave it in? 144 | always @(posedge clk) 145 | out[0] <= ~in[0]; 146 | always @(negedge clk) 147 | out[1] <= ~in[1]; 148 | 149 | endmodule 150 | 151 | 152 | /* 153 | * Deserialize 10 input bits into a 10-bit register. 154 | * 155 | * This uses a LVDS DDR input to capture two bits per clock, 156 | * using a 5x PLL off the HDMI clock. To transfer them to 157 | * the HDMI clock domain, it uses a dual port block ram 158 | * configured with a 2-bit write port and 16-bit read port. 159 | * This allows individual bits to be written, and then 160 | * an entire 10-bit tmds word to be read. 161 | * 162 | * To avoid overwriting the one that the HDMI clock domain 163 | * is reading, it alternates between address 0 and 1 in 164 | * the 16-bit address space. 165 | * 166 | * TODO: move write address stuff to outside 167 | */ 168 | module tmds_shift_register_ddr( 169 | input reset, 170 | input hdmi_clk, 171 | input bit_clk, 172 | input in_p, 173 | output [BITS-1:0] out 174 | ); 175 | parameter BITS = 10; 176 | parameter LOCATION = ""; 177 | wire [1:0] in_raw; 178 | wire [15:0] rd_data; 179 | 180 | // extract just the low-order bits from the 16 181 | assign out = rd_data[9:0]; 182 | 183 | reg [2:0] wr_addr = 0; 184 | reg rd_addr = 0; 185 | 186 | lvds_ddr_input lvds( 187 | .clk(bit_clk), 188 | .in_p(in_p), 189 | .out(in_raw) 190 | ); 191 | 192 | always @(posedge bit_clk) 193 | begin 194 | if (reset) 195 | begin 196 | wr_addr <= 0; 197 | end else 198 | if (wr_addr == 3'h4) 199 | begin 200 | wr_addr <= 0; 201 | rd_addr <= ~rd_addr; 202 | end else 203 | wr_addr <= wr_addr + 1; 204 | end 205 | 206 | dpram_2x16 #( 207 | .LOCATION(LOCATION) 208 | ) dpram_buf( 209 | .wr_clk(bit_clk), 210 | .wr_addr({7'b0, ~rd_addr, wr_addr}), 211 | .wr_data(in_raw), 212 | .wr_enable(1'b1), 213 | .rd_clk(hdmi_clk), 214 | .rd_data(rd_data), 215 | .rd_addr({7'h00, rd_addr}) 216 | ); 217 | endmodule 218 | 219 | // detect a control message in the shift register and use it 220 | // to resync our bit clock offset from the pixel clock. 221 | // tracks if our clock is still in sync with the old values 222 | module tmds_sync_recognizer( 223 | input reset, 224 | input hdmi_clk, 225 | input [9:0] in, 226 | output valid, 227 | output [2:0] phase 228 | ); 229 | //parameter CTRL_00 = 10'b1101010100; // 354 230 | //parameter CTRL_01 = 10'b0010101011; // 0AB 231 | //parameter CTRL_10 = 10'b0101010100; // 154 232 | parameter CTRL_11 = 10'b1010101011; // 2AB 233 | parameter DELAY_BITS = 24; 234 | 235 | reg valid = 0; 236 | reg [2:0] phase = 0; 237 | reg [DELAY_BITS:0] counter; 238 | 239 | always @(posedge reset or posedge hdmi_clk) 240 | begin 241 | if (reset) 242 | begin 243 | counter <= 0; 244 | valid <= 0; 245 | end else 246 | if (in == CTRL_11) 247 | begin 248 | // we have a good control word! 249 | valid <= 1; 250 | counter <= 0; 251 | end else 252 | if (counter[DELAY_BITS]) 253 | begin 254 | // no recent control word! adjust the phase 255 | if (phase == 4'h4) 256 | phase <= 0; 257 | else 258 | phase <= phase + 1; 259 | 260 | valid <= 0; 261 | counter <= 0; 262 | end else begin 263 | // keep counting until we have another valid signal 264 | counter <= counter + 1; 265 | end 266 | end 267 | endmodule 268 | 269 | 270 | module tmds_clk_pll( 271 | input reset, 272 | input clk_p, 273 | output hdmi_clk, 274 | output bit_clk, 275 | output locked 276 | ); 277 | SB_GB_IO #( 278 | .PIN_TYPE(6'b000000), 279 | .IO_STANDARD("SB_LVDS_INPUT") 280 | ) differential_clock_input ( 281 | .PACKAGE_PIN(clk_p), 282 | .GLOBAL_BUFFER_OUTPUT(hdmi_clk) 283 | ); 284 | 285 | hdmi_pll pll( 286 | .clock_in(hdmi_clk), 287 | .clock_out(bit_clk), 288 | .locked(locked), 289 | .reset(reset) 290 | ); 291 | endmodule 292 | 293 | 294 | // Synchronize the three channels with the TMDS clock and unknown phase 295 | // of the bits. Returns the raw 8b10b encoded values for futher processing 296 | // and a TMDS synchronize clock for the data stream. The data are only valid 297 | // when locked 298 | module tmds_raw_decoder( 299 | input reset, 300 | 301 | input d0_p, 302 | input d1_p, 303 | input d2_p, 304 | input clk_p, 305 | 306 | // d0,d1,d2 are in clk domain 307 | output [9:0] d0, 308 | output [9:0] d1, 309 | output [9:0] d2, 310 | output valid, // good pixel data 311 | output locked, // only timing data 312 | output hdmi_clk, 313 | output bit_clk 314 | ); 315 | parameter INVERT = 3'b000; 316 | wire hdmi_clk; // 25 MHz decoded from TDMS input 317 | wire bit_clk; // 250 MHz PLL'ed from TMDS clock (or 125 MHz if DDR) 318 | reg pixel_strobe, pixel_valid; // when new pixels are detected by the synchronizer 319 | wire hdmi_locked; 320 | assign locked = hdmi_locked; 321 | reg valid; 322 | 323 | tmds_clk_pll tmds_clk_pll_i( 324 | .reset(reset), 325 | .clk_p(clk_p), 326 | .hdmi_clk(hdmi_clk), 327 | .bit_clk(bit_clk), 328 | .locked(hdmi_locked) 329 | ); 330 | 331 | // hdmi_clk domain 332 | wire [9:0] d0_data; 333 | wire [9:0] d1_data; 334 | wire [9:0] d2_data; 335 | 336 | reg [9:0] d0; 337 | reg [9:0] d1; 338 | reg [9:0] d2; 339 | always @(posedge hdmi_clk) 340 | begin 341 | d0 <= INVERT[0] ? d0_data : ~d0_data; 342 | d1 <= INVERT[1] ? d1_data : ~d1_data; 343 | d2 <= INVERT[2] ? d2_data : ~d2_data; 344 | end 345 | 346 | // this is a bit of a hack to put the block rams right 347 | // next to the inputs for the tmds signals. otherwise 348 | // the timing gets really bad, depending on the seed etc 349 | // these also output in the hdmi_clk domain, so no 350 | // clock crossing is required 351 | 352 | // Info: constrained 'tmds_d0n' to bel 'X19/Y31/io0' 353 | tmds_shift_register_ddr #( 354 | .LOCATION("X19/Y25/ram") 355 | ) d0_shift( 356 | .reset(reset), 357 | .hdmi_clk(hdmi_clk), 358 | .bit_clk(bit_clk), 359 | .in_p(d0_p), 360 | .out(d0_data) 361 | ); 362 | 363 | // Info: constrained 'tmds_d1n' to bel 'X18/Y31/io0' 364 | tmds_shift_register_ddr #( 365 | .LOCATION("X19/Y29/ram") 366 | ) d1_shift( 367 | .reset(reset), 368 | .hdmi_clk(hdmi_clk), 369 | .bit_clk(bit_clk), 370 | .in_p(d1_p), 371 | .out(d1_data) 372 | ); 373 | 374 | // Info: constrained 'tmds_d2p' to bel 'X16/Y31/io0' 375 | tmds_shift_register_ddr #( 376 | .LOCATION("X19/Y27/ram") 377 | ) d2_shift( 378 | .reset(reset), 379 | .hdmi_clk(hdmi_clk), 380 | .bit_clk(bit_clk), 381 | .in_p(d2_p), 382 | .out(d2_data) 383 | ); 384 | 385 | /* 386 | reg [9:0] d0_data, d1_data, d2_data; 387 | always @(posedge hdmi_clk) 388 | begin 389 | d0_data <= d0_wire; 390 | d1_data <= d1_wire; 391 | d2_data <= d2_wire; 392 | end 393 | */ 394 | 395 | // detect the pixel clock from the PLL'ed bit_clk 396 | // only channel 0 carries the special command words 397 | // with DDR we only count up to 5 so three bits is enough 398 | wire [2:0] phase; 399 | 400 | tmds_sync_recognizer d0_sync_recognizer( 401 | .reset(reset), 402 | .hdmi_clk(hdmi_clk), 403 | .in(d0), 404 | .phase(phase), 405 | .valid(pixel_valid) 406 | ); 407 | 408 | always @(posedge hdmi_clk) 409 | begin 410 | valid <= hdmi_locked && pixel_valid; 411 | valid <= pixel_valid; 412 | end 413 | endmodule 414 | 415 | module tmds_decoder( 416 | input reset, 417 | 418 | // the differential pair inputs only take the positive pin 419 | // otherwise nextpnr gets upset! 420 | input clk_p, 421 | input d0_p, 422 | input d1_p, 423 | input d2_p, 424 | 425 | // hdmi pixel clock and PLL'ed bit clock 426 | output hdmi_clk, 427 | output bit_clk, 428 | 429 | // clock sync and data decode is good 430 | output hdmi_locked, // good clock 431 | output hdmi_valid, // good sync 432 | 433 | // data valid should be based on sync pulses, so ignore it for now 434 | output data_valid, 435 | output [7:0] d0, 436 | output [7:0] d1, 437 | output [7:0] d2, 438 | 439 | // these hold value so sync_valid is not necessary 440 | output sync_valid, 441 | output [1:0] sync, 442 | 443 | // terc4 data is not used yet 444 | output ctrl_valid, 445 | output [3:0] ctrl 446 | ); 447 | parameter [2:0] INVERT = 3'b000; 448 | 449 | wire [9:0] tmds_d0; 450 | wire [9:0] tmds_d1; 451 | wire [9:0] tmds_d2; 452 | wire hdmi_clk; // hdmi pixel clock domain, sync'ed to the TMDS clock 453 | wire bit_clk; // PLL'ed from the pixel clock 454 | 455 | wire hdmi_locked; // good clock? 456 | wire hdmi_valid; // good decode? 457 | 458 | tmds_raw_decoder #(.INVERT(INVERT)) 459 | tmds_raw_i( 460 | .reset(reset), 461 | 462 | // physical inputs 463 | .clk_p(clk_p), 464 | .d0_p(d0_p), 465 | .d1_p(d1_p), 466 | .d2_p(d2_p), 467 | 468 | // outputs 469 | .hdmi_clk(hdmi_clk), 470 | .bit_clk(bit_clk), 471 | .locked(hdmi_locked), 472 | .valid(hdmi_valid), 473 | .d0(tmds_d0), 474 | .d1(tmds_d1), 475 | .d2(tmds_d2), 476 | ); 477 | 478 | tmds_8b10b_decoder d0_decoder( 479 | .hdmi_clk(hdmi_clk), 480 | .in(tmds_d0), 481 | .data(d0), 482 | .sync(sync), 483 | .ctrl(ctrl), 484 | .data_valid(data_valid), 485 | .sync_valid(sync_valid), 486 | .ctrl_valid(ctrl_valid), 487 | ); 488 | 489 | // audio data is on d1 and d2, but we don't handle it yet 490 | tmds_8b10b_decoder d1_decoder( 491 | .hdmi_clk(hdmi_clk), 492 | .in(tmds_d1), 493 | .data(d1), 494 | ); 495 | 496 | tmds_8b10b_decoder d2_decoder( 497 | .hdmi_clk(hdmi_clk), 498 | .in(tmds_d2), 499 | .data(d2), 500 | ); 501 | endmodule 502 | -------------------------------------------------------------------------------- /verilog/top.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Top-level interface for the Pixel Wrangler 3 | * 4 | * You should define a module display and include 5 | * this file to do all of the hardware setup. 6 | */ 7 | `default_nettype none 8 | `include "tmds.v" 9 | `include "hdmi.v" 10 | `include "uart.v" 11 | `include "i2c.v" 12 | `include "pwm.v" 13 | `include "util.v" 14 | 15 | `ifndef WRANGLER_NO_HDMI 16 | `define WRANGLER_HDMI 17 | `endif 18 | `ifndef WRANGLER_NO_GPIO 19 | `define WRANGLER_GPIO 20 | `endif 21 | 22 | `ifdef WRANGLER_UART_TX 23 | `define WRANGLER_UART 24 | `endif 25 | 26 | /* 27 | * You do not need to instantiate all of these interfaces! 28 | * These are the ones that are provided by the top module 29 | * and wrap the underlying HDMI decoder, USB port and gpio pins. 30 | */ 31 | /* 32 | module display( 33 | input clk_48mhz, 34 | input clk, // system clock, probably 12 or 24 Mhz 35 | 36 | // Streaming HDMI interface (in 25 MHz hdmi_clk domain) 37 | input hdmi_clk, 38 | input hdmi_valid, 39 | input vsync, 40 | input hsync, 41 | input rgb_valid, 42 | input [7:0] r, 43 | input [7:0] g, 44 | input [7:0] b, 45 | input [11:0] xaddr, 46 | input [11:0] yaddr, 47 | 48 | // GPIO banks for output 49 | output [7:0] gpio_bank_0, 50 | output [7:0] gpio_bank_1, 51 | 52 | // USB interface tristate 53 | output usb_pullup, 54 | output usb_out_enable, 55 | output [1:0] usb_out, 56 | input [1:0] usb_in, 57 | 58 | input uart_txd_ready, 59 | output uart_txd_strobe, 60 | output [7:0] uart_txd, 61 | input uart_rxd_strobe, 62 | input [7:0] uart_rxd, 63 | 64 | // user switch 65 | input sw1, 66 | 67 | // RGB led on the board with PWM 68 | output [7:0] led_r, 69 | output [7:0] led_g, 70 | output [7:0] led_b, 71 | 72 | // SPI flash (be careful not to overwrite the boot loader!) 73 | output spi_cs, 74 | output spi_clk, 75 | output spi_do, 76 | input spi_di 77 | ); 78 | */ 79 | 80 | module top( 81 | output spi_cs, 82 | output led_r, 83 | output led_g, 84 | output led_b, 85 | 86 | //inout hdmi_sda, // OOPS conflicts with tmds clk 87 | input hdmi_scl, 88 | 89 | input tmds_d0n, // need to invert 90 | input tmds_d1n, // need to invert 91 | input tmds_d2p, 92 | input tmds_clkp, 93 | 94 | output gpio_0_0, 95 | output gpio_0_1, 96 | output gpio_0_2, 97 | output gpio_0_3, 98 | output gpio_0_4, 99 | output gpio_0_5, 100 | output gpio_0_6, 101 | //output gpio_0_7, 102 | inout gpio_0_7, // temporarily bodged to hdmi_sda 103 | 104 | output gpio_1_0, 105 | output gpio_1_1, 106 | output gpio_1_2, 107 | output gpio_1_3, 108 | output gpio_1_4, 109 | output gpio_1_5, 110 | output gpio_1_6, 111 | output gpio_1_7, 112 | 113 | input sw1 114 | ); 115 | assign spi_cs = 1; // it is necessary to turn off the SPI flash chip 116 | //reg led_r, led_g, led_b; 117 | 118 | reg reset = 0; 119 | wire clk_48mhz; 120 | SB_HFOSC inthosc(.CLKHFPU(1'b1), .CLKHFEN(1'b1), .CLKHF(clk_48mhz)); 121 | 122 | reg [3:0] clk_div; 123 | wire clk = clk_div[2]; 124 | always @(posedge clk_48mhz) 125 | clk_div <= clk_div + 1; 126 | 127 | wire hdmi_clk; 128 | wire hdmi_locked; 129 | reg valid; 130 | 131 | `ifdef WRANGLER_LED 132 | /* 133 | * builtin RGB LED 134 | */ 135 | wire [7:0] bright_r; 136 | wire [7:0] bright_g; 137 | wire [7:0] bright_b; 138 | 139 | rgb_drv rgb_drv_i( 140 | .clk(clk_48mhz), 141 | .enable(1'b1), 142 | .out({led_r,led_g,led_b}), 143 | .bright_r(bright_r), 144 | .bright_g(bright_g), 145 | .bright_b(bright_b) 146 | ); 147 | `else 148 | // turn off the LEDs 149 | assign led_r = 1; 150 | assign led_g = 1; 151 | assign led_b = 1; 152 | `endif 153 | 154 | wire sw1_in; 155 | tristate #(.PULLUP(1)) sw1_buffer( 156 | .pin(sw1), 157 | .enable(0), 158 | .data_in(sw1_in), 159 | .data_out(1'b0) 160 | ); 161 | 162 | `ifdef WRANGLER_UART 163 | // serial port interface 164 | // TODO: replace with USB serial port 165 | wire uart_txd_strobe; 166 | wire uart_txd_ready; 167 | wire [7:0] uart_txd; 168 | 169 | wire uart_rxd_strobe; 170 | wire [7:0] uart_rxd; 171 | 172 | uart uart_i( 173 | .clk_48mhz(clk_48mhz), 174 | .clk(clk), 175 | .reset(reset), 176 | .serial_txd(`WRANGLER_UART_TX), 177 | .uart_txd(uart_txd), 178 | .uart_txd_strobe(uart_txd_strobe), 179 | .uart_rxd(`WRANGLER_UART_RX), 180 | .uart_rxd_strobe(uart_rxd_strobe) 181 | ); 182 | `endif 183 | 184 | `ifdef WRANGLER_HDMI 185 | /* 186 | * HDMI and TMDS decoders with streaming interface 187 | * optional but why are you using this otherwise? 188 | */ 189 | wire hdmi_clk; 190 | wire hdmi_bit_clk; 191 | wire hdmi_valid; 192 | wire hdmi_locked; 193 | 194 | wire data_valid; 195 | wire [7:0] d0; 196 | wire [7:0] d1; 197 | wire [7:0] d2; 198 | 199 | wire [1:0] hdmi_sync; 200 | wire hsync, vsync; 201 | wire rgb_valid; 202 | wire [7:0] r; 203 | wire [7:0] g; 204 | wire [7:0] b; 205 | wire [11:0] hdmi_xaddr; 206 | wire [11:0] hdmi_yaddr; 207 | 208 | // need to expose this reset to the user? 209 | wire user_hdmi_reset; 210 | reg hdmi_reset = 0; 211 | reg [20:0] invalid_counter = 0; 212 | always @(posedge clk) 213 | begin 214 | if (!hdmi_valid) 215 | invalid_counter <= invalid_counter + 1; 216 | else 217 | invalid_counter <= invalid_counter == 0 ? 0 : invalid_counter - 1; 218 | 219 | hdmi_reset <= invalid_counter[20] || user_hdmi_reset; 220 | end 221 | 222 | tmds_decoder #( 223 | .INVERT(3'b011) 224 | ) tmds_decoder_i( 225 | .reset(hdmi_reset), 226 | 227 | // physical inputs 228 | .clk_p(tmds_clkp), 229 | .d0_p(tmds_d0n), 230 | .d1_p(tmds_d1n), 231 | .d2_p(tmds_d2p), 232 | 233 | // outputs 234 | .hdmi_clk(hdmi_clk), 235 | .bit_clk(hdmi_bit_clk), 236 | .hdmi_valid(hdmi_valid), 237 | .hdmi_locked(hdmi_locked), 238 | .sync(hdmi_sync), 239 | .d0(d0), 240 | .d1(d1), 241 | .d2(d2), 242 | .data_valid(data_valid) 243 | ); 244 | 245 | hdmi_stream hdmi_s( 246 | // inputs 247 | .hdmi_clk(hdmi_clk), 248 | .valid(hdmi_valid), 249 | .sync(hdmi_sync), 250 | .d0(d0), 251 | .d1(d1), 252 | .d2(d2), 253 | // outputs 254 | .xaddr(hdmi_xaddr), 255 | .yaddr(hdmi_yaddr), 256 | .vsync(vsync), 257 | .hsync(hsync), 258 | .rgb_valid(rgb_valid), 259 | .r(r), 260 | .g(g), 261 | .b(b) 262 | ); 263 | `endif 264 | reg [7:0] vsync_count; 265 | reg last_vsync; 266 | always @(posedge hdmi_clk) 267 | begin 268 | if (last_vsync && !vsync) 269 | vsync_count <= vsync_count + 1; 270 | last_vsync <= vsync; 271 | end 272 | 273 | // instantiate whatever display module included us 274 | display display_( 275 | .clk_48mhz(clk_48mhz), 276 | .clk(clk), 277 | 278 | `ifdef WRANGLER_HDMI 279 | // Streaming HDMI interface (in 25 MHz hdmi_clk domain) 280 | .hdmi_clk(hdmi_clk), 281 | .hdmi_bit_clk(hdmi_bit_clk), 282 | .hdmi_valid(hdmi_valid), 283 | .hdmi_reset(user_hdmi_reset), 284 | .vsync(vsync), 285 | .hsync(hsync), 286 | .rgb_valid(rgb_valid), 287 | .r(r), 288 | .g(g), 289 | .b(b), 290 | //.g(hdmi_yaddr[7:0] + vsync_count), 291 | //.b(hdmi_xaddr[7:0] + vsync_count), 292 | .hdmi_xaddr(hdmi_xaddr), 293 | .hdmi_yaddr(hdmi_yaddr), 294 | `endif 295 | 296 | `ifdef WRANGLER_GPIO 297 | // GPIO banks for output 298 | .gpio_bank_0({ 299 | gpio_0_0, 300 | gpio_0_1, 301 | gpio_0_2, 302 | gpio_0_3, 303 | gpio_0_4, 304 | gpio_0_5, 305 | gpio_0_6, 306 | gpio_0_7 307 | }), 308 | 309 | .gpio_bank_1({ 310 | gpio_1_7, 311 | gpio_1_6, 312 | gpio_1_5, 313 | gpio_1_4, 314 | gpio_1_3, 315 | gpio_1_2, 316 | gpio_1_1, 317 | gpio_1_0 318 | }), 319 | `endif 320 | 321 | `ifdef WRANGLER_USB 322 | // USB interface tristate 323 | //output usb_pullup, 324 | //output usb_out_enable, 325 | //output [1:0] usb_out, 326 | //input [1:0] usb_in, 327 | `endif 328 | 329 | `ifdef WRANGLER_UART 330 | // serial interface (for now) 331 | .uart_txd(uart_txd), 332 | .uart_txd_strobe(uart_txd_strobe), 333 | .uart_txd_ready(uart_txd_ready), 334 | .uart_rxd(uart_rxd), 335 | .uart_rxd_strobe(uart_rxd_strobe), 336 | `endif 337 | 338 | `ifdef WRANGLER_SWITCH 339 | // user switch 340 | .sw1(sw1_in), 341 | `endif 342 | 343 | `ifdef WRANGLER_LED 344 | // RGB led on the board with PWM 345 | .led_r(bright_r), 346 | .led_g(bright_g), 347 | .led_b(bright_b), 348 | `endif 349 | 350 | // SPI flash (be careful not to overwrite the boot loader!) 351 | `ifdef WRANGLER_SPI 352 | .spi_cs(spi_cs), 353 | .spi_clk(spi_clk), 354 | .spi_do(spi_do), 355 | .spi_di(spi_di), 356 | `endif 357 | ); 358 | 359 | 360 | // EDID interface is not yet exposed to the user 361 | wire sda_out; 362 | wire sda_in; 363 | wire sda_enable; 364 | 365 | tristate sda_buffer( 366 | //.pin(hdmi_sda), 367 | .pin(gpio_0_7), 368 | .enable(sda_enable), 369 | .data_out(sda_out), 370 | .data_in(sda_in) 371 | ); 372 | reg [7:0] edid[0:255]; 373 | reg [7:0] edid_data; 374 | wire [7:0] edid_read_addr; 375 | initial $readmemh("edid.hex", edid); 376 | 377 | i2c_device i2c_i( 378 | .clk(clk), 379 | .reset(reset), 380 | .scl_in(hdmi_scl), 381 | .sda_in(sda_in), 382 | .sda_out(sda_out), 383 | .sda_enable(sda_enable), 384 | 385 | // we only implement reads 386 | .data_addr(edid_read_addr), 387 | .rd_data(edid[edid_read_addr]) 388 | ); 389 | endmodule 390 | 391 | -------------------------------------------------------------------------------- /verilog/train.v: -------------------------------------------------------------------------------- 1 | /* 2 | * HDMI interface for the NS Train display. 3 | * 4 | * This uses the HDMI streaming interface to populate two 5 | * block RAM framebuffers that are then clocked out on the GPIO 6 | * pins of the pixel wrangler. 7 | */ 8 | `default_nettype none 9 | `define WRANGLER_LED 10 | `include "top.v" 11 | 12 | module display( 13 | input clk_48mhz, 14 | input clk, // system clock, probably 12 or 24 Mhz 15 | 16 | // Streaming HDMI interface (in 25 MHz hdmi_clk domain) 17 | input hdmi_clk, 18 | input hdmi_valid, 19 | input vsync, 20 | input hsync, 21 | input rgb_valid, 22 | input [7:0] r, 23 | input [7:0] g, 24 | input [7:0] b, 25 | input [11:0] hdmi_xaddr, 26 | input [11:0] hdmi_yaddr, 27 | 28 | // GPIO banks for output 29 | output [7:0] gpio_bank_0, 30 | output [7:0] gpio_bank_1, 31 | 32 | // RGB led on the board with PWM 33 | output [7:0] led_r, 34 | output [7:0] led_g, 35 | output [7:0] led_b 36 | ); 37 | wire reset = 0; 38 | 39 | wire panel_data1 = gpio_bank_0[7]; // gpio_12; 40 | wire panel_latch = gpio_bank_0[6]; // gpio_21; 41 | wire panel_clk = gpio_bank_0[5]; // gpio_13; 42 | wire panel_en = gpio_bank_0[4]; // gpio_19; 43 | wire panel_a3 = gpio_bank_0[3]; // gpio_18; 44 | wire [2:0] panel_addr = { gpio_bank_0[2:0] }; // { gpio_11, gpio_9, gpio_6 }; 45 | wire panel_data0 = gpio_bank_1[3]; // gpio_44; 46 | assign panel_a3 = 0; 47 | 48 | // for debug output the sync signals on the gpio 49 | assign gpio_bank_1[0] = vsync; 50 | assign gpio_bank_1[1] = hsync; 51 | assign gpio_bank_1[2] = hdmi_valid; 52 | 53 | parameter LED_PANEL_WIDTH = 104; 54 | parameter ADDR_WIDTH = 12; 55 | parameter MIN_X = 50; 56 | parameter MIN_Y = 110; // we aren't doing overscan correctly 57 | 58 | // turn the weird linear addresses from the led matrix into 59 | // frame buffer read addresses for the RAM. note that both 60 | // framebuffers are read with the same x and y since the 61 | // read addresses are in fb space, not hdmi space 62 | wire [ADDR_WIDTH-1:0] led_addr; 63 | wire [11:0] led_xaddr; 64 | wire [11:0] led_yaddr; 65 | display_mapper mapper(led_addr, led_xaddr, led_yaddr); 66 | 67 | // outputs to the LED matrices 68 | wire [7:0] r0; 69 | wire [7:0] g0; 70 | wire [7:0] b0; 71 | wire [7:0] r1; 72 | wire [7:0] g1; 73 | wire [7:0] b1; 74 | 75 | // the train display has two separate LED modules, 76 | // so two subsections of the frame buffer are used 77 | // the modules aren't 128 across, but for simplicity 78 | // the overlapping bits are stored here anyway 79 | hdmi_framebuffer #( 80 | .MIN_X(MIN_X + 0*LED_PANEL_WIDTH), 81 | .MIN_Y(MIN_Y), 82 | .WIDTH(128), 83 | .HEIGHT(32), 84 | ) fb0( 85 | // hdmi side 86 | .hdmi_clk(hdmi_clk), 87 | .xaddr(hdmi_xaddr), 88 | .yaddr(hdmi_yaddr), 89 | .rgb_valid(rgb_valid), 90 | .r(r), 91 | .g(g), 92 | .b(b), 93 | // output side 94 | .clk(clk), 95 | .xaddr_r(led_xaddr), 96 | .yaddr_r(led_yaddr), 97 | .r_out(r0), 98 | .g_out(g0), 99 | .b_out(b0) 100 | ); 101 | 102 | hdmi_framebuffer #( 103 | .MIN_X(MIN_X + 1*LED_PANEL_WIDTH), 104 | .MIN_Y(MIN_Y), 105 | .WIDTH(128), 106 | .HEIGHT(32), 107 | ) fb1( 108 | // hdmi side 109 | .hdmi_clk(hdmi_clk), 110 | .rgb_valid(rgb_valid), 111 | .xaddr(hdmi_xaddr), 112 | .yaddr(hdmi_yaddr), 113 | .r(r), 114 | .g(g), 115 | .b(b), 116 | // output side 117 | .clk(clk), 118 | .xaddr_r(led_xaddr), 119 | .yaddr_r(led_yaddr), 120 | .r_out(r1), 121 | .g_out(g1), 122 | .b_out(b1) 123 | ); 124 | 125 | led_matrix #( 126 | // internal display 4 address lines, 32 * 128 127 | //.DISP_ADDR_WIDTH(4), 128 | //.DISPLAY_WIDTH(13'd384), // 24 * 16 129 | // external display is 3 address lines, 32 * 104 130 | .DISP_ADDR_WIDTH(3), 131 | .DISPLAY_WIDTH(416), // 13 columns * 16 * 2 132 | .FB_ADDR_WIDTH(ADDR_WIDTH) 133 | ) disp0( 134 | .clk(clk), 135 | .reset(reset), 136 | // physical interface 137 | .data_out(panel_data0), // gpio_34), 138 | .clk_out(panel_clk), // gpio_26), 139 | .latch_out(panel_latch), // gpio_25), 140 | .enable_out(panel_en), // gpio_27), 141 | .addr_out(panel_addr), // outside panel has 3 address bits 142 | // logical interface 143 | .data_in(b0), 144 | .data_addr(led_addr) 145 | ); 146 | 147 | led_matrix #( 148 | // internal display 4 address lines, 32 * 128 149 | //.DISP_ADDR_WIDTH(4), 150 | //.DISPLAY_WIDTH(13'd384), // 24 * 16 151 | // external display is 3 address lines, 32 * 104 152 | .DISP_ADDR_WIDTH(3), 153 | .DISPLAY_WIDTH(416), // 26 * 16 * 2 154 | .FB_ADDR_WIDTH(ADDR_WIDTH) 155 | ) disp1( 156 | .clk(clk), 157 | .reset(reset), 158 | // physical interface (only data is used) 159 | .data_out(panel_data1), // gpio_23), 160 | // logical interface 161 | .data_in(b1), 162 | //.data_addr(read_addr) 163 | ); 164 | 165 | // pulse the RGB led. should do something with state here 166 | wire [7:0] rate_r = 8'h0F; 167 | wire [7:0] rate_g = 8'h1F; 168 | wire [7:0] rate_b = 8'h3F; 169 | 170 | breath breath_r(clk, rate_r, led_r); 171 | breath breath_g(clk, rate_g, led_g); 172 | breath breath_b(clk, rate_b, led_b); 173 | endmodule 174 | 175 | 176 | 177 | // for speed of receiving the HDMI signals, the framebuffer is stored in 178 | // normal layout with a power-of-two pitch. 179 | // the actual LED matrix might be weird, so turn a linear offset 180 | // into a framebuffer offset. 181 | // 182 | // external display is 104 wide 32 high, but mapped like: 183 | // 184 | // 10 skip eight 30 repeat 13 times 190 185 | // | \ | | 186 | // 1f \ 3f 19f -> go back to second column 187 | // 00 1a0 \->20 180 188 | // | | | | 189 | // 0f 1af 2f 18f 190 | // 191 | 192 | module display_mapper( 193 | input [12:0] linear_addr, 194 | output [11:0] x_addr, 195 | output [4:0] y_addr 196 | ); 197 | parameter PANEL_SHIFT_WIDTH = (13 * 32) / 32; 198 | parameter PANEL_PITCH = 128; 199 | 200 | wire y_bank = linear_addr[4]; 201 | 202 | wire [12:0] x_value = linear_addr[12:5]; 203 | wire [12:0] x_offset; 204 | reg [2:0] x_minor; 205 | reg [12:0] x_major; 206 | 207 | wire [4:0] y_addr = linear_addr[3:0] + (y_bank ? 0 : 16); 208 | wire [11:0] x_addr = x_major*8 + x_minor; 209 | 210 | always @(*) 211 | begin 212 | if (x_value >= 7 * PANEL_SHIFT_WIDTH) begin 213 | x_minor = 7; 214 | x_major = x_value - 7 * PANEL_SHIFT_WIDTH; 215 | end else 216 | if (x_value >= 6 * PANEL_SHIFT_WIDTH) begin 217 | x_minor = 6; 218 | x_major = x_value - 6 * PANEL_SHIFT_WIDTH; 219 | end else 220 | if (x_value >= 5 * PANEL_SHIFT_WIDTH) begin 221 | x_minor = 5; 222 | x_major = x_value - 5 * PANEL_SHIFT_WIDTH; 223 | end else 224 | if (x_value >= 4 * PANEL_SHIFT_WIDTH) begin 225 | x_minor = 4; 226 | x_major = x_value - 4 * PANEL_SHIFT_WIDTH; 227 | end else 228 | if (x_value >= 3 * PANEL_SHIFT_WIDTH) begin 229 | x_minor = 3; 230 | x_major = x_value - 3 * PANEL_SHIFT_WIDTH; 231 | end else 232 | if (x_value >= 2 * PANEL_SHIFT_WIDTH) begin 233 | x_minor = 2; 234 | x_major = x_value - 2 * PANEL_SHIFT_WIDTH; 235 | end else 236 | if (x_value >= 1 * PANEL_SHIFT_WIDTH) begin 237 | x_minor = 1; 238 | x_major = x_value - 1 * PANEL_SHIFT_WIDTH; 239 | end else begin 240 | x_minor = 0; 241 | x_major = x_value; 242 | end 243 | end 244 | endmodule 245 | 246 | 247 | module led_matrix( 248 | input clk, 249 | input reset, 250 | // physical 251 | output data_out, 252 | output clk_out, 253 | output latch_out, 254 | output enable_out, 255 | output [DISP_ADDR_WIDTH-1:0] addr_out, 256 | // framebuffer 257 | output [FB_ADDR_WIDTH-1:0] data_addr, 258 | input [DATA_WIDTH-1:0] data_in 259 | ); 260 | parameter DISP_ADDR_WIDTH = 4; 261 | parameter DISPLAY_WIDTH = 32; 262 | parameter FB_ADDR_WIDTH = 8; 263 | parameter DATA_WIDTH = 8; 264 | 265 | reg clk_out; 266 | reg latch_out; 267 | reg data_out; 268 | reg enable_out; 269 | reg [DISP_ADDR_WIDTH-1:0] addr_out; 270 | reg [DISP_ADDR_WIDTH-1:0] addr; 271 | 272 | reg [FB_ADDR_WIDTH-1:0] x_index; 273 | reg [FB_ADDR_WIDTH-1:0] data_addr; 274 | 275 | reg [FB_ADDR_WIDTH-1:0] counter; 276 | reg [30:0] counter_timer; 277 | 278 | // usable brightness values start around 0x40 279 | reg [2:0] latch_counter = 0; 280 | reg [7:0] brightness = 8'hFF; 281 | 282 | always @(posedge clk) 283 | begin 284 | clk_out <= 0; 285 | 286 | counter_timer <= counter_timer + 1; 287 | enable_out <= !(brightness > counter_timer[7:0]); 288 | 289 | if (reset) 290 | begin 291 | counter <= 0; 292 | enable_out <= 1; 293 | data_addr <= ~0; 294 | x_index <= 0; 295 | addr_out <= 0; 296 | addr <= 0; 297 | data_out <= 0; 298 | latch_counter <= 0; 299 | brightness <= 8'h80; 300 | end else 301 | if (latch_out) 302 | begin 303 | // unlatch and re-enable the display 304 | latch_out <= 0; 305 | //enable_out <= 0; 306 | 307 | // if this has wrapped the display, 308 | // start over on reading the frame buffer 309 | if (addr == 0) 310 | data_addr <= 0; 311 | // hold the clock high 312 | clk_out <= 1; 313 | end else 314 | if (x_index == DISPLAY_WIDTH) 315 | begin 316 | if (latch_counter == 7) 317 | begin 318 | // done with this scan line, reset for the next time 319 | addr <= addr + 1; 320 | brightness <= 8'hFF; // last one, so make it bright 321 | end else begin 322 | // redraw the same scan line a few times at different brightness levels 323 | data_addr <= data_addr - DISPLAY_WIDTH; 324 | brightness <= brightness + 8'h18; 325 | end 326 | 327 | // latch this data and ensure that the correct matrix row is selected 328 | latch_out <= 1; 329 | addr_out <= addr; 330 | latch_counter <= latch_counter + 1; 331 | 332 | // start a new scan line 333 | x_index <= 0; 334 | // hold the clock high 335 | clk_out <= 1; 336 | end else 337 | if (clk_out == 1) 338 | begin 339 | // falling edge of the clock, prepare the next output 340 | // use binary-coded pulse modulation, so turn on the output 341 | // based on each bit and the current brightness level 342 | if (data_in[latch_counter]) 343 | //if (data_in) 344 | data_out <= 1; 345 | else 346 | data_out <= 0; 347 | 348 | x_index <= x_index + 1; 349 | 350 | // start the fetch for the next address 351 | data_addr <= data_addr + 1; 352 | end else begin 353 | // rising edge of the clock, new data should be ready 354 | // and stable, so mark it 355 | clk_out <= 1; 356 | end 357 | end 358 | endmodule 359 | -------------------------------------------------------------------------------- /verilog/uart.v: -------------------------------------------------------------------------------- 1 | /* 2 | * uart.v - High-speed serial support. Includes a baud generator, UART, 3 | * and a simple RFC1662-inspired packet framing protocol. 4 | * 5 | * This module is designed a 3 Mbaud serial port. 6 | * This is the highest data rate supported by 7 | * the popular FT232 USB-to-serial chip. 8 | * 9 | * Copyright (C) 2009 Micah Dowty 10 | * (C) 2018 Trammell Hudson 11 | * 12 | * Permission is hereby granted, free of charge, to any person obtaining a copy 13 | * of this software and associated documentation files (the "Software"), to deal 14 | * in the Software without restriction, including without limitation the rights 15 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 | * copies of the Software, and to permit persons to whom the Software is 17 | * furnished to do so, subject to the following conditions: 18 | * 19 | * The above copyright notice and this permission notice shall be included in 20 | * all copies or substantial portions of the Software. 21 | * 22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 | * THE SOFTWARE. 29 | */ 30 | 31 | 32 | /* 33 | * Byte transmitter, RS-232 8-N-1 34 | * 35 | * Transmits on 'serial'. When 'ready' goes high, we can accept another byte. 36 | * It should be supplied on 'data' with a pulse on 'data_strobe'. 37 | */ 38 | 39 | module uart_tx( 40 | input mclk, 41 | input reset, 42 | input baud_x1, 43 | output serial, 44 | output reg ready, 45 | input [7:0] data, 46 | input data_strobe 47 | ); 48 | 49 | /* 50 | * Left-to-right shift register. 51 | * Loaded with data, start bit, and stop bit. 52 | * 53 | * The stop bit doubles as a flag to tell us whether data has been 54 | * loaded; we initialize the whole shift register to zero on reset, 55 | * and when the register goes zero again, it's ready for more data. 56 | */ 57 | reg [7+1+1:0] shiftreg; 58 | 59 | /* 60 | * Serial output register. This is like an extension of the 61 | * shift register, but we never load it separately. This gives 62 | * us one bit period of latency to prepare the next byte. 63 | * 64 | * This register is inverted, so we can give it a reset value 65 | * of zero and still keep the 'serial' output high when idle. 66 | */ 67 | reg serial_r; 68 | assign serial = !serial_r; 69 | 70 | //assign ready = (shiftreg == 0); 71 | 72 | reg baud_x1_rising; 73 | reg baud_x1_prev = 0; 74 | always @(posedge mclk) begin 75 | baud_x1_rising <= baud_x1 && !baud_x1_prev; 76 | baud_x1_prev <= baud_x1; 77 | end 78 | 79 | /* 80 | * State machine 81 | */ 82 | 83 | always @(posedge mclk) 84 | if (reset) begin 85 | shiftreg <= 0; 86 | serial_r <= 0; 87 | end 88 | else if (data_strobe) begin 89 | shiftreg <= { 90 | 1'b1, // stop bit 91 | data, 92 | 1'b0 // start bit (inverted) 93 | }; 94 | ready <= 0; 95 | end 96 | else if (baud_x1_rising) begin 97 | if (shiftreg == 0) 98 | begin 99 | /* Idle state is idle high, serial_r is inverted */ 100 | serial_r <= 0; 101 | ready <= 1; 102 | end else 103 | serial_r <= !shiftreg[0]; 104 | // shift the output register down 105 | shiftreg <= {1'b0, shiftreg[7+1+1:1]}; 106 | end else 107 | ready <= (shiftreg == 0); 108 | 109 | endmodule 110 | 111 | 112 | /* 113 | * Byte receiver, RS-232 8-N-1 114 | * 115 | * Receives on 'serial'. When a properly framed byte is 116 | * received, 'data_strobe' pulses while the byte is on 'data'. 117 | * 118 | * Error bytes are ignored. 119 | */ 120 | 121 | module uart_rx(mclk, reset, baud_x4, 122 | serial, data, data_strobe); 123 | 124 | input mclk, reset, baud_x4, serial; 125 | output [7:0] data; 126 | output data_strobe; 127 | 128 | /* 129 | * Synchronize the serial input to this clock domain 130 | */ 131 | reg serial_sync; 132 | always @(posedge mclk) serial_sync <= serial; 133 | 134 | reg baud_x4_rising; 135 | reg baud_x4_prev; 136 | always @(posedge mclk) begin 137 | baud_x4_rising <= baud_x4 && !baud_x4_prev; 138 | baud_x4_prev <= baud_x4; 139 | end 140 | 141 | /* 142 | * State machine: Four clocks per bit, 10 total bits. 143 | */ 144 | reg [8:0] shiftreg; 145 | reg [5:0] state; 146 | reg data_strobe; 147 | wire [3:0] bit_count = state[5:2]; 148 | wire [1:0] bit_phase = state[1:0]; 149 | 150 | wire sampling_phase = (bit_phase == 1); 151 | wire start_bit = (bit_count == 0 && sampling_phase); 152 | wire stop_bit = (bit_count == 9 && sampling_phase); 153 | 154 | wire waiting_for_start = (state == 0 && serial_sync == 1); 155 | 156 | wire error = ( (start_bit && serial_sync == 1) || 157 | (stop_bit && serial_sync == 0) ); 158 | 159 | assign data = shiftreg[7:0]; 160 | 161 | always @(posedge mclk or posedge reset) 162 | if (reset) begin 163 | state <= 0; 164 | data_strobe <= 0; 165 | end 166 | else if (baud_x4_rising) begin 167 | 168 | if (waiting_for_start || error || stop_bit) 169 | state <= 0; 170 | else 171 | state <= state + 1; 172 | 173 | if (bit_phase == 1) 174 | shiftreg <= { serial_sync, shiftreg[8:1] }; 175 | 176 | data_strobe <= stop_bit && !error; 177 | 178 | end 179 | else begin 180 | data_strobe <= 0; 181 | end 182 | 183 | endmodule 184 | 185 | module uart( 186 | input clk_48mhz, 187 | input clk, 188 | input reset, 189 | input serial_rxd, 190 | output serial_txd, 191 | input [7:0] uart_txd, 192 | input uart_txd_strobe, 193 | output uart_txd_ready, 194 | output [7:0] uart_rxd, 195 | output uart_rxd_strobe 196 | ); 197 | // generate a 3 MHz/12 MHz serial clock from the 48 MHz clock 198 | // this is the 3 Mb/s maximum supported by the FTDI chip 199 | reg [3:0] baud_clk; 200 | always @(posedge clk_48mhz) 201 | baud_clk <= baud_clk + 1; 202 | 203 | wire uart_txd_ready; 204 | 205 | uart_rx rxd( 206 | .mclk(clk), 207 | .reset(reset), 208 | .baud_x4(baud_clk[1]), // 48 MHz / 4 == 12 Mhz 209 | .serial(serial_rxd), 210 | .data(uart_rxd), 211 | .data_strobe(uart_rxd_strobe) 212 | ); 213 | 214 | uart_tx txd( 215 | .mclk(clk), 216 | .reset(reset), 217 | .baud_x1(baud_clk[3]), // 48 MHz / 16 == 3 Mhz 218 | .serial(serial_txd), 219 | .ready(uart_txd_ready), 220 | .data(uart_txd), 221 | .data_strobe(uart_txd_strobe) 222 | ); 223 | endmodule 224 | -------------------------------------------------------------------------------- /verilog/upduino_v2.pcf: -------------------------------------------------------------------------------- 1 | # The LED pins are using the current controlled outputs 2 | # and are negative logic (write a 0 to turn on). 3 | set_io -nowarn led_r 41 4 | set_io -nowarn led_g 39 5 | set_io -nowarn led_b 40 6 | 7 | # FTDI chip, which sort of works 8 | set_io -nowarn serial_txd 14 # FPGA transmit to USB 9 | set_io -nowarn serial_rxd 15 # FPGA receive from USB 10 | set_io -nowarn spi_cs 16 # Drive high to ensure that the SPI flash is disabled 11 | # set_io serial_rts_n 14 # no? 12 | # set_io serial_dtr_n 16 # no? 13 | 14 | # Normal GPIO pins, left side 15 | set_io -nowarn gpio_23 23 16 | set_io -nowarn gpio_25 25 17 | set_io -nowarn gpio_26 26 18 | set_io -nowarn gpio_27 27 19 | set_io -nowarn gpio_32 32 20 | set_io -nowarn gpio_35 35 21 | set_io -nowarn gpio_31 31 22 | set_io -nowarn gpio_37 37 23 | set_io -nowarn gpio_34 34 24 | set_io -nowarn gpio_43 43 25 | set_io -nowarn gpio_36 36 26 | set_io -nowarn gpio_42 42 27 | set_io -nowarn gpio_38 38 28 | set_io -nowarn gpio_28 28 29 | 30 | # Normal GPIO pins, right side 31 | set_io -nowarn gpio_12 12 32 | set_io -nowarn gpio_21 21 33 | set_io -nowarn gpio_13 13 34 | set_io -nowarn gpio_19 19 35 | set_io -nowarn gpio_18 18 36 | set_io -nowarn gpio_11 11 37 | set_io -nowarn gpio_9 9 38 | set_io -nowarn gpio_6 6 39 | set_io -nowarn gpio_44 44 40 | set_io -nowarn gpio_4 4 41 | set_io -nowarn gpio_3 3 42 | set_io -nowarn gpio_48 48 43 | set_io -nowarn gpio_45 45 44 | set_io -nowarn gpio_47 47 45 | set_io -nowarn gpio_46 46 46 | set_io -nowarn gpio_2 2 47 | -------------------------------------------------------------------------------- /verilog/util.v: -------------------------------------------------------------------------------- 1 | `ifndef _util_v_ 2 | `define _util_v_ 3 | 4 | module 5 | tristate( 6 | inout pin, 7 | input enable, 8 | input data_out, 9 | output data_in 10 | ); 11 | parameter PULLUP = 1'b0; 12 | SB_IO #( 13 | .PIN_TYPE(6'b1010_01), // tristatable output 14 | .PULLUP(PULLUP) 15 | ) buffer( 16 | .PACKAGE_PIN(pin), 17 | .OUTPUT_ENABLE(enable), 18 | .D_IN_0(data_in), 19 | .D_OUT_0(data_out) 20 | ); 21 | endmodule 22 | 23 | 24 | module clk_div3( 25 | input clk, 26 | input reset, 27 | output clk_out 28 | ); 29 | reg [1:0] pos_count, neg_count; 30 | assign clk_out = (pos_count == 2) || (neg_count == 2); 31 | 32 | always @(posedge clk) 33 | if (reset || pos_count == 2) 34 | pos_count <= 0; 35 | else 36 | pos_count <= pos_count + 1; 37 | 38 | always @(negedge clk) 39 | if (reset || neg_count == 2) 40 | neg_count <= 0; 41 | else 42 | neg_count <= neg_count + 1; 43 | 44 | endmodule 45 | 46 | 47 | module spram_32k( 48 | input clk, 49 | input reset = 0, 50 | input cs = 1, 51 | input wen, 52 | input [13:0] wr_addr, 53 | input [15:0] wr_data, 54 | input [3:0] wr_mask = 4'b1111, 55 | input [13:0] rd_addr, 56 | output [15:0] rd_data 57 | ); 58 | SB_SPRAM256KA ram( 59 | // read 16 bits at a time 60 | .DATAOUT(rd_data), 61 | .ADDRESS(wen ? wr_addr : rd_addr), 62 | .DATAIN(wr_data), 63 | .MASKWREN(wr_mask), 64 | .WREN(wen), 65 | 66 | .CHIPSELECT(cs && !reset), 67 | .CLOCK(clk), 68 | 69 | // if we cared about power, maybe we would adjust these 70 | .STANDBY(1'b0), 71 | .SLEEP(1'b0), 72 | .POWEROFF(1'b1) 73 | ); 74 | 75 | endmodule 76 | 77 | 78 | module clock_cross_strobe( 79 | input clk_in, 80 | input in, 81 | input clk_out, 82 | output out 83 | ); 84 | reg flag = 0; 85 | reg last_flag = 0; 86 | reg out = 0; 87 | 88 | always @(posedge clk_in) 89 | if (in) 90 | flag <= ~flag; 91 | 92 | always @(posedge clk_out) 93 | begin 94 | out <= last_flag != flag; 95 | last_flag <= flag; 96 | end 97 | endmodule 98 | 99 | 100 | module edge_detect( 101 | input clk, 102 | input in, 103 | output fall, 104 | output rise 105 | ); 106 | reg last; 107 | assign fall = !in && last; 108 | assign rise = in && !last; 109 | always @(posedge clk) 110 | last <= in; 111 | endmodule 112 | 113 | `endif 114 | --------------------------------------------------------------------------------