├── .gitignore ├── Makefile ├── Makefile.icestorm ├── README.md ├── blink.c ├── hello.c ├── ice40-risc8.v ├── program.syn.hex ├── risc8-alu.v ├── risc8-core.v ├── risc8-dev.v ├── risc8-instr.v ├── risc8-ram.v ├── risc8-regs.v ├── risc8-soc.v ├── test-risc8.v ├── tests ├── test0.S ├── test1.c ├── test2.c └── test3.c ├── uart.v ├── upduino_v2.pcf └── zero.hex /.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.elf 3 | *.hex 4 | *.bin 5 | *.bit 6 | *.vvp 7 | *.asc 8 | *.json 9 | *.vcd 10 | .*.d 11 | .*.swp 12 | *.new 13 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: ice40-risc8.bit 3 | 4 | TEST-y += test-risc8 5 | TEST-y += test-reg 6 | 7 | ice40-risc8.bit: program.hex 8 | 9 | PROGRAM ?= hello 10 | program.hex: $(PROGRAM).hex 11 | cp $< $@ 12 | 13 | include Makefile.icestorm 14 | 15 | CROSS ?= avr- 16 | 17 | CFLAGS ?= \ 18 | -O3 \ 19 | -Wall \ 20 | -mmcu=attiny85 \ 21 | 22 | NO=\ 23 | -Wl,-T,sections.lds \ 24 | -ffreestanding \ 25 | -nostdinc \ 26 | -nostdlib \ 27 | 28 | %.bin: %.elf 29 | $(CROSS)objcopy -Obinary $< $@ 30 | %.elf: %.o 31 | $(CROSS)gcc $(CFLAGS) -o $@ $^ \ 32 | 33 | %.o: %.c 34 | $(CROSS)gcc $(CFLAGS) -c -o $@ $^ 35 | %.elf: %.S 36 | $(CROSS)gcc $(CFLAGS) -o $@ $^ \ 37 | -ffreestanding \ 38 | -nostdinc \ 39 | -nostdlib \ 40 | 41 | %.hex: %.bin 42 | xxd -g2 -c2 -e $< | cut -d' ' -f2 > $@ 43 | -------------------------------------------------------------------------------- /Makefile.icestorm: -------------------------------------------------------------------------------- 1 | DEVICE-upduino ?= up5k 2 | FOOTPRINT-upduino ?= sg48 3 | PIN_SRC-upduino ?= upduino_v2.pcf 4 | 5 | DEVICE-icebreaker ?= up5k 6 | FOOTPRINT-icebreaker ?= sg48 7 | PIN_SRC-icebreaker ?= icebreaker.pcf 8 | 9 | DEVICE-tinyfpga := lp8k 10 | FOOTPRINT-tinyfpga := cm81 11 | PIN_SRC-tinyfpga := tinyfpga-bx.pcf 12 | 13 | DEVICE-tomu := up5k 14 | FOOTPRINT-tomu := uwg30 15 | PIN_SRC-tomu := tomu.pcf 16 | 17 | USB_DEV ?= 1-4:1.0 18 | BOARD ?= upduino 19 | DEVICE := $(DEVICE-$(BOARD)) 20 | FOOTPRINT := $(FOOTPRINT-$(BOARD)) 21 | PIN_SRC := $(PIN_SRC-$(BOARD)) 22 | 23 | 24 | FPGA ?= FPGA_ICE40UP5K 25 | PNR ?= $(ICEPATH)nextpnr-ice40 26 | .SECONDARY: 27 | 28 | %.flash: %.bit 29 | $(ICEPATH)iceprog -e 128 # Force a reset 30 | $(ICEPATH)iceprog $< 31 | echo $(USB_DEV) | tee /sys/bus/usb/drivers/ftdi_sio/bind 32 | sleep 1 33 | -stty -F /dev/ttyUSB0 1:0:1cbd:0:3:1c:7f:15:4:5:1:0:11:13:1a:0:12:f:17:16:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0 34 | 35 | %.bit: %.asc 36 | $(ICEPATH)icepack $< $@ 37 | 38 | %.json: %.v 39 | $(ICEPATH)yosys \ 40 | -q \ 41 | -D$(FPGA) \ 42 | -p 'read_verilog $<' \ 43 | -p 'synth_ice40 -top top -json $@' \ 44 | -E .$(basename $@).d \ 45 | 46 | %.asc: $(PIN_SRC) %.json 47 | $(PNR) \ 48 | --$(DEVICE) \ 49 | --package $(FOOTPRINT) \ 50 | --asc $@ \ 51 | --pcf $(PIN_SRC) \ 52 | --json $(basename $@).json \ 53 | --timing-allow-fail \ 54 | 55 | %.gui: %.json 56 | $(PNR) --gui --$(DEVICE) --pcf $(PIN_SRC) --json $< 57 | 58 | %.bit: %.asc 59 | cp $< $<.new 60 | for bram in $(filter %.hex,$^); do \ 61 | echo "Replacing $$bram" ; \ 62 | $(ICEPATH)icebram \ 63 | $$(basename $$bram .hex).syn.hex \ 64 | $$bram \ 65 | < $<.new > $<.tmp \ 66 | || exit 1 ; \ 67 | mv $<.tmp $<.new ; \ 68 | done 69 | $(ICEPATH)icepack $<.new $@ 70 | $(RM) $<.new 71 | 72 | # Generate a desired MHz pll 73 | pll_%.v: 74 | $(ICEPATH)icepll \ 75 | -i 48 \ 76 | -o $(subst pll_,,$(basename $@)) \ 77 | -m \ 78 | -n $(basename $@) \ 79 | -f $@ 80 | 81 | 82 | define make-test = 83 | $1: $1.vvp 84 | vvp $$< 85 | $1.vvp: $1.v 86 | endef 87 | 88 | test: $(TEST-y) 89 | $(foreach t,$(TEST-y),$(eval $(call make-test,$t))) 90 | %.vvp: 91 | iverilog \ 92 | -o $@ \ 93 | -s top \ 94 | -D "RISC8_PROGRAM=\"$(PROGRAM)\"" \ 95 | -M $(dir $@).$(basename $@).m \ 96 | $^ 97 | sed -i -e '1s/^/$@: /' -e 's/$$/ \\/' $(dir $@).$(basename $@).m 98 | mv $(dir $@).$(basename $@).m $(dir $@).$(basename $@).d 99 | 100 | clean: 101 | $(RM) *.blif *.asc *.bin *.json .*.d 102 | 103 | -include .*.d 104 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RISC-8 softcore 2 | 3 | The RISC-8 is a small 8-bit CPU that is mostly compatible with the 4 | [AVR instruction set](http://ww1.microchip.com/downloads/en/devicedoc/atmel-0856-avr-instruction-set-manual.pdf). 5 | It does not have 100% of the architecture implemented, although 6 | enough to run many `avr-gcc` compiled programs in the soft-core. 7 | 8 | Sometimes you want all the power of a 32-bit RISC-V like Claire's 9 | [picorv32](https://github.com/cliffordwolf/picorv32), although sometimes 10 | the 8-bit CPU isn't a limitation and you prefer faster synthesis times 11 | (10 seconds vs 45 seconds) or using fewer FPGA resources (1200 LC vs 12 | 4500 LC), and the 8-bit CPU isn't a limitation. 13 | 14 | ## CPU overview 15 | 16 | The CPU has a two stage pipeline (instruction decode and register fetch, operation and 17 | register write) and can retire one instruction per clock. 18 | Most instructions are single cycle, with some complex instructions like `IN`/`OUT`, 19 | `LD`/`ST` and `CALL`/`RET` that require multiple cycles. 20 | 21 | On an ice40up5k it uses approximately 1400 LC for the SOC with uart and gpio 22 | with nearly the full instruction set (which will synthesize around 15.5 MHz). 23 | By removing some of the instructions the design can run up to 18 MHz, 24 | and overclocking is also possible. 25 | 26 | The ice40up5k's 64 KB of SPRAM can be used for the SOC's data memory, 27 | although the program memory has to be in DPRAM so that it can be stored 28 | in the bitstream. 29 | 30 | The two stage pipeline allows the register file to be stored in block RAM, 31 | which greatly reducing the number of logic cells required. The register 32 | file has a forward-feed to support immediate use-after-write with no 33 | wait states. 34 | 35 | ## Limitations 36 | 37 | * No interrupts 38 | * No `SPM` instruction support 39 | * Not very many built in peripherals 40 | * Probably full of bugs 41 | 42 | ## Examples 43 | 44 | ## Instruction set 45 | 46 | -------------------------------------------------------------------------------- /blink.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | static void __attribute__((__noinline__)) pwm(uint8_t b, uint8_t led) 5 | { 6 | for(uint8_t i = 0 ; i < b ; i++) 7 | PORTB = led; 8 | 9 | for(uint8_t i = b ; i < 255 ; i++) 10 | PORTB = 0; 11 | } 12 | 13 | int main(void) 14 | { 15 | uint8_t led = 1; 16 | while(1) 17 | { 18 | for(uint8_t b = 1 ; b < 64; b++) 19 | { 20 | for(uint8_t s = 0 ; s < 64 ; s++) 21 | pwm(b, led); 22 | } 23 | 24 | for(uint8_t b = 64 ; b > 0 ; b--) 25 | { 26 | for(uint8_t s = 0 ; s < 64 ; s++) 27 | pwm(b, led); 28 | } 29 | 30 | if (led == 4) 31 | led = 1; 32 | else 33 | led <<= 1; 34 | PINB = led; 35 | } 36 | } 37 | -------------------------------------------------------------------------------- /hello.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | void uart_putc(char c) 7 | { 8 | while((USISR & 1) == 0) 9 | ; 10 | for(uint16_t i = 0 ; i < 100 ; i++) 11 | asm("nop"); 12 | USIDR = c; 13 | } 14 | 15 | void uart_puts(const char * s) 16 | { 17 | while(*s) 18 | uart_putc(*s++); 19 | } 20 | 21 | static void __attribute__((__noinline__)) pwm(uint8_t b, uint8_t led) 22 | { 23 | for(uint8_t i = 0 ; i < b ; i++) 24 | PORTB = led; 25 | 26 | for(uint8_t i = b ; i < 255 ; i++) 27 | PORTB = 0; 28 | } 29 | 30 | static char __attribute__((__noinline__)) hexdigit(uint8_t x) 31 | { 32 | static const char PROGMEM hexdigit[16] = "0123456789abcdef"; 33 | return pgm_read_byte_near(hexdigit + (x & 0xF)); 34 | } 35 | 36 | int main(void) 37 | { 38 | uint16_t cycle = 0xFADE; 39 | 40 | *(volatile uint8_t*) 0x20 = hexdigit(cycle >> 4); 41 | *(volatile uint8_t*) 0x20 = hexdigit(cycle >> 0); 42 | 43 | while(1) 44 | { 45 | uint8_t bright = cycle >> 4; 46 | if (bright & 0x80) 47 | bright = ~bright; 48 | pwm(bright, cycle >> 12); 49 | 50 | cycle++; 51 | if ((cycle & 0xFFF) != 0) 52 | continue; 53 | 54 | uart_putc(hexdigit(bright >> 4)); 55 | uart_putc(hexdigit(bright >> 0)); 56 | uart_putc(' '); 57 | uart_putc(hexdigit(cycle >> 12)); 58 | uart_putc(hexdigit(cycle >> 8)); 59 | uart_putc(hexdigit(cycle >> 4)); 60 | uart_putc(hexdigit(cycle >> 0)); 61 | uart_puts(" Hello world\r\n"); 62 | } 63 | } 64 | -------------------------------------------------------------------------------- /ice40-risc8.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `define UART_DIV 5 3 | `include "risc8-soc.v" 4 | 5 | module top( 6 | output led_r, 7 | output led_g, 8 | output led_b, 9 | output spi_cs, 10 | input serial_rxd, 11 | output serial_txd 12 | ); 13 | assign spi_cs = 1; 14 | 15 | wire clk_48; 16 | wire reset = 0; 17 | SB_HFOSC u_hfosc ( 18 | .CLKHFPU(1'b1), 19 | .CLKHFEN(1'b1), 20 | .CLKHF(clk_48) 21 | ); 22 | reg [2:0] clk_div; 23 | always @(posedge clk_48) 24 | clk_div <= clk_div + 1; 25 | //wire clk = clk_div[1]; // 12 MHz 26 | wire clk = clk_div[2]; // 6 MHz 27 | 28 | assign led_r = ~port_b[0]; 29 | assign led_g = ~port_b[1]; 30 | assign led_b = ~port_b[2]; 31 | 32 | wire [7:0] port_b; 33 | wire [7:0] ddr_b; 34 | reg [7:0] pin_b = 0; 35 | 36 | risc8_soc cpu( 37 | .clk(clk), 38 | .reset(reset), 39 | 40 | .port_b(port_b), 41 | .pin_b(pin_b), 42 | .ddr_b(ddr_b), 43 | 44 | .serial_tx(serial_txd), 45 | .serial_rx(serial_rxd) 46 | ); 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /program.syn.hex: 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| 854a 3421 | b314 3422 | 55a9 3423 | ee9a 3424 | ad1f 3425 | 5498 3426 | 0063 3427 | c3f9 3428 | 3bf9 3429 | 623d 3430 | efe0 3431 | ec42 3432 | f04a 3433 | df52 3434 | 73ea 3435 | ff32 3436 | 91ea 3437 | 0079 3438 | 13c1 3439 | 90e5 3440 | 7dbc 3441 | 3111 3442 | a372 3443 | 14f6 3444 | 909d 3445 | e79c 3446 | 2789 3447 | 0b1f 3448 | 7c5f 3449 | a796 3450 | 86e6 3451 | 15cb 3452 | 2dcb 3453 | 5f79 3454 | abde 3455 | 25d6 3456 | 7f5a 3457 | f0e9 3458 | eb94 3459 | db70 3460 | d3c7 3461 | 65b1 3462 | a60d 3463 | 5b77 3464 | e5a1 3465 | 12cb 3466 | 52ff 3467 | a134 3468 | 9aef 3469 | 75cf 3470 | 1421 3471 | 1ae7 3472 | 3f1c 3473 | 959a 3474 | 28ae 3475 | be37 3476 | 6091 3477 | 416f 3478 | b4cc 3479 | 2c19 3480 | fd3c 3481 | e281 3482 | 984e 3483 | cd42 3484 | 0ee7 3485 | 39c3 3486 | 6d46 3487 | f20c 3488 | 6517 3489 | 8be7 3490 | 568b 3491 | 4cf7 3492 | bd40 3493 | eadc 3494 | c475 3495 | fe4d 3496 | eeb8 3497 | b1d9 3498 | 8007 3499 | d2b6 3500 | eb2f 3501 | 6f70 3502 | de84 3503 | 881c 3504 | dd37 3505 | c6c0 3506 | cdff 3507 | cf24 3508 | 7aba 3509 | efb4 3510 | 1fd4 3511 | 383d 3512 | 5bc7 3513 | 75e7 3514 | 957b 3515 | 97c6 3516 | 2cf4 3517 | 49d4 3518 | 138d 3519 | 0737 3520 | 8db8 3521 | 97b2 3522 | ad06 3523 | acdc 3524 | f49f 3525 | 8dd4 3526 | 522a 3527 | 3dfc 3528 | 8f8c 3529 | 3f1c 3530 | c802 3531 | 634c 3532 | 1dc6 3533 | 5166 3534 | 28ae 3535 | 192d 3536 | 8991 3537 | fb18 3538 | c5d0 3539 | 620c 3540 | 3b36 3541 | d1c4 3542 | 1aa9 3543 | 20de 3544 | c1c4 3545 | 2d96 3546 | db6b 3547 | 9ffb 3548 | 239b 3549 | 7582 3550 | 374c 3551 | 2375 3552 | f610 3553 | 8428 3554 | db44 3555 | d9bb 3556 | 09c0 3557 | 2ec3 3558 | a5a3 3559 | bc66 3560 | eaf9 3561 | 9bc4 3562 | c61f 3563 | bf4f 3564 | 5291 3565 | 6f4f 3566 | 4159 3567 | 2d9e 3568 | 7add 3569 | 1e97 3570 | 962c 3571 | 0ef9 3572 | 3299 3573 | 1569 3574 | bf33 3575 | 2cc3 3576 | bd6a 3577 | e5cb 3578 | 1ba2 3579 | 63f0 3580 | d0b0 3581 | 3d6f 3582 | 6eed 3583 | 4ae0 3584 | 6c11 3585 | 97ae 3586 | 3742 3587 | 50b5 3588 | 9431 3589 | 343e 3590 | 2682 3591 | 0da9 3592 | 50df 3593 | 24ba 3594 | 8231 3595 | 3436 3596 | a591 3597 | 4fd0 3598 | 9bdc 3599 | 9fa3 3600 | fb62 3601 | 95c9 3602 | fbfe 3603 | cdf2 3604 | 4679 3605 | 306a 3606 | 5551 3607 | dc60 3608 | f3f7 3609 | a056 3610 | c308 3611 | 53d5 3612 | 80f9 3613 | 250d 3614 | f2b8 3615 | 0961 3616 | 9d45 3617 | 61dd 3618 | c36f 3619 | adae 3620 | cd2c 3621 | 4c74 3622 | 6327 3623 | 1c9b 3624 | dd65 3625 | 7a89 3626 | b2c2 3627 | e538 3628 | 296f 3629 | b9e3 3630 | b98b 3631 | bddb 3632 | 537a 3633 | afc7 3634 | 9084 3635 | 52a9 3636 | 262c 3637 | 55db 3638 | 532e 3639 | 1f32 3640 | 77f1 3641 | 2df2 3642 | 21df 3643 | b3eb 3644 | a946 3645 | 7088 3646 | be03 3647 | 0e55 3648 | 9ad2 3649 | e0ff 3650 | 23cf 3651 | c9c1 3652 | 3317 3653 | 7627 3654 | 63bc 3655 | 6452 3656 | 01fa 3657 | a4f5 3658 | 89b1 3659 | 1403 3660 | 7ff0 3661 | 158e 3662 | 6dd1 3663 | 73a8 3664 | 89af 3665 | 87f1 3666 | 5016 3667 | b731 3668 | 976a 3669 | d556 3670 | 8cc7 3671 | f36f 3672 | 856c 3673 | d132 3674 | 5597 3675 | b650 3676 | 835a 3677 | 4af9 3678 | fdee 3679 | 0241 3680 | 5bdf 3681 | d939 3682 | f714 3683 | 89f5 3684 | 9be4 3685 | c1b8 3686 | 99c2 3687 | a165 3688 | 0a0c 3689 | e97c 3690 | c0ab 3691 | 7d01 3692 | 3438 3693 | dc16 3694 | 3b96 3695 | 3570 3696 | 306e 3697 | 297a 3698 | 62b3 3699 | 8d47 3700 | 121b 3701 | c11d 3702 | 24b1 3703 | 08c5 3704 | e69c 3705 | ee85 3706 | bedb 3707 | 28fb 3708 | 065f 3709 | ee0a 3710 | aff6 3711 | a100 3712 | 3bb5 3713 | 710b 3714 | d900 3715 | dc3d 3716 | 6a90 3717 | 850e 3718 | d17a 3719 | 38c4 3720 | a0eb 3721 | d9c7 3722 | c629 3723 | e120 3724 | c068 3725 | 8421 3726 | 0651 3727 | 14d1 3728 | 1633 3729 | ad7e 3730 | 50d7 3731 | 21b8 3732 | fdad 3733 | 400e 3734 | df9a 3735 | bb3b 3736 | c20f 3737 | ef85 3738 | 4936 3739 | 321c 3740 | 8371 3741 | 990f 3742 | 59e4 3743 | 382b 3744 | 4498 3745 | fc90 3746 | 520a 3747 | 415d 3748 | edb6 3749 | bf28 3750 | 4dbd 3751 | 23dc 3752 | c95a 3753 | 63a4 3754 | 8eb7 3755 | e90d 3756 | f5da 3757 | ebbd 3758 | 77f4 3759 | 3006 3760 | 587d 3761 | 77af 3762 | 54fe 3763 | 67ef 3764 | 8c1b 3765 | f862 3766 | 04fa 3767 | 2237 3768 | 0036 3769 | c3e2 3770 | 0157 3771 | 2caa 3772 | fab0 3773 | 9aa7 3774 | 66f0 3775 | 6eac 3776 | 9735 3777 | 0527 3778 | 7aaa 3779 | d6b2 3780 | 6677 3781 | 11d0 3782 | cc61 3783 | f9df 3784 | 3d3d 3785 | 5c36 3786 | 3433 3787 | 5f28 3788 | 20e6 3789 | e3c3 3790 | 8c87 3791 | 1edd 3792 | cac6 3793 | 4ad9 3794 | 2ac6 3795 | 8916 3796 | d12d 3797 | 6774 3798 | 6dab 3799 | eb95 3800 | 2142 3801 | 9be3 3802 | 7b1f 3803 | 75a2 3804 | 6429 3805 | 9764 3806 | a348 3807 | ee55 3808 | 0201 3809 | 3565 3810 | 117b 3811 | 5231 3812 | 0bb6 3813 | 9558 3814 | 82e2 3815 | b04b 3816 | 4563 3817 | 2dd5 3818 | 75e5 3819 | a216 3820 | e514 3821 | ef35 3822 | 0a9b 3823 | 441b 3824 | 9a23 3825 | d5f5 3826 | 42d7 3827 | 5c69 3828 | addc 3829 | 9663 3830 | 9693 3831 | c49e 3832 | 581c 3833 | 67f6 3834 | ef65 3835 | 22ba 3836 | bc9d 3837 | 8544 3838 | a9c7 3839 | d9f5 3840 | e264 3841 | d53f 3842 | ddd9 3843 | e4a3 3844 | d817 3845 | b87b 3846 | 45bc 3847 | 253f 3848 | e06f 3849 | 41fb 3850 | ee39 3851 | 552f 3852 | f196 3853 | 946f 3854 | 5183 3855 | 9e41 3856 | a5e1 3857 | 9fcb 3858 | ee18 3859 | 18eb 3860 | 52ee 3861 | 4cc7 3862 | 5578 3863 | 40f4 3864 | 1e1d 3865 | c118 3866 | c266 3867 | 5e5c 3868 | 3291 3869 | bc03 3870 | dc68 3871 | ff55 3872 | 9a47 3873 | a2db 3874 | 4729 3875 | cd3d 3876 | dc47 3877 | 3fcb 3878 | 3bca 3879 | 9c3f 3880 | e200 3881 | a602 3882 | 45bd 3883 | 693f 3884 | 8ac8 3885 | b20a 3886 | c193 3887 | 26fc 3888 | bf9a 3889 | 5c9d 3890 | 1cb3 3891 | b10c 3892 | 71a5 3893 | 5ba5 3894 | 2fd0 3895 | 28b4 3896 | 38a8 3897 | c9b1 3898 | 6f88 3899 | 69a3 3900 | dcff 3901 | 2546 3902 | 1200 3903 | f069 3904 | 3ad8 3905 | 9e10 3906 | b2cb 3907 | b8f4 3908 | 3192 3909 | 7648 3910 | 7198 3911 | ae70 3912 | 38ab 3913 | e3c1 3914 | 697d 3915 | b472 3916 | ad48 3917 | 9e3f 3918 | fd93 3919 | 6b6b 3920 | 4333 3921 | d6d2 3922 | 849e 3923 | 6bc8 3924 | 9dd1 3925 | 08a3 3926 | 8d1f 3927 | d4f2 3928 | 094e 3929 | ba81 3930 | 7f7d 3931 | 070a 3932 | d657 3933 | 77c0 3934 | d424 3935 | 165b 3936 | 57c9 3937 | 665f 3938 | 4a63 3939 | 6319 3940 | efe1 3941 | 82d4 3942 | 98b5 3943 | ee00 3944 | df54 3945 | b0e8 3946 | a86c 3947 | 5f6b 3948 | 2a63 3949 | abe6 3950 | 1e41 3951 | cd07 3952 | c314 3953 | 3dca 3954 | 77ab 3955 | d6b0 3956 | 64af 3957 | 7031 3958 | 2b53 3959 | ed0d 3960 | 4742 3961 | 50d0 3962 | 64a1 3963 | 34a3 3964 | 6806 3965 | 79b7 3966 | a4ab 3967 | 590a 3968 | 6f0d 3969 | 3d57 3970 | b21a 3971 | 1245 3972 | 3408 3973 | 2157 3974 | 778d 3975 | 25ca 3976 | 2ea1 3977 | 9b15 3978 | 4dc2 3979 | 27e5 3980 | 38b1 3981 | 536d 3982 | 1b38 3983 | 4b13 3984 | bbc0 3985 | f45a 3986 | 8826 3987 | 2bf3 3988 | 5bb3 3989 | 42b1 3990 | 37ee 3991 | 1445 3992 | 2dd0 3993 | cd2c 3994 | c3ef 3995 | 07d7 3996 | fd74 3997 | 7718 3998 | 84fa 3999 | abc1 4000 | 5305 4001 | d062 4002 | a158 4003 | 73df 4004 | 697a 4005 | 5d05 4006 | 5b66 4007 | 6e2d 4008 | cfd6 4009 | cfb1 4010 | b25c 4011 | f698 4012 | ccd7 4013 | c82e 4014 | 4ffb 4015 | 20ee 4016 | 224c 4017 | 0e42 4018 | 01dd 4019 | f44f 4020 | 549f 4021 | 5b38 4022 | 0fa5 4023 | e629 4024 | 027c 4025 | c093 4026 | 07f2 4027 | 5404 4028 | ea8c 4029 | b3c5 4030 | 97e9 4031 | 26e4 4032 | b2a6 4033 | b0b0 4034 | 8585 4035 | 42e5 4036 | 7ae3 4037 | 802f 4038 | bac3 4039 | 55a6 4040 | c04b 4041 | 49e9 4042 | db78 4043 | a3d6 4044 | 35a4 4045 | 6ff6 4046 | a75d 4047 | d304 4048 | ee11 4049 | e10a 4050 | bf92 4051 | cdfc 4052 | 5d9f 4053 | 3513 4054 | c8a7 4055 | a8ae 4056 | 146f 4057 | 478f 4058 | 062c 4059 | 2725 4060 | 7a94 4061 | 9d88 4062 | 2f4d 4063 | 5c64 4064 | a10e 4065 | 2328 4066 | f432 4067 | 2e4f 4068 | 7058 4069 | 2516 4070 | 4a77 4071 | 4355 4072 | c3b5 4073 | f600 4074 | 6649 4075 | cd8d 4076 | 904a 4077 | 9105 4078 | 3797 4079 | 2847 4080 | 42b9 4081 | faaa 4082 | 5db6 4083 | 3341 4084 | f25b 4085 | 8f04 4086 | 78b2 4087 | b704 4088 | b857 4089 | b311 4090 | 9fb4 4091 | ff26 4092 | 29e3 4093 | 035e 4094 | 6347 4095 | a884 4096 | db75 4097 | -------------------------------------------------------------------------------- /risc8-alu.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Combinatorial 8-bit ALU 3 | * 4 | * This implements a simple 8-bit ALU with status register flags, 5 | * as definied in the AVR instruction datasheet. 6 | * 7 | * Ra can be 8 or 16-bits, Rb is only 8 bits. 8 | */ 9 | `ifndef _risc8_alu_v_ 10 | `define _risc8_alu_v_ 11 | 12 | `define OP_MOVE 4'h0 // Copy the input Ra word to the output 13 | `define OP_MOVR 4'h1 // Copy the input Rb byte to the output 14 | `define OP_ADD 4'h2 15 | `define OP_SUB 4'h3 16 | `define OP_ADW 4'h4 17 | `define OP_SBW 4'h5 // must be OP_ADW | 1 18 | `define OP_NEG 4'h6 19 | `define OP_SWAP 4'h7 20 | `define OP_ASR 4'h8 21 | `define OP_ROR 4'h9 // must be OP_ASR | 1 22 | `define OP_LSR 4'hA 23 | `define OP_AND 4'hB 24 | `define OP_EOR 4'hC 25 | `define OP_OR 4'hD 26 | `define OP_SREG 4'hE // Update the SREG flags, uses carry input for set/clear 27 | `define OP_MUL 4'hF // optional 28 | 29 | // If not every status register bit is required, 30 | // they can be toggled off here. 31 | //`define CONFIG_SREG_SI 32 | //`define CONFIG_SREG_ST 33 | //`define CONFIG_SREG_SH 34 | `define CONFIG_SREG_SS 35 | `define CONFIG_SREG_SV 36 | `define CONFIG_SREG_SN 37 | `define CONFIG_SREG_SZ 38 | `define CONFIG_SREG_SC 39 | 40 | // And if some ALU operations are not required 41 | // they can also be turned off. 42 | 43 | `define CONFIG_OP_ADD 44 | `define CONFIG_OP_SUB 45 | `define CONFIG_OP_ADW_OR_SBW 46 | `define CONFIG_OP_SBW 47 | `define CONFIG_OP_NEG 48 | `define CONFIG_OP_SWAP 49 | `define CONFIG_OP_ASR_OR_ROR 50 | `define CONFIG_OP_LSR 51 | `define CONFIG_OP_AND 52 | `define CONFIG_OP_EOR 53 | `define CONFIG_OP_OR 54 | `define CONFIG_OP_SREG 55 | //`define CONFIG_OP_MUL 56 | 57 | 58 | module risc8_alu( 59 | input clk, 60 | input reset, 61 | 62 | input [15:0] Rd_in, // Might be a word register 63 | input [7:0] Rr_in, 64 | input [7:0] sreg_in, // carry in 65 | input [3:0] op, 66 | input use_carry, 67 | input [7:0] keep_sreg, 68 | 69 | output [15:0] R_out, // full word output register 70 | output [7:0] sreg_out 71 | ); 72 | reg [7:0] R; 73 | reg [7:0] Rh; 74 | assign R_out = { Rh, R }; 75 | 76 | wire [7:0] Rr = Rr_in; 77 | wire [7:0] Rd = Rd_in[7:0]; // default is operate on only the bottom byte 78 | reg SI, ST, SH, SS, SV, SN, SZ, SC; 79 | assign sreg_out = { 80 | `ifdef CONFIG_SREG_SI 81 | SI, 82 | `else 83 | 1'b0, 84 | `endif 85 | `ifdef CONFIG_SREG_ST 86 | ST, 87 | `else 88 | 1'b0, 89 | `endif 90 | `ifdef CONFIG_SREG_SH 91 | SH, 92 | `else 93 | 1'b0, 94 | `endif 95 | `ifdef CONFIG_SREG_SS 96 | SS, 97 | `else 98 | 1'b0, 99 | `endif 100 | `ifdef CONFIG_SREG_SV 101 | SV, 102 | `else 103 | 1'b0, 104 | `endif 105 | `ifdef CONFIG_SREG_SN 106 | SN, 107 | `else 108 | 1'b0, 109 | `endif 110 | `ifdef CONFIG_SREG_SZ 111 | SZ, 112 | `else 113 | 1'b0, 114 | `endif 115 | `ifdef CONFIG_SREG_SC 116 | SC 117 | `else 118 | 1'b0 119 | `endif 120 | }; 121 | 122 | // helpers for computing sreg updates 123 | wire Rd3 = Rd[3]; 124 | wire Rd7 = Rd[7]; 125 | wire Rdh7 = Rd_in[15]; 126 | wire Rr3 = Rr[3]; 127 | wire Rr7 = Rr[7]; 128 | wire R3 = R_out[3]; 129 | wire R7 = R_out[7]; 130 | wire R15 = R_out[15]; 131 | wire C = sreg_in[0]; 132 | wire opt_C = use_carry ? C : 0; // Optional Carry 133 | wire R_zero = R == 0; 134 | 135 | always @(*) begin 136 | {Rh, R} = Rd_in; 137 | { SI, ST, SH, SS, SV, SN, SZ, SC } = sreg_in; 138 | 139 | (* fullcase *) 140 | case(op) 141 | `OP_MOVE: begin 142 | // Default will copy {R,Rh} <= Rd 143 | // Do not modify any SREG 144 | end 145 | `OP_MOVR: begin 146 | // Copy the Rb input byte to the output 147 | // Do not modify any SREG 148 | Rh = 0; 149 | R = Rr; 150 | end 151 | `ifdef CONFIG_OP_ADD 152 | `OP_ADD: begin 153 | R = Rd + Rr + opt_C; 154 | SH = (Rd3 & Rr3) | (Rr3 & !R3) | (!R3 & Rd3); 155 | SV = (Rd7 & Rr7 & !R7) | (!Rd7 & !Rr7 & R7); 156 | SC = (Rd7 & Rr7) | (Rr7 & !R7) | (!R7 & Rd7); 157 | 158 | SN = R7; 159 | SS = SN^SV; 160 | SZ = R_zero; 161 | end 162 | `endif 163 | `ifdef CONFIG_OP_SUB 164 | `OP_SUB: begin 165 | R = Rd - Rr - opt_C; 166 | SH = (!Rd3 & Rr3) | (Rr3 & R3) | (R3 & !Rd3); 167 | SV = (Rd7 & !Rr7 & !R7) | (!Rd7 & Rr7 & R7); 168 | SC = (!Rd7 & Rr7) | (Rr7 & R7) | (R7 & !Rd7); 169 | 170 | SN = R7; 171 | SS = SN^SV; 172 | 173 | // SBC clears flag when result is non-zero, and keeps previous value otherwise 174 | if(!use_carry || !R_zero) 175 | SZ = R_zero; 176 | end 177 | `endif 178 | `ifdef CONFIG_OP_ADW_OR_SBW 179 | `OP_ADW, `OP_SBW: begin 180 | if (op[0]) begin 181 | // SBW 182 | {Rh,R} = Rd_in - Rr; 183 | SC = R15 & !Rdh7; 184 | SV = !R15 & Rdh7; 185 | end else begin 186 | // ADW 187 | {Rh,R} = Rd_in + Rr; 188 | SC = !R15 & Rdh7; 189 | SV = R15 & !Rdh7; 190 | end 191 | SN = R15; 192 | SS = SN ^ SV; 193 | SZ = { Rh, R } == 0; 194 | end 195 | `endif 196 | `ifdef CONFIG_OP_NEG 197 | `OP_NEG: begin 198 | R = -Rd; 199 | SH = R3 | Rd3; 200 | SV = R == 8'h80; 201 | SC = R != 0; 202 | SN = R7; 203 | SS = SN^SV; 204 | SZ = R_zero; 205 | end 206 | `endif 207 | `ifdef CONFIG_OP_SWAP 208 | `OP_SWAP: begin 209 | R = { Rd[3:0], Rd[7:4] }; 210 | // no sreg update 211 | end 212 | `endif 213 | `ifdef CONFIG_OP_ASR_OR_ROR 214 | `OP_ASR, `OP_ROR: begin 215 | R = { op[0] ? C : Rd[7], Rd[7:1] }; 216 | SC = Rd[0]; 217 | SN = R7; 218 | SV = SN^SC; 219 | SS = SN^SV; 220 | SZ = R_zero; 221 | end 222 | `endif 223 | `ifdef CONFIG_OP_LSR 224 | `OP_LSR: begin 225 | R = { 1'b0, Rd[7:1] }; 226 | SC = Rd[0]; 227 | SN = 0; 228 | SZ = R_zero; 229 | SV = SN^SC; 230 | SS = SN^SV; 231 | end 232 | `endif 233 | `ifdef CONFIG_OP_AND 234 | `OP_AND: begin 235 | R = Rd & Rr; 236 | SV = 0; 237 | SN = R7; 238 | SS = SN^SV; 239 | SZ = R_zero; 240 | end 241 | `endif 242 | `ifdef CONFIG_OP_EOR 243 | `OP_EOR: begin 244 | R = Rd ^ Rr; 245 | if(use_carry) SC = 1; // For COM instruction 246 | SV = 0; 247 | SN = R7; 248 | SS = SN^SV; 249 | SZ = R_zero; 250 | end 251 | `endif 252 | `ifdef CONFIG_OP_OR 253 | `OP_OR: begin 254 | R = Rd | Rr; 255 | SV = 0; 256 | SN = R7; 257 | SS = SN^SV; 258 | SZ = R_zero; 259 | end 260 | `endif 261 | `ifdef CONFIG_OP_SREG 262 | `OP_SREG: begin 263 | if(Rr[3] == 0) begin 264 | // CLX or SEX 265 | (* full_case *) 266 | case(Rr[2:0]) 267 | 3'b000: SC = use_carry; 268 | 3'b001: SZ = use_carry; 269 | 3'b010: SN = use_carry; 270 | 3'b011: SV = use_carry; 271 | 3'b100: SS = use_carry; 272 | 3'b101: SH = use_carry; 273 | 3'b110: ST = use_carry; 274 | 3'b111: SI = use_carry; 275 | endcase 276 | end else 277 | begin 278 | if(use_carry) 279 | // BST 280 | ST = Rd[Rr[2:0]]; 281 | else 282 | // BLD 283 | R[Rr[2:0]] = ST; 284 | end 285 | end 286 | `endif 287 | `ifdef CONFIG_OP_MULU 288 | // need to infer a multiplier 289 | `OP_MUL: begin 290 | { Rh, R } = Rd * Rr; 291 | SC = R15; 292 | SZ = { Rh, R } == 0; 293 | end 294 | `endif 295 | default: begin 296 | // NOTHING 297 | end 298 | endcase 299 | 300 | if(keep_sreg[7]) SI = sreg_in[7]; 301 | if(keep_sreg[6]) ST = sreg_in[6]; 302 | if(keep_sreg[5]) SH = sreg_in[5]; 303 | if(keep_sreg[4]) SS = sreg_in[4]; 304 | if(keep_sreg[3]) SV = sreg_in[3]; 305 | if(keep_sreg[2]) SN = sreg_in[2]; 306 | if(keep_sreg[1]) SZ = sreg_in[1]; 307 | if(keep_sreg[0]) SC = sreg_in[0]; 308 | end 309 | 310 | endmodule 311 | 312 | 313 | `endif 314 | -------------------------------------------------------------------------------- /risc8-core.v: -------------------------------------------------------------------------------- 1 | /* 2 | * RISC-8, a mostly AVR comptaible softcore. 3 | * 4 | * Two stage pipeline design, similar to the actual ATtiny85 architecture. 5 | * Each clock can retire one instruction. 6 | * 7 | * First stage: 8 | * - Receive opcode on input 9 | * - Decode into registers required 10 | * - Setup reads of those registers 11 | * - Latch constant values and flags for next stage. 12 | * - Latch destination register 13 | * 14 | * Second stage: 15 | * - Route registers values or constant values to ALU 16 | * - Setup write of ALU output 17 | * 18 | */ 19 | `ifndef _risc8_core_v_ 20 | `define _risc8_core_v_ 21 | 22 | //`define CONFIG_MULU 23 | 24 | `include "risc8-alu.v" 25 | `include "risc8-regs.v" 26 | `include "risc8-instr.v" 27 | 28 | //`define config_is_inc 29 | //`define config_is_dec 30 | `define config_is_com 31 | `define config_is_adiw_or_sbiw 32 | `define config_is_movw 33 | `define config_is_clx_or_sex 34 | //`define config_is_mulu 35 | `define config_is_out 36 | `define config_is_in 37 | //`define config_is_lds 38 | `define config_is_ld_xyz 39 | `define config_is_ld_yz_plus_q 40 | `define config_is_lpm 41 | `define config_is_push 42 | `define config_is_pop 43 | `define config_is_ret 44 | `define config_is_cpse 45 | `define config_is_sbrc_or_sbrs 46 | `define config_is_brbc_or_brbs 47 | `define config_is_bld_or_bst 48 | //`define config_is_jmp 49 | //`define config_is_call 50 | //`define config_is_ijmp 51 | `define config_is_rjmp 52 | `define config_is_rcall 53 | `define config_is_sbis_or_sbic 54 | 55 | 56 | 57 | module risc8_core( 58 | input clk, 59 | input reset, 60 | 61 | // the program memory should provide a new opcode 62 | // every clock cycle 63 | output [15:0] pc, 64 | input [15:0] cdata, 65 | 66 | // the data memory is used for LD/ST as well as the stack 67 | output [15:0] data_addr, 68 | output data_wen, 69 | output data_ren, 70 | input [7:0] data_read, 71 | output [7:0] data_write 72 | ); 73 | // register file (as flops, not as BRAM) 74 | localparam BASE_X = 26; 75 | localparam BASE_Y = 28; 76 | localparam BASE_Z = 30; 77 | 78 | // The register file has a block ram underneath with a one-cycle 79 | // delay to reads. This means that there is a two stage pipeline 80 | // of decoding the existing instruction on one clock and loading 81 | // the register, and then one clock to evaluate and retire it. 82 | reg [5:0] sel_Ra; 83 | reg [5:0] sel_Rb; 84 | reg [5:0] sel_Rd; 85 | wire [15:0] reg_Ra; 86 | wire [7:0] reg_Rb; 87 | 88 | 89 | risc8_regs regs( 90 | .clk(clk), 91 | .reset(reset), 92 | // Read ports. Rd is 8 or 16 bits, Rr is always 8 93 | .a(sel_Ra), 94 | .b(sel_Rb), 95 | .Ra(reg_Ra), 96 | .Rb(reg_Rb), 97 | // write port, 8 or 16 bits, delayed by a clock for the ALU 98 | .d(prev_sel_Rd), 99 | .Rd(alu_out), 100 | .write(prev_alu_store), 101 | .write_word(prev_alu_word) 102 | ); 103 | 104 | reg [15:0] temp; 105 | reg [15:0] next_temp; 106 | reg [15:0] reg_PC; 107 | reg [15:0] reg_SP; 108 | reg [15:0] next_SP; 109 | reg [7:0] sreg; 110 | 111 | // the PC output is almost always the actual PC, 112 | // although sometimes it is the address for a LPM 113 | // or a LDS instruction that uses the next cdata 114 | assign pc = next_PC; 115 | reg [15:0] next_PC; 116 | reg force_PC; 117 | 118 | // Some instructions require an extra cycle; 119 | // they will set cycle and re-use the previous opcode 120 | reg [1:0] cycle; 121 | reg [1:0] next_cycle; 122 | 123 | // Some instruction can cause the next instruction to be skipped, 124 | // which might be multiple words; this still executes the instruction, 125 | // but doesn't write any results 126 | reg skip; 127 | reg next_skip; 128 | reg [15:0] prev_opcode; 129 | wire [15:0] opcode = cycle == 0 ? cdata : prev_opcode; 130 | reg [15:0] addr; 131 | reg [15:0] next_addr; 132 | reg [7:0] wdata; 133 | reg [7:0] next_wdata; 134 | reg wen; 135 | reg ren; 136 | reg next_wen; 137 | reg next_ren; 138 | 139 | assign data_addr = next_addr; 140 | assign data_wen = next_wen; 141 | assign data_ren = next_ren; 142 | assign data_write = next_wdata; 143 | 144 | reg is_invalid; 145 | reg alu_store; 146 | reg alu_word; 147 | reg alu_carry; 148 | reg [7:0] alu_keep_sreg; 149 | 150 | // delayed by one cycle for the register file to finish loading 151 | reg prev_alu_store; 152 | reg prev_alu_word; 153 | reg prev_alu_carry; 154 | reg [7:0] prev_alu_keep_sreg; 155 | reg [5:0] prev_sel_Rd; 156 | 157 | // opcode registers 158 | wire [5:0] op_Rr = { opcode[9], opcode[3:0] }; // 0-31 159 | wire [5:0] op_Rd = opcode[8:4]; // 0-31 160 | wire [5:0] op_Rdi = { 1'b1, opcode[7:4] }; // 16-31 161 | wire [5:0] op_Rp = { 2'b11, opcode[5:4], 1'b0 }; // 24-30 162 | wire [7:0] op_K = { opcode[11:8], opcode[3:0] }; 163 | wire [5:0] op_Q = { opcode[13], opcode[11:10], opcode[2:0] }; 164 | 165 | // IN and OUT instructions 166 | wire [5:0] io_addr = { opcode[10:9], opcode[3:0] }; 167 | wire [2:0] op_bit_select = opcode[2:0]; 168 | wire op_bit_set = opcode[9]; 169 | wire op_brbx_bit_set = opcode[10]; 170 | 171 | // LD vs ST is in the 9th bit 172 | wire op_is_store = opcode[9]; 173 | 174 | // sign extended 12-bit value 175 | wire [15:0] simm12 = { 176 | {4{opcode[11]}}, 177 | opcode[11:0] 178 | }; 179 | 180 | // sign extended 7-bit value for branch instructions 181 | wire [15:0] simm7 = { 182 | {9{opcode[9]}}, 183 | opcode[9:3] 184 | }; 185 | 186 | // immediate word 6-bit values 187 | wire [5:0] immw6 = { opcode[7:6], opcode[3:0] }; 188 | 189 | // ALU to perform the operations 190 | reg [3:0] alu_op; 191 | reg [3:0] prev_alu_op; 192 | wire [15:0] alu_out; 193 | reg [7:0] alu_const_value; 194 | reg [7:0] prev_alu_const_value; 195 | reg alu_const; 196 | reg prev_alu_const; 197 | reg [7:0] next_sreg; 198 | wire [7:0] sreg_out; 199 | 200 | wire [15:0] alu_Rd = reg_Ra; 201 | wire [ 7:0] alu_Rr = prev_alu_const ? prev_alu_const_value : reg_Rb; // sometimes a constant value 202 | 203 | risc8_alu core_alu( 204 | .clk(clk), 205 | .reset(reset), 206 | .op(prev_alu_op), 207 | .use_carry(prev_alu_carry), 208 | .keep_sreg(prev_alu_keep_sreg), 209 | .Rd_in(alu_Rd), 210 | .Rr_in(alu_Rr), 211 | .R_out(alu_out), 212 | .sreg_in(sreg), 213 | .sreg_out(sreg_out) 214 | ); 215 | 216 | always @(posedge clk) if (reset) begin 217 | cycle <= 0; 218 | skip <= 0; 219 | reg_PC <= 0; 220 | reg_SP <= 16'h1000; 221 | sreg <= 0; 222 | addr <= 0; 223 | wen <= 0; 224 | ren <= 0; 225 | wdata <= 0; 226 | prev_alu_store <= 0; 227 | 228 | end else begin 229 | if (cycle == 0) 230 | $display("%04x: %04x %02x A[%d]=%04x B[%d]=%02x, %04x %x %02x %b = %04x => %d%s%s", 231 | reg_PC * 16'h2, 232 | opcode, 233 | sreg, 234 | sel_Ra, reg_Ra, 235 | sel_Rb, reg_Rb, 236 | alu_Rd, 237 | prev_alu_op, 238 | alu_Rr, 239 | prev_alu_carry, 240 | alu_out, 241 | prev_sel_Rd, 242 | prev_alu_store ? " WRITE" : "", 243 | skip ? " SKIP" : "" 244 | ); 245 | 246 | // only advance the PC if we are not in 247 | // a multi-cycle instruction and not a LPM 248 | if (force_PC || next_cycle == 0) 249 | reg_PC <= next_PC; 250 | 251 | reg_SP <= next_SP; 252 | sreg <= next_sreg; 253 | temp <= next_temp; 254 | cycle <= next_cycle; 255 | skip <= next_skip; 256 | prev_opcode <= opcode; 257 | 258 | addr <= next_addr; 259 | wen <= next_wen; 260 | ren <= next_ren; 261 | wdata <= next_wdata; 262 | 263 | // Since the register file takes a cycle to 264 | // read, update the actual destination 265 | // to write into the register file on the 266 | // following cycle, after the ALU has 267 | // finished the operation. 268 | prev_sel_Rd <= sel_Rd; 269 | prev_alu_op <= alu_op; 270 | prev_alu_store <= alu_store; 271 | prev_alu_carry <= alu_carry; 272 | prev_alu_keep_sreg <= alu_keep_sreg; 273 | prev_alu_const <= alu_const; 274 | prev_alu_const_value <= alu_const_value; 275 | prev_alu_word <= alu_word; 276 | 277 | if (is_invalid) 278 | $display("INVALID %04x", opcode); 279 | end 280 | 281 | wire [4:0] instr; 282 | wire [3:0] is_alu_op; 283 | wire is_alu_rdi; 284 | wire is_alu_store; 285 | wire is_alu_carry; 286 | risc8_instruction decoder( 287 | .opcode(opcode), 288 | .instr(instr), 289 | .alu_op(is_alu_op), 290 | .alu_store(is_alu_store), 291 | .alu_carry(is_alu_carry), 292 | .alu_rdi(is_alu_rdi) 293 | ); 294 | 295 | /*******************************/ 296 | reg do_sp_push; 297 | reg do_sp_pop; 298 | reg do_ldst; 299 | reg do_alu_ldst; 300 | reg do_reg_ldst; 301 | reg do_data_load; 302 | 303 | always @(*) begin 304 | // start pre-fetching the next PC if we are not in reset 305 | if (reset) 306 | next_PC = 0; 307 | else 308 | next_PC = reg_PC + 1; 309 | 310 | // most instructions are single cycle, no writes, no reads 311 | is_invalid = 0; 312 | next_sreg = sreg_out; 313 | next_cycle = 0; 314 | next_skip = 0; 315 | next_ren = 0; 316 | next_wen = 0; 317 | next_addr = 0; 318 | next_wdata = 0; 319 | next_temp = temp; 320 | force_PC = 0; 321 | next_SP = reg_SP; 322 | 323 | // micro-ops 324 | do_sp_push = 0; 325 | do_sp_pop = 0; 326 | do_ldst = 0; 327 | do_alu_ldst = 0; 328 | do_reg_ldst = 0; 329 | do_data_load = 0; 330 | 331 | // Default is to not store, but if commiting to the register 332 | // file is selected, then to store to the Rd value 333 | alu_store = 0; 334 | alu_word = 0; 335 | alu_const = 0; 336 | alu_const_value = 0; 337 | alu_carry = 0; 338 | alu_keep_sreg = 0; 339 | 340 | // default is to select the Rd and Rr from the opcode, 341 | // storing into Rd. Most instructions modify these 342 | alu_op = `OP_MOVE; 343 | sel_Ra = op_Rd; 344 | sel_Rb = op_Rr; 345 | sel_Rd = op_Rd; 346 | 347 | if (skip) begin 348 | // only a few instructions are multiple 349 | // bytes. Otherwise we only skip one PC. 350 | if (instr == `is_call 351 | || instr == `is_jmp 352 | || instr == `is_lds) begin 353 | force_PC = 1; 354 | next_cycle = 1; 355 | next_skip = 1; 356 | end 357 | end else 358 | 359 | (* full_case *) 360 | case(instr) 361 | `is_alu: begin 362 | alu_op = is_alu_op; 363 | alu_carry = is_alu_carry; 364 | alu_store = is_alu_store; 365 | 366 | if (is_alu_rdi) begin 367 | sel_Ra = op_Rdi; 368 | sel_Rd = op_Rdi; 369 | alu_const = 1; 370 | alu_const_value = op_K; 371 | end 372 | end 373 | 374 | `ifdef config_is_inc 375 | `is_inc: begin 376 | // INC Rd 377 | alu_op = `OP_ADD; 378 | alu_store = 1; 379 | alu_const = 1; 380 | alu_const_value = 1; 381 | alu_keep_sreg = 8'b1110_0001; // ITH____C 382 | end 383 | `endif 384 | `ifdef config_is_dec 385 | `is_dec: begin 386 | // DEC Rd 387 | alu_op = `OP_SUB; 388 | alu_store = 1; 389 | alu_const = 1; 390 | alu_const_value = 1; 391 | alu_keep_sreg = 8'b1110_0001; // ITH____C 392 | end 393 | `endif 394 | `ifdef config_is_com 395 | `is_com: begin 396 | // COM Rd 397 | alu_op = `OP_EOR; 398 | alu_store = 1; 399 | alu_const = 1; 400 | alu_const_value = 8'hFF; 401 | alu_carry = 1; 402 | end 403 | `endif 404 | `ifdef config_is_adiw_or_sbiw 405 | `is_adiw_or_sbiw: begin 406 | // ADIW/SBIW Rp, uimm6 407 | sel_Ra = op_Rp; 408 | sel_Rd = op_Rp; 409 | alu_store = 1; 410 | alu_word = 1; 411 | alu_const = 1; 412 | alu_const_value = immw6; 413 | 414 | if (opcode[8]) 415 | alu_op = `OP_SBW; 416 | else 417 | alu_op = `OP_ADW; 418 | end 419 | `endif 420 | `ifdef config_is_movw 421 | `is_movw: begin 422 | // MOVW Rd,Rr Move register pair 423 | sel_Ra = { opcode[3:0], 1'b0 }; // will read both bytes 424 | sel_Rd = { opcode[7:4], 1'b0 }; // will write both bytes 425 | alu_word = 1; 426 | alu_store = 1; 427 | end 428 | `endif 429 | `ifdef config_is_clx_or_sex 430 | `is_clx_or_sex: begin 431 | // Status register update bit 432 | // 16'b1001_0100_1???_1000: CLx 433 | // 16'b1001_0100_0???_1000: SEx 434 | alu_op = `OP_SREG; 435 | alu_carry = !opcode[7]; 436 | alu_const = 1; 437 | alu_const_value = opcode[6:4]; 438 | end 439 | `endif 440 | `ifdef config_is_mulu 441 | `is_mulu: begin 442 | // MULU Rd, Rr => R1/R0 443 | alu_op = `OP_MUL; 444 | alu_store = 1; 445 | alu_word = 1; 446 | sel_Rd = 0; 447 | end 448 | `endif 449 | 450 | `ifdef config_is_out 451 | // OUT to IO space (no sreg update) 452 | // the ones for registers are handled here, 453 | // otherwise the external controller will handle it 454 | // should be single cycle, except that reading 455 | // the register now takes a cycle 456 | `is_out: begin 457 | if(cycle[0] == 0) begin 458 | // wait for Rd to show up in Ra 459 | next_cycle = 1; 460 | end else begin 461 | next_wen = 1; 462 | next_wdata = reg_Ra; 463 | next_addr = io_addr + 8'h20; 464 | 465 | case(io_addr) 466 | 6'h3D: next_SP[ 7:0] = reg_Ra; 467 | 6'h3E: next_SP[15:8] = reg_Ra; 468 | 6'h3F: next_sreg = reg_Ra; 469 | default: begin 470 | // nothing to do here; 471 | // the SOC handles it 472 | end 473 | endcase 474 | end 475 | end 476 | `endif 477 | 478 | `ifdef config_is_in 479 | // IN from IO space (no sreg update, should be 1 cycle) 480 | // the registers ones are handled here, otherwise 481 | // the external SOC will handle it. 482 | `is_in: begin 483 | if(cycle[0] == 0) begin 484 | next_addr = io_addr + 8'h20; 485 | next_ren = 1; 486 | next_cycle = 1; 487 | end else begin 488 | alu_op = `OP_MOVR; 489 | alu_store = 1; 490 | alu_const = 1; 491 | case(io_addr) 492 | 6'h3D: alu_const_value = reg_SP[ 7:0]; 493 | 6'h3E: alu_const_value = reg_SP[15:8]; 494 | 6'h3F: alu_const_value = sreg; 495 | default: alu_const_value = data_read; // from the SOC 496 | endcase 497 | end 498 | end 499 | `endif 500 | 501 | `ifdef config_is_lds 502 | `is_lds: begin 503 | // LDS rdi,i / STS i,rdi 504 | // No sreg update 505 | // 2 cycles 506 | // Load or store instructions 507 | // followed by 16-bit immediate SRAM address 508 | sel_Rb = op_Rdi; 509 | sel_Rd = op_Rdi; 510 | 511 | case(cycle) 512 | 2'b00: begin 513 | // wait for the next read to get the address 514 | // for a STS the op_Rd will load the correct 515 | // register into reg_Ra by the next cycle 516 | force_PC = 1; 517 | next_cycle = 1; 518 | end 519 | 2'b01: begin 520 | next_addr = cdata; 521 | do_ldst = 1; 522 | end 523 | 2'b10: do_data_load = 1; 524 | endcase 525 | end 526 | `endif 527 | 528 | `ifdef config_is_ld_xyz 529 | `is_ld_xyz: begin 530 | case(opcode[3:2]) 531 | 2'b00: sel_Ra = BASE_Z; 532 | 2'b10: sel_Ra = BASE_Y; 533 | 2'b11: sel_Ra = BASE_X; 534 | endcase 535 | 536 | sel_Rb = op_Rd; 537 | sel_Rd = sel_Ra; 538 | 539 | case(cycle) 540 | 2'b00: begin 541 | // wait for the full X/Z register to fetch 542 | // as well as the contents of Rd 543 | next_cycle = 1; 544 | 545 | // setup an ALU operation to store a 546 | // whole word back into X/Z 547 | alu_word = 1; 548 | alu_const = 1; 549 | alu_const_value = 1; 550 | alu_keep_sreg = 8'b1111_1111; 551 | 552 | case(opcode[1:0]) 553 | 2'b01: begin 554 | // post-increment the register word 555 | alu_op = `OP_ADW; 556 | alu_store = 1; 557 | end 558 | 2'b10: begin 559 | // pre-decrement the register word 560 | alu_op = `OP_SBW; 561 | alu_store = 1; 562 | end 563 | endcase 564 | end 565 | 2'b01: begin 566 | // pointer word is in Ra, d is in Rb, 567 | // for a pre-decrement, pointer-1 is in alu_out 568 | if (opcode[1:0] == 2'b10) 569 | do_alu_ldst = 1; 570 | else 571 | do_reg_ldst = 1; 572 | end 573 | 2'b10: begin 574 | sel_Rd = op_Rd; 575 | do_data_load = 1; 576 | end 577 | endcase 578 | end 579 | `endif 580 | 581 | `ifdef config_is_ld_yz_plus_q 582 | `is_ld_yz_plus_q: begin 583 | // ST / LD Rd, Y/Z+Q (no status update) 584 | // Z+Q: 16'b10?0_????_????_0???: 585 | // Y+Q: 16'b10?0_????_????_1???: 586 | sel_Ra = opcode[3] ? BASE_Y : BASE_Z; 587 | sel_Rb = op_Rd; 588 | sel_Rd = op_Rd; 589 | 590 | case(cycle) 591 | 2'b00: begin 592 | // wait for the full Y or Z register, 593 | // with the immediate value added 594 | // to fetch as well as the contents of Rd 595 | alu_op = `OP_ADW; 596 | alu_const = 1; 597 | alu_const_value = op_Q; 598 | alu_keep_sreg = 8'b1111_1111; 599 | 600 | next_cycle = 1; 601 | end 602 | 2'b01: do_alu_ldst = 1; 603 | 2'b10: do_data_load = 1; 604 | endcase 605 | end 606 | `endif 607 | 608 | `ifdef config_is_lpm 609 | `is_lpm: begin 610 | // LPM/ELPM Rd, Z / Z+ 611 | sel_Ra = BASE_Z; 612 | sel_Rd = sel_Ra; 613 | 614 | case(cycle) 615 | 2'b00: begin 616 | // fetch the Z register 617 | next_cycle = 1; 618 | end 619 | 2'b01: begin 620 | // if this is Z+ mode, add one to Z 621 | alu_op = `OP_ADW; 622 | alu_store = 1; 623 | alu_word = 1; 624 | alu_const = 1; 625 | alu_const_value = opcode[0]; 626 | alu_keep_sreg = 8'b1111_1111; 627 | 628 | // start a read of the program memory space 629 | // storing the real next PC into the temp reg 630 | // PC is in words, not bytes 631 | force_PC = 1; 632 | next_PC = reg_Ra >> 1; 633 | next_temp = reg_PC; 634 | next_cycle = 2; 635 | end 636 | 2'b10: begin 637 | // store the correct byte of read data into Rd 638 | // based on the bottom bit of the original Z 639 | alu_op = `OP_MOVR; 640 | alu_store = 1; 641 | alu_const = 1; 642 | alu_const_value = reg_Ra[0] ? cdata[15:8] : cdata[7:0]; 643 | sel_Rd = op_Rd; 644 | 645 | // Exception for simple LPM 646 | if(opcode == 16'b1001_0101_1100_1000) sel_Rd = 0; 647 | 648 | // restore the PC, and do one more cycle 649 | // so that the next_PC will prefetch the 650 | // correct next instruction 651 | force_PC = 1; 652 | next_PC = temp; 653 | next_cycle = 3; 654 | end 655 | 2'b11: begin 656 | // nothing to do, just allow prefetch to work 657 | end 658 | endcase 659 | end 660 | `endif 661 | 662 | /* 663 | 16'b1001001_?????_0100: begin 664 | // XCH Z,Rd 665 | invalid_op = 1; 666 | end 667 | 16'b1001001_?????_0101: begin 668 | // LAS Z,Rd 669 | invalid_op = 1; 670 | end 671 | 16'b1001001_?????_0110: begin 672 | // LAC Z,Rd 673 | invalid_op = 1; 674 | end 675 | 16'b1001001_?????_0111: begin 676 | // LAT Z,Rd 677 | invalid_op = 1; 678 | end 679 | if (do_ldst) begin 680 | if (op_is_store) begin 681 | // STS (no extra cycle needed) 682 | next_wen = 1; 683 | next_wdata = reg_Rb; 684 | end else begin 685 | // LD (one more cycle required) 686 | next_ren = 1; 687 | next_cycle = 2; 688 | end 689 | end 690 | */ 691 | 692 | `ifdef config_is_push 693 | `is_push: begin 694 | next_wdata = reg_Ra[7:0]; 695 | 696 | // PUSH Rd 697 | // delay one cycle until we have the Rd 698 | // available in register A 699 | if(cycle[0] == 0) 700 | next_cycle = 1; 701 | else 702 | do_sp_push = 1; 703 | end 704 | `endif 705 | 706 | `ifdef config_is_pop 707 | `is_pop: begin 708 | // POP Rd 709 | // start the read and load the data into Rd 710 | // once it is ready on the next cycle 711 | if(cycle[0] == 0) begin 712 | do_sp_pop = 1; 713 | next_cycle = 1; 714 | end else 715 | do_data_load = 1; 716 | end 717 | `endif 718 | 719 | `ifdef config_is_ret 720 | `is_ret: begin 721 | // RET 722 | case(cycle) 723 | 2'b00: begin 724 | do_sp_pop = 1; 725 | next_cycle = 1; 726 | end 727 | 2'b01: begin 728 | do_sp_pop = 1; 729 | next_temp[7:0] = data_read; 730 | next_cycle = 2; 731 | end 732 | 2'b10: begin 733 | next_PC = { temp[7:0], data_read }; 734 | end 735 | endcase 736 | end 737 | `endif 738 | 739 | `ifdef config_is_cpse 740 | // CPSE Rd,Rr 741 | `is_cpse: begin 742 | // wait for Rd and Rr to be available 743 | if (cycle[0] == 0) 744 | next_cycle = 1; 745 | else 746 | if (reg_Ra[7:0] == reg_Rb) 747 | next_skip = 1; 748 | end 749 | `endif 750 | 751 | `ifdef config_is_sbrc_or_sbrs 752 | // SBRC/SBRS skip if register bit b equals B 753 | `is_sbrc_or_sbrs: begin 754 | // 16'b1111_110?_????_0???, // SBRC 755 | // 16'b1111_111?_????_0???: // SBRS 756 | if(cycle[0] == 0) 757 | next_cycle = 1; 758 | else 759 | if (reg_Ra[op_bit_select] == op_bit_set) 760 | next_skip = 1; 761 | end 762 | `endif 763 | 764 | `ifdef config_is_brbc_or_brbs 765 | // BRBS/BRBC - Branch if bit in SREG is set/clear 766 | // this happens while the ALU is still computing the 767 | // previous instruction, so use the next SREG value, 768 | // not the current register. 769 | `is_brbc_or_brbs: begin 770 | // 16'b1111_00??_????_????, // BRBS 771 | // 16'b1111_01??_????_????: // BRBC 772 | if (next_sreg[op_bit_select] != op_brbx_bit_set) 773 | next_PC = reg_PC + simm7 + 1; 774 | end 775 | `endif 776 | 777 | `ifdef config_is_bld_or_bst 778 | // BLD - Bit Load from the T Bit in SREG to a Bit in Register 779 | // BST - Bit Store from Bit in Register to T Bit in SREG 780 | // 16'b1111_100?_????_0??? // BLD 781 | // 16'b1111_101?_????_0??? // BST 782 | // ^ Bit 9 (BLD / BST) 783 | `is_bld_or_bst: begin 784 | alu_op = `OP_SREG; 785 | alu_const = 1; 786 | alu_const_value = {1'b1, opcode[2:0]}; 787 | alu_carry = opcode[9]; 788 | alu_store = !opcode[9]; 789 | end 790 | `endif 791 | 792 | `ifdef config_is_jmp 793 | `is_jmp: begin 794 | // JMP abs22, 3 cycles 795 | // 16'b1001_010?_????_110?: 796 | // 16 bits in next word 797 | case(cycle) 798 | 2'b00: begin 799 | next_cycle = 1; 800 | force_PC = 1; 801 | end 802 | 2'b01: begin 803 | // cdata now has the destination address 804 | // start pre-fetch of next_PC 805 | next_PC = cdata; 806 | force_PC = 1; 807 | next_cycle = 2; 808 | end 809 | 2'b10: begin 810 | // should be ready 811 | end 812 | endcase 813 | end 814 | `endif 815 | 816 | `ifdef config_is_call 817 | `is_call: begin 818 | // CALL abs22 819 | // 16'b1001_010?_????_111?: 820 | // 16 bits in next word 821 | case(cycle) 822 | 2'b00: begin 823 | next_cycle = 1; 824 | force_PC = 1; 825 | end 826 | 2'b01: begin 827 | // cdata now has the destination address 828 | // start pushing next_PC 829 | do_sp_push = 1; 830 | next_temp = cdata; 831 | next_wdata = next_PC[7:0]; 832 | next_cycle = 2; 833 | end 834 | 2'b10: begin 835 | // write the second half of the return address 836 | next_wdata = next_PC[15:8]; 837 | do_sp_push = 1; 838 | next_cycle = 3; 839 | end 840 | 2'b11: begin 841 | // 22-bit PC has extra bits in opcode 842 | // but we are a 16-bit PC CPU, so ignored 843 | next_PC = temp; 844 | end 845 | endcase 846 | end 847 | `endif 848 | 849 | `ifdef config_is_ijmp 850 | `is_ijmp: begin 851 | // IJMP Z - Indirect jump/call to Z or EIND:Z 852 | // 16'b1001_010?_000?_1001: 853 | // 2 cycles 854 | sel_Ra = BASE_Z; 855 | if(cycle[0] == 0) 856 | next_cycle = 1; 857 | else 858 | next_PC = reg_Ra; 859 | end 860 | `endif 861 | 862 | `ifdef config_is_rjmp 863 | `is_rjmp: begin 864 | // RJMP to PC + simm12 865 | // 16'b1100_????????????: 866 | // 2 cycles 867 | next_PC = reg_PC + simm12 + 1; 868 | end 869 | `endif 870 | 871 | `ifdef config_is_rcall 872 | `is_rcall: begin 873 | // RCALL to PC + simm12 874 | // 16'b1101_????????????: 875 | // 3 cycles 876 | case(cycle) 877 | 2'b00: begin 878 | // push the first half of the PC 879 | do_sp_push = 1; 880 | next_wdata = next_PC[7:0]; // pc + 1 881 | next_cycle = 1; 882 | end 883 | 2'b01: begin 884 | // push the second half 885 | do_sp_push = 1; 886 | next_wdata = next_PC[15:8]; // pc + 1 887 | next_cycle = 2; 888 | end 889 | 2'b10: begin 890 | // and do the jump 891 | next_PC = reg_PC + simm12 + 1; 892 | force_PC = 1; 893 | end 894 | endcase 895 | end 896 | `endif 897 | 898 | `ifdef config_is_sbis_or_sbic 899 | // Skip if bit in IO space is set or clear. 900 | `is_sbis_or_sbic: begin 901 | if (cycle[0] == 0) begin 902 | next_addr = opcode[7:3] + 8'h20; 903 | next_ren = 1; 904 | next_cycle = 1; 905 | end else 906 | if (data_read[op_bit_select] == op_bit_set) 907 | next_skip = 1; 908 | end 909 | `endif 910 | 911 | default: begin 912 | is_invalid = 1; 913 | end 914 | endcase 915 | 916 | 917 | /* 918 | * Micro-ops 919 | */ 920 | 921 | // post-decrement the stack pointer 922 | // and start a write of next_wdata to the stack 923 | if (do_sp_push) begin 924 | next_wen = 1; 925 | next_addr = reg_SP; 926 | next_SP = reg_SP - 1; 927 | end 928 | 929 | // pre-increment the stack pointer 930 | // and start a read of the stack, will be in read_data 931 | if (do_sp_pop) begin 932 | next_ren = 1; 933 | next_addr = reg_SP + 1; 934 | next_SP = reg_SP + 1; 935 | end 936 | 937 | // complete a load/store using either the ALU 938 | // or Ra output 939 | if (do_alu_ldst) begin 940 | next_addr = alu_out; 941 | do_ldst = 1; 942 | end 943 | if (do_reg_ldst) begin 944 | next_addr = reg_Ra; 945 | do_ldst = 1; 946 | end 947 | 948 | // continue a load from the address in next_addr, 949 | // using the data into Rb. This must be called 950 | // on cycle 1 (or else the next_cycle will be wrong). 951 | if (do_ldst) begin 952 | if (op_is_store) begin 953 | // STS (no extra cycle needed) 954 | next_wen = 1; 955 | next_wdata = reg_Rb; 956 | end else begin 957 | // LD (one more cycle required) 958 | next_ren = 1; 959 | next_cycle = 2; 960 | end 961 | end 962 | 963 | // finish a load by copying the data into Rd 964 | if (do_data_load) begin 965 | // extra cycle only for LD 966 | // the memory has loaded the value, 967 | // so use the ALU to store into Rd 968 | alu_op = `OP_MOVR; 969 | alu_store = 1; 970 | alu_const = 1; 971 | alu_const_value = data_read; 972 | end 973 | end 974 | endmodule 975 | 976 | `endif 977 | -------------------------------------------------------------------------------- /risc8-dev.v: -------------------------------------------------------------------------------- 1 | `ifndef _risc8_dev_ 2 | `define _risc8_dev_ 3 | /* 4 | * IO bus peripherals. 5 | */ 6 | `include "uart.v" 7 | `ifndef UART_DIV 8 | `define UART_DIV 5 9 | `endif 10 | 11 | module risc8_uart( 12 | input clk, 13 | input reset, 14 | // IO bus 15 | input ren, 16 | input wen, 17 | input [6:0] addr, 18 | input [7:0] wdata, 19 | output reg [7:0] rdata, 20 | output reg valid, 21 | // physical 22 | input rx_in, 23 | output tx_out 24 | ); 25 | parameter BASE = 7'h2D; 26 | reg [7:0] uart_baud_div = `UART_DIV; 27 | reg [7:0] uart_tx_data; 28 | reg uart_tx_strobe; 29 | wire uart_tx_ready; 30 | 31 | wire [7:0] uart_status_reg = { 7'b0000000, uart_tx_ready }; 32 | 33 | uart uart( 34 | .clk(clk), 35 | .reset(reset), 36 | .baud_div(uart_baud_div), 37 | .tx_strobe(uart_tx_strobe), 38 | .tx_data(uart_tx_data), 39 | .tx_ready(uart_tx_ready), 40 | .tx_out(tx_out) 41 | //.rx_strobe(uart_rx_ 42 | //.rx_data(usidr 43 | ); 44 | 45 | always @(posedge clk) begin 46 | uart_tx_strobe <= 0; 47 | valid <= 0; 48 | 49 | if (wen) case(addr) 50 | BASE + 0: uart_baud_div <= wdata; 51 | BASE + 2: { uart_tx_data, uart_tx_strobe } <= { wdata, 1'b1 }; 52 | endcase 53 | 54 | if (ren) case(addr) 55 | BASE + 0: { rdata, valid } <= { uart_baud_div, 1'b1 }; 56 | BASE + 1: { rdata, valid } <= { uart_status_reg, 1'b1 }; 57 | endcase 58 | end 59 | endmodule 60 | 61 | module risc8_timer( 62 | input clk, 63 | input reset, 64 | // IO bus 65 | input ren, 66 | input wen, 67 | input [6:0] addr, 68 | input [7:0] wdata, 69 | output reg [7:0] rdata, 70 | output reg valid 71 | ); 72 | parameter BASE = 7'h4F; 73 | 74 | // timer running at the clock speed 75 | reg [7:0] tcnt1 = 8'h55; 76 | 77 | always @(posedge clk) begin 78 | valid <= 0; 79 | tcnt1 <= tcnt1 + 1; 80 | 81 | if (wen) case(addr) 82 | BASE + 0: tcnt1 <= wdata; 83 | endcase 84 | 85 | if (ren) case(addr) 86 | BASE + 0: { rdata, valid } <= { tcnt1, 1'b1 }; 87 | endcase 88 | end 89 | endmodule 90 | 91 | module risc8_gpio( 92 | input clk, 93 | input reset, 94 | // IO bus 95 | input ren, 96 | input wen, 97 | input [6:0] addr, 98 | input [7:0] wdata, 99 | output reg [7:0] rdata, 100 | output reg valid, 101 | // physical 102 | output [7:0] port, 103 | input [7:0] pin, 104 | output [7:0] ddr 105 | ); 106 | parameter BASE = 7'h36; 107 | reg [7:0] port; 108 | reg [7:0] ddr; 109 | 110 | always @(posedge clk) begin 111 | if (reset) begin 112 | port <= 0; 113 | ddr <= 0; 114 | end 115 | 116 | valid <= 0; 117 | 118 | if (wen) case(addr) 119 | //BASE + 0: pin <= wdata; 120 | BASE + 1: ddr <= wdata; 121 | BASE + 2: begin 122 | $display("PORT %02x", wdata); 123 | port <= wdata; 124 | end 125 | endcase 126 | 127 | if (ren) case(addr) 128 | BASE + 0: { rdata, valid } <= { pin, 1'b1 }; 129 | BASE + 1: { rdata, valid } <= { ddr, 1'b1 }; 130 | BASE + 2: { rdata, valid } <= { port, 1'b1 }; 131 | endcase 132 | end 133 | endmodule 134 | 135 | `endif 136 | -------------------------------------------------------------------------------- /risc8-instr.v: -------------------------------------------------------------------------------- 1 | `ifndef _risc8_instruction_v_ 2 | `define _risc8_instruction_v_ 3 | /* 4 | * Decode the RISC-8 instruction opcodes into macro instructions 5 | * and src/dest registers. 6 | * 7 | * The single cycle instructions are grouped first. 8 | */ 9 | 10 | // Single cycle arithmetic operators mostly go straight to the alu 11 | // op Rd, Rr 12 | `define is_alu 5'h00 13 | 14 | // although some require special handling 15 | `define is_inc 5'h01 16 | `define is_dec 5'h02 17 | `define is_com 5'h03 18 | `define is_adiw_or_sbiw 5'h04 19 | `define is_movw 5'h05 20 | `define is_clx_or_sex 5'h06 21 | `define is_mulu 5'h07 22 | 23 | // Memory instructions 24 | `define is_out 5'h08 25 | `define is_in 5'h09 26 | `define is_lds 5'h0a 27 | `define is_ld_xyz 5'h0b 28 | `define is_ld_yz_plus_q 5'h0c 29 | `define is_lpm 5'h0d 30 | `define is_pop 5'h0e 31 | `define is_push 5'h0f 32 | 33 | // Control flow instructions 34 | `define is_ret 5'h10 35 | `define is_cpse 5'h11 36 | `define is_sbrc_or_sbrs 5'h12 37 | `define is_brbc_or_brbs 5'h13 38 | `define is_jmp 5'h14 39 | `define is_call 5'h15 40 | `define is_ijmp 5'h16 41 | `define is_rjmp 5'h17 42 | `define is_rcall 5'h18 43 | `define is_sbis_or_sbic 5'h19 44 | `define is_bld_or_bst 5'h1a 45 | 46 | module risc8_instruction( 47 | input [15:0] opcode, 48 | output [4:0] instr, 49 | output [3:0] alu_op, 50 | output alu_rdi, 51 | output alu_store, 52 | output alu_carry 53 | ); 54 | // Register in the opcode 55 | wire [5:0] op_Rd = opcode[8:4]; // 0-31 56 | 57 | /* Instruction decoding */ 58 | reg [4:0] instr; 59 | reg [3:0] alu_op; 60 | reg alu_store; 61 | reg alu_carry; 62 | reg alu_rdi; 63 | 64 | `define ALU_OP(op, store, carry) \ 65 | begin \ 66 | alu_op = op; \ 67 | alu_store = store; \ 68 | alu_carry = carry; \ 69 | end 70 | 71 | `define ALU_OP_RDI(op, store, carry) \ 72 | begin \ 73 | alu_op = op; \ 74 | alu_store = store; \ 75 | alu_carry = carry; \ 76 | alu_rdi = 1; \ 77 | end 78 | 79 | /* 80 | * Match instructions on every bit except for the 81 | * five Rd bits (opcode[8:4]), which are wildcard 82 | * for almost every instruction. 83 | */ 84 | always @(*) begin 85 | instr = `is_alu; 86 | alu_op = 0; 87 | alu_store = 0; 88 | alu_carry = 0; 89 | alu_rdi = 0; 90 | 91 | casez({opcode[15:9],opcode[3:0]}) 92 | 11'b0000_000_????: if (opcode[8] == 1'b1) instr = `is_movw; // else NOP 93 | 11'b0000_01?_????: `ALU_OP(`OP_SUB, 0, 1) // CPC Rd,Rr 94 | 11'b0000_10?_????: `ALU_OP(`OP_SUB, 1, 1) // SBC Rd, Rr 95 | 11'b0000_11?_????: `ALU_OP(`OP_ADD, 1, 0) // ADD Rd, Rd 96 | 11'b0001_00?_????: instr = `is_cpse; 97 | 11'b0001_01?_????: `ALU_OP(`OP_SUB, 0, 0) // CP Rd,Rr 98 | 11'b0001_10?_????: `ALU_OP(`OP_SUB, 1, 0) // SUB Rd, Rr 99 | 11'b0001_11?_????: `ALU_OP(`OP_ADD, 1, 1) // ADC Rd, Rr 100 | 11'b0010_00?_????: `ALU_OP(`OP_AND, 1, 0) // AND Rd, Rr 101 | 11'b0010_01?_????: `ALU_OP(`OP_EOR, 1, 0) // EOR Rd, Rr 102 | 11'b0010_10?_????: `ALU_OP(`OP_OR, 1, 0) // OR Rd, Rr 103 | 11'b0010_11?_????: `ALU_OP(`OP_MOVR, 1, 0) // MOV Rd, Rr 104 | 11'b0011_???_????: `ALU_OP_RDI(`OP_SUB, 0, 0) // CPI Rdi, K 105 | 11'b0100_???_????: `ALU_OP_RDI(`OP_SUB, 1, 1) // SBCI Rdi, K 106 | 11'b0101_???_????: `ALU_OP_RDI(`OP_SUB, 1, 0) // SUBI Rdi, K 107 | 11'b0110_???_????: `ALU_OP_RDI(`OP_OR, 1, 0) // ORI Rdi, K 108 | 11'b0111_???_????: `ALU_OP_RDI(`OP_AND, 1, 0) // ANDI Rdi, K 109 | 11'b1001_00?_0000: instr = `is_lds; 110 | 11'b1001_000_010?: instr = `is_lpm; // Z 111 | 11'b1000_00?_0000: instr = `is_ld_xyz; // z 112 | 11'b1000_00?_1000: instr = `is_ld_xyz; // Y 113 | 11'b1001_00?_1100: instr = `is_ld_xyz; // X 114 | 11'b1001_00?_0001: instr = `is_ld_xyz; // Z+ 115 | 11'b1001_00?_0010: instr = `is_ld_xyz; // -Z 116 | 11'b1001_00?_1001: instr = `is_ld_xyz; // Y+ 117 | 11'b1001_00?_1010: instr = `is_ld_xyz; // -Y 118 | 11'b1001_00?_1101: instr = `is_ld_xyz; // X+ 119 | 11'b1001_00?_1110: instr = `is_ld_xyz; // -X 120 | 11'b10?0_???_????: instr = `is_ld_yz_plus_q; 121 | 11'b1001_000_1111: instr = `is_pop; 122 | 11'b1001_001_1111: instr = `is_push; 123 | 11'b1001_010_0000: instr = `is_com; 124 | 11'b1001_010_0001: `ALU_OP(`OP_NEG, 1, 0) // NEG Rd 125 | 11'b1001_010_0010: `ALU_OP(`OP_SWAP, 1, 0) // SWAP Rd 126 | 11'b1001_010_0011: instr = `is_inc; // INC Rd 127 | //11'b1001_010?_0100: instr = `is_nop; // reserved 128 | 11'b1001_010_0101: `ALU_OP(`OP_ASR, 1, 0) // ASR Rd 129 | 11'b1001_010_0110: `ALU_OP(`OP_LSR, 1, 0) // LSR Rd 130 | 11'b1001_010_0111: `ALU_OP(`OP_ROR, 1, 0) // ROR Rd 131 | 11'b1001_010_1000: begin 132 | casez(opcode[8:4]) 133 | 5'b0????: instr = `is_clx_or_sex; 134 | 5'b10000: instr = `is_ret; 135 | 5'b11100: instr = `is_lpm; 136 | endcase 137 | end 138 | 11'b1001_010_1001: instr = `is_ijmp; 139 | 11'b1001_010_1010: instr = `is_dec; // DEC Rd 140 | 11'b1001_010_110?: instr = `is_jmp; 141 | 11'b1001_010_1111: instr = `is_call; 142 | 11'b1001_011_????: instr = `is_adiw_or_sbiw; 143 | 11'b1001_11?_????: instr = `is_mulu; 144 | 11'b1001_10?_????: instr = `is_sbis_or_sbic; 145 | 11'b1011_0??_????: instr = `is_in; 146 | 11'b1011_1??_????: instr = `is_out; 147 | 11'b1100_???_????: instr = `is_rjmp; 148 | 11'b1101_???_????: instr = `is_rcall; 149 | 11'b1110_???_????: `ALU_OP_RDI(`OP_MOVR, 1, 0) // LDI Rdi, K also SER, with all 1 150 | 11'b1111_0??_????: instr = `is_brbc_or_brbs; 151 | 11'b1111_10?_0???: instr = `is_bld_or_bst; 152 | 11'b1111_11?_0???: instr = `is_sbrc_or_sbrs; 153 | endcase 154 | end 155 | endmodule 156 | 157 | `endif 158 | -------------------------------------------------------------------------------- /risc8-ram.v: -------------------------------------------------------------------------------- 1 | `ifndef _risc8_ram_ 2 | `define _risc8_ram_ 3 | 4 | `ifdef FPGA_ICE40UP5K 5 | /* 6 | * ice40up5k has 256 Kbit single port block RAMs that are perfect 7 | * for the risc8 memory since there are either read or write cycles. 8 | * The SPRAMs can't be initialized in the bitstream, so the startup code 9 | * in the CPU is responsible for copying data to the RAM. 10 | * 11 | * They are fixed in 16-bit widths, so a wrapper is needed to make them 12 | * byte addressable. 13 | */ 14 | 15 | module ice40up5k_spram( 16 | input clk, 17 | input cs, 18 | input wen, 19 | input [14:0] addr, 20 | input [7:0] wdata, 21 | output [7:0] rdata 22 | ); 23 | wire align = addr[0]; 24 | wire [15:0] rdata16; 25 | reg byte; 26 | assign rdata = byte ? rdata16[15:8] : rdata16[7:0]; 27 | 28 | always @(posedge clk) 29 | byte <= align; 30 | 31 | SB_SPRAM256KA spram ( 32 | .CLOCK(clk), 33 | .CHIPSELECT(cs), 34 | .WREN(wen), 35 | .ADDRESS(addr[14:1]), 36 | .DATAOUT(rdata16), 37 | .DATAIN({wdata, wdata}), 38 | .MASKWREN({align, align, !align, !align}), 39 | .STANDBY(1'b0), 40 | .SLEEP(1'b0), 41 | .POWEROFF(1'b1) 42 | ); 43 | endmodule 44 | 45 | 46 | /* 47 | * Bond together two SPRAM's to make one 64 KB data RAM for 48 | * the risc8 CPU. Since `addr` can change after a read, it is 49 | * necessary to buffer the `bank` that the address needs. 50 | */ 51 | module risc8_ram( 52 | input clk, 53 | input wen, 54 | input [15:0] addr, 55 | input [7:0] wdata, 56 | output [7:0] rdata 57 | ); 58 | 59 | wire [7:0] rdata_00, rdata_01; 60 | wire [7:0] rdata = bank ? rdata_01 : rdata_00; 61 | reg bank; 62 | 63 | always @(posedge clk) 64 | bank <= addr[15]; 65 | 66 | ice40up5k_spram spram00( 67 | .clk(clk), 68 | .cs(addr[15] == 1'b0), 69 | .wen(wen), 70 | .addr(addr[14:0]), 71 | .rdata(rdata_00), 72 | .wdata(wdata) 73 | ); 74 | 75 | ice40up5k_spram spram01( 76 | .clk(clk), 77 | .cs(addr[15] == 1'b1), 78 | .wen(wen), 79 | .addr(addr[14:0]), 80 | .rdata(rdata_01), 81 | .wdata(wdata) 82 | ); 83 | endmodule 84 | 85 | `else 86 | 87 | /* 88 | * Fall back for simulation or other FPGAs 89 | */ 90 | module risc8_ram( 91 | input clk, 92 | input wen, 93 | input [15:0] addr, 94 | input [7:0] wdata, 95 | output [7:0] rdata 96 | ); 97 | reg [7:0] ram[0:65535]; 98 | reg [7:0] rdata; 99 | 100 | always @(posedge clk) 101 | begin 102 | rdata <= ram[addr]; 103 | if (wen) 104 | ram[addr] <= wdata; 105 | end 106 | 107 | endmodule 108 | 109 | `endif 110 | 111 | `endif 112 | -------------------------------------------------------------------------------- /risc8-regs.v: -------------------------------------------------------------------------------- 1 | `ifndef _risc8_regfile_v_ 2 | `define _risc8_regfile_v_ 3 | 4 | /* 5 | * The block RAM regfile has a limitation that writes are not available 6 | * until the next clock cycle. 7 | * 8 | * The A register can be a pair of registers, while the B is always one byte. 9 | */ 10 | module risc8_regs( 11 | input clk, 12 | input reset, 13 | 14 | // read ports 15 | input [5:0] a, 16 | input [5:0] b, 17 | output [15:0] Ra, 18 | output [7:0] Rb, 19 | 20 | // write port 21 | input write, 22 | input write_word, 23 | input [5:0] d, 24 | input [15:0] Rd 25 | ); 26 | // duplicate the register file so that we can emulate a 27 | // dual-read port, single-write port block RAM 28 | // 32 8-bit registers == 16 16-bit words 29 | reg [15:0] ram_a[0:15]; 30 | reg [15:0] ram_b[0:15]; 31 | 32 | // there has to be a better way to do this 33 | initial $readmemh("zero.hex", ram_a); 34 | initial $readmemh("zero.hex", ram_b); 35 | 36 | wire [4:0] a_word = a[5:1]; 37 | wire [4:0] b_word = b[5:1]; 38 | wire [4:0] d_word = d[5:1]; 39 | 40 | reg [1:0] al_src; 41 | reg [1:0] ah_src; 42 | reg [1:0] bl_src; 43 | 44 | reg [15:0] Ra_ram; 45 | reg [15:0] Rb_ram; 46 | 47 | reg [15:0] Ra; 48 | reg [ 7:0] Rb; 49 | reg [15:0] cache_Rd; 50 | 51 | always @(posedge clk) if (!reset) begin 52 | Ra_ram <= ram_a[a_word]; 53 | Rb_ram <= ram_b[b_word]; 54 | 55 | // default source is from the ram read 56 | // with the correct byte selected from the a and b address 57 | al_src <= { 1'b0, a[0] }; 58 | ah_src <= { 1'b0, 1'b1 }; 59 | bl_src <= { 1'b0, b[0] }; 60 | 61 | if (write) begin 62 | cache_Rd <= Rd; 63 | 64 | if (write_word) begin 65 | // assume aligned write for d 66 | ram_a[d_word][15:0] <= Rd; 67 | ram_b[d_word][15:0] <= Rd; 68 | 69 | // check for cache hit 70 | if (a_word == d_word) begin 71 | if (a[0] == 0) begin 72 | // replace both bytes from the cache 73 | al_src <= 2'b10; 74 | ah_src <= 2'b11; 75 | end else 76 | if (a[0] == 1) begin 77 | // replace bottom byte from top byte 78 | al_src <= 2'b11; 79 | end 80 | end 81 | 82 | if (b_word == d_word) begin 83 | if (b[0] == 0) begin 84 | // low byte of cache 85 | bl_src <= 2'b10; 86 | end else begin 87 | // high byte of cache 88 | bl_src <= 2'b11; 89 | end 90 | end 91 | end else 92 | if (d[0] == 0) begin 93 | // low byte write 94 | //$display("R[%dL] <= %02x", d_word, Rd[7:0]); 95 | ram_a[d_word][7:0] <= Rd[7:0]; 96 | ram_b[d_word][7:0] <= Rd[7:0]; 97 | 98 | if (a_word == d_word && a[0] == 0) begin 99 | // cache hit on low byte of A 100 | al_src <= 2'b10; 101 | end 102 | 103 | if (b == d) begin 104 | // cache hit on low byte of B 105 | bl_src <= 2'b10; 106 | end 107 | end else begin 108 | // high byte write 109 | //$display("R[%dH] <= %02x", d_word, Rd[7:0]); 110 | ram_a[d_word][15:8] <= Rd[7:0]; 111 | ram_b[d_word][15:8] <= Rd[7:0]; 112 | 113 | if (a_word == d_word) begin 114 | if (a[0] == 0) begin 115 | // cache hit on high byte of A 116 | ah_src <= 2'b10; 117 | end else begin 118 | // cache hit on low byte of A 119 | al_src <= 2'b10; 120 | end 121 | end 122 | 123 | if (b == d) begin 124 | // cache hit on low byte of D 125 | bl_src <= 2'b10; 126 | end 127 | end 128 | end 129 | end 130 | 131 | // satisfy reads from the cache 132 | always @(*) begin 133 | case(al_src) 134 | 2'b00: Ra[7:0] = Ra_ram[7:0]; 135 | 2'b01: Ra[7:0] = Ra_ram[15:8]; 136 | 2'b10: Ra[7:0] = cache_Rd[7:0]; 137 | 2'b11: Ra[7:0] = cache_Rd[15:8]; 138 | endcase 139 | 140 | case(ah_src) 141 | 2'b00: Ra[15:8] = Ra_ram[7:0]; 142 | 2'b01: Ra[15:8] = Ra_ram[15:8]; 143 | 2'b10: Ra[15:8] = cache_Rd[7:0]; 144 | 2'b11: Ra[15:8] = cache_Rd[15:8]; 145 | endcase 146 | 147 | case(bl_src) 148 | 2'b00: Rb[7:0] = Rb_ram[7:0]; 149 | 2'b01: Rb[7:0] = Rb_ram[15:8]; 150 | 2'b10: Rb[7:0] = cache_Rd[7:0]; 151 | 2'b11: Rb[7:0] = cache_Rd[15:8]; 152 | endcase 153 | end 154 | endmodule 155 | 156 | `endif 157 | -------------------------------------------------------------------------------- /risc8-soc.v: -------------------------------------------------------------------------------- 1 | `ifndef _risc8_soc_v_ 2 | `define _risc8_soc_v_ 3 | 4 | `default_nettype none 5 | `include "risc8-core.v" 6 | `include "risc8-ram.v" 7 | `include "risc8-dev.v" 8 | 9 | `ifndef RISC8_PROGRAM 10 | `define RISC8_PROGRAM "program.syn.hex" 11 | `endif 12 | 13 | 14 | 15 | module risc8_soc( 16 | input clk, 17 | input reset, 18 | 19 | output [7:0] port_b, 20 | input [7:0] pin_b, 21 | output [7:0] ddr_b, 22 | output serial_tx, 23 | input serial_rx 24 | ); 25 | localparam CODEBITS = 12; 26 | 27 | // code memory (stored in normal block RAM) 28 | reg [15:0] code[0:(1 << CODEBITS) - 1]; 29 | reg [15:0] cdata; 30 | wire [15:0] pc; 31 | `ifdef RISC8_PROGRAM 32 | initial $readmemh(`RISC8_PROGRAM, code); 33 | `endif 34 | 35 | always @(posedge clk) 36 | cdata <= code[pc[CODEBITS-1:0]]; 37 | 38 | 39 | // data memory (stored in up5k SPRAM or in normal block RAM) 40 | // byte addressable, single port, either read or write but not both 41 | wire [15:0] addr; 42 | wire [7:0] ram_data; 43 | wire [7:0] wdata; 44 | wire wen; 45 | wire ren; 46 | 47 | risc8_ram ram( 48 | .clk(clk), 49 | .wen(wen), 50 | .addr(addr), 51 | .wdata(wdata), 52 | .rdata(ram_data) 53 | ); 54 | 55 | // IO mapped peripherals are at the bottom 64-bytes of RAM 56 | wire [6:0] io_addr = addr[6:0]; 57 | wire io_sel = addr[15:7] == 0; 58 | wire io_ren = io_sel & ren; 59 | wire io_wen = io_sel & wen; 60 | 61 | // uart on the serial pins 62 | wire [7:0] uart_data; 63 | wire uart_valid; 64 | risc8_uart uart( 65 | .clk(clk), 66 | .reset(reset), 67 | // logical 68 | .addr(io_addr), 69 | .ren(io_ren), 70 | .wen(io_wen), 71 | .wdata(wdata), 72 | .rdata(uart_data), 73 | .valid(uart_valid), 74 | // physical 75 | .tx_out(serial_tx) 76 | ); 77 | 78 | // timer 79 | wire [7:0] tcnt1_data; 80 | wire tcnt1_valid; 81 | risc8_timer #(.BASE(7'h3F)) tcnt1( 82 | .clk(clk), 83 | .reset(reset), 84 | // logical 85 | .addr(io_addr), 86 | .ren(io_ren), 87 | .wen(io_wen), 88 | .wdata(wdata), 89 | .rdata(tcnt1_data), 90 | .valid(tcnt1_valid) 91 | ); 92 | 93 | // gpio for port b 94 | wire [7:0] portb_data; 95 | wire portb_valid; 96 | risc8_gpio #(.BASE(7'h36)) portb_dev( 97 | .clk(clk), 98 | .reset(reset), 99 | // logical 100 | .addr(io_addr), 101 | .ren(io_ren), 102 | .wen(io_wen), 103 | .wdata(wdata), 104 | .rdata(portb_data), 105 | .valid(portb_valid), 106 | // physical 107 | .port(port_b), 108 | .pin(pin_b), 109 | .ddr(ddr_b) 110 | ); 111 | 112 | // Memory or peripheral read response 113 | reg [7:0] rdata; 114 | always @(*) begin 115 | rdata = ram_data; 116 | if (uart_valid) rdata = uart_data; 117 | if (tcnt1_valid) rdata = tcnt1_data; 118 | if (portb_valid) rdata = portb_data; 119 | end 120 | 121 | always @(posedge clk) 122 | if (wen) $display("WR %04x <= %02x", addr, wdata); 123 | 124 | risc8_core core( 125 | .clk(clk), 126 | .reset(reset), 127 | 128 | // Program memory 129 | .pc(pc), 130 | .cdata(cdata), 131 | 132 | // Data memory and IO bus 133 | .data_addr(addr), 134 | .data_wen(wen), 135 | .data_ren(ren), 136 | .data_read(rdata), 137 | .data_write(wdata) 138 | ); 139 | 140 | endmodule 141 | 142 | `endif 143 | -------------------------------------------------------------------------------- /test-risc8.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | `ifndef RISC8_PROGRAM 4 | `define RISC8_PROGRAM "tests/test0.hex" 5 | `endif 6 | 7 | `include "risc8-soc.v" 8 | 9 | module top( 10 | ); 11 | reg clk; 12 | reg reset; 13 | 14 | initial begin 15 | $dumpfile("test-risc8.vcd"); 16 | $dumpvars(0,top); 17 | clk = 0; 18 | reset = 1; 19 | repeat(4) #4 clk = ~clk; 20 | reset = 0; 21 | $display("!RESET"); 22 | forever #5 clk = ~clk; 23 | end 24 | 25 | always begin 26 | #24000 27 | $finish; 28 | end 29 | 30 | wire [7:0] port_b; 31 | wire [7:0] ddr_b; 32 | reg [7:0] pin_b; 33 | 34 | //always @(posedge clk) 35 | //$display("PORTB %02x", port_b); 36 | 37 | risc8_soc cpu( 38 | .clk(clk), 39 | .reset(reset), 40 | 41 | .port_b(port_b), 42 | .pin_b(pin_b), 43 | .ddr_b(ddr_b) 44 | ); 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /tests/test0.S: -------------------------------------------------------------------------------- 1 | ldi r26, 0x50 2 | ldi r27, 0x09 3 | ldi r20, 0x40 4 | ldi r21, 0x41 5 | ldi r22, 0x42 6 | st X+, r20 7 | st X+, r21 8 | st X+, r22 9 | st X, r20 10 | ld r19, -X 11 | ld r18, -X 12 | ld r17, -X 13 | ld r16, X 14 | 15 | sts 0x0aa5, r20 16 | lds r20, 0x0aa5 17 | ldi r24, 7 18 | ldi r25, 8 19 | mov r25, r24 20 | nop 21 | ldi r29, 15 22 | nop 23 | inc r24 24 | inc r29 25 | nop 26 | add r29, r24 27 | 28 | ldi r16, 0 29 | ldi r17, 1 30 | ldi r18, 2 31 | ldi r19, 3 32 | ldi r20, 4 33 | subi r20, 2 34 | sub r20, r19 35 | -------------------------------------------------------------------------------- /tests/test1.c: -------------------------------------------------------------------------------- 1 | typedef unsigned char uint8_t; 2 | 3 | uint8_t __attribute__((__noinline__)) foo(uint8_t n) 4 | { 5 | uint8_t rc = 0; 6 | for(uint8_t i = 0 ; i < n ; i++) 7 | rc += i; 8 | return rc; 9 | } 10 | 11 | void __attribute__((__section__(".text.entry"))) _start(void) 12 | { 13 | *(volatile uint8_t *) 0xABEF = 27; 14 | *(volatile uint8_t *) 0x100 = foo(5); 15 | while(1) 16 | ; 17 | } 18 | -------------------------------------------------------------------------------- /tests/test2.c: -------------------------------------------------------------------------------- 1 | typedef unsigned char uint8_t; 2 | 3 | static const char msg[] = "Hello, world!"; 4 | 5 | void main(void) 6 | { 7 | *(volatile uint8_t*) 0x1234 = 0xAB; 8 | 9 | const char * c = msg; 10 | while(*c != '\0') 11 | *(volatile uint8_t *) 0x5aa5 = *c++; 12 | 13 | while(1); 14 | } 15 | -------------------------------------------------------------------------------- /tests/test3.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | // 123456789abcd 4 | static const char msg[] = "Hello, world!"; 5 | 6 | //int __attribute__((__noinline__)) my_strlen(const char * s) 7 | int my_strlen(const char * s) 8 | { 9 | int rc = 0; 10 | while(*s++) 11 | rc++; 12 | return rc; 13 | } 14 | 15 | void main(void) 16 | { 17 | *(volatile uint8_t*) 0x1234 = 0xAB; 18 | 19 | *(volatile uint8_t *) 0x5aa5 = my_strlen(msg); 20 | 21 | while(1); 22 | } 23 | -------------------------------------------------------------------------------- /uart.v: -------------------------------------------------------------------------------- 1 | /* 2 | * uart.v - High-speed serial support. Includes a baud generator, UART, 3 | * and a simple RFC1662-inspired packet framing protocol. 4 | * 5 | * This module is designed a 3 Mbaud serial port. 6 | * This is the highest data rate supported by 7 | * the popular FT232 USB-to-serial chip. 8 | * 9 | * Copyright (C) 2009 Micah Dowty 10 | * (C) 2018 Trammell Hudson 11 | * 12 | * Permission is hereby granted, free of charge, to any person obtaining a copy 13 | * of this software and associated documentation files (the "Software"), to deal 14 | * in the Software without restriction, including without limitation the rights 15 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 | * copies of the Software, and to permit persons to whom the Software is 17 | * furnished to do so, subject to the following conditions: 18 | * 19 | * The above copyright notice and this permission notice shall be included in 20 | * all copies or substantial portions of the Software. 21 | * 22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 | * THE SOFTWARE. 29 | */ 30 | 31 | `ifndef _risc8_uart_v_ 32 | `define _risc8_uart_v_ 33 | 34 | 35 | /* 36 | * Byte transmitter, RS-232 8-N-1 37 | * 38 | * Transmits on 'serial'. When 'ready' goes high, we can accept another byte. 39 | * It should be supplied on 'data' with a pulse on 'data_strobe'. 40 | */ 41 | module uart_tx( 42 | input clk, 43 | input reset, 44 | input baud_x1, 45 | output serial, 46 | output reg ready, 47 | input [7:0] data, 48 | input data_strobe 49 | ); 50 | 51 | /* 52 | * Left-to-right shift register. 53 | * Loaded with data, start bit, and stop bit. 54 | * 55 | * The stop bit doubles as a flag to tell us whether data has been 56 | * loaded; we initialize the whole shift register to zero on reset, 57 | * and when the register goes zero again, it's ready for more data. 58 | */ 59 | reg [7+1+1:0] shiftreg; 60 | 61 | /* 62 | * Serial output register. This is like an extension of the 63 | * shift register, but we never load it separately. This gives 64 | * us one bit period of latency to prepare the next byte. 65 | * 66 | * This register is inverted, so we can give it a reset value 67 | * of zero and still keep the 'serial' output high when idle. 68 | */ 69 | reg serial_r; 70 | assign serial = !serial_r; 71 | 72 | //assign ready = (shiftreg == 0); 73 | 74 | /* 75 | * State machine 76 | */ 77 | 78 | always @(posedge clk) 79 | if (reset) begin 80 | shiftreg <= 0; 81 | serial_r <= 0; 82 | end 83 | else if (data_strobe) begin 84 | $display("UART TX %02x", data); 85 | shiftreg <= { 86 | 1'b1, // stop bit 87 | data, 88 | 1'b0 // start bit (inverted) 89 | }; 90 | ready <= 0; 91 | end 92 | else if (baud_x1) begin 93 | if (shiftreg == 0) 94 | begin 95 | /* Idle state is idle high, serial_r is inverted */ 96 | serial_r <= 0; 97 | ready <= 1; 98 | end else 99 | serial_r <= !shiftreg[0]; 100 | // shift the output register down 101 | shiftreg <= {1'b0, shiftreg[7+1+1:1]}; 102 | end else 103 | ready <= (shiftreg == 0); 104 | 105 | endmodule 106 | 107 | 108 | /* 109 | * Byte receiver, RS-232 8-N-1 110 | * 111 | * Receives on 'serial'. When a properly framed byte is 112 | * received, 'data_strobe' pulses while the byte is on 'data'. 113 | * 114 | * Error bytes are ignored. 115 | */ 116 | 117 | module uart_rx( 118 | input clk, 119 | input reset, 120 | input baud_x4, 121 | input serial, 122 | output [7:0] data, 123 | output data_strobe 124 | ); 125 | /* 126 | * Synchronize the serial input to this clock domain 127 | */ 128 | wire serial_sync; 129 | d_flipflop_pair input_dff(clk, reset, serial, serial_sync); 130 | 131 | /* 132 | * State machine: Four clocks per bit, 10 total bits. 133 | */ 134 | reg [8:0] shiftreg; 135 | reg [5:0] state; 136 | reg data_strobe; 137 | wire [3:0] bit_count = state[5:2]; 138 | wire [1:0] bit_phase = state[1:0]; 139 | 140 | wire sampling_phase = (bit_phase == 1); 141 | wire start_bit = (bit_count == 0 && sampling_phase); 142 | wire stop_bit = (bit_count == 9 && sampling_phase); 143 | 144 | wire waiting_for_start = (state == 0 && serial_sync == 1); 145 | 146 | wire error = ( (start_bit && serial_sync == 1) || 147 | (stop_bit && serial_sync == 0) ); 148 | 149 | assign data = shiftreg[7:0]; 150 | 151 | always @(posedge clk or posedge reset) 152 | if (reset) begin 153 | state <= 0; 154 | data_strobe <= 0; 155 | end 156 | else if (baud_x4) begin 157 | 158 | if (waiting_for_start || error || stop_bit) 159 | state <= 0; 160 | else 161 | state <= state + 1; 162 | 163 | if (bit_phase == 1) 164 | shiftreg <= { serial_sync, shiftreg[8:1] }; 165 | 166 | data_strobe <= stop_bit && !error; 167 | 168 | end 169 | else begin 170 | data_strobe <= 0; 171 | end 172 | 173 | endmodule 174 | 175 | 176 | module uart( 177 | input clk, 178 | input reset, 179 | // logical 180 | input [7:0] baud_div, 181 | input tx_strobe, 182 | input [7:0] tx_data, 183 | output tx_ready, 184 | output rx_ready, 185 | // physical 186 | input rx_in, 187 | output tx_out 188 | ); 189 | reg [7:0] counter; 190 | reg baud_x1; 191 | 192 | always @(posedge clk) 193 | begin 194 | if (counter == 0) begin 195 | baud_x1 <= 1; 196 | counter <= baud_div; 197 | end else begin 198 | baud_x1 <= 0; 199 | counter <= counter - 1; 200 | end 201 | end 202 | 203 | uart_tx tx( 204 | .clk(clk), 205 | .reset(reset), 206 | .baud_x1(baud_x1), 207 | .ready(tx_ready), 208 | .data(tx_data), 209 | .data_strobe(tx_strobe), 210 | .serial(tx_out) 211 | ); 212 | endmodule 213 | `endif 214 | -------------------------------------------------------------------------------- /upduino_v2.pcf: -------------------------------------------------------------------------------- 1 | # The LED pins are using the current controlled outputs 2 | # and are negative logic (write a 0 to turn on). 3 | set_io -nowarn led_r 41 4 | set_io -nowarn led_g 39 5 | set_io -nowarn led_b 40 6 | 7 | # FTDI chip, which sort of works 8 | set_io -nowarn serial_txd 14 # FPGA transmit to USB 9 | set_io -nowarn serial_rxd 15 # FPGA receive from USB 10 | set_io -nowarn spi_cs 16 # Drive high to ensure that the SPI flash is disabled 11 | # set_io serial_rts_n 14 # no? 12 | # set_io serial_dtr_n 16 # no? 13 | 14 | # Normal GPIO pins, left side 15 | set_io -nowarn gpio_23 23 16 | set_io -nowarn gpio_25 25 17 | set_io -nowarn gpio_26 26 18 | set_io -nowarn gpio_27 27 19 | set_io -nowarn gpio_32 32 20 | set_io -nowarn gpio_35 35 21 | set_io -nowarn gpio_31 31 22 | set_io -nowarn gpio_37 37 23 | set_io -nowarn gpio_34 34 24 | set_io -nowarn gpio_43 43 25 | set_io -nowarn gpio_36 36 26 | set_io -nowarn gpio_42 42 27 | set_io -nowarn gpio_38 38 28 | set_io -nowarn gpio_28 28 29 | 30 | # Normal GPIO pins, right side 31 | set_io -nowarn gpio_12 12 32 | set_io -nowarn gpio_21 21 33 | set_io -nowarn gpio_13 13 34 | set_io -nowarn gpio_19 19 35 | set_io -nowarn gpio_18 18 36 | set_io -nowarn gpio_11 11 37 | set_io -nowarn gpio_9 9 38 | set_io -nowarn gpio_6 6 39 | set_io -nowarn gpio_44 44 40 | set_io -nowarn gpio_4 4 41 | set_io -nowarn gpio_3 3 42 | set_io -nowarn gpio_48 48 43 | set_io -nowarn gpio_45 45 44 | set_io -nowarn gpio_47 47 45 | set_io -nowarn gpio_46 46 46 | set_io -nowarn gpio_2 2 47 | -------------------------------------------------------------------------------- /zero.hex: -------------------------------------------------------------------------------- 1 | 0000 2 | 0000 3 | 0000 4 | 0000 5 | 0000 6 | 0000 7 | 0000 8 | 0000 9 | 0000 10 | 0000 11 | 0000 12 | 0000 13 | 0000 14 | 0000 15 | 0000 16 | 0000 17 | --------------------------------------------------------------------------------