├── .gitignore ├── ThunderboltReset ├── ThunderboltWait.hpp ├── ThunderboltWait.cpp ├── Info.plist └── kern_start.cpp ├── README.md ├── ThunderboltNative ├── Makefile ├── SSDT-HPLog.asl ├── SSDT-TbtOnPCH-GA-Z390-Designare.asl ├── SSDT-TbtOnPCH-NUC-Hades-Canyon.asl ├── SSDT-TbtOnPCH-GA-X99-Designare-EX.asl ├── SSDT-TbtOnPCH-Boot.asl └── SSDT-TbtOnPCH.asl ├── PatchingACPI.md ├── PatchingNVM.md ├── LICENSE └── ThunderboltReset.xcodeproj └── project.pbxproj /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | *.aml 3 | 4 | -------------------------------------------------------------------------------- /ThunderboltReset/ThunderboltWait.hpp: -------------------------------------------------------------------------------- 1 | // 2 | // ThunderboltWait.hpp 3 | // ThunderboltReset 4 | // 5 | // Copyright © 2019 osy86. All rights reserved. 6 | // 7 | 8 | #ifndef ThunderboltWait_hpp 9 | #define ThunderboltWait_hpp 10 | 11 | #include 12 | 13 | class ThunderboltWait : public IOService { 14 | OSDeclareDefaultStructors(ThunderboltWait); 15 | public: 16 | virtual IOService *probe(IOService *provider, SInt32 *score) override; 17 | }; 18 | 19 | #endif /* ThunderboltWait_hpp */ 20 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Thunderbolt Reset 2 | 3 | This plugin will disable the ICM in the Alpine Ridge in order for OSX to take 4 | over as the LC. 5 | 6 | Please note that due to the fact that the AR was designed by Intel, the 7 | controller becomes very unstable if the ICM was powered up enabled and then 8 | subsequently disabled (by this plugin). Therefore, this should only be used 9 | for testing. 10 | 11 | Lilu is required for this to work. 12 | 13 | ## Guides 14 | 15 | [Patching Ridge NVM](PatchingNVM.md) 16 | [Patching ACPI](PatchingACPI.md) 17 | -------------------------------------------------------------------------------- /ThunderboltReset/ThunderboltWait.cpp: -------------------------------------------------------------------------------- 1 | // 2 | // ThunderboltWait.cpp 3 | // ThunderboltReset 4 | // 5 | // Copyright © 2019 osy86. All rights reserved. 6 | // 7 | 8 | #include "ThunderboltWait.hpp" 9 | #include 10 | 11 | OSDefineMetaClassAndStructors(ThunderboltWait, IOService); 12 | 13 | extern volatile bool gIsReady; 14 | 15 | IOService *ThunderboltWait::probe(IOService *provider, SInt32 *score) { 16 | while (!gIsReady) { 17 | IOLog("ThunderboltWait: patch not ready yet, delaying thread\n"); 18 | IODelay(1000000); 19 | } 20 | IOLog("ThunderboltWait: patch completed, returning\n"); 21 | return NULL; 22 | } 23 | -------------------------------------------------------------------------------- /ThunderboltNative/Makefile: -------------------------------------------------------------------------------- 1 | IASL=iasl 2 | TARGET?=NUC-Hades-Canyon 3 | 4 | DEFINES=-DTARGET=$(TARGET) 5 | ifneq ($(SSDT_NAME),) 6 | DEFINES+=-DSSDT_NAME=\"$(SSDT_NAME)\" 7 | endif 8 | ifneq ($(NO_WINDOWS_SUPPORT),) 9 | DEFINES+=-DNO_WINDOWS_SUPPORT=$(NO_WINDOWS_SUPPORT) 10 | endif 11 | ifneq ($(TBT_HOTPLUG_GPE),) 12 | DEFINES+=-DTBT_HOTPLUG_GPE=$(TBT_HOTPLUG_GPE) 13 | endif 14 | ifneq ($(TBT_ROOT),) 15 | DEFINES+=-DTBT_ROOT=$(TBT_ROOT) 16 | endif 17 | 18 | .PHONY: all 19 | all: SSDT-TbtOnPCH.aml 20 | 21 | %.aml: %.sasl 22 | $(IASL) $< 23 | 24 | %.sasl: %.pasl 25 | sed '/^#/ d' $< > $@ 26 | 27 | %.pasl: %.asl 28 | $(CC) -E -x c $(DEFINES) $< -o $@ 29 | 30 | .PHONY: clean 31 | clean: 32 | rm -rf *.aml 33 | -------------------------------------------------------------------------------- /ThunderboltNative/SSDT-HPLog.asl: -------------------------------------------------------------------------------- 1 | /** 2 | * Template. Replace this with your own candidates. 3 | */ 4 | DefinitionBlock ("", "SSDT", 2, "OSY86 ", "HPLog", 0x00001000) 5 | { 6 | External (\_GPE.XL69, MethodObj) 7 | External (\_GPE.XL61, MethodObj) 8 | External (\_GPE.XL62, MethodObj) 9 | External (\_GPE.XL66, MethodObj) 10 | External (\_GPE.XL12, MethodObj) 11 | External (\_GPE.XL6F, MethodObj) 12 | External (\RMDT.P1, MethodObj) 13 | 14 | Scope (_GPE) 15 | { 16 | Method (_L69, 0, Serialized) // _Lxx: Level-Triggered GPE 17 | { 18 | \RMDT.P1 ("_L69") 19 | XL69 () 20 | } 21 | 22 | Method (_L61, 0, NotSerialized) // _Lxx: Level-Triggered GPE 23 | { 24 | \RMDT.P1 ("_L61") 25 | XL61 () 26 | } 27 | 28 | Method (_L62, 0, NotSerialized) // _Lxx: Level-Triggered GPE 29 | { 30 | \RMDT.P1 ("_L62") 31 | XL62 () 32 | } 33 | 34 | Method (_L66, 0, NotSerialized) // _Lxx: Level-Triggered GPE 35 | { 36 | \RMDT.P1 ("_L66") 37 | XL66 () 38 | } 39 | 40 | Method (_L12, 0, NotSerialized) // _Lxx: Level-Triggered GPE 41 | { 42 | \RMDT.P1 ("_L12") 43 | XL12 () 44 | } 45 | 46 | Method (_L6F, 0, NotSerialized) // _Lxx: Level-Triggered GPE 47 | { 48 | \RMDT.P1 ("_L6F") 49 | XL6F () 50 | } 51 | } 52 | } -------------------------------------------------------------------------------- /ThunderboltNative/SSDT-TbtOnPCH-GA-Z390-Designare.asl: -------------------------------------------------------------------------------- 1 | /** 2 | * Support file for Z390 Designare 3 | * 4 | * Copyright (c) 2019 osy86 5 | */ 6 | 7 | #define TBT_HAS_COMPANION Zero 8 | #define TBT_HOTPLUG_GPE _E17 9 | #define TBT_ROOT \_SB.PCI0.RP21 10 | #define XHC_ROOT \_SB.PCI0.XHC 11 | #define TBT_USB_PORT_1_COMPANION 0x00 12 | #define TBT_USB_PORT_2_COMPANION 0x00 13 | 14 | External (TBT_ROOT, DeviceObj) 15 | External (TBT_ROOT.PXSX, DeviceObj) 16 | External (XHC_ROOT, DeviceObj) 17 | Scope (TBT_ROOT) 18 | { 19 | External (MMRP, MethodObj) // Memory mapped root port 20 | External (MMTB, MethodObj) // Memory mapped TB port 21 | External (TBSE, FieldUnitObj) // TB root port number 22 | External (\_SB.PCI0.GPCB, MethodObj) // get PCI MMIO base 23 | External (\_SB.PCI0.RP05.PXSX, DeviceObj) // Replace the old device 24 | 25 | /** 26 | * Implement a call to the original HP handler 27 | * Then return One if this is a TB HP 28 | */ 29 | Method (OHPE, 0, NotSerialized) 30 | { 31 | Return (One) 32 | } 33 | 34 | /** 35 | * Get PCI base address 36 | * Arg0 = bus, Arg1 = device, Arg2 = function 37 | */ 38 | Method (MMIO, 3, NotSerialized) 39 | { 40 | Local0 = \_SB.PCI0.GPCB () // base address 41 | Local0 += (Arg0 << 20) 42 | Local0 += (Arg1 << 15) 43 | Local0 += (Arg2 << 12) 44 | Return (Local0) 45 | } 46 | 47 | /** 48 | * PXSX replaced by UPSB 49 | */ 50 | Scope (PXSX) 51 | { 52 | Method (_STA, 0, NotSerialized) 53 | { 54 | Return (Zero) // hidden 55 | } 56 | } 57 | } 58 | -------------------------------------------------------------------------------- /ThunderboltNative/SSDT-TbtOnPCH-NUC-Hades-Canyon.asl: -------------------------------------------------------------------------------- 1 | /** 2 | * Support file for NUC Hades Canyon 3 | * 4 | * Copyright (c) 2019 osy86 5 | */ 6 | 7 | #define TBT_HAS_COMPANION One 8 | #define TBT_HOTPLUG_GPE _E20 9 | #define TBT_ROOT \_SB.PCI0.RP05 10 | #define XHC_ROOT \_SB.PCI0.XHC 11 | #define TBT_USB_PORT_1_COMPANION 0x0C 12 | #define TBT_USB_PORT_2_COMPANION 0x0D 13 | 14 | External (TBT_ROOT, DeviceObj) 15 | External (TBT_ROOT.PXSX, DeviceObj) 16 | External (XHC_ROOT, DeviceObj) 17 | Scope (TBT_ROOT) 18 | { 19 | External (MMRP, MethodObj) // Memory mapped root port 20 | External (MMTB, MethodObj) // Memory mapped TB port 21 | External (TBSE, FieldUnitObj) // TB root port number 22 | External (\_SB.PCI0.GPCB, MethodObj) // get PCI MMIO base 23 | External (\_SB.PCI0.RP05.PXSX, DeviceObj) // Replace the old device 24 | 25 | /** 26 | * Implement a call to the original HP handler 27 | * Then return One if this is a TB HP 28 | */ 29 | Method (OHPE, 0, NotSerialized) 30 | { 31 | Return (One) 32 | } 33 | 34 | /** 35 | * Get PCI base address 36 | * Arg0 = bus, Arg1 = device, Arg2 = function 37 | */ 38 | Method (MMIO, 3, NotSerialized) 39 | { 40 | Local0 = \_SB.PCI0.GPCB () // base address 41 | Local0 += (Arg0 << 20) 42 | Local0 += (Arg1 << 15) 43 | Local0 += (Arg2 << 12) 44 | Return (Local0) 45 | } 46 | 47 | /** 48 | * PXSX replaced by UPSB 49 | */ 50 | Scope (PXSX) 51 | { 52 | Method (_STA, 0, NotSerialized) 53 | { 54 | Return (Zero) // hidden 55 | } 56 | } 57 | } 58 | -------------------------------------------------------------------------------- /PatchingACPI.md: -------------------------------------------------------------------------------- 1 | # Patching ACPI 2 | 3 | Once the native LC is disabled through either ThunderboltReset or 4 | [native NVM patches][1], you need custom ACPI entries to support power 5 | management (including S3hot) and hot-plug. 6 | 7 | ## New Board 8 | 9 | Start by making a copy of the closest board config in `ThunderboltNative` and 10 | name it `SSDT-TbtOnPCH-TARGETNAME.asl`. 11 | 12 | There are a list of defines near the top of the file that must be changed: 13 | 14 | 1. `TBT_HOTPLUG_GPE`: details in the next section 15 | 2. `TBT_ROOT`: Root device path for TB controller. Use `ioreg` and find the PCI 16 | device that connects to a `AppleThunderboltHAL`. 17 | 3. `TBT_HAS_COMPANION`: Companion device used only for power saving on boards 18 | that support it. Safe to always disable. 19 | 4. `XHC_ROOT`: Only used with companion device. Path to XHCI controller where 20 | the companion ports are connected to. 21 | 5. `TBT_USB_PORT_1_COMPANION`: Only used with companion device. 22 | First port number. 23 | 6. `TBT_USB_PORT_2_COMPANION`: Only used with companion device. 24 | Second port number. 25 | 26 | ## Finding GPE 27 | 28 | 1. Have Thunderbolt working either with the ThunderboltReset plugin or patched 29 | NVM. 30 | 2. Install [RehabMan's ACPI logger][2]. 31 | 3. Dump your DSDT/SSDT tables and find all methods with names beginning with 32 | `_L` and `_E`. 33 | 4. Modify the template in `ThunderboltNative/SSDT-HPLog.asl` with your GPE 34 | candidates. 35 | 5. Build and install `ThunderboltNative/SSDT-HPLog.asl`. 36 | 6. Add the ACPI patches to your config.plist renaming all the different `_Lxx` 37 | and `_Exx` method names to `XLxx` and `XExx` where `xx` is each GPE number. 38 | 7. Reboot with a TB device plugged in. 39 | 8. Open a Terminal and type in `log stream --process 0 | grep ACPI` 40 | 9. Unplug and re-plugin the TB device 41 | 10. Look at the Terminal window to see which GPE is printed. That is your 42 | hotplug GPE. 43 | 11. You can delete all the ACPI patches from config.plist except for the 44 | hotplug GPE. 45 | 46 | ## Building ACPI 47 | 48 | Have [iasl][3] in your `PATH` and run `make TARGET=TARGETNAME` in 49 | `ThunderboltNative`. 50 | 51 | [1]: [PatchingNVM.md] 52 | [2]: [https://github.com/RehabMan/OS-X-ACPI-Debug] 53 | [3]: [https://bitbucket.org/RehabMan/acpica/downloads/] 54 | -------------------------------------------------------------------------------- /ThunderboltReset/Info.plist: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | CFBundleDevelopmentRegion 6 | $(DEVELOPMENT_LANGUAGE) 7 | CFBundleExecutable 8 | $(EXECUTABLE_NAME) 9 | CFBundleIdentifier 10 | $(PRODUCT_BUNDLE_IDENTIFIER) 11 | CFBundleInfoDictionaryVersion 12 | 6.0 13 | CFBundleName 14 | $(PRODUCT_NAME) 15 | CFBundlePackageType 16 | KEXT 17 | CFBundleShortVersionString 18 | $(MODULE_VERSION) 19 | CFBundleVersion 20 | $(MODULE_VERSION) 21 | IOKitPersonalities 22 | 23 | ThunderboltReset 24 | 25 | CFBundleIdentifier 26 | $(PRODUCT_BUNDLE_IDENTIFIER) 27 | IOClass 28 | $(PRODUCT_NAME:rfc1034identifier) 29 | IOMatchCategory 30 | $(PRODUCT_NAME:rfc1034identifier) 31 | IOProviderClass 32 | IOResources 33 | IOResourceMatch 34 | IOKit 35 | 36 | ThunderboltWait 37 | 38 | CFBundleIdentifier 39 | $(PRODUCT_BUNDLE_IDENTIFIER) 40 | IOClass 41 | ThunderboltWait 42 | IOPCIClassMatch 43 | 0x08800000&0xffff0000 44 | IOPCIMatch 45 | 0x15008086&0xff00ffff 46 | IOPCITunnelCompatible 47 | 48 | IOProviderClass 49 | IOPCIDevice 50 | IOProbeScore 51 | 500 52 | 53 | 54 | NSHumanReadableCopyright 55 | Copyright © 2019 osy86. All rights reserved. 56 | OSBundleLibraries 57 | 58 | as.vit9696.Lilu 59 | 1.2.0 60 | com.apple.kpi.bsd 61 | 12.0.0 62 | com.apple.kpi.dsep 63 | 12.0.0 64 | com.apple.kpi.iokit 65 | 12.0.0 66 | com.apple.kpi.libkern 67 | 12.0.0 68 | com.apple.kpi.mach 69 | 12.0.0 70 | com.apple.kpi.unsupported 71 | 12.0.0 72 | 73 | OSBundleRequired 74 | Local-Root 75 | 76 | 77 | -------------------------------------------------------------------------------- /ThunderboltNative/SSDT-TbtOnPCH-GA-X99-Designare-EX.asl: -------------------------------------------------------------------------------- 1 | /** 2 | * Support file for GA-X99-Designare EX 3 | * 4 | * Copyright (c) 2019 osy86 5 | */ 6 | 7 | #ifndef TBT_HOTPLUG_GPE 8 | #define TBT_HOTPLUG_GPE _L01 9 | #endif 10 | #ifndef TBT_ROOT 11 | #define TBT_ROOT \_SB.PCI0.BR3A.H000 12 | #endif 13 | #define TBT_HAS_COMPANION Zero 14 | #define TBT_USB_PORT_1_COMPANION Zero 15 | #define TBT_USB_PORT_2_COMPANION Zero 16 | 17 | External (TBT_ROOT, DeviceObj) 18 | External (\_GPE.XL01, MethodObj) 19 | External (\_SB.PCI0.BR3A.PMEP, FieldUnitObj) 20 | External (\_SB.PCI0.BR3A.PMEH, MethodObj) 21 | External (\_SB.PCI0.BR3A.HPEH, MethodObj) 22 | External (\_GPE.MMRP, MethodObj) 23 | External (\_GPE.MMTB, MethodObj) 24 | External (\PEMA, IntObj) 25 | External (\TBRP, IntObj) 26 | Scope (TBT_ROOT) 27 | { 28 | /** 29 | * Implement a call to the original HP handler 30 | * Then return One if this is a TB HP 31 | */ 32 | Method (OHPE, 0, NotSerialized) 33 | { 34 | \_GPE.XL01 () // call original 35 | 36 | If ((\_SB.PCI0.BR3A.PMEP == 0x01)) 37 | { 38 | Local0 = \_SB.PCI0.BR3A.PMEH (0x05) 39 | } 40 | Else 41 | { 42 | Local0 = \_SB.PCI0.BR3A.HPEH (0x05) 43 | If ((ToInteger (TBRP) == 0x28)) 44 | { 45 | Local0 = 0xFF 46 | } 47 | } 48 | 49 | DBG2 ("OHPE", Local0) 50 | If ((Local0 != 0xFF)) 51 | { 52 | Return (One) 53 | } 54 | Else 55 | { 56 | Return (Zero) 57 | } 58 | } 59 | 60 | /** 61 | * Get PCI base address 62 | * Arg0 = bus, Arg1 = device, Arg2 = function 63 | */ 64 | Method (MMIO, 3, NotSerialized) 65 | { 66 | Local0 = PEMA // base address 67 | Local0 += (Arg0 << 20) 68 | Local0 += (Arg1 << 15) 69 | Local0 += (Arg2 << 12) 70 | Return (Local0) 71 | } 72 | 73 | /** 74 | * Implement a call that returns the MMIO address 75 | * for the root port in Arg0 76 | */ 77 | Method (MMRP, 1, Serialized) 78 | { 79 | Return (\_GPE.MMRP (Arg0)) 80 | } 81 | 82 | /** 83 | * Implement a call that returns the MMIO address 84 | * for the upstream port in Arg0 85 | */ 86 | Method (MMTB, 1, Serialized) 87 | { 88 | Return (\_GPE.MMTB (Arg0)) 89 | } 90 | 91 | /** 92 | * This is passed to MMRP and MMTB as Arg0 93 | * Store the root controller for the TB here. 94 | */ 95 | //Name (TBSE, 0) 96 | #define TBSE TBRP 97 | } 98 | -------------------------------------------------------------------------------- /ThunderboltReset/kern_start.cpp: -------------------------------------------------------------------------------- 1 | // 2 | // kern_start.cpp 3 | // ThunderboltReset 4 | // 5 | // Copyright © 2019 osy86. All rights reserved. 6 | // 7 | 8 | #include 9 | #include 10 | 11 | #define MODULE_SHORT "tbr" 12 | 13 | // Registers 14 | #define REG_FW_STS 0x39944 15 | #define REG_FW_STS_ICM_EN_INVERT (1 << 1) 16 | #define REG_FW_STS_ICM_EN (1 << 0) 17 | 18 | // Paths 19 | static const char *pathThunderboltNHI[] { "/System/Library/Extensions/AppleThunderboltNHI.kext/Contents/MacOS/AppleThunderboltNHI" }; 20 | 21 | static KernelPatcher::KextInfo kextThunderbolt = 22 | { "com.apple.driver.AppleThunderboltNHI", pathThunderboltNHI, 1, {true}, {}, KernelPatcher::KextInfo::Unloaded }; 23 | 24 | typedef void (*HALRegisterWrite32_t)(IOService *that, uint32_t offset, uint32_t data); 25 | typedef uint32_t (*HALRegisterRead32_t)(IOService *that, uint32_t offset); 26 | typedef int (*ResetNHI_t)(IOService *that); 27 | 28 | static HALRegisterWrite32_t HALRegisterWrite32 = NULL; 29 | static HALRegisterRead32_t HALRegisterRead32 = NULL; 30 | static mach_vm_address_t OriginalResetNHI = 0; 31 | 32 | volatile bool gIsReady = false; 33 | 34 | static int PatchedResetHNI(IOService *that) { 35 | DBGLOG(MODULE_SHORT, "AppleThunderboltNHI::resetNHI called"); 36 | 37 | IOService *hal = that->getProvider(); 38 | uint32_t reg = HALRegisterRead32(hal, REG_FW_STS); 39 | DBGLOG(MODULE_SHORT, "AppleThunderboltNHI::resetNHI: REG_FW_STS = 0x%08X", reg); 40 | if (!(reg & REG_FW_STS_ICM_EN)) { 41 | reg |= REG_FW_STS_ICM_EN_INVERT; 42 | HALRegisterWrite32(hal, REG_FW_STS, reg); 43 | IODelay(1000000); 44 | } else { 45 | DBGLOG(MODULE_SHORT, "AppleThunderboltNHI::resetNHI: ARC already disabled, bypassing", reg); 46 | } 47 | 48 | return reinterpret_cast(OriginalResetNHI)(that); 49 | } 50 | 51 | static void patchThunderboltNHI(KernelPatcher& patcher, size_t index, mach_vm_address_t address, size_t size) { 52 | HALRegisterWrite32 = reinterpret_cast(patcher.solveSymbol(index, "__ZN26AppleThunderboltGenericHAL15registerWrite32Ejj", address, size)); 53 | if (!HALRegisterWrite32) { 54 | SYSLOG(MODULE_SHORT, "failed to find AppleThunderboltGenericHAL::registerWrite32"); 55 | patcher.clearError(); 56 | gIsReady = true; 57 | return; 58 | } 59 | 60 | HALRegisterRead32 = reinterpret_cast(patcher.solveSymbol(index, "__ZN26AppleThunderboltGenericHAL14registerRead32Ej", address, size)); 61 | if (!HALRegisterRead32) { 62 | SYSLOG(MODULE_SHORT, "failed to find AppleThunderboltGenericHAL::registerRead32"); 63 | patcher.clearError(); 64 | gIsReady = true; 65 | return; 66 | } 67 | 68 | KernelPatcher::RouteRequest requests[] { 69 | KernelPatcher::RouteRequest("__ZN19AppleThunderboltNHI8resetNHIEv", PatchedResetHNI, OriginalResetNHI), 70 | }; 71 | patcher.routeMultiple(index, requests, 1, address, size); 72 | if (patcher.getError() != KernelPatcher::Error::NoError) { 73 | SYSLOG(MODULE_SHORT, "failed to patch AppleThunderboltNHI::resetNHI, error %d", patcher.getError()); 74 | patcher.clearError(); 75 | } 76 | gIsReady = true; 77 | } 78 | 79 | // main function 80 | static void pluginStart() { 81 | DBGLOG(MODULE_SHORT, "start"); 82 | auto error = lilu.onKextLoad(&kextThunderbolt, 1, 83 | [](void* user, KernelPatcher& patcher, size_t index, mach_vm_address_t address, size_t size) { 84 | if (index == kextThunderbolt.loadIndex) { 85 | DBGLOG(MODULE_SHORT, "found AppleThunderboltNHI"); 86 | patchThunderboltNHI(patcher, index, address, size); 87 | } 88 | }, nullptr); 89 | 90 | if (error != LiluAPI::Error::NoError) 91 | { 92 | SYSLOG(MODULE_SHORT, "failed to register onPatcherLoad method %d", error); 93 | gIsReady = true; 94 | } 95 | } 96 | 97 | // Boot args. 98 | static const char *bootargOff[] { 99 | "-tbresetoff" 100 | }; 101 | static const char *bootargDebug[] { 102 | "-tbresetdbg" 103 | }; 104 | static const char *bootargBeta[] { 105 | "-tbresetbeta" 106 | }; 107 | 108 | // Plugin configuration. 109 | PluginConfiguration ADDPR(config) { 110 | xStringify(PRODUCT_NAME), 111 | parseModuleVersion(xStringify(MODULE_VERSION)), 112 | LiluAPI::AllowNormal, 113 | bootargOff, 114 | arrsize(bootargOff), 115 | bootargDebug, 116 | arrsize(bootargDebug), 117 | bootargBeta, 118 | arrsize(bootargBeta), 119 | KernelVersion::HighSierra, 120 | KernelVersion::Catalina, 121 | pluginStart 122 | }; 123 | -------------------------------------------------------------------------------- /PatchingNVM.md: -------------------------------------------------------------------------------- 1 | # Patching Ridge NVM 2 | 3 | The ThunderboltReset plugin disables the ARC processor built into the Ridge and 4 | allows OSX to take over as the LC. However, this reset-after-boot is an Intel 5 | unsupported use case and you will run into a lot of annoying hardware issues 6 | (such as random system panics after wakeup). A better solution is to patch the 7 | NVM (Ridge firmware) into an Apple configuration. 8 | 9 | This guide is for **advanced users** only. Note that flashing the Ridge 10 | can result in a brick resulting in inoperable TB3/USB-C ports. If that is the 11 | case, you need to manually recover with an external SPI flasher. You should be 12 | aware of the risks here. 13 | 14 | ## Quick note on signed firmwares 15 | 16 | It appears that Apple Ridge firmwares are signed with a different private key 17 | than the Ridge firmwares found on literally every other device. That means that 18 | you cannot just flash an Apple firmware. If you could, things would be a lot 19 | easier. The next best option is to break the signature with a patched firmware. 20 | However, in doing so, you lose Thunderbolt support in Windows and Linux (can be 21 | worked around). USB 3.0 should still function with a patched firmware. 22 | 23 | ## Extracting Apple USB-C firmwares 24 | 25 | To dump all the different USB-C firmwares from OSX installer, you need to run 26 | `pkgutil --expand-full FirmwareUpdate.pkg path/to/output`. This pkg is found in 27 | `InstallESD.dmg` on newer OSX installers. 28 | 29 | Now in `path/to/output/Scripts/Tools/USBCUpdater` you will find the firmwares 30 | for all the different Mac models (including those without Thunderbolt, which 31 | just updates the TI PD firmware). 32 | 33 | ## Dumping your firmware 34 | 35 | The easiest way to get your original firmware is to find an update for your 36 | board's Thunderbolt controller online. You can also dump it externally with a 37 | SPI flasher. Finally, you can use [ThunderboltPatcher][1] to dump it, but this 38 | requires you to use the ThunderboltReset plugin. 39 | 40 | ## Finding the active partition 41 | 42 | To find the start of the active partition in a dump/firmware update, first look 43 | at the first 4 bytes. If it is not `FF FF FF FF`, then that is the starting 44 | offset (in little endian) of the active partition. If it is `FF FF FF FF`, then 45 | look at the 4 bytes starting at offset 0x1000. That should be the starting 46 | offset (in little endian) of the active partition. 47 | 48 | ## Matching firmware 49 | 50 | First, you need to figure out the version number for your existing firmware. 51 | If you downloaded it from the OEM's web site, the file name will usually tell 52 | you what the version is. For example 53 | `Intel_Hades_AR_HR_4C_C0_rev33_W_TI_20180109_SEC1_sign.bin` is version 33. 54 | 55 | If you have a raw dump, look at the byte at offset 0xA of the active partition 56 | (directions for finding the active partition is in the section above). For 57 | example if the byte is (hex) `19` then it is version 19. 58 | 59 | Now you want to find the Apple Ridge firmware closest to this version. In the 60 | `USBCUpdater` directory, you will find a lot of Mac models, each containing a 61 | `Config.plist` file. Look for `Ridge Firmware Version` (if that does 62 | not exist, then that model does not have a Thunderbolt controller). Compare the 63 | version there with the one for your board. You may have to dump different 64 | versions of OSX installer to get older Ridge firmwares (someone should make a 65 | central database). 66 | 67 | Ideally, you want one that is +/- 2 versions away from your board's version. 68 | The reason is that the config section of the firmware (where we will be 69 | copying from) contains some size/offset fields. If those change, then the diff 70 | process will be a lot more complicated. I've noticed that those fields usually 71 | stay constant for many versions. You can be sure that no size/offset fields 72 | changed by using a diff tool and checking that no bytes are added or removed 73 | (only changed) after ignoring the DROM. 74 | 75 | ## Patching firmware 76 | 77 | Using a binary diff tool (such as Araxis Merge or HxD), compare the first 78 | 0x1000 bytes *of the active partition* in the two firmware. You can now create 79 | a [ThunderboltPatcher patch][2] for your firmware. 80 | 81 | You can skip the follow differences: 82 | 83 | * Offset 0xA-0xB has the version number 84 | * Offset 0x200-0x600 is the DROM 85 | * Any time you see the version number (e.g. `33` vs `34` if your controller 86 | is v33 and Apple's is v34) 87 | * Any time you see `86 80 XX XX` from Apple's firmware (controller PID) and 88 | your board's firmware is NOT `FF FF FF FF`. 89 | 90 | [1]: https://github.com/osy86/ThunderboltPatcher 91 | [2]: https://github.com/osy86/ThunderboltPatcher/blob/master/README.md 92 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | 2 | Apache License 3 | Version 2.0, January 2004 4 | http://www.apache.org/licenses/ 5 | 6 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 7 | 8 | 1. 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We also recommend that a 186 | file or class name and description of purpose be included on the 187 | same "printed page" as the copyright notice for easier 188 | identification within third-party archives. 189 | 190 | Copyright [yyyy] [name of copyright owner] 191 | 192 | Licensed under the Apache License, Version 2.0 (the "License"); 193 | you may not use this file except in compliance with the License. 194 | You may obtain a copy of the License at 195 | 196 | http://www.apache.org/licenses/LICENSE-2.0 197 | 198 | Unless required by applicable law or agreed to in writing, software 199 | distributed under the License is distributed on an "AS IS" BASIS, 200 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 201 | See the License for the specific language governing permissions and 202 | limitations under the License. 203 | -------------------------------------------------------------------------------- /ThunderboltNative/SSDT-TbtOnPCH-Boot.asl: -------------------------------------------------------------------------------- 1 | /** 2 | * Power on TB controller and disable ICM on bootup. 3 | * We must do this early in _INI before XNU PCI 4 | * enumeration. This code is only used at cold boot. 5 | * 6 | * Copyright (c) 2019 osy86 7 | */ 8 | // Scope (TBT_ROOT) 9 | // { 10 | Name (EICM, Zero) 11 | Name (R020, Zero) // RP base/limit from UEFI 12 | Name (R024, Zero) // RP prefetch base/limit from UEFI 13 | Name (R118, Zero) // UPSB Pri Bus = RP Sec Bus (UEFI) 14 | Name (R119, Zero) // UPSB Sec Bus = RP Sec Bus + 1 15 | Name (R11A, Zero) // UPSB Sub Bus = RP Sub Bus (UEFI) 16 | Name (R11C, Zero) // UPSB IO base/limit = RP IO base/limit (UEFI) 17 | Name (R120, Zero) // UPSB mem base/limit = RP mem base/limit (UEFI) 18 | Name (R124, Zero) // UPSB pre base/limit = RP pre base/limit (UEFI) 19 | Name (R218, Zero) // DSB0 Pri Bus = UPSB Sec Bus 20 | Name (R219, Zero) // DSB0 Sec Bus = UPSB Sec Bus + 1 21 | Name (R21A, Zero) // DSB0 Sub Bus = UPSB Sub Bus 22 | Name (R21C, Zero) // DSB0 IO base/limit = UPSB IO base/limit 23 | Name (R220, Zero) // DSB0 mem base/limit = UPSB mem base/limit 24 | Name (R224, Zero) // DSB0 pre base/limit = UPSB pre base/limit 25 | Name (R318, Zero) // DSB1 Pri Bus = UPSB Sec Bus 26 | Name (R319, Zero) // DSB1 Sec Bus = UPSB Sec Bus + 2 27 | Name (R31A, Zero) // DSB1 Sub Bus = no children 28 | Name (R31C, Zero) // DSB1 disable IO 29 | Name (R320, Zero) // DSB1 disable mem 30 | Name (R324, Zero) // DSB1 disable prefetch 31 | Name (R418, Zero) // DSB2 Pri Bus = UPSB Sec Bus 32 | Name (R419, Zero) // DSB2 Sec Bus = UPSB Sec Bus + 3 33 | Name (R41A, Zero) // DSB2 Sub Bus = no children 34 | Name (R41C, Zero) // DSB2 disable IO 35 | Name (R420, Zero) // DSB2 disable mem 36 | Name (R424, Zero) // DSB2 disable prefetch 37 | Name (RVES, Zero) // DSB2 offset 0x564, unknown 38 | Name (R518, Zero) // DSB4 Pri Bus = UPSB Sec Bus 39 | Name (R519, Zero) // DSB4 Sec Bus = UPSB Sec Bus + 4 40 | Name (R51A, Zero) // DSB4 Sub Bus = no children 41 | Name (R51C, Zero) // DSB4 disable IO 42 | Name (R520, Zero) // DSB4 disable mem 43 | Name (R524, Zero) // DSB4 disable prefetch 44 | Name (R618, Zero) 45 | Name (R619, Zero) 46 | Name (R61A, Zero) 47 | Name (R61C, Zero) 48 | Name (R620, Zero) 49 | Name (R624, Zero) 50 | Name (RH10, Zero) // NHI0 BAR0 = DSB0 mem base 51 | Name (RH14, Zero) // NHI0 BAR1 unused 52 | Name (POC0, Zero) 53 | 54 | // Root port configuration base 55 | OperationRegion (RPSM, SystemMemory, MMRP (TBSE), 0x54) 56 | Field (RPSM, DWordAcc, NoLock, Preserve) 57 | { 58 | RPVD, 32, 59 | RPR4, 8, 60 | Offset (0x18), 61 | RP18, 8, 62 | RP19, 8, 63 | RP1A, 8, 64 | Offset (0x1C), 65 | RP1C, 16, 66 | Offset (0x20), 67 | R_20, 32, 68 | R_24, 32, 69 | Offset (0x52), 70 | , 11, 71 | RPLT, 1, 72 | Offset (0x54) 73 | } 74 | 75 | // UPSB (up stream port) configuration base 76 | OperationRegion (UPSM, SystemMemory, MMTB (TBSE), 0x0550) 77 | Field (UPSM, DWordAcc, NoLock, Preserve) 78 | { 79 | UPVD, 32, 80 | UP04, 8, 81 | Offset (0x08), 82 | CLRD, 32, 83 | Offset (0x18), 84 | UP18, 8, 85 | UP19, 8, 86 | UP1A, 8, 87 | Offset (0x1C), 88 | UP1C, 16, 89 | Offset (0x20), 90 | UP20, 32, 91 | UP24, 32, 92 | Offset (0xD2), 93 | , 11, 94 | UPLT, 1, 95 | Offset (0xD4), 96 | Offset (0x544), 97 | UPMB, 1, 98 | Offset (0x548), 99 | T2PR, 32, 100 | P2TR, 32 101 | } 102 | 103 | // DSB0 configuration base 104 | OperationRegion (DNSM, SystemMemory, MMIO (UP19, 0, 0), 0xD4) 105 | Field (DNSM, DWordAcc, NoLock, Preserve) 106 | { 107 | DPVD, 32, 108 | DP04, 8, 109 | Offset (0x18), 110 | DP18, 8, 111 | DP19, 8, 112 | DP1A, 8, 113 | Offset (0x1C), 114 | DP1C, 16, 115 | Offset (0x20), 116 | DP20, 32, 117 | DP24, 32, 118 | Offset (0xD2), 119 | , 11, 120 | DPLT, 1, 121 | Offset (0xD4) 122 | } 123 | 124 | // DSB1 configuration base 125 | OperationRegion (DS3M, SystemMemory, MMIO (UP19, 1, 0), 0x40) 126 | Field (DS3M, DWordAcc, NoLock, Preserve) 127 | { 128 | D3VD, 32, 129 | D304, 8, 130 | Offset (0x18), 131 | D318, 8, 132 | D319, 8, 133 | D31A, 8, 134 | Offset (0x1C), 135 | D31C, 16, 136 | Offset (0x20), 137 | D320, 32, 138 | D324, 32 139 | } 140 | 141 | // DSB2 configuration base 142 | OperationRegion (DS4M, SystemMemory, MMIO (UP19, 2, 0), 0x0568) 143 | Field (DS4M, DWordAcc, NoLock, Preserve) 144 | { 145 | D4VD, 32, 146 | D404, 8, 147 | Offset (0x18), 148 | D418, 8, 149 | D419, 8, 150 | D41A, 8, 151 | Offset (0x1C), 152 | D41C, 16, 153 | Offset (0x20), 154 | D420, 32, 155 | D424, 32, 156 | Offset (0x564), 157 | DVES, 32 158 | } 159 | 160 | // DSB4 configuration base 161 | OperationRegion (DS5M, SystemMemory, MMIO (UP19, 4, 0), 0x40) 162 | Field (DS5M, DWordAcc, NoLock, Preserve) 163 | { 164 | D5VD, 32, 165 | D504, 8, 166 | Offset (0x18), 167 | D518, 8, 168 | D519, 8, 169 | D51A, 8, 170 | Offset (0x1C), 171 | D51C, 16, 172 | Offset (0x20), 173 | D520, 32, 174 | D524, 32 175 | } 176 | 177 | OperationRegion (NHIM, SystemMemory, MMIO (DP19, 0, 0), 0x40) 178 | Field (NHIM, DWordAcc, NoLock, Preserve) 179 | { 180 | NH00, 32, 181 | NH04, 8, 182 | Offset (0x10), 183 | NH10, 32, 184 | NH14, 32 185 | } 186 | 187 | OperationRegion (RSTR, SystemMemory, NH10 + 0x39858, 0x0100) 188 | Field (RSTR, DWordAcc, NoLock, Preserve) 189 | { 190 | CIOR, 32, 191 | Offset (0xB8), 192 | ISTA, 32, 193 | Offset (0xEC), 194 | ICME, 32 195 | } 196 | 197 | OperationRegion (XHCM, SystemMemory, MMIO (D519, 0, 0), 0x40) 198 | Field (XHCM, DWordAcc, NoLock, Preserve) 199 | { 200 | XH00, 32, 201 | XH04, 8, 202 | Offset (0x10), 203 | XH10, 32, 204 | XH14, 32 205 | } 206 | 207 | Method (_INI, 0, NotSerialized) // _INI: Initialize 208 | { 209 | If (!OSDW ()) 210 | { 211 | DBG3 ("RP", RPVD, R_20) 212 | R020 = R_20 /* \_SB_.PCI0.RP05.R_20 */ 213 | R024 = R_24 /* \_SB_.PCI0.RP05.R_24 */ 214 | R118 = UP18 /* \_SB_.PCI0.RP05.UP18 */ 215 | R119 = UP19 /* \_SB_.PCI0.RP05.UP19 */ 216 | R11A = UP1A /* \_SB_.PCI0.RP05.UP1A */ 217 | R11C = UP1C /* \_SB_.PCI0.RP05.UP1C */ 218 | R120 = UP20 /* \_SB_.PCI0.RP05.UP20 */ 219 | R124 = UP24 /* \_SB_.PCI0.RP05.UP24 */ 220 | R218 = DP18 /* \_SB_.PCI0.RP05.DP18 */ 221 | R219 = DP19 /* \_SB_.PCI0.RP05.DP19 */ 222 | R21A = DP1A /* \_SB_.PCI0.RP05.DP1A */ 223 | R21C = DP1C /* \_SB_.PCI0.RP05.DP1C */ 224 | R220 = DP20 /* \_SB_.PCI0.RP05.DP20 */ 225 | R224 = DP24 /* \_SB_.PCI0.RP05.DP24 */ 226 | R318 = D318 /* \_SB_.PCI0.RP05.D318 */ 227 | R319 = D319 /* \_SB_.PCI0.RP05.D319 */ 228 | R31A = D31A /* \_SB_.PCI0.RP05.D31A */ 229 | R31C = D31C /* \_SB_.PCI0.RP05.D31C */ 230 | R320 = D320 /* \_SB_.PCI0.RP05.D320 */ 231 | R324 = D324 /* \_SB_.PCI0.RP05.D324 */ 232 | R418 = D418 /* \_SB_.PCI0.RP05.D418 */ 233 | R419 = D419 /* \_SB_.PCI0.RP05.D419 */ 234 | R41A = D41A /* \_SB_.PCI0.RP05.D41A */ 235 | R41C = D41C /* \_SB_.PCI0.RP05.D41C */ 236 | R420 = D420 /* \_SB_.PCI0.RP05.D420 */ 237 | R424 = D424 /* \_SB_.PCI0.RP05.D424 */ 238 | RVES = DVES /* \_SB_.PCI0.RP05.DVES */ 239 | R518 = D518 /* \_SB_.PCI0.RP05.D518 */ 240 | R519 = D519 /* \_SB_.PCI0.RP05.D519 */ 241 | R51A = D51A /* \_SB_.PCI0.RP05.D51A */ 242 | R51C = D51C /* \_SB_.PCI0.RP05.D51C */ 243 | R520 = D520 /* \_SB_.PCI0.RP05.D520 */ 244 | R524 = D524 /* \_SB_.PCI0.RP05.D524 */ 245 | RH10 = NH10 /* \_SB_.PCI0.RP05.NH10 */ 246 | RH14 = NH14 /* \_SB_.PCI0.RP05.NH14 */ 247 | Sleep (One) 248 | ICMS () 249 | } 250 | } 251 | 252 | Method (ICMS, 0, NotSerialized) 253 | { 254 | TBT_ROOT.POC0 = One 255 | DBG2 ("ICME", TBT_ROOT.ICME) 256 | If (TBT_ROOT.ICME != 0x800001A6 && TBT_ROOT.ICME != 0x800000A6) 257 | { 258 | If (TBT_ROOT.CNHI ()) 259 | { 260 | DBG2 ("ICME", TBT_ROOT.ICME) 261 | If (TBT_ROOT.ICME != 0xFFFFFFFF) 262 | { 263 | //SGDI (0x01070004) 264 | TBT_ROOT.WTLT () 265 | DBG2 ("ICME", TBT_ROOT.ICME) 266 | If (!Local0 = (TBT_ROOT.ICME & 0x80000000)) // NVM started means we need reset 267 | { 268 | TBT_ROOT.ICME |= 0x06 // invert EN | enable CPU 269 | Local0 = 1000 270 | While ((Local1 = (TBT_ROOT.ICME & 0x80000000)) == Zero) 271 | { 272 | Local0-- 273 | If (Local0 == Zero) 274 | { 275 | Break 276 | } 277 | 278 | Sleep (One) 279 | } 280 | DBG2 ("ICME", TBT_ROOT.ICME) 281 | //\_SB.SGOV (0x01070004, Zero) 282 | //\_SB.SGDO (0x01070004) 283 | } 284 | } 285 | } 286 | } 287 | 288 | TBT_ROOT.POC0 = Zero 289 | 290 | // disable USB force power 291 | //SGOV (0x01070007, Zero) 292 | //SGDO (0x01070007) 293 | } 294 | 295 | /** 296 | * Send TBT command 297 | */ 298 | Method (TBTC, 1, Serialized) 299 | { 300 | P2TR = Arg0 301 | Local0 = 100 302 | Local1 = T2PR /* \_SB_.PCI0.RP05.T2PR */ 303 | While ((Local2 = (Local1 & One)) == Zero) 304 | { 305 | If (Local1 == 0xFFFFFFFF) 306 | { 307 | Return 308 | } 309 | 310 | Local0-- 311 | If (Local0 == Zero) 312 | { 313 | Break 314 | } 315 | 316 | Local1 = T2PR /* \_SB_.PCI0.RP05.T2PR */ 317 | Sleep (50) 318 | } 319 | 320 | P2TR = Zero 321 | } 322 | 323 | /** 324 | * Plug detection for Windows 325 | */ 326 | Method (CMPE, 0, Serialized) 327 | { 328 | Notify (TBT_ROOT, Zero) // Bus Check 329 | } 330 | 331 | /** 332 | * Configure NHI device 333 | */ 334 | Method (CNHI, 0, Serialized) 335 | { 336 | Local0 = 10 337 | 338 | // Configure root port 339 | DBG1 ("Configure root") 340 | While (Local0) 341 | { 342 | R_20 = R020 // Memory Base/Limit 343 | R_24 = R024 // Prefetch Base/Limit 344 | RPR4 = 0x07 // Command 345 | If (R020 == R_20) // read back check 346 | { 347 | Break 348 | } 349 | 350 | Sleep (One) 351 | Local0-- 352 | } 353 | 354 | If (R020 != R_20) // configure failed 355 | { 356 | Return (Zero) 357 | } 358 | 359 | // Configure UPSB 360 | DBG1 ("Configure UPSB") 361 | Local0 = 10 362 | While (Local0) 363 | { 364 | UP18 = R118 // UPSB Pri Bus 365 | UP19 = R119 // UPSB Sec Bus 366 | UP1A = R11A // UPSB Sub Bus 367 | UP1C = R11C // UPSB IO Base/Limit 368 | UP20 = R120 // UPSB Memory Base/Limit 369 | UP24 = R124 // UPSB Prefetch Base/Limit 370 | UP04 = 0x07 // UPSB Command 371 | If (R119 == UP19) // read back check 372 | { 373 | Break 374 | } 375 | 376 | Sleep (One) 377 | Local0-- 378 | } 379 | 380 | If (R119 != UP19) // configure failed 381 | { 382 | Return (Zero) 383 | } 384 | 385 | DBG1 ("Wait for link training") 386 | If (WTLT () != One) 387 | { 388 | Return (Zero) 389 | } 390 | 391 | // Configure DSB0 392 | DBG1 ("Configure DSB") 393 | Local0 = 10 394 | While (Local0) 395 | { 396 | DP18 = R218 // Pri Bus 397 | DP19 = R219 // Sec Bus 398 | DP1A = R21A // Sub Bus 399 | DP1C = R21C // IO Base/Limit 400 | DP20 = R220 // Memory Base/Limit 401 | DP24 = R224 // Prefetch Base/Limit 402 | DP04 = 0x07 // Command 403 | D318 = R318 // Pri Bus 404 | D319 = R319 // Sec Bus 405 | D31A = R31A // Sub Bus 406 | D31C = R31C // IO Base/Limit 407 | D320 = R320 // Memory Base/Limit 408 | D324 = R324 // Prefetch Base/Limit 409 | D304 = 0x07 // Command 410 | D418 = R418 // Pri Bus 411 | D419 = R419 // Sec Bus 412 | D41A = R41A // Sub Bus 413 | D41C = R41C // IO Base/Limit 414 | D420 = R420 // Memory Base/Limit 415 | D424 = R424 // Prefetch Base/Limit 416 | DVES = RVES // DSB2 0x564 417 | D404 = 0x07 // Command 418 | D518 = R518 // Pri Bus 419 | D519 = R519 // Sec Bus 420 | D51A = R51A // Sub Bus 421 | D51C = R51C // IO Base/Limit 422 | D520 = R520 // Memory Base/Limit 423 | D524 = R524 // Prefetch Base/Limit 424 | D504 = 0x07 // Command 425 | If (R219 == DP19) // read back check 426 | { 427 | Break 428 | } 429 | 430 | Sleep (One) 431 | Local0-- 432 | } 433 | 434 | If (R219 != DP19) // configure failed 435 | { 436 | Return (Zero) 437 | } 438 | 439 | DBG1 ("Wait for down link") 440 | If (WTDL () != One) 441 | { 442 | Return (Zero) 443 | } 444 | 445 | // Configure NHI 446 | DBG1 ("Configure NHI") 447 | Local0 = 100 448 | While (Local0) 449 | { 450 | NH10 = RH10 // NHI BAR 0 451 | NH14 = RH14 // NHI BAR 1 452 | NH04 = 0x07 // NHI Command 453 | If (RH10 == NH10) // read back check 454 | { 455 | Break 456 | } 457 | 458 | Sleep (One) 459 | Local0-- 460 | } 461 | DBG2 ("NHI BAR", NH10) 462 | 463 | If (RH10 != NH10) // configure failed 464 | { 465 | Return (Zero) 466 | } 467 | 468 | DBG1 ("CNHI done") 469 | 470 | Return (One) 471 | } 472 | 473 | /** 474 | * Uplink check 475 | */ 476 | Method (UPCK, 0, Serialized) 477 | { 478 | If ((UPVD & 0xFFFF) == 0x8086) 479 | { 480 | Return (One) 481 | } 482 | Else 483 | { 484 | Return (Zero) 485 | } 486 | } 487 | 488 | /** 489 | * Uplink training check 490 | */ 491 | Method (ULTC, 0, Serialized) 492 | { 493 | If (RPLT == Zero) 494 | { 495 | If (UPLT == Zero) 496 | { 497 | Return (One) 498 | } 499 | } 500 | 501 | Return (Zero) 502 | } 503 | 504 | /** 505 | * Wait for link training 506 | */ 507 | Method (WTLT, 0, Serialized) 508 | { 509 | Local0 = 2000 510 | Local1 = Zero 511 | While (Local0) 512 | { 513 | If (RPR4 == 0x07) 514 | { 515 | If (ULTC ()) 516 | { 517 | If (UPCK ()) 518 | { 519 | Local1 = One 520 | Break 521 | } 522 | } 523 | } 524 | 525 | Sleep (One) 526 | Local0-- 527 | } 528 | 529 | Return (Local1) 530 | } 531 | 532 | /** 533 | * Downlink training check 534 | */ 535 | Method (DLTC, 0, Serialized) 536 | { 537 | If (RPLT == Zero) 538 | { 539 | If (UPLT == Zero) 540 | { 541 | If (DPLT == Zero) 542 | { 543 | Return (One) 544 | } 545 | } 546 | } 547 | 548 | Return (Zero) 549 | } 550 | 551 | /** 552 | * Wait for downlink training 553 | */ 554 | Method (WTDL, 0, Serialized) 555 | { 556 | Local0 = 2000 557 | Local1 = Zero 558 | While (Local0) 559 | { 560 | If (RPR4 == 0x07) 561 | { 562 | If (DLTC ()) 563 | { 564 | If (UPCK ()) 565 | { 566 | Local1 = One 567 | Break 568 | } 569 | } 570 | } 571 | 572 | Sleep (One) 573 | Local0-- 574 | } 575 | 576 | Return (Local1) 577 | } 578 | // } 579 | -------------------------------------------------------------------------------- /ThunderboltReset.xcodeproj/project.pbxproj: -------------------------------------------------------------------------------- 1 | // !$*UTF8*$! 2 | { 3 | archiveVersion = 1; 4 | classes = { 5 | }; 6 | objectVersion = 50; 7 | objects = { 8 | 9 | /* Begin PBXBuildFile section */ 10 | CE0D113D2377FA5F003BE3C3 /* ThunderboltWait.cpp in Sources */ = {isa = PBXBuildFile; fileRef = CE0D113B2377FA5F003BE3C3 /* ThunderboltWait.cpp */; }; 11 | CE0D113E2377FA5F003BE3C3 /* ThunderboltWait.hpp in Headers */ = {isa = PBXBuildFile; fileRef = CE0D113C2377FA5F003BE3C3 /* ThunderboltWait.hpp */; }; 12 | CEDE8D7B22984F8F00C73034 /* libkmod.a in Frameworks */ = {isa = PBXBuildFile; fileRef = CEDE8D6E22984F7700C73034 /* libkmod.a */; }; 13 | CEDE8D7C22984FE600C73034 /* plugin_start.cpp in Sources */ = {isa = PBXBuildFile; fileRef = CEDE8D7822984F7700C73034 /* plugin_start.cpp */; }; 14 | CEDE8D7E2298501600C73034 /* kern_start.cpp in Sources */ = {isa = PBXBuildFile; fileRef = CEDE8D7D2298501600C73034 /* kern_start.cpp */; }; 15 | /* End PBXBuildFile section */ 16 | 17 | /* Begin PBXFileReference section */ 18 | CE0D113B2377FA5F003BE3C3 /* ThunderboltWait.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = ThunderboltWait.cpp; sourceTree = ""; }; 19 | CE0D113C2377FA5F003BE3C3 /* ThunderboltWait.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = ThunderboltWait.hpp; sourceTree = ""; }; 20 | CEDE8CE522984C0800C73034 /* ThunderboltReset.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = ThunderboltReset.kext; sourceTree = BUILT_PRODUCTS_DIR; }; 21 | CEDE8CEC22984C0800C73034 /* Info.plist */ = {isa = PBXFileReference; lastKnownFileType = text.plist.xml; path = Info.plist; sourceTree = ""; }; 22 | CEDE8D4D22984F7600C73034 /* kern_config.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_config.hpp; sourceTree = ""; }; 23 | CEDE8D4E22984F7600C73034 /* kern_atomic.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_atomic.hpp; sourceTree = ""; }; 24 | CEDE8D4F22984F7600C73034 /* kern_time.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_time.hpp; sourceTree = ""; }; 25 | CEDE8D5022984F7600C73034 /* kern_nvram.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_nvram.hpp; sourceTree = ""; }; 26 | CEDE8D5122984F7600C73034 /* kern_cpu.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_cpu.hpp; sourceTree = ""; }; 27 | CEDE8D5222984F7600C73034 /* kern_devinfo.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_devinfo.hpp; sourceTree = ""; }; 28 | CEDE8D5322984F7600C73034 /* kern_efi.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_efi.hpp; sourceTree = ""; }; 29 | CEDE8D5422984F7600C73034 /* kern_policy.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_policy.hpp; sourceTree = ""; }; 30 | CEDE8D5522984F7600C73034 /* kern_user.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_user.hpp; sourceTree = ""; }; 31 | CEDE8D5622984F7600C73034 /* plugin_start.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = plugin_start.hpp; sourceTree = ""; }; 32 | CEDE8D5722984F7600C73034 /* kern_iokit.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_iokit.hpp; sourceTree = ""; }; 33 | CEDE8D5822984F7600C73034 /* kern_crypto.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_crypto.hpp; sourceTree = ""; }; 34 | CEDE8D5922984F7600C73034 /* kern_mach.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_mach.hpp; sourceTree = ""; }; 35 | CEDE8D5A22984F7600C73034 /* kern_compression.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_compression.hpp; sourceTree = ""; }; 36 | CEDE8D5B22984F7600C73034 /* kern_file.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_file.hpp; sourceTree = ""; }; 37 | CEDE8D5C22984F7600C73034 /* kern_rtc.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_rtc.hpp; sourceTree = ""; }; 38 | CEDE8D5D22984F7700C73034 /* kern_disasm.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_disasm.hpp; sourceTree = ""; }; 39 | CEDE8D5F22984F7700C73034 /* capstone.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = capstone.h; sourceTree = ""; }; 40 | CEDE8D6022984F7700C73034 /* mips.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = mips.h; sourceTree = ""; }; 41 | CEDE8D6122984F7700C73034 /* sparc.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = sparc.h; sourceTree = ""; }; 42 | CEDE8D6222984F7700C73034 /* systemz.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = systemz.h; sourceTree = ""; }; 43 | CEDE8D6322984F7700C73034 /* arm.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = arm.h; sourceTree = ""; }; 44 | CEDE8D6422984F7700C73034 /* x86.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = x86.h; sourceTree = ""; }; 45 | CEDE8D6522984F7700C73034 /* ppc.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = ppc.h; sourceTree = ""; }; 46 | CEDE8D6622984F7700C73034 /* arm64.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = arm64.h; sourceTree = ""; }; 47 | CEDE8D6722984F7700C73034 /* xcore.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = xcore.h; sourceTree = ""; }; 48 | CEDE8D6822984F7700C73034 /* platform.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = platform.h; sourceTree = ""; }; 49 | CEDE8D6922984F7700C73034 /* kern_patcher.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_patcher.hpp; sourceTree = ""; }; 50 | CEDE8D6A22984F7700C73034 /* kern_compat.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_compat.hpp; sourceTree = ""; }; 51 | CEDE8D6B22984F7700C73034 /* kern_api.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_api.hpp; sourceTree = ""; }; 52 | CEDE8D6C22984F7700C73034 /* kern_util.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = kern_util.hpp; sourceTree = ""; }; 53 | CEDE8D6E22984F7700C73034 /* libkmod.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; path = libkmod.a; sourceTree = ""; }; 54 | CEDE8D7022984F7700C73034 /* entry64.S */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.asm; path = entry64.S; sourceTree = ""; }; 55 | CEDE8D7122984F7700C73034 /* build.tool */ = {isa = PBXFileReference; lastKnownFileType = text.script.sh; path = build.tool; sourceTree = ""; }; 56 | CEDE8D7222984F7700C73034 /* entry32.S */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.asm; path = entry32.S; sourceTree = ""; }; 57 | CEDE8D7322984F7700C73034 /* wrappers.inc */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.pascal; path = wrappers.inc; sourceTree = ""; }; 58 | CEDE8D7522984F7700C73034 /* mac_framework.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = mac_framework.h; sourceTree = ""; }; 59 | CEDE8D7622984F7700C73034 /* mac_policy.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = mac_policy.h; sourceTree = ""; }; 60 | CEDE8D7722984F7700C73034 /* _label.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = _label.h; sourceTree = ""; }; 61 | CEDE8D7822984F7700C73034 /* plugin_start.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = plugin_start.cpp; sourceTree = ""; }; 62 | CEDE8D7922984F7700C73034 /* LegacyIOService.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = LegacyIOService.h; sourceTree = ""; }; 63 | CEDE8D7D2298501600C73034 /* kern_start.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = kern_start.cpp; sourceTree = ""; }; 64 | /* End PBXFileReference section */ 65 | 66 | /* Begin PBXFrameworksBuildPhase section */ 67 | CEDE8CE222984C0800C73034 /* Frameworks */ = { 68 | isa = PBXFrameworksBuildPhase; 69 | buildActionMask = 2147483647; 70 | files = ( 71 | CEDE8D7B22984F8F00C73034 /* libkmod.a in Frameworks */, 72 | ); 73 | runOnlyForDeploymentPostprocessing = 0; 74 | }; 75 | /* End PBXFrameworksBuildPhase section */ 76 | 77 | /* Begin PBXGroup section */ 78 | CEDE8CDB22984C0800C73034 = { 79 | isa = PBXGroup; 80 | children = ( 81 | CEDE8D4B22984F5B00C73034 /* SDK */, 82 | CEDE8CE722984C0800C73034 /* ThunderboltReset */, 83 | CEDE8CE622984C0800C73034 /* Products */, 84 | ); 85 | sourceTree = ""; 86 | }; 87 | CEDE8CE622984C0800C73034 /* Products */ = { 88 | isa = PBXGroup; 89 | children = ( 90 | CEDE8CE522984C0800C73034 /* ThunderboltReset.kext */, 91 | ); 92 | name = Products; 93 | sourceTree = ""; 94 | }; 95 | CEDE8CE722984C0800C73034 /* ThunderboltReset */ = { 96 | isa = PBXGroup; 97 | children = ( 98 | CEDE8CEC22984C0800C73034 /* Info.plist */, 99 | CEDE8D7D2298501600C73034 /* kern_start.cpp */, 100 | CE0D113B2377FA5F003BE3C3 /* ThunderboltWait.cpp */, 101 | CE0D113C2377FA5F003BE3C3 /* ThunderboltWait.hpp */, 102 | ); 103 | path = ThunderboltReset; 104 | sourceTree = ""; 105 | }; 106 | CEDE8D4B22984F5B00C73034 /* SDK */ = { 107 | isa = PBXGroup; 108 | children = ( 109 | CEDE8D4C22984F7600C73034 /* Headers */, 110 | CEDE8D6D22984F7700C73034 /* Library */, 111 | ); 112 | name = SDK; 113 | sourceTree = ""; 114 | }; 115 | CEDE8D4C22984F7600C73034 /* Headers */ = { 116 | isa = PBXGroup; 117 | children = ( 118 | CEDE8D4D22984F7600C73034 /* kern_config.hpp */, 119 | CEDE8D4E22984F7600C73034 /* kern_atomic.hpp */, 120 | CEDE8D4F22984F7600C73034 /* kern_time.hpp */, 121 | CEDE8D5022984F7600C73034 /* kern_nvram.hpp */, 122 | CEDE8D5122984F7600C73034 /* kern_cpu.hpp */, 123 | CEDE8D5222984F7600C73034 /* kern_devinfo.hpp */, 124 | CEDE8D5322984F7600C73034 /* kern_efi.hpp */, 125 | CEDE8D5422984F7600C73034 /* kern_policy.hpp */, 126 | CEDE8D5522984F7600C73034 /* kern_user.hpp */, 127 | CEDE8D5622984F7600C73034 /* plugin_start.hpp */, 128 | CEDE8D5722984F7600C73034 /* kern_iokit.hpp */, 129 | CEDE8D5822984F7600C73034 /* kern_crypto.hpp */, 130 | CEDE8D5922984F7600C73034 /* kern_mach.hpp */, 131 | CEDE8D5A22984F7600C73034 /* kern_compression.hpp */, 132 | CEDE8D5B22984F7600C73034 /* kern_file.hpp */, 133 | CEDE8D5C22984F7600C73034 /* kern_rtc.hpp */, 134 | CEDE8D5D22984F7700C73034 /* kern_disasm.hpp */, 135 | CEDE8D5E22984F7700C73034 /* capstone */, 136 | CEDE8D6922984F7700C73034 /* kern_patcher.hpp */, 137 | CEDE8D6A22984F7700C73034 /* kern_compat.hpp */, 138 | CEDE8D6B22984F7700C73034 /* kern_api.hpp */, 139 | CEDE8D6C22984F7700C73034 /* kern_util.hpp */, 140 | ); 141 | name = Headers; 142 | path = Lilu.kext/Contents/Resources/Headers; 143 | sourceTree = ""; 144 | }; 145 | CEDE8D5E22984F7700C73034 /* capstone */ = { 146 | isa = PBXGroup; 147 | children = ( 148 | CEDE8D5F22984F7700C73034 /* capstone.h */, 149 | CEDE8D6022984F7700C73034 /* mips.h */, 150 | CEDE8D6122984F7700C73034 /* sparc.h */, 151 | CEDE8D6222984F7700C73034 /* systemz.h */, 152 | CEDE8D6322984F7700C73034 /* arm.h */, 153 | CEDE8D6422984F7700C73034 /* x86.h */, 154 | CEDE8D6522984F7700C73034 /* ppc.h */, 155 | CEDE8D6622984F7700C73034 /* arm64.h */, 156 | CEDE8D6722984F7700C73034 /* xcore.h */, 157 | CEDE8D6822984F7700C73034 /* platform.h */, 158 | ); 159 | path = capstone; 160 | sourceTree = ""; 161 | }; 162 | CEDE8D6D22984F7700C73034 /* Library */ = { 163 | isa = PBXGroup; 164 | children = ( 165 | CEDE8D6E22984F7700C73034 /* libkmod.a */, 166 | CEDE8D6F22984F7700C73034 /* wrappers */, 167 | CEDE8D7422984F7700C73034 /* security */, 168 | CEDE8D7822984F7700C73034 /* plugin_start.cpp */, 169 | CEDE8D7922984F7700C73034 /* LegacyIOService.h */, 170 | ); 171 | name = Library; 172 | path = Lilu.kext/Contents/Resources/Library; 173 | sourceTree = ""; 174 | }; 175 | CEDE8D6F22984F7700C73034 /* wrappers */ = { 176 | isa = PBXGroup; 177 | children = ( 178 | CEDE8D7022984F7700C73034 /* entry64.S */, 179 | CEDE8D7122984F7700C73034 /* build.tool */, 180 | CEDE8D7222984F7700C73034 /* entry32.S */, 181 | CEDE8D7322984F7700C73034 /* wrappers.inc */, 182 | ); 183 | path = wrappers; 184 | sourceTree = ""; 185 | }; 186 | CEDE8D7422984F7700C73034 /* security */ = { 187 | isa = PBXGroup; 188 | children = ( 189 | CEDE8D7522984F7700C73034 /* mac_framework.h */, 190 | CEDE8D7622984F7700C73034 /* mac_policy.h */, 191 | CEDE8D7722984F7700C73034 /* _label.h */, 192 | ); 193 | path = security; 194 | sourceTree = ""; 195 | }; 196 | /* End PBXGroup section */ 197 | 198 | /* Begin PBXHeadersBuildPhase section */ 199 | CEDE8CE022984C0800C73034 /* Headers */ = { 200 | isa = PBXHeadersBuildPhase; 201 | buildActionMask = 2147483647; 202 | files = ( 203 | CE0D113E2377FA5F003BE3C3 /* ThunderboltWait.hpp in Headers */, 204 | ); 205 | runOnlyForDeploymentPostprocessing = 0; 206 | }; 207 | /* End PBXHeadersBuildPhase section */ 208 | 209 | /* Begin PBXNativeTarget section */ 210 | CEDE8CE422984C0800C73034 /* ThunderboltReset */ = { 211 | isa = PBXNativeTarget; 212 | buildConfigurationList = CEDE8CEF22984C0800C73034 /* Build configuration list for PBXNativeTarget "ThunderboltReset" */; 213 | buildPhases = ( 214 | CEDE8CE022984C0800C73034 /* Headers */, 215 | CEDE8CE122984C0800C73034 /* Sources */, 216 | CEDE8CE222984C0800C73034 /* Frameworks */, 217 | CEDE8CE322984C0800C73034 /* Resources */, 218 | ); 219 | buildRules = ( 220 | ); 221 | dependencies = ( 222 | ); 223 | name = ThunderboltReset; 224 | productName = Polaris22Fixup; 225 | productReference = CEDE8CE522984C0800C73034 /* ThunderboltReset.kext */; 226 | productType = "com.apple.product-type.kernel-extension"; 227 | }; 228 | /* End PBXNativeTarget section */ 229 | 230 | /* Begin PBXProject section */ 231 | CEDE8CDC22984C0800C73034 /* Project object */ = { 232 | isa = PBXProject; 233 | attributes = { 234 | LastUpgradeCheck = 1020; 235 | ORGANIZATIONNAME = osy86; 236 | TargetAttributes = { 237 | CEDE8CE422984C0800C73034 = { 238 | CreatedOnToolsVersion = 10.2.1; 239 | }; 240 | }; 241 | }; 242 | buildConfigurationList = CEDE8CDF22984C0800C73034 /* Build configuration list for PBXProject "ThunderboltReset" */; 243 | compatibilityVersion = "Xcode 9.3"; 244 | developmentRegion = en; 245 | hasScannedForEncodings = 0; 246 | knownRegions = ( 247 | en, 248 | ); 249 | mainGroup = CEDE8CDB22984C0800C73034; 250 | productRefGroup = CEDE8CE622984C0800C73034 /* Products */; 251 | projectDirPath = ""; 252 | projectRoot = ""; 253 | targets = ( 254 | CEDE8CE422984C0800C73034 /* ThunderboltReset */, 255 | ); 256 | }; 257 | /* End PBXProject section */ 258 | 259 | /* Begin PBXResourcesBuildPhase section */ 260 | CEDE8CE322984C0800C73034 /* Resources */ = { 261 | isa = PBXResourcesBuildPhase; 262 | buildActionMask = 2147483647; 263 | files = ( 264 | ); 265 | runOnlyForDeploymentPostprocessing = 0; 266 | }; 267 | /* End PBXResourcesBuildPhase section */ 268 | 269 | /* Begin PBXSourcesBuildPhase section */ 270 | CEDE8CE122984C0800C73034 /* Sources */ = { 271 | isa = PBXSourcesBuildPhase; 272 | buildActionMask = 2147483647; 273 | files = ( 274 | CEDE8D7C22984FE600C73034 /* plugin_start.cpp in Sources */, 275 | CE0D113D2377FA5F003BE3C3 /* ThunderboltWait.cpp in Sources */, 276 | CEDE8D7E2298501600C73034 /* kern_start.cpp in Sources */, 277 | ); 278 | runOnlyForDeploymentPostprocessing = 0; 279 | }; 280 | /* End PBXSourcesBuildPhase section */ 281 | 282 | /* Begin XCBuildConfiguration section */ 283 | CEDE8CED22984C0800C73034 /* Debug */ = { 284 | isa = XCBuildConfiguration; 285 | buildSettings = { 286 | ALWAYS_SEARCH_USER_PATHS = NO; 287 | CLANG_ANALYZER_NONNULL = YES; 288 | CLANG_ANALYZER_NUMBER_OBJECT_CONVERSION = YES_AGGRESSIVE; 289 | CLANG_CXX_LANGUAGE_STANDARD = "gnu++14"; 290 | CLANG_CXX_LIBRARY = "libc++"; 291 | CLANG_ENABLE_MODULES = YES; 292 | CLANG_ENABLE_OBJC_ARC = YES; 293 | CLANG_ENABLE_OBJC_WEAK = YES; 294 | CLANG_WARN_BLOCK_CAPTURE_AUTORELEASING = YES; 295 | CLANG_WARN_BOOL_CONVERSION = YES; 296 | CLANG_WARN_COMMA = YES; 297 | CLANG_WARN_CONSTANT_CONVERSION = YES; 298 | CLANG_WARN_DEPRECATED_OBJC_IMPLEMENTATIONS = YES; 299 | CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; 300 | CLANG_WARN_DOCUMENTATION_COMMENTS = YES; 301 | CLANG_WARN_EMPTY_BODY = YES; 302 | CLANG_WARN_ENUM_CONVERSION = YES; 303 | CLANG_WARN_INFINITE_RECURSION = YES; 304 | CLANG_WARN_INT_CONVERSION = YES; 305 | CLANG_WARN_NON_LITERAL_NULL_CONVERSION = YES; 306 | CLANG_WARN_OBJC_IMPLICIT_RETAIN_SELF = YES; 307 | CLANG_WARN_OBJC_LITERAL_CONVERSION = YES; 308 | CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; 309 | CLANG_WARN_RANGE_LOOP_ANALYSIS = YES; 310 | CLANG_WARN_STRICT_PROTOTYPES = YES; 311 | CLANG_WARN_SUSPICIOUS_MOVE = YES; 312 | CLANG_WARN_UNGUARDED_AVAILABILITY = YES_AGGRESSIVE; 313 | CLANG_WARN_UNREACHABLE_CODE = YES; 314 | CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; 315 | CODE_SIGN_IDENTITY = "-"; 316 | COPY_PHASE_STRIP = NO; 317 | DEBUG_INFORMATION_FORMAT = dwarf; 318 | ENABLE_STRICT_OBJC_MSGSEND = YES; 319 | ENABLE_TESTABILITY = YES; 320 | GCC_C_LANGUAGE_STANDARD = gnu11; 321 | GCC_DYNAMIC_NO_PIC = NO; 322 | GCC_NO_COMMON_BLOCKS = YES; 323 | GCC_OPTIMIZATION_LEVEL = 0; 324 | GCC_PREPROCESSOR_DEFINITIONS = ( 325 | "DEBUG=1", 326 | "$(inherited)", 327 | ); 328 | GCC_WARN_64_TO_32_BIT_CONVERSION = YES; 329 | GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; 330 | GCC_WARN_UNDECLARED_SELECTOR = YES; 331 | GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; 332 | GCC_WARN_UNUSED_FUNCTION = YES; 333 | GCC_WARN_UNUSED_VARIABLE = YES; 334 | MACOSX_DEPLOYMENT_TARGET = 10.14; 335 | MTL_ENABLE_DEBUG_INFO = INCLUDE_SOURCE; 336 | MTL_FAST_MATH = YES; 337 | ONLY_ACTIVE_ARCH = YES; 338 | SDKROOT = macosx; 339 | }; 340 | name = Debug; 341 | }; 342 | CEDE8CEE22984C0800C73034 /* Release */ = { 343 | isa = XCBuildConfiguration; 344 | buildSettings = { 345 | ALWAYS_SEARCH_USER_PATHS = NO; 346 | CLANG_ANALYZER_NONNULL = YES; 347 | CLANG_ANALYZER_NUMBER_OBJECT_CONVERSION = YES_AGGRESSIVE; 348 | CLANG_CXX_LANGUAGE_STANDARD = "gnu++14"; 349 | CLANG_CXX_LIBRARY = "libc++"; 350 | CLANG_ENABLE_MODULES = YES; 351 | CLANG_ENABLE_OBJC_ARC = YES; 352 | CLANG_ENABLE_OBJC_WEAK = YES; 353 | CLANG_WARN_BLOCK_CAPTURE_AUTORELEASING = YES; 354 | CLANG_WARN_BOOL_CONVERSION = YES; 355 | CLANG_WARN_COMMA = YES; 356 | CLANG_WARN_CONSTANT_CONVERSION = YES; 357 | CLANG_WARN_DEPRECATED_OBJC_IMPLEMENTATIONS = YES; 358 | CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR; 359 | CLANG_WARN_DOCUMENTATION_COMMENTS = YES; 360 | CLANG_WARN_EMPTY_BODY = YES; 361 | CLANG_WARN_ENUM_CONVERSION = YES; 362 | CLANG_WARN_INFINITE_RECURSION = YES; 363 | CLANG_WARN_INT_CONVERSION = YES; 364 | CLANG_WARN_NON_LITERAL_NULL_CONVERSION = YES; 365 | CLANG_WARN_OBJC_IMPLICIT_RETAIN_SELF = YES; 366 | CLANG_WARN_OBJC_LITERAL_CONVERSION = YES; 367 | CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR; 368 | CLANG_WARN_RANGE_LOOP_ANALYSIS = YES; 369 | CLANG_WARN_STRICT_PROTOTYPES = YES; 370 | CLANG_WARN_SUSPICIOUS_MOVE = YES; 371 | CLANG_WARN_UNGUARDED_AVAILABILITY = YES_AGGRESSIVE; 372 | CLANG_WARN_UNREACHABLE_CODE = YES; 373 | CLANG_WARN__DUPLICATE_METHOD_MATCH = YES; 374 | CODE_SIGN_IDENTITY = "-"; 375 | COPY_PHASE_STRIP = NO; 376 | DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym"; 377 | ENABLE_NS_ASSERTIONS = NO; 378 | ENABLE_STRICT_OBJC_MSGSEND = YES; 379 | GCC_C_LANGUAGE_STANDARD = gnu11; 380 | GCC_NO_COMMON_BLOCKS = YES; 381 | GCC_WARN_64_TO_32_BIT_CONVERSION = YES; 382 | GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; 383 | GCC_WARN_UNDECLARED_SELECTOR = YES; 384 | GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE; 385 | GCC_WARN_UNUSED_FUNCTION = YES; 386 | GCC_WARN_UNUSED_VARIABLE = YES; 387 | MACOSX_DEPLOYMENT_TARGET = 10.14; 388 | MTL_ENABLE_DEBUG_INFO = NO; 389 | MTL_FAST_MATH = YES; 390 | SDKROOT = macosx; 391 | }; 392 | name = Release; 393 | }; 394 | CEDE8CF022984C0800C73034 /* Debug */ = { 395 | isa = XCBuildConfiguration; 396 | buildSettings = { 397 | CODE_SIGN_STYLE = Automatic; 398 | COMBINE_HIDPI_IMAGES = YES; 399 | CURRENT_PROJECT_VERSION = 1.0.0d1; 400 | GCC_PREPROCESSOR_DEFINITIONS = ( 401 | "$(inherited)", 402 | "MODULE_VERSION=$(MODULE_VERSION)", 403 | "PRODUCT_NAME=$(PRODUCT_NAME)", 404 | ); 405 | HEADER_SEARCH_PATHS = "${PROJECT_DIR}/Lilu.kext/Contents/Resources"; 406 | INFOPLIST_FILE = ThunderboltReset/Info.plist; 407 | LIBRARY_SEARCH_PATHS = "$(PROJECT_DIR)/Lilu.kext/Contents/Resources/Library"; 408 | MODULE_NAME = com.osy86.ThunderboltReset; 409 | MODULE_START = "$(PRODUCT_NAME)_kern_start"; 410 | MODULE_STOP = "$(PRODUCT_NAME)_kern_stop"; 411 | MODULE_VERSION = 1.0.0d1; 412 | PRODUCT_BUNDLE_IDENTIFIER = com.osy86.ThunderboltReset; 413 | PRODUCT_NAME = "$(TARGET_NAME)"; 414 | WRAPPER_EXTENSION = kext; 415 | }; 416 | name = Debug; 417 | }; 418 | CEDE8CF122984C0800C73034 /* Release */ = { 419 | isa = XCBuildConfiguration; 420 | buildSettings = { 421 | CODE_SIGN_STYLE = Automatic; 422 | COMBINE_HIDPI_IMAGES = YES; 423 | CURRENT_PROJECT_VERSION = 1.0.0d1; 424 | GCC_PREPROCESSOR_DEFINITIONS = ( 425 | "$(inherited)", 426 | "MODULE_VERSION=$(MODULE_VERSION)", 427 | "PRODUCT_NAME=$(PRODUCT_NAME)", 428 | ); 429 | HEADER_SEARCH_PATHS = "${PROJECT_DIR}/Lilu.kext/Contents/Resources"; 430 | INFOPLIST_FILE = ThunderboltReset/Info.plist; 431 | LIBRARY_SEARCH_PATHS = "$(PROJECT_DIR)/Lilu.kext/Contents/Resources/Library"; 432 | MODULE_NAME = com.osy86.ThunderboltReset; 433 | MODULE_START = "$(PRODUCT_NAME)_kern_start"; 434 | MODULE_STOP = "$(PRODUCT_NAME)_kern_stop"; 435 | MODULE_VERSION = 1.0.0d1; 436 | PRODUCT_BUNDLE_IDENTIFIER = com.osy86.ThunderboltReset; 437 | PRODUCT_NAME = "$(TARGET_NAME)"; 438 | WRAPPER_EXTENSION = kext; 439 | }; 440 | name = Release; 441 | }; 442 | /* End XCBuildConfiguration section */ 443 | 444 | /* Begin XCConfigurationList section */ 445 | CEDE8CDF22984C0800C73034 /* Build configuration list for PBXProject "ThunderboltReset" */ = { 446 | isa = XCConfigurationList; 447 | buildConfigurations = ( 448 | CEDE8CED22984C0800C73034 /* Debug */, 449 | CEDE8CEE22984C0800C73034 /* Release */, 450 | ); 451 | defaultConfigurationIsVisible = 0; 452 | defaultConfigurationName = Release; 453 | }; 454 | CEDE8CEF22984C0800C73034 /* Build configuration list for PBXNativeTarget "ThunderboltReset" */ = { 455 | isa = XCConfigurationList; 456 | buildConfigurations = ( 457 | CEDE8CF022984C0800C73034 /* Debug */, 458 | CEDE8CF122984C0800C73034 /* Release */, 459 | ); 460 | defaultConfigurationIsVisible = 0; 461 | defaultConfigurationName = Release; 462 | }; 463 | /* End XCConfigurationList section */ 464 | }; 465 | rootObject = CEDE8CDC22984C0800C73034 /* Project object */; 466 | } 467 | -------------------------------------------------------------------------------- /ThunderboltNative/SSDT-TbtOnPCH.asl: -------------------------------------------------------------------------------- 1 | /** 2 | * Thunderbolt For Alpine Ridge 3 | * Large parts (link training and enumeration) 4 | * taken from decompiled Mac AML. 5 | * Note: USB/CIO RTD3 power management largly 6 | * missing due to lack of GPIO pins. 7 | * 8 | * Copyright (c) 2019 osy86 9 | */ 10 | #ifndef SSDT_NAME 11 | #define SSDT_NAME "TbtOnPCH" 12 | #endif 13 | DefinitionBlock ("", "SSDT", 2, "OSY86 ", SSDT_NAME, 0x00001000) 14 | { 15 | #ifndef TARGET 16 | #error "Must define TARGET" 17 | #endif 18 | #define XSTR(x) #x 19 | #define STR(x) XSTR(x) 20 | #include STR(SSDT-TbtOnPCH-TARGET.asl) 21 | 22 | /* Support methods */ 23 | External (DTGP, MethodObj) 24 | External (OSDW, MethodObj) // OS Is Darwin? 25 | External (\RMDT.P1, MethodObj) // Debug printing 26 | External (\RMDT.P2, MethodObj) // Debug printing 27 | External (\RMDT.P3, MethodObj) // Debug printing 28 | 29 | Scope (\_GPE) 30 | { 31 | Method (TBT_HOTPLUG_GPE, 0, NotSerialized) // _Exx: Edge-Triggered GPE 32 | { 33 | TBT_ROOT.DBG1 ("Hot plug event") 34 | If (!TBT_ROOT.OHPE ()) 35 | { 36 | Return 37 | } 38 | #ifndef NO_WINDOWS_SUPPORT 39 | If (!OSDW ()) 40 | { 41 | If (TBT_ROOT.POC0 == One) 42 | { 43 | Return 44 | } 45 | 46 | Sleep (400) 47 | If (TBT_ROOT.WTLT () == One) 48 | { 49 | TBT_ROOT.ICMS () 50 | } 51 | Else // force power off 52 | { 53 | //\_SB.SGOV (0x01070004, Zero) 54 | //\_SB.SGDO (0x01070004) 55 | } 56 | 57 | If (TBT_ROOT.UPMB) 58 | { 59 | TBT_ROOT.UPMB = Zero 60 | Sleep (One) 61 | } 62 | 63 | TBT_ROOT.CMPE () 64 | } 65 | /* 66 | ElseIf (\_SB.GGII (0x01070015) == One) 67 | { 68 | \_SB.SGII (0x01070015, Zero) 69 | } 70 | Else 71 | { 72 | \_SB.SGII (0x01070015, One) 73 | } 74 | */ 75 | Else 76 | { 77 | TBT_ROOT.UPSB.AMPE () 78 | } 79 | #else // NO_WINDOWS_SUPPORT 80 | TBT_ROOT.UPSB.AMPE () 81 | #endif 82 | TBT_ROOT.DBG1 ("End hotplug handler") 83 | } 84 | } 85 | 86 | Name(U2OP, TBT_HAS_COMPANION) // use companion controller 87 | 88 | Scope (TBT_ROOT) 89 | { 90 | // Use https://github.com/RehabMan/OS-X-ACPI-Debug 91 | // to see debug messages 92 | 93 | Method (DBG1, 1, NotSerialized) 94 | { 95 | If (CondRefOf (\RMDT.P1)) 96 | { 97 | \RMDT.P1 (Arg0) 98 | } 99 | } 100 | 101 | Method (DBG2, 2, NotSerialized) 102 | { 103 | If (CondRefOf (\RMDT.P2)) 104 | { 105 | \RMDT.P2 (Arg0, Arg1) 106 | } 107 | } 108 | 109 | Method (DBG3, 3, NotSerialized) 110 | { 111 | If (CondRefOf (\RMDT.P3)) 112 | { 113 | \RMDT.P3 (Arg0, Arg1, Arg2) 114 | } 115 | } 116 | 117 | #ifndef NO_WINDOWS_SUPPORT 118 | #include "SSDT-TbtOnPCH-Boot.asl" 119 | #endif 120 | 121 | Name (IIP3, Zero) 122 | Name (PRSR, Zero) 123 | Name (PCIA, One) 124 | 125 | /** 126 | * Bring up PCI link 127 | * Train downstream link 128 | */ 129 | Method (PCEU, 0, Serialized) 130 | { 131 | TBT_ROOT.PRSR = Zero 132 | If (TBT_ROOT.PSTA != Zero) 133 | { 134 | TBT_ROOT.PRSR = One 135 | TBT_ROOT.PSTA = Zero 136 | } 137 | 138 | If (TBT_ROOT.LDXX == One) 139 | { 140 | TBT_ROOT.PRSR = One 141 | TBT_ROOT.LDXX = Zero 142 | } 143 | } 144 | 145 | /** 146 | * Bring down PCI link 147 | */ 148 | Method (PCDA, 0, Serialized) 149 | { 150 | If (TBT_ROOT.POFF () != Zero) 151 | { 152 | TBT_ROOT.PCIA = Zero 153 | TBT_ROOT.PSTA = 0x03 154 | TBT_ROOT.LDXX = One 155 | Local5 = (Timer + 10000000) 156 | While (Timer <= Local5) 157 | { 158 | If (TBT_ROOT.LACR == One) 159 | { 160 | If (TBT_ROOT.LACT == Zero) 161 | { 162 | Break 163 | } 164 | } 165 | ElseIf (TBT_ROOT.UPSB.AVND == 0xFFFFFFFF) 166 | { 167 | Break 168 | } 169 | 170 | Sleep (10) 171 | } 172 | 173 | TBT_ROOT.GPCI = Zero 174 | TBT_ROOT.UGIO () 175 | } 176 | Else 177 | { 178 | } 179 | 180 | TBT_ROOT.IIP3 = One 181 | } 182 | 183 | /** 184 | * Returns true if both TB and TB-USB are idle 185 | */ 186 | Method (POFF, 0, Serialized) 187 | { 188 | Return ((!TBT_ROOT.RTBT && !TBT_ROOT.RUSB)) 189 | } 190 | 191 | Name (GPCI, One) 192 | Name (GNHI, One) 193 | Name (GXCI, One) 194 | Name (RTBT, One) 195 | Name (RUSB, One) 196 | Name (CTPD, Zero) 197 | 198 | /** 199 | * Send power down ack to CP 200 | */ 201 | Method (CTBT, 0, Serialized) 202 | { 203 | //If ((GGDV (0x01070004) == One) && (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF)) 204 | If (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF) 205 | { 206 | Local2 = TBT_ROOT.UPSB.CRMW (0x3C, Zero, 0x02, 0x04000000, 0x04000000) 207 | If (Local2 == Zero) 208 | { 209 | TBT_ROOT.CTPD = One 210 | } 211 | } 212 | } 213 | 214 | /** 215 | * Toggle controller power 216 | * Power controllers either up or down depending on the request. 217 | * On Macs, there's two GPIO signals for controlling TB and XHC 218 | * separately. If such signals exist, we need to find it. Otherwise 219 | * we lose the power saving capabilities. 220 | * Returns if controller is powered up 221 | */ 222 | Method (UGIO, 0, Serialized) 223 | { 224 | // Which controller is requested to be on? 225 | Local0 = (TBT_ROOT.GNHI || TBT_ROOT.RTBT) // TBT 226 | Local1 = (TBT_ROOT.GXCI || TBT_ROOT.RUSB) // USB 227 | DBG3 ("UGIO", Local0, Local1) 228 | If (TBT_ROOT.GPCI != Zero) 229 | { 230 | // if neither are requested to be on but the NHI controller 231 | // needs to be up, then we go ahead and power it on anyways 232 | If ((Local0 == Zero) && (Local1 == Zero)) 233 | { 234 | Local0 = One 235 | Local1 = One 236 | } 237 | } 238 | 239 | Local2 = Zero 240 | 241 | /** 242 | * Force power to CIO 243 | */ 244 | If (Local0 != Zero) 245 | { 246 | // TODO: check if CIO power is forced 247 | //If (GGDV (0x01070004) == Zero) 248 | If (Zero) 249 | { 250 | // TODO: force CIO power 251 | //SGDI (0x01070004) 252 | Local2 = One 253 | TBT_ROOT.CTPD = Zero 254 | } 255 | } 256 | 257 | /** 258 | * Force power to USB 259 | */ 260 | If (Local1 != Zero) 261 | { 262 | // TODO: check if USB power is forced 263 | //If (GGDV (0x01070007) == Zero) 264 | If (Zero) 265 | { 266 | // TODO: force USB power 267 | //SGDI (0x01070007) 268 | Local2 = One 269 | } 270 | } 271 | 272 | // if we did power on 273 | If (Local2 != Zero) 274 | { 275 | Sleep (500) 276 | } 277 | 278 | Local3 = Zero 279 | 280 | /** 281 | * Disable force power to CIO 282 | */ 283 | If (Local0 == Zero) 284 | { 285 | // TODO: check if CIO power is off 286 | //If (GGDV (0x01070004) == One) 287 | If (Zero) 288 | { 289 | TBT_ROOT.CTBT () 290 | If (TBT_ROOT.CTPD != Zero) 291 | { 292 | // TODO: force power off CIO 293 | //SGOV (0x01070004, Zero) 294 | //SGDO (0x01070004) 295 | Local3 = One 296 | } 297 | } 298 | } 299 | 300 | /** 301 | * Disable force power to USB 302 | */ 303 | If (Local1 == Zero) 304 | { 305 | //If (GGDV (0x01070007) == One) 306 | If (Zero) 307 | { 308 | // TODO: force power off USB 309 | //SGOV (0x01070007, Zero) 310 | //SGDO (0x01070007) 311 | Local3 = One 312 | } 313 | } 314 | 315 | // if we did power down, wait for things to settle 316 | If (Local3 != Zero) 317 | { 318 | Sleep (100) 319 | } 320 | DBG3 ("UGIO finish", Local2, Local3) 321 | 322 | Return (Local2) 323 | } 324 | 325 | Method (_PS0, 0, Serialized) // _PS0: Power State 0 326 | { 327 | If (OSDW ()) 328 | { 329 | PCEU () 330 | } 331 | } 332 | 333 | Method (_PS3, 0, Serialized) // _PS3: Power State 3 334 | { 335 | If (OSDW ()) 336 | { 337 | If (TBT_ROOT.POFF () != Zero) 338 | { 339 | TBT_ROOT.CTBT () 340 | } 341 | 342 | PCDA () 343 | } 344 | } 345 | 346 | Method (UTLK, 2, Serialized) 347 | { 348 | Local0 = Zero 349 | // if CIO force power is zero 350 | //If ((GGOV (0x01070004) == Zero) && (GGDV (0x01070004) == Zero)) 351 | If (Zero) 352 | { 353 | TBT_ROOT.PSTA = Zero 354 | While (One) 355 | { 356 | If (TBT_ROOT.LDXX == One) 357 | { 358 | TBT_ROOT.LDXX = Zero 359 | } 360 | 361 | // here, we force CIO power on 362 | //SGDI (0x01070004) 363 | Local1 = Zero 364 | Local2 = (Timer + 10000000) 365 | While (Timer <= Local2) 366 | { 367 | If (TBT_ROOT.LACR == Zero) 368 | { 369 | If (TBT_ROOT.LTRN != One) 370 | { 371 | Break 372 | } 373 | } 374 | ElseIf ((TBT_ROOT.LTRN != One) && (TBT_ROOT.LACT == One)) 375 | { 376 | Break 377 | } 378 | 379 | Sleep (10) 380 | } 381 | 382 | Sleep (Arg1) 383 | While (Timer <= Local2) 384 | { 385 | If (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF) 386 | { 387 | Local1 = One 388 | Break 389 | } 390 | 391 | Sleep (10) 392 | } 393 | 394 | If (Local1 == One) 395 | { 396 | TBT_ROOT.MABT = One 397 | Break 398 | } 399 | 400 | If (Local0 == 0x04) 401 | { 402 | Break 403 | } 404 | 405 | Local0++ 406 | // CIO force power back to 0 407 | //SGOV (0x01070004, Zero) 408 | //SGDO (0x01070004) 409 | Sleep (1000) 410 | } 411 | } 412 | } 413 | 414 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 415 | Field (A1E0, ByteAcc, NoLock, Preserve) 416 | { 417 | AVND, 32, 418 | BMIE, 3, 419 | Offset (0x18), 420 | PRIB, 8, 421 | SECB, 8, 422 | SUBB, 8, 423 | Offset (0x1E), 424 | , 13, 425 | MABT, 1 426 | } 427 | 428 | OperationRegion (HD94, PCI_Config, 0x0D94, 0x08) 429 | Field (HD94, ByteAcc, NoLock, Preserve) 430 | { 431 | Offset (0x04), 432 | PLEQ, 1, 433 | Offset (0x08) 434 | } 435 | 436 | OperationRegion (A1E1, PCI_Config, 0x40, 0x40) 437 | Field (A1E1, ByteAcc, NoLock, Preserve) 438 | { 439 | Offset (0x01), 440 | Offset (0x02), 441 | Offset (0x04), 442 | Offset (0x08), 443 | Offset (0x0A), 444 | , 5, 445 | TPEN, 1, 446 | Offset (0x0C), 447 | SSPD, 4, 448 | , 16, 449 | LACR, 1, 450 | Offset (0x10), 451 | , 4, 452 | LDXX, 1, 453 | LRTN, 1, 454 | Offset (0x12), 455 | CSPD, 4, 456 | CWDT, 6, 457 | , 1, 458 | LTRN, 1, 459 | , 1, 460 | LACT, 1, 461 | Offset (0x14), 462 | Offset (0x30), 463 | TSPD, 4 464 | } 465 | 466 | OperationRegion (A1E2, PCI_Config, 0xA0, 0x08) 467 | Field (A1E2, ByteAcc, NoLock, Preserve) 468 | { 469 | Offset (0x01), 470 | Offset (0x02), 471 | Offset (0x04), 472 | PSTA, 2 473 | } 474 | 475 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 476 | { 477 | Return (Zero) 478 | } 479 | 480 | Device (UPSB) 481 | { 482 | Name (_ADR, Zero) // _ADR: Address 483 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 484 | Field (A1E0, ByteAcc, NoLock, Preserve) 485 | { 486 | AVND, 32, 487 | BMIE, 3, 488 | Offset (0x18), 489 | PRIB, 8, 490 | SECB, 8, 491 | SUBB, 8, 492 | Offset (0x1E), 493 | , 13, 494 | MABT, 1 495 | } 496 | 497 | OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) 498 | Field (A1E1, ByteAcc, NoLock, Preserve) 499 | { 500 | Offset (0x01), 501 | Offset (0x02), 502 | Offset (0x04), 503 | Offset (0x08), 504 | Offset (0x0A), 505 | , 5, 506 | TPEN, 1, 507 | Offset (0x0C), 508 | SSPD, 4, 509 | , 16, 510 | LACR, 1, 511 | Offset (0x10), 512 | , 4, 513 | LDIS, 1, 514 | LRTN, 1, 515 | Offset (0x12), 516 | CSPD, 4, 517 | CWDT, 6, 518 | , 1, 519 | LTRN, 1, 520 | , 1, 521 | LACT, 1, 522 | Offset (0x14), 523 | Offset (0x30), 524 | TSPD, 4 525 | } 526 | 527 | OperationRegion (A1E2, PCI_Config, 0x80, 0x08) 528 | Field (A1E2, ByteAcc, NoLock, Preserve) 529 | { 530 | Offset (0x01), 531 | Offset (0x02), 532 | Offset (0x04), 533 | PSTA, 2 534 | } 535 | 536 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 537 | { 538 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.SECB */ 539 | } 540 | 541 | Method (_STA, 0, NotSerialized) // _STA: Status 542 | { 543 | Return (0x0F) // visible for everyone 544 | } 545 | 546 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 547 | { 548 | Return (Zero) 549 | } 550 | 551 | /** 552 | * Enable downstream link 553 | */ 554 | Method (PCED, 0, Serialized) 555 | { 556 | TBT_ROOT.GPCI = One 557 | // power up the controller 558 | If (TBT_ROOT.UGIO () != Zero) 559 | { 560 | TBT_ROOT.PRSR = One 561 | } 562 | 563 | Local0 = Zero 564 | Local1 = Zero 565 | If (Local1 == Zero) 566 | { 567 | If (TBT_ROOT.IIP3 != Zero) 568 | { 569 | TBT_ROOT.PRSR = One 570 | Local0 = One 571 | TBT_ROOT.LDXX = One 572 | } 573 | } 574 | 575 | Local5 = (Timer + 10000000) 576 | If (TBT_ROOT.PRSR != Zero) 577 | { 578 | Sleep (30) 579 | If ((Local0 != Zero) || (Local1 != Zero)) 580 | { 581 | TBT_ROOT.TSPD = One 582 | If (Local1 != Zero) {} 583 | ElseIf (Local0 != Zero) 584 | { 585 | TBT_ROOT.LDXX = Zero 586 | } 587 | 588 | While (Timer <= Local5) 589 | { 590 | If (TBT_ROOT.LACR == Zero) 591 | { 592 | If (TBT_ROOT.LTRN != One) 593 | { 594 | Break 595 | } 596 | } 597 | ElseIf ((TBT_ROOT.LTRN != One) && (TBT_ROOT.LACT == One)) 598 | { 599 | Break 600 | } 601 | 602 | Sleep (10) 603 | } 604 | 605 | Sleep (120) 606 | While (Timer <= Local5) 607 | { 608 | If (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF) 609 | { 610 | Break 611 | } 612 | 613 | Sleep (10) 614 | } 615 | 616 | TBT_ROOT.TSPD = 0x03 617 | TBT_ROOT.LRTN = One 618 | } 619 | 620 | Local5 = (Timer + 10000000) 621 | While (Timer <= Local5) 622 | { 623 | If (TBT_ROOT.LACR == Zero) 624 | { 625 | If (TBT_ROOT.LTRN != One) 626 | { 627 | Break 628 | } 629 | } 630 | ElseIf ((TBT_ROOT.LTRN != One) && (TBT_ROOT.LACT == One)) 631 | { 632 | Break 633 | } 634 | 635 | Sleep (10) 636 | } 637 | 638 | Sleep (250) 639 | } 640 | 641 | TBT_ROOT.PRSR = Zero 642 | While (Timer <= Local5) 643 | { 644 | If (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF) 645 | { 646 | Break 647 | } 648 | 649 | Sleep (10) 650 | } 651 | 652 | If (TBT_ROOT.CSPD != 0x03) 653 | { 654 | If (TBT_ROOT.SSPD == 0x03) 655 | { 656 | If (TBT_ROOT.UPSB.SSPD == 0x03) 657 | { 658 | If (TBT_ROOT.TSPD != 0x03) 659 | { 660 | TBT_ROOT.TSPD = 0x03 661 | } 662 | 663 | If (TBT_ROOT.UPSB.TSPD != 0x03) 664 | { 665 | TBT_ROOT.UPSB.TSPD = 0x03 666 | } 667 | 668 | TBT_ROOT.LRTN = One 669 | Local2 = (Timer + 10000000) 670 | While (Timer <= Local2) 671 | { 672 | If (TBT_ROOT.LACR == Zero) 673 | { 674 | If ((TBT_ROOT.LTRN != One) && (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF)) 675 | { 676 | TBT_ROOT.PCIA = One 677 | Local1 = One 678 | Break 679 | } 680 | } 681 | ElseIf (((TBT_ROOT.LTRN != One) && (TBT_ROOT.LACT == One)) && 682 | (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF)) 683 | { 684 | TBT_ROOT.PCIA = One 685 | Local1 = One 686 | Break 687 | } 688 | 689 | Sleep (10) 690 | } 691 | } 692 | Else 693 | { 694 | TBT_ROOT.PCIA = One 695 | } 696 | } 697 | Else 698 | { 699 | TBT_ROOT.PCIA = One 700 | } 701 | } 702 | Else 703 | { 704 | TBT_ROOT.PCIA = One 705 | } 706 | 707 | TBT_ROOT.IIP3 = Zero 708 | } 709 | 710 | /** 711 | * Hotplug notify 712 | * Called by ACPI 713 | */ 714 | Method (AMPE, 0, Serialized) 715 | { 716 | Notify (TBT_ROOT.UPSB.DSB0.NHI0, Zero) // Bus Check 717 | } 718 | 719 | /** 720 | * Hotplug notify 721 | * MUST called by NHI driver indicating cable plug-in 722 | * This passes the message to the XHC driver 723 | */ 724 | Method (UMPE, 0, Serialized) 725 | { 726 | Notify (TBT_ROOT.UPSB.DSB2.XHC2, Zero) // Bus Check 727 | #ifdef XHC_ROOT 728 | Notify (XHC_ROOT, Zero) // Bus Check 729 | #endif 730 | } 731 | 732 | Name (MDUV, One) // plug status 733 | 734 | /** 735 | * Cable status callback 736 | * Called from NHI driver on hotplug 737 | */ 738 | Method (MUST, 1, Serialized) 739 | { 740 | DBG2 ("MUST", Arg0) 741 | If (OSDW ()) 742 | { 743 | If (MDUV != Arg0) 744 | { 745 | MDUV = Arg0 746 | UMPE () 747 | } 748 | } 749 | 750 | Return (Zero) 751 | } 752 | 753 | Method (_PS0, 0, Serialized) // _PS0: Power State 0 754 | { 755 | If (OSDW ()) 756 | { 757 | PCED () // enable downlink 758 | // some magical commands to CIO 759 | #ifdef THUNDERBOLT_TITAN_RIDGE 760 | TBT_ROOT.UPSB.CRMW (0x0150, Zero, 0x02, 0x04000000, 0x04000000) 761 | TBT_ROOT.UPSB.CRMW (0x0250, Zero, 0x02, 0x04000000, 0x04000000) 762 | #else 763 | TBT_ROOT.UPSB.CRMW (0x013E, Zero, 0x02, 0x0200, 0x0200) 764 | TBT_ROOT.UPSB.CRMW (0x023E, Zero, 0x02, 0x0200, 0x0200) 765 | #endif 766 | } 767 | } 768 | 769 | Method (_PS3, 0, Serialized) // _PS3: Power State 3 770 | { 771 | #ifndef NO_WINDOWS_SUPPORT 772 | If (!OSDW ()) 773 | { 774 | If (TBT_ROOT.UPCK () == Zero) 775 | { 776 | TBT_ROOT.UTLK (One, 1000) 777 | } 778 | 779 | TBT_ROOT.TBTC (0x05) 780 | } 781 | #endif 782 | } 783 | 784 | OperationRegion (H548, PCI_Config, 0x0548, 0x20) 785 | Field (H548, DWordAcc, Lock, Preserve) 786 | { 787 | T2PC, 32, 788 | PC2T, 32 789 | } 790 | 791 | OperationRegion (H530, PCI_Config, 0x0530, 0x0C) 792 | Field (H530, DWordAcc, Lock, Preserve) 793 | { 794 | DWIX, 13, 795 | PORT, 6, 796 | SPCE, 2, 797 | CMD0, 1, 798 | CMD1, 1, 799 | CMD2, 1, 800 | , 6, 801 | PROG, 1, 802 | TMOT, 1, 803 | WDAT, 32, 804 | RDAT, 32 805 | } 806 | 807 | /** 808 | * CIO write 809 | */ 810 | Method (CIOW, 4, Serialized) 811 | { 812 | WDAT = Arg3 813 | DWIX = Arg0 814 | PORT = Arg1 815 | SPCE = Arg2 816 | CMD0 = One 817 | CMD1 = Zero 818 | CMD2 = Zero 819 | TMOT = Zero 820 | PROG = One 821 | Local1 = One 822 | Local0 = 0x2710 823 | While (Zero < Local0) 824 | { 825 | If (PROG == Zero) 826 | { 827 | Local1 = Zero 828 | Break 829 | } 830 | 831 | Stall (0x19) 832 | Local0-- 833 | } 834 | 835 | If (Local1 == Zero) 836 | { 837 | Local1 = TMOT /* \_SB_.PCI0.RP05.UPSB.TMOT */ 838 | } 839 | 840 | Return (Local1) 841 | } 842 | 843 | /** 844 | * CIO read 845 | */ 846 | Method (CIOR, 3, Serialized) 847 | { 848 | RDAT = Zero 849 | DWIX = Arg0 850 | PORT = Arg1 851 | SPCE = Arg2 852 | CMD0 = Zero 853 | CMD1 = Zero 854 | CMD2 = Zero 855 | TMOT = Zero 856 | PROG = One 857 | Local1 = One 858 | Local0 = 0x2710 859 | While (Zero < Local0) 860 | { 861 | If (PROG == Zero) 862 | { 863 | Local1 = Zero 864 | Break 865 | } 866 | 867 | Stall (0x19) 868 | Local0-- 869 | } 870 | 871 | If (Local1 == Zero) 872 | { 873 | Local1 = TMOT /* \_SB_.PCI0.RP05.UPSB.TMOT */ 874 | } 875 | 876 | If (Local1 == Zero) 877 | { 878 | Return (Package (0x02) 879 | { 880 | Zero, 881 | RDAT 882 | }) 883 | } 884 | Else 885 | { 886 | Return (Package (0x02) 887 | { 888 | One, 889 | RDAT 890 | }) 891 | } 892 | } 893 | 894 | /** 895 | * CIO Read Modify Write 896 | */ 897 | Method (CRMW, 5, Serialized) 898 | { 899 | Local1 = One 900 | //If (((GGDV (0x01070004) == One) || (GGDV (0x01070007) == One)) && 901 | If (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF) 902 | { 903 | Local3 = Zero 904 | While (Local3 <= 0x04) 905 | { 906 | Local2 = CIOR (Arg0, Arg1, Arg2) 907 | If (DerefOf (Local2 [Zero]) == Zero) 908 | { 909 | Local2 = DerefOf (Local2 [One]) 910 | Local2 &= ~Arg4 911 | Local2 |= Arg3 912 | Local2 = CIOW (Arg0, Arg1, Arg2, Local2) 913 | If (Local2 == Zero) 914 | { 915 | Local2 = CIOR (Arg0, Arg1, Arg2) 916 | If (DerefOf (Local2 [Zero]) == Zero) 917 | { 918 | Local2 = DerefOf (Local2 [One]) 919 | Local2 &= Arg4 920 | If (Local2 == Arg3) 921 | { 922 | Local1 = Zero 923 | Break 924 | } 925 | } 926 | } 927 | } 928 | 929 | Local3++ 930 | Sleep (100) 931 | } 932 | } 933 | 934 | DBG3 ("CRMW", Arg0, Local1) 935 | Return (Local1) 936 | } 937 | 938 | /** 939 | * Not used anywhere AFAIK 940 | */ 941 | Method (LSTX, 2, Serialized) 942 | { 943 | If (T2PC != 0xFFFFFFFF) 944 | { 945 | Local0 = Zero 946 | If ((T2PC & One) && One) 947 | { 948 | Local0 = One 949 | } 950 | 951 | If (Local0 == Zero) 952 | { 953 | Local1 = 0x2710 954 | While (Zero < Local1) 955 | { 956 | If (T2PC == Zero) 957 | { 958 | Break 959 | } 960 | 961 | Stall (0x19) 962 | Local1-- 963 | } 964 | 965 | If (Zero == Local1) 966 | { 967 | Local0 = One 968 | } 969 | } 970 | 971 | If (Local0 == Zero) 972 | { 973 | Local1 = One 974 | Local1 |= 0x14 975 | Local1 |= (Arg0 << 0x08) 976 | Local1 |= (Arg1 << 0x0C) 977 | Local1 |= 0x00400000 978 | PC2T = Local1 979 | } 980 | 981 | If (Local0 == Zero) 982 | { 983 | Local1 = 0x2710 984 | While (Zero < Local1) 985 | { 986 | If (T2PC == 0x15) 987 | { 988 | Break 989 | } 990 | 991 | Stall (0x19) 992 | Local1-- 993 | } 994 | 995 | If (Zero == Local1) 996 | { 997 | Local0 = One 998 | } 999 | } 1000 | 1001 | PC2T = Zero 1002 | } 1003 | } 1004 | 1005 | Device (DSB0) 1006 | { 1007 | Name (_ADR, Zero) // _ADR: Address 1008 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1009 | Field (A1E0, ByteAcc, NoLock, Preserve) 1010 | { 1011 | AVND, 32, 1012 | BMIE, 3, 1013 | Offset (0x18), 1014 | PRIB, 8, 1015 | SECB, 8, 1016 | SUBB, 8, 1017 | Offset (0x1E), 1018 | , 13, 1019 | MABT, 1 1020 | } 1021 | 1022 | OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) 1023 | Field (A1E1, ByteAcc, NoLock, Preserve) 1024 | { 1025 | Offset (0x01), 1026 | Offset (0x02), 1027 | Offset (0x04), 1028 | Offset (0x08), 1029 | Offset (0x0A), 1030 | , 5, 1031 | TPEN, 1, 1032 | Offset (0x0C), 1033 | SSPD, 4, 1034 | , 16, 1035 | LACR, 1, 1036 | Offset (0x10), 1037 | , 4, 1038 | LDIS, 1, 1039 | LRTN, 1, 1040 | Offset (0x12), 1041 | CSPD, 4, 1042 | CWDT, 6, 1043 | , 1, 1044 | LTRN, 1, 1045 | , 1, 1046 | LACT, 1, 1047 | Offset (0x14), 1048 | Offset (0x30), 1049 | TSPD, 4 1050 | } 1051 | 1052 | OperationRegion (A1E2, PCI_Config, 0x80, 0x08) 1053 | Field (A1E2, ByteAcc, NoLock, Preserve) 1054 | { 1055 | Offset (0x01), 1056 | Offset (0x02), 1057 | Offset (0x04), 1058 | PSTA, 2 1059 | } 1060 | 1061 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1062 | { 1063 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB0.SECB */ 1064 | } 1065 | 1066 | Method (_STA, 0, NotSerialized) // _STA: Status 1067 | { 1068 | Return (0x0F) 1069 | } 1070 | 1071 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1072 | { 1073 | Return (Zero) 1074 | } 1075 | 1076 | Name (IIP3, Zero) 1077 | Name (PRSR, Zero) 1078 | Name (PCIA, One) 1079 | Method (PCEU, 0, Serialized) 1080 | { 1081 | TBT_ROOT.UPSB.DSB0.PRSR = Zero 1082 | If (TBT_ROOT.UPSB.DSB0.PSTA != Zero) 1083 | { 1084 | TBT_ROOT.UPSB.DSB0.PRSR = One 1085 | TBT_ROOT.UPSB.DSB0.PSTA = Zero 1086 | } 1087 | 1088 | If (TBT_ROOT.UPSB.DSB0.LDIS == One) 1089 | { 1090 | TBT_ROOT.UPSB.DSB0.PRSR = One 1091 | TBT_ROOT.UPSB.DSB0.LDIS = Zero 1092 | } 1093 | } 1094 | 1095 | Method (PCDA, 0, Serialized) 1096 | { 1097 | If (TBT_ROOT.UPSB.DSB0.POFF () != Zero) 1098 | { 1099 | TBT_ROOT.UPSB.DSB0.PCIA = Zero 1100 | TBT_ROOT.UPSB.DSB0.PSTA = 0x03 1101 | TBT_ROOT.UPSB.DSB0.LDIS = One 1102 | Local5 = (Timer + 10000000) 1103 | While (Timer <= Local5) 1104 | { 1105 | If (TBT_ROOT.UPSB.DSB0.LACR == One) 1106 | { 1107 | If (TBT_ROOT.UPSB.DSB0.LACT == Zero) 1108 | { 1109 | Break 1110 | } 1111 | } 1112 | ElseIf (TBT_ROOT.UPSB.DSB0.NHI0.AVND == 0xFFFFFFFF) 1113 | { 1114 | Break 1115 | } 1116 | 1117 | Sleep (10) 1118 | } 1119 | 1120 | TBT_ROOT.GNHI = Zero 1121 | TBT_ROOT.UGIO () 1122 | } 1123 | Else 1124 | { 1125 | } 1126 | 1127 | TBT_ROOT.UPSB.DSB0.IIP3 = One 1128 | } 1129 | 1130 | Method (POFF, 0, Serialized) 1131 | { 1132 | Return (!TBT_ROOT.RTBT) 1133 | } 1134 | 1135 | Method (_PS0, 0, Serialized) // _PS0: Power State 0 1136 | { 1137 | If (OSDW ()) 1138 | { 1139 | PCEU () 1140 | } 1141 | } 1142 | 1143 | Method (_PS3, 0, Serialized) // _PS3: Power State 3 1144 | { 1145 | If (OSDW ()) 1146 | { 1147 | PCDA () 1148 | } 1149 | } 1150 | 1151 | Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method 1152 | { 1153 | If (OSDW ()) 1154 | { 1155 | If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) 1156 | { 1157 | Local0 = Package (0x02) 1158 | { 1159 | "PCIHotplugCapable", 1160 | Zero 1161 | } 1162 | DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) 1163 | Return (Local0) 1164 | } 1165 | } 1166 | 1167 | Return (Zero) 1168 | } 1169 | 1170 | Device (NHI0) 1171 | { 1172 | Name (_ADR, Zero) // _ADR: Address 1173 | Name (_STR, Unicode ("Thunderbolt")) // _STR: Description String 1174 | 1175 | /** 1176 | * Enable downstream link 1177 | */ 1178 | Method (PCED, 0, Serialized) 1179 | { 1180 | TBT_ROOT.GNHI = One 1181 | // we should not need to force power since 1182 | // UPSX init should already have done so! 1183 | If (TBT_ROOT.UGIO () != Zero) 1184 | { 1185 | TBT_ROOT.UPSB.DSB0.PRSR = One 1186 | } 1187 | 1188 | // Do some link training 1189 | 1190 | Local0 = Zero 1191 | Local1 = Zero 1192 | Local5 = (Timer + 10000000) 1193 | If (TBT_ROOT.UPSB.DSB0.PRSR != Zero) 1194 | { 1195 | Local5 = (Timer + 10000000) 1196 | While (Timer <= Local5) 1197 | { 1198 | If (TBT_ROOT.UPSB.DSB0.LACR == Zero) 1199 | { 1200 | If (TBT_ROOT.UPSB.DSB0.LTRN != One) 1201 | { 1202 | Break 1203 | } 1204 | } 1205 | ElseIf ((TBT_ROOT.UPSB.DSB0.LTRN != One) && (TBT_ROOT.UPSB.DSB0.LACT == One)) 1206 | { 1207 | Break 1208 | } 1209 | 1210 | Sleep (10) 1211 | } 1212 | 1213 | Sleep (150) 1214 | } 1215 | 1216 | TBT_ROOT.UPSB.DSB0.PRSR = Zero 1217 | While (Timer <= Local5) 1218 | { 1219 | If (TBT_ROOT.UPSB.DSB0.NHI0.AVND != 0xFFFFFFFF) 1220 | { 1221 | TBT_ROOT.UPSB.DSB0.PCIA = One 1222 | Break 1223 | } 1224 | 1225 | Sleep (10) 1226 | } 1227 | 1228 | TBT_ROOT.UPSB.DSB0.IIP3 = Zero 1229 | } 1230 | 1231 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1232 | { 1233 | Return (Zero) 1234 | } 1235 | 1236 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1237 | Field (A1E0, ByteAcc, NoLock, Preserve) 1238 | { 1239 | AVND, 32, 1240 | BMIE, 3, 1241 | Offset (0x10), 1242 | BAR1, 32, 1243 | Offset (0x18), 1244 | PRIB, 8, 1245 | SECB, 8, 1246 | SUBB, 8, 1247 | Offset (0x1E), 1248 | , 13, 1249 | MABT, 1 1250 | } 1251 | 1252 | /** 1253 | * Run Time Power Check 1254 | * Called by NHI driver when link is idle. 1255 | * Once both XHC and NHI idle, we can power down. 1256 | */ 1257 | Method (RTPC, 1, Serialized) 1258 | { 1259 | If (OSDW ()) 1260 | { 1261 | If (Arg0 <= One) 1262 | { 1263 | TBT_ROOT.RTBT = Arg0 1264 | } 1265 | } 1266 | 1267 | Return (Zero) 1268 | } 1269 | 1270 | /** 1271 | * Cable detection callback 1272 | * Called by NHI driver on hotplug 1273 | */ 1274 | Method (MUST, 1, Serialized) 1275 | { 1276 | Return (TBT_ROOT.UPSB.MUST (Arg0)) 1277 | } 1278 | 1279 | Method (_PS0, 0, Serialized) // _PS0: Power State 0 1280 | { 1281 | If (OSDW ()) 1282 | { 1283 | PCED () 1284 | TBT_ROOT.CTBT () 1285 | } 1286 | } 1287 | 1288 | Method (_PS3, 0, Serialized) // _PS3: Power State 3 1289 | { 1290 | } 1291 | 1292 | Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method 1293 | { 1294 | If (OSDW ()) 1295 | { 1296 | Local0 = Package (0x03) 1297 | { 1298 | "power-save", 1299 | One, 1300 | Buffer (One) 1301 | { 1302 | 0x00 /* . */ 1303 | } 1304 | } 1305 | DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) 1306 | Return (Local0) 1307 | } 1308 | 1309 | Return (Zero) 1310 | } 1311 | 1312 | /** 1313 | * Late sleep force power 1314 | * NHI driver sends a sleep cmd to TB controller 1315 | * But we might be sleeping at this time. So this will 1316 | * force the power on right before sleep. 1317 | */ 1318 | Method (SXFP, 1, Serialized) 1319 | { 1320 | DBG2 ("SXFP", Arg0) 1321 | If (Arg0 == Zero) 1322 | { 1323 | //If (GGDV (0x01070007) == One) 1324 | //{ 1325 | // SGOV (0x01070007, Zero) 1326 | // SGDO (0x01070007) 1327 | // Sleep (0x64) 1328 | //} 1329 | //SGOV (0x01070004, Zero) 1330 | //SGDO (0x01070004) 1331 | } 1332 | } 1333 | } 1334 | } 1335 | 1336 | Device (DSB1) 1337 | { 1338 | Name (_ADR, 0x00010000) // _ADR: Address 1339 | Name (_SUN, One) // _SUN: Slot User Number 1340 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1341 | Field (A1E0, ByteAcc, NoLock, Preserve) 1342 | { 1343 | AVND, 32, 1344 | BMIE, 3, 1345 | Offset (0x18), 1346 | PRIB, 8, 1347 | SECB, 8, 1348 | SUBB, 8, 1349 | Offset (0x1E), 1350 | , 13, 1351 | MABT, 1 1352 | } 1353 | 1354 | OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) 1355 | Field (A1E1, ByteAcc, NoLock, Preserve) 1356 | { 1357 | Offset (0x01), 1358 | Offset (0x02), 1359 | Offset (0x04), 1360 | Offset (0x08), 1361 | Offset (0x0A), 1362 | , 5, 1363 | TPEN, 1, 1364 | Offset (0x0C), 1365 | SSPD, 4, 1366 | , 16, 1367 | LACR, 1, 1368 | Offset (0x10), 1369 | , 4, 1370 | LDIS, 1, 1371 | LRTN, 1, 1372 | Offset (0x12), 1373 | CSPD, 4, 1374 | CWDT, 6, 1375 | , 1, 1376 | LTRN, 1, 1377 | , 1, 1378 | LACT, 1, 1379 | Offset (0x14), 1380 | Offset (0x30), 1381 | TSPD, 4 1382 | } 1383 | 1384 | OperationRegion (A1E2, PCI_Config, 0x80, 0x08) 1385 | Field (A1E2, ByteAcc, NoLock, Preserve) 1386 | { 1387 | Offset (0x01), 1388 | Offset (0x02), 1389 | Offset (0x04), 1390 | PSTA, 2 1391 | } 1392 | 1393 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1394 | { 1395 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.SECB */ 1396 | } 1397 | 1398 | Method (_STA, 0, NotSerialized) // _STA: Status 1399 | { 1400 | Return (0x0F) 1401 | } 1402 | 1403 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1404 | { 1405 | Return (Zero) 1406 | } 1407 | 1408 | Device (UPS0) 1409 | { 1410 | Name (_ADR, Zero) // _ADR: Address 1411 | OperationRegion (ARE0, PCI_Config, Zero, 0x04) 1412 | Field (ARE0, ByteAcc, NoLock, Preserve) 1413 | { 1414 | AVND, 16 1415 | } 1416 | 1417 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1418 | { 1419 | If (OSDW ()) 1420 | { 1421 | Return (One) 1422 | } 1423 | 1424 | Return (Zero) 1425 | } 1426 | 1427 | Device (DSB0) 1428 | { 1429 | Name (_ADR, Zero) // _ADR: Address 1430 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1431 | Field (A1E0, ByteAcc, NoLock, Preserve) 1432 | { 1433 | AVND, 32, 1434 | BMIE, 3, 1435 | Offset (0x18), 1436 | PRIB, 8, 1437 | SECB, 8, 1438 | SUBB, 8, 1439 | Offset (0x1E), 1440 | , 13, 1441 | MABT, 1, 1442 | Offset (0x3E), 1443 | , 6, 1444 | SBRS, 1 1445 | } 1446 | 1447 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1448 | { 1449 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB0.SECB */ 1450 | } 1451 | 1452 | Method (_STA, 0, NotSerialized) // _STA: Status 1453 | { 1454 | Return (0x0F) 1455 | } 1456 | 1457 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1458 | { 1459 | If (OSDW ()) 1460 | { 1461 | Return (One) 1462 | } 1463 | 1464 | Return (Zero) 1465 | } 1466 | 1467 | Device (DEV0) 1468 | { 1469 | Name (_ADR, Zero) // _ADR: Address 1470 | Method (_STA, 0, NotSerialized) // _STA: Status 1471 | { 1472 | Return (0x0F) 1473 | } 1474 | 1475 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1476 | { 1477 | If (OSDW ()) 1478 | { 1479 | Return (One) 1480 | } 1481 | 1482 | Return (Zero) 1483 | } 1484 | } 1485 | } 1486 | 1487 | Device (DSB3) 1488 | { 1489 | Name (_ADR, 0x00030000) // _ADR: Address 1490 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1491 | Field (A1E0, ByteAcc, NoLock, Preserve) 1492 | { 1493 | AVND, 32, 1494 | BMIE, 3, 1495 | Offset (0x18), 1496 | PRIB, 8, 1497 | SECB, 8, 1498 | SUBB, 8, 1499 | Offset (0x1E), 1500 | , 13, 1501 | MABT, 1 1502 | } 1503 | 1504 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1505 | { 1506 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB3.SECB */ 1507 | } 1508 | 1509 | Method (_STA, 0, NotSerialized) // _STA: Status 1510 | { 1511 | Return (0x0F) 1512 | } 1513 | 1514 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1515 | { 1516 | If (OSDW ()) 1517 | { 1518 | Return (One) 1519 | } 1520 | 1521 | Return (Zero) 1522 | } 1523 | 1524 | Device (UPS0) 1525 | { 1526 | Name (_ADR, Zero) // _ADR: Address 1527 | OperationRegion (ARE0, PCI_Config, Zero, 0x04) 1528 | Field (ARE0, ByteAcc, NoLock, Preserve) 1529 | { 1530 | AVND, 16 1531 | } 1532 | 1533 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1534 | { 1535 | If (OSDW ()) 1536 | { 1537 | Return (One) 1538 | } 1539 | 1540 | Return (Zero) 1541 | } 1542 | 1543 | Device (DSB0) 1544 | { 1545 | Name (_ADR, Zero) // _ADR: Address 1546 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1547 | Field (A1E0, ByteAcc, NoLock, Preserve) 1548 | { 1549 | AVND, 32, 1550 | BMIE, 3, 1551 | Offset (0x18), 1552 | PRIB, 8, 1553 | SECB, 8, 1554 | SUBB, 8, 1555 | Offset (0x1E), 1556 | , 13, 1557 | MABT, 1, 1558 | Offset (0x3E), 1559 | , 6, 1560 | SBRS, 1 1561 | } 1562 | 1563 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1564 | { 1565 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB3.UPS0.DSB0.SECB */ 1566 | } 1567 | 1568 | Method (_STA, 0, NotSerialized) // _STA: Status 1569 | { 1570 | Return (0x0F) 1571 | } 1572 | 1573 | Device (DEV0) 1574 | { 1575 | Name (_ADR, Zero) // _ADR: Address 1576 | Method (_STA, 0, NotSerialized) // _STA: Status 1577 | { 1578 | Return (0x0F) 1579 | } 1580 | } 1581 | } 1582 | 1583 | Device (DSB3) 1584 | { 1585 | Name (_ADR, 0x00030000) // _ADR: Address 1586 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1587 | Field (A1E0, ByteAcc, NoLock, Preserve) 1588 | { 1589 | AVND, 32, 1590 | BMIE, 3, 1591 | Offset (0x18), 1592 | PRIB, 8, 1593 | SECB, 8, 1594 | SUBB, 8, 1595 | Offset (0x1E), 1596 | , 13, 1597 | MABT, 1 1598 | } 1599 | 1600 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1601 | { 1602 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB3.UPS0.DSB3.SECB */ 1603 | } 1604 | 1605 | Method (_STA, 0, NotSerialized) // _STA: Status 1606 | { 1607 | Return (0x0F) 1608 | } 1609 | 1610 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1611 | { 1612 | If (OSDW ()) 1613 | { 1614 | Return (One) 1615 | } 1616 | 1617 | Return (Zero) 1618 | } 1619 | 1620 | Device (DEV0) 1621 | { 1622 | Name (_ADR, Zero) // _ADR: Address 1623 | Method (_STA, 0, NotSerialized) // _STA: Status 1624 | { 1625 | Return (0x0F) 1626 | } 1627 | 1628 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1629 | { 1630 | If (OSDW ()) 1631 | { 1632 | Return (One) 1633 | } 1634 | 1635 | Return (Zero) 1636 | } 1637 | } 1638 | } 1639 | 1640 | Device (DSB4) 1641 | { 1642 | Name (_ADR, 0x00040000) // _ADR: Address 1643 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1644 | Field (A1E0, ByteAcc, NoLock, Preserve) 1645 | { 1646 | AVND, 32, 1647 | BMIE, 3, 1648 | Offset (0x18), 1649 | PRIB, 8, 1650 | SECB, 8, 1651 | SUBB, 8, 1652 | Offset (0x1E), 1653 | , 13, 1654 | MABT, 1 1655 | } 1656 | 1657 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1658 | { 1659 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB3.UPS0.DSB4.SECB */ 1660 | } 1661 | 1662 | Method (_STA, 0, NotSerialized) // _STA: Status 1663 | { 1664 | Return (0x0F) 1665 | } 1666 | 1667 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1668 | { 1669 | If (OSDW ()) 1670 | { 1671 | Return (One) 1672 | } 1673 | 1674 | Return (Zero) 1675 | } 1676 | 1677 | Device (DEV0) 1678 | { 1679 | Name (_ADR, Zero) // _ADR: Address 1680 | Method (_STA, 0, NotSerialized) // _STA: Status 1681 | { 1682 | Return (0x0F) 1683 | } 1684 | 1685 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1686 | { 1687 | If (OSDW ()) 1688 | { 1689 | Return (One) 1690 | } 1691 | 1692 | Return (Zero) 1693 | } 1694 | } 1695 | } 1696 | 1697 | Device (DSB5) 1698 | { 1699 | Name (_ADR, 0x00050000) // _ADR: Address 1700 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1701 | Field (A1E0, ByteAcc, NoLock, Preserve) 1702 | { 1703 | AVND, 32, 1704 | BMIE, 3, 1705 | Offset (0x18), 1706 | PRIB, 8, 1707 | SECB, 8, 1708 | SUBB, 8, 1709 | Offset (0x1E), 1710 | , 13, 1711 | MABT, 1 1712 | } 1713 | 1714 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1715 | { 1716 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB3.UPS0.DSB5.SECB */ 1717 | } 1718 | 1719 | Method (_STA, 0, NotSerialized) // _STA: Status 1720 | { 1721 | Return (0x0F) 1722 | } 1723 | 1724 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1725 | { 1726 | If (OSDW ()) 1727 | { 1728 | Return (One) 1729 | } 1730 | 1731 | Return (Zero) 1732 | } 1733 | } 1734 | 1735 | Device (DSB6) 1736 | { 1737 | Name (_ADR, 0x00060000) // _ADR: Address 1738 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1739 | Field (A1E0, ByteAcc, NoLock, Preserve) 1740 | { 1741 | AVND, 32, 1742 | BMIE, 3, 1743 | Offset (0x18), 1744 | PRIB, 8, 1745 | SECB, 8, 1746 | SUBB, 8, 1747 | Offset (0x1E), 1748 | , 13, 1749 | MABT, 1 1750 | } 1751 | 1752 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1753 | { 1754 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB3.UPS0.DSB6.SECB */ 1755 | } 1756 | 1757 | Method (_STA, 0, NotSerialized) // _STA: Status 1758 | { 1759 | Return (0x0F) 1760 | } 1761 | 1762 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1763 | { 1764 | If (OSDW ()) 1765 | { 1766 | Return (One) 1767 | } 1768 | 1769 | Return (Zero) 1770 | } 1771 | } 1772 | } 1773 | } 1774 | 1775 | Device (DSB4) 1776 | { 1777 | Name (_ADR, 0x00040000) // _ADR: Address 1778 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1779 | Field (A1E0, ByteAcc, NoLock, Preserve) 1780 | { 1781 | AVND, 32, 1782 | BMIE, 3, 1783 | Offset (0x18), 1784 | PRIB, 8, 1785 | SECB, 8, 1786 | SUBB, 8, 1787 | Offset (0x1E), 1788 | , 13, 1789 | MABT, 1 1790 | } 1791 | 1792 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1793 | { 1794 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB4.SECB */ 1795 | } 1796 | 1797 | Method (_STA, 0, NotSerialized) // _STA: Status 1798 | { 1799 | Return (0x0F) 1800 | } 1801 | 1802 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1803 | { 1804 | If (OSDW ()) 1805 | { 1806 | Return (One) 1807 | } 1808 | 1809 | Return (Zero) 1810 | } 1811 | 1812 | Device (UPS0) 1813 | { 1814 | Name (_ADR, Zero) // _ADR: Address 1815 | OperationRegion (ARE0, PCI_Config, Zero, 0x04) 1816 | Field (ARE0, ByteAcc, NoLock, Preserve) 1817 | { 1818 | AVND, 16 1819 | } 1820 | 1821 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1822 | { 1823 | If (OSDW ()) 1824 | { 1825 | Return (One) 1826 | } 1827 | 1828 | Return (Zero) 1829 | } 1830 | 1831 | Device (DSB0) 1832 | { 1833 | Name (_ADR, Zero) // _ADR: Address 1834 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1835 | Field (A1E0, ByteAcc, NoLock, Preserve) 1836 | { 1837 | AVND, 32, 1838 | BMIE, 3, 1839 | Offset (0x18), 1840 | PRIB, 8, 1841 | SECB, 8, 1842 | SUBB, 8, 1843 | Offset (0x1E), 1844 | , 13, 1845 | MABT, 1, 1846 | Offset (0x3E), 1847 | , 6, 1848 | SBRS, 1 1849 | } 1850 | 1851 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1852 | { 1853 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB4.UPS0.DSB0.SECB */ 1854 | } 1855 | 1856 | Method (_STA, 0, NotSerialized) // _STA: Status 1857 | { 1858 | Return (0x0F) 1859 | } 1860 | 1861 | Device (DEV0) 1862 | { 1863 | Name (_ADR, Zero) // _ADR: Address 1864 | Method (_STA, 0, NotSerialized) // _STA: Status 1865 | { 1866 | Return (0x0F) 1867 | } 1868 | 1869 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1870 | { 1871 | If (OSDW ()) 1872 | { 1873 | Return (One) 1874 | } 1875 | 1876 | Return (Zero) 1877 | } 1878 | } 1879 | } 1880 | 1881 | Device (DSB3) 1882 | { 1883 | Name (_ADR, 0x00030000) // _ADR: Address 1884 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1885 | Field (A1E0, ByteAcc, NoLock, Preserve) 1886 | { 1887 | AVND, 32, 1888 | BMIE, 3, 1889 | Offset (0x18), 1890 | PRIB, 8, 1891 | SECB, 8, 1892 | SUBB, 8, 1893 | Offset (0x1E), 1894 | , 13, 1895 | MABT, 1 1896 | } 1897 | 1898 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1899 | { 1900 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB4.UPS0.DSB3.SECB */ 1901 | } 1902 | 1903 | Method (_STA, 0, NotSerialized) // _STA: Status 1904 | { 1905 | Return (0x0F) 1906 | } 1907 | 1908 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1909 | { 1910 | If (OSDW ()) 1911 | { 1912 | Return (One) 1913 | } 1914 | 1915 | Return (Zero) 1916 | } 1917 | 1918 | Device (DEV0) 1919 | { 1920 | Name (_ADR, Zero) // _ADR: Address 1921 | Method (_STA, 0, NotSerialized) // _STA: Status 1922 | { 1923 | Return (0x0F) 1924 | } 1925 | 1926 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1927 | { 1928 | If (OSDW ()) 1929 | { 1930 | Return (One) 1931 | } 1932 | 1933 | Return (Zero) 1934 | } 1935 | } 1936 | } 1937 | 1938 | Device (DSB4) 1939 | { 1940 | Name (_ADR, 0x00040000) // _ADR: Address 1941 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1942 | Field (A1E0, ByteAcc, NoLock, Preserve) 1943 | { 1944 | AVND, 32, 1945 | BMIE, 3, 1946 | Offset (0x18), 1947 | PRIB, 8, 1948 | SECB, 8, 1949 | SUBB, 8, 1950 | Offset (0x1E), 1951 | , 13, 1952 | MABT, 1 1953 | } 1954 | 1955 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 1956 | { 1957 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB4.UPS0.DSB4.SECB */ 1958 | } 1959 | 1960 | Method (_STA, 0, NotSerialized) // _STA: Status 1961 | { 1962 | Return (0x0F) 1963 | } 1964 | 1965 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1966 | { 1967 | If (OSDW ()) 1968 | { 1969 | Return (One) 1970 | } 1971 | 1972 | Return (Zero) 1973 | } 1974 | 1975 | Device (DEV0) 1976 | { 1977 | Name (_ADR, Zero) // _ADR: Address 1978 | Method (_STA, 0, NotSerialized) // _STA: Status 1979 | { 1980 | Return (0x0F) 1981 | } 1982 | 1983 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 1984 | { 1985 | If (OSDW ()) 1986 | { 1987 | Return (One) 1988 | } 1989 | 1990 | Return (Zero) 1991 | } 1992 | } 1993 | } 1994 | 1995 | Device (DSB5) 1996 | { 1997 | Name (_ADR, 0x00050000) // _ADR: Address 1998 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 1999 | Field (A1E0, ByteAcc, NoLock, Preserve) 2000 | { 2001 | AVND, 32, 2002 | BMIE, 3, 2003 | Offset (0x18), 2004 | PRIB, 8, 2005 | SECB, 8, 2006 | SUBB, 8, 2007 | Offset (0x1E), 2008 | , 13, 2009 | MABT, 1 2010 | } 2011 | 2012 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 2013 | { 2014 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB4.UPS0.DSB5.SECB */ 2015 | } 2016 | 2017 | Method (_STA, 0, NotSerialized) // _STA: Status 2018 | { 2019 | Return (0x0F) 2020 | } 2021 | 2022 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2023 | { 2024 | If (OSDW ()) 2025 | { 2026 | Return (One) 2027 | } 2028 | 2029 | Return (Zero) 2030 | } 2031 | } 2032 | 2033 | Device (DSB6) 2034 | { 2035 | Name (_ADR, 0x00060000) // _ADR: Address 2036 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 2037 | Field (A1E0, ByteAcc, NoLock, Preserve) 2038 | { 2039 | AVND, 32, 2040 | BMIE, 3, 2041 | Offset (0x18), 2042 | PRIB, 8, 2043 | SECB, 8, 2044 | SUBB, 8, 2045 | Offset (0x1E), 2046 | , 13, 2047 | MABT, 1 2048 | } 2049 | 2050 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 2051 | { 2052 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB4.UPS0.DSB6.SECB */ 2053 | } 2054 | 2055 | Method (_STA, 0, NotSerialized) // _STA: Status 2056 | { 2057 | Return (0x0F) 2058 | } 2059 | 2060 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2061 | { 2062 | If (OSDW ()) 2063 | { 2064 | Return (One) 2065 | } 2066 | 2067 | Return (Zero) 2068 | } 2069 | } 2070 | } 2071 | } 2072 | 2073 | Device (DSB5) 2074 | { 2075 | Name (_ADR, 0x00050000) // _ADR: Address 2076 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 2077 | Field (A1E0, ByteAcc, NoLock, Preserve) 2078 | { 2079 | AVND, 32, 2080 | BMIE, 3, 2081 | Offset (0x18), 2082 | PRIB, 8, 2083 | SECB, 8, 2084 | SUBB, 8, 2085 | Offset (0x1E), 2086 | , 13, 2087 | MABT, 1 2088 | } 2089 | 2090 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 2091 | { 2092 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB5.SECB */ 2093 | } 2094 | 2095 | Method (_STA, 0, NotSerialized) // _STA: Status 2096 | { 2097 | Return (0x0F) 2098 | } 2099 | 2100 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2101 | { 2102 | If (OSDW ()) 2103 | { 2104 | Return (One) 2105 | } 2106 | 2107 | Return (Zero) 2108 | } 2109 | } 2110 | 2111 | Device (DSB6) 2112 | { 2113 | Name (_ADR, 0x00060000) // _ADR: Address 2114 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 2115 | Field (A1E0, ByteAcc, NoLock, Preserve) 2116 | { 2117 | AVND, 32, 2118 | BMIE, 3, 2119 | Offset (0x18), 2120 | PRIB, 8, 2121 | SECB, 8, 2122 | SUBB, 8, 2123 | Offset (0x1E), 2124 | , 13, 2125 | MABT, 1 2126 | } 2127 | 2128 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 2129 | { 2130 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB6.SECB */ 2131 | } 2132 | 2133 | Method (_STA, 0, NotSerialized) // _STA: Status 2134 | { 2135 | Return (0x0F) 2136 | } 2137 | 2138 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2139 | { 2140 | If (OSDW ()) 2141 | { 2142 | Return (One) 2143 | } 2144 | 2145 | Return (Zero) 2146 | } 2147 | } 2148 | } 2149 | } 2150 | 2151 | Device (DSB2) 2152 | { 2153 | Name (_ADR, 0x00020000) // _ADR: Address 2154 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 2155 | Field (A1E0, ByteAcc, NoLock, Preserve) 2156 | { 2157 | AVND, 32, 2158 | BMIE, 3, 2159 | Offset (0x18), 2160 | PRIB, 8, 2161 | SECB, 8, 2162 | SUBB, 8, 2163 | Offset (0x1E), 2164 | , 13, 2165 | MABT, 1 2166 | } 2167 | 2168 | OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) 2169 | Field (A1E1, ByteAcc, NoLock, Preserve) 2170 | { 2171 | Offset (0x01), 2172 | Offset (0x02), 2173 | Offset (0x04), 2174 | Offset (0x08), 2175 | Offset (0x0A), 2176 | , 5, 2177 | TPEN, 1, 2178 | Offset (0x0C), 2179 | SSPD, 4, 2180 | , 16, 2181 | LACR, 1, 2182 | Offset (0x10), 2183 | , 4, 2184 | LDIS, 1, 2185 | LRTN, 1, 2186 | Offset (0x12), 2187 | CSPD, 4, 2188 | CWDT, 6, 2189 | , 1, 2190 | LTRN, 1, 2191 | , 1, 2192 | LACT, 1, 2193 | Offset (0x14), 2194 | Offset (0x30), 2195 | TSPD, 4 2196 | } 2197 | 2198 | OperationRegion (A1E2, PCI_Config, 0x80, 0x08) 2199 | Field (A1E2, ByteAcc, NoLock, Preserve) 2200 | { 2201 | Offset (0x01), 2202 | Offset (0x02), 2203 | Offset (0x04), 2204 | PSTA, 2 2205 | } 2206 | 2207 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 2208 | { 2209 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB2.SECB */ 2210 | } 2211 | 2212 | Method (_STA, 0, NotSerialized) // _STA: Status 2213 | { 2214 | Return (0x0F) 2215 | } 2216 | 2217 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2218 | { 2219 | Return (Zero) 2220 | } 2221 | 2222 | Name (IIP3, Zero) 2223 | Name (PRSR, Zero) 2224 | Name (PCIA, One) 2225 | 2226 | /** 2227 | * Enable upstream link 2228 | */ 2229 | Method (PCEU, 0, Serialized) 2230 | { 2231 | TBT_ROOT.UPSB.DSB2.PRSR = Zero 2232 | If (TBT_ROOT.UPSB.DSB2.PSTA != Zero) 2233 | { 2234 | TBT_ROOT.UPSB.DSB2.PRSR = One 2235 | TBT_ROOT.UPSB.DSB2.PSTA = Zero 2236 | } 2237 | 2238 | If (TBT_ROOT.UPSB.DSB2.LDIS == One) 2239 | { 2240 | TBT_ROOT.UPSB.DSB2.PRSR = One 2241 | TBT_ROOT.UPSB.DSB2.LDIS = Zero 2242 | } 2243 | } 2244 | 2245 | /** 2246 | * PCI disable link 2247 | */ 2248 | Method (PCDA, 0, Serialized) 2249 | { 2250 | If (TBT_ROOT.UPSB.DSB2.POFF () != Zero) 2251 | { 2252 | TBT_ROOT.UPSB.DSB2.PCIA = Zero 2253 | TBT_ROOT.UPSB.DSB2.PSTA = 0x03 2254 | TBT_ROOT.UPSB.DSB2.LDIS = One 2255 | Local5 = (Timer + 10000000) 2256 | While (Timer <= Local5) 2257 | { 2258 | If (TBT_ROOT.UPSB.DSB2.LACR == One) 2259 | { 2260 | If (TBT_ROOT.UPSB.DSB2.LACT == Zero) 2261 | { 2262 | Break 2263 | } 2264 | } 2265 | ElseIf (TBT_ROOT.UPSB.DSB2.XHC2.AVND == 0xFFFFFFFF) 2266 | { 2267 | Break 2268 | } 2269 | 2270 | Sleep (10) 2271 | } 2272 | 2273 | TBT_ROOT.GXCI = Zero 2274 | TBT_ROOT.UGIO () // power down if needed 2275 | } 2276 | Else 2277 | { 2278 | } 2279 | 2280 | TBT_ROOT.UPSB.DSB2.IIP3 = One 2281 | } 2282 | 2283 | /** 2284 | * Is power saving requested? 2285 | */ 2286 | Method (POFF, 0, Serialized) 2287 | { 2288 | Return (!TBT_ROOT.RUSB) 2289 | } 2290 | 2291 | Method (_PS0, 0, Serialized) // _PS0: Power State 0 2292 | { 2293 | If (OSDW ()) 2294 | { 2295 | PCEU () 2296 | } 2297 | } 2298 | 2299 | Method (_PS3, 0, Serialized) // _PS3: Power State 3 2300 | { 2301 | If (OSDW ()) 2302 | { 2303 | PCDA () 2304 | } 2305 | } 2306 | 2307 | Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method 2308 | { 2309 | If (OSDW ()) 2310 | { 2311 | If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) 2312 | { 2313 | Local0 = Package (0x02) 2314 | { 2315 | "PCIHotplugCapable", 2316 | Zero 2317 | } 2318 | DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) 2319 | Return (Local0) 2320 | } 2321 | } 2322 | 2323 | Return (Zero) 2324 | } 2325 | 2326 | Device (XHC2) 2327 | { 2328 | Name (_ADR, Zero) // _ADR: Address 2329 | Name (SDPC, Zero) 2330 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 2331 | Field (A1E0, ByteAcc, NoLock, Preserve) 2332 | { 2333 | AVND, 32, 2334 | BMIE, 3, 2335 | Offset (0x18), 2336 | PRIB, 8, 2337 | SECB, 8, 2338 | SUBB, 8, 2339 | Offset (0x1E), 2340 | , 13, 2341 | MABT, 1 2342 | } 2343 | 2344 | /** 2345 | * PCI Enable downstream 2346 | */ 2347 | Method (PCED, 0, Serialized) 2348 | { 2349 | TBT_ROOT.GXCI = One 2350 | // this powers up both TBT and USB when needed 2351 | If (TBT_ROOT.UGIO () != Zero) 2352 | { 2353 | TBT_ROOT.UPSB.DSB2.PRSR = One 2354 | } 2355 | 2356 | // Do some link training 2357 | Local0 = Zero 2358 | Local1 = Zero 2359 | Local5 = (Timer + 10000000) 2360 | If (TBT_ROOT.UPSB.DSB2.PRSR != Zero) 2361 | { 2362 | Local5 = (Timer + 10000000) 2363 | While (Timer <= Local5) 2364 | { 2365 | If (TBT_ROOT.UPSB.DSB2.LACR == Zero) 2366 | { 2367 | If (TBT_ROOT.UPSB.DSB2.LTRN != One) 2368 | { 2369 | Break 2370 | } 2371 | } 2372 | ElseIf ((TBT_ROOT.UPSB.DSB2.LTRN != One) && (TBT_ROOT.UPSB.DSB2.LACT == One)) 2373 | { 2374 | Break 2375 | } 2376 | 2377 | Sleep (10) 2378 | } 2379 | 2380 | Sleep (150) 2381 | } 2382 | 2383 | TBT_ROOT.UPSB.DSB2.PRSR = Zero 2384 | While (Timer <= Local5) 2385 | { 2386 | If (TBT_ROOT.UPSB.DSB2.XHC2.AVND != 0xFFFFFFFF) 2387 | { 2388 | TBT_ROOT.UPSB.DSB2.PCIA = One 2389 | Break 2390 | } 2391 | 2392 | Sleep (10) 2393 | } 2394 | 2395 | TBT_ROOT.UPSB.DSB2.IIP3 = Zero 2396 | } 2397 | 2398 | Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method 2399 | { 2400 | If (U2OP == One) 2401 | { 2402 | Local0 = Package (0x06) 2403 | { 2404 | "USBBusNumber", 2405 | Zero, 2406 | "AAPL,xhci-clock-id", 2407 | One, 2408 | "UsbCompanionControllerPresent", 2409 | One 2410 | } 2411 | } 2412 | Else 2413 | { 2414 | Local0 = Package (0x04) 2415 | { 2416 | "USBBusNumber", 2417 | Zero, 2418 | "AAPL,xhci-clock-id", 2419 | One 2420 | } 2421 | } 2422 | 2423 | DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) 2424 | Return (Local0) 2425 | } 2426 | Name (HS, Package (0x01) 2427 | { 2428 | "XHC" 2429 | }) 2430 | Name (FS, Package (0x01) 2431 | { 2432 | "XHC" 2433 | }) 2434 | Name (LS, Package (0x01) 2435 | { 2436 | "XHC" 2437 | }) 2438 | Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake 2439 | { 2440 | If (OSDW ()) 2441 | { 2442 | Return (Package (0x02) 2443 | { 2444 | 0x6D, 2445 | 0x04 2446 | }) 2447 | } 2448 | Else 2449 | { 2450 | Return (Package (0x02) 2451 | { 2452 | 0x6D, 2453 | 0x03 2454 | }) 2455 | } 2456 | } 2457 | 2458 | Method (_PS0, 0, Serialized) // _PS0: Power State 0 2459 | { 2460 | If (OSDW ()) 2461 | { 2462 | PCED () 2463 | } 2464 | } 2465 | 2466 | Method (_PS3, 0, Serialized) // _PS3: Power State 3 2467 | { 2468 | } 2469 | 2470 | /** 2471 | * Run Time Power Check 2472 | * Called by XHC driver when idle 2473 | */ 2474 | Method (RTPC, 1, Serialized) 2475 | { 2476 | If (OSDW ()) 2477 | { 2478 | If (Arg0 <= One) 2479 | { 2480 | TBT_ROOT.RUSB = Arg0 2481 | } 2482 | } 2483 | 2484 | Return (Zero) 2485 | } 2486 | 2487 | /** 2488 | * USB cable check 2489 | * Called by XHC driver to check cable status 2490 | * Used as idle hint. 2491 | */ 2492 | Method (MODU, 0, Serialized) 2493 | { 2494 | Return (TBT_ROOT.UPSB.MDUV) 2495 | } 2496 | 2497 | Device (RHUB) 2498 | { 2499 | Name (_ADR, Zero) // _ADR: Address 2500 | Device (SSP1) 2501 | { 2502 | Name (_ADR, 0x03) // _ADR: Address 2503 | Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities 2504 | { 2505 | 0xFF, 2506 | 0x09, 2507 | Zero, 2508 | Zero 2509 | }) 2510 | Name (_PLD, Package (0x01) // _PLD: Physical Location of Device 2511 | { 2512 | ToPLD ( 2513 | PLD_Revision = 0x1, 2514 | PLD_IgnoreColor = 0x1, 2515 | PLD_Red = 0x0, 2516 | PLD_Green = 0x0, 2517 | PLD_Blue = 0x0, 2518 | PLD_Width = 0x0, 2519 | PLD_Height = 0x0, 2520 | PLD_UserVisible = 0x1, 2521 | PLD_Dock = 0x0, 2522 | PLD_Lid = 0x0, 2523 | PLD_Panel = "UNKNOWN", 2524 | PLD_VerticalPosition = "UPPER", 2525 | PLD_HorizontalPosition = "LEFT", 2526 | PLD_Shape = "UNKNOWN", 2527 | PLD_GroupOrientation = 0x0, 2528 | PLD_GroupToken = 0x0, 2529 | PLD_GroupPosition = 0x0, 2530 | PLD_Bay = 0x0, 2531 | PLD_Ejectable = 0x0, 2532 | PLD_EjectRequired = 0x0, 2533 | PLD_CabinetNumber = 0x0, 2534 | PLD_CardCageNumber = 0x0, 2535 | PLD_Reference = 0x0, 2536 | PLD_Rotation = 0x0, 2537 | PLD_Order = 0x0) 2538 | 2539 | }) 2540 | Name (HS, Package (0x02) 2541 | { 2542 | "XHC", 2543 | TBT_USB_PORT_1_COMPANION 2544 | }) 2545 | Name (FS, Package (0x02) 2546 | { 2547 | "XHC", 2548 | TBT_USB_PORT_1_COMPANION 2549 | }) 2550 | Name (LS, Package (0x02) 2551 | { 2552 | "XHC", 2553 | TBT_USB_PORT_1_COMPANION 2554 | }) 2555 | Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method 2556 | { 2557 | If (U2OP == One) 2558 | { 2559 | Local0 = Package (0x0A) 2560 | { 2561 | "UsbCPortNumber", 2562 | 0x03, 2563 | "UsbPowerSource", 2564 | 0x03, 2565 | "kUSBWakePortCurrentLimit", 2566 | 0x0BB8, 2567 | "kUSBSleepPortCurrentLimit", 2568 | 0x0BB8, 2569 | "UsbCompanionPortPresent", 2570 | One 2571 | } 2572 | } 2573 | Else 2574 | { 2575 | Local0 = Package (0x08) 2576 | { 2577 | "UsbCPortNumber", 2578 | 0x03, 2579 | "UsbPowerSource", 2580 | 0x03, 2581 | "kUSBWakePortCurrentLimit", 2582 | 0x0BB8, 2583 | "kUSBSleepPortCurrentLimit", 2584 | 0x0BB8 2585 | } 2586 | } 2587 | 2588 | DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) 2589 | Return (Local0) 2590 | } 2591 | } 2592 | 2593 | Device (SSP2) 2594 | { 2595 | Name (_ADR, 0x04) // _ADR: Address 2596 | Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities 2597 | { 2598 | 0xFF, 2599 | 0x09, 2600 | Zero, 2601 | Zero 2602 | }) 2603 | Name (_PLD, Package (0x01) // _PLD: Physical Location of Device 2604 | { 2605 | ToPLD ( 2606 | PLD_Revision = 0x1, 2607 | PLD_IgnoreColor = 0x1, 2608 | PLD_Red = 0x0, 2609 | PLD_Green = 0x0, 2610 | PLD_Blue = 0x0, 2611 | PLD_Width = 0x0, 2612 | PLD_Height = 0x0, 2613 | PLD_UserVisible = 0x1, 2614 | PLD_Dock = 0x0, 2615 | PLD_Lid = 0x0, 2616 | PLD_Panel = "UNKNOWN", 2617 | PLD_VerticalPosition = "UPPER", 2618 | PLD_HorizontalPosition = "LEFT", 2619 | PLD_Shape = "UNKNOWN", 2620 | PLD_GroupOrientation = 0x0, 2621 | PLD_GroupToken = 0x0, 2622 | PLD_GroupPosition = 0x0, 2623 | PLD_Bay = 0x0, 2624 | PLD_Ejectable = 0x0, 2625 | PLD_EjectRequired = 0x0, 2626 | PLD_CabinetNumber = 0x0, 2627 | PLD_CardCageNumber = 0x0, 2628 | PLD_Reference = 0x0, 2629 | PLD_Rotation = 0x0, 2630 | PLD_Order = 0x0) 2631 | 2632 | }) 2633 | Name (HS, Package (0x02) 2634 | { 2635 | "XHC", 2636 | TBT_USB_PORT_2_COMPANION 2637 | }) 2638 | Name (FS, Package (0x02) 2639 | { 2640 | "XHC", 2641 | TBT_USB_PORT_2_COMPANION 2642 | }) 2643 | Name (LS, Package (0x02) 2644 | { 2645 | "XHC", 2646 | TBT_USB_PORT_2_COMPANION 2647 | }) 2648 | Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method 2649 | { 2650 | If (U2OP == One) 2651 | { 2652 | Local0 = Package (0x0A) 2653 | { 2654 | "UsbCPortNumber", 2655 | 0x04, 2656 | "UsbPowerSource", 2657 | 0x04, 2658 | "kUSBWakePortCurrentLimit", 2659 | 0x0BB8, 2660 | "kUSBSleepPortCurrentLimit", 2661 | 0x0BB8, 2662 | "UsbCompanionPortPresent", 2663 | One 2664 | } 2665 | } 2666 | Else 2667 | { 2668 | Local0 = Package (0x0A) 2669 | { 2670 | "UsbCPortNumber", 2671 | 0x04, 2672 | "UsbPowerSource", 2673 | 0x04, 2674 | "kUSBWakePortCurrentLimit", 2675 | 0x0BB8, 2676 | "kUSBSleepPortCurrentLimit", 2677 | 0x0BB8, 2678 | "UsbCompanionPortPresent", 2679 | Zero 2680 | } 2681 | } 2682 | 2683 | DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) 2684 | Return (Local0) 2685 | } 2686 | } 2687 | } 2688 | } 2689 | } 2690 | 2691 | Device (DSB4) 2692 | { 2693 | Name (_ADR, 0x00040000) // _ADR: Address 2694 | Name (_SUN, 0x02) // _SUN: Slot User Number 2695 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 2696 | Field (A1E0, ByteAcc, NoLock, Preserve) 2697 | { 2698 | AVND, 32, 2699 | BMIE, 3, 2700 | Offset (0x18), 2701 | PRIB, 8, 2702 | SECB, 8, 2703 | SUBB, 8, 2704 | Offset (0x1E), 2705 | , 13, 2706 | MABT, 1 2707 | } 2708 | 2709 | OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) 2710 | Field (A1E1, ByteAcc, NoLock, Preserve) 2711 | { 2712 | Offset (0x01), 2713 | Offset (0x02), 2714 | Offset (0x04), 2715 | Offset (0x08), 2716 | Offset (0x0A), 2717 | , 5, 2718 | TPEN, 1, 2719 | Offset (0x0C), 2720 | SSPD, 4, 2721 | , 16, 2722 | LACR, 1, 2723 | Offset (0x10), 2724 | , 4, 2725 | LDIS, 1, 2726 | LRTN, 1, 2727 | Offset (0x12), 2728 | CSPD, 4, 2729 | CWDT, 6, 2730 | , 1, 2731 | LTRN, 1, 2732 | , 1, 2733 | LACT, 1, 2734 | Offset (0x14), 2735 | Offset (0x30), 2736 | TSPD, 4 2737 | } 2738 | 2739 | OperationRegion (A1E2, PCI_Config, 0x80, 0x08) 2740 | Field (A1E2, ByteAcc, NoLock, Preserve) 2741 | { 2742 | Offset (0x01), 2743 | Offset (0x02), 2744 | Offset (0x04), 2745 | PSTA, 2 2746 | } 2747 | 2748 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 2749 | { 2750 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.SECB */ 2751 | } 2752 | 2753 | Method (_STA, 0, NotSerialized) // _STA: Status 2754 | { 2755 | Return (0x0F) 2756 | } 2757 | 2758 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2759 | { 2760 | Return (Zero) 2761 | } 2762 | 2763 | Device (UPS0) 2764 | { 2765 | Name (_ADR, Zero) // _ADR: Address 2766 | OperationRegion (ARE0, PCI_Config, Zero, 0x04) 2767 | Field (ARE0, ByteAcc, NoLock, Preserve) 2768 | { 2769 | AVND, 16 2770 | } 2771 | 2772 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2773 | { 2774 | If (OSDW ()) 2775 | { 2776 | Return (One) 2777 | } 2778 | 2779 | Return (Zero) 2780 | } 2781 | 2782 | Device (DSB0) 2783 | { 2784 | Name (_ADR, Zero) // _ADR: Address 2785 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 2786 | Field (A1E0, ByteAcc, NoLock, Preserve) 2787 | { 2788 | AVND, 32, 2789 | BMIE, 3, 2790 | Offset (0x18), 2791 | PRIB, 8, 2792 | SECB, 8, 2793 | SUBB, 8, 2794 | Offset (0x1E), 2795 | , 13, 2796 | MABT, 1, 2797 | Offset (0x3E), 2798 | , 6, 2799 | SBRS, 1 2800 | } 2801 | 2802 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 2803 | { 2804 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB0.SECB */ 2805 | } 2806 | 2807 | Method (_STA, 0, NotSerialized) // _STA: Status 2808 | { 2809 | Return (0x0F) 2810 | } 2811 | 2812 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2813 | { 2814 | If (OSDW ()) 2815 | { 2816 | Return (One) 2817 | } 2818 | 2819 | Return (Zero) 2820 | } 2821 | 2822 | Device (DEV0) 2823 | { 2824 | Name (_ADR, Zero) // _ADR: Address 2825 | Method (_STA, 0, NotSerialized) // _STA: Status 2826 | { 2827 | Return (0x0F) 2828 | } 2829 | 2830 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2831 | { 2832 | If (OSDW ()) 2833 | { 2834 | Return (One) 2835 | } 2836 | 2837 | Return (Zero) 2838 | } 2839 | } 2840 | } 2841 | 2842 | Device (DSB3) 2843 | { 2844 | Name (_ADR, 0x00030000) // _ADR: Address 2845 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 2846 | Field (A1E0, ByteAcc, NoLock, Preserve) 2847 | { 2848 | AVND, 32, 2849 | BMIE, 3, 2850 | Offset (0x18), 2851 | PRIB, 8, 2852 | SECB, 8, 2853 | SUBB, 8, 2854 | Offset (0x1E), 2855 | , 13, 2856 | MABT, 1 2857 | } 2858 | 2859 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 2860 | { 2861 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB3.SECB */ 2862 | } 2863 | 2864 | Method (_STA, 0, NotSerialized) // _STA: Status 2865 | { 2866 | Return (0x0F) 2867 | } 2868 | 2869 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2870 | { 2871 | If (OSDW ()) 2872 | { 2873 | Return (One) 2874 | } 2875 | 2876 | Return (Zero) 2877 | } 2878 | 2879 | Device (UPS0) 2880 | { 2881 | Name (_ADR, Zero) // _ADR: Address 2882 | OperationRegion (ARE0, PCI_Config, Zero, 0x04) 2883 | Field (ARE0, ByteAcc, NoLock, Preserve) 2884 | { 2885 | AVND, 16 2886 | } 2887 | 2888 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2889 | { 2890 | If (OSDW ()) 2891 | { 2892 | Return (One) 2893 | } 2894 | 2895 | Return (Zero) 2896 | } 2897 | 2898 | Device (DSB0) 2899 | { 2900 | Name (_ADR, Zero) // _ADR: Address 2901 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 2902 | Field (A1E0, ByteAcc, NoLock, Preserve) 2903 | { 2904 | AVND, 32, 2905 | BMIE, 3, 2906 | Offset (0x18), 2907 | PRIB, 8, 2908 | SECB, 8, 2909 | SUBB, 8, 2910 | Offset (0x1E), 2911 | , 13, 2912 | MABT, 1, 2913 | Offset (0x3E), 2914 | , 6, 2915 | SBRS, 1 2916 | } 2917 | 2918 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 2919 | { 2920 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB3.UPS0.DSB0.SECB */ 2921 | } 2922 | 2923 | Method (_STA, 0, NotSerialized) // _STA: Status 2924 | { 2925 | Return (0x0F) 2926 | } 2927 | 2928 | Device (DEV0) 2929 | { 2930 | Name (_ADR, Zero) // _ADR: Address 2931 | Method (_STA, 0, NotSerialized) // _STA: Status 2932 | { 2933 | Return (0x0F) 2934 | } 2935 | } 2936 | } 2937 | 2938 | Device (DSB3) 2939 | { 2940 | Name (_ADR, 0x00030000) // _ADR: Address 2941 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 2942 | Field (A1E0, ByteAcc, NoLock, Preserve) 2943 | { 2944 | AVND, 32, 2945 | BMIE, 3, 2946 | Offset (0x18), 2947 | PRIB, 8, 2948 | SECB, 8, 2949 | SUBB, 8, 2950 | Offset (0x1E), 2951 | , 13, 2952 | MABT, 1 2953 | } 2954 | 2955 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 2956 | { 2957 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB3.UPS0.DSB3.SECB */ 2958 | } 2959 | 2960 | Method (_STA, 0, NotSerialized) // _STA: Status 2961 | { 2962 | Return (0x0F) 2963 | } 2964 | 2965 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2966 | { 2967 | If (OSDW ()) 2968 | { 2969 | Return (One) 2970 | } 2971 | 2972 | Return (Zero) 2973 | } 2974 | 2975 | Device (DEV0) 2976 | { 2977 | Name (_ADR, Zero) // _ADR: Address 2978 | Method (_STA, 0, NotSerialized) // _STA: Status 2979 | { 2980 | Return (0x0F) 2981 | } 2982 | 2983 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 2984 | { 2985 | If (OSDW ()) 2986 | { 2987 | Return (One) 2988 | } 2989 | 2990 | Return (Zero) 2991 | } 2992 | } 2993 | } 2994 | 2995 | Device (DSB4) 2996 | { 2997 | Name (_ADR, 0x00040000) // _ADR: Address 2998 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 2999 | Field (A1E0, ByteAcc, NoLock, Preserve) 3000 | { 3001 | AVND, 32, 3002 | BMIE, 3, 3003 | Offset (0x18), 3004 | PRIB, 8, 3005 | SECB, 8, 3006 | SUBB, 8, 3007 | Offset (0x1E), 3008 | , 13, 3009 | MABT, 1 3010 | } 3011 | 3012 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 3013 | { 3014 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB3.UPS0.DSB4.SECB */ 3015 | } 3016 | 3017 | Method (_STA, 0, NotSerialized) // _STA: Status 3018 | { 3019 | Return (0x0F) 3020 | } 3021 | 3022 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3023 | { 3024 | If (OSDW ()) 3025 | { 3026 | Return (One) 3027 | } 3028 | 3029 | Return (Zero) 3030 | } 3031 | 3032 | Device (DEV0) 3033 | { 3034 | Name (_ADR, Zero) // _ADR: Address 3035 | Method (_STA, 0, NotSerialized) // _STA: Status 3036 | { 3037 | Return (0x0F) 3038 | } 3039 | 3040 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3041 | { 3042 | If (OSDW ()) 3043 | { 3044 | Return (One) 3045 | } 3046 | 3047 | Return (Zero) 3048 | } 3049 | } 3050 | } 3051 | 3052 | Device (DSB5) 3053 | { 3054 | Name (_ADR, 0x00050000) // _ADR: Address 3055 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 3056 | Field (A1E0, ByteAcc, NoLock, Preserve) 3057 | { 3058 | AVND, 32, 3059 | BMIE, 3, 3060 | Offset (0x18), 3061 | PRIB, 8, 3062 | SECB, 8, 3063 | SUBB, 8, 3064 | Offset (0x1E), 3065 | , 13, 3066 | MABT, 1 3067 | } 3068 | 3069 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 3070 | { 3071 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB3.UPS0.DSB5.SECB */ 3072 | } 3073 | 3074 | Method (_STA, 0, NotSerialized) // _STA: Status 3075 | { 3076 | Return (0x0F) 3077 | } 3078 | 3079 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3080 | { 3081 | If (OSDW ()) 3082 | { 3083 | Return (One) 3084 | } 3085 | 3086 | Return (Zero) 3087 | } 3088 | } 3089 | 3090 | Device (DSB6) 3091 | { 3092 | Name (_ADR, 0x00060000) // _ADR: Address 3093 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 3094 | Field (A1E0, ByteAcc, NoLock, Preserve) 3095 | { 3096 | AVND, 32, 3097 | BMIE, 3, 3098 | Offset (0x18), 3099 | PRIB, 8, 3100 | SECB, 8, 3101 | SUBB, 8, 3102 | Offset (0x1E), 3103 | , 13, 3104 | MABT, 1 3105 | } 3106 | 3107 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 3108 | { 3109 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB3.UPS0.DSB6.SECB */ 3110 | } 3111 | 3112 | Method (_STA, 0, NotSerialized) // _STA: Status 3113 | { 3114 | Return (0x0F) 3115 | } 3116 | 3117 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3118 | { 3119 | If (OSDW ()) 3120 | { 3121 | Return (One) 3122 | } 3123 | 3124 | Return (Zero) 3125 | } 3126 | } 3127 | } 3128 | } 3129 | 3130 | Device (DSB4) 3131 | { 3132 | Name (_ADR, 0x00040000) // _ADR: Address 3133 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 3134 | Field (A1E0, ByteAcc, NoLock, Preserve) 3135 | { 3136 | AVND, 32, 3137 | BMIE, 3, 3138 | Offset (0x18), 3139 | PRIB, 8, 3140 | SECB, 8, 3141 | SUBB, 8, 3142 | Offset (0x1E), 3143 | , 13, 3144 | MABT, 1 3145 | } 3146 | 3147 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 3148 | { 3149 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB4.SECB */ 3150 | } 3151 | 3152 | Method (_STA, 0, NotSerialized) // _STA: Status 3153 | { 3154 | Return (0x0F) 3155 | } 3156 | 3157 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3158 | { 3159 | If (OSDW ()) 3160 | { 3161 | Return (One) 3162 | } 3163 | 3164 | Return (Zero) 3165 | } 3166 | 3167 | Device (UPS0) 3168 | { 3169 | Name (_ADR, Zero) // _ADR: Address 3170 | OperationRegion (ARE0, PCI_Config, Zero, 0x04) 3171 | Field (ARE0, ByteAcc, NoLock, Preserve) 3172 | { 3173 | AVND, 16 3174 | } 3175 | 3176 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3177 | { 3178 | If (OSDW ()) 3179 | { 3180 | Return (One) 3181 | } 3182 | 3183 | Return (Zero) 3184 | } 3185 | 3186 | Device (DSB0) 3187 | { 3188 | Name (_ADR, Zero) // _ADR: Address 3189 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 3190 | Field (A1E0, ByteAcc, NoLock, Preserve) 3191 | { 3192 | AVND, 32, 3193 | BMIE, 3, 3194 | Offset (0x18), 3195 | PRIB, 8, 3196 | SECB, 8, 3197 | SUBB, 8, 3198 | Offset (0x1E), 3199 | , 13, 3200 | MABT, 1, 3201 | Offset (0x3E), 3202 | , 6, 3203 | SBRS, 1 3204 | } 3205 | 3206 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 3207 | { 3208 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB4.UPS0.DSB0.SECB */ 3209 | } 3210 | 3211 | Method (_STA, 0, NotSerialized) // _STA: Status 3212 | { 3213 | Return (0x0F) 3214 | } 3215 | 3216 | Device (DEV0) 3217 | { 3218 | Name (_ADR, Zero) // _ADR: Address 3219 | Method (_STA, 0, NotSerialized) // _STA: Status 3220 | { 3221 | Return (0x0F) 3222 | } 3223 | 3224 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3225 | { 3226 | If (OSDW ()) 3227 | { 3228 | Return (One) 3229 | } 3230 | 3231 | Return (Zero) 3232 | } 3233 | } 3234 | } 3235 | 3236 | Device (DSB3) 3237 | { 3238 | Name (_ADR, 0x00030000) // _ADR: Address 3239 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 3240 | Field (A1E0, ByteAcc, NoLock, Preserve) 3241 | { 3242 | AVND, 32, 3243 | BMIE, 3, 3244 | Offset (0x18), 3245 | PRIB, 8, 3246 | SECB, 8, 3247 | SUBB, 8, 3248 | Offset (0x1E), 3249 | , 13, 3250 | MABT, 1 3251 | } 3252 | 3253 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 3254 | { 3255 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB4.UPS0.DSB3.SECB */ 3256 | } 3257 | 3258 | Method (_STA, 0, NotSerialized) // _STA: Status 3259 | { 3260 | Return (0x0F) 3261 | } 3262 | 3263 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3264 | { 3265 | If (OSDW ()) 3266 | { 3267 | Return (One) 3268 | } 3269 | 3270 | Return (Zero) 3271 | } 3272 | 3273 | Device (DEV0) 3274 | { 3275 | Name (_ADR, Zero) // _ADR: Address 3276 | Method (_STA, 0, NotSerialized) // _STA: Status 3277 | { 3278 | Return (0x0F) 3279 | } 3280 | 3281 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3282 | { 3283 | If (OSDW ()) 3284 | { 3285 | Return (One) 3286 | } 3287 | 3288 | Return (Zero) 3289 | } 3290 | } 3291 | } 3292 | 3293 | Device (DSB4) 3294 | { 3295 | Name (_ADR, 0x00040000) // _ADR: Address 3296 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 3297 | Field (A1E0, ByteAcc, NoLock, Preserve) 3298 | { 3299 | AVND, 32, 3300 | BMIE, 3, 3301 | Offset (0x18), 3302 | PRIB, 8, 3303 | SECB, 8, 3304 | SUBB, 8, 3305 | Offset (0x1E), 3306 | , 13, 3307 | MABT, 1 3308 | } 3309 | 3310 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 3311 | { 3312 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB4.UPS0.DSB4.SECB */ 3313 | } 3314 | 3315 | Method (_STA, 0, NotSerialized) // _STA: Status 3316 | { 3317 | Return (0x0F) 3318 | } 3319 | 3320 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3321 | { 3322 | If (OSDW ()) 3323 | { 3324 | Return (One) 3325 | } 3326 | 3327 | Return (Zero) 3328 | } 3329 | 3330 | Device (DEV0) 3331 | { 3332 | Name (_ADR, Zero) // _ADR: Address 3333 | Method (_STA, 0, NotSerialized) // _STA: Status 3334 | { 3335 | Return (0x0F) 3336 | } 3337 | 3338 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3339 | { 3340 | If (OSDW ()) 3341 | { 3342 | Return (One) 3343 | } 3344 | 3345 | Return (Zero) 3346 | } 3347 | } 3348 | } 3349 | 3350 | Device (DSB5) 3351 | { 3352 | Name (_ADR, 0x00050000) // _ADR: Address 3353 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 3354 | Field (A1E0, ByteAcc, NoLock, Preserve) 3355 | { 3356 | AVND, 32, 3357 | BMIE, 3, 3358 | Offset (0x18), 3359 | PRIB, 8, 3360 | SECB, 8, 3361 | SUBB, 8, 3362 | Offset (0x1E), 3363 | , 13, 3364 | MABT, 1 3365 | } 3366 | 3367 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 3368 | { 3369 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB4.UPS0.DSB5.SECB */ 3370 | } 3371 | 3372 | Method (_STA, 0, NotSerialized) // _STA: Status 3373 | { 3374 | Return (0x0F) 3375 | } 3376 | 3377 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3378 | { 3379 | If (OSDW ()) 3380 | { 3381 | Return (One) 3382 | } 3383 | 3384 | Return (Zero) 3385 | } 3386 | } 3387 | 3388 | Device (DSB6) 3389 | { 3390 | Name (_ADR, 0x00060000) // _ADR: Address 3391 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 3392 | Field (A1E0, ByteAcc, NoLock, Preserve) 3393 | { 3394 | AVND, 32, 3395 | BMIE, 3, 3396 | Offset (0x18), 3397 | PRIB, 8, 3398 | SECB, 8, 3399 | SUBB, 8, 3400 | Offset (0x1E), 3401 | , 13, 3402 | MABT, 1 3403 | } 3404 | 3405 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 3406 | { 3407 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB4.UPS0.DSB6.SECB */ 3408 | } 3409 | 3410 | Method (_STA, 0, NotSerialized) // _STA: Status 3411 | { 3412 | Return (0x0F) 3413 | } 3414 | 3415 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3416 | { 3417 | If (OSDW ()) 3418 | { 3419 | Return (One) 3420 | } 3421 | 3422 | Return (Zero) 3423 | } 3424 | } 3425 | } 3426 | } 3427 | 3428 | Device (DSB5) 3429 | { 3430 | Name (_ADR, 0x00050000) // _ADR: Address 3431 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 3432 | Field (A1E0, ByteAcc, NoLock, Preserve) 3433 | { 3434 | AVND, 32, 3435 | BMIE, 3, 3436 | Offset (0x18), 3437 | PRIB, 8, 3438 | SECB, 8, 3439 | SUBB, 8, 3440 | Offset (0x1E), 3441 | , 13, 3442 | MABT, 1 3443 | } 3444 | 3445 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 3446 | { 3447 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB5.SECB */ 3448 | } 3449 | 3450 | Method (_STA, 0, NotSerialized) // _STA: Status 3451 | { 3452 | Return (0x0F) 3453 | } 3454 | 3455 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3456 | { 3457 | If (OSDW ()) 3458 | { 3459 | Return (One) 3460 | } 3461 | 3462 | Return (Zero) 3463 | } 3464 | } 3465 | 3466 | Device (DSB6) 3467 | { 3468 | Name (_ADR, 0x00060000) // _ADR: Address 3469 | OperationRegion (A1E0, PCI_Config, Zero, 0x40) 3470 | Field (A1E0, ByteAcc, NoLock, Preserve) 3471 | { 3472 | AVND, 32, 3473 | BMIE, 3, 3474 | Offset (0x18), 3475 | PRIB, 8, 3476 | SECB, 8, 3477 | SUBB, 8, 3478 | Offset (0x1E), 3479 | , 13, 3480 | MABT, 1 3481 | } 3482 | 3483 | Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number 3484 | { 3485 | Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB6.SECB */ 3486 | } 3487 | 3488 | Method (_STA, 0, NotSerialized) // _STA: Status 3489 | { 3490 | Return (0x0F) 3491 | } 3492 | 3493 | Method (_RMV, 0, NotSerialized) // _RMV: Removal Status 3494 | { 3495 | If (OSDW ()) 3496 | { 3497 | Return (One) 3498 | } 3499 | 3500 | Return (Zero) 3501 | } 3502 | } 3503 | } 3504 | } 3505 | 3506 | Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method 3507 | { 3508 | If (OSDW ()) 3509 | { 3510 | If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) 3511 | { 3512 | Local0 = Package (0x02) 3513 | { 3514 | "PCI-Thunderbolt", 3515 | One 3516 | } 3517 | DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) 3518 | Return (Local0) 3519 | } 3520 | } 3521 | 3522 | Return (Zero) 3523 | } 3524 | } 3525 | } 3526 | } 3527 | 3528 | --------------------------------------------------------------------------------