├── image.png
├── SRT2
    ├── q_sel.v
    ├── find_1.v
    ├── tb_srt.v
    └── SRT2.v
├── SRT4
    ├── find_1.v
    ├── tb_srt.v
    ├── q_sel.v
    └── SRT4.v
└── README.md


/image.png:
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https://raw.githubusercontent.com/out-of-order55/SRT-Divider/HEAD/image.png


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/SRT2/q_sel.v:
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 1 | module q_sel #(
 2 |     parameter WIDTH = 8
 3 | ) (
 4 |     rem     ,
 5 |     d       ,
 6 |     q       ,
 7 |     neg
 8 | );
 9 | input[2:0]  rem;
10 | input       d;
11 | output reg  q;
12 | output      neg;
13 | 
14 | always @(*) begin
15 |     if(rem<3'b010|rem>=3'b110)begin
16 |         q = 1'b0;
17 |     end
18 |     else begin
19 |         q = 1'b1;
20 |     end
21 | end
22 | assign neg = q&(d!=rem[2]);
23 | endmodule


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/SRT2/find_1.v:
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 1 | module find_1#
 2 | (
 3 |     parameter WID=8
 4 | )
 5 | (
 6 |     d_i     ,
 7 |     pos_o   
 8 | );
 9 | input   [WID-1:0]    d_i;
10 | output  reg[WID-1:0]     pos_o;
11 | 
12 | wire [WID-1:0] pos_oh;
13 | 
14 | reg [WID-1:0] op_t;//one hot
15 | integer i;
16 | always @(*) begin
17 | 	for(i=0; i<WID; i=i+1) begin
18 | 		if(d_i[WID-1]==1'b0) begin
19 | 			op_t[i] <= d_i[WID-1-i];
20 | 		end 
21 |         else begin
22 | 			op_t[i] <= ~d_i[WID-1-i];
23 | 		end
24 | 	end
25 | end
26 | 
27 | assign pos_oh = op_t & (~op_t+1);	// ripple carry
28 | 
29 | integer j;
30 | always @(*) begin
31 | 	for(j=0; j<WID; j=j+1) begin
32 | 		if(pos_oh[j]==1) begin
33 | 			pos_o <= j-1;
34 | 		end
35 | 	end
36 | end
37 | endmodule


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/SRT4/find_1.v:
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 1 | module find_1#
 2 | (
 3 |     parameter WID=8
 4 | )
 5 | (
 6 |     d_i     ,
 7 |     pos_o   
 8 | );
 9 | input   [WID-1:0]    d_i;
10 | output  reg[WID-1:0]     pos_o;
11 | 
12 | wire [WID-1:0] pos_oh;
13 | 
14 | reg [WID-1:0] op_t;//one hot
15 | integer i;
16 | always @(*) begin
17 | 	for(i=0; i<WID; i=i+1) begin
18 | 		if(d_i[WID-1]==1'b0) begin
19 | 			op_t[i] <= d_i[WID-1-i];
20 | 		end 
21 |         else begin
22 | 			op_t[i] <= ~d_i[WID-1-i];
23 | 		end
24 | 	end
25 | end
26 | 
27 | assign pos_oh = op_t & (~op_t+1);	// ripple carry
28 | 
29 | integer j;
30 | always @(*) begin
31 | 	for(j=0; j<WID; j=j+1) begin
32 | 		if(pos_oh[j]==1) begin
33 | 			pos_o <= j-1;
34 | 		end
35 | 	end
36 | end
37 | endmodule


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/README.md:
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 1 | # SRT-Divider
 2 | 
 3 | ## 简介
 4 |     本文适用人群:已经了解恢复除法和非恢复除法,想实现SRT除法。
 5 | SRT除法属于non-restoring除法的一种,我们正常使用算式计算除法是一位一位的得到商值,但实际上我们可以一次计算多位,这样就会加速除法,而SRT除法就是通过一次得出多位商来加速除法。
 6 | ## SRT前置知识
 7 | 1.https://zhuanlan.zhihu.com/p/397563781 <br>
 8 | 知乎的这篇文章将SRT需要知道的前置知识总结了一下,不过大概率看不懂,没关系,还有一个链接<br> 
 9 | 2.https://zhuanlan.zhihu.com/p/550913605 <br>
10 | 这个链接主要讲解了SRT除法的实现,如果仅仅想实现SRT除法,强推这个链接<br>
11 | 如果真的想读懂SRT,建议搜索A New Class of Digital Division Methods,这篇论文是SRT算法的源论文之一,另一篇全是数学推导
12 | ## 实现细节
13 | 主要有四个模块:QDS表,找1模块,on-the-fly conversion和DIV状态机
14 | ### QDS 表
15 | 见链接2或3,选择任意一个实现即可
16 | ### 找1模块
17 | 网上很多资料了,本人采用的one hot码实现
18 | ### on-the-fly
19 | 在看完上面两个链接后,你可能觉得还是不太懂,并且也没说on-the-fly怎么实现<br>
20 | 3.https://www.cnblogs.com/devindd/articles/17633558.html<br>
21 | 这个链接列出了on-the-fly的实现公式,并且给出了SRT4除法的QDS表一种选择方法<br>
22 | 我自己是按照第二个链接给的QDS表实现的,在实现中,发现-2,-1,0,1,2的边界商的取值也不能乱选(可以看看当选择的table为15时,有一部分范围会重叠),对于这些部分,其可供选择的商就有两个,比如部分余数的前六位为-4,这时候既可以选择1,也可以选择0,但我建议选择1,有时候选择0会导致之后的步骤部分余数前六位超出QDS表的范围(实现中在高位商遇到该问题,选择0导致输出最大也达不到正确的值)
23 | ### DIV状态机  
24 | 
25 | ![alt text](image.png)<br>
26 | 
27 | 图上未标出转换条件即为下周期就跳转状态,下面介绍每个状态的含义  
28 | **IDLE**:DIV初始状态,等待valid信号输入  
29 | **DIV_1**:除数为1,这时有些table商选择范围会超出QDS表,导致计算出错,故单独列一个状态计算除数为1的情况  
30 | **DIV_ERROR**:除数为0,拉高error信号  
31 | **DIV_PRE**:寄存除数被除数,得出到底该使用QDS表的哪个table  
32 | **DIV_WORKING**:除法器运行状态,当div_cnt为0时结束运行,div_cnt的初始值即为迭代次数,对于SRT4来说,迭代次数为位宽的1/2  
33 | **DIV_END**:对得到的商和余数做后处理,查看余数正负性,生成ready信号  
34 | ## 仿真
35 | 先生成正确的商和余数,然后等自己的除法器计算完成后进行对比,如果错误则停止仿真。
36 | ## 其他参考资料
37 | https://zhuanlan.zhihu.com/p/445439418<br>
38 | COMPUTER ARITHMETIC Algorithms and Hardware Designs:这本书介绍了许多高级的乘除法算法  
39 | Higher-Radix Division Using Estimates of the Divisor and Partial Remainders:对高基SRT算法的分析论文
40 | 


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/SRT2/tb_srt.v:
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 1 | `timescale 1ns/1ps
 2 | module tb_srt();
 3 | parameter WID=64;
 4 | reg            clk;
 5 | reg            rst;
 6 | wire[WID-1:0]  rem_ref;
 7 | wire[WID-1:0]  q_ref;
 8 | wire[WID-1:0]  rem_d;
 9 | wire[WID-1:0]  q_d;
10 | reg[WID-1:0]   dividend;
11 | reg start;
12 | reg[WID-1:0]  divisor;
13 | reg valid;
14 | parameter    MAX_NUM = 64'hffffffffff;
15 | parameter    MIN_NUM = 64'hffffff;
16 | 
17 | initial begin
18 |     clk <= 1'b0;
19 |     rst <= 1'b1;
20 |     start <= 1'b0;
21 |     #60
22 |     rst <= 1'b0;
23 |     #20
24 |     start <= 1'b1;
25 |     #20
26 |     start <= 1'b0;
27 | end
28 | always #10 clk <= ~clk;
29 | always @(posedge clk) begin
30 |     if(rst)begin
31 |         dividend <= 'b1;
32 |         divisor  <= 'b1;
33 |         valid    <= 'b0;
34 |     end
35 |     else if(start)begin
36 |         dividend <= MIN_NUM + {$random()} % (MAX_NUM-MIN_NUM+1);
37 |         divisor  <= {$random()} % MIN_NUM+1;
38 |         valid    <= 1'b1;
39 |     end
40 |     else if(ready)begin
41 |         dividend <= MIN_NUM + {$random()} % (MAX_NUM-MIN_NUM+1);
42 |         divisor  <= {$random()} % MIN_NUM+1;
43 |         valid    <= 1'b1;
44 |     end
45 |     else begin
46 |         valid <= 1'b0;
47 |     end
48 | end
49 | assign rem_ref = dividend%divisor;
50 | assign q_ref   = dividend/divisor;
51 | always @(*) begin
52 |     if(ready)begin
53 |         if((rem_ref!=rem_d)|(q_ref!=q_d))begin
54 |             $stop;
55 |         end
56 |     end
57 | end
58 | wire ready;
59 | SRT2 #(
60 |     .WID(WID)
61 | ) SRT2(
62 |     .clk         (clk),
63 |     .rst         (rst),
64 |     .dividend    (dividend),
65 |     .divisor     (divisor),
66 |     .valid       (valid),
67 |     .ready       (ready),
68 |     .quotient    (q_d),
69 |     .remainder   (rem_d)   
70 | );
71 | endmodule


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/SRT4/tb_srt.v:
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 1 | `timescale 1ns/1ps
 2 | module tb_srt();
 3 | parameter WID=64;
 4 | reg            clk;
 5 | reg            rst;
 6 | wire signed[WID-1:0]  rem_ref;
 7 | wire signed[WID-1:0]  q_ref;
 8 | wire[WID-1:0]  rem_d;
 9 | wire[WID-1:0]  q_d;
10 | reg signed[WID-1:0]   dividend;
11 | reg start;
12 | reg signed[WID-1:0]  divisor;
13 | reg valid;
14 | parameter    MAX_NUM = 64'hffffffffffffffff;
15 | parameter    MIN_NUM = 64'h7fffffffffffffff;
16 | 
17 | initial begin
18 |     clk <= 1'b0;
19 |     rst <= 1'b1;
20 |     start <= 1'b0;
21 |     #60
22 |     rst <= 1'b0;
23 |     #20
24 |     start <= 1'b1;
25 |     #20
26 |     start <= 1'b0;
27 | end
28 | always #10 clk <= ~clk;
29 | always @(posedge clk) begin
30 |     if(rst)begin
31 |         dividend <= 'b1;
32 |         divisor  <= 'b1;
33 |         valid    <= 'b0;
34 |     end
35 |     else if(start)begin
36 |         dividend <= MIN_NUM + {$random()} % (MAX_NUM-MIN_NUM+1);
37 |         divisor  <= {$random()} % MIN_NUM+1;
38 |         valid    <= 1'b1;
39 |     end
40 |     else if(ready)begin
41 |         dividend <= MIN_NUM + {$random()} % (MAX_NUM-MIN_NUM+1);
42 |         divisor  <= {$random()} % MIN_NUM+1;
43 |         valid    <= 1'b1;
44 |     end
45 |     else begin
46 |         valid <= 1'b0;
47 |     end
48 | end
49 | assign rem_ref = dividend%divisor;
50 | assign q_ref   = dividend/divisor;
51 | always @(*) begin
52 |     if(ready)begin
53 |         if((rem_ref!=rem_d)|(q_ref!=q_d))begin
54 |             $stop;
55 |         end
56 |     end
57 | end
58 | wire ready;
59 | SRT4 #(
60 |     .WID(WID)
61 | ) SRT4(
62 |     .clk         (clk),
63 |     .rst         (rst),
64 |     .dividend    (dividend),
65 |     .divisor     (divisor),
66 |     .sign        (1'b1),
67 |     .valid       (valid),
68 |     .ready       (ready),
69 |     .quotient    (q_d),
70 |     .remainder   (rem_d)   
71 | );
72 | endmodule


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/SRT4/q_sel.v:
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 1 | module q_sel #(
 2 |     parameter WIDTH = 8
 3 | ) (
 4 |     rem     ,
 5 |     d       ,
 6 |     q       ,
 7 |     neg
 8 | );
 9 | input[5:0]   rem;
10 | input[3:0]   d;
11 | output[1:0]  q;
12 | output       neg;
13 | 
14 | wire    table_8,table_9,table_10,table_11,table_12,table_13,table_14,table_15;
15 | 
16 | assign table_8  = d==4'b1000;
17 | assign table_9  = d==4'b1001;
18 | assign table_10 = d==4'b1010;
19 | assign table_11 = d==4'b1011;
20 | assign table_12 = d==4'b1100;
21 | assign table_13 = d==4'b1101;
22 | assign table_14 = d==4'b1110;
23 | assign table_15 = d==4'b1111;
24 | wire   q2       ;
25 | wire   q0       ;
26 | 
27 | assign neg = 
28 |             table_8 &&(rem>=6'b110100&&rem<6'b111110)
29 |             ||table_9 &&(rem>=6'b110010&&rem<6'b111101)
30 |             ||table_10&&(rem>=6'b110001&&rem<6'b111101)
31 |             ||table_11&&(rem>=6'b110000&&rem<6'b111101)
32 |             ||table_12&&(rem>=6'b101110&&rem<6'b111100)
33 |             ||table_13&&(rem>=6'b101101&&rem<6'b111100)
34 |             ||table_14&&(rem>=6'b101100&&rem<6'b111100)
35 |             ||table_15&&(rem>=6'b101010&&rem<6'b111100);
36 | assign q2 = 
37 |             table_8 &&((rem>=6'b110100&&rem<6'b111010)||(rem>=6'b000110&&rem<=6'b001011))
38 |             ||table_9 &&((rem>=6'b110010&&rem<6'b111001)||(rem>=6'b000111&&rem<=6'b001101))
39 |             ||table_10&&((rem>=6'b110001&&rem<6'b111000)||(rem>=6'b001000&&rem<=6'b001110))
40 |             ||table_11&&((rem>=6'b110000&&rem<6'b110111)||(rem>=6'b001000&&rem<=6'b001111))
41 |             ||table_12&&((rem>=6'b101110&&rem<6'b110110)||(rem>=6'b001001&&rem<=6'b010001))
42 |             ||table_13&&((rem>=6'b101101&&rem<6'b110110)||(rem>=6'b001010&&rem<=6'b010010))
43 |             ||table_14&&((rem>=6'b101100&&rem<6'b110101)||(rem>=6'b001010&&rem<=6'b010011))
44 |             ||table_15&&((rem>=6'b101010&&rem<6'b110100)||(rem>=6'b001011&&rem<=6'b010101));
45 | assign q0 = 
46 |             table_8 &&((rem>=6'b111110&&rem<=6'b111111)||  (rem>=0&&rem<6'b000010))
47 |             ||table_9 &&((rem>=6'b111101&&rem<=6'b111111)||(rem>=0&&rem<6'b000010))
48 |             ||table_10&&((rem>=6'b111101&&rem<=6'b111111)||(rem>=0&&rem<6'b000010))
49 |             ||table_11&&((rem>=6'b111101&&rem<=6'b111111)||(rem>=0&&rem<6'b000010))
50 |             ||table_12&&((rem>=6'b111100&&rem<=6'b111111)||(rem>=0&&rem<6'b000011))
51 |             ||table_13&&((rem>=6'b111100&&rem<=6'b111111)||(rem>=0&&rem<6'b000011))
52 |             ||table_14&&((rem>=6'b111100&&rem<=6'b111111)||(rem>=0&&rem<6'b000011))
53 |             ||table_15&&((rem>=6'b111100&&rem<=6'b111111)||(rem>=0&&rem<6'b000100));
54 | assign q =   q2 ? 2'b10 
55 |             :q0 ? 2'b00
56 |             :2'b01;
57 | endmodule


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/SRT2/SRT2.v:
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  1 | module SRT2 #(
  2 |     parameter WID=8
  3 | ) (
  4 |     clk         ,
  5 |     rst         ,
  6 |     dividend    ,
  7 |     divisor     ,
  8 |     valid       ,
  9 |     ready       ,
 10 |     quotient    ,
 11 |     remainder      
 12 | );
 13 | input           clk;
 14 | input           rst;
 15 | input[WID-1:0]  dividend;
 16 | input[WID-1:0]  divisor;
 17 | input           valid;
 18 | output          ready; 
 19 | output[WID-1:0]  quotient;
 20 | output[WID-1:0]  remainder;
 21 | 
 22 | reg             ready_o;
 23 | wire[WID-1:0]   pos_1;
 24 | wire            q;
 25 | wire            neg;
 26 | reg[WID-1:0]    div_shift;
 27 | reg             dividend_sign;
 28 | always @(posedge clk) begin
 29 |     if(rst)begin
 30 |         dividend_sign <= 'b0;
 31 |     end
 32 |     else if(valid)begin
 33 |         dividend_sign <= dividend[WID-1];
 34 |     end
 35 | end
 36 | find_1#
 37 | (
 38 |     .WID(WID)
 39 | )
 40 | find_1(
 41 |     .d_i     (divisor),
 42 |     .pos_o   (pos_1)
 43 | );
 44 | q_sel #(
 45 |     .WIDTH(WID)
 46 | )q_sel (
 47 |     .rem     (shift_rem[WID:WID-2]),
 48 |     .d       (1'b0),
 49 |     .q       (q),
 50 |     .neg     (neg)
 51 | );
 52 | always @(posedge clk) begin
 53 |     if(rst)begin
 54 |         div_shift <= 'b0;
 55 |     end
 56 |     else if(valid)begin
 57 |         div_shift <= pos_1+2;//to allow op1 in{-1/2,1/2}
 58 |     end
 59 | end
 60 | wire[WID+1:0]     shift_divisor;
 61 | wire[WID+1:0]     shift_divisor_n;
 62 | reg[WID+1:0]      Q;
 63 | reg[WID+1:0]      QM;  
 64 | reg[WID+1:0]      shift_rem;
 65 | reg[WID+1:0]      div_cnt;  
 66 | assign shift_divisor   = divisor<<div_shift;
 67 | assign shift_divisor_n = (~shift_divisor)+1;
 68 | 
 69 | parameter   IDLE = 2'b00,
 70 |                 DIV_WORKING = 2'b01,
 71 |                 DIV_END = 2'b11;
 72 | reg[1:0]    state;
 73 | always @(posedge clk) begin
 74 |     if(rst)begin
 75 |         state <= IDLE;
 76 |     end
 77 |     else begin
 78 |         case (state)
 79 |             IDLE:begin
 80 |                 if(valid)begin
 81 |                     state <= DIV_WORKING;
 82 |                 end
 83 |             end
 84 |             DIV_WORKING:begin
 85 |                 if(div_cnt=='b0)
 86 |                     state <= DIV_END;
 87 |             end
 88 |             DIV_END:begin
 89 |                 state <= IDLE;
 90 |             end 
 91 |             default: state <= IDLE;
 92 |         endcase
 93 |     end
 94 | end
 95 | reg[WID+1:0]      Q1;
 96 | reg[WID+1:0]      QM1;  
 97 | //on-the-fly-convert
 98 | // always @(posedge clk) begin
 99 | //     if(rst)begin
100 | //         Q <= 'b0;
101 | //         QM<= 'b0;
102 | //     end
103 | //     else if(state==DIV_WORKING)begin
104 | //         case ({q,neg})
105 | //             2'b00:begin
106 | //                 Q <= {Q[WID:0],1'b0};
107 | //                 QM <= {QM[WID:0],1'b0};
108 | //             end
109 | //             2'b01:begin
110 | //                 Q  <= {Q[WID:0],1'b0};
111 | //                 QM <= {QM[WID:0],1'b0};
112 | //             end
113 | //             2'b10:begin
114 | //                 Q  <= {Q[WID:0],q};
115 | //                 QM <= {QM[WID:0],1'b0};
116 | //             end
117 | //             2'b11: begin
118 | //                 Q  <= {Q[WID:0],1'b0};
119 | //                 QM <= {QM[WID:0],q};
120 | //             end 
121 | //             default: ;
122 | //         endcase
123 | //     end
124 | //     else begin
125 | //         Q <= 'b0;
126 | //         QM<= 'b0;
127 | //     end
128 | // end
129 | always @(posedge clk) begin
130 |     if(rst)begin
131 |         Q <= 'b0;
132 |         QM<= 'b0;
133 |     end
134 |     else if(state==DIV_WORKING)begin
135 |         if(~neg)begin
136 |             Q <= {Q[WID:0],q};
137 |         end
138 |         else begin
139 |             Q <= {QM[WID:0],q};
140 |         end
141 |         if ((~neg)&&(q))begin
142 |             QM <= {Q[WID:0],~q};
143 |         end
144 |         else begin
145 |             QM <= {QM[WID:0],~q};
146 |         end
147 |     end
148 |     else begin
149 |         Q <= 'b0;
150 |         QM<= 'b0;
151 |     end
152 | end
153 | ////////////////////////
154 | reg[WID+1:0]    fin_q;
155 | reg[WID+1:0]    fin_rem;
156 | always @(posedge clk) begin
157 |     if(rst)begin
158 |         fin_q   <= 'b0;
159 |         fin_rem <= 'b0;
160 |     end
161 |     else if(state==DIV_END)begin
162 |         if((shift_rem[WID+1]))begin
163 |             fin_rem <= shift_rem + shift_divisor;
164 |             fin_q   <= Q-1;
165 |         end
166 |         else begin
167 |             fin_rem <= shift_rem;
168 |             fin_q   <= Q ;
169 |         end
170 |     end
171 | end
172 | always @(posedge clk) begin
173 |     if(rst)begin
174 |         div_cnt <= 'b0;
175 |     end
176 |     else if(valid)begin
177 |         div_cnt <= pos_1+1;
178 |     end
179 |     else if(state==DIV_WORKING)begin
180 |         div_cnt <= div_cnt - 1 ;
181 |     end
182 | end
183 | always @(posedge clk) begin
184 |     if(rst)begin
185 |         shift_rem <= 'b0;
186 |     end
187 |     else if(valid)begin
188 |         shift_rem <= dividend;
189 |     end
190 |     else begin
191 |         case ({q,neg})
192 |             2'b00:shift_rem <= {shift_rem[WID:0],1'b0};
193 |             2'b01:shift_rem <= {shift_rem[WID:0],1'b0};
194 |             2'b10:shift_rem <= {shift_rem[WID:0],1'b0}+shift_divisor_n;
195 |             2'b11:shift_rem <= {shift_rem[WID:0],1'b0}+shift_divisor;
196 |             default: ;
197 |         endcase 
198 |     end
199 | end
200 | always @(posedge clk) begin
201 |     if(rst)begin
202 |         ready_o <= 'b0;
203 |     end
204 |     else if(state==DIV_END)begin
205 |         ready_o <= 1'b1;
206 |     end
207 |     else begin
208 |         ready_o <= 1'b0;
209 |     end
210 | end
211 | assign  ready = ready_o;
212 | assign  quotient = fin_q;
213 | assign  remainder= fin_rem>>div_shift;
214 | endmodule


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/SRT4/SRT4.v:
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  1 | module SRT4 #(
  2 |     parameter WID=8
  3 | ) (
  4 |     clk         ,
  5 |     rst         ,
  6 |     dividend    ,
  7 |     divisor     ,
  8 |     sign        ,
  9 |     valid       ,
 10 |     ready       ,
 11 |     quotient    ,
 12 |     error       ,
 13 |     remainder      
 14 | );
 15 | input           clk;
 16 | input           rst;
 17 | input[WID-1:0]  dividend;
 18 | input[WID-1:0]  divisor;
 19 | input           sign;
 20 | input           valid;
 21 | output          error;
 22 | output          ready; 
 23 | output[WID-1:0]  quotient;
 24 | output[WID-1:0]  remainder;
 25 | 
 26 | 
 27 | wire [2*WID:0]  rem;//only use [2*WID:WID]
 28 | reg             ready_o;
 29 | wire[WID-1:0]   pos_1;
 30 | wire[1:0]       q;
 31 | wire            neg;
 32 | reg[WID-1:0]    div_shift;
 33 | reg[WID-1:0]    dividend_r;
 34 | reg[WID-1:0]    divisor_r;
 35 | reg[1:0]        div_sign;//{dividend,divisor}
 36 | reg             sign_r;    
 37 | wire[3:0]       qds_table;
 38 | wire[WID-1:0]   dividend_u;
 39 | wire[WID-1:0]   divisor_u;
 40 | wire[WID:0]     shift_divisor_X2;
 41 | wire[WID:0]     shift_divisor;
 42 | wire[WID:0]     shift_divisor_X2n;
 43 | wire[WID:0]     shift_divisor_n;
 44 | 
 45 | reg[WID:0]      Q;
 46 | reg[WID:0]      QM;  
 47 | reg[2*WID:0]    shift_rem;
 48 | reg[WID-1:0]    shift_dividend;
 49 | reg[WID:0]      div_cnt;
 50 | reg[WID:0]      fin_q;
 51 | reg[WID:0]      fin_rem;
 52 | wire[WID:0]     q_signed;
 53 | wire[WID:0]     rem_signed;
 54 | wire[WID:0]     q_unsigned;
 55 | wire[WID:0]     rem_unsigned;
 56 | reg[2:0]        state;
 57 | 
 58 | assign dividend_u = sign&&dividend[WID-1]?(~dividend+1):dividend;
 59 | assign divisor_u  = sign&&divisor[WID-1]?(~divisor+1):divisor;
 60 | always @(posedge clk) begin
 61 |     if(rst)begin
 62 |         sign_r <= 'b0;
 63 |     end
 64 |     else if(valid&&sign)begin
 65 |         sign_r <= sign;
 66 |     end
 67 | end
 68 | always @(posedge clk) begin
 69 |     if(rst)begin
 70 |         dividend_r <= 'b0;
 71 |         divisor_r  <= 'b0;
 72 |         div_sign   <= 'b0;
 73 |     end
 74 |     else if(valid)begin
 75 |         dividend_r <= dividend_u;
 76 |         divisor_r  <= divisor_u;
 77 |         div_sign   <= {dividend[WID-1],divisor[WID-1]};
 78 |     end
 79 | end
 80 | 
 81 | 
 82 | find_1#
 83 | (
 84 |     .WID(WID)
 85 | )
 86 | find_1(
 87 |     .d_i     (divisor_u),
 88 |     .pos_o   (pos_1)
 89 | );
 90 | q_sel #(
 91 |     .WIDTH(WID)
 92 | )q_sel (
 93 |     .rem     (shift_rem[2*WID:2*WID-5]),
 94 |     .d       (qds_table),
 95 |     .q       (q),
 96 |     .neg     (neg)
 97 | );
 98 | always @(posedge clk) begin
 99 |     if(rst)begin
100 |         div_shift <= 'b0;
101 |     end
102 |     else if(state==IDLE&&valid)begin
103 |         div_shift <= pos_1+1;
104 |     end
105 | end
106 | 
107 | assign rem              = {{(WID+1){0}},dividend_r}<<div_shift;
108 | assign qds_table        = shift_divisor[WID-1:WID-4];
109 | assign shift_divisor    = divisor_r<<div_shift;
110 | assign shift_divisor_n  = (~shift_divisor)+1;
111 | assign shift_divisor_X2 = shift_divisor<<1;
112 | assign shift_divisor_X2n=(~shift_divisor_X2)+1; 
113 | 
114 | parameter       IDLE = 3'b000,
115 |                 DIV_PRE = 3'b001,
116 |                 DIV_WORKING = 3'b010,
117 |                 DIV_END = 3'b011,
118 |                 DIV_1   = 3'b100,
119 |                 DIV_ERROR=3'b101;
120 | 
121 | 
122 | always @(posedge clk) begin
123 |     if(rst)begin
124 |         state <= IDLE;
125 |     end
126 |     else begin
127 |         case (state)
128 |             IDLE:begin
129 |                 if(valid)begin
130 |                     if(divisor==0)begin
131 |                         state <= DIV_ERROR;
132 |                     end
133 |                     else if(divisor==1)begin
134 |                         state <= DIV_1; 
135 |                     end
136 |                     else begin
137 |                         state <= DIV_PRE;
138 |                     end
139 |                 end
140 |             end
141 |             DIV_PRE:state <= DIV_WORKING;
142 |             DIV_WORKING:begin
143 |                 if(div_cnt=='b0)
144 |                     state <= DIV_END;
145 |             end
146 |             DIV_END:begin
147 |                 state <= IDLE;
148 |             end
149 |             DIV_ERROR:begin
150 |                 state <= IDLE;
151 |             end  
152 |             DIV_1:begin
153 |                 state <= IDLE;
154 |             end
155 |             default: state <= IDLE;
156 |         endcase
157 |     end
158 | end
159 | 
160 | always @(posedge clk) begin
161 |     if(rst)begin
162 |         shift_rem <= 'b0;
163 |     end
164 |     else if(state==DIV_PRE)begin
165 |         shift_rem <= rem;
166 |     end
167 |     else begin
168 |         case ({neg,q})
169 |             3'b000:shift_rem <= {shift_rem[2*WID-2:WID-2]+0                 ,shift_rem[WID-3:0],2'b0};
170 |             3'b001:shift_rem <= {shift_rem[2*WID-2:WID-2]+shift_divisor_n   ,shift_rem[WID-3:0],2'b0};
171 |             3'b010:shift_rem <= {shift_rem[2*WID-2:WID-2]+shift_divisor_X2n ,shift_rem[WID-3:0],2'b0};
172 |             3'b100:shift_rem <= {shift_rem[2*WID-2:WID-2]+0                 ,shift_rem[WID-3:0],2'b0};
173 |             3'b101:shift_rem <= {shift_rem[2*WID-2:WID-2]+shift_divisor     ,shift_rem[WID-3:0],2'b0};
174 |             3'b110:shift_rem <= {shift_rem[2*WID-2:WID-2]+shift_divisor_X2  ,shift_rem[WID-3:0],2'b0};
175 |             default: ;
176 |         endcase 
177 |     end
178 | end
179 | always @(posedge clk) begin
180 |     if(rst)begin
181 |         Q <= 'b0;
182 |         QM<= 'b0;
183 |     end
184 |     else if(state==DIV_WORKING)begin
185 |         if(~neg)begin
186 |             Q <= {Q[WID-3:0],q};
187 |         end
188 |         else begin
189 |             Q <= {QM[WID-3:0],1'b1,q[0]};
190 |         end
191 |         if ((~neg)&(|q))begin
192 |             QM <= {Q[WID-3:0],1'b0,q[1]};
193 |         end
194 |         else begin
195 |             QM <= {QM[WID-3:0],~q};
196 |         end
197 |     end
198 |     else begin
199 |         Q <= 'b0;
200 |         QM<= 'b0;
201 |     end
202 | end
203 | 
204 | ////////////////////////
205 | 
206 | always @(posedge clk) begin
207 |     if(rst)begin
208 |         fin_q   <= 'b0;
209 |         fin_rem <= 'b0;
210 |     end
211 |     else if(state==DIV_END)begin
212 |         if((shift_rem[2*WID]))begin
213 |             fin_rem <= shift_rem[2*WID:WID] + shift_divisor;
214 |             fin_q   <= Q-1;
215 |         end
216 |         else begin
217 |             fin_rem <= shift_rem[2*WID:WID];
218 |             fin_q   <= Q ;
219 |         end
220 |     end
221 | end
222 | always @(posedge clk) begin
223 |     if(rst)begin
224 |         div_cnt <= 'b0;
225 |     end
226 |     else if(valid)begin
227 |         div_cnt <= (WID>>1)-1;
228 |     end
229 |     else if(state==DIV_WORKING)begin
230 |         div_cnt <= div_cnt - 1 ;
231 |     end
232 | end
233 | 
234 | always @(posedge clk) begin
235 |     if(rst)begin
236 |         ready_o <= 'b0;
237 |     end
238 |     else if(state==DIV_END)begin
239 |         ready_o <= 1'b1;
240 |     end
241 |     else begin
242 |         ready_o <= 1'b0;
243 |     end
244 | end
245 | assign  q_signed     = (div_sign==2'b11||div_sign==2'b00)?fin_q:(~fin_q+1);
246 | assign  rem_signed   = (div_sign[1]==1'b1)?(~(fin_rem>>div_shift)+1):(fin_rem>>div_shift);
247 | assign  q_unsigned   = fin_q;
248 | assign  rem_unsigned = fin_rem>>div_shift;
249 | 
250 | assign  ready    = state==DIV_1?1'b1:ready_o;
251 | assign  quotient = state==DIV_1?dividend:(sign_r?q_signed:q_unsigned);
252 | assign  remainder= state==DIV_1?1'b0:(sign_r?rem_signed:rem_unsigned);
253 | assign  error    = state==DIV_ERROR;
254 | endmodule


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