├── .editorconfig
├── .gitignore
├── README.md
├── resources
    └── isa.jpg
├── sources
    ├── modules
    │   ├── ALU.v
    │   ├── Alu_Control.v
    │   ├── BufferRegister.v
    │   ├── Control_Unit.v
    │   ├── InstructionMemoryModule.v
    │   ├── MainMemory.v
    │   ├── ProgramCounter.v
    │   ├── Register_File.v
    │   ├── cpu.v
    │   ├── mux2x1.v
    │   ├── regmux2x1.v
    │   └── signExtension.v
    └── testbench
    │   ├── ALU_tb.v
    │   ├── Register_File_tb.v
    │   └── cpu_tb.v
└── utils
    ├── ISA.md
    ├── assembler.py
    ├── test_code
    └── test_code.bin


/.editorconfig:
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 1 | root = true
 2 | [*]
 3 | 
 4 | end_of_line = lf
 5 | insert_final_newline = true
 6 | trim_trailing_whitespace = true
 7 | 
 8 | [*.v]
 9 | charset = utf-8
10 | indent_style = space
11 | indent_size = 4
12 | 


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/.gitignore:
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1 | *.swp
2 | 


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/README.md:
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1 | ## RISC Processor
2 | 
3 | - A 32-bit RISC processor to with a self designed Instruction Set Architecture.
4 | 
5 | ### ISA
6 | 
7 | ![ISA](./resources/isa.jpg)
8 | 


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/resources/isa.jpg:
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https://raw.githubusercontent.com/pandeykartikey/RISCY-Processor/c476822b8c9853060e863092f10df8f04c620bff/resources/isa.jpg


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/sources/modules/ALU.v:
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  1 | `timescale 1ns / 1ps
  2 | 
  3 | module ALU(clk,a, b, alufn, otp, zero, overflow);
  4 |     input wire clk;
  5 |     input wire [31:0] a;
  6 |     input wire [31:0] b;
  7 |     input wire [5:0] alufn; // choosing 6 bit op code
  8 |     output reg [31:0] otp;
  9 |     output reg zero; // set if the output of the alu is 0
 10 |     output reg overflow;
 11 |     wire [31:0] tempAuRes;
 12 |     wire [31:0] tempLuRes;
 13 |     wire [31:0] tempSuRes;
 14 |     wire tempAuZero,tempAuOverflow;
 15 |     wire tempLuZero,tempLuOverflow;
 16 |     wire tempSuZero,tempSuOverflow;
 17 |     
 18 |     
 19 |     // ArithmeticUnit arith_inst_0(.a(a),.b(b),.alufn(alufn[1:0]),.otp(tempAuRes),.zero(tempAuZero),.overflow(tempAuOverflow));
 20 |     // LogicalUnit logic_inst_0(.a(a),.b(b),.alufn(alufn[1:0]),.otp(tempLuRes),.zero(tempLuZero),.overflow(tempLuOverflow));
 21 |     // ShiftUnit shift_inst_0(.a(a),.b(b),.alufn(alufn[1:0]),.otp(tempSuRes),.zero(tempSuZero),.overflow(tempSuOverflow));
 22 |     
 23 |     always @(a or b or alufn)
 24 |     begin
 25 |         // $display("a%h - b%h",a,b);
 26 |         // $display("tempAuRes- %h",tempAuRes);
 27 |         casex(alufn)
 28 |             6'b0000xx: begin
 29 |         if(alufn[1:0] == 2'b00)
 30 |             begin //ADD
 31 |                 otp = a + b;
 32 |                 zero = (otp==0)?1:0;
 33 |                 if ((a >= 0 && b >= 0 && otp < 0) || (a < 0 && b < 0 && otp >= 0))
 34 |                     overflow = 1;
 35 |                 else
 36 |                     overflow = 0;
 37 |                 $display("a%h - b%h - otp %h",a,b,otp);
 38 |             end
 39 |         else if(alufn[1:0] == 2'b01) //SUB
 40 |             begin
 41 |                 otp = a-b;
 42 |                 zero = (otp==0)?1:0;
 43 |                 if ((a >= 0 && b < 0 && otp < 0) || (a < 0 && b >= 0 && otp > 0))
 44 |                     overflow = 1;
 45 |                 else
 46 |                     overflow = 0;
 47 |             end
 48 |         else if (alufn[1:0] == 2'b10) //MUL
 49 |             begin
 50 |                 otp = a*b;
 51 |                 zero = (otp==0)?1:0;
 52 |                 overflow = 0;
 53 |             end
 54 |     end
 55 |             6'b0001xx: begin
 56 |         case (alufn[1:0])
 57 |         2'b00: //AND
 58 |             begin
 59 |                 otp = a & b;
 60 |                 overflow = 0;
 61 |                 zero = (otp==0)?1:0;
 62 |             end
 63 |         2'b01: //OR
 64 |             begin
 65 |                 otp = a | b;
 66 |                 overflow = 0;
 67 |                 zero = (otp==0)?1:0;
 68 |             end
 69 |         2'b10:  //XOR
 70 |                 begin
 71 |                     otp = a ^ b;
 72 |                     overflow = 0;
 73 |                     zero = (otp==0)?1:0;
 74 |                 end
 75 |         endcase
 76 |     end
 77 |             6'b0010xx: begin
 78 |         case(alufn[1:0])
 79 |         2'b00: //SHIFTLEFT
 80 |             begin
 81 |                 otp = a<<b;
 82 |                 zero = (otp == 0)?1:0;
 83 |                 overflow = 0;
 84 |             end
 85 |         2'b01: //shiftright
 86 |             begin
 87 |                 otp = a>>b;
 88 |                 zero = (otp == 0)?1:0;
 89 |                 overflow = 0;
 90 |             end
 91 |         2'b11: //slt
 92 |             begin
 93 |                 otp = (a<b)? 1:0;
 94 |                 zero = (otp == 0)?1:0;
 95 |                 overflow = 0;
 96 |             end
 97 |         endcase
 98 |     end
 99 |             default:
100 |             begin 
101 |                 otp = {32{1'b0}};
102 |             end
103 |         endcase
104 |         $display("a%h - b%h - otp %h alufn %b",a,b,otp,alufn);
105 |     end
106 | 
107 | endmodule
108 | 
109 | module ArithmeticUnit(a,b,alufn,otp,zero,overflow);
110 |     input wire [31:0] a;
111 |     input wire [31:0] b;
112 |     input wire [1:0] alufn; // choosing 6 bit op code
113 |     output reg [31:0] otp;
114 |     output reg zero; // set if the output of the alu is 0
115 |     output reg overflow;
116 |     
117 |     always @(alufn or a or b)
118 |     begin
119 |         $display("a%h - b%h - otp %h alufn %b",a,b,otp,alufn);
120 |         if(alufn == 2'b00)
121 |             begin //ADD
122 |                 otp = a + b;
123 |                 zero = (otp==0)?1:0;
124 |                 if ((a >= 0 && b >= 0 && otp < 0) || (a < 0 && b < 0 && otp >= 0))
125 |                     overflow = 1;
126 |                 else
127 |                     overflow = 0;
128 |                 $display("a%h - b%h - otp %h",a,b,otp);
129 |             end
130 |         else if(alufn == 2'b01) //SUB
131 |             begin
132 |                 otp = a-b;
133 |                 zero = (otp==0)?1:0;
134 |                 if ((a >= 0 && b < 0 && otp < 0) || (a < 0 && b >= 0 && otp > 0))
135 |                     overflow = 1;
136 |                 else
137 |                     overflow = 0;
138 |             end
139 |         else if (alufn == 2'b10) //MUL
140 |             begin
141 |                 otp = a*b;
142 |                 zero = (otp==0)?1:0;
143 |                 overflow = 0;
144 |             end
145 |     end
146 | endmodule
147 | 
148 | module LogicalUnit(a,b,otp,alufn,zero,overflow);
149 |     input wire [31:0] a;
150 |     input wire [31:0] b;
151 |     input wire [1:0] alufn;
152 |     output reg zero;
153 |     output reg overflow;
154 |     output reg [31:0] otp;
155 |     
156 |     always @(a,b,alufn)
157 |     begin
158 |         case (alufn)
159 |         2'b00: //AND
160 |             begin
161 |                 otp = a & b;
162 |                 overflow = 0;
163 |                 zero = (otp==0)?1:0;
164 |             end
165 |         2'b01: //OR
166 |             begin
167 |                 otp = a | b;
168 |                 overflow = 0;
169 |                 zero = (otp==0)?1:0;
170 |             end
171 |         2'b10:  //XOR
172 |                 begin
173 |                     otp = a ^ b;
174 |                     overflow = 0;
175 |                     zero = (otp==0)?1:0;
176 |                 end
177 |         endcase
178 |     end
179 | endmodule
180 | 
181 | module ShiftUnit(a,b,otp,alufn,zero,overflow);
182 |     input wire [31:0] a;
183 |     input wire [31:0] b;
184 |     input wire [1:0] alufn;
185 |     output reg zero;
186 |     output reg overflow;
187 |     output reg [31:0] otp;
188 |     
189 |     always @(a,b,alufn)
190 |     begin
191 |         case(alufn)
192 |         2'b00: //SHIFTLEFT
193 |             begin
194 |                 otp = a<<b;
195 |                 zero = (otp == 0)?1:0;
196 |                 overflow = 0;
197 |             end
198 |         2'b01: //shiftright
199 |             begin
200 |                 otp = a>>b;
201 |                 zero = (otp == 0)?1:0;
202 |                 overflow = 0;
203 |             end
204 |         2'b11: //slt
205 |             begin
206 |                 otp = (a<b)? 1:0;
207 |                 zero = (otp == 0)?1:0;
208 |                 overflow = 0;
209 |             end
210 |         endcase
211 |     end
212 | endmodule   
213 | 


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/sources/modules/Alu_Control.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module alu_control(
 4 |     input      [31:0] instruction,
 5 |     input      [2:0]  ALUOp,
 6 |     output reg [5:0]  ALUFn
 7 | );
 8 | 
 9 | always @(instruction or ALUOp)
10 | begin
11 |     if (ALUOp == 3'b010) begin
12 |         ALUFn <= instruction[5:0];
13 |     end else if (ALUOp == 3'b000) begin
14 |         ALUFn <= 6'b000000;
15 |     end else if (ALUOp == 3'b001) begin
16 |         ALUFn <= 6'b000001;
17 |     end else if (ALUOp == 3'b011)begin
18 |         ALUFn <= 6'b000000;
19 |     end else if (ALUOp == 3'b100)begin
20 |         ALUFn <= 6'b000100;
21 |     end else if (ALUOp == 3'b101)begin
22 |         ALUFn <= 6'b000110;
23 |     end else if (ALUOp == 3'b110)begin
24 |         ALUFn <= 6'b001011;
25 |     end
26 | end
27 | 
28 | endmodule
29 | 


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/sources/modules/BufferRegister.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module BufferRegister(
 4 |     input clk,
 5 | 	input clear,
 6 | 	input hold,
 7 | 	input wire [N-1:0] in,
 8 | 	output reg [N-1:0] out);
 9 | 
10 | 	parameter N = 1;
11 | 
12 | 	always @(posedge clk) begin
13 | 		if (clear)
14 | 			out <= {N{1'b0}};
15 | 		else if (hold)
16 | 			out <= out;
17 | 		else
18 | 			out <= in;
19 | 	end
20 | endmodule
21 | 


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/sources/modules/Control_Unit.v:
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 1 | `timescale 1ns / 1ps
 2 | 
 3 | module control_unit(
 4 |     input [31:0] instruction,
 5 |     output reg       RegDst,    // Destination for I and R type instruction
 6 |     output reg       ALUSrc,    // Decides between Register input to ALU and I Type add immediate
 7 |     output reg       MemToReg,  // Decides between SW and ALU output
 8 |     output reg       RegWrite,  // Write enable for Register File
 9 |     output reg       MemRead,   // Read from data memory
10 |     output reg       MemWrite,  // Write to data memory
11 |     output reg       Branch,    // 1 if instruction is beq and thus decides Program Counter
12 |     output reg [2:0] ALUOp,     // ALU Opcode
13 |     output reg       Jump       // 1 if insturction is J type
14 | 
15 | );
16 | 
17 | wire [5:0] opcode;
18 | assign opcode = instruction [31:26];
19 | reg [10:0]  controlSignals[63:0];
20 | 
21 | initial
22 | begin
23 |     controlSignals[6'b000000] = 11'b10010000100; // rtype
24 |     controlSignals[6'b010000] = 11'b01010000110; // addi
25 |     controlSignals[6'b010001] = 11'b01010001000; // andi
26 |     controlSignals[6'b010010] = 11'b01010001010; // xori
27 |     controlSignals[6'b010011] = 11'b00000010010; // beq
28 |     //controlSignals[6'b010100] = 11'b; //bne
29 |     controlSignals[6'b010101] = 11'b01111000000; // lw
30 |     controlSignals[6'b010110] = 11'b01001000000; // sw
31 |     controlSignals[6'b010111] = 11'b10010000100; // slt
32 |     controlSignals[6'b011000] = 11'b01010001100; // slti
33 |     controlSignals[6'b110000] = 11'b00000011111; // jump
34 | end
35 | 
36 | always @(instruction)
37 |     begin
38 |         RegDst   = controlSignals[opcode][10];
39 |         ALUSrc   = controlSignals[opcode][9];
40 |         MemToReg = controlSignals[opcode][8];
41 |         RegWrite = controlSignals[opcode][7];
42 |         MemWrite = controlSignals[opcode][6];
43 |         MemRead  = controlSignals[opcode][5];
44 |         Branch   = controlSignals[opcode][4];
45 |         ALUOp    = controlSignals[opcode][3:1];
46 |         Jump     = controlSignals[opcode][0];
47 | 
48 |     end
49 | endmodule
50 | 


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/sources/modules/InstructionMemoryModule.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module InstructionMemoryModule(
 4 |     input wire clk,
 5 |     input wire [31:0] address,
 6 |     input wire readEnable,
 7 |     input wire writeEnable,
 8 |     input wire [31:0] dataIn,
 9 |     output reg [31:0] dataOut
10 |     );
11 | reg [31:0] memory[8191:0];
12 | 
13 | initial 
14 | begin
15 |     // memory[0] <= 32'b11000000000000000000000000000010;//jump
16 |     // memory[0] <= 32'b01001100001000010000000000000001;// branch
17 |     //memory[1] <= 32'b01011000100000100000000000000001; //sw value of R2 in memory address in R4 
18 |     //memory[2] <= 32'b00000000001000100001100000000010;
19 |     
20 |     memory[0] <= 32'b00000000011000100000100000000000;
21 |     memory[1] <= 32'b00000000110001010010000000000000;
22 |     memory[2] <= 32'b00000000100000010000100000000001;
23 |     memory[3] <= 32'b01000000001000010000000001000000;
24 |     memory[4] <= 32'b01001100001000100000000000000011;
25 |     memory[5] <= 32'b01000000101001010000000000010000;
26 |     memory[6] <= 32'b00000000100001010010100000000001;
27 |     memory[7] <= 32'b00000000100000010000100000000000;
28 |     memory[8] <= 32'b00000001000000010001000000000001;
29 | end
30 | always @(address) 
31 |     begin
32 |     dataOut = memory[address]; 
33 |     $display("dataout - %b address- %d",dataOut,address); 
34 | end
35 | 
36 | 
37 | endmodule
38 | 


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/sources/modules/MainMemory.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module MainMemoryModule(
 4 |     input wire clk,
 5 |     input wire [31:0] address,
 6 |     input wire readEnable,
 7 |     input wire writeEnable,
 8 |     input wire [31:0] dataIn,
 9 |     output reg [31:0] dataOut
10 |     );
11 | reg [31:0] memory[1024*1024*1024*4-1:0];
12 | 
13 | always @(address) 
14 |     begin
15 |     memory[0] <= 32'b00000000001000100001100000000000;//ADD R1 and R2 Store in R3
16 |     //memory[0] <= 32'b01011000100000100000000000000001; //sw value of R2 in memory address in R4 
17 |     //  memory[8] <= 32'b00000000001000100001100000000000;
18 |     dataOut = memory[address];
19 |     // $display("address main memory - %b",address);
20 | end
21 | 
22 | always @(dataIn) 
23 |     begin
24 |     if(writeEnable & !readEnable) begin
25 |         memory[address] = dataIn;
26 |     end 
27 | end
28 | 
29 | endmodule
30 | 


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/sources/modules/ProgramCounter.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module ProgramCounter(
 4 |     input clk,
 5 |     input reset,
 6 |     input zero,
 7 |     input branch,
 8 |     input jump,
 9 |     input [25:0] jumpAddress,
10 |     input [15:0] branchOffset,
11 |     input [31:0] regAddress,
12 |     output reg [31:0] pc 
13 | );
14 |     wire [31:0] pcPlus4;
15 |     reg [1:0] pcControl;
16 |     initial
17 |     begin
18 |         pc <= 32'h00000000;
19 |     end
20 |     
21 |     assign pcPlus4 = pc + 1;
22 |     
23 |     always @(posedge clk)
24 |     begin
25 |         if(reset == 1)
26 |             pc <= 32'h00000000;
27 |         else
28 |         begin
29 |         pcControl = ( branch & zero == 1)? 2'b10: 2'b00;
30 |         pcControl = (jump)?2'b11:pcControl;
31 |         
32 |             case(pcControl)
33 |                 2'b00: pc <= pcPlus4;                                                       //Increment of program counter by 4
34 |                 2'b11: pc <= {pcPlus4[31:26],jumpAddress};                                  //Jump address calculation.
35 |                 2'b01: pc <= regAddress;                                                    //Initial address
36 |                 2'b10: pc <= pcPlus4 + {{14{branchOffset[15]}},branchOffset[15:0]};   //Branch address calculation.
37 |                 default: pc<= pcPlus4;
38 |             endcase
39 |         end
40 |         // $display("pc - %d clk -%d  reset- %d pcControl- %b",pc,clk,reset,pcControl);
41 |     end
42 | endmodule
43 | 


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/sources/modules/Register_File.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module Register_File(
 4 |         clk,
 5 |         read_addr1,
 6 |         read_addr2,
 7 |         read_data1,
 8 |         read_data2,
 9 |         write_addr,
10 |         write_data,
11 |         write_enable
12 |     );
13 | 
14 | /***************************
15 | ******** PARAMETERS ********
16 | ***************************/
17 | 
18 | input wire clk;
19 | 
20 | input wire [4:0]  read_addr1;
21 | input wire [4:0]  read_addr2;
22 | input wire [4:0]  write_addr;
23 | 
24 | input wire [31:0] write_data;
25 | input wire        write_enable;
26 | 
27 | output reg [31:0] read_data1;
28 | output reg [31:0] read_data2;
29 | 
30 | 
31 | // REGISTER FILE
32 | 
33 | reg [31:0] Register_File [31:0]; // 32 - 32 Bit Registers
34 | 
35 | 
36 | /*************************
37 | ********* LOGIC **********
38 | **************************/
39 | 
40 | 
41 | initial
42 | begin
43 |         Register_File[0]=32'h00000002;
44 |         Register_File[1]=32'h00000000;
45 |         Register_File[2]=32'h00000050;
46 |         Register_File[3]=32'h00000000;
47 |         Register_File[4]=32'h00000006;
48 |         Register_File[5]=32'h00000040;
49 |         Register_File[6]=32'h00000000;
50 |         Register_File[7]=32'h00000009;
51 |         Register_File[8]=32'h00000001;
52 | end
53 | 
54 | always @(read_addr1 or read_addr2)
55 |     begin
56 |     // $display("read_addr1 %d - read_addr2 -%d write_data -%h clk%b",read_addr1,read_addr2,write_data,clk);
57 |     read_data1 = 32'h00000000;
58 |     read_data2 = 32'h00000000;
59 |     if (read_addr1 != 5'b11111) begin
60 |         read_data1 = Register_File[read_addr1];
61 |     end 
62 |     if (read_addr2 != 5'b11111) begin
63 |         read_data2 = Register_File[read_addr2]; 
64 |     end
65 |     
66 |     end
67 | always @(negedge(clk))
68 |     begin
69 |     $display("write_addr- %d - write_enable -%d write_data -%h clk%b",write_addr,write_enable,write_data,clk);
70 |     if (write_enable) begin
71 |         if (write_addr != 5'b11111) begin
72 |             Register_File[write_addr] = write_data;   
73 |         end
74 |     end
75 |    end
76 | endmodule
77 | 


--------------------------------------------------------------------------------
/sources/modules/cpu.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | 
  3 | module cpu(
  4 |     input clk,
  5 |     input rst
  6 | );
  7 |     wire [31:0] alu_operand;
  8 |     wire [31:0] alu_otp;
  9 |     wire [31:0] pc_instaddr;
 10 |     wire [31:0] instruction;
 11 |     wire [31:0] sign_extend;
 12 |     wire [31:0] reg1data;
 13 |     wire [31:0] reg2data;
 14 |     wire [31:0] regwrdata;
 15 |     wire [31:0] data_mem_in;
 16 |     wire [31:0] data_mem_out;   
 17 |     wire [1:0]  pcControl;
 18 |     wire [2:0]  alu_op;
 19 |     wire [4:0]  reg_radd0;
 20 |     wire [4:0]  reg_radd1;
 21 |     wire [4:0]  reg_waddr;
 22 |     wire [5:0]  alu_control_otp;
 23 |     wire        reg_wr_add_control;
 24 |     wire        datamem_readen;
 25 |     wire        datawr_select;
 26 |     wire        datamemwriteen;
 27 |     wire        alusrcselect;
 28 |     wire        reg_wr_en;
 29 |     wire        branch_control;
 30 |     wire        jump_control;
 31 |     wire        alu_zero;
 32 |     wire        overflow_signal;
 33 | 
 34 |     
 35 |     ProgramCounter prcount (
 36 |         .clk(clk),
 37 |         .reset(rst),
 38 |         .zero(alu_zero),
 39 |         .branch(branch_control),
 40 |         .jump(jump_control),
 41 |         .jumpAddress(instruction[25:0]),
 42 |         .branchOffset(instruction[15:0]),
 43 |         .regAddress(reg1data),
 44 |         .pc(pc_instaddr)
 45 |     );
 46 |         
 47 |     InstructionMemoryModule instructionMemory(
 48 |         .clk(clk),
 49 |         .address(pc_instaddr),
 50 |         .readEnable(1'b1),
 51 |         .writeEnable(1'b0),
 52 |         .dataIn(32'h000000),
 53 |         .dataOut(instruction)
 54 |     );
 55 |         
 56 |     control_unit signals(
 57 |         .instruction(instruction),
 58 |         .RegDst(reg_wr_add_control),
 59 |         .MemRead(datamem_readen),
 60 |         .MemToReg(datawr_select),
 61 |         .ALUOp(alu_op),
 62 |         .MemWrite(datamemwriteen),
 63 |         .ALUSrc(alusrcselect),
 64 |         .RegWrite(reg_wr_en),
 65 |         .Branch(branch_control),
 66 |         .Jump(jump_control)
 67 |     );
 68 | 
 69 |     assign reg_radd0 = instruction[25:21];
 70 | 
 71 |     assign reg_radd1 = instruction[20:16];
 72 |     
 73 |     
 74 |     regmux2x1 reg_wr_dst(
 75 |         .select(reg_wr_add_control),
 76 |         .in0(reg_radd1),
 77 |         .in1(instruction[15:11]),
 78 |         .out(reg_waddr)
 79 |     );
 80 | 
 81 |     Register_File regfile(
 82 |         .clk(clk),
 83 |         .read_addr1(reg_radd0),
 84 |         .read_addr2(reg_radd1),
 85 |         .write_addr(reg_waddr),
 86 |         .write_data(regwrdata),
 87 |         .write_enable(reg_wr_en),
 88 |         .read_data1(reg1data),
 89 |         .read_data2(reg2data)
 90 |     );
 91 | 
 92 |     signExtension sign(
 93 |         .in(instruction[15:0]),
 94 |         .out(sign_extend)
 95 |     );
 96 | 
 97 |     mux2x1 alusrc_select(
 98 |         .select(alusrcselect),
 99 |         .in0(reg2data),
100 |         .in1(sign_extend),
101 |         .out(alu_operand)
102 |     );
103 |         
104 |     alu_control alucntrl(
105 |         .instruction(instruction),
106 |         .ALUOp(alu_op),
107 |         .ALUFn(alu_control_otp)
108 |     );
109 |         
110 |     ALU alu(
111 |         .clk(clk),
112 |         .a(reg1data),
113 |         .b(alu_operand),
114 |         .alufn(alu_control_otp),
115 |         .otp(alu_otp),
116 |         .zero(alu_zero),
117 |         .overflow(overflow_signal)
118 |     );
119 |  
120 |     MainMemoryModule data_mem(.clk(clk),
121 |         .address(alu_otp),
122 |         .readEnable(datamem_readen),
123 |         .writeEnable(datamemwriteen),
124 |         .dataIn(data_mem_in),
125 |         .dataOut(data_mem_out)
126 |     );
127 | 
128 |     mux2x1 write_select(.select(datawr_select),
129 |         .in1(data_mem_out),
130 |         .in0(alu_otp),
131 |         .out(regwrdata)
132 |     );
133 | 
134 |     
135 |     assign data_mem_in=reg2data;
136 |     always @(posedge clk)
137 |         begin
138 |             $display("reg_radd0- %d - reg_radd1 - %d",reg_radd0,reg_radd1);
139 |             $display("INSTRUCTION=%h - reg1data=%h - reg2data=%h  - alu_control_otp=%d - datamemwriteen=%d - data_mem_in=%d - alu_otp=%h",
140 |                 instruction, 
141 |                 reg1data, 
142 |                 reg2data,
143 |                 alu_control_otp,
144 |                 datamemwriteen,
145 |                 data_mem_in,
146 |                 alu_otp);
147 |         end
148 | endmodule
149 | 


--------------------------------------------------------------------------------
/sources/modules/mux2x1.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module mux2x1(in0, in1, select, out);
 4 |     input wire select;
 5 |     input wire [31:0] in0;
 6 |     input wire [31:0] in1;
 7 |     output wire[31:0] out;
 8 | 
 9 |     assign out = (select == 0) ? in0 : in1;
10 | 
11 | endmodule
12 | 


--------------------------------------------------------------------------------
/sources/modules/regmux2x1.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module regmux2x1(in0, in1, select, out);
 4 |     input wire select; 
 5 |     input wire [4:0] in0;
 6 |     input wire [4:0] in1;
 7 |     output reg[4:0] out;
 8 | 
 9 |     always @(*)
10 |     begin
11 |         if(select == 0)
12 |         begin
13 |             out <= in0;
14 |         end
15 |         else begin
16 |             out <= in1;
17 |         end
18 |     end
19 | 
20 | endmodule
21 | 


--------------------------------------------------------------------------------
/sources/modules/signExtension.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module signExtension(
 4 |     input [15:0] in,
 5 |     output [31:0] out
 6 | );
 7 | 
 8 | assign out = {{16{in[15]}},in[15:0]};
 9 | 
10 | endmodule
11 | 


--------------------------------------------------------------------------------
/sources/testbench/ALU_tb.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 26.09.2017 23:21:05
 7 | // Design Name: 
 8 | // Module Name: ALU_tb
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module ALU_tb;
24 |     reg [31:0] a;
25 |     reg [31:0] b;
26 |     reg [5:0] alufn;
27 |     wire [31:0] otp;
28 |     wire overflow;
29 |     wire zero;
30 |     
31 |     
32 |     ALU alu_inst_1(.a(a),.b(b),.alufn(alufn),.otp(otp),.overflow(overflow),.zero(zero));
33 |     
34 |     initial 
35 |         begin
36 |             //add
37 |             #100 
38 |             alufn = 6'b000000;     
39 |             a = 32'h00000001; 
40 |             b = 32'h00000001; 
41 |             //subtract
42 |             #100 
43 |             alufn = 6'b000001;     
44 |             a = 32'h00000013; 
45 |             b = 32'h00000002;
46 |             //multiply
47 |             #100 
48 |             alufn = 6'b000010;     
49 |             a = 32'h00000013; 
50 |             b = 32'h00000002;  
51 |             #100 //and
52 |             alufn = 6'b000100;     
53 |             a = 1; 
54 |             b = 0;
55 |             #100 //or
56 |             alufn = 6'b000101;     
57 |             a = 32'h00000001; 
58 |             b = 32'h00000000;    
59 |             #100 //xor
60 |             alufn = 6'b000110;     
61 |             a = 32'h00000001; 
62 |             b = 32'h00000000;  
63 |             #100 //shiftleft
64 |             alufn = 6'b001000;     
65 |             a = 32'h00000001; 
66 |             b = 32'h00000003; 
67 |             #100 //shiftright
68 |             alufn = 6'b001001;     
69 |             a = 32'h00000010; 
70 |             b = 32'h00000003;         
71 |         end
72 |     
73 | endmodule
74 | 


--------------------------------------------------------------------------------
/sources/testbench/Register_File_tb.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 28.09.2017 02:17:25
 7 | // Design Name: 
 8 | // Module Name: Register_File_tb
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module Register_File_tb;
24 | 
25 | reg clk;
26 | 
27 | reg [4:0]  read_addr1;
28 | reg [4:0]  read_addr2;
29 | reg [4:0]  write_addr;
30 | 
31 | reg [31:0] write_data;
32 | reg        write_enable;
33 | 
34 | wire [31:0] read_data1;
35 | wire [31:0] read_data2;
36 | 
37 | Register_File regfile(
38 |         .clk(clk),
39 |         .read_addr1(read_addr1),
40 |         .read_addr2(read_addr2),
41 |         .read_data1(read_data1),
42 |         .read_data2(read_data1),
43 |         .write_addr(write_addr),
44 |         .write_data(write_data),
45 |         .write_enable(write_enable)
46 |     );
47 | integer i = 0;
48 | initial
49 |     begin
50 |         clk = 0; 
51 |         read_addr1 = 5'h00000;
52 |         read_addr2 = 5'h00000;
53 |         write_enable = 1;
54 |         for(i=0;i<32;i=i+1)begin
55 |             write_addr = $realtobits(i);
56 |             write_data = 5'h00001;
57 |             #5 clk = ~clk;
58 |             #5 clk = ~clk;    
59 |         end
60 |     end
61 | always begin
62 | #10
63 |     read_addr1 = 5'h00002;
64 |     read_addr2 = 5'h00300;
65 |     write_enable = 0;
66 |     #5 clk = ~clk;
67 |     #5 clk = ~clk;
68 | #10 
69 |     read_addr1 = 5'h00000;
70 |     read_addr2 = 5'h00000;
71 |     write_enable = 1;
72 |     write_addr = 5'h00010;
73 |     write_data = 5'h00100;
74 |     #5 clk = ~clk;
75 |     #5 clk = ~clk;    
76 | #10
77 |     read_addr1 = 5'h00010;
78 |     read_addr2 = 5'h00300;
79 |     write_enable = 0;
80 |     #5 clk = ~clk;
81 |     #5 clk = ~clk;
82 | end
83 | endmodule
84 | 


--------------------------------------------------------------------------------
/sources/testbench/cpu_tb.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module cpu_tb;
 4 | reg clk;
 5 | reg rst;
 6 | cpu uut(.clk(clk),
 7 | .rst(rst));
 8 | 
 9 |    always begin 
10 | 		#50 clk = ~clk;
11 | 	end 
12 | 	initial
13 | 	begin
14 | 	
15 | 		clk    = 1'b0      ; // time = 0 
16 | 	    rst    = 1'b1;
17 | 		#60 rst    = 1'b0;                
18 |     end
19 | endmodule


--------------------------------------------------------------------------------
/utils/ISA.md:
--------------------------------------------------------------------------------
 1 | # ISA
 2 | 
 3 | OPCODES | Opcode-Repr | Description
 4 | ------- | ----------  | -----------
 5 | ADD     | 000000      | Add content of two register and store it in third register
 6 | SUB     | 000000      | Subract the contents of second register from first register and store it in third register
 7 | MUL     | 000000      | Multiply the content of two register and store it in third register
 8 | AND     | 000000      | Bitwise AND two register and strore in third register.
 9 | OR      | 000000      | Bitwise OR two 32-bit register and store in third register.
10 | XOR     | 000000      | Bitwise XOR the contents of two register and store in third.
11 | SLL     | 000000      | Shift the register content bitwise left logically by a given amount and store in a register.
12 | SRL     | 000000      | Shift register content bitwise right logically by a given amount and store in a register.
13 | ADDI    | 010000      | Add the contents of register with an immediate constant value and store in a register.
14 | ANDI    | 010001      | Bitwise logically **and** the content of a register with a constant immediate.
15 | XORI    | 010010      | Bitwise logically **xor** the content of a register with a constant immediate.
16 | BEQ     | 010011      | Update the Program counter to branch address relative to PC when the register content are equal.
17 | LW      | 010100      | Load a word from memory location specified in the instruction into a register.
18 | SW      | 010101      | Store the contents of a register into data memory at the location specified in the instruciton.
19 | SLT     | 010110      | Set the contents of a register to zero comparing the other two register(Set to zero if first is less than second register).
20 | SLTI    | 010111      | Set the contents of a register to zero if content of other register is less than the immediate value specified in the instruction.
21 | JMP     | 110000      | Jump to address specified in the instruction(Update program counter to the specified address).
22 | 


--------------------------------------------------------------------------------
/utils/assembler.py:
--------------------------------------------------------------------------------
  1 | #!/usr/bin/python
  2 | 
  3 | """
  4 | A simple python script to convert the desired MIPS code to binary to be run for the implementation
  5 | The Syntax for writing the program is as follows:
  6 | 
  7 | 1. Comments
  8 |     For now only single line comments have been implemented, comment using (//)
  9 | 2. Registers
 10 |     To select a register use $r[register_no] as $r13
 11 | 3. Syntax for statement
 12 |     Each statement must be terminated using semicolon(;)
 13 |     Arguments to an opcode must be comma seperated
 14 |     Eg. ADD $r1, $r2, $r3
 15 |     The syntax follow Intel assembly implementation that is
 16 |     OPCODE [Destination] [Source1] [Source2]
 17 | """
 18 | 
 19 | import sys
 20 | import re
 21 | import argparse
 22 | import os
 23 | 
 24 | """
 25 | RTYPE_FUNCTION_FIELD maps opcodes for an R-Type instruction to function fields
 26 | OPCODE_MAPPING maps opcodes to their binary values
 27 | """
 28 | 
 29 | RTYPE_FUNCTION_FIELD = {
 30 |     "ADD" : '000000',
 31 |     "SUB" : '000001',
 32 |     "MUL" : '000010',
 33 |     "AND" : '000100',
 34 |     "OR"  : '000101',
 35 |     "XOR" : '000110',
 36 |     "SLL" : '001000',
 37 |     "SRL" : '001001',
 38 | }
 39 | 
 40 | OPCODE_MAPPING = {
 41 |     "ADDI": '010000',
 42 |     "ANDI": '010001',
 43 |     "XORI": '010010',
 44 |     "BEQ" : '010011',
 45 |     "LW"  : '010100',
 46 |     "SW"  : '010101',
 47 |     "SLT" : '010110',
 48 |     "SLTI": '010111'
 49 | }
 50 | 
 51 | labelTable = {}
 52 | 
 53 | def enum(**enums):
 54 |     return type('Enum', (), enums)
 55 | 
 56 | # Defines error_codes
 57 | Errors = enum(INVALID_OPCODE=0, INVALID_SYNTAX=1)
 58 | 
 59 | def handleError(error_code, instruction):
 60 |     if (error_code == Errors.INVALID_OPCODE):
 61 |         print "[-] Invalid OPCODE : " + str(instruction)
 62 |     elif (error_code == Errors.INVALID_SYNTAX):
 63 |         print "[-] Invalid Instruction syntax: " + str(instruction)
 64 |     raise SystemExit()
 65 | 
 66 | def stripComments(content):
 67 |     """
 68 |     Removes comments from program content 
 69 |     Syntax assumes that the comments start with // and only single line commenting exists
 70 |     removes everything after // character until a new-line character is found
 71 |     """
 72 |     return re.sub(r'//[^\n]*', '', content)
 73 | 
 74 | def stripContent(content):
 75 |     """
 76 |     Removes unnecessery newline characters and spaces from the content provided
 77 |     Syntax of writing assumes that each instruction ends with a ;(semicolon)
 78 |     """
 79 |     
 80 |     uncommentedContent = stripComments(content)
 81 |     return re.sub(r'[ \t]+', ' ', re.sub(r'\n', '', uncommentedContent))
 82 | 
 83 | def getLabelOffset(label, addr):
 84 |     return labelTable[label] - int(addr)
 85 | 
 86 | def addToLabelTable(instructionArr):
 87 |     currAddr = 0
 88 |     for instruction in instructionArr:
 89 |         if instruction[0] == ":":
 90 |             labelTable[instruction[1:]] = currAddr
 91 |         currAddr += 1
 92 | 
 93 | def getIntegerValue(value):
 94 |     if value[0:2] == "0x":
 95 |         return int(value[2:], 16)
 96 |     else:
 97 |         return int(value)
 98 | 
 99 | 
100 | def convertInstruction(instruction, addr):
101 |     """
102 |     Instruction in MIPS implementation can be catagorized into three catagories
103 |     1. R-Type instruction : OPCODE Rd, Rs, Rt 
104 |     2. I-Type instruction : OPCODE Rd, Rs, [16-bit value]
105 |     A register in instruction starts with $ as in ADD $r1 $r2 $r3
106 |     """
107 | 
108 |     compArr = re.split(r', |,| ', instruction)
109 |     instructionOpcode = compArr[0].upper()
110 |     regUsedNo = instruction.count('$')
111 | 
112 |     if len(compArr) == 4 and regUsedNo == 3:
113 |         # Instruction is an R-type instruction
114 |         if instructionOpcode in RTYPE_FUNCTION_FIELD:
115 |             opcode = '0'*6
116 |             shiftAmt = '0'*5
117 |             fnField = RTYPE_FUNCTION_FIELD[instructionOpcode]
118 |             r1 = '{0:05b}'.format(int(compArr[1][2:])) # Rd
119 |             r2 = '{0:05b}'.format(int(compArr[2][2:])) # Rt
120 |             r3 = '{0:05b}'.format(int(compArr[3][2:])) # Rs
121 |             return opcode + r3 + r2 + r1 + shiftAmt + fnField
122 |         else:
123 |             handleError(0, instruction)
124 | 
125 |     elif len(compArr) == 4 and regUsedNo == 2:
126 |         # Instrution is an I-Type instruction
127 |         if instructionOpcode in OPCODE_MAPPING:
128 |             r1 = '{0:05b}'.format(int(compArr[1][2:])) # Rt
129 |             r2 = '{0:05b}'.format(int(compArr[2][2:])) # Rs
130 |             opcode = OPCODE_MAPPING[instructionOpcode]
131 |             if instructionOpcode == "BEQ":
132 |                 # Third argument is a label
133 |                 branchOffset = '{0:016b}'.format(getLabelOffset(compArr[3], addr))
134 |                 return opcode + r1 + r2 + branchOffset
135 |             else:
136 |                 imm = '{0:016b}'.format(getIntegerValue(compArr[3]))
137 |                 return opcode + r1 + r2 + imm
138 |         else:
139 |             handleError(0, instruction)
140 |     else:
141 |         handleError(1, instruction)
142 | 
143 | def writeAssembledCode(instrArr, filePath, verilogMemory):
144 |     newFilePath = filePath + '.bin'
145 |     if verilogMemory:
146 |         binarySeqVerilog = ''
147 |         i = 0
148 |         for instr in instrArr:
149 |             binarySeqVerilog += 'memory[%d] <= %s;\n' % (i, instr)
150 |             i += 1
151 |         open(newFilePath, 'w').write(binarySeqVerilog)
152 |     else:
153 |         open(newFilePath, 'w').write('\n'.join(instrArr))  
154 | 
155 | def main(filePath, verilogMemory):
156 |     with open(filePath, "r") as program:
157 |         content = program.read()
158 |         strippedContent = stripContent(content)
159 |         instructionArr = strippedContent.split(';')[:-1]
160 |         currAddr = 0
161 |         addToLabelTable(instructionArr)
162 |         assembledInstr = []
163 |         # Instruction array can conatin a label that begins with : used for branching
164 |         # LabelTable is used to store these label and address corresponding to that
165 |         for instruction in instructionArr:
166 |             if instruction[0] != ':':
167 |                 bitStreamInstruction = convertInstruction(instruction, currAddr)
168 |                 print instruction, " : ", bitStreamInstruction
169 |                 assembledInstr.append(bitStreamInstruction)
170 |             currAddr += 1
171 |     writeAssembledCode(assembledInstr, filePath, verilogMemory)
172 | 
173 | 
174 | if __name__ == "__main__":
175 |     parser = argparse.ArgumentParser()
176 |     parser.add_argument("-f",
177 |                         "--file",
178 |                         help="[*] Path of the file to be interpreted")
179 |     parser.add_argument("-m",
180 |                         "--verilogmemory",
181 |                         help="[*] Save the binary code to file as verilog memory array decleration",
182 |                         action="store_true")
183 |     args = parser.parse_args()
184 |     filePath = ""
185 |     try:
186 |         os.stat(args.file)
187 |         filePath = args.file
188 |     except:
189 |         try:
190 |             filePath = os.path.join(os.getcwd(), args.file)
191 |             os.stat(filePath)
192 |         except:
193 |             print "[-] The file path provided is not valid"
194 |             raise SystemExit()
195 |     main(filePath, args.verilogmemory)
196 | 


--------------------------------------------------------------------------------
/utils/test_code:
--------------------------------------------------------------------------------
 1 | :main;
 2 | ADD $r1, $r2, $r3;
 3 | ADD $r4, $r5, $r6;
 4 | SUB $r1, $r1, $r4;
 5 | ADDI $r1, $r1, 0x40;
 6 | BEQ $r1, $r2, branch;
 7 | ADDI $r5, $r5, 0x10;
 8 | SUB $r5, $r5, $r4;
 9 | 
10 | :branch;
11 | ADD $r1, $r1, $r4;
12 | SUB $r2, $r1, $r8;
13 | 


--------------------------------------------------------------------------------
/utils/test_code.bin:
--------------------------------------------------------------------------------
 1 | memory[0] <= 00000000011000100000100000000000;
 2 | memory[1] <= 00000000110001010010000000000000;
 3 | memory[2] <= 00000000100000010000100000000001;
 4 | memory[3] <= 01000000001000010000000001000000;
 5 | memory[4] <= 01001100001000100000000000000011;
 6 | memory[5] <= 01000000101001010000000000010000;
 7 | memory[6] <= 00000000100001010010100000000001;
 8 | memory[7] <= 00000000100000010000100000000000;
 9 | memory[8] <= 00000001000000010001000000000001;
10 | 


--------------------------------------------------------------------------------