├── AddressDecoder.v
├── AsyncCounter.v
├── CONTRIBUTING.md
├── Counter4Bit.v
├── D-FlipFlop.v
├── D-FlipFlopEnable.v
├── Finite_State_Machines
└── 110_Sequence_Detector
│ ├── FiniteStateMachine.v
│ ├── State diagram.drawio
│ ├── State_Diagram.PNG
│ └── State_Table.PNG
├── FourBit2To1Mux.v
├── FourBitShiftRegister.v
├── FullAdder.v
├── Gated-D-Latch.v
├── LICENSE
├── Mux7To1.v
├── ParallelLoadShiftRegister.v
├── ParametricRegister.v
├── ParamtericCounter.v
├── README.md
├── RippleCarryAdder.v
├── SevenSegmentDisplay.v
├── Supporting files
├── DE1_SoC.qsf
├── fakefpga.vpi
├── run_sim.bat
└── tb.v
├── T-FlipFlop.v
├── justModules.v
├── main.v
├── mux4to1.v
├── registers.v
└── schematics
├── Neg_edge_D_flipflop.PNG
├── Pos_edge_D_flipflop.PNG
├── T-Latch.circ
├── T_FlipFlop.PNG
├── d_latch.PNG
├── eight_bit_register.PNG
├── meme.jpg
├── rs_latch.PNG
├── shift_registers.PNG
└── verliog_meme.png
/AddressDecoder.v:
--------------------------------------------------------------------------------
1 | // Truth Table
2 |
3 | // A | B | C || S | T | U | V | W | X | Y | Z
4 | // 0 0 0 || 1 0 0 0 0 0 0 0
5 | // 0 0 1 || 0 1 0 0 0 0 0 0
6 | // 0 1 0 || 0 0 1 0 0 0 0 0
7 | // 0 1 1 || 0 0 0 1 0 0 0 0
8 | // 1 0 0 || 0 0 0 0 1 0 0 0
9 | // 1 0 1 || 0 0 0 0 0 1 0 0
10 | // 1 1 0 || 0 0 0 0 0 0 1 0
11 | // 1 1 1 || 0 0 0 0 0 0 0 1
12 |
13 | // This is an address decoder for a memory matrix with eight (2^3) rows
14 | // The outputs are in One-Hot encoded format as that's how a address decoder works
15 |
16 | `timescale 1ns / 1ps
17 | `default_nettype none
18 |
19 | // DE1_SoC board needs the below main module
20 |
21 | module main (
22 | input wire CLOCK_50, //On Board 50 MHz
23 | input wire [9:0] SW, // On board Switches
24 | input wire [3:0] KEY, // On board push buttons
25 | output wire [6:0] HEX0, // HEX displays
26 | output wire [6:0] HEX1,
27 | output wire [6:0] HEX2,
28 | output wire [6:0] HEX3,
29 | output wire [6:0] HEX4,
30 | output wire [6:0] HEX5,
31 | output wire [9:0] LEDR, // LEDs
32 | output wire [7:0] x, // VGA pixel coordinates
33 | output wire [6:0] y,
34 | output wire [2:0] colour, // VGA pixel colour (0-7)
35 | output wire plot, // Pixel drawn when this is pulsed
36 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
37 | );
38 | top u1(SW, LEDR);
39 |
40 | endmodule
41 |
42 | module top(SW, LEDR);
43 | input [9:0] SW;
44 | output [9:0] LEDR;
45 |
46 | address_decoder v1 (SW[2:0], LEDR[7:0]);
47 |
48 | endmodule
49 |
50 | module address_decoder (inp, row);
51 | input [2:0] inp;
52 | output reg [7:0] row;
53 |
54 | always@(*)
55 | begin
56 | row = 8'b00000000;
57 | case (inp)
58 | 3'b000 : row[0] = 1;
59 | 3'b001 : row[1] = 1;
60 | 3'b010 : row[2] = 1;
61 | 3'b011 : row[3] = 1;
62 | 3'b100 : row[4] = 1;
63 | 3'b101 : row[5] = 1;
64 | 3'b110 : row[6] = 1;
65 | 3'b111 : row[7] = 1;
66 | default row = 8'b0;
67 | endcase
68 | end
69 | endmodule
70 |
--------------------------------------------------------------------------------
/AsyncCounter.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module
5 |
6 | module main (
7 | input wire CLOCK_50, //On Board 50 MHz
8 | input wire [9:0] SW, // On board Switches
9 | input wire [3:0] KEY, // On board push buttons
10 | output wire [6:0] HEX0, // HEX displays
11 | output wire [6:0] HEX1,
12 | output wire [6:0] HEX2,
13 | output wire [6:0] HEX3,
14 | output wire [6:0] HEX4,
15 | output wire [6:0] HEX5,
16 | output wire [9:0] LEDR, // LEDs
17 | output wire [7:0] x, // VGA pixel coordinates
18 | output wire [6:0] y,
19 | output wire [2:0] colour, // VGA pixel colour (0-7)
20 | output wire plot, // Pixel drawn when this is pulsed
21 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
22 | );
23 | async_counter_top u1(SW[8], SW[9], SW[7], LEDR[2:0]);
24 |
25 | endmodule
26 |
27 | module async_counter_top(enable, clock, resetp, q);
28 | input enable, clock, resetp;
29 | output [2:0] q;
30 | wire [2:0] c ;
31 |
32 | t_flipflop v1 (enable, resetp, clock, c[0]);
33 | t_flipflop v2 (enable, resetp, ~c[0], c[1]);
34 | t_flipflop v3 (enable, resetp, ~c[1], c[2]);
35 |
36 | assign q = c;
37 | endmodule
38 |
39 | module t_flipflop(t, resetp, clock, q);
40 | input clock, t, resetp;
41 | output reg q;
42 |
43 | always@(posedge clock, posedge resetp)
44 | begin
45 | if (resetp)
46 | q <= 0;
47 | else if (t == 1)
48 | q <= ~q;
49 | end
50 |
51 | endmodule
52 |
--------------------------------------------------------------------------------
/CONTRIBUTING.md:
--------------------------------------------------------------------------------
1 | ## **Here we gather ECE241 resources for upcoming and current ECE241 batch at the University of Toronto!**
2 |
3 | ### Let's Contribute :+1:
4 | - **Step 1** - Fork this repository.
5 | - **Step 2** - Clone the repository to your local machine.
6 | - **Step 3** - Resolve the bugs, mentions provided in the Issues section of the repository OR Add new verilog code for non-existing modules. *Also add a description of what changes you have made*.
7 | - **Step 4** - Add the changes to your repository.
8 | - **Step 5** - Create a PULL Request. And that's all.
9 |
10 | **NOTE** - Please follow the camel case format for file name with first letter capitalized e.g. NewVerilogFile.v
11 | **NOTE** - All schematics go in the schematics directory
12 | **NOTE** - Currently there is no modelsim directory, so if you want to add a modelsim file (.do or simulation snapshot) make a new directory
13 |
14 | ### What you can contribute in this repo? :punch:
15 | - You can add your new **verilog modules**.
16 | - You can add **Modelsim** simulation files and/or snippets
17 | - You can add **Logisim** schematics or .circ files
18 | - You can contribute some **Learning Resources** in the ***Readme.md*** File.
19 | - You can modify previous solutions if you feel like your codes has **better placement and/or timing advantage**.
20 | - You **MUST NOT** add .exe (executable files) as they may posses security threats.
21 |
22 |
23 | ##### Let's Contribute For The Furture Batches of ECE 241 :smiley:
24 |
--------------------------------------------------------------------------------
/Counter4Bit.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module
5 |
6 | module main (
7 | input wire CLOCK_50, //On Board 50 MHz
8 | input wire [9:0] SW, // On board Switches
9 | input wire [3:0] KEY, // On board push buttons
10 | output wire [6:0] HEX0, // HEX displays
11 | output wire [6:0] HEX1,
12 | output wire [6:0] HEX2,
13 | output wire [6:0] HEX3,
14 | output wire [6:0] HEX4,
15 | output wire [6:0] HEX5,
16 | output wire [9:0] LEDR, // LEDs
17 | output wire [7:0] x, // VGA pixel coordinates
18 | output wire [6:0] y,
19 | output wire [2:0] colour, // VGA pixel colour (0-7)
20 | output wire plot, // Pixel drawn when this is pulsed
21 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
22 | );
23 | top v1(SW, LEDR);
24 |
25 | endmodule
26 |
27 | // Top Module
28 |
29 | module top(SW, LEDR);
30 | input [9:0] SW;
31 | output [9:0] LEDR;
32 |
33 | counter_4_bit u1 (SW[9], SW[0], SW[8], LEDR[3:0]);
34 |
35 | endmodule
36 |
37 | module counter_4_bit (clock, enable, resetp, q); // Active high - synchronous
38 | input clock, enable, resetp;
39 | output reg [3:0] q;
40 |
41 | always@(posedge clock)
42 | begin
43 | if (resetp == 1)
44 | q <= 0;
45 | else if (enable == 1)
46 | q <= q + 1;
47 | end
48 | endmodule
49 |
--------------------------------------------------------------------------------
/D-FlipFlop.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | module main (
5 | input wire CLOCK_50, //On Board 50 MHz
6 | input wire [9:0] SW, // On board Switches
7 | input wire [3:0] KEY, // On board push buttons
8 | output wire [6:0] HEX0, // HEX displays
9 | output wire [6:0] HEX1,
10 | output wire [6:0] HEX2,
11 | output wire [6:0] HEX3,
12 | output wire [6:0] HEX4,
13 | output wire [6:0] HEX5,
14 | output wire [9:0] LEDR, // LEDs
15 | output wire [7:0] x, // VGA pixel coordinates
16 | output wire [6:0] y,
17 | output wire [2:0] colour, // VGA pixel colour (0-7)
18 | output wire plot, // Pixel drawn when this is pulsed
19 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
20 | );
21 | top v1(SW, LEDR);
22 |
23 | endmodule
24 |
25 | // Top module
26 |
27 | module top (SW, LEDR); // NOTE: Uncomment the module you wanna use :)
28 | input[9:0] SW;
29 | output[9:0] LEDR;
30 |
31 | // Sync modules
32 | pos_edge_sync_active_high u1 (SW[0], SW[9], SW[1], LEDR[0]);
33 | // pos_edge_sync_active_low u1 (SW[0], SW[9], SW[1], LEDR[0]);
34 | // neg_edge_sync_active_high u1 (SW[0], SW[9], SW[1], LEDR[0]);
35 | // neg_edge_sync_active_low u1 (SW[0], SW[9], SW[1], LEDR[0]);
36 |
37 | // Async modules
38 | // pos_edge_async_active_high u1 (SW[0], SW[9], SW[1], LEDR[0]);
39 | // pos_edge_async_active_low u1 (SW[0], SW[9], SW[1], LEDR[0]);
40 | // neg_edge_async_active_high u1 (SW[0], SW[9], SW[1], LEDR[0]);
41 | // neg_edge_async_active_low u1 (SW[0], SW[9], SW[1], LEDR[0]);
42 |
43 | endmodule
44 |
45 |
46 | // Sync modules
47 |
48 | module pos_edge_sync_active_high(d, clock, reset, q);
49 | input d, clock, reset;
50 | output reg q;
51 | always@(posedge clock) // edge triggered devices
52 | begin
53 | if (reset == 1)
54 | q <= 0; // Non-blocking statements
55 | else
56 | q <= d;
57 | end
58 | endmodule
59 |
60 | module pos_edge_sync_active_low(d, clock, reset, q);
61 | input d, clock, reset;
62 | output reg q;
63 | always@(posedge clock) // edge triggered devices
64 | begin
65 | if (reset == 0)
66 | q <= 0; // Non-blocking statements
67 | else
68 | q <= d;
69 | end
70 | endmodule
71 |
72 | module neg_edge_sync_active_high(d, clock, reset, q);
73 | input d, clock, reset;
74 | output reg q;
75 | always@(negedge clock) // edge triggered devices
76 | begin
77 | if (reset == 1)
78 | q <= 0; // Non-blocking statements
79 | else
80 | q <= d;
81 | end
82 | endmodule
83 |
84 | module neg_edge_sync_active_low(d, clock, reset, q);
85 | input d, clock, reset;
86 | output reg q;
87 | always@(negedge clock) // edge triggered devices
88 | begin
89 | if (reset == 0)
90 | q <= 0; // Non-blocking statements
91 | else
92 | q <= d;
93 | end
94 | endmodule
95 |
96 | // Async modules
97 |
98 | module pos_edge_async_active_high(d, clock, reset, q);
99 | input d, clock, reset;
100 | output reg q;
101 | always@(posedge clock, posedge reset) // edge triggered devices
102 | begin
103 | if (reset == 1)
104 | q <= 0; // Non-blocking statements
105 | else
106 | q <= d;
107 | end
108 | endmodule
109 |
110 | module pos_edge_async_active_low(d, clock, reset, q);
111 | input d, clock, reset;
112 | output reg q;
113 | always@(posedge clock, negedge reset) // edge triggered devices
114 | begin
115 | if (reset == 0)
116 | q <= 0; // Non-blocking statements
117 | else
118 | q <= d;
119 | end
120 | endmodule
121 |
122 | module neg_edge_async_active_high(d, clock, reset, q);
123 | input d, clock, reset;
124 | output reg q;
125 | always@(negedge clock, posedge reset) // edge triggered devices
126 | begin
127 | if (reset == 1)
128 | q <= 0; // Non-blocking statements
129 | else
130 | q <= d;
131 | end
132 | endmodule
133 |
134 | module neg_edge_async_active_low(d, clock, reset, q);
135 | input d, clock, reset;
136 | output reg q;
137 | always@(negedge clock, negedge reset) // edge triggered devices
138 | begin
139 | if (reset == 0)
140 | q <= 0; // Non-blocking statements
141 | else
142 | q <= d;
143 | end
144 | endmodule
145 |
--------------------------------------------------------------------------------
/D-FlipFlopEnable.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module
5 |
6 | module main (
7 | input wire CLOCK_50, //On Board 50 MHz
8 | input wire [9:0] SW, // On board Switches
9 | input wire [3:0] KEY, // On board push buttons
10 | output wire [6:0] HEX0, // HEX displays
11 | output wire [6:0] HEX1,
12 | output wire [6:0] HEX2,
13 | output wire [6:0] HEX3,
14 | output wire [6:0] HEX4,
15 | output wire [6:0] HEX5,
16 | output wire [9:0] LEDR, // LEDs
17 | output wire [7:0] x, // VGA pixel coordinates
18 | output wire [6:0] y,
19 | output wire [2:0] colour, // VGA pixel colour (0-7)
20 | output wire plot, // Pixel drawn when this is pulsed
21 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
22 | );
23 | top v1(SW, LEDR);
24 |
25 | endmodule
26 |
27 | // Top Module
28 |
29 | module top(SW, LEDR);
30 | input [9:0] SW;
31 | output [9:0] LEDR;
32 |
33 | d_flipflop_enable u1 (SW[0], SW[9], SW[8], SW[1], LEDR[0]);
34 |
35 | endmodule
36 |
37 | // D Flip Flop with enable
38 |
39 | module d_flipflop_enable(d, clock, enable, resetn, q);
40 | input d, clock, resetn, enable;
41 | output reg q;
42 |
43 | always@(negedge clock)
44 | begin
45 | if (resetn == 0)
46 | q <= 0;
47 | else if (enable == 1)
48 | q <= d;
49 | end
50 | endmodule
51 |
--------------------------------------------------------------------------------
/Finite_State_Machines/110_Sequence_Detector/FiniteStateMachine.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module
5 |
6 | module main (
7 | input wire CLOCK_50, //On Board 50 MHz
8 | input wire [9:0] SW, // On board Switches
9 | input wire [3:0] KEY, // On board push buttons
10 | output wire [6:0] HEX0, // HEX displays
11 | output wire [6:0] HEX1,
12 | output wire [6:0] HEX2,
13 | output wire [6:0] HEX3,
14 | output wire [6:0] HEX4,
15 | output wire [6:0] HEX5,
16 | output wire [9:0] LEDR, // LEDs
17 | output wire [7:0] x, // VGA pixel coordinates
18 | output wire [6:0] y,
19 | output wire [2:0] colour, // VGA pixel colour (0-7)
20 | output wire plot, // Pixel drawn when this is pulsed
21 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
22 | );
23 | top u1(SW, LEDR);
24 |
25 | endmodule
26 |
27 | // Top level module
28 |
29 | module top(SW, LEDR);
30 | input [9:0] SW;
31 | output [9:0] LEDR;
32 |
33 | seq110_detector v1 (SW[9], SW[8], SW[0], LEDR[0]);
34 |
35 | endmodule
36 |
37 | module seq110_detector(clock, resetp, w, z); // Finite state machine for detecting 110 sequence
38 | parameter [1:0] a = 2'b00, b = 2'b01, c = 2'b10, d = 2'b11;
39 | input clock, resetp, w;
40 | reg [1:0] y, Y;
41 | output z;
42 |
43 | // Initial combinational block
44 | always@(posedge clock)
45 | case (y)
46 | a: if (!w) Y = a;
47 | else Y = b;
48 | b: if (!w) Y = a;
49 | else Y = c;
50 | c: if (!w) Y = d;
51 | else Y = c;
52 | d: if (!w) Y = a;
53 | else Y = b;
54 | default: Y = a; // Default is reset state
55 | endcase
56 |
57 | // State Flip Flop implementing active high reset
58 | always@(posedge clock)
59 | begin
60 | if (resetp == 1)
61 | y <= a;
62 | else
63 | y <= Y;
64 | end
65 |
66 | // Output combinational logic block
67 | assign z = (y == d);
68 |
69 | endmodule
70 |
--------------------------------------------------------------------------------
/Finite_State_Machines/110_Sequence_Detector/State diagram.drawio:
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/Finite_State_Machines/110_Sequence_Detector/State_Diagram.PNG:
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https://raw.githubusercontent.com/pandyah5/ECE241_Verilog/3a9fbf8ac07ef824b697d1f8d09a00c68e13f200/Finite_State_Machines/110_Sequence_Detector/State_Diagram.PNG
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/Finite_State_Machines/110_Sequence_Detector/State_Table.PNG:
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https://raw.githubusercontent.com/pandyah5/ECE241_Verilog/3a9fbf8ac07ef824b697d1f8d09a00c68e13f200/Finite_State_Machines/110_Sequence_Detector/State_Table.PNG
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/FourBit2To1Mux.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | module main (
5 | input wire CLOCK_50, //On Board 50 MHz
6 | input wire [9:0] SW, // On board Switches
7 | input wire [3:0] KEY, // On board push buttons
8 | output wire [6:0] HEX0, // HEX displays
9 | output wire [6:0] HEX1,
10 | output wire [6:0] HEX2,
11 | output wire [6:0] HEX3,
12 | output wire [6:0] HEX4,
13 | output wire [6:0] HEX5,
14 | output wire [9:0] LEDR, // LEDs
15 | output wire [7:0] x, // VGA pixel coordinates
16 | output wire [6:0] y,
17 | output wire [2:0] colour, // VGA pixel colour (0-7)
18 | output wire plot, // Pixel drawn when this is pulsed
19 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
20 | );
21 | fourBit_mux2to1 u0(.X(SW[3:0]), .Y(SW[7:4]), .Z(LEDR[3:0]), .S(SW[9]));
22 |
23 | endmodule
24 |
25 | //Write code in here!
26 |
27 | module mux2to1(a, b, Y, S);
28 | // Declaring inputs and outputs
29 | input a, b;
30 | input S;
31 | output Y;
32 |
33 | // assign Y = S?b:a;
34 | assign Y = (~S & a)|(S & b);
35 |
36 | endmodule
37 |
38 | module fourBit_mux2to1 (X, Y, S, Z);
39 | input[3:0] X, Y;
40 | input S;
41 | output[3:0] Z;
42 |
43 | mux2to1 u1(.a(X[0]), .b(Y[0]), .Y(Z[0]), .S(S));
44 | mux2to1 u2(.a(X[1]), .b(Y[1]), .Y(Z[1]), .S(S));
45 | mux2to1 u3(.a(X[2]), .b(Y[2]), .Y(Z[2]), .S(S));
46 | mux2to1 u4(.a(X[3]), .b(Y[3]), .Y(Z[3]), .S(S));
47 |
48 | endmodule
49 |
--------------------------------------------------------------------------------
/FourBitShiftRegister.v:
--------------------------------------------------------------------------------
1 | module four_bit_shift_register(w, clock, q);
2 | input w, clock;
3 | output reg[3:0] q;
4 | always@(posedge clock)
5 | begin
6 | q[0] <= w; // Non-blocking statements make this type of assignment possible
7 | q[1] <= q[0];
8 | q[2] <= q[1];
9 | q[3] <= q[2];
10 | end
11 | endmodule
12 |
--------------------------------------------------------------------------------
/FullAdder.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | module main (
5 | input wire CLOCK_50, //On Board 50 MHz
6 | input wire [9:0] SW, // On board Switches
7 | input wire [3:0] KEY, // On board push buttons
8 | output wire [6:0] HEX0, // HEX displays
9 | output wire [6:0] HEX1,
10 | output wire [6:0] HEX2,
11 | output wire [6:0] HEX3,
12 | output wire [6:0] HEX4,
13 | output wire [6:0] HEX5,
14 | output wire [9:0] LEDR, // LEDs
15 | output wire [7:0] x, // VGA pixel coordinates
16 | output wire [6:0] y,
17 | output wire [2:0] colour, // VGA pixel colour (0-7)
18 | output wire plot, // Pixel drawn when this is pulsed
19 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
20 | );
21 | full_adder(SW[0], SW[1], SW[2], LEDR[0], LEDR[1]);
22 |
23 | endmodule
24 |
25 | //Write code in here!
26 |
27 | module full_adder (a, b, c_p, s, c_n);
28 | input a, b, c_p;
29 | output s, c_n;
30 |
31 | assign s = a^b^c_p;
32 | assign c_n = (a&b)|(a&c_p)|(b&c_p);
33 |
34 | endmodule
35 |
36 |
37 |
--------------------------------------------------------------------------------
/Gated-D-Latch.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module module
5 |
6 | module main (
7 | input wire CLOCK_50, //On Board 50 MHz
8 | input wire [9:0] SW, // On board Switches
9 | input wire [3:0] KEY, // On board push buttons
10 | output wire [6:0] HEX0, // HEX displays
11 | output wire [6:0] HEX1,
12 | output wire [6:0] HEX2,
13 | output wire [6:0] HEX3,
14 | output wire [6:0] HEX4,
15 | output wire [6:0] HEX5,
16 | output wire [9:0] LEDR, // LEDs
17 | output wire [7:0] x, // VGA pixel coordinates
18 | output wire [6:0] y,
19 | output wire [2:0] colour, // VGA pixel colour (0-7)
20 | output wire plot, // Pixel drawn when this is pulsed
21 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
22 | );
23 | top v1(SW, LEDR);
24 |
25 | endmodule
26 |
27 | // Top Module
28 |
29 | module top(SW, LEDR);
30 | input [9:0] SW;
31 | output [9:0] LEDR;
32 |
33 | d_latch u1 (SW[0], SW[9], LEDR[0]);
34 |
35 | endmodule
36 |
37 | // d_latch module
38 |
39 | module d_latch(d, clock, q);
40 | input d, clock;
41 | output reg q;
42 | always@(*)
43 | begin
44 | if (clock == 1)
45 | q <= d;
46 | end
47 | endmodule
48 |
--------------------------------------------------------------------------------
/LICENSE:
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540 | 12. No Surrender of Others' Freedom.
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612 | 17. Interpretation of Sections 15 and 16.
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621 | END OF TERMS AND CONDITIONS
622 |
623 | How to Apply These Terms to Your New Programs
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625 | If you develop a new program, and you want it to be of the greatest
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633 |
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650 | Also add information on how to contact you by electronic and paper mail.
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652 | If the program does terminal interaction, make it output a short
653 | notice like this when it starts in an interactive mode:
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657 | This is free software, and you are welcome to redistribute it
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664 | You should also get your employer (if you work as a programmer) or school,
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667 | .
668 |
669 | The GNU General Public License does not permit incorporating your program
670 | into proprietary programs. If your program is a subroutine library, you
671 | may consider it more useful to permit linking proprietary applications with
672 | the library. If this is what you want to do, use the GNU Lesser General
673 | Public License instead of this License. But first, please read
674 | .
675 |
--------------------------------------------------------------------------------
/Mux7To1.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module
5 |
6 | endmodule //
7 | module main (
8 | input wire CLOCK_50, //On Board 50 MHz
9 | input wire [9:0] SW, // On board Switches
10 | input wire [3:0] KEY, // On board push buttons
11 | output wire [6:0] HEX0, // HEX displays
12 | output wire [6:0] HEX1,
13 | output wire [6:0] HEX2,
14 | output wire [6:0] HEX3,
15 | output wire [6:0] HEX4,
16 | output wire [6:0] HEX5,
17 | output wire [9:0] LEDR, // LEDs
18 | output wire [7:0] x, // VGA pixel coordinates
19 | output wire [6:0] y,
20 | output wire [2:0] colour, // VGA pixel colour (0-7)
21 | output wire plot, // Pixel drawn when this is pulsed
22 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
23 | );
24 | top v1(SW, LEDR);
25 |
26 | endmodule
27 |
28 | // Top Module
29 |
30 | module top(SW, LEDR);
31 | input [9:0] SW;
32 | output [9:0] LEDR;
33 |
34 | _7to1_mux u1 (SW[6:0], SW[9:7], LEDR[0]);
35 |
36 | endmodule
37 |
38 | // Mux module
39 |
40 | module _7to1_mux(inp, signal, out);
41 | input[6:0] inp;
42 | input[2:0] signal;
43 |
44 | output reg out;
45 | always@(*)
46 | case(signal)
47 | 3'b000 : out = inp[0];
48 | 3'b001 : out = inp[1];
49 | 3'b010 : out = inp[2];
50 | 3'b011 : out = inp[3];
51 | 3'b100 : out = inp[4];
52 | 3'b101 : out = inp[5];
53 | 3'b110 : out = inp[6];
54 | default : out = 1'b0;
55 | endcase
56 | endmodule
57 |
--------------------------------------------------------------------------------
/ParallelLoadShiftRegister.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module
5 |
6 | module main (
7 | input wire CLOCK_50, //On Board 50 MHz
8 | input wire [9:0] SW, // On board Switches
9 | input wire [3:0] KEY, // On board push buttons
10 | output wire [6:0] HEX0, // HEX displays
11 | output wire [6:0] HEX1,
12 | output wire [6:0] HEX2,
13 | output wire [6:0] HEX3,
14 | output wire [6:0] HEX4,
15 | output wire [6:0] HEX5,
16 | output wire [9:0] LEDR, // LEDs
17 | output wire [7:0] x, // VGA pixel coordinates
18 | output wire [6:0] y,
19 | output wire [2:0] colour, // VGA pixel colour (0-7)
20 | output wire plot, // Pixel drawn when this is pulsed
21 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
22 | );
23 | top v1(SW, LEDR);
24 |
25 | endmodule
26 |
27 | // Top Module
28 |
29 | module top(SW, LEDR);
30 | input [9:0] SW;
31 | output [9:0] LEDR;
32 |
33 | shift_reg_parallel_load u1 (SW[4], SW[3:0], SW[9], SW[8], SW[7], LEDR[3:0]);
34 | // shift_reg_parallel_load_1 u1 (SW[4], SW[3:0], SW[9], SW[8], SW[7], LEDR[3:0]);
35 | // You can try the above too - just uncomment the one you wanna try
36 |
37 | endmodule
38 |
39 | // Register - n bit
40 |
41 | module shift_reg_parallel_load(w, d, clock, loadn, resetp, q); // Synchronous and Active High
42 | input w, clock, loadn, resetp;
43 | input[3:0] d;
44 | output reg [3:0] q;
45 |
46 | always@(posedge clock)
47 | begin
48 | if (resetp == 1)
49 | q <= 0;
50 | else if (loadn == 1)
51 | q <= d;
52 | else
53 | begin
54 | q[0] <= w;
55 | q[1] <= q[0];
56 | q[2] <= q[1];
57 | q[3] <= q[2];
58 | end
59 | end
60 | endmodule
61 |
62 | module shift_reg_parallel_load_1(w, d, clock, loadn, resetn, q); // Asynchronous and Active low
63 | input w, clock, loadn, resetn;
64 | input[3:0] d;
65 | output reg [3:0] q;
66 |
67 | always@(posedge clock, negedge resetn)
68 | begin
69 | if (resetn == 0)
70 | q <= 0;
71 | else if (loadn == 1)
72 | q <= d;
73 | else
74 | begin
75 | q[0] <= w;
76 | q[1] <= q[0];
77 | q[2] <= q[1];
78 | q[3] <= q[2];
79 | end
80 | end
81 | endmodule
82 |
--------------------------------------------------------------------------------
/ParametricRegister.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module
5 |
6 | module main (
7 | input wire CLOCK_50, //On Board 50 MHz
8 | input wire [9:0] SW, // On board Switches
9 | input wire [3:0] KEY, // On board push buttons
10 | output wire [6:0] HEX0, // HEX displays
11 | output wire [6:0] HEX1,
12 | output wire [6:0] HEX2,
13 | output wire [6:0] HEX3,
14 | output wire [6:0] HEX4,
15 | output wire [6:0] HEX5,
16 | output wire [9:0] LEDR, // LEDs
17 | output wire [7:0] x, // VGA pixel coordinates
18 | output wire [6:0] y,
19 | output wire [2:0] colour, // VGA pixel colour (0-7)
20 | output wire plot, // Pixel drawn when this is pulsed
21 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
22 | );
23 | top v1(SW, LEDR);
24 |
25 | endmodule
26 |
27 | // Top Module
28 |
29 | module top(SW, LEDR);
30 | input [9:0] SW;
31 | output [9:0] LEDR;
32 |
33 | n_bit_register #2 u1 (SW[1:0], SW[9], SW[8], SW[7], LEDR[1:0]);
34 | // You can try out the others too by changing the parameter above :)
35 | // Don't forget to change the size of inputs if you change the parameter 'n'
36 |
37 | endmodule
38 |
39 | // Register - n bit
40 |
41 | module n_bit_register(d, clock, resetn, enable, q);
42 | parameter n = 4; // Default value
43 | input [n-1:0] d;
44 | input clock, resetn, enable;
45 | output reg [n-1:0] q;
46 |
47 | always@(posedge clock)
48 | begin
49 | if (resetn == 0)
50 | q <= 0;
51 | else if (enable == 1)
52 | q <= d;
53 | end
54 | endmodule
55 |
--------------------------------------------------------------------------------
/ParamtericCounter.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module
5 |
6 | module main (
7 | input wire CLOCK_50, //On Board 50 MHz
8 | input wire [9:0] SW, // On board Switches
9 | input wire [3:0] KEY, // On board push buttons
10 | output wire [6:0] HEX0, // HEX displays
11 | output wire [6:0] HEX1,
12 | output wire [6:0] HEX2,
13 | output wire [6:0] HEX3,
14 | output wire [6:0] HEX4,
15 | output wire [6:0] HEX5,
16 | output wire [9:0] LEDR, // LEDs
17 | output wire [7:0] x, // VGA pixel coordinates
18 | output wire [6:0] y,
19 | output wire [2:0] colour, // VGA pixel colour (0-7)
20 | output wire plot, // Pixel drawn when this is pulsed
21 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
22 | );
23 | top v1(SW, LEDR);
24 |
25 | endmodule
26 |
27 | // Top Module
28 |
29 | module top(SW, LEDR);
30 | input [9:0] SW;
31 | output [9:0] LEDR;
32 |
33 | param_counter #2 u1 (SW[9], SW[8], SW[7], SW[6], LEDR[1:0]);
34 |
35 | endmodule
36 |
37 | module param_counter(clock, enable, updown, resetn, q);
38 | parameter n = 3;
39 | input clock, enable, updown, resetn;
40 | output reg [n-1:0] q;
41 |
42 | always@(posedge clock)
43 | begin
44 | if (resetn == 0)
45 | q <= 0;
46 | else if (enable == 1)
47 | q <= q + (updown?1:-1);
48 | end
49 | endmodule
50 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # ECE241_Verilog
2 |
3 | 
4 |
5 | Lmao let's be serious now!
6 |
7 | ## What is this repo about?
8 |
9 | This repo contains verilog codes, modelsim simulations, logisim schematics and other resources for the course ECE241 taught at the University of Toronto. This repo is to help the current batch of ECE 2T3 and upcoming batches of ECE 241 because the online resources are very limited and hard to find.
10 |
11 | The code was validated using **Intel's Quartus Prime Software** using the tcl scripts (provided in the "Supporting Files" Directory.
12 |
13 | ## How to contribute?
14 |
15 | Contributions are most welcome but please read the **_CONTRIBUTING.md_** before generating a pull request, it will prevent your pull request from being rejected and help us review it more easily.
16 |
17 | ## Contents:
18 |
19 | * 2-to-1 multiplexer (Our dear mux)
20 |
21 | * 4-to-1 multiplexer
22 |
23 | * 4 bit 2-to-1 multiplexer
24 |
25 | * 7-to-1 multiplexer
26 |
27 | * Full adder
28 |
29 | * Ripple carry adder
30 |
31 | * 7 - Segment Hex Display
32 |
33 | * Gated D-Latch
34 |
35 | * D-flipflops (8 types without enable)
36 |
37 | * D-flipflop (with enable)
38 |
39 | * Register - 1 bit
40 |
41 | * Register - 4 bit
42 |
43 | * Register - 8 bit
44 |
45 | * Register - n bit - Parameterized
46 |
47 | * Shift Register
48 |
49 | * Shift Register - Parallel load
50 |
51 | * Toggle - flipflop
52 |
53 | * Counter - 4 bit
54 |
55 | * Updown counter - Parameterized
56 |
57 | * Async counter
58 |
59 | * Address Decoder (Memory)
60 |
61 | * 110 Sequence Detector - Finite State Machine
62 |
63 | ## Schematics
64 |
65 | > D-Latch:
66 |
67 | 
68 |
69 | > RS-Latch:
70 |
71 | 
72 |
73 | > Positive Edge D-Flip Flop:
74 |
75 | 
76 |
77 | > Negative Edge D-Flip Flop:
78 |
79 | 
80 |
81 | > Eight Bit Register:
82 |
83 | 
84 |
85 | > Four Bit Shift Registers:
86 |
87 | 
88 |
89 | > Toggle Flip Flop (T-Flip Flop)
90 |
91 | 
92 |
93 | > 110 Sequence Detector (State Diagram)
94 |
95 | 
96 |
97 |
98 | > Disclaimer: I do not own the files in the "Supporting files directory". They are open-source files made available to me by University of Toronto and can be found at: https://github.com/UofT-HPRC/fake_fpga/releases
99 |
--------------------------------------------------------------------------------
/RippleCarryAdder.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | module main (
5 | input wire CLOCK_50, //On Board 50 MHz
6 | input wire [9:0] SW, // On board Switches
7 | input wire [3:0] KEY, // On board push buttons
8 | output wire [6:0] HEX0, // HEX displays
9 | output wire [6:0] HEX1,
10 | output wire [6:0] HEX2,
11 | output wire [6:0] HEX3,
12 | output wire [6:0] HEX4,
13 | output wire [6:0] HEX5,
14 | output wire [9:0] LEDR, // LEDs
15 | output wire [7:0] x, // VGA pixel coordinates
16 | output wire [6:0] y,
17 | output wire [2:0] colour, // VGA pixel colour (0-7)
18 | output wire plot, // Pixel drawn when this is pulsed
19 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
20 | );
21 | three_bit_adder(SW[3:0], SW[7:4], SW[8], LEDR[3:0], LEDR[4]);
22 |
23 | endmodule
24 |
25 | //Write code in here!
26 |
27 | module full_adder (a, b, c_p, s, c_n);
28 | input a, b, c_p;
29 | output s, c_n;
30 |
31 | assign s = a^b^c_p;
32 | assign c_n = (a&b)|(a&c_p)|(b&c_p);
33 |
34 | endmodule
35 |
36 | module three_bit_adder(A, B, cin, S, cout);
37 | input[3:0] A, B;
38 | input cin;
39 | output[3:0] S;
40 | output cout;
41 |
42 | wire d1, d2, d3;
43 |
44 | full_adder(A[0], B[0], cin, S[0], d1);
45 | full_adder(A[1], B[1], d1, S[1], d2);
46 | full_adder(A[2], B[2], d2, S[2], d3);
47 | full_adder(A[3], B[3], d3, S[3], cout);
48 |
49 | endmodule
50 |
51 |
52 |
--------------------------------------------------------------------------------
/SevenSegmentDisplay.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module
5 |
6 | module main (
7 | input wire CLOCK_50, //On Board 50 MHz
8 | input wire [9:0] SW, // On board Switches
9 | input wire [3:0] KEY, // On board push buttons
10 | output wire [6:0] HEX0, // HEX displays
11 | output wire [6:0] HEX1,
12 | output wire [6:0] HEX2,
13 | output wire [6:0] HEX3,
14 | output wire [6:0] HEX4,
15 | output wire [6:0] HEX5,
16 | output wire [9:0] LEDR, // LEDs
17 | output wire [7:0] x, // VGA pixel coordinates
18 | output wire [6:0] y,
19 | output wire [2:0] colour, // VGA pixel colour (0-7)
20 | output wire plot, // Pixel drawn when this is pulsed
21 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
22 | );
23 | top u1(SW, HEX0);
24 |
25 | endmodule
26 |
27 | module top (SW, HEX0);
28 | input [9:0] SW;
29 | output [6:0] HEX0;
30 |
31 | hex_decoder v1 (SW[3], SW[2], SW[1], SW[0], HEX0[0], HEX0[1], HEX0[2], HEX0[3], HEX0[4], HEX0[5], HEX0[6]);
32 |
33 | endmodule
34 |
35 | module hex_decoder(input c3, c2, c1, c0, output s0, s1, s2, s3, s4, s5, s6);
36 | assign s0 = (~c3 & ~c2 & ~c1 & c0) | (~c3 & c2 & ~c1 & ~c0) | (c3 & ~c2 & c1 & c0) | (c3 & c2 & ~c1 & c0);
37 |
38 | assign s1 = (~c3 & c2 & ~c1 & c0) | (~c3 & c2 & c1 & ~c0) | (c3 & ~c2 & c1 & c0) | (c3 & c2 & ~c1 & ~c0) | (c3 & c2 & c1 & ~c0) | (c3 & c2 & c1 & c0);
39 |
40 | assign s2 = (~c3 & ~c2 & c1 & ~c0) | (c3 & c2 & ~c1 & ~c0) | (c3 & c2 & c1 & ~c0) | (c3 & c2 & c1 & c0);
41 |
42 | assign s3 = (~c3 & ~c2 & ~c1 & c0) | (~c3 & c2 & ~c1 & ~c0) | (~c3 & c2 & c1 & c0) | (c3 & ~c2 & c1 & ~c0) | (c3 & c2 & c1 & c0);
43 |
44 | assign s4 = (~c3 & ~c2 & ~c1 & c0) | (~c3 & ~c2 & c1 & c0) | (~c3 & c2 & ~c1 & ~c0) | (~c3 & c2 & ~c1 & c0) | (~c3 & c2 & c1 & c0) | (c3 & ~c2 & ~c1 & c0);
45 |
46 | assign s5 = (~c3 & ~c2 & ~c1 & c0) | (~c3 & ~c2 & c1 & ~c0) | (~c3 & ~c2 & c1 & c0) | (~c3 & c2 & c1 & c0) | (c3 & c2 & ~c1 & c0);
47 |
48 | assign s6 = (~c3 & ~c2 & ~c1 & c0) | (~c3 & c2 & c1 & c0) | (c3 & c2 & ~c1 & ~c0) | (~c3 & ~c2 & ~c1 & ~c0);
49 |
50 | endmodule
51 |
--------------------------------------------------------------------------------
/Supporting files/DE1_SoC.qsf:
--------------------------------------------------------------------------------
1 | #============================================================
2 | # Altera DE1-SoC board settings
3 | #============================================================
4 |
5 |
6 | set_global_assignment -name FAMILY "Cyclone V"
7 | set_global_assignment -name DEVICE 5CSEMA5F31C6
8 | set_global_assignment -name TOP_LEVEL_ENTITY "DE1_SoC"
9 | set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
10 | set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
11 |
12 |
13 | #============================================================
14 | # ADC
15 | #============================================================
16 | set_location_assignment PIN_AJ4 -to ADC_CS_N
17 | set_location_assignment PIN_AK4 -to ADC_DIN
18 | set_location_assignment PIN_AK3 -to ADC_DOUT
19 | set_location_assignment PIN_AK2 -to ADC_SCLK
20 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N
21 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DIN
22 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DOUT
23 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK
24 |
25 | #============================================================
26 | # AUD
27 | #============================================================
28 | set_location_assignment PIN_K7 -to AUD_ADCDAT
29 | set_location_assignment PIN_K8 -to AUD_ADCLRCK
30 | set_location_assignment PIN_H7 -to AUD_BCLK
31 | set_location_assignment PIN_J7 -to AUD_DACDAT
32 | set_location_assignment PIN_H8 -to AUD_DACLRCK
33 | set_location_assignment PIN_G7 -to AUD_XCK
34 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT
35 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK
36 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK
37 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT
38 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK
39 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK
40 |
41 | #============================================================
42 | # CLOCK
43 | #============================================================
44 | set_location_assignment PIN_AF14 -to CLOCK_50
45 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
46 |
47 | #============================================================
48 | # CLOCK2
49 | #============================================================
50 | set_location_assignment PIN_AA16 -to CLOCK2_50
51 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50
52 |
53 | #============================================================
54 | # CLOCK3
55 | #============================================================
56 | set_location_assignment PIN_Y26 -to CLOCK3_50
57 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50
58 |
59 | #============================================================
60 | # CLOCK4
61 | #============================================================
62 | set_location_assignment PIN_K14 -to CLOCK4_50
63 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK4_50
64 |
65 | #============================================================
66 | # DRAM
67 | #============================================================
68 | set_location_assignment PIN_AK14 -to DRAM_ADDR[0]
69 | set_location_assignment PIN_AH14 -to DRAM_ADDR[1]
70 | set_location_assignment PIN_AG15 -to DRAM_ADDR[2]
71 | set_location_assignment PIN_AE14 -to DRAM_ADDR[3]
72 | set_location_assignment PIN_AB15 -to DRAM_ADDR[4]
73 | set_location_assignment PIN_AC14 -to DRAM_ADDR[5]
74 | set_location_assignment PIN_AD14 -to DRAM_ADDR[6]
75 | set_location_assignment PIN_AF15 -to DRAM_ADDR[7]
76 | set_location_assignment PIN_AH15 -to DRAM_ADDR[8]
77 | set_location_assignment PIN_AG13 -to DRAM_ADDR[9]
78 | set_location_assignment PIN_AG12 -to DRAM_ADDR[10]
79 | set_location_assignment PIN_AH13 -to DRAM_ADDR[11]
80 | set_location_assignment PIN_AJ14 -to DRAM_ADDR[12]
81 | set_location_assignment PIN_AF13 -to DRAM_BA[0]
82 | set_location_assignment PIN_AJ12 -to DRAM_BA[1]
83 | set_location_assignment PIN_AF11 -to DRAM_CAS_N
84 | set_location_assignment PIN_AK13 -to DRAM_CKE
85 | set_location_assignment PIN_AH12 -to DRAM_CLK
86 | set_location_assignment PIN_AG11 -to DRAM_CS_N
87 | set_location_assignment PIN_AK6 -to DRAM_DQ[0]
88 | set_location_assignment PIN_AJ7 -to DRAM_DQ[1]
89 | set_location_assignment PIN_AK7 -to DRAM_DQ[2]
90 | set_location_assignment PIN_AK8 -to DRAM_DQ[3]
91 | set_location_assignment PIN_AK9 -to DRAM_DQ[4]
92 | set_location_assignment PIN_AG10 -to DRAM_DQ[5]
93 | set_location_assignment PIN_AK11 -to DRAM_DQ[6]
94 | set_location_assignment PIN_AJ11 -to DRAM_DQ[7]
95 | set_location_assignment PIN_AH10 -to DRAM_DQ[8]
96 | set_location_assignment PIN_AJ10 -to DRAM_DQ[9]
97 | set_location_assignment PIN_AJ9 -to DRAM_DQ[10]
98 | set_location_assignment PIN_AH9 -to DRAM_DQ[11]
99 | set_location_assignment PIN_AH8 -to DRAM_DQ[12]
100 | set_location_assignment PIN_AH7 -to DRAM_DQ[13]
101 | set_location_assignment PIN_AJ6 -to DRAM_DQ[14]
102 | set_location_assignment PIN_AJ5 -to DRAM_DQ[15]
103 | set_location_assignment PIN_AB13 -to DRAM_LDQM
104 | set_location_assignment PIN_AE13 -to DRAM_RAS_N
105 | set_location_assignment PIN_AK12 -to DRAM_UDQM
106 | set_location_assignment PIN_AA13 -to DRAM_WE_N
107 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
108 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
109 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
110 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
111 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
112 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
113 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
114 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
115 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
116 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
117 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
118 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
119 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
120 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
121 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
122 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
123 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
124 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
125 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
126 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
127 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
128 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
129 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
130 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
131 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
132 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
133 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
134 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
135 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
136 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
137 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
138 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
139 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
140 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
141 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
142 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
143 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
144 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
145 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
146 |
147 | #============================================================
148 | # FAN
149 | #============================================================
150 | set_location_assignment PIN_AA12 -to FAN_CTRL
151 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL
152 |
153 | #============================================================
154 | # FPGA
155 | #============================================================
156 | set_location_assignment PIN_J12 -to FPGA_I2C_SCLK
157 | set_location_assignment PIN_K12 -to FPGA_I2C_SDAT
158 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SCLK
159 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SDAT
160 |
161 | #============================================================
162 | # GPIO
163 | #============================================================
164 | set_location_assignment PIN_AC18 -to GPIO_0[0]
165 | set_location_assignment PIN_AH18 -to GPIO_0[10]
166 | set_location_assignment PIN_AH17 -to GPIO_0[11]
167 | set_location_assignment PIN_AG16 -to GPIO_0[12]
168 | set_location_assignment PIN_AE16 -to GPIO_0[13]
169 | set_location_assignment PIN_AF16 -to GPIO_0[14]
170 | set_location_assignment PIN_AG17 -to GPIO_0[15]
171 | set_location_assignment PIN_AA18 -to GPIO_0[16]
172 | set_location_assignment PIN_AA19 -to GPIO_0[17]
173 | set_location_assignment PIN_AE17 -to GPIO_0[18]
174 | set_location_assignment PIN_AC20 -to GPIO_0[19]
175 | set_location_assignment PIN_Y17 -to GPIO_0[1]
176 | set_location_assignment PIN_AH19 -to GPIO_0[20]
177 | set_location_assignment PIN_AJ20 -to GPIO_0[21]
178 | set_location_assignment PIN_AH20 -to GPIO_0[22]
179 | set_location_assignment PIN_AK21 -to GPIO_0[23]
180 | set_location_assignment PIN_AD19 -to GPIO_0[24]
181 | set_location_assignment PIN_AD20 -to GPIO_0[25]
182 | set_location_assignment PIN_AE18 -to GPIO_0[26]
183 | set_location_assignment PIN_AE19 -to GPIO_0[27]
184 | set_location_assignment PIN_AF20 -to GPIO_0[28]
185 | set_location_assignment PIN_AF21 -to GPIO_0[29]
186 | set_location_assignment PIN_AD17 -to GPIO_0[2]
187 | set_location_assignment PIN_AF19 -to GPIO_0[30]
188 | set_location_assignment PIN_AG21 -to GPIO_0[31]
189 | set_location_assignment PIN_AF18 -to GPIO_0[32]
190 | set_location_assignment PIN_AG20 -to GPIO_0[33]
191 | set_location_assignment PIN_AG18 -to GPIO_0[34]
192 | set_location_assignment PIN_AJ21 -to GPIO_0[35]
193 | set_location_assignment PIN_Y18 -to GPIO_0[3]
194 | set_location_assignment PIN_AK16 -to GPIO_0[4]
195 | set_location_assignment PIN_AK18 -to GPIO_0[5]
196 | set_location_assignment PIN_AK19 -to GPIO_0[6]
197 | set_location_assignment PIN_AJ19 -to GPIO_0[7]
198 | set_location_assignment PIN_AJ17 -to GPIO_0[8]
199 | set_location_assignment PIN_AJ16 -to GPIO_0[9]
200 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
201 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
202 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
203 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
204 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
205 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
206 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
207 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
208 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
209 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
210 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
211 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
212 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
213 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
214 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
215 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
216 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
217 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
218 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
219 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
220 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
221 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
222 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
223 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
224 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
225 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
226 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
227 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34]
228 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35]
229 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
230 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
231 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
232 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
233 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
234 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
235 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
236 |
237 | set_location_assignment PIN_AB17 -to GPIO_1[0]
238 | set_location_assignment PIN_AG26 -to GPIO_1[10]
239 | set_location_assignment PIN_AH24 -to GPIO_1[11]
240 | set_location_assignment PIN_AH27 -to GPIO_1[12]
241 | set_location_assignment PIN_AJ27 -to GPIO_1[13]
242 | set_location_assignment PIN_AK29 -to GPIO_1[14]
243 | set_location_assignment PIN_AK28 -to GPIO_1[15]
244 | set_location_assignment PIN_AK27 -to GPIO_1[16]
245 | set_location_assignment PIN_AJ26 -to GPIO_1[17]
246 | set_location_assignment PIN_AK26 -to GPIO_1[18]
247 | set_location_assignment PIN_AH25 -to GPIO_1[19]
248 | set_location_assignment PIN_AA21 -to GPIO_1[1]
249 | set_location_assignment PIN_AJ25 -to GPIO_1[20]
250 | set_location_assignment PIN_AJ24 -to GPIO_1[21]
251 | set_location_assignment PIN_AK24 -to GPIO_1[22]
252 | set_location_assignment PIN_AG23 -to GPIO_1[23]
253 | set_location_assignment PIN_AK23 -to GPIO_1[24]
254 | set_location_assignment PIN_AH23 -to GPIO_1[25]
255 | set_location_assignment PIN_AK22 -to GPIO_1[26]
256 | set_location_assignment PIN_AJ22 -to GPIO_1[27]
257 | set_location_assignment PIN_AH22 -to GPIO_1[28]
258 | set_location_assignment PIN_AG22 -to GPIO_1[29]
259 | set_location_assignment PIN_AB21 -to GPIO_1[2]
260 | set_location_assignment PIN_AF24 -to GPIO_1[30]
261 | set_location_assignment PIN_AF23 -to GPIO_1[31]
262 | set_location_assignment PIN_AE22 -to GPIO_1[32]
263 | set_location_assignment PIN_AD21 -to GPIO_1[33]
264 | set_location_assignment PIN_AA20 -to GPIO_1[34]
265 | set_location_assignment PIN_AC22 -to GPIO_1[35]
266 | set_location_assignment PIN_AC23 -to GPIO_1[3]
267 | set_location_assignment PIN_AD24 -to GPIO_1[4]
268 | set_location_assignment PIN_AE23 -to GPIO_1[5]
269 | set_location_assignment PIN_AE24 -to GPIO_1[6]
270 | set_location_assignment PIN_AF25 -to GPIO_1[7]
271 | set_location_assignment PIN_AF26 -to GPIO_1[8]
272 | set_location_assignment PIN_AG25 -to GPIO_1[9]
273 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
274 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
275 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
276 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
277 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
278 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
279 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
280 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
281 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
282 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
283 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
284 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
285 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
286 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
287 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
288 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
289 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
290 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
291 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
292 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
293 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
294 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
295 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
296 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
297 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
298 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
299 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
300 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34]
301 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35]
302 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
303 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
304 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
305 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
306 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
307 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
308 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
309 |
310 | #============================================================
311 | # HEX0
312 | #============================================================
313 | set_location_assignment PIN_AE26 -to HEX0[0]
314 | set_location_assignment PIN_AE27 -to HEX0[1]
315 | set_location_assignment PIN_AE28 -to HEX0[2]
316 | set_location_assignment PIN_AG27 -to HEX0[3]
317 | set_location_assignment PIN_AF28 -to HEX0[4]
318 | set_location_assignment PIN_AG28 -to HEX0[5]
319 | set_location_assignment PIN_AH28 -to HEX0[6]
320 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
321 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
322 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
323 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
324 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
325 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
326 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
327 |
328 | #============================================================
329 | # HEX1
330 | #============================================================
331 | set_location_assignment PIN_AJ29 -to HEX1[0]
332 | set_location_assignment PIN_AH29 -to HEX1[1]
333 | set_location_assignment PIN_AH30 -to HEX1[2]
334 | set_location_assignment PIN_AG30 -to HEX1[3]
335 | set_location_assignment PIN_AF29 -to HEX1[4]
336 | set_location_assignment PIN_AF30 -to HEX1[5]
337 | set_location_assignment PIN_AD27 -to HEX1[6]
338 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
339 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
340 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
341 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
342 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
343 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
344 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
345 |
346 | #============================================================
347 | # HEX2
348 | #============================================================
349 | set_location_assignment PIN_AB23 -to HEX2[0]
350 | set_location_assignment PIN_AE29 -to HEX2[1]
351 | set_location_assignment PIN_AD29 -to HEX2[2]
352 | set_location_assignment PIN_AC28 -to HEX2[3]
353 | set_location_assignment PIN_AD30 -to HEX2[4]
354 | set_location_assignment PIN_AC29 -to HEX2[5]
355 | set_location_assignment PIN_AC30 -to HEX2[6]
356 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
357 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
358 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
359 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
360 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
361 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
362 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
363 |
364 | #============================================================
365 | # HEX3
366 | #============================================================
367 | set_location_assignment PIN_AD26 -to HEX3[0]
368 | set_location_assignment PIN_AC27 -to HEX3[1]
369 | set_location_assignment PIN_AD25 -to HEX3[2]
370 | set_location_assignment PIN_AC25 -to HEX3[3]
371 | set_location_assignment PIN_AB28 -to HEX3[4]
372 | set_location_assignment PIN_AB25 -to HEX3[5]
373 | set_location_assignment PIN_AB22 -to HEX3[6]
374 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
375 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
376 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
377 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
378 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
379 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
380 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
381 |
382 | #============================================================
383 | # HEX4
384 | #============================================================
385 | set_location_assignment PIN_AA24 -to HEX4[0]
386 | set_location_assignment PIN_Y23 -to HEX4[1]
387 | set_location_assignment PIN_Y24 -to HEX4[2]
388 | set_location_assignment PIN_W22 -to HEX4[3]
389 | set_location_assignment PIN_W24 -to HEX4[4]
390 | set_location_assignment PIN_V23 -to HEX4[5]
391 | set_location_assignment PIN_W25 -to HEX4[6]
392 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
393 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
394 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
395 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
396 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
397 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
398 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
399 |
400 | #============================================================
401 | # HEX5
402 | #============================================================
403 | set_location_assignment PIN_V25 -to HEX5[0]
404 | set_location_assignment PIN_AA28 -to HEX5[1]
405 | set_location_assignment PIN_Y27 -to HEX5[2]
406 | set_location_assignment PIN_AB27 -to HEX5[3]
407 | set_location_assignment PIN_AB26 -to HEX5[4]
408 | set_location_assignment PIN_AA26 -to HEX5[5]
409 | set_location_assignment PIN_AA25 -to HEX5[6]
410 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
411 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
412 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
413 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
414 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
415 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
416 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
417 |
418 | #============================================================
419 | # IRDA
420 | #============================================================
421 | set_location_assignment PIN_AA30 -to IRDA_RXD
422 | set_location_assignment PIN_AB30 -to IRDA_TXD
423 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD
424 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_TXD
425 |
426 | #============================================================
427 | # KEY
428 | #============================================================
429 | set_location_assignment PIN_AA14 -to KEY[0]
430 | set_location_assignment PIN_AA15 -to KEY[1]
431 | set_location_assignment PIN_W15 -to KEY[2]
432 | set_location_assignment PIN_Y16 -to KEY[3]
433 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
434 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
435 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
436 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
437 |
438 | #============================================================
439 | # LEDR
440 | #============================================================
441 | set_location_assignment PIN_V16 -to LEDR[0]
442 | set_location_assignment PIN_W16 -to LEDR[1]
443 | set_location_assignment PIN_V17 -to LEDR[2]
444 | set_location_assignment PIN_V18 -to LEDR[3]
445 | set_location_assignment PIN_W17 -to LEDR[4]
446 | set_location_assignment PIN_W19 -to LEDR[5]
447 | set_location_assignment PIN_Y19 -to LEDR[6]
448 | set_location_assignment PIN_W20 -to LEDR[7]
449 | set_location_assignment PIN_W21 -to LEDR[8]
450 | set_location_assignment PIN_Y21 -to LEDR[9]
451 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
452 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
453 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
454 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
455 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
456 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
457 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
458 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
459 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
460 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
461 |
462 | #============================================================
463 | # PS2
464 | #============================================================
465 | set_location_assignment PIN_AD7 -to PS2_CLK
466 | set_location_assignment PIN_AE7 -to PS2_DAT
467 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
468 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
469 |
470 | set_location_assignment PIN_AD9 -to PS2_CLK2
471 | set_location_assignment PIN_AE9 -to PS2_DAT2
472 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2
473 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2
474 |
475 | #============================================================
476 | # SW
477 | #============================================================
478 | set_location_assignment PIN_AB12 -to SW[0]
479 | set_location_assignment PIN_AC12 -to SW[1]
480 | set_location_assignment PIN_AF9 -to SW[2]
481 | set_location_assignment PIN_AF10 -to SW[3]
482 | set_location_assignment PIN_AD11 -to SW[4]
483 | set_location_assignment PIN_AD12 -to SW[5]
484 | set_location_assignment PIN_AE11 -to SW[6]
485 | set_location_assignment PIN_AC9 -to SW[7]
486 | set_location_assignment PIN_AD10 -to SW[8]
487 | set_location_assignment PIN_AE12 -to SW[9]
488 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
489 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
490 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
491 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
492 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
493 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
494 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
495 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
496 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
497 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
498 |
499 | #============================================================
500 | # TD
501 | #============================================================
502 | set_location_assignment PIN_H15 -to TD_CLK27
503 | set_location_assignment PIN_D2 -to TD_DATA[0]
504 | set_location_assignment PIN_B1 -to TD_DATA[1]
505 | set_location_assignment PIN_E2 -to TD_DATA[2]
506 | set_location_assignment PIN_B2 -to TD_DATA[3]
507 | set_location_assignment PIN_D1 -to TD_DATA[4]
508 | set_location_assignment PIN_E1 -to TD_DATA[5]
509 | set_location_assignment PIN_C2 -to TD_DATA[6]
510 | set_location_assignment PIN_B3 -to TD_DATA[7]
511 | set_location_assignment PIN_A5 -to TD_HS
512 | set_location_assignment PIN_F6 -to TD_RESET_N
513 | set_location_assignment PIN_A3 -to TD_VS
514 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27
515 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0]
516 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1]
517 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2]
518 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3]
519 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4]
520 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5]
521 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6]
522 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7]
523 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS
524 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N
525 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS
526 |
527 | #============================================================
528 | # USB
529 | #============================================================
530 | set_location_assignment PIN_AF4 -to USB_B2_CLK
531 | set_location_assignment PIN_AH4 -to USB_B2_DATA[0]
532 | set_location_assignment PIN_AH3 -to USB_B2_DATA[1]
533 | set_location_assignment PIN_AJ2 -to USB_B2_DATA[2]
534 | set_location_assignment PIN_AJ1 -to USB_B2_DATA[3]
535 | set_location_assignment PIN_AH2 -to USB_B2_DATA[4]
536 | set_location_assignment PIN_AG3 -to USB_B2_DATA[5]
537 | set_location_assignment PIN_AG2 -to USB_B2_DATA[6]
538 | set_location_assignment PIN_AG1 -to USB_B2_DATA[7]
539 | set_location_assignment PIN_AF5 -to USB_EMPTY
540 | set_location_assignment PIN_AG5 -to USB_FULL
541 | set_location_assignment PIN_AF6 -to USB_OE_N
542 | set_location_assignment PIN_AG6 -to USB_RD_N
543 | set_location_assignment PIN_AG7 -to USB_RESET_N
544 | set_location_assignment PIN_AG8 -to USB_SCL
545 | set_location_assignment PIN_AF8 -to USB_SDA
546 | set_location_assignment PIN_AH5 -to USB_WR_N
547 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_CLK
548 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[0]
549 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[1]
550 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[2]
551 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[3]
552 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[4]
553 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[5]
554 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[6]
555 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[7]
556 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_EMPTY
557 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FULL
558 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_OE_N
559 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_RD_N
560 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_RESET_N
561 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SCL
562 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SDA
563 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_WR_N
564 |
565 | #============================================================
566 | # VGA
567 | #============================================================
568 | set_location_assignment PIN_B13 -to VGA_B[0]
569 | set_location_assignment PIN_G13 -to VGA_B[1]
570 | set_location_assignment PIN_H13 -to VGA_B[2]
571 | set_location_assignment PIN_F14 -to VGA_B[3]
572 | set_location_assignment PIN_H14 -to VGA_B[4]
573 | set_location_assignment PIN_F15 -to VGA_B[5]
574 | set_location_assignment PIN_G15 -to VGA_B[6]
575 | set_location_assignment PIN_J14 -to VGA_B[7]
576 | set_location_assignment PIN_F10 -to VGA_BLANK_N
577 | set_location_assignment PIN_A11 -to VGA_CLK
578 | set_location_assignment PIN_J9 -to VGA_G[0]
579 | set_location_assignment PIN_J10 -to VGA_G[1]
580 | set_location_assignment PIN_H12 -to VGA_G[2]
581 | set_location_assignment PIN_G10 -to VGA_G[3]
582 | set_location_assignment PIN_G11 -to VGA_G[4]
583 | set_location_assignment PIN_G12 -to VGA_G[5]
584 | set_location_assignment PIN_F11 -to VGA_G[6]
585 | set_location_assignment PIN_E11 -to VGA_G[7]
586 | set_location_assignment PIN_B11 -to VGA_HS
587 | set_location_assignment PIN_A13 -to VGA_R[0]
588 | set_location_assignment PIN_C13 -to VGA_R[1]
589 | set_location_assignment PIN_E13 -to VGA_R[2]
590 | set_location_assignment PIN_B12 -to VGA_R[3]
591 | set_location_assignment PIN_C12 -to VGA_R[4]
592 | set_location_assignment PIN_D12 -to VGA_R[5]
593 | set_location_assignment PIN_E12 -to VGA_R[6]
594 | set_location_assignment PIN_F13 -to VGA_R[7]
595 | set_location_assignment PIN_C10 -to VGA_SYNC_N
596 | set_location_assignment PIN_D11 -to VGA_VS
597 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
598 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
599 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
600 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
601 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
602 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
603 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6]
604 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7]
605 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N
606 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK
607 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
608 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
609 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
610 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
611 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
612 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
613 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6]
614 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7]
615 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
616 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
617 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
618 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
619 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
620 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
621 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
622 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6]
623 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7]
624 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N
625 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
626 |
627 | #============================================================
628 | # HPS
629 | #============================================================
630 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
631 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[0]
632 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[1]
633 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[2]
634 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[3]
635 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[4]
636 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[5]
637 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[6]
638 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[7]
639 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[8]
640 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[9]
641 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[10]
642 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[11]
643 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[12]
644 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[13]
645 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[14]
646 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_BA[0]
647 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_BA[1]
648 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_BA[2]
649 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_CAS_N
650 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_CKE
651 | set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_CK_N
652 | set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_CK_P
653 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_CS_N
654 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[0]
655 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[1]
656 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[2]
657 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[3]
658 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[0]
659 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[1]
660 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[2]
661 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[3]
662 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[4]
663 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[5]
664 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[6]
665 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[7]
666 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[8]
667 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[9]
668 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[10]
669 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[11]
670 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[12]
671 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[13]
672 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[14]
673 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[15]
674 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[16]
675 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[17]
676 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[18]
677 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[19]
678 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[20]
679 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[21]
680 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[22]
681 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[23]
682 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[24]
683 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[25]
684 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[26]
685 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[27]
686 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[28]
687 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[29]
688 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[30]
689 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[31]
690 | set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[0]
691 | set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[1]
692 | set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[2]
693 | set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[3]
694 | set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[0]
695 | set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[1]
696 | set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[2]
697 | set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[3]
698 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ODT
699 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_RAS_N
700 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_RESET_N
701 | set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ
702 | set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_WE_N
703 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
704 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
705 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
706 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
707 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
708 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
709 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
710 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
711 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
712 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
713 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
714 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
715 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
716 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
717 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
718 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[0]
719 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[1]
720 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[2]
721 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[3]
722 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DCLK
723 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_NCSO
724 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
725 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
726 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
727 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C2_SCLK
728 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C2_SDAT
729 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_CONTROL
730 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY
731 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
732 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
733 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
734 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
735 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
736 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
737 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
738 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
739 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
740 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
741 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
742 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
743 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
744 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
745 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
746 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
747 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
748 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
749 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
750 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
751 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
752 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
753 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
754 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
755 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
756 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
757 |
758 | #============================================================
759 | # End of pin and io_standard assignments
760 | #============================================================
761 |
762 |
--------------------------------------------------------------------------------
/Supporting files/fakefpga.vpi:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/pandyah5/ECE241_Verilog/3a9fbf8ac07ef824b697d1f8d09a00c68e13f200/Supporting files/fakefpga.vpi
--------------------------------------------------------------------------------
/Supporting files/run_sim.bat:
--------------------------------------------------------------------------------
1 | REM https://stackoverflow.com/a/34182234/2737696
2 | cls
3 | @pushd %~dp0
4 |
5 | PATH C:\DESL\Quartus18\modelsim_ase\win32aloem;%PATH%
6 |
7 | vlib work
8 | vlog tb.v
9 | vlog main.vo
10 | vsim -pli fakefpga.vpi +nowarn3116 -c -t 1ps -L cyclonev_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver tb -voptargs="+acc" -do "run -all"
11 |
12 | REM https://stackoverflow.com/a/34182234/2737696
13 | @popd
14 |
--------------------------------------------------------------------------------
/Supporting files/tb.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | //This testbench is designed to hide the details of using the VPI code
5 |
6 | module tb();
7 |
8 | reg CLOCK_50 = 0; // 50 MHz clock, scaled down for simulation
9 | reg [9:0] SW = 0; // Switches
10 | reg [3:0] KEY = 4'b1111; // Push buttons
11 | wire [(8*6) -1:0] HEX; // HEX displays
12 | wire [9:0] LED; // LEDs
13 | wire [7:0] x; // VGA pixel coordinates
14 | wire [6:0] y;
15 | wire [2:0] colour; // VGA pixel colour (0-7)
16 | wire plot; // Pixel drawn when this is pulsed
17 | wire vga_resetn; // VGA reset to black when this is pulsed
18 |
19 | initial $fake_fpga(CLOCK_50, SW, KEY, LED, HEX, x, y, colour, plot, vga_resetn);
20 |
21 | //Easiest way to generate the clock is in the verilog rather than in the VPI
22 | //As promised, this simulates a 50 MHz clock.
23 | always #10 CLOCK_50 <= ~CLOCK_50;
24 |
25 | main DUT (
26 | .CLOCK_50(CLOCK_50),
27 | .SW(SW),
28 | .KEY(KEY),
29 | .HEX0(HEX[8*1 - 2 -: 7]),
30 | .HEX1(HEX[8*2 - 2 -: 7]),
31 | .HEX2(HEX[8*3 - 2 -: 7]),
32 | .HEX3(HEX[8*4 - 2 -: 7]),
33 | .HEX4(HEX[8*5 - 2 -: 7]),
34 | .HEX5(HEX[8*6 - 2 -: 7]),
35 | .LEDR(LED),
36 | .x(x),
37 | .y(y),
38 | .colour(colour),
39 | .plot(plot),
40 | .vga_resetn(vga_resetn)
41 | );
42 |
43 | genvar i;
44 | generate for (i = 1; i <= 6; i = i + 1) begin : assign_unused
45 | assign HEX[8*i - 1] = 0;
46 | end endgenerate
47 |
48 | endmodule
49 |
--------------------------------------------------------------------------------
/T-FlipFlop.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module
5 |
6 | module main (
7 | input wire CLOCK_50, //On Board 50 MHz
8 | input wire [9:0] SW, // On board Switches
9 | input wire [3:0] KEY, // On board push buttons
10 | output wire [6:0] HEX0, // HEX displays
11 | output wire [6:0] HEX1,
12 | output wire [6:0] HEX2,
13 | output wire [6:0] HEX3,
14 | output wire [6:0] HEX4,
15 | output wire [6:0] HEX5,
16 | output wire [9:0] LEDR, // LEDs
17 | output wire [7:0] x, // VGA pixel coordinates
18 | output wire [6:0] y,
19 | output wire [2:0] colour, // VGA pixel colour (0-7)
20 | output wire plot, // Pixel drawn when this is pulsed
21 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
22 | );
23 | top v1(SW, LEDR);
24 |
25 | endmodule
26 |
27 | // Top Module
28 |
29 | module top(SW, LEDR);
30 | input [9:0] SW;
31 | output [9:0] LEDR;
32 |
33 | t_flipflop u1 (SW[0], SW[1], SW[9], LEDR[0]);
34 | endmodule
35 |
36 | module t_flipflop(t, resetn, clock, q);
37 | input clock, t, resetn;
38 | output reg q;
39 |
40 | always@(posedge clock)
41 | begin
42 | if (!resetn)
43 | q <= 0;
44 | else if (t == 1)
45 | q <= ~q;
46 | end
47 | endmodule
48 |
--------------------------------------------------------------------------------
/justModules.v:
--------------------------------------------------------------------------------
1 | // 7 to 1 mux
2 |
3 | module _7to1_mux(inp, signal, out);
4 | input[6:0] inp;
5 | input[2:0] signal;
6 |
7 | output reg out;
8 | always@(*)
9 | case(signal)
10 | 3'b000 : out = inp[0];
11 | 3'b001 : out = inp[1];
12 | 3'b010 : out = inp[2];
13 | 3'b011 : out = inp[3];
14 | 3'b100 : out = inp[4];
15 | 3'b101 : out = inp[5];
16 | 3'b110 : out = inp[6];
17 | default : out = 1'b0;
18 | endcase
19 | endmodule
20 |
21 | // D-Latch
22 |
23 | module d_latch(d, clock, q);
24 | input d, clock;
25 | output reg q;
26 |
27 | always@(*)
28 | if (clock == 1)
29 | q <= d;
30 | endmodule
31 |
32 | // DFF - posedge
33 |
34 | module d_flipflop(d, clock, q, resetn);
35 | input d, clock, resetn;
36 | output reg q;
37 |
38 | always@(posedge clock)
39 | begin
40 | if (resetn == 0)
41 | q <= 0;
42 | else
43 | q <= d;
44 | end
45 | endmodule
46 |
47 | // DFF - negedge
48 |
49 | module d_flipflop(d, clock, resetn, q);
50 | input d, clock, resetn;
51 | output reg q;
52 |
53 | always@(negedge clock)
54 | begin
55 | if (resetn == 0)
56 | q <= 0;
57 | else
58 | q <= d;
59 | end
60 | endmodule
61 |
62 | // Register - 4 bit
63 |
64 | module register_4_bit (d, clock, resetn, q);
65 | // Posedge clock - Synchronous - Active low
66 | input[3:0] d;
67 | input clock, resetn;
68 | output reg [3:0] q;
69 |
70 | always@(posedge clock)
71 | begin
72 | if (resetn == 0)
73 | q <= 0;
74 | else
75 | q <= d;
76 | end
77 | endmodule
78 |
79 | // Register - n bit
80 |
81 | module n_bit_register(d, clock, resetn, enable, q);
82 | parameter n = 4; // Default value
83 | input [n-1:0] d;
84 | input clock, resetn, enable;
85 | output reg [n-1:0] q;
86 |
87 | always(posedge clock)
88 | begin
89 | if (resetn == 0)
90 | q <= 0;
91 | else if (enable == 1)
92 | q <= d;
93 | end
94 | endmodule
95 |
96 | // Shift Register
97 |
98 | module shift_register_3_bit (w, clock, resetn, load, pl, q);
99 | input clock, w, load, resetn;
100 | input[2:0] pl;
101 | output reg [2:0] q;
102 |
103 | always@(posedge clock)
104 | begin
105 | if (!resetn)
106 | q <= 0;
107 | else if (load == 0)
108 | q <= pl;
109 | else
110 | begin
111 | q[0] <= w; // Very important - USE NON-BLOCKING STATEMENTS
112 | q[1] <= q[0]; // Very important - USE NON-BLOCKING STATEMENTS
113 | q[2] <= q[1]; // Very important - USE NON-BLOCKING STATEMENTS
114 | end
115 | end
116 | endmodule
117 |
118 | // T - flipflop
119 |
120 | module t_flipflop(t, resetn, clock, q);
121 | input clock, t, resetn;
122 | output reg q;
123 |
124 | always@(posedge clock)
125 | begin
126 | if (!resetn)
127 | q <= 0;
128 | else if (t == 1)
129 | q <= ~q;
130 | end
131 | endmodule
132 |
133 | // Counter - 4 bit
134 |
135 | module counter_4_bit (clock, enable, resetp, q);
136 | input clock, enable, resetp;
137 | output reg [3:0] q;
138 |
139 | always@(posedge clock)
140 | begin
141 | if (resetp == 0)
142 | q <= 0;
143 | else if (enable == 1)
144 | q <= q + 1;
145 | end
146 | endmodule
147 |
148 | // Updown counter - Parameterized
149 |
150 | module param_counter(clock, enable ,updown, resetn, q);
151 | parameter n = 3;
152 | input clock, enable, updown, resetn;
153 | output reg [n-1:0] q;
154 |
155 | always@(posedge clock)
156 | begin
157 | if (resetn == 0)
158 | q <= 0;
159 | else if (enable == 1)
160 | q <= q + (updown?1:-1);
161 | end
162 | endmodule
163 |
164 | // Async counter
165 |
166 | module async_counter_top(enable, clock, resetp, q);
167 | input enable, clock, resetp;
168 | output [2:0] q;
169 | wire [2:0] c ;
170 |
171 | t_flipflop v1 (enable, resetp, clock, c[0]);
172 | t_flipflop v2 (enable, resetp, ~c[0], c[1]);
173 | t_flipflop v3 (enable, resetp, ~c[1], c[2]);
174 |
175 | assign q = c;
176 | endmodule
177 |
178 | module t_flipflop(t, resetp, clock, q);
179 | input clock, t, resetp;
180 | output reg q;
181 |
182 | always@(posedge clock, posedge resetp)
183 | begin
184 | if (resetp)
185 | q <= 0;
186 | else if (t == 1)
187 | q <= ~q;
188 | end
189 |
190 | endmodule
191 |
--------------------------------------------------------------------------------
/main.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module
5 |
6 | module main (
7 | input wire CLOCK_50, //On Board 50 MHz
8 | input wire [9:0] SW, // On board Switches
9 | input wire [3:0] KEY, // On board push buttons
10 | output wire [6:0] HEX0, // HEX displays
11 | output wire [6:0] HEX1,
12 | output wire [6:0] HEX2,
13 | output wire [6:0] HEX3,
14 | output wire [6:0] HEX4,
15 | output wire [6:0] HEX5,
16 | output wire [9:0] LEDR, // LEDs
17 | output wire [7:0] x, // VGA pixel coordinates
18 | output wire [6:0] y,
19 | output wire [2:0] colour, // VGA pixel colour (0-7)
20 | output wire plot, // Pixel drawn when this is pulsed
21 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
22 | );
23 |
24 | endmodule
25 |
--------------------------------------------------------------------------------
/mux4to1.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | module main (
5 | input wire CLOCK_50, //On Board 50 MHz
6 | input wire [9:0] SW, // On board Switches
7 | input wire [3:0] KEY, // On board push buttons
8 | output wire [6:0] HEX0, // HEX displays
9 | output wire [6:0] HEX1,
10 | output wire [6:0] HEX2,
11 | output wire [6:0] HEX3,
12 | output wire [6:0] HEX4,
13 | output wire [6:0] HEX5,
14 | output wire [9:0] LEDR, // LEDs
15 | output wire [7:0] x, // VGA pixel coordinates
16 | output wire [6:0] y,
17 | output wire [2:0] colour, // VGA pixel colour (0-7)
18 | output wire plot, // Pixel drawn when this is pulsed
19 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
20 | );
21 | mux4to1 u0(.X(SW[1:0]), .Y(SW[3:2]), .Z(LEDR[0]), .S(SW[9:8]));
22 |
23 | endmodule
24 |
25 | module mux2to1(a, b, Y, S);
26 | // Declaring inputs and outputs
27 | input a, b;
28 | input S;
29 | output Y;
30 |
31 | assign Y = (~S & a)|(S & b);
32 |
33 | endmodule
34 |
35 | module mux4to1 (input[1:0] X, Y, S, output Z);
36 | wire c1, c2;
37 |
38 | mux2to1 u1(.a(X[0]), .b(Y[0]), .Y(c1), .S(S[0]));
39 | mux2to1 u2(.a(X[1]), .b(Y[1]), .Y(c2), .S(S[0]));
40 | mux2to1 u3(.a(c1), .b(c2), .Y(Z), .S(S[1]));
41 |
42 | endmodule
43 |
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/registers.v:
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1 | `timescale 1ns / 1ps
2 | `default_nettype none
3 |
4 | // DE1_SoC board needs the below main module
5 |
6 | module main (
7 | input wire CLOCK_50, //On Board 50 MHz
8 | input wire [9:0] SW, // On board Switches
9 | input wire [3:0] KEY, // On board push buttons
10 | output wire [6:0] HEX0, // HEX displays
11 | output wire [6:0] HEX1,
12 | output wire [6:0] HEX2,
13 | output wire [6:0] HEX3,
14 | output wire [6:0] HEX4,
15 | output wire [6:0] HEX5,
16 | output wire [9:0] LEDR, // LEDs
17 | output wire [7:0] x, // VGA pixel coordinates
18 | output wire [6:0] y,
19 | output wire [2:0] colour, // VGA pixel colour (0-7)
20 | output wire plot, // Pixel drawn when this is pulsed
21 | output wire vga_resetn // VGA resets to black when this is pulsed (NOT CURRENTLY AVAILABLE)
22 | );
23 | top v1(SW, LEDR);
24 |
25 | endmodule
26 |
27 | // Top Module
28 |
29 | module top(SW, LEDR);
30 | input [9:0] SW;
31 | output [9:0] LEDR;
32 |
33 | register_4_bit u1 (SW[3:0], SW[9], SW[8], SW[7], LEDR[3:0]);
34 | // You can try out the others too by changing the line above :)
35 |
36 | endmodule
37 |
38 | // Registers
39 |
40 | module register_1_bit(d, enable, clock, resetn, q); // Active low reset and Synchronous
41 | input d, enable, clock, resetn;
42 | output reg q;
43 | always@(posedge clock)
44 | begin
45 | if (!resetn)
46 | q <= 0;
47 | else if (enable == 1)
48 | q <= d;
49 | end
50 | endmodule
51 |
52 | module register_4_bit (d, clock, resetn, enable, q); // Synchronous - Active low
53 | input[3:0] d;
54 | input clock, enable, resetn;
55 | output reg [3:0] q;
56 |
57 | always@(posedge clock)
58 | begin
59 | if (resetn == 0)
60 | q <= 0;
61 | else if (enable == 1)
62 | q <= d;
63 | end
64 | endmodule
65 |
66 | module register_8_bit(d, enable, clock, resetp, q); // Active high reset and Asynchronous
67 | input enable, clock, resetp;
68 | input[7:0] d;
69 | output reg[7:0] q;
70 | always@(posedge clock, posedge resetp)
71 | begin
72 | if (resetp == 1)
73 | q <= 8'b00000000; // Binary 8 bit
74 | else if (enable)
75 | q <= d;
76 | end
77 | endmodule
78 |
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