├── .gitmodules ├── Changelog.md ├── README.md └── scripts ├── .gitignore ├── packageAllIp.tcl ├── runGhdl.tcl ├── runModelsim.tcl └── runVivado.tcl /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "VHDL/psi_tb"] 2 | path = VHDL/psi_tb 3 | url = git@github.com:paulscherrerinstitute/psi_tb.git 4 | [submodule "VHDL/psi_common"] 5 | path = VHDL/psi_common 6 | url = git@github.com:paulscherrerinstitute/psi_common.git 7 | [submodule "TCL/PsiSim"] 8 | path = TCL/PsiSim 9 | url = git@github.com:paulscherrerinstitute/PsiSim.git 10 | [submodule "Python/PsiPyUtils"] 11 | path = Python/PsiPyUtils 12 | url = git@github.com:paulscherrerinstitute/PsiPyUtils.git 13 | [submodule "Python/TbGenerator"] 14 | path = Python/TbGenerator 15 | url = git@github.com:paulscherrerinstitute/TbGenerator.git 16 | [submodule "Python/VivadoScripting"] 17 | path = Python/VivadoScripting 18 | url = git@github.com:paulscherrerinstitute/VivadoScripting.git 19 | [submodule "Python/IseScripting"] 20 | path = Python/IseScripting 21 | url = git@github.com:paulscherrerinstitute/IseScripting.git 22 | [submodule "VHDL/en_cl_fix"] 23 | path = VHDL/en_cl_fix 24 | url = git@github.com:paulscherrerinstitute/en_cl_fix.git 25 | [submodule "VHDL/psi_fix"] 26 | path = VHDL/psi_fix 27 | url = git@github.com:paulscherrerinstitute/psi_fix.git 28 | [submodule "TCL/PsiIpPackage"] 29 | path = TCL/PsiIpPackage 30 | url = git@github.com:paulscherrerinstitute/PsiIpPackage.git 31 | [submodule "VivadoIp/vivadoIP_data_rec"] 32 | path = VivadoIp/vivadoIP_data_rec 33 | url = git@github.com:paulscherrerinstitute/vivadoIP_data_rec.git 34 | [submodule "VivadoIp/vivadoIP_clock_measure"] 35 | path = VivadoIp/vivadoIP_clock_measure 36 | url = git@github.com:paulscherrerinstitute/vivadoIP_clock_measure.git 37 | [submodule "VivadoIp/vivadoIP_spi_simple"] 38 | path = VivadoIp/vivadoIP_spi_simple 39 | url = git@github.com:paulscherrerinstitute/vivadoIP_spi_simple.git 40 | [submodule "VivadoIp/vivadoIP_axis_data_gen"] 41 | path = VivadoIp/vivadoIP_axis_data_gen 42 | url = git@github.com:paulscherrerinstitute/vivadoIP_axis_data_gen.git 43 | [submodule "VivadoIp/vivadoIP_mem_test"] 44 | path = VivadoIp/vivadoIP_mem_test 45 | url = git@github.com:paulscherrerinstitute/vivadoIP_mem_test.git 46 | [submodule "VHDL/psi_multi_stream_daq"] 47 | path = VHDL/psi_multi_stream_daq 48 | url = git@github.com:paulscherrerinstitute/psi_multi_stream_daq.git 49 | [submodule "VivadoIp/vivadoIP_psi_ms_daq"] 50 | path = VivadoIp/vivadoIP_psi_ms_daq 51 | url = git@github.com:paulscherrerinstitute/vivadoIP_psi_ms_daq.git 52 | [submodule "Python/PsiFpgaLibDependencies"] 53 | path = Python/PsiFpgaLibDependencies 54 | url = git@github.com:paulscherrerinstitute/PsiFpgaLibDependencies.git 55 | [submodule "VivadoIp/vivadoIP_i2c_devreg"] 56 | path = VivadoIp/vivadoIP_i2c_devreg 57 | url = git@github.com:paulscherrerinstitute/vivadoIP_i2c_devreg.git 58 | [submodule "VivadoIp/vivadoIP_power_sink"] 59 | path = VivadoIp/vivadoIP_power_sink 60 | url = git@github.com:paulscherrerinstitute/vivadoIP_power_sink.git 61 | [submodule "VivadoIp/vivadoIP_fpga_base"] 62 | path = VivadoIp/vivadoIP_fpga_base 63 | url = git@github.com:paulscherrerinstitute/vivadoIP_fpga_base.git 64 | [submodule "VivadoIp/vivadoIP_sync_edge_det"] 65 | path = VivadoIp/vivadoIP_sync_edge_det 66 | url = git@github.com:paulscherrerinstitute/vivadoIP_sync_edge_det.git 67 | [submodule "VivadoIp/vivadoIP_axi_mm_reader"] 68 | path = VivadoIp/vivadoIP_axi_mm_reader 69 | url = git@github.com:paulscherrerinstitute/vivadoIP_axi_mm_reader.git 70 | -------------------------------------------------------------------------------- /Changelog.md: -------------------------------------------------------------------------------- 1 | ## 2021.1 (23.08.2021) 2 | * TCL 3 | * [PsiIpPackage] (https://github.com/paulscherrerinstitute/PsiIpPackage) 2.4.0 4 | * VHDL 5 | * [en\_cl\_fix](https://github.com/paulscherrerinstitute/en_cl_fix) 1.1.8 6 | * [psi\_common](https://github.com/paulscherrerinstitute/psi_common) 2.17.0 7 | * [psi\_fix](https://github.com/paulscherrerinstitute/psi_fix) 3.1.0 8 | * VivadoIP 9 | * [vivadoIP_mem_test](https://github.com/paulscherrerinstitute/vivadoIP_mem_test) 1.3.0 10 | 11 | ## 2020.2 (20.10.2020) 12 | * TCL 13 | * [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) 2.5.0 14 | * [PsiIpPackage] (https://github.com/paulscherrerinstitute/PsiIpPackage) 2.3.0 15 | * VHDL 16 | * [en\_cl\_fix](https://github.com/paulscherrerinstitute/en_cl_fix) 1.1.5 17 | * [psi\_common](https://github.com/paulscherrerinstitute/psi_common) 2.13.0 18 | * [psi\_multi\_stream\_daq](https://github.com/paulscherrerinstitute/psi_multi_stream_daq) 1.2.3 19 | * [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) 2.6.0 20 | * [psi\_fix](https://github.com/paulscherrerinstitute/psi_fix) 2.4.1 21 | * Python 22 | * [IseScripting](https://github.com/paulscherrerinstitute/IseScripting) 3.1.0 23 | * [VivadoScripting](https://github.com/paulscherrerinstitute/VivadoScripting) 4.3.0 24 | * [PsiFpgaLibDependencies](https://github.com/paulscherrerinstitute/PsiFpgaLibDependencies) 2.1.0 25 | * [PsiPyUtils](https://github.com/paulscherrerinstitute/PsiPyUtils) 3.0.1 26 | * [TbGenerator](https://github.com/paulscherrerinstitute/TbGenerator) 3.0.4 27 | * VivadoIP 28 | * [vivadoIP_axi_mm_reader](https://github.com/paulscherrerinstitute/vivadoIP_axi_mm_reader) 1.0.0 29 | * [vivadoIP_axis_data_gen](https://github.com/paulscherrerinstitute/vivadoIP_axis_data_gen) 1.2.1 30 | * [vivadoIP_clock_measure](https://github.com/paulscherrerinstitute/vivadoIP_clock_measure) 1.5.0 31 | * [vivadoIP_data_rec](https://github.com/paulscherrerinstitute/vivadoIP_data_rec) 2.3.2 32 | * [vivadoIP_fpga_base](https://github.com/paulscherrerinstitute/vivadoIP_fpga_base) 1.4.0 33 | * [vivadoIP_i2c_devreg](https://github.com/paulscherrerinstitute/vivadoIP_i2c_devreg) 1.1.2 34 | * [vivadoIP_mem_test](https://github.com/paulscherrerinstitute/vivadoIP_mem_test) 1.3.0 35 | * [vivadoIP_power_sink](https://github.com/paulscherrerinstitute/vivadoIP_power_sink) 1.1.1 36 | * [vivadoIP_psi_ms_daq](https://github.com/paulscherrerinstitute/vivadoIP_psi_ms_daq) 1.2.1 37 | * [vivadoIP_spi_simple](https://github.com/paulscherrerinstitute/vivadoIP_spi_simple) 1.2.1 38 | * [vivadoIP_sync_det_edge](https://github.com/paulscherrerinstitute/vivadoIP_sync_det_edge) V1.00_20180125 39 | 40 | ## 2020.1 (12.05.2020) 41 | * TCL 42 | * [PsiIpPackage] (https://github.com/paulscherrerinstitute/PsiIpPackage) 2.2.0 43 | * VHDL 44 | * [psi\_common](https://github.com/paulscherrerinstitute/psi_common) 2.12.0 45 | * [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) 2.6.0 46 | * [psi\_fix](https://github.com/paulscherrerinstitute/psi_fix) 2.4.1 47 | * Python 48 | * [TbGenerator](https://github.com/paulscherrerinstitute/TbGenerator) 3.0.4 49 | * VivadoIP 50 | * [vivadoIP_axis_mm_reader](https://github.com/paulscherrerinstitute/vivadoIP_axis_mm_reader) 1.0.0 51 | * [vivadoIP_fpga_base](https://github.com/paulscherrerinstitute/vivadoIP_fpga_base) 1.4.0 52 | * [vivadoIP_sync_det_edge](https://github.com/paulscherrerinstitute/vivadoIP_sync_det_edge) V1.00_20180125 53 | 54 | ## 2019.4 (02.12.2019) 55 | * TCL 56 | * [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) 2.4.0 57 | * [PsiIpPackage] (https://github.com/paulscherrerinstitute/PsiIpPackage) 2.1.0 58 | * VHDL 59 | * [en\_cl\_fix](https://github.com/paulscherrerinstitute/en_cl_fix) 1.1.3 - fork of a a library provided by Enclustra GmbH 60 | * [Original Location](https://github.com/enclustra/en_cl_fix) 61 | * [psi\_common](https://github.com/paulscherrerinstitute/psi_common) 2.7.1 62 | * [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) 2.4.1 63 | * [psi\_fix](https://github.com/paulscherrerinstitute/psi_fix) 2.3.3 64 | * [psi\_multi\_stream\_daq](https://github.com/paulscherrerinstitute/psi_multi_stream_daq) 1.2.2 65 | * Python 66 | * [PsiPyUtils](https://github.com/paulscherrerinstitute/PsiPyUtils) 3.0.1 67 | * [IseScripting](https://github.com/paulscherrerinstitute/IseScripting) 3.0.1 68 | * [VivadoScripting](https://github.com/paulscherrerinstitute/VivadoScripting) 4.2.0 69 | * [TbGenerator](https://github.com/paulscherrerinstitute/TbGenerator) 3.0.2 70 | * [PsiFpgaLibDependencies](https://github.com/paulscherrerinstitute/PsiFpgaLibDependencies) 2.1.0 71 | * VivadoIp 72 | * [vivadoIP_axis_data_gen](https://github.com/paulscherrerinstitute/vivadoIP_axis_data_gen) 1.2.1 73 | * [vivadoIP_clock_measure](https://github.com/paulscherrerinstitute/vivadoIP_clock_measure) 1.4.1 74 | * [vivadoIP_data_rec](https://github.com/paulscherrerinstitute/vivadoIP_data_rec) 2.3.2 75 | * [vivadoIP_i2c_devreg](https://github.com/paulscherrerinstitute/vivadoIP_i2c_devreg) 1.1.1 76 | * [vivadoIP_mem_test](https://github.com/paulscherrerinstitute/vivadoIP_mem_test) 1.2.1 77 | * [vivadoIP_power_sink](https://github.com/paulscherrerinstitute/vivadoIP_power_sink) 1.1.1 78 | * [vivadoIP_psi_ms_daq](https://github.com/paulscherrerinstitute/vivadoIP_psi_ms_daq) 1.2.1 79 | * [vivadoIP_spi_simple](https://github.com/paulscherrerinstitute/vivadoIP_spi_simple) 1.2.1 80 | 81 | ## 2019.3 (02.08.2019) 82 | * TCL 83 | * [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) 2.2.0 84 | * [PsiIpPackage] (https://github.com/paulscherrerinstitute/PsiIpPackage) 2.0.0 85 | * VHDL 86 | * [en\_cl\_fix](https://github.com/paulscherrerinstitute/en_cl_fix) 1.1.3 - fork of a a library provided by Enclustra GmbH 87 | * [Original Location](https://github.com/enclustra/en_cl_fix) 88 | * [psi\_common](https://github.com/paulscherrerinstitute/psi_common) 2.5.1 89 | * [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) 2.2.4 90 | * [psi\_fix](https://github.com/paulscherrerinstitute/psi_fix) 2.3.2 91 | * [psi\_multi\_stream\_daq](https://github.com/paulscherrerinstitute/psi_multi_stream_daq) 1.2.0 92 | * Python 93 | * [PsiPyUtils](https://github.com/paulscherrerinstitute/PsiPyUtils) 3.0.1 94 | * [IseScripting](https://github.com/paulscherrerinstitute/IseScripting) 3.0.1 95 | * [VivadoScripting](https://github.com/paulscherrerinstitute/VivadoScripting) 4.0.1 96 | * [TbGenerator](https://github.com/paulscherrerinstitute/TbGenerator) 3.0.1 97 | * [PsiFpgaLibDependencies](https://github.com/paulscherrerinstitute/PsiFpgaLibDependencies) 2.1.0 98 | * VivadoIp 99 | * [vivadoIP_axis_data_gen](https://github.com/paulscherrerinstitute/vivadoIP_axis_data_gen) 1.2.0 100 | * [vivadoIP_clock_measure](https://github.com/paulscherrerinstitute/vivadoIP_clock_measure) 1.4.0 101 | * [vivadoIP_data_rec](https://github.com/paulscherrerinstitute/vivadoIP_data_rec) 2.3.0 102 | * [vivadoIP_mem_test](https://github.com/paulscherrerinstitute/vivadoIP_mem_test) 1.2.0 103 | * [vivadoIP_psi_ms_daq](https://github.com/paulscherrerinstitute/vivadoIP_psi_ms_daq) 1.2.0 104 | * [vivadoIP_spi_simple](https://github.com/paulscherrerinstitute/vivadoIP_spi_simple) 1.2.0 105 | 106 | ## 2019.2 (13.05.2019) 107 | * TCL 108 | * [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) 2.0.0 109 | * VHDL 110 | * [en\_cl\_fix](https://github.com/paulscherrerinstitute/en_cl_fix) 1.1.1 - fork of a a library provided by Enclustra GmbH 111 | * [Original Location](https://github.com/enclustra/en_cl_fix) 112 | * [psi\_common](https://github.com/paulscherrerinstitute/psi_common) 2.2.0 113 | * [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) 2.2.0 114 | * [psi\_fix](https://github.com/paulscherrerinstitute/psi_fix) 2.2.0 115 | * Python 116 | * [PsiPyUtils](https://github.com/paulscherrerinstitute/PsiPyUtils) 3.0.1 117 | * [IseScripting](https://github.com/paulscherrerinstitute/IseScripting) 3.0.1 118 | * [VivadoScripting](https://github.com/paulscherrerinstitute/VivadoScripting) 4.0.1 119 | * [TbGenerator](https://github.com/paulscherrerinstitute/TbGenerator) 3.0.0 120 | 121 | ## 2019.1 (07.01.2019) 122 | * TCL 123 | * [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) 2.0.0 124 | * VHDL 125 | * [en\_cl\_fix](https://github.com/paulscherrerinstitute/en_cl_fix) 1.1.1 - fork of a a library provided by Enclustra GmbH 126 | * [Original Location](https://github.com/enclustra/en_cl_fix) 127 | * [psi\_common](https://github.com/paulscherrerinstitute/psi_common) 2.1.0 128 | * [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) 2.1.0 129 | * [psi\_fix](https://github.com/paulscherrerinstitute/psi_fix) 2.1.0 130 | * Python 131 | * [PsiPyUtils](https://github.com/paulscherrerinstitute/PsiPyUtils) 2.1.0 132 | * [IseScripting](https://github.com/paulscherrerinstitute/IseScripting) 2.0.0 133 | * [VivadoScripting](https://github.com/paulscherrerinstitute/VivadoScripting) 3.0.0 134 | * [TbGenerator](https://github.com/paulscherrerinstitute/TbGenerator) 2.0.1 135 | 136 | ## 2018.1 (16.10.2018) 137 | * TCL 138 | * [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) 2.0.0 139 | * VHDL 140 | * [en\_cl\_fix](https://github.com/paulscherrerinstitute/en_cl_fix) 1.1.0 - fork of a a library provided by Enclustra GmbH 141 | * [Original Location](https://github.com/enclustra/en_cl_fix) 142 | * [psi\_common](https://github.com/paulscherrerinstitute/psi_common) 2.0.0 143 | * [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) 2.0.0 144 | * [psi\_fix](https://github.com/paulscherrerinstitute/psi_fix) 2.0.0 145 | * Python 146 | * [PsiPyUtils](https://github.com/paulscherrerinstitute/PsiPyUtils) 2.0.0 147 | * [IseScripting](https://github.com/paulscherrerinstitute/IseScripting) 2.0.0 148 | * [VivadoScripting](https://github.com/paulscherrerinstitute/VivadoScripting) 3.0.0 149 | * [TbGenerator](https://github.com/paulscherrerinstitute/TbGenerator) 2.0.0 150 | 151 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # General Information 2 | 3 | ## Maintainer 4 | Benoit Stef [benoit.stef@psi.ch] 5 | 6 | ## Authors 7 | * Oliver Bründler [oli.bruendler@gmx.ch] 8 | * Benoit Stef [benoit.stef@psi.ch] 9 | 10 | ## Changelog 11 | See [Changelog](Changelog.md) 12 | 13 | ## Purpose of the Repository 14 | This repository is a collection-repo. It contains all FPGA related libraries as submodules in exactly the directory structure required. The directory structure is important because different libraries reference to each other using relative paths. 15 | 16 | The repository will be updated regularly (roughly every 3 months) but it may not always contain the vey-newest state of all submodules in between the updates. You can update submodules individually if required. 17 | 18 | Alternatively only the repositories used can be checked out manually into the directory structure described below. 19 | 20 | * TCL 21 | * [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) 22 | * VHDL 23 | * [psi\_common](https://github.com/paulscherrerinstitute/psi_common) 24 | * [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) 25 | * [psi\_fix](https://github.com/paulscherrerinstitute/psi_fix) 26 | * [en\_cl\_fix](https://github.com/paulscherrerinstitute/en_cl_fix) (fork of a a library provided by Enclustra GmbH) 27 | * [Original Location](https://github.com/enclustra/en_cl_fix) 28 | * Python 29 | * [PsiPyUtils](https://github.com/paulscherrerinstitute/PsiPyUtils) 30 | * [IseScripting](https://github.com/paulscherrerinstitute/IseScripting) 31 | * [VivadoScripting](https://github.com/paulscherrerinstitute/VivadoScripting) 32 | * [TbGenerator](https://github.com/paulscherrerinstitute/TbGenerator) 33 | 34 | ## Cloning 35 | Because the repository contains submodules, it must be cloned with the *--recurse-submodules* option: 36 | 37 | ``` 38 | git clone --recurse-submodules git@github.com:paulscherrerinstitute/psi_fpga_all.git 39 | ``` 40 | 41 | 42 | 43 | -------------------------------------------------------------------------------- /scripts/.gitignore: -------------------------------------------------------------------------------- 1 | #Ignore everything except the file types required 2 | * 3 | !*.tcl 4 | !.gitignore 5 | 6 | #Ignore artifacts from runs 7 | psi_sim_run.tcl -------------------------------------------------------------------------------- /scripts/packageAllIp.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | # Copyright (c) 2019 by Paul Scherrer Institute, Switzerland 3 | # All rights reserved. 4 | # Authors: Oliver Bruendler 5 | ############################################################################## 6 | 7 | #Setup 8 | set myPath [pwd] 9 | 10 | #Package 11 | cd $myPath/../VivadoIp/vivadoIP_axis_data_gen/scripts 12 | source package.tcl 13 | 14 | cd $myPath/../VivadoIp/vivadoIP_clock_measure/scripts 15 | source package.tcl 16 | 17 | cd $myPath/../VivadoIp/vivadoIP_data_rec/scripts 18 | source package.tcl 19 | 20 | cd $myPath/../VivadoIp/vivadoIP_mem_test/scripts 21 | source package.tcl 22 | 23 | cd $myPath/../VivadoIp/vivadoIP_psi_ms_daq/scripts 24 | source package.tcl 25 | 26 | cd $myPath/../VivadoIp/vivadoIP_spi_simple/scripts 27 | source package.tcl 28 | 29 | cd $myPath/../VivadoIp/vivadoIP_i2c_devreg/scripts 30 | source package.tcl 31 | 32 | cd $myPath/../VivadoIp/vivadoIP_power_sink/scripts 33 | source package.tcl 34 | 35 | #Go back to initial directory 36 | cd $myPath 37 | 38 | -------------------------------------------------------------------------------- /scripts/runGhdl.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | # Copyright (c) 2018 by Paul Scherrer Institute, Switzerland 3 | # All rights reserved. 4 | # Authors: Oliver Bruendler 5 | ############################################################################## 6 | 7 | #Load dependencies 8 | source ../TCL/PsiSim/PsiSim.tcl 9 | namespace import psi::sim::* 10 | 11 | #Initialize Simulation 12 | init -ghdl 13 | 14 | #Configure 15 | set myPath [pwd] 16 | 17 | cd $myPath/../VHDL/psi_common/sim 18 | source config.tcl 19 | 20 | cd $myPath/../VHDL/psi_fix/sim 21 | source config.tcl 22 | 23 | #TB not GHDL compatible! 24 | #cd $myPath/../VHDL/psi_multi_stream_daq/sim 25 | #source config.tcl 26 | 27 | cd $myPath/../VivadoIp/vivadoIP_axis_data_gen/sim 28 | source config.tcl 29 | 30 | cd $myPath/../VivadoIp/vivadoIP_clock_measure/sim 31 | source config.tcl 32 | 33 | #TB not GHDL compatible! 34 | #cd $myPath/../VivadoIp/vivadoIP_data_rec/sim 35 | #source config.tcl 36 | 37 | cd $myPath/../VivadoIp/vivadoIP_mem_test/sim 38 | source config.tcl 39 | 40 | cd $myPath/../VivadoIp/vivadoIP_spi_simple/sim 41 | source config.tcl 42 | 43 | cd $myPath/../VivadoIp/vivadoIP_i2c_devreg/sim 44 | source config.tcl 45 | 46 | cd $myPath/../VivadoIp/vivadoIP_axi_mm_reader/sim 47 | source config.tcl 48 | 49 | #cd $myPath/../VivadoIp/vivadoIP_power_sink/sim 50 | #Does not have a self-checking TB because power consumption/toggling/optimization cannot be simulated! 51 | 52 | cd $myPath 53 | 54 | #Run Simulation 55 | puts "------------------------------" 56 | puts "-- Compile" 57 | puts "------------------------------" 58 | compile_files -all -clean 59 | puts "------------------------------" 60 | puts "-- Run" 61 | puts "------------------------------" 62 | run_tb -all 63 | puts "------------------------------" 64 | puts "-- Check" 65 | puts "------------------------------" 66 | 67 | run_check_errors "###ERROR###" -------------------------------------------------------------------------------- /scripts/runModelsim.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | # Copyright (c) 2018 by Paul Scherrer Institute, Switzerland 3 | # All rights reserved. 4 | # Authors: Oliver Bruendler 5 | ############################################################################## 6 | 7 | #Load dependencies 8 | source ../TCL/PsiSim/PsiSim.tcl 9 | namespace import psi::sim::* 10 | 11 | #Initialize Simulation 12 | init 13 | 14 | #Configure 15 | set myPath [pwd] 16 | 17 | cd $myPath/../VHDL/psi_common/sim 18 | source config.tcl 19 | 20 | cd $myPath/../VHDL/psi_fix/sim 21 | source config.tcl 22 | 23 | cd $myPath/../VHDL/psi_multi_stream_daq/sim 24 | source config.tcl 25 | 26 | cd $myPath/../VivadoIp/vivadoIP_axis_data_gen/sim 27 | source config.tcl 28 | 29 | cd $myPath/../VivadoIp/vivadoIP_clock_measure/sim 30 | source config.tcl 31 | 32 | cd $myPath/../VivadoIp/vivadoIP_data_rec/sim 33 | source config.tcl 34 | 35 | cd $myPath/../VivadoIp/vivadoIP_mem_test/sim 36 | source config.tcl 37 | 38 | cd $myPath/../VivadoIp/vivadoIP_spi_simple/sim 39 | source config.tcl 40 | 41 | cd $myPath/../VivadoIp/vivadoIP_i2c_devreg/sim 42 | source config.tcl 43 | 44 | cd $myPath/../VivadoIp/vivadoIP_axi_mm_reader/sim 45 | source config.tcl 46 | 47 | #cd $myPath/../VivadoIp/vivadoIP_power_sink/sim 48 | #Does not have a self-checking TB because power consumption/toggling/optimization cannot be simulated! 49 | 50 | cd $myPath 51 | 52 | #Run Simulation 53 | puts "------------------------------" 54 | puts "-- Compile" 55 | puts "------------------------------" 56 | compile_files -all -clean 57 | puts "------------------------------" 58 | puts "-- Run" 59 | puts "------------------------------" 60 | run_tb -all 61 | puts "------------------------------" 62 | puts "-- Check" 63 | puts "------------------------------" 64 | 65 | run_check_errors "###ERROR###" -------------------------------------------------------------------------------- /scripts/runVivado.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | # Copyright (c) 2018 by Paul Scherrer Institute, Switzerland 3 | # All rights reserved. 4 | # Authors: Oliver Bruendler 5 | ############################################################################## 6 | 7 | #Load dependencies 8 | source -quiet ../TCL/PsiSim/PsiSim.tcl 9 | 10 | #Import psi::sim library 11 | namespace import psi::sim::* 12 | 13 | #Initialize Simulation 14 | init -vivado 15 | 16 | #Configure 17 | set myPath [pwd] 18 | 19 | cd $myPath/../VHDL/psi_common/sim 20 | source -quiet config.tcl 21 | 22 | #TB not Vivado compatible! 23 | #cd $myPath/../VHDL/psi_fix/sim 24 | #source -quiet config.tcl 25 | 26 | #TB not Vivado compatible! 27 | #cd $myPath/../VHDL/psi_multi_stream_daq/sim 28 | #source -quiet config.tcl 29 | 30 | #TB not Vivado compatible! 31 | #cd $myPath/../VivadoIp/vivadoIP_axis_data_gen/sim 32 | #source -quiet config.tcl 33 | 34 | #TB not Vivado compatible! 35 | #cd $myPath/../VivadoIp/vivadoIP_clock_measure/sim 36 | #source -quiet config.tcl 37 | 38 | #TB not Vivado compatible! 39 | #cd $myPath/../VivadoIp/vivadoIP_data_rec/sim 40 | #source -quiet config.tcl 41 | 42 | #TB not Vivado compatible! 43 | #cd $myPath/../VivadoIp/vivadoIP_mem_test/sim 44 | #source -quiet config.tcl 45 | 46 | #TB not Vivado compatible! 47 | #cd $myPath/../VivadoIp/vivadoIP_spi_simple/sim 48 | #source -quiet config.tcl 49 | 50 | #TB not Vivado compatible! 51 | #cd $myPath/../VivadoIp/vivadoIP_i2c_devreg/sim 52 | #source config.tcl 53 | 54 | #cd $myPath/../VivadoIp/vivadoIP_power_sink/sim 55 | #Does not have a self-checking TB because power consumption/toggling/optimization cannot be simulated! 56 | 57 | cd $myPath 58 | 59 | #Run Simulation 60 | puts "------------------------------" 61 | puts "-- Compile" 62 | puts "------------------------------" 63 | compile_files -all -clean 64 | puts "------------------------------" 65 | puts "-- Run" 66 | puts "------------------------------" 67 | run_tb -all 68 | puts "------------------------------" 69 | puts "-- Check" 70 | puts "------------------------------" 71 | 72 | run_check_errors "###ERROR###" --------------------------------------------------------------------------------