├── .gitignore ├── .gitmodules ├── README.md ├── doc ├── Microchip │ ├── .gitignore │ └── usb200c.zip ├── USB Controller Registermap.pdf └── USB Pad Configuration.pdf ├── firmware ├── .gitignore ├── Makefile ├── README.md ├── application.fs ├── descriptors.fs ├── device.fs ├── hex-display.fs ├── io-access.fs ├── main.fs └── usb-defs.fs ├── perl ├── crc16.pl ├── crc5.pl └── crcdes.pdf ├── rtl ├── MegaWizard │ ├── .qsys_edit │ │ ├── clkctrl.xml │ │ ├── clkctrl_schematic.nlv │ │ ├── filters.xml │ │ └── preferences.xml │ ├── clkctrl.qsys │ ├── clkctrl.sopcinfo │ ├── clkctrl │ │ ├── clkctrl.bsf │ │ ├── clkctrl.cmp │ │ ├── clkctrl.csv │ │ ├── clkctrl.html │ │ ├── clkctrl.ppf │ │ ├── clkctrl.spd │ │ ├── clkctrl.xml │ │ ├── clkctrl_bb.v │ │ ├── clkctrl_generation.rpt │ │ ├── clkctrl_generation_previous.rpt │ │ ├── clkctrl_inst.v │ │ ├── clkctrl_inst.vhd │ │ ├── simulation │ │ │ ├── aldec │ │ │ │ └── rivierapro_setup.tcl │ │ │ ├── cadence │ │ │ │ ├── cds.lib │ │ │ │ ├── cds_libs │ │ │ │ │ └── altclkctrl_0.cds.lib │ │ │ │ ├── hdl.var │ │ │ │ └── ncsim_setup.sh │ │ │ ├── clkctrl.sip │ │ │ ├── clkctrl.v │ │ │ ├── mentor │ │ │ │ └── msim_setup.tcl │ │ │ ├── submodules │ │ │ │ └── clkctrl_altclkctrl_0.v │ │ │ └── synopsys │ │ │ │ ├── vcs │ │ │ │ └── vcs_setup.sh │ │ │ │ └── vcsmx │ │ │ │ ├── synopsys_sim.setup │ │ │ │ └── vcsmx_setup.sh │ │ └── synthesis │ │ │ ├── clkctrl.debuginfo │ │ │ ├── clkctrl.qip │ │ │ ├── clkctrl.v │ │ │ └── submodules │ │ │ └── clkctrl_altclkctrl_0.v │ ├── fifo16x8.qip │ ├── fifo16x8.v │ ├── fifo16x8_bb.v │ ├── fifo16x8_show_ahead.qip │ ├── fifo16x8_show_ahead.v │ ├── fifo16x8_show_ahead_bb.v │ ├── pll.bsf │ ├── pll.cmp │ ├── pll.ppf │ ├── pll.qip │ ├── pll.sip │ ├── pll.spd │ ├── pll.v │ ├── pll │ │ ├── pll_0002.qip │ │ └── pll_0002.v │ ├── pll_sim.f │ ├── pll_sim │ │ ├── aldec │ │ │ └── rivierapro_setup.tcl │ │ ├── cadence │ │ │ ├── cds.lib │ │ │ ├── hdl.var │ │ │ └── ncsim_setup.sh │ │ ├── mentor │ │ │ └── msim_setup.tcl │ │ ├── pll.vo │ │ └── synopsys │ │ │ ├── vcs │ │ │ └── vcs_setup.sh │ │ │ └── vcsmx │ │ │ ├── synopsys_sim.setup │ │ │ └── vcsmx_setup.sh │ ├── ram1kx16.qip │ ├── ram1kx16.v │ ├── ram1kx16_bb.v │ ├── rom4kx16.qip │ ├── rom4kx16.v │ └── rom4kx16_bb.v ├── board_io.sv ├── interfaces.sv ├── ioaddr.sv ├── sync_reset.sv ├── top_c5gx.sv ├── types.sv ├── usb_cdr.sv ├── usb_device_controller.sv ├── usb_filter.sv ├── usb_reset.sv ├── usb_rx.sv ├── usb_sie.sv ├── usb_transceiver.sv ├── usb_tx.sv ├── wb_intercon.sv ├── wb_ram.sv └── wb_rom.sv └── sim ├── tb_top.sv ├── tb_usb_cdr.sv ├── tb_usb_reset.sv ├── tb_usb_rx.sv ├── tb_usb_sie.sv ├── tb_usb_transceiver.sv └── tb_usb_tx.sv /.gitignore: -------------------------------------------------------------------------------- 1 | syn/ 2 | 3 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "J1_WB"] 2 | path = J1_WB 3 | url = https://github.com/pbing/J1_WB.git 4 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FPGA USB 1.1 Low-Speed Implementation 2 | 3 | Derived from an example [application](https://github.com/pbing/USB/tree/master/doc/Microchip) which emulates a mouse. 4 | The cursor will move in a continual octagon. 5 | 6 | ## Status 7 | - FPGA proven as additional mouse for Windows 10 8 | - Does not work with macOS -- although USB continous IN packages can be observed with a logic analyzer. 9 | 10 | ## Installation 11 | ```shell 12 | git clone https://github.com/pbing/USB.git 13 | cd USB 14 | git submodule update --init --recursive 15 | ``` 16 | 17 | ## Used Parts 18 | - [Cyclone V GX Starter Kit](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830&PartNo=1) 19 | 20 | - The USB D+ and D- pads were [configured](https://github.com/pbing/USB/blob/master/doc/USB%20Pad%20Configuration.pdf) 21 | for low-speed (1.5 Mbit/s). 22 | 23 | ## Other IP 24 | - [J1 CPU with Wishbone interface](https://github.com/pbing/J1_WB) 25 | -------------------------------------------------------------------------------- /doc/Microchip/.gitignore: -------------------------------------------------------------------------------- 1 | usb200c/ 2 | -------------------------------------------------------------------------------- /doc/Microchip/usb200c.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pbing/USB/9aadca37b94164f224894abb201678b2367df8bd/doc/Microchip/usb200c.zip -------------------------------------------------------------------------------- /doc/USB Controller Registermap.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pbing/USB/9aadca37b94164f224894abb201678b2367df8bd/doc/USB Controller Registermap.pdf -------------------------------------------------------------------------------- /doc/USB Pad Configuration.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pbing/USB/9aadca37b94164f224894abb201678b2367df8bd/doc/USB Pad Configuration.pdf -------------------------------------------------------------------------------- /firmware/.gitignore: -------------------------------------------------------------------------------- 1 | *.mif 2 | *.lst 3 | -------------------------------------------------------------------------------- /firmware/Makefile: -------------------------------------------------------------------------------- 1 | # Create firmware 2 | 3 | FORTH = /usr/local/opt/SwiftForth/bin/osx/sf 4 | #FORTH = gforth -e 5 | 6 | VPATH = ../J1_WB/j1_forth 7 | 8 | SRC = crossj1.fs \ 9 | basewords.fs \ 10 | nuc.fs \ 11 | main.fs 12 | 13 | .PHONY: sim syn 14 | 15 | j1.mif j1.lst: $(SRC) *.fs 16 | $(FORTH) main.fs 17 | 18 | sim: j1.mif 19 | cp $^ ../sim 20 | 21 | syn: j1.mif 22 | cp $^ ../syn 23 | -------------------------------------------------------------------------------- /firmware/README.md: -------------------------------------------------------------------------------- 1 | # Edit Makefile 2 | 3 | 1. Change variable FORTH to SwiftForth or GForth binary. 4 | 5 | 2. Compile the firmware and provide the MIF to Modelsim and Quartus II 6 | 7 | ```shell 8 | make sim syn 9 | ``` 10 | -------------------------------------------------------------------------------- /firmware/application.fs: -------------------------------------------------------------------------------- 1 | \ Application 2 | module[ application" 3 | 4 | false constant DEBUG 5 | 6 | include usb-defs.fs 7 | include io-access.fs 8 | include descriptors.fs 9 | include device.fs 10 | 11 | ROM 12 | : main ( --) 13 | /mouse 14 | begin do-transfer again ; 15 | 16 | ]module 17 | -------------------------------------------------------------------------------- /firmware/descriptors.fs: -------------------------------------------------------------------------------- 1 | \ Descriptors 2 | 3 | ROM 4 | create report-descriptor1 5 | $05 c, $01 c, \ usage page (generic desktop) 6 | $09 c, $02 c, \ usage mouse 7 | $a1 c, $01 c, \ collection (application) 8 | $09 c, $01 c, \ usage (pointer) 9 | $a1 c, $00 c, \ collection (physical) 10 | $05 c, $09 c, \ usage page (buttons) 11 | $19 c, $01 c, \ usage minimum (1) 12 | $29 c, $03 c, \ usage maximum (3) 13 | $15 c, $00 c, \ logical minimum (0) 14 | $25 c, $01 c, \ logical maximum (1) 15 | $95 c, $03 c, \ report count (3) 16 | $75 c, $01 c, \ report size (1 bit) 17 | $81 c, $02 c, \ input (variable, 3 bits) 18 | $95 c, $01 c, \ report count (1) 19 | $75 c, $05 c, \ report size (5 bits) 20 | $81 c, $01 c, \ input (constant, 5 bit padding) 21 | 22 | $05 c, $01 c, \ usage page (generic desktop) 23 | $09 c, $30 c, \ usage X 24 | $09 c, $31 c, \ usage Y 25 | $15 c, $81 c, \ logical minimum -127 26 | $25 c, $7F c, \ logical maximum 127 27 | $75 c, $08 c, \ report size (8 bits) 28 | $95 c, $02 c, \ report count (2) 29 | $81 c, $06 c, \ input (relative+variable, 2 position bytes X & Y) 30 | $c0 c, \ end collection (physical), 31 | $c0 c, \ end collection (application) 32 | 33 | #50 constant size-report-descriptor1 34 | 35 | 36 | create device-descriptor 37 | #18 c, \ bLength 38 | %device c, \ bDescriptorType 39 | $0110 h, \ bcdUSB 40 | $00 c, \ bDeviceClass 41 | $00 c, \ bDeviceSubClass 42 | $00 c, \ bDeviceProtocol 43 | $08 c, \ bMaxPacketSize0 44 | $04d8 h, \ idVendor 45 | $0001 h, \ idProduct 46 | $0200 h, \ bcdDevice 47 | $01 c, \ iManufacturer 48 | $02 c, \ iProduct 49 | $00 c, \ iSerialNumber 50 | $01 c, \ bNumConfigurations 51 | 52 | 53 | create configuration-descriptor 54 | #9 c, \ bLength 55 | %configuration c, \ bDescriptorType 56 | 34 h, \ wTotalLength (9+9+9+7) 57 | $01 c, \ bNumInterfaces 58 | $01 c, \ bConfigurationValue 59 | $00 c, \ iConfiguration 60 | $A0 c, \ bmAttributes 61 | 50 c, \ bMaxPower 62 | \ interface-descriptor 63 | #9 c, \ bLength 64 | %interface c, \ bDescriptorType 65 | $00 c, \ bInterfaceNumber 66 | $00 c, \ bAlternateSetting 67 | $01 c, \ bNumEndpoints 68 | $03 c, \ bInterfaceClass (Human interface device) 69 | $01 c, \ bInterfaceSubClass (Boot interface) 70 | $02 c, \ bInterfaceProtocol (Mouse) 71 | $00 c, \ iInterface 72 | \ hid-descriptor 73 | meta there target constant hid-descriptor 74 | #9 c, \ bLength 75 | %hid c, \ bDescriptorType 76 | $0100 h, \ bcdHID 77 | $00 c, \ bCountryCode 78 | $01 c, \ bNumDescriptors 79 | %report c, \ bDescriptorType 80 | size-report-descriptor1 h, \ wDescriptorLength 81 | \ endpoint-descriptor1 82 | #7 c, \ bLength 83 | %endpoint c, \ bDescriptorType 84 | $81 c, \ bEndPointAddress (IN1) 85 | $03 c, \ bmAttributes (Interrupt) 86 | #8 h, \ wMaxPacketSize 87 | #10 c, \ bInterval (10 ms) 88 | 89 | #34 constant size-configuration-descriptor 90 | 91 | 92 | \ LANGID 93 | create string-descriptor0 94 | #4 c, \ bLength 95 | %string c, \ bDescriptorType 96 | $409 h, \ wLANGID[0] 97 | 98 | \ iManufacturer 99 | create string-descriptor1 100 | #54 c, \ bLength 101 | %string c, \ bDescriptorType 102 | 'M' h, \ bString 103 | 'i' h, 104 | 'c' h, 105 | 'r' h, 106 | 'o' h, 107 | 'c' h, 108 | 'h' h, 109 | 'i' h, 110 | 'p' h, 111 | bl h, 112 | 'T' h, 113 | 'e' h, 114 | 'c' h, 115 | 'h' h, 116 | 'n' h, 117 | 'o' h, 118 | 'l' h, 119 | 'o' h, 120 | 'g' h, 121 | 'y' h, 122 | ',' h, 123 | bl h, 124 | 'I' h, 125 | 'n' h, 126 | 'c' h, 127 | '.' h, 128 | 129 | 130 | \ iProduct 131 | create string-descriptor2 132 | #92 c, 133 | %string c, 134 | 'P' h, 135 | 'i' h, 136 | 'c' h, 137 | '1' h, 138 | '6' h, 139 | 'C' h, 140 | '7' h, 141 | '4' h, 142 | '5' h, 143 | '/' h, 144 | '7' h, 145 | '6' h, 146 | '5' h, 147 | bl h, 148 | 'U' h, 149 | 'S' h, 150 | 'B' h, 151 | bl h, 152 | 'S' h, 153 | 'u' h, 154 | 'p' h, 155 | 'p' h, 156 | 'o' h, 157 | 'r' h, 158 | 't' h, 159 | bl h, 160 | 'F' h, 161 | 'i' h, 162 | 'r' h, 163 | 'm' h, 164 | 'w' h, 165 | 'a' h, 166 | 'r' h, 167 | 'e' h, 168 | ',' h, 169 | bl h, 170 | 'V' h, 171 | 'e' h, 172 | 'r' h, 173 | '.' h, 174 | bl h, 175 | '2' h, 176 | '.' h, 177 | '0' h, 178 | '0' h, 179 | -------------------------------------------------------------------------------- /firmware/hex-display.fs: -------------------------------------------------------------------------------- 1 | \ 4-digit HEX display 2 | 3 | ROM 4 | create hex-display-table 5 | $3f , $06 , $5b , $4f , $66 , $6d , $7d , $07 , \ 0 1 2 3 4 5 6 7 6 | $7f , $6f , $77 , $7c , $39 , $5e , $79 , $71 , \ 8 9 A b C d E F 7 | 8 | \ convert number n to digit and display it at addr 9 | : hex-display-digit! ( n addr -- ) >r cells hex-display-table + @ r> ! ; 10 | 11 | \ use SW[0:3] in order to select different outputs 12 | : hex-select ( -- ) 13 | io-sw @ h# 1 and if 14 | \ SW[0] 15 | h# 0 io-hex0 hex-display-digit! 16 | h# 1 io-hex1 hex-display-digit! 17 | h# 2 io-hex2 hex-display-digit! 18 | h# 3 io-hex3 hex-display-digit! 19 | else io-sw @ h# 2 and if 20 | \ SW[1] 21 | h# 4 io-hex0 hex-display-digit! 22 | h# 5 io-hex1 hex-display-digit! 23 | h# 6 io-hex2 hex-display-digit! 24 | h# 7 io-hex3 hex-display-digit! 25 | else io-sw @ h# 4 and if 26 | \ SW[2] 27 | h# 8 io-hex0 hex-display-digit! 28 | h# 9 io-hex1 hex-display-digit! 29 | h# a io-hex2 hex-display-digit! 30 | h# b io-hex3 hex-display-digit! 31 | else io-sw @ h# 8 and if 32 | \ SW[3] 33 | h# c io-hex0 hex-display-digit! 34 | h# d io-hex1 hex-display-digit! 35 | h# e io-hex2 hex-display-digit! 36 | h# f io-hex3 hex-display-digit! 37 | else 38 | \ SW[0:3] off 39 | h# 40 dup io-hex0 ! dup io-hex1 ! dup io-hex2 ! io-hex3 ! 40 | then then then then ; 41 | -------------------------------------------------------------------------------- /firmware/io-access.fs: -------------------------------------------------------------------------------- 1 | \ I/O addresses 2 | \ same as in rtl/ioaddr.sv 3 | 4 | \ LED 5 | $5000 constant io-ledg 6 | $5002 constant io-ledr 7 | 8 | \ HEX display 9 | $5010 constant io-hex0 10 | $5012 constant io-hex1 11 | $5014 constant io-hex2 12 | $5016 constant io-hex3 13 | 14 | \ keys and switches 15 | $5020 constant io-key 16 | $5022 constant io-sw 17 | 18 | \ USB endpoints and control registers 19 | $6000 constant io-txbuf-data 20 | $6002 constant io-txbuf-control 21 | 22 | $6004 constant io-rxbuf-data 23 | $6006 constant io-rxbuf-control 24 | 25 | : txbuf-wait-empty ( -- ) begin io-txbuf-control @ h# 1 and until ; 26 | : txbuf-c! ( 8b -- ) io-txbuf-data ! ; 27 | : txbuf-! ( 16b -- ) hilo txbuf-c! txbuf-c! ; 28 | 29 | : rxbuf-c@ ( -- 8b ) begin io-rxbuf-control @ h# 1 and while repeat io-rxbuf-data @ ; 30 | : rxbuf-@ ( -- 16b ) rxbuf-c@ rxbuf-c@ lohi-pack ; 31 | 32 | \ Receive ACK and return true. 33 | \ If timeout return false. 34 | : ack? ( -- f) 35 | d# 200 \ timeout counter (16..18 bit times) 36 | begin io-rxbuf-control @ h# 1 and while 37 | 1- dup 0= if exit then 38 | repeat drop 39 | io-rxbuf-data @ %ack = ; 40 | -------------------------------------------------------------------------------- /firmware/main.fs: -------------------------------------------------------------------------------- 1 | \ Compile the firmware 2 | 3 | include ../J1_WB/j1_forth/crossj1.fs 4 | include ../J1_WB/j1_forth/basewords.fs 5 | 6 | target 7 | 8 | \ low high type name 9 | $0000 $1fff cdata section ROM \ ROM 10 | $2000 $27ff udata section URAM \ uninitalized RAM 11 | \ ... ... idata section IRAM \ initalized RAM 12 | 13 | ROM 14 | 4 org 15 | 16 | module[ everything" 17 | 18 | include ../J1_WB/j1_forth/nuc.fs 19 | 20 | include application.fs 21 | 22 | ]module 23 | 24 | 0 org 25 | 26 | code 0jump 27 | main ubranch 28 | end-code 29 | 30 | \ ********************************************************************** 31 | 32 | meta 33 | hex 34 | 35 | : create-output-file w/o create-file throw to outfile ; 36 | 37 | \ \ for RTL simulation 38 | \ s" j1.hex" create-output-file 39 | \ :noname 40 | \ 2000 0 do 41 | \ i t@ s>d <# # # # # #> type cr 42 | \ 2 +loop 43 | \ ; execute 44 | 45 | \ for Quartus II synthesis 46 | s" j1.mif" create-output-file 47 | :noname 48 | s" -- Quartus II generated Memory Initialization File (.mif)" type cr 49 | s" WIDTH=16;" type cr 50 | s" DEPTH=4096;" type cr 51 | s" ADDRESS_RADIX=HEX;" type cr 52 | s" DATA_RADIX=HEX;" type cr 53 | s" CONTENT BEGIN" type cr 54 | 55 | 2000 0 do 56 | 4 spaces 57 | i 2/ s>d <# # # # # #> type s" : " type 58 | i t@ s>d <# # # # # #> type [char] ; emit cr 59 | 2 +loop 60 | 61 | s" END;" type cr 62 | ; execute 63 | 64 | s" j1.lst" create-output-file 65 | 0 1000 disassemble-block 66 | 67 | bye 68 | -------------------------------------------------------------------------------- /firmware/usb-defs.fs: -------------------------------------------------------------------------------- 1 | \ USB definitions 2 | 3 | \ token PID 4 | $e1 constant %out 5 | $69 constant %in 6 | $a5 constant %sof 7 | $2d constant %setup 8 | \ data PID 9 | $c3 constant %data0 10 | $4b constant %data1 11 | $87 constant %data2 12 | $0f constant %mdata 13 | \ handshake PID 14 | $d2 constant %ack 15 | $5a constant %nak 16 | $1e constant %stall 17 | $96 constant %nyet 18 | \ special PID 19 | $3c constant %pre 20 | $3c constant %err 21 | $78 constant %ping 22 | 23 | \ request types 24 | $00 constant %host-to-device 25 | $01 constant %host-to-interface 26 | $02 constant %host-to-endpoint 27 | $80 constant %device-to-host 28 | $81 constant %interface-to-host 29 | $82 constant %endpoint-to-host 30 | 31 | \ standard code requests 32 | 0 constant %get-status 33 | 1 constant %clear-feature 34 | 3 constant %set-feature 35 | 5 constant %set-address 36 | 6 constant %get-descriptor 37 | 7 constant %set-descriptor 38 | 8 constant %get-configuration 39 | 9 constant %set-configuration 40 | 10 constant %get-interface 41 | 11 constant %set-interface 42 | 12 constant %synch-frame 43 | 44 | \ descriptor types 45 | 1 constant %device 46 | 2 constant %configuration 47 | 3 constant %string 48 | 4 constant %interface 49 | 5 constant %endpoint 50 | \ 6 constant %device-qualifier 51 | \ 7 constant %other-speed-configuration 52 | \ 8 constant %interface-power 53 | 33 constant %hid 54 | 34 constant %report 55 | \ 35 constant %physical 56 | 57 | \ standard feature selectors 58 | \ 0 constant %endpoint-halt 59 | \ 1 constant %device-remote-wakeup 60 | \ 2 constant %test-mode -------------------------------------------------------------------------------- /perl/crc16.pl: -------------------------------------------------------------------------------- 1 | #! /usr/bin/perl 2 | ## usage: 3 | ## crc16 nrzstream 4 | ## nrz stream is sent in left to right order 5 | ## generated crc should also be sent out in left to right order 6 | 7 | sub xor16 { 8 | local(@x) = @_[0..15]; 9 | local(@y) = @_[16..31]; 10 | local(@results16) = (); 11 | 12 | for($j=0;$j<16;$j++) { 13 | if (shift(@x) eq shift(@y)) { 14 | push(@results16, '0'); 15 | } else { 16 | push(@results16, '1'); 17 | } 18 | } 19 | return(@results16[0..15]); 20 | } 21 | 22 | { 23 | local($st_data) = $ARGV[0]; 24 | local(@G) = ('1','0','0','0','0','0','0','0','0','0','0','0','0','1','0','1'); 25 | local(@hold) = ('1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1'); 26 | local(@data) = split (//,$st_data); 27 | 28 | if (scalar(@data) > 0) { 29 | loop16: 30 | while (scalar(@data) > 0) { 31 | $nextb=shift(@data); 32 | 33 | if (($nextb ne "0") && ($nextb ne "1")) { 34 | next loop16; 35 | } ## comment character 36 | 37 | if ($nextb eq shift(@hold)) { 38 | push(@hold, '0'); 39 | } else { 40 | push(@hold, '0'); 41 | @hold = &xor16(@hold,@G); 42 | } 43 | } 44 | } 45 | 46 | ## invert shift reg contents to generate CRC field 47 | for ($i=0;$i<=$#hold;$i++) { 48 | if (@hold[$i] eq "1") { 49 | print("0"); 50 | } else { 51 | print("1"); 52 | } 53 | } 54 | print "\n"; 55 | } 56 | -------------------------------------------------------------------------------- /perl/crc5.pl: -------------------------------------------------------------------------------- 1 | #! /usr/bin/perl 2 | ## crc5 nrzstream 3 | ## e.g. crc5 1000111 4 | ## nrz stream is sent in left to right order 5 | ## generated crc should also be sent out in left to right order 6 | 7 | sub xor5 { 8 | local(@x) = @_[0..4]; 9 | local(@y) = @_[5..9]; 10 | local(@results5) = (); 11 | 12 | for($j=0;$j<5;$j++) { 13 | if (shift(@x) eq shift(@y)) { 14 | push(@results5, '0'); 15 | } else { 16 | push(@results5, '1'); 17 | } 18 | } 19 | return(@results5[0..4]); 20 | } 21 | 22 | { 23 | local($st_data) = $ARGV[0]; 24 | local(@G) = ('0','0','1','0','1'); 25 | local(@hold) = ('1','1','1','1','1'); 26 | local(@data) = split (//,$st_data); 27 | 28 | if (scalar(@data) > 0) { 29 | loop5: 30 | while (scalar(@data) > 0) { 31 | $nextb=shift(@data); 32 | 33 | if (($nextb ne "0") && ($nextb ne "1")) { 34 | next loop5; 35 | } ## comment character 36 | 37 | if ($nextb eq shift(@hold)) { 38 | push(@hold, '0'); 39 | } else { 40 | push(@hold, '0'); 41 | @hold = &xor5(@hold,@G); 42 | } 43 | } 44 | } 45 | 46 | ## invert shift reg contents to generate CRC field 47 | for ($i=0;$i<=$#hold;$i++) { 48 | if (@hold[$i] eq "1") { 49 | print("0"); 50 | } else { 51 | print("1"); 52 | } 53 | } 54 | print "\n"; 55 | } 56 | -------------------------------------------------------------------------------- /perl/crcdes.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pbing/USB/9aadca37b94164f224894abb201678b2367df8bd/perl/crcdes.pdf -------------------------------------------------------------------------------- /rtl/MegaWizard/.qsys_edit/clkctrl_schematic.nlv: -------------------------------------------------------------------------------- 1 | # # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35 2 | # 3 | preplace inst clkctrl -pg 1 -lvl 1 -y 40 -regy -20 4 | preplace inst clkctrl.altclkctrl_0 -pg 1 -lvl 1 -y 30 5 | preplace netloc EXPORTclkctrl(SLAVE)altclkctrl_0.altclkctrl_output,(SLAVE)clkctrl.altclkctrl_output) 1 0 1 NJ 6 | preplace netloc EXPORTclkctrl(SLAVE)altclkctrl_0.altclkctrl_input,(SLAVE)clkctrl.altclkctrl_input) 1 0 1 NJ 7 | levelinfo -pg 1 0 120 310 8 | levelinfo -hier clkctrl 130 160 300 9 | -------------------------------------------------------------------------------- /rtl/MegaWizard/.qsys_edit/filters.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /rtl/MegaWizard/.qsys_edit/preferences.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl.qsys: -------------------------------------------------------------------------------- 1 | 2 | 3 | 10 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 57 | 58 | 59 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/clkctrl.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 288 168) 24 | (text "clkctrl" (rect 127 -1 149 11)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 152 20 164)(font "Arial" )) 26 | (port 27 | (pt 0 72) 28 | (input) 29 | (text "inclk3x" (rect 0 0 25 12)(font "Arial" (font_size 8))) 30 | (text "inclk3x" (rect 4 61 46 72)(font "Arial" (font_size 8))) 31 | (line (pt 0 72)(pt 96 72)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 88) 35 | (input) 36 | (text "inclk2x" (rect 0 0 25 12)(font "Arial" (font_size 8))) 37 | (text "inclk2x" (rect 4 77 46 88)(font "Arial" (font_size 8))) 38 | (line (pt 0 88)(pt 96 88)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 104) 42 | (input) 43 | (text "inclk1x" (rect 0 0 24 12)(font "Arial" (font_size 8))) 44 | (text "inclk1x" (rect 4 93 46 104)(font "Arial" (font_size 8))) 45 | (line (pt 0 104)(pt 96 104)(line_width 1)) 46 | ) 47 | (port 48 | (pt 0 120) 49 | (input) 50 | (text "inclk0x" (rect 0 0 25 12)(font "Arial" (font_size 8))) 51 | (text "inclk0x" (rect 4 109 46 120)(font "Arial" (font_size 8))) 52 | (line (pt 0 120)(pt 96 120)(line_width 1)) 53 | ) 54 | (port 55 | (pt 0 136) 56 | (input) 57 | (text "clkselect[1..0]" (rect 0 0 51 12)(font "Arial" (font_size 8))) 58 | (text "clkselect[1..0]" (rect 4 125 94 136)(font "Arial" (font_size 8))) 59 | (line (pt 0 136)(pt 96 136)(line_width 3)) 60 | ) 61 | (port 62 | (pt 288 72) 63 | (output) 64 | (text "outclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) 65 | (text "outclk" (rect 258 61 294 72)(font "Arial" (font_size 8))) 66 | (line (pt 288 72)(pt 176 72)(line_width 1)) 67 | ) 68 | (drawing 69 | (text "altclkctrl_input" (rect 13 43 122 99)(font "Arial" (color 128 0 0)(font_size 9))) 70 | (text "inclk3x" (rect 101 67 244 144)(font "Arial" (color 0 0 0))) 71 | (text "inclk2x" (rect 101 83 244 176)(font "Arial" (color 0 0 0))) 72 | (text "inclk1x" (rect 101 99 244 208)(font "Arial" (color 0 0 0))) 73 | (text "inclk0x" (rect 101 115 244 240)(font "Arial" (color 0 0 0))) 74 | (text "clkselect" (rect 101 131 256 272)(font "Arial" (color 0 0 0))) 75 | (text "altclkctrl_output" (rect 177 43 456 99)(font "Arial" (color 128 0 0)(font_size 9))) 76 | (text "outclk" (rect 148 67 332 144)(font "Arial" (color 0 0 0))) 77 | (text " clkctrl " (rect 259 152 572 314)(font "Arial" )) 78 | (line (pt 96 32)(pt 176 32)(line_width 1)) 79 | (line (pt 176 32)(pt 176 152)(line_width 1)) 80 | (line (pt 96 152)(pt 176 152)(line_width 1)) 81 | (line (pt 96 32)(pt 96 152)(line_width 1)) 82 | (line (pt 97 52)(pt 97 140)(line_width 1)) 83 | (line (pt 98 52)(pt 98 140)(line_width 1)) 84 | (line (pt 175 52)(pt 175 76)(line_width 1)) 85 | (line (pt 174 52)(pt 174 76)(line_width 1)) 86 | (line (pt 0 0)(pt 288 0)(line_width 1)) 87 | (line (pt 288 0)(pt 288 168)(line_width 1)) 88 | (line (pt 0 168)(pt 288 168)(line_width 1)) 89 | (line (pt 0 0)(pt 0 168)(line_width 1)) 90 | ) 91 | ) 92 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/clkctrl.cmp: -------------------------------------------------------------------------------- 1 | component clkctrl is 2 | port ( 3 | inclk3x : in std_logic := 'X'; -- inclk3x 4 | inclk2x : in std_logic := 'X'; -- inclk2x 5 | inclk1x : in std_logic := 'X'; -- inclk1x 6 | inclk0x : in std_logic := 'X'; -- inclk0x 7 | clkselect : in std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect 8 | outclk : out std_logic -- outclk 9 | ); 10 | end component clkctrl; 11 | 12 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/clkctrl.csv: -------------------------------------------------------------------------------- 1 | # system info clkctrl on 2018.08.31.17:22:04 2 | system_info: 3 | name,value 4 | DEVICE,5CGXFC5C6F27C7 5 | DEVICE_FAMILY,Cyclone V 6 | GENERATION_ID,1535728923 7 | # 8 | # 9 | # Files generated for clkctrl on 2018.08.31.17:22:04 10 | files: 11 | filepath,kind,attributes,module,is_top 12 | simulation/clkctrl.v,VERILOG,,clkctrl,true 13 | simulation/submodules/clkctrl_altclkctrl_0.v,VERILOG,,clkctrl_altclkctrl_0,false 14 | # 15 | # Map from instance-path to kind of module 16 | instances: 17 | instancePath,module 18 | clkctrl.altclkctrl_0,clkctrl_altclkctrl_0 19 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/clkctrl.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | datasheet for clkctrl 6 | 57 | 58 | 59 | 60 | 61 | 62 | 66 | 67 |
clkctrl 63 |
64 |
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68 | 69 | 70 | 71 | 72 | 73 |
2018.08.31.17:22:07Datasheet
74 |
75 |
Overview
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78 | 79 | 80 | 81 | 82 |
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86 |
87 |
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Memory Map
90 | 91 | 92 | 93 | 94 |
95 | 96 |
97 |
98 |

altclkctrl_0

altclkctrl v18.0 99 |
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102 | 103 | 104 | 141 | 142 |
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Parameters

106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 |
DEVICE_FAMILYCYCLONEV
CLOCK_TYPE1
NUMBER_OF_CLOCKS4
ENA_REGISTER_MODE1
GUI_USE_ENAfalse
USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATIONfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
140 |
   143 | 144 | 145 | 147 | 148 |
146 |

Software Assignments

(none)
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150 | 151 | 152 | 153 | 154 | 155 |
generation took 0,00 secondsrendering took 0,00 seconds
156 | 157 | 158 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/clkctrl.ppf: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/clkctrl.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/clkctrl.xml: -------------------------------------------------------------------------------- 1 | 2 | 5 | 6 | 12 | 18 | 24 | 30 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 67 | 68 | 69 | 73 | 74 | 75 | 76 | 77 | 78 | 80 | 81 | 82 | queue size: 0 starting:clkctrl "clkctrl" 83 | 84 | 85 | 86 | Transform: CustomInstructionTransform 87 | No custom instruction connections, skipping transform 88 | 1 modules, 0 connections]]> 89 | Transform: MMTransform 90 | Transform: InterruptMapperTransform 91 | Transform: InterruptSyncTransform 92 | Transform: InterruptFanoutTransform 93 | Transform: AvalonStreamingTransform 94 | Transform: ResetAdaptation 95 | clkctrl" reuses altclkctrl "submodules/clkctrl_altclkctrl_0"]]> 96 | queue size: 0 starting:altclkctrl "submodules/clkctrl_altclkctrl_0" 97 | Generating top-level entity clkctrl_altclkctrl_0. 98 | Current quartus bindir: C:/intelfpga_lite/18.0/quartus/bin64/. 99 | clkctrl" instantiated altclkctrl "altclkctrl_0"]]> 100 | 101 | 102 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 120 | 121 | 122 | 123 | 125 | 126 | 127 | 128 | 129 | queue size: 0 starting:altclkctrl "submodules/clkctrl_altclkctrl_0" 130 | Generating top-level entity clkctrl_altclkctrl_0. 131 | Current quartus bindir: C:/intelfpga_lite/18.0/quartus/bin64/. 132 | clkctrl" instantiated altclkctrl "altclkctrl_0"]]> 133 | 134 | 135 | 136 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/clkctrl_bb.v: -------------------------------------------------------------------------------- 1 | 2 | module clkctrl ( 3 | inclk3x, 4 | inclk2x, 5 | inclk1x, 6 | inclk0x, 7 | clkselect, 8 | outclk); 9 | 10 | input inclk3x; 11 | input inclk2x; 12 | input inclk1x; 13 | input inclk0x; 14 | input [1:0] clkselect; 15 | output outclk; 16 | endmodule 17 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/clkctrl_generation.rpt: -------------------------------------------------------------------------------- 1 | Info: Starting: Create simulation model 2 | Info: qsys-generate Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl\simulation --family="Cyclone V" --part=5CGXFC5C6F27C7 3 | Progress: Loading MegaWizard/clkctrl.qsys 4 | Progress: Reading input file 5 | Progress: Adding altclkctrl_0 [altclkctrl 18.0] 6 | Progress: Parameterizing module altclkctrl_0 7 | Progress: Building connections 8 | Progress: Parameterizing connections 9 | Progress: Validating 10 | Progress: Done reading input file 11 | : clkctrl.altclkctrl_0: Targeting device family: Cyclone V. 12 | : clkctrl.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs. 13 | : clkctrl.altclkctrl_0: The register mode of port 'ena' is unavailable while 'ena' port not added. 14 | Info: clkctrl: Generating clkctrl "clkctrl" for SIM_VERILOG 15 | Info: altclkctrl_0: Generating top-level entity clkctrl_altclkctrl_0. 16 | Info: altclkctrl_0: "clkctrl" instantiated altclkctrl "altclkctrl_0" 17 | Info: clkctrl: Done "clkctrl" with 2 modules, 2 files 18 | Info: qsys-generate succeeded. 19 | Info: Finished: Create simulation model 20 | Info: Starting: Create Modelsim Project. 21 | Info: sim-script-gen --spd=Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl\clkctrl.spd --output-directory=Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ --use-relative-paths=true 22 | Info: Doing: ip-make-simscript --spd=Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl\clkctrl.spd --output-directory=Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ --use-relative-paths=true 23 | Info: Generating the following file(s) for MODELSIM simulator in Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ directory: 24 | Info: mentor/msim_setup.tcl 25 | Info: Generating the following file(s) for VCS simulator in Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ directory: 26 | Info: synopsys/vcs/vcs_setup.sh 27 | Info: Generating the following file(s) for VCSMX simulator in Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ directory: 28 | Info: synopsys/vcsmx/synopsys_sim.setup 29 | Info: synopsys/vcsmx/vcsmx_setup.sh 30 | Info: Generating the following file(s) for NCSIM simulator in Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ directory: 31 | Info: cadence/cds.lib 32 | Info: cadence/hdl.var 33 | Info: cadence/ncsim_setup.sh 34 | Info: 1 .cds.lib files in cadence/cds_libs/ directory 35 | Info: Generating the following file(s) for RIVIERA simulator in Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ directory: 36 | Info: aldec/rivierapro_setup.tcl 37 | Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/. 38 | Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. 39 | Info: Finished: Create Modelsim Project. 40 | Info: Starting: Create block symbol file (.bsf) 41 | Info: qsys-generate Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl.qsys --block-symbol-file --output-directory=Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl --family="Cyclone V" --part=5CGXFC5C6F27C7 42 | Progress: Loading MegaWizard/clkctrl.qsys 43 | Progress: Reading input file 44 | Progress: Adding altclkctrl_0 [altclkctrl 18.0] 45 | Progress: Parameterizing module altclkctrl_0 46 | Progress: Building connections 47 | Progress: Parameterizing connections 48 | Progress: Validating 49 | Progress: Done reading input file 50 | : clkctrl.altclkctrl_0: Targeting device family: Cyclone V. 51 | : clkctrl.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs. 52 | : clkctrl.altclkctrl_0: The register mode of port 'ena' is unavailable while 'ena' port not added. 53 | Info: qsys-generate succeeded. 54 | Info: Finished: Create block symbol file (.bsf) 55 | Info: 56 | Info: Starting: Create HDL design files for synthesis 57 | Info: qsys-generate Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl.qsys --synthesis=VERILOG --output-directory=Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl\synthesis --family="Cyclone V" --part=5CGXFC5C6F27C7 58 | Progress: Loading MegaWizard/clkctrl.qsys 59 | Progress: Reading input file 60 | Progress: Adding altclkctrl_0 [altclkctrl 18.0] 61 | Progress: Parameterizing module altclkctrl_0 62 | Progress: Building connections 63 | Progress: Parameterizing connections 64 | Progress: Validating 65 | Progress: Done reading input file 66 | : clkctrl.altclkctrl_0: Targeting device family: Cyclone V. 67 | : clkctrl.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs. 68 | : clkctrl.altclkctrl_0: The register mode of port 'ena' is unavailable while 'ena' port not added. 69 | Info: clkctrl: Generating clkctrl "clkctrl" for QUARTUS_SYNTH 70 | Info: altclkctrl_0: Generating top-level entity clkctrl_altclkctrl_0. 71 | Info: altclkctrl_0: "clkctrl" instantiated altclkctrl "altclkctrl_0" 72 | Info: clkctrl: Done "clkctrl" with 2 modules, 2 files 73 | Info: qsys-generate succeeded. 74 | Info: Finished: Create HDL design files for synthesis 75 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/clkctrl_generation_previous.rpt: -------------------------------------------------------------------------------- 1 | Info: Starting: Create simulation model 2 | Info: qsys-generate Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl\simulation --family="Cyclone V" --part=5CGXFC5C6F27C7 3 | Progress: Loading MegaWizard/clkctrl.qsys 4 | Progress: Reading input file 5 | Progress: Adding altclkctrl_0 [altclkctrl 18.0] 6 | Progress: Parameterizing module altclkctrl_0 7 | Progress: Building connections 8 | Progress: Parameterizing connections 9 | Progress: Validating 10 | Progress: Done reading input file 11 | : clkctrl.altclkctrl_0: Targeting device family: Cyclone V. 12 | : clkctrl.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs. 13 | : clkctrl.altclkctrl_0: The register mode of port 'ena' is unavailable while 'ena' port not added. 14 | Info: clkctrl: Generating clkctrl "clkctrl" for SIM_VERILOG 15 | Info: altclkctrl_0: Generating top-level entity clkctrl_altclkctrl_0. 16 | Info: altclkctrl_0: "clkctrl" instantiated altclkctrl "altclkctrl_0" 17 | Info: clkctrl: Done "clkctrl" with 2 modules, 2 files 18 | Info: qsys-generate succeeded. 19 | Info: Finished: Create simulation model 20 | Info: Starting: Create Modelsim Project. 21 | Info: sim-script-gen --spd=Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl\clkctrl.spd --output-directory=Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ --use-relative-paths=true 22 | Info: Doing: ip-make-simscript --spd=Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl\clkctrl.spd --output-directory=Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ --use-relative-paths=true 23 | Info: Generating the following file(s) for MODELSIM simulator in Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ directory: 24 | Info: mentor/msim_setup.tcl 25 | Info: Generating the following file(s) for VCS simulator in Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ directory: 26 | Info: synopsys/vcs/vcs_setup.sh 27 | Info: Generating the following file(s) for VCSMX simulator in Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ directory: 28 | Info: synopsys/vcsmx/synopsys_sim.setup 29 | Info: synopsys/vcsmx/vcsmx_setup.sh 30 | Info: Generating the following file(s) for NCSIM simulator in Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ directory: 31 | Info: cadence/cds.lib 32 | Info: cadence/hdl.var 33 | Info: cadence/ncsim_setup.sh 34 | Info: 1 .cds.lib files in cadence/cds_libs/ directory 35 | Info: Generating the following file(s) for RIVIERA simulator in Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/ directory: 36 | Info: aldec/rivierapro_setup.tcl 37 | Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under Z:/Projects/github.com/pbing/USB/rtl/MegaWizard/clkctrl/simulation/. 38 | Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. 39 | Info: Finished: Create Modelsim Project. 40 | Info: Starting: Create block symbol file (.bsf) 41 | Info: qsys-generate Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl.qsys --block-symbol-file --output-directory=Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl --family="Cyclone V" --part=5CGXFC5C6F27C7 42 | Progress: Loading MegaWizard/clkctrl.qsys 43 | Progress: Reading input file 44 | Progress: Adding altclkctrl_0 [altclkctrl 18.0] 45 | Progress: Parameterizing module altclkctrl_0 46 | Progress: Building connections 47 | Progress: Parameterizing connections 48 | Progress: Validating 49 | Progress: Done reading input file 50 | : clkctrl.altclkctrl_0: Targeting device family: Cyclone V. 51 | : clkctrl.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs. 52 | : clkctrl.altclkctrl_0: The register mode of port 'ena' is unavailable while 'ena' port not added. 53 | Info: qsys-generate succeeded. 54 | Info: Finished: Create block symbol file (.bsf) 55 | Info: 56 | Info: Starting: Create HDL design files for synthesis 57 | Info: qsys-generate Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl.qsys --synthesis=VERILOG --output-directory=Z:\Projects\github.com\pbing\USB\rtl\MegaWizard\clkctrl\synthesis --family="Cyclone V" --part=5CGXFC5C6F27C7 58 | Progress: Loading MegaWizard/clkctrl.qsys 59 | Progress: Reading input file 60 | Progress: Adding altclkctrl_0 [altclkctrl 18.0] 61 | Progress: Parameterizing module altclkctrl_0 62 | Progress: Building connections 63 | Progress: Parameterizing connections 64 | Progress: Validating 65 | Progress: Done reading input file 66 | : clkctrl.altclkctrl_0: Targeting device family: Cyclone V. 67 | : clkctrl.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs. 68 | : clkctrl.altclkctrl_0: The register mode of port 'ena' is unavailable while 'ena' port not added. 69 | Info: clkctrl: Generating clkctrl "clkctrl" for QUARTUS_SYNTH 70 | Info: altclkctrl_0: Generating top-level entity clkctrl_altclkctrl_0. 71 | Info: altclkctrl_0: "clkctrl" instantiated altclkctrl "altclkctrl_0" 72 | Info: clkctrl: Done "clkctrl" with 2 modules, 2 files 73 | Info: qsys-generate succeeded. 74 | Info: Finished: Create HDL design files for synthesis 75 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/clkctrl_inst.v: -------------------------------------------------------------------------------- 1 | clkctrl u0 ( 2 | .inclk3x (), // altclkctrl_input.inclk3x 3 | .inclk2x (), // .inclk2x 4 | .inclk1x (), // .inclk1x 5 | .inclk0x (), // .inclk0x 6 | .clkselect (), // .clkselect 7 | .outclk () // altclkctrl_output.outclk 8 | ); 9 | 10 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/clkctrl_inst.vhd: -------------------------------------------------------------------------------- 1 | component clkctrl is 2 | port ( 3 | inclk3x : in std_logic := 'X'; -- inclk3x 4 | inclk2x : in std_logic := 'X'; -- inclk2x 5 | inclk1x : in std_logic := 'X'; -- inclk1x 6 | inclk0x : in std_logic := 'X'; -- inclk0x 7 | clkselect : in std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect 8 | outclk : out std_logic -- outclk 9 | ); 10 | end component clkctrl; 11 | 12 | u0 : component clkctrl 13 | port map ( 14 | inclk3x => CONNECTED_TO_inclk3x, -- altclkctrl_input.inclk3x 15 | inclk2x => CONNECTED_TO_inclk2x, -- .inclk2x 16 | inclk1x => CONNECTED_TO_inclk1x, -- .inclk1x 17 | inclk0x => CONNECTED_TO_inclk0x, -- .inclk0x 18 | clkselect => CONNECTED_TO_clkselect, -- .clkselect 19 | outclk => CONNECTED_TO_outclk -- altclkctrl_output.outclk 20 | ); 21 | 22 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/simulation/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE altclkctrl_0 ./libraries/altclkctrl_0/ 13 | DEFINE altera_ver ./libraries/altera_ver/ 14 | DEFINE lpm_ver ./libraries/lpm_ver/ 15 | DEFINE sgate_ver ./libraries/sgate_ver/ 16 | DEFINE altera_mf_ver ./libraries/altera_mf_ver/ 17 | DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/ 18 | DEFINE cyclonev_ver ./libraries/cyclonev_ver/ 19 | DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/ 20 | DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/ 21 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/simulation/cadence/cds_libs/altclkctrl_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./../libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./../libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./../libraries/cyclonev_pcie_hip_ver/ 20 | DEFINE altclkctrl_0 ./../libraries/altclkctrl_0/ 21 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/simulation/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/simulation/clkctrl.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "clkctrl" -library "lib_clkctrl" -name IP_TOOL_NAME "Qsys" 2 | set_global_assignment -entity "clkctrl" -library "lib_clkctrl" -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -entity "clkctrl" -library "lib_clkctrl" -name IP_TOOL_ENV "Qsys" 4 | set_global_assignment -library "lib_clkctrl" -name SPD_FILE [file join $::quartus(sip_path) "../clkctrl.spd"] 5 | set_global_assignment -library "lib_clkctrl" -name MISC_FILE [file join $::quartus(sip_path) "../../clkctrl.qsys"] 6 | 7 | set_global_assignment -library "lib_clkctrl" -name MISC_FILE [file join $::quartus(sip_path) "clkctrl.v"] 8 | set_global_assignment -library "lib_clkctrl" -name MISC_FILE [file join $::quartus(sip_path) "submodules/clkctrl_altclkctrl_0.v"] 9 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/simulation/clkctrl.v: -------------------------------------------------------------------------------- 1 | // clkctrl.v 2 | 3 | // Generated using ACDS version 18.0 614 4 | 5 | `timescale 1 ps / 1 ps 6 | module clkctrl ( 7 | input wire inclk3x, // altclkctrl_input.inclk3x 8 | input wire inclk2x, // .inclk2x 9 | input wire inclk1x, // .inclk1x 10 | input wire inclk0x, // .inclk0x 11 | input wire [1:0] clkselect, // .clkselect 12 | output wire outclk // altclkctrl_output.outclk 13 | ); 14 | 15 | clkctrl_altclkctrl_0 altclkctrl_0 ( 16 | .inclk3x (inclk3x), // altclkctrl_input.inclk3x 17 | .inclk2x (inclk2x), // .inclk2x 18 | .inclk1x (inclk1x), // .inclk1x 19 | .inclk0x (inclk0x), // .inclk0x 20 | .clkselect (clkselect), // .clkselect 21 | .outclk (outclk) // altclkctrl_output.outclk 22 | ); 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/simulation/submodules/clkctrl_altclkctrl_0.v: -------------------------------------------------------------------------------- 1 | //altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone V" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" clkselect ena inclk outclk 2 | //VERSION_BEGIN 18.0 cbx_altclkbuf 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ VERSION_END 3 | // synthesis VERILOG_INPUT_VERSION VERILOG_2001 4 | // altera message_off 10463 5 | 6 | 7 | 8 | // Copyright (C) 2018 Intel Corporation. All rights reserved. 9 | // Your use of Intel Corporation's design tools, logic functions 10 | // and other software and tools, and its AMPP partner logic 11 | // functions, and any output files from any of the foregoing 12 | // (including device programming or simulation files), and any 13 | // associated documentation or information are expressly subject 14 | // to the terms and conditions of the Intel Program License 15 | // Subscription Agreement, the Intel Quartus Prime License Agreement, 16 | // the Intel FPGA IP License Agreement, or other applicable license 17 | // agreement, including, without limitation, that your use is for 18 | // the sole purpose of programming logic devices manufactured by 19 | // Intel and sold by Intel or its authorized distributors. Please 20 | // refer to the applicable agreement for further details. 21 | 22 | 23 | 24 | //synthesis_resources = cyclonev_clkena 1 25 | //synopsys translate_off 26 | `timescale 1 ps / 1 ps 27 | //synopsys translate_on 28 | module clkctrl_altclkctrl_0_sub 29 | ( 30 | clkselect, 31 | ena, 32 | inclk, 33 | outclk) /* synthesis synthesis_clearbox=1 */; 34 | input [1:0] clkselect; 35 | input ena; 36 | input [3:0] inclk; 37 | output outclk; 38 | `ifndef ALTERA_RESERVED_QIS 39 | // synopsys translate_off 40 | `endif 41 | tri0 [1:0] clkselect; 42 | tri1 ena; 43 | tri0 [3:0] inclk; 44 | `ifndef ALTERA_RESERVED_QIS 45 | // synopsys translate_on 46 | `endif 47 | 48 | wire wire_sd2_outclk; 49 | wire wire_sd1_outclk; 50 | wire [1:0] clkselect_wire; 51 | wire [3:0] inclk_wire; 52 | 53 | cyclonev_clkselect sd2 54 | ( 55 | .clkselect(clkselect_wire), 56 | .inclk(inclk_wire), 57 | .outclk(wire_sd2_outclk)); 58 | cyclonev_clkena sd1 59 | ( 60 | .ena(ena), 61 | .enaout(), 62 | .inclk(wire_sd2_outclk), 63 | .outclk(wire_sd1_outclk)); 64 | defparam 65 | sd1.clock_type = "Global Clock", 66 | sd1.ena_register_mode = "always enabled", 67 | sd1.lpm_type = "cyclonev_clkena"; 68 | assign 69 | clkselect_wire = {clkselect}, 70 | inclk_wire = {inclk}, 71 | outclk = wire_sd1_outclk; 72 | endmodule //clkctrl_altclkctrl_0_sub 73 | //VALID FILE // (C) 2001-2018 Intel Corporation. All rights reserved. 74 | // Your use of Intel Corporation's design tools, logic functions and other 75 | // software and tools, and its AMPP partner logic functions, and any output 76 | // files from any of the foregoing (including device programming or simulation 77 | // files), and any associated documentation or information are expressly subject 78 | // to the terms and conditions of the Intel Program License Subscription 79 | // Agreement, Intel FPGA IP License Agreement, or other applicable 80 | // license agreement, including, without limitation, that your use is for the 81 | // sole purpose of programming logic devices manufactured by Intel and sold by 82 | // Intel or its authorized distributors. Please refer to the applicable 83 | // agreement for further details. 84 | 85 | 86 | 87 | // synopsys translate_off 88 | `timescale 1 ps / 1 ps 89 | // synopsys translate_on 90 | module clkctrl_altclkctrl_0 ( 91 | clkselect, 92 | inclk0x, 93 | inclk1x, 94 | inclk2x, 95 | inclk3x, 96 | outclk); 97 | 98 | input [1:0] clkselect; 99 | input inclk0x; 100 | input inclk1x; 101 | input inclk2x; 102 | input inclk3x; 103 | output outclk; 104 | `ifndef ALTERA_RESERVED_QIS 105 | // synopsys translate_off 106 | `endif 107 | tri0 [1:0] clkselect; 108 | `ifndef ALTERA_RESERVED_QIS 109 | // synopsys translate_on 110 | `endif 111 | 112 | wire sub_wire0; 113 | wire outclk; 114 | wire sub_wire1; 115 | wire sub_wire2; 116 | wire [3:0] sub_wire3; 117 | wire sub_wire4; 118 | wire sub_wire5; 119 | wire sub_wire6; 120 | 121 | assign outclk = sub_wire0; 122 | assign sub_wire1 = 1'h1; 123 | assign sub_wire2 = inclk0x; 124 | assign sub_wire3[3:0] = {sub_wire6, sub_wire5, sub_wire4, sub_wire2}; 125 | assign sub_wire4 = inclk1x; 126 | assign sub_wire5 = inclk2x; 127 | assign sub_wire6 = inclk3x; 128 | 129 | clkctrl_altclkctrl_0_sub clkctrl_altclkctrl_0_sub_component ( 130 | .clkselect (clkselect), 131 | .ena (sub_wire1), 132 | .inclk (sub_wire3), 133 | .outclk (sub_wire0)); 134 | 135 | endmodule -------------------------------------------------------------------------------- /rtl/MegaWizard/clkctrl/simulation/synopsys/vcs/vcs_setup.sh: -------------------------------------------------------------------------------- 1 | 2 | # (C) 2001-2018 Altera Corporation. All rights reserved. 3 | # Your use of Altera Corporation's design tools, logic functions and 4 | # other software and tools, and its AMPP partner logic functions, and 5 | # any output files any of the foregoing (including device programming 6 | # or simulation files), and any associated documentation or information 7 | # are expressly subject to the terms and conditions of the Altera 8 | # Program License Subscription Agreement, Altera MegaCore Function 9 | # License Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by Altera 12 | # or its authorized distributors. Please refer to the applicable 13 | # agreement for further details. 14 | 15 | # ACDS 18.0 614 win32 2018.08.31.17:22:05 16 | 17 | # ---------------------------------------- 18 | # vcs - auto-generated simulation script 19 | 20 | # ---------------------------------------- 21 | # This script provides commands to simulate the following IP detected in 22 | # your Quartus project: 23 | # clkctrl 24 | # 25 | # Altera recommends that you source this Quartus-generated IP simulation 26 | # script from your own customized top-level script, and avoid editing this 27 | # generated script. 28 | # 29 | # To write a top-level shell script that compiles Altera simulation libraries 30 | # and the Quartus-generated IP in your project, along with your design and 31 | # testbench files, follow the guidelines below. 32 | # 33 | # 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section 34 | # below into a new file, e.g. named "vcs_sim.sh". 35 | # 36 | # 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into 37 | # a separate file, e.g. named "filelist.f". 38 | # 39 | # ---------------------------------------- 40 | # # TOP-LEVEL TEMPLATE - BEGIN 41 | # # 42 | # # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to 43 | # # set the top-level simulation or testbench module/entity name. 44 | # # 45 | # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to 46 | # # construct paths to the files required to simulate the IP in your Quartus 47 | # # project. By default, the IP script assumes that you are launching the 48 | # # simulator from the IP script location. If launching from another 49 | # # location, set QSYS_SIMDIR to the output directory you specified when you 50 | # # generated the IP script, relative to the directory from which you launch 51 | # # the simulator. 52 | # # 53 | # # Source the Quartus-generated IP simulation script and do the following: 54 | # # - Compile the Quartus EDA simulation library and IP simulation files. 55 | # # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR. 56 | # # - Compile the design and top-level simulation module/entity using 57 | # # information specified in "filelist.f". 58 | # # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run 59 | # # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="". 60 | # # - Run the simulation. 61 | # # 62 | # source