├── soc ├── fpga │ └── arty-a7-100 │ │ ├── sim │ │ ├── clean.sh │ │ ├── use.sh │ │ ├── sim.sh │ │ ├── .gitignore │ │ ├── fib │ │ │ ├── .gitignore │ │ │ ├── fib.c.vmem │ │ │ ├── fib.vmem │ │ │ └── tb.sv │ │ ├── led │ │ │ ├── .gitignore │ │ │ ├── led.sv │ │ │ ├── led.c.vmem │ │ │ ├── led.vmem │ │ │ └── tb.sv │ │ ├── nettle-aes │ │ │ ├── .gitignore │ │ │ └── tb.sv │ │ ├── crc_32 │ │ │ ├── .gitignore │ │ │ ├── tb.sv │ │ │ ├── crc_32.c.vmem │ │ │ └── crc_32.vmem │ │ ├── debugger │ │ │ ├── .gitignore │ │ │ ├── fib.c.vmem │ │ │ ├── fib.vmem │ │ │ ├── tasks.svh │ │ │ └── tb.sv │ │ ├── build.sh │ │ ├── sim_main.cpp │ │ ├── verilator.f │ │ └── common │ │ │ └── wb_checker.sv │ │ ├── sw │ │ ├── crc_32 │ │ │ ├── .gitignore │ │ │ ├── boardsupport.h │ │ │ ├── board.c │ │ │ ├── boardsupport.c │ │ │ ├── main.c │ │ │ ├── beebsc.h │ │ │ ├── crt0.S │ │ │ ├── support.h │ │ │ ├── Makefile │ │ │ ├── link.ld │ │ │ ├── beebsc.c │ │ │ └── crc_32.c │ │ ├── fib │ │ │ ├── .gitignore │ │ │ ├── fib.c │ │ │ ├── crt0.S │ │ │ ├── Makefile │ │ │ └── link.ld │ │ ├── led │ │ │ ├── .gitignore │ │ │ ├── led.c │ │ │ ├── crt0.S │ │ │ ├── Makefile │ │ │ └── link.ld │ │ └── nettle-aes │ │ │ ├── .gitignore │ │ │ ├── boardsupport.h │ │ │ ├── board.c │ │ │ ├── boardsupport.c │ │ │ ├── main.c │ │ │ ├── beebsc.h │ │ │ ├── crt0.S │ │ │ ├── support.h │ │ │ ├── Makefile │ │ │ ├── link.ld │ │ │ └── beebsc.c │ │ ├── syn │ │ ├── .gitignore │ │ ├── ibex_soc.gen │ │ │ └── sources_1 │ │ │ │ └── ip │ │ │ │ └── clkgen_50mhz │ │ │ │ ├── clkgen_50mhz_board.xdc │ │ │ │ ├── clkgen_50mhz.bmj │ │ │ │ ├── clkgen_50mhz.dcp │ │ │ │ ├── clkgen_50mhz_bmstub.v │ │ │ │ ├── clkgen_50mhz_stub.v │ │ │ │ ├── clkgen_50mhz_stub.vhdl │ │ │ │ ├── clkgen_50mhz_ooc.xdc │ │ │ │ ├── clkgen_50mhz.xdc │ │ │ │ ├── clkgen_50mhz.veo │ │ │ │ ├── clkgen_50mhz.v │ │ │ │ ├── clkgen_50mhz_clk_wiz.v │ │ │ │ ├── clkgen_50mhz_sim_netlist.vhdl │ │ │ │ └── clkgen_50mhz_sim_netlist.v │ │ └── timing.sdc │ │ ├── lint │ │ └── lint.sh │ │ ├── lib │ │ └── verilog │ │ │ ├── clkgen_50mhz.sv │ │ │ └── BSCANE2.sv │ │ ├── rtl │ │ ├── crg.sv │ │ ├── sync_reset.sv │ │ ├── spramx32.vmem │ │ ├── spramx32.sv │ │ ├── wb_led.sv │ │ ├── wb_spramx32.sv │ │ └── ibex_soc.sv │ │ └── util │ │ └── arty-a7-openocd-cfg.tcl └── common │ ├── rtl │ ├── wb_interconnect_xbar.sv │ └── wb_interconnect_sharedbus.sv │ └── sim │ └── wb_checker.sv ├── fv ├── core2wb │ ├── README │ ├── run.tcl │ └── fv_core2wb.sv └── wb2core │ ├── README │ ├── run.tcl │ └── fv_wb2core.sv ├── rtl ├── wb_pkg.sv ├── wb2core.sv ├── core_if.sv ├── core2wb.sv ├── wb_if.sv └── wb_dm_top.sv ├── scripts ├── hex2vmem.pl └── hex2mif.pl ├── .gitmodules ├── doc ├── timing1.json ├── timing3.json └── timing2.json └── README.md /soc/fpga/arty-a7-100/sim/clean.sh: -------------------------------------------------------------------------------- 1 | rm -rf obj_dir 2 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/use.sh: -------------------------------------------------------------------------------- 1 | cp $1 spramx32.vmem 2 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/sim.sh: -------------------------------------------------------------------------------- 1 | ./obj_dir/sim_main ${@} 2 | -------------------------------------------------------------------------------- /fv/core2wb/README: -------------------------------------------------------------------------------- 1 | # module add jasper/24.03.008 2 | bsub -Is -app jasper.inter jg run.tcl 3 | -------------------------------------------------------------------------------- /fv/wb2core/README: -------------------------------------------------------------------------------- 1 | # module add jasper/24.03.008 2 | bsub -Is -app jasper.inter jg run.tcl 3 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/crc_32/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.d 3 | *.dis 4 | *.elf 5 | *.o 6 | *.vmem 7 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/fib/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.d 3 | *.dis 4 | *.elf 5 | *.o 6 | *.vmem 7 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/led/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.d 3 | *.dis 4 | *.elf 5 | *.o 6 | *.vmem 7 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/nettle-aes/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.d 3 | *.dis 4 | *.elf 5 | *.o 6 | *.vmem 7 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/.gitignore: -------------------------------------------------------------------------------- 1 | compile_flags.txt 2 | *.log 3 | *.fst 4 | *.gtkw 5 | *.vmem 6 | obj_dir/ -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/.gitignore: -------------------------------------------------------------------------------- 1 | ibex_soc.*/ 2 | !ibex_soc.gen 3 | .Xil/ 4 | vivado*.jou 5 | vivado*.log 6 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/lint/lint.sh: -------------------------------------------------------------------------------- 1 | verilator --lint-only \ 2 | --top-module ibex_soc \ 3 | -Wno-REDEFMACRO \ 4 | -f ../sim/verilator.f 5 | -------------------------------------------------------------------------------- /rtl/wb_pkg.sv: -------------------------------------------------------------------------------- 1 | /* Wishbone definitions */ 2 | 3 | package wb_pkg; 4 | typedef logic [31:0] adr_t; 5 | typedef logic [31:0] dat_t; 6 | typedef logic [3:0] sel_t; 7 | endpackage 8 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/fib/.gitignore: -------------------------------------------------------------------------------- 1 | *.do 2 | *.key 3 | *.log 4 | *.sh 5 | *.tcl 6 | *.vpd 7 | DVEfiles/ 8 | README 9 | csrc/ 10 | logs/ 11 | simv* 12 | vc_hdrs.h 13 | vcs.args 14 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/led/.gitignore: -------------------------------------------------------------------------------- 1 | *.do 2 | *.key 3 | *.log 4 | *.sh 5 | *.tcl 6 | *.vpd 7 | DVEfiles/ 8 | README 9 | csrc/ 10 | logs/ 11 | simv* 12 | vc_hdrs.h 13 | vcs.args 14 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/nettle-aes/.gitignore: -------------------------------------------------------------------------------- 1 | *.do 2 | *.key 3 | *.log 4 | *.sh 5 | *.tcl 6 | *.vpd 7 | DVEfiles/ 8 | README 9 | csrc/ 10 | logs/ 11 | simv* 12 | vc_hdrs.h 13 | vcs.args 14 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz.bmj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pbing/ibex_wb/HEAD/soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz.bmj -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pbing/ibex_wb/HEAD/soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz.dcp -------------------------------------------------------------------------------- /scripts/hex2vmem.pl: -------------------------------------------------------------------------------- 1 | #! /usr/bin/perl 2 | # Convert to 32-bit Verilog memory file. 3 | 4 | use warnings; 5 | use strict; 6 | 7 | while (<>) { 8 | s/(\w\w) (\w\w) (\w\w) (\w\w)/$4$3$2$1/g; 9 | print; 10 | } 11 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/crc_32/.gitignore: -------------------------------------------------------------------------------- 1 | *.args 2 | *.do 3 | *.history 4 | *.key 5 | *.log 6 | *.sh 7 | *.tcl 8 | *.vpd 9 | .simvision 10 | DVEfiles/ 11 | README 12 | csrc/ 13 | logs/ 14 | simv* 15 | vc_hdrs.h 16 | waves.shm 17 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/debugger/.gitignore: -------------------------------------------------------------------------------- 1 | *.do 2 | *.key 3 | *.log 4 | *.sh 5 | *.tcl 6 | *.vpd 7 | DVEfiles/ 8 | README 9 | csrc/ 10 | logs/ 11 | simv* 12 | vc_hdrs.h 13 | vcs.args 14 | xrun.args 15 | xcelium.d/ 16 | xrun.history 17 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/lib/verilog/clkgen_50mhz.sv: -------------------------------------------------------------------------------- 1 | /* Simple simulation model for Verilator */ 2 | 3 | module clkgen_50mhz 4 | (output logic clk_out1, 5 | input logic clk_in1); 6 | 7 | initial 8 | clk_out1 = 1'b0; 9 | 10 | always @(posedge clk_in1) 11 | clk_out1 <= ~clk_out1; 12 | endmodule 13 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/fib/fib.c: -------------------------------------------------------------------------------- 1 | int main(void) { 2 | int a, b; 3 | volatile int y; 4 | 5 | a = 0; 6 | b = 1; 7 | 8 | /* F10 = 55 (0x37) */ 9 | for (int i = 1; i < 10; ++i) { 10 | y = a + b; 11 | a = b; 12 | b = y; 13 | } 14 | 15 | for (;;) { 16 | asm("wfi"); 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/crc_32/boardsupport.h: -------------------------------------------------------------------------------- 1 | /* Copyright (C) 2017 Embecosm Limited and University of Bristol 2 | 3 | Contributor Graham Markall 4 | 5 | This file is part of Embench and was formerly part of the Bristol/Embecosm 6 | Embedded Benchmark Suite. 7 | 8 | SPDX-License-Identifier: GPL-3.0-or-later */ 9 | 10 | #define CPU_MHZ 1 11 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/nettle-aes/boardsupport.h: -------------------------------------------------------------------------------- 1 | /* Copyright (C) 2017 Embecosm Limited and University of Bristol 2 | 3 | Contributor Graham Markall 4 | 5 | This file is part of Embench and was formerly part of the Bristol/Embecosm 6 | Embedded Benchmark Suite. 7 | 8 | SPDX-License-Identifier: GPL-3.0-or-later */ 9 | 10 | #define CPU_MHZ 1 11 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/rtl/crg.sv: -------------------------------------------------------------------------------- 1 | /* Clock and reset generator */ 2 | 3 | module crg 4 | (input logic clk100m, 5 | input logic ext_rst_n, 6 | output logic rst_n, 7 | output logic clk); 8 | 9 | clkgen_50mhz u_glk_gen 10 | (.clk_out1 (clk), 11 | .clk_in1 (clk100m)); 12 | 13 | sync_reset sync_reset 14 | (.clk, 15 | .ext_rst_n, 16 | .rst_n); 17 | endmodule 18 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/rtl/sync_reset.sv: -------------------------------------------------------------------------------- 1 | /* Reset synchronizer */ 2 | 3 | module sync_reset 4 | #(parameter N = 2) 5 | (input wire clk, 6 | input wire ext_rst_n, 7 | output wire rst_n); 8 | 9 | logic [N-1:0] q; 10 | 11 | always_ff @(posedge clk or negedge ext_rst_n) 12 | if (!ext_rst_n) 13 | q <= '0; 14 | else 15 | q <= {q[N-2:0], 1'b1}; 16 | 17 | assign rst_n = q[N-1]; 18 | endmodule 19 | -------------------------------------------------------------------------------- /fv/core2wb/run.tcl: -------------------------------------------------------------------------------- 1 | clear -all 2 | 3 | # read design 4 | analyze -sv ../../rtl/wb_pkg.sv 5 | analyze -sv ../../rtl/wb_if.sv 6 | analyze -sv ../../rtl/core_if.sv 7 | analyze -sv ../../rtl/core2wb.sv +define+FORMAL +define+NO_MODPORT_EXPRESSIONS 8 | 9 | # read constraints 10 | analyze -sv12 fv_core2wb.sv 11 | 12 | elaborate -top core2wb 13 | 14 | clock core.clk 15 | reset -expression !core.rst_n 16 | 17 | check_assumptions 18 | prove -all 19 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/build.sh: -------------------------------------------------------------------------------- 1 | verilator --cc \ 2 | -CFLAGS -std=c++20 \ 3 | --build --exe -o sim_main \ 4 | --trace-fst --trace-structs \ 5 | --top-module ibex_soc \ 6 | -Wno-fatal -Wno-lint \ 7 | -Wno-REDEFMACRO -Wno-UNOPTFLAT -Wno-WIDTHEXPAND -Wno-WIDTHCONCAT -Wno-MULTIDRIVEN \ 8 | -f verilator.f \ 9 | +define+USE_TRACER +define+RVFI \ 10 | sim_main.cpp 11 | -------------------------------------------------------------------------------- /fv/wb2core/run.tcl: -------------------------------------------------------------------------------- 1 | clear -all 2 | 3 | # read design 4 | analyze -sv ../../rtl/wb_pkg.sv 5 | analyze -sv ../../rtl/wb_if.sv 6 | analyze -sv ../../rtl/core_if.sv 7 | analyze -sv ../../rtl/wb2core.sv +define+FORMAL +define+NO_MODPORT_EXPRESSIONS 8 | 9 | # read constraints 10 | analyze -sv12 fv_wb2core.sv 11 | 12 | elaborate -top wb2core 13 | 14 | clock wb.clk 15 | #reset -expression wb.rst 16 | reset -none 17 | 18 | check_assumptions 19 | prove -all 20 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/timing.sdc: -------------------------------------------------------------------------------- 1 | # Timing constraints 2 | 3 | # System clock is generated by MMCM by module crg. 4 | # It's timing constraints are in clkgen_50mhz.xdc 5 | 6 | # JTAG 7 | create_clock -period 100.000 -name TCK -waveform {0.000 50.000} [get_ports tck] 8 | 9 | set_input_delay -clock [get_clocks TCK] -clock_fall 0.000 [get_ports {trst_n tms tdi}] 10 | set_output_delay -clock [get_clocks TCK] 0.000 [get_ports tdo] 11 | 12 | set_clock_groups -asynchronous -group {TCK} -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/crc_32/board.c: -------------------------------------------------------------------------------- 1 | /* Common board.c for the benchmarks 2 | 3 | Copyright (C) 2018-2019 Embecosm Limited 4 | 5 | Contributor: Jeremy Bennett 6 | 7 | This file is part of Embench and was formerly part of the Bristol/Embecosm 8 | Embedded Benchmark Suite. 9 | 10 | SPDX-License-Identifier: GPL-3.0-or-later */ 11 | 12 | /* This is just a wrapper for the board specific support file. */ 13 | 14 | #include "boardsupport.c" 15 | 16 | 17 | /* 18 | Local Variables: 19 | mode: C 20 | c-file-style: "gnu" 21 | End: 22 | */ 23 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/nettle-aes/board.c: -------------------------------------------------------------------------------- 1 | /* Common board.c for the benchmarks 2 | 3 | Copyright (C) 2018-2019 Embecosm Limited 4 | 5 | Contributor: Jeremy Bennett 6 | 7 | This file is part of Embench and was formerly part of the Bristol/Embecosm 8 | Embedded Benchmark Suite. 9 | 10 | SPDX-License-Identifier: GPL-3.0-or-later */ 11 | 12 | /* This is just a wrapper for the board specific support file. */ 13 | 14 | #include "boardsupport.c" 15 | 16 | 17 | /* 18 | Local Variables: 19 | mode: C 20 | c-file-style: "gnu" 21 | End: 22 | */ 23 | -------------------------------------------------------------------------------- /scripts/hex2mif.pl: -------------------------------------------------------------------------------- 1 | #! /usr/bin/perl 2 | # Convert to MIF 3 | 4 | use warnings; 5 | use strict; 6 | 7 | my $addr; 8 | my @data; 9 | 10 | print <) { 20 | if (/^@(\w+)/) { 21 | $addr = hex($1); 22 | next; 23 | } 24 | 25 | s/(\w\w) (\w\w) (\w\w) (\w\w)/$4$3$2$1/g; 26 | @data = split(/\s/, $_); 27 | 28 | foreach (@data) { 29 | printf("%08X: %s;\n", $addr++, $_); 30 | } 31 | } 32 | 33 | print "END;\n" 34 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "common_cells"] 2 | path = common_cells 3 | url = https://github.com/pulp-platform/common_cells.git 4 | [submodule "pulpino"] 5 | path = pulpino 6 | url = https://github.com/pulp-platform/pulpino.git 7 | [submodule "ibex"] 8 | path = ibex 9 | url = https://github.com/lowRISC/ibex.git 10 | [submodule "riscv-dbg"] 11 | path = riscv-dbg 12 | url = https://github.com/pulp-platform/riscv-dbg.git 13 | [submodule "tech_cells_generic"] 14 | path = tech_cells_generic 15 | url = https://github.com/pulp-platform/tech_cells_generic.git 16 | [submodule "wb2axip"] 17 | path = wb2axip 18 | url = https://github.com/ZipCPU/wb2axip.git 19 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/lib/verilog/BSCANE2.sv: -------------------------------------------------------------------------------- 1 | /* Simple Verilog model for Verilator */ 2 | 3 | module BSCANE2 4 | #(parameter DISABLE_JTAG = "FALSE", 5 | parameter integer JTAG_CHAIN = 1) 6 | (output logic CAPTURE, 7 | output logic DRCK, 8 | output logic RESET, 9 | output logic RUNTEST, 10 | output logic SEL, 11 | output logic SHIFT, 12 | output logic TCK, 13 | output logic TDI, 14 | output logic TMS, 15 | output logic UPDATE, 16 | input logic TDO); 17 | 18 | assign 19 | CAPTURE = 1'b0, 20 | DRCK = 1'b0, 21 | RESET = 1'b0, 22 | RUNTEST = 1'b0, 23 | SEL = 1'b0, 24 | SHIFT = 1'b0, 25 | TCK = 1'b0, 26 | TDI = 1'b0, 27 | TMS = 1'b0, 28 | UPDATE = 1'b0; 29 | endmodule 30 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/crc_32/boardsupport.c: -------------------------------------------------------------------------------- 1 | /* Copyright (C) 2017 Embecosm Limited and University of Bristol 2 | 3 | Contributor Graham Markall 4 | 5 | This file is part of Embench and was formerly part of the Bristol/Embecosm 6 | Embedded Benchmark Suite. 7 | 8 | SPDX-License-Identifier: GPL-3.0-or-later */ 9 | 10 | //#include 11 | 12 | void 13 | initialise_board () 14 | { 15 | __asm__ volatile ("li a0, 0" : : : "memory"); 16 | } 17 | 18 | void __attribute__ ((noinline)) __attribute__ ((externally_visible)) 19 | start_trigger () 20 | { 21 | __asm__ volatile ("li a0, 0" : : : "memory"); 22 | } 23 | 24 | void __attribute__ ((noinline)) __attribute__ ((externally_visible)) 25 | stop_trigger () 26 | { 27 | __asm__ volatile ("li a0, 0" : : : "memory"); 28 | } 29 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/nettle-aes/boardsupport.c: -------------------------------------------------------------------------------- 1 | /* Copyright (C) 2017 Embecosm Limited and University of Bristol 2 | 3 | Contributor Graham Markall 4 | 5 | This file is part of Embench and was formerly part of the Bristol/Embecosm 6 | Embedded Benchmark Suite. 7 | 8 | SPDX-License-Identifier: GPL-3.0-or-later */ 9 | 10 | //#include 11 | 12 | void 13 | initialise_board () 14 | { 15 | __asm__ volatile ("li a0, 0" : : : "memory"); 16 | } 17 | 18 | void __attribute__ ((noinline)) __attribute__ ((externally_visible)) 19 | start_trigger () 20 | { 21 | __asm__ volatile ("li a0, 0" : : : "memory"); 22 | } 23 | 24 | void __attribute__ ((noinline)) __attribute__ ((externally_visible)) 25 | stop_trigger () 26 | { 27 | __asm__ volatile ("li a0, 0" : : : "memory"); 28 | } 29 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/fib/fib.c.vmem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00000013 00000013 00000013 00000013 3 | 00000013 00000013 00000013 00000013 4 | 00000013 00000013 00000013 00000013 5 | 00000013 00000013 00000013 00000013 6 | 00000013 00000013 00000013 00000013 7 | 00000013 00000013 00000013 00000013 8 | 00000013 00000013 00000013 00000013 9 | 00000013 00000013 00000013 0100006F 10 | 0100006F 0080006F 0040006F 11 | @00000023 12 | 0000006F 00000093 81868106 82868206 13 | 83868306 84868406 85868506 86868606 14 | 87868706 88868806 89868906 8A868A06 15 | 8B868B06 8C868C06 8D868D06 8E868E06 16 | 8F868F06 00010117 F3010113 12800D13 17 | 12800D93 01BD5763 000D2023 DDE30D11 18 | 0513FFAD 05930000 00EF0000 11410040 19 | 46854725 97B64781 4632C63E 87B6177D 20 | FB7586B2 10500073 0000BFF5 00000000 21 | 00000000 00000000 00000000 22 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/debugger/fib.c.vmem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00000013 00000013 00000013 00000013 3 | 00000013 00000013 00000013 00000013 4 | 00000013 00000013 00000013 00000013 5 | 00000013 00000013 00000013 00000013 6 | 00000013 00000013 00000013 00000013 7 | 00000013 00000013 00000013 00000013 8 | 00000013 00000013 00000013 00000013 9 | 00000013 00000013 00000013 0100006F 10 | 0100006F 0080006F 0040006F 11 | @00000023 12 | 0000006F 00000093 81868106 82868206 13 | 83868306 84868406 85868506 86868606 14 | 87868706 88868806 89868906 8A868A06 15 | 8B868B06 8C868C06 8D868D06 8E868E06 16 | 8F868F06 00010117 F3010113 12800D13 17 | 12800D93 01BD5763 000D2023 DDE30D11 18 | 0513FFAD 05930000 00EF0000 11410040 19 | 46854725 97B64781 4632C63E 87B6177D 20 | FB7586B2 10500073 0000BFF5 00000000 21 | 00000000 00000000 00000000 22 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/led/led.sv: -------------------------------------------------------------------------------- 1 | /* LED driver (only word access) */ 2 | 3 | `default_nettype none 4 | 5 | module led 6 | #(parameter size) 7 | (output logic led, 8 | wb_if.slave wb); 9 | 10 | localparam addr_width = $clog2(size) - 2; 11 | 12 | logic valid; 13 | logic select; 14 | 15 | always @(posedge wb.clk) 16 | if (valid && wb.we && select) 17 | led <= wb.dat_i[0]; 18 | 19 | /* Wishbone control */ 20 | assign valid = wb.cyc & wb.stb; 21 | assign select = wb.adr[addr_width - 1 : 2] == 0; 22 | assign wb.stall = 1'b0; 23 | assign wb.err = 1'b0; 24 | 25 | always_ff @(posedge wb.clk or posedge wb.rst) 26 | if (wb.rst) 27 | wb.ack <= 1'b0; 28 | else 29 | wb.ack <= valid & ~wb.stall; 30 | 31 | assign wb.dat_o = {31'h00000000,led}; 32 | endmodule 33 | 34 | `resetall 35 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/rtl/spramx32.vmem: -------------------------------------------------------------------------------- 1 | // led.c (blinky) 2 | @00000000 3 | 00000013 00000013 00000013 00000013 4 | 00000013 00000013 00000013 00000013 5 | 00000013 00000013 00000013 00000013 6 | 00000013 00000013 00000013 00000013 7 | 00000013 00000013 00000013 00000013 8 | 00000013 00000013 00000013 00000013 9 | 00000013 00000013 00000013 00000013 10 | 00000013 00000013 00000013 0100006F 11 | 0100006F 0080006F 0040006F 12 | @00000023 13 | 0000006F 00000093 81868106 82868206 14 | 83868306 84868406 85868506 86868606 15 | 87868706 88868806 89868906 8A868A06 16 | 8B868B06 8C868C06 8D868D06 8E868E06 17 | 8F868F06 00010117 F3010113 13000D13 18 | 13000D93 01BD5763 000D2023 DDE30D11 19 | 4501FFAD 00EF4581 07B70040 A0231000 20 | E0730007 66B77C00 8693005F 8736E106 21 | 00010001 00010001 FB7D177D 07054398 22 | B7F5C398 00000000 00000000 00000000 23 | 00000000 24 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/led/led.c.vmem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00000013 00000013 00000013 00000013 3 | 00000013 00000013 00000013 00000013 4 | 00000013 00000013 00000013 00000013 5 | 00000013 00000013 00000013 00000013 6 | 00000013 00000013 00000013 00000013 7 | 00000013 00000013 00000013 00000013 8 | 00000013 00000013 00000013 00000013 9 | 00000013 00000013 00000013 0100006F 10 | 0100006F 0080006F 0040006F 11 | @00000023 12 | 0000006F 00000093 81868106 82868206 13 | 83868306 84868406 85868506 86868606 14 | 87868706 88868806 89868906 8A868A06 15 | 8B868B06 8C868C06 8D868D06 8E868E06 16 | 8F868F06 00010117 F3010113 13400D13 17 | 13400D93 01BD5763 000D2023 DDE30D11 18 | 0513FFAD 05930000 00EF0000 07B70040 19 | 670D1000 0007A023 0D470713 100006B7 20 | 000187BA 00010001 17FD0001 429CFBFD 21 | C29C0785 0000B7F5 00000000 00000000 22 | 00000000 00000000 23 | -------------------------------------------------------------------------------- /rtl/wb2core.sv: -------------------------------------------------------------------------------- 1 | /* Wishbone to core memory interface converter */ 2 | 3 | module wb2core 4 | ( 5 | `ifndef FORMAL 6 | core_if.master core, 7 | wb_if.slave wb 8 | `else 9 | core_if core, 10 | wb_if wb 11 | `endif 12 | ); 13 | 14 | logic resp; 15 | 16 | assign 17 | core.req = wb.cyc & wb.stb, 18 | core.we = wb.we, 19 | core.addr = wb.adr, 20 | core.be = wb.sel, 21 | wb.stall = ~core.gnt, 22 | wb.ack = resp & wb.cyc & core.rvalid & ~core.err, 23 | wb.err = resp & wb.cyc & core.rvalid & core.err; 24 | 25 | `ifdef NO_MODPORT_EXPRESSIONS 26 | assign 27 | core.wdata = wb.dat_m, 28 | wb.dat_s = core.rdata; 29 | `else 30 | assign 31 | core.wdata = wb.dat_i, 32 | wb.dat_o = core.rdata; 33 | `endif 34 | 35 | always_ff @(posedge wb.clk or posedge wb.rst) 36 | if (wb.rst) 37 | resp <= 1'b0; 38 | else 39 | resp <= wb.cyc & wb.stb & ~wb.stall; 40 | endmodule 41 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/rtl/spramx32.sv: -------------------------------------------------------------------------------- 1 | /* Single port 32 bit RAM */ 2 | 3 | module spramx32 4 | #(parameter size = 'h80, 5 | localparam addr_width = $clog2(size) - 2) 6 | (input logic clk, // clock 7 | input logic [addr_width-1:0] addr, // address 8 | input logic ce, // chip enable 9 | input logic [3:0] we, // write enables 10 | input logic [31:0] d, // data input 11 | output logic [31:0] q); // data output 12 | 13 | (* ram_style = "block" *) logic [31:0] mem[size >> 2]; 14 | 15 | initial 16 | $readmemh("spramx32.vmem", mem); 17 | 18 | always @(posedge clk) 19 | if (ce) 20 | begin 21 | if (we[0]) mem[addr][7:0] <= d[7:0]; 22 | if (we[1]) mem[addr][15:8] <= d[15:8]; 23 | if (we[2]) mem[addr][23:16] <= d[23:16]; 24 | if (we[3]) mem[addr][31:24] <= d[31:24]; 25 | end 26 | 27 | always_ff @(posedge clk) 28 | if (ce) 29 | q <= mem[addr]; 30 | endmodule 31 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/fib/fib.vmem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00000013 00000013 00000013 00000013 3 | 00000013 00000013 00000013 00000013 4 | 00000013 00000013 00000013 00000013 5 | 00000013 00000013 00000013 00000013 6 | 00000013 00000013 00000013 00000013 7 | 00000013 00000013 00000013 00000013 8 | 00000013 00000013 00000013 00000013 9 | 00000013 00000013 00000013 0100006F 10 | 0100006F 0080006F 0040006F 11 | @00000023 12 | 0000006F 00000093 00008113 00008193 13 | 00008213 00008293 00008313 00008393 14 | 00008413 00008493 00008513 00008593 15 | 00008613 00008693 00008713 00008793 16 | 00008813 00008893 00008913 00008993 17 | 00008A13 00008A93 00008B13 00008B93 18 | 00008C13 00008C93 00008D13 00008D93 19 | 00008E13 00008E93 00008F13 00008F93 20 | 00010117 EF410113 17C00D13 17C00D93 21 | 01BD5863 000D2023 004D0D13 FFADDCE3 22 | 00000513 00000593 004000EF FF010113 23 | 00900713 00100693 00000793 00D787B3 24 | 00F12623 00C12603 FFF70713 00068793 25 | 00060693 FE0714E3 10500073 FFDFF06F 26 | 00000000 00000000 00000000 00000000 27 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/rtl/wb_led.sv: -------------------------------------------------------------------------------- 1 | /* LED driver (only word access) */ 2 | 3 | module wb_led 4 | #(parameter N = 4) 5 | (output logic [N-1:0] led, 6 | wb_if.slave wb); 7 | 8 | logic valid; 9 | logic select; 10 | 11 | always_ff @(posedge wb.clk or posedge wb.rst) 12 | if (wb.rst) 13 | led <= '0; 14 | else 15 | if (valid && wb.we && select) 16 | `ifdef NO_MODPORT_EXPRESSIONS 17 | led <= wb.dat_m[N-1:0]; 18 | `else 19 | led <= wb.dat_i[N-1:0]; 20 | `endif 21 | 22 | /* Wishbone control */ 23 | assign 24 | valid = wb.cyc & wb.stb, 25 | select = wb.adr[11:2] == 0, 26 | wb.stall = 1'b0, 27 | wb.err = 1'b0; 28 | 29 | always_ff @(posedge wb.clk or posedge wb.rst) 30 | if (wb.rst) 31 | wb.ack <= 1'b0; 32 | else 33 | wb.ack <= valid & ~wb.stall; 34 | 35 | `ifdef NO_MODPORT_EXPRESSIONS 36 | assign wb.dat_s = {{(32 - N){1'b0}}, led}; 37 | `else 38 | assign wb.dat_o = {{(32 - N){1'b0}}, led}; 39 | `endif 40 | endmodule 41 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/debugger/fib.vmem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00000013 00000013 00000013 00000013 3 | 00000013 00000013 00000013 00000013 4 | 00000013 00000013 00000013 00000013 5 | 00000013 00000013 00000013 00000013 6 | 00000013 00000013 00000013 00000013 7 | 00000013 00000013 00000013 00000013 8 | 00000013 00000013 00000013 00000013 9 | 00000013 00000013 00000013 0100006F 10 | 0100006F 0080006F 0040006F 11 | @00000023 12 | 0000006F 00000093 00008113 00008193 13 | 00008213 00008293 00008313 00008393 14 | 00008413 00008493 00008513 00008593 15 | 00008613 00008693 00008713 00008793 16 | 00008813 00008893 00008913 00008993 17 | 00008A13 00008A93 00008B13 00008B93 18 | 00008C13 00008C93 00008D13 00008D93 19 | 00008E13 00008E93 00008F13 00008F93 20 | 00010117 EF410113 17C00D13 17C00D93 21 | 01BD5863 000D2023 004D0D13 FFADDCE3 22 | 00000513 00000593 004000EF FF010113 23 | 00900713 00100693 00000793 00D787B3 24 | 00F12623 00C12603 FFF70713 00068793 25 | 00060693 FE0714E3 10500073 FFDFF06F 26 | 00000000 00000000 00000000 00000000 27 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/led/led.vmem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00000013 00000013 00000013 00000013 3 | 00000013 00000013 00000013 00000013 4 | 00000013 00000013 00000013 00000013 5 | 00000013 00000013 00000013 00000013 6 | 00000013 00000013 00000013 00000013 7 | 00000013 00000013 00000013 00000013 8 | 00000013 00000013 00000013 00000013 9 | 00000013 00000013 00000013 0100006F 10 | 0100006F 0080006F 0040006F 11 | @00000023 12 | 0000006F 00000093 00008113 00008193 13 | 00008213 00008293 00008313 00008393 14 | 00008413 00008493 00008513 00008593 15 | 00008613 00008693 00008713 00008793 16 | 00008813 00008893 00008913 00008993 17 | 00008A13 00008A93 00008B13 00008B93 18 | 00008C13 00008C93 00008D13 00008D93 19 | 00008E13 00008E93 00008F13 00008F93 20 | 00010117 EF410113 18800D13 18800D93 21 | 01BD5863 000D2023 004D0D13 FFADDCE3 22 | 00000513 00000593 004000EF 100007B7 23 | 00001737 0007A023 C3570713 100006B7 24 | 00070793 00000013 00000013 00000013 25 | 00000013 FFF78793 FE0796E3 0006A783 26 | 00178793 00F6A023 FD9FF06F 00000000 27 | 00000000 00000000 00000000 28 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/util/arty-a7-openocd-cfg.tcl: -------------------------------------------------------------------------------- 1 | # Copyright lowRISC contributors. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | adapter driver ftdi 6 | transport select jtag 7 | 8 | ftdi device_desc "Digilent USB Device" 9 | ftdi vid_pid 0x0403 0x6010 10 | ftdi channel 0 11 | ftdi layout_init 0x0088 0x008b 12 | 13 | reset_config none 14 | 15 | # Configure JTAG chain and the target processor 16 | set _CHIPNAME riscv 17 | 18 | # Configure JTAG expected ID 19 | # arty-a7-35t 20 | # set _EXPECTED_ID 0x0362D093 21 | # arty-a7-100t 22 | set _EXPECTED_ID 0x13631093 23 | 24 | jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_EXPECTED_ID -ignore-version 25 | set _TARGETNAME $_CHIPNAME.cpu 26 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME 27 | 28 | riscv set_ir idcode 0x09 29 | riscv set_ir dtmcs 0x22 30 | riscv set_ir dmi 0x23 31 | 32 | adapter speed 10000 33 | 34 | riscv set_mem_access sysbus 35 | gdb_report_data_abort enable 36 | gdb_report_register_access_error enable 37 | gdb_breakpoint_override hard 38 | 39 | reset_config none 40 | 41 | init 42 | halt 43 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/sim_main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "Vibex_soc.h" 4 | 5 | int main(int argc, char **argv) { 6 | const std::unique_ptr contextp{new VerilatedContext}; 7 | contextp->traceEverOn(true); 8 | contextp->commandArgs(argc, argv); 9 | 10 | const std::unique_ptr top{new Vibex_soc{contextp.get(), "TOP"}}; 11 | top->ck_rst_n = 1; 12 | top->clk100mhz = 0; 13 | top->eval(); 14 | 15 | const std::unique_ptr tfp{new VerilatedFstC}; 16 | top->trace(tfp.get(), 99); 17 | tfp->open("dump.fst"); 18 | 19 | while (contextp->time() < 600000) { 20 | contextp->timeInc(1); 21 | 22 | top->clk100mhz = ~top->clk100mhz; 23 | 24 | if (!top->clk100mhz) { 25 | if (contextp->time() > 15 && contextp->time() < 30) { 26 | top->ck_rst_n = 0; // Assert reset 27 | } else { 28 | top->ck_rst_n = 1; // Deassert reset 29 | } 30 | } 31 | 32 | top->eval(); 33 | tfp->dump(contextp->time()); 34 | } 35 | 36 | top->final(); 37 | tfp->close(); 38 | contextp->statsPrintSummary(); 39 | 40 | return 0; 41 | } 42 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/fib/tb.sv: -------------------------------------------------------------------------------- 1 | /* Testbench */ 2 | 3 | `default_nettype none 4 | 5 | module tb; 6 | timeunit 1ns / 1ps; 7 | 8 | const realtime tclk = 1s / 100.0e6; // CPU clock period 9 | const realtime ttck = 1s / 10.0e6; // JTAG clock period 10 | 11 | bit clk; 12 | bit rst_n; 13 | wire led; 14 | bit trst_n; 15 | bit tck; 16 | bit tms; 17 | bit tdi; 18 | wire tdo; 19 | wire tdo_oe; 20 | 21 | ibex_soc_example dut(.*); 22 | 23 | always #(tclk / 2) clk = ~clk; 24 | 25 | always #(ttck / 2) tck = ~tck; 26 | 27 | assign trst_n = rst_n; 28 | 29 | initial 30 | begin:main 31 | string filename; 32 | int status; 33 | 34 | $timeformat(-9, 3, " ns"); 35 | 36 | status = $value$plusargs("filename=%s", filename); 37 | assert(status) else $fatal(1, "No memory file provided. Please use './simv '+filename="); 38 | $readmemh(filename, tb.dut.wb_spram.spram.mem); 39 | 40 | repeat (3) @(negedge clk); 41 | rst_n = 1'b1; 42 | 43 | repeat (350) @(negedge clk); 44 | $finish; 45 | end:main 46 | endmodule 47 | 48 | `resetall 49 | -------------------------------------------------------------------------------- /rtl/core_if.sv: -------------------------------------------------------------------------------- 1 | /* Core interface */ 2 | 3 | interface core_if 4 | (input logic clk, 5 | input logic rst_n); 6 | 7 | logic req; 8 | logic gnt; 9 | logic rvalid; 10 | logic we; 11 | logic [3:0] be; 12 | logic [31:0] addr; 13 | logic [31:0] wdata; 14 | logic [31:0] rdata; 15 | logic err; 16 | 17 | modport master 18 | (input clk, 19 | input rst_n, 20 | output req, 21 | input gnt, 22 | input rvalid, 23 | output we, 24 | output be, 25 | output addr, 26 | output wdata, 27 | input rdata, 28 | input err); 29 | 30 | modport slave 31 | (input clk, 32 | input rst_n, 33 | input req, 34 | output gnt, 35 | output rvalid, 36 | input we, 37 | input be, 38 | input addr, 39 | input wdata, 40 | output rdata, 41 | output err); 42 | 43 | modport monitor 44 | (input clk, 45 | input rst_n, 46 | input req, 47 | input gnt, 48 | input rvalid, 49 | input we, 50 | input be, 51 | input addr, 52 | input wdata, 53 | input rdata, 54 | input err); 55 | endinterface 56 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz_bmstub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. 3 | // ------------------------------------------------------------------------------- 4 | 5 | `timescale 1 ps / 1 ps 6 | 7 | (* BLOCK_STUB = "true" *) 8 | module clkgen_50mhz ( 9 | clk_in1, 10 | clk_out1 11 | ); 12 | 13 | (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock_CLK_IN1 CLK_IN1" *) 14 | (* X_INTERFACE_MODE = "slave clock_CLK_IN1" *) 15 | (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clock_CLK_IN1, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN , ASSOCIATED_BUSIF , ASSOCIATED_PORT , ASSOCIATED_RESET , INSERT_VIP 0, BOARD.ASSOCIATED_PARAM CLK_IN1_BOARD_INTERFACE" *) 16 | input clk_in1; 17 | (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock_CLK_OUT1 CLK_OUT1" *) 18 | (* X_INTERFACE_MODE = "master clock_CLK_OUT1" *) 19 | (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clock_CLK_OUT1, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN , ASSOCIATED_BUSIF , ASSOCIATED_PORT , ASSOCIATED_RESET , INSERT_VIP 0" *) 20 | output clk_out1; 21 | 22 | // stub module has no contents 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /rtl/core2wb.sv: -------------------------------------------------------------------------------- 1 | /* Core to Wishbone memory interface converter */ 2 | 3 | module core2wb 4 | #(parameter pending = 16) // number of outstandig transactions 5 | ( 6 | `ifndef FORMAL 7 | core_if.slave core, 8 | wb_if.master wb 9 | `else 10 | core_if core, 11 | wb_if wb 12 | `endif 13 | ); 14 | 15 | logic signed [$clog2(pending):0] counts; 16 | 17 | assign 18 | core.gnt = core.req & ~wb.stall, 19 | core.rvalid = wb.cyc & (wb.ack | wb.err), 20 | core.err = wb.err, 21 | wb.stb = core.req, 22 | wb.adr = core.addr, 23 | wb.we = core.we, 24 | wb.sel = core.we ? core.be : '1; 25 | 26 | `ifdef NO_MODPORT_EXPRESSIONS 27 | assign 28 | core.rdata = wb.dat_s, 29 | wb.dat_m = core.wdata; 30 | `else 31 | assign 32 | core.rdata = wb.dat_i, 33 | wb.dat_o = core.wdata; 34 | `endif 35 | 36 | always_ff @(posedge core.clk or negedge core.rst_n) 37 | if (!core.rst_n) 38 | counts <= 0; 39 | else 40 | if (core.req && core.gnt) 41 | counts <= (wb.cyc && wb.ack) ? counts : counts + 1; 42 | else if (wb.cyc && wb.ack) 43 | counts <= counts - 1; 44 | 45 | assign wb.cyc = core.req || (counts > 0); 46 | endmodule 47 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/led/tb.sv: -------------------------------------------------------------------------------- 1 | /* Testbench */ 2 | 3 | `default_nettype none 4 | 5 | module tb; 6 | timeunit 1ns / 1ps; 7 | 8 | const realtime tclk = 1s / 100.0e6; 9 | 10 | bit clk100mhz; 11 | bit [3:0] sw; 12 | wire [3:0] led; 13 | bit [3:0] btn; 14 | bit ck_rst_n; 15 | bit tck; 16 | bit trst_n; 17 | bit tms; 18 | bit tdi; 19 | wire tdo; 20 | 21 | glbl glbl(); 22 | ibex_soc dut(.*); 23 | 24 | always #(tclk / 2) clk100mhz = ~clk100mhz; 25 | 26 | `ifdef ASSERT_ON 27 | bind dut wb_checker wbm0_checker(wbm[0]); 28 | bind dut wb_checker wbm1_checker(wbm[1]); 29 | bind dut wb_checker wbs0_checker(wbs[0]); 30 | bind dut wb_checker wbs1_checker(wbs[1]); 31 | `endif 32 | 33 | initial 34 | begin:main 35 | string filename; 36 | int status; 37 | 38 | $timeformat(-9, 3, " ns"); 39 | 40 | status = $value$plusargs("filename=%s", filename); 41 | chk_filename: assert(status) else $fatal(1, "No memory file provided. Please use './simv '+filename="); 42 | $readmemh(filename, tb.dut.wb_spram.spram.mem); 43 | 44 | repeat (3) @(negedge clk100mhz); 45 | ck_rst_n = 1'b1; 46 | 47 | #33ms $finish; 48 | end:main 49 | endmodule 50 | 51 | `resetall 52 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/rtl/wb_spramx32.sv: -------------------------------------------------------------------------------- 1 | /* Single port 32 bit RAM with Wishbone interface */ 2 | 3 | module wb_spramx32 4 | #(parameter size = 'h80) 5 | (wb_if.slave wb); 6 | 7 | localparam addr_width = $clog2(size) - 2; 8 | 9 | logic valid; 10 | logic [addr_width - 1:0] ram_addr; // RAM address 11 | logic ram_ce; 12 | logic [3:0] ram_we; 13 | logic [31:0] ram_data; 14 | logic [31:0] ram_q; 15 | 16 | spramx32 17 | #(.size(size)) 18 | spram 19 | (.clk (wb.clk), 20 | .addr (ram_addr), 21 | .ce (ram_ce), 22 | .we (ram_we), 23 | .d (ram_data), 24 | .q (ram_q)); 25 | 26 | assign 27 | ram_addr = wb.adr[addr_width+1:2], 28 | ram_ce = valid, 29 | ram_we = {4{wb.we}} & wb.sel, 30 | `ifdef NO_MODPORT_EXPRESSIONS 31 | ram_data = wb.dat_m, 32 | wb.dat_s = ram_q; 33 | `else 34 | ram_data = wb.dat_i, 35 | wb.dat_o = ram_q; 36 | `endif 37 | 38 | /* Wishbone control */ 39 | assign 40 | valid = wb.cyc & wb.stb, 41 | wb.stall = 1'b0, 42 | wb.err = 1'b0; 43 | 44 | always_ff @(posedge wb.clk or posedge wb.rst) 45 | if (wb.rst) 46 | wb.ack <= 1'b0; 47 | else 48 | wb.ack <= valid & ~wb.stall; 49 | endmodule 50 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/crc_32/main.c: -------------------------------------------------------------------------------- 1 | /* Common main.c for the benchmarks 2 | 3 | Copyright (C) 2014 Embecosm Limited and University of Bristol 4 | Copyright (C) 2018-2019 Embecosm Limited 5 | 6 | Contributor: James Pallister 7 | Contributor: Jeremy Bennett 8 | 9 | This file is part of Embench and was formerly part of the Bristol/Embecosm 10 | Embedded Benchmark Suite. 11 | 12 | SPDX-License-Identifier: GPL-3.0-or-later */ 13 | 14 | #include "support.h" 15 | 16 | 17 | int __attribute__ ((used)) 18 | main (int argc __attribute__ ((unused)), 19 | char *argv[] __attribute__ ((unused))) 20 | { 21 | volatile int result; 22 | volatile int correct; 23 | 24 | //asm("csrci 0x7c0, 1"); // disable icache 25 | asm("csrsi 0x7c0, 1"); // enable icache 26 | 27 | initialise_board (); 28 | initialise_benchmark (); 29 | warm_caches (WARMUP_HEAT); 30 | 31 | start_trigger (); 32 | result = benchmark (); 33 | stop_trigger (); 34 | 35 | /* bmarks that use arrays will check a global array rather than int result */ 36 | 37 | correct = verify_benchmark (result); 38 | 39 | //return (!correct); 40 | for (;;) { 41 | asm("wfi"); 42 | } 43 | } /* main () */ 44 | 45 | 46 | /* 47 | Local Variables: 48 | mode: C 49 | c-file-style: "gnu" 50 | End: 51 | */ 52 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/nettle-aes/main.c: -------------------------------------------------------------------------------- 1 | /* Common main.c for the benchmarks 2 | 3 | Copyright (C) 2014 Embecosm Limited and University of Bristol 4 | Copyright (C) 2018-2019 Embecosm Limited 5 | 6 | Contributor: James Pallister 7 | Contributor: Jeremy Bennett 8 | 9 | This file is part of Embench and was formerly part of the Bristol/Embecosm 10 | Embedded Benchmark Suite. 11 | 12 | SPDX-License-Identifier: GPL-3.0-or-later */ 13 | 14 | #include "support.h" 15 | 16 | 17 | int __attribute__ ((used)) 18 | main (int argc __attribute__ ((unused)), 19 | char *argv[] __attribute__ ((unused))) 20 | { 21 | volatile int result; 22 | volatile int correct; 23 | 24 | //asm("csrci 0x7c0, 1"); // disable icache 25 | asm("csrsi 0x7c0, 1"); // enable icache 26 | 27 | initialise_board (); 28 | initialise_benchmark (); 29 | warm_caches (WARMUP_HEAT); 30 | 31 | start_trigger (); 32 | result = benchmark (); 33 | stop_trigger (); 34 | 35 | /* bmarks that use arrays will check a global array rather than int result */ 36 | 37 | correct = verify_benchmark (result); 38 | 39 | //return (!correct); 40 | for (;;) { 41 | asm("wfi"); 42 | } 43 | } /* main () */ 44 | 45 | 46 | /* 47 | Local Variables: 48 | mode: C 49 | c-file-style: "gnu" 50 | End: 51 | */ 52 | -------------------------------------------------------------------------------- /doc/timing1.json: -------------------------------------------------------------------------------- 1 | {"signal": 2 | [ 3 | {"name": "clk", "wave": "p......"}, 4 | ["Ibex", 5 | {"name": "data_req_o", "wave": "01.0..."}, 6 | {"name": "data_addr_o", "wave": "x=.xxxx", "data": ["Address"]}, 7 | {"name": "data_we_o", "wave": "x=.xxxx", "data": ["WE"]}, 8 | {"name": "data_be_o", "wave": "x=.xxxx", "data": ["BE"]}, 9 | {"name": "data_wdata_o", "wave": "x=.xxxx", "data": ["WData"]}, 10 | {"name": "data_gnt_i", "wave": "0.10..."}, 11 | {"name": "data_rvalid_i", "wave": "0..10.."}, 12 | {"name": "data_err_i", "wave": "xxx=xxx", "data": ["Err"]}, 13 | {"name": "data_rdata_i", "wave": "xxx=xxx", "data": ["RData"]} 14 | ], 15 | {}, 16 | ["Wishbone", 17 | {"name": "CYC", "wave": "01..0.."}, 18 | {"name": "STB", "wave": "01.0..."}, 19 | {"name": "ADR", "wave": "x=.xxxx", "data": ["Address"]}, 20 | {"name": "SEL", "wave": "x=.xxxx", "data": ["BE"]}, 21 | {"name": "WE", "wave": "x=.xxxx", "data": ["WE"]}, 22 | {"name": "DAT_O", "wave": "x=.xxxx", "data": ["WData"]}, 23 | {"name": "STALL", "wave": "x10xxxx"}, 24 | {"name": "ACK", "wave": "xxx=xxx", "data": ["Ack"]}, 25 | {"name": "ERR", "wave": "xxx=xxx", "data": ["Err"]}, 26 | {"name": "DAT_I", "wave": "xxx=xxx", "data": ["RData"]} 27 | ], 28 | ], 29 | "config": { "hscale": 2 } 30 | } 31 | -------------------------------------------------------------------------------- /doc/timing3.json: -------------------------------------------------------------------------------- 1 | {"signal": 2 | [ 3 | {"name": "clk", "wave": "p......"}, 4 | ["Ibex", 5 | {"name": "data_req_o", "wave": "01..0.."}, 6 | {"name": "data_addr_o", "wave": "x=..xxx", "data": ["Address"]}, 7 | {"name": "data_we_o", "wave": "x=..xxx", "data": ["WE"]}, 8 | {"name": "data_be_o", "wave": "x=..xxx", "data": ["BE"]}, 9 | {"name": "data_wdata_o", "wave": "x=..xxx", "data": ["WData"]}, 10 | {"name": "data_gnt_i", "wave": "0..10.."}, 11 | {"name": "data_rvalid_i", "wave": "0....10"}, 12 | {"name": "data_err_i", "wave": "xxxxx=x", "data": ["Err"]}, 13 | {"name": "data_rdata_i", "wave": "xxxxx=x", "data": ["RData"]} 14 | ], 15 | {}, 16 | ["Wishbone", 17 | {"name": "CYC", "wave": "01....0"}, 18 | {"name": "STB", "wave": "01..0.."}, 19 | {"name": "ADR", "wave": "x=..xxx", "data": ["Address"]}, 20 | {"name": "SEL", "wave": "x=..xxx", "data": ["BE"]}, 21 | {"name": "WE", "wave": "x=..xxx", "data": ["WE"]}, 22 | {"name": "DAT_O", "wave": "x=..xxx", "data": ["WData"]}, 23 | {"name": "STALL", "wave": "x1.0xxx"}, 24 | {"name": "ACK", "wave": "xxxxx=x", "data": ["Ack"]}, 25 | {"name": "ERR", "wave": "xxxxx=x", "data": ["Err"]}, 26 | {"name": "DAT_I", "wave": "xxxxx=x", "data": ["RData"]} 27 | ], 28 | ], 29 | "config": { "hscale": 2 } 30 | } 31 | -------------------------------------------------------------------------------- /doc/timing2.json: -------------------------------------------------------------------------------- 1 | {"signal": 2 | [ 3 | {"name": "clk", "wave": "p......"}, 4 | ["Ibex", 5 | {"name": "data_req_o", "wave": "01.0..."}, 6 | {"name": "data_addr_o", "wave": "x==xxxx", "data": ["Addr1", "Addr2"]}, 7 | {"name": "data_we_o", "wave": "x==xxxx", "data": ["WE1", "WE2"]}, 8 | {"name": "data_be_o", "wave": "x==xxxx", "data": ["BE1", "BE2"]}, 9 | {"name": "data_wdata_o", "wave": "x==xxxx", "data": ["WData1", "Wdata2"]}, 10 | {"name": "data_gnt_i", "wave": "01.0..."}, 11 | {"name": "data_rvalid_i", "wave": "0.1.0.."}, 12 | {"name": "data_err_i", "wave": "xx==xxx", "data": ["Err1", "Err2"]}, 13 | {"name": "data_rdata_i", "wave": "xx==xxx", "data": ["RData1", "RData2"]} 14 | ], 15 | {}, 16 | ["Wishbone", 17 | {"name": "CYC", "wave": "01..0.."}, 18 | {"name": "STB", "wave": "01.0..."}, 19 | {"name": "ADR", "wave": "x==xxxx", "data": ["Addr1", "Addr2"]}, 20 | {"name": "SEL", "wave": "x==xxxx", "data": ["BE1", "BE2"]}, 21 | {"name": "WE", "wave": "x==xxxx", "data": ["WE1", "WE2"]}, 22 | {"name": "DAT_O", "wave": "x==xxxx", "data": ["WData1", "WData2"]}, 23 | {"name": "STALL", "wave": "x0.xxxx"}, 24 | {"name": "ACK", "wave": "xx==xxx", "data": ["Ack1", "Ack2"]}, 25 | {"name": "ERR", "wave": "xx==xxx", "data": ["Err1", "Err2"]}, 26 | {"name": "DAT_I", "wave": "xx==xxx", "data": ["RData1", "RData2"]} 27 | ], 28 | ], 29 | "config": { "hscale": 2 } 30 | } 31 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/crc_32/beebsc.h: -------------------------------------------------------------------------------- 1 | /* BEEBS local library variants header 2 | 3 | Copyright (C) 2019 Embecosm Limited. 4 | 5 | Contributor Jeremy Bennett 6 | 7 | This file is part of Embench and was formerly part of the Bristol/Embecosm 8 | Embedded Benchmark Suite. 9 | 10 | SPDX-License-Identifier: GPL-3.0-or-later */ 11 | 12 | #ifndef BEEBSC_H 13 | #define BEEBSC_H 14 | 15 | #include 16 | 17 | /* BEEBS fixes RAND_MAX to its lowest permitted value, 2^15-1 */ 18 | 19 | #ifdef RAND_MAX 20 | #undef RAND_MAX 21 | #endif 22 | #define RAND_MAX ((1U << 15) - 1) 23 | 24 | /* Simplified assert. 25 | 26 | The full complexity of assert is not needed for a benchmark. See the 27 | discussion at: 28 | 29 | https://lists.librecores.org/pipermail/embench/2019-August/000007.html 30 | 31 | This function just*/ 32 | 33 | #define assert_beebs(expr) { if (!(expr)) exit (1); } 34 | 35 | /* Local simplified versions of library functions */ 36 | 37 | int rand_beebs (void); 38 | void srand_beebs (unsigned int new_seed); 39 | 40 | void init_heap_beebs (void *heap, const size_t heap_size); 41 | int check_heap_beebs (void *heap); 42 | void *malloc_beebs (size_t size); 43 | void *calloc_beebs (size_t nmemb, size_t size); 44 | void *realloc_beebs (void *ptr, size_t size); 45 | void free_beebs (void *ptr); 46 | #endif /* BEEBSC_H */ 47 | 48 | 49 | /* 50 | Local Variables: 51 | mode: C 52 | c-file-style: "gnu" 53 | End: 54 | */ 55 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/nettle-aes/beebsc.h: -------------------------------------------------------------------------------- 1 | /* BEEBS local library variants header 2 | 3 | Copyright (C) 2019 Embecosm Limited. 4 | 5 | Contributor Jeremy Bennett 6 | 7 | This file is part of Embench and was formerly part of the Bristol/Embecosm 8 | Embedded Benchmark Suite. 9 | 10 | SPDX-License-Identifier: GPL-3.0-or-later */ 11 | 12 | #ifndef BEEBSC_H 13 | #define BEEBSC_H 14 | 15 | #include 16 | 17 | /* BEEBS fixes RAND_MAX to its lowest permitted value, 2^15-1 */ 18 | 19 | #ifdef RAND_MAX 20 | #undef RAND_MAX 21 | #endif 22 | #define RAND_MAX ((1U << 15) - 1) 23 | 24 | /* Simplified assert. 25 | 26 | The full complexity of assert is not needed for a benchmark. See the 27 | discussion at: 28 | 29 | https://lists.librecores.org/pipermail/embench/2019-August/000007.html 30 | 31 | This function just*/ 32 | 33 | #define assert_beebs(expr) { if (!(expr)) exit (1); } 34 | 35 | /* Local simplified versions of library functions */ 36 | 37 | int rand_beebs (void); 38 | void srand_beebs (unsigned int new_seed); 39 | 40 | void init_heap_beebs (void *heap, const size_t heap_size); 41 | int check_heap_beebs (void *heap); 42 | void *malloc_beebs (size_t size); 43 | void *calloc_beebs (size_t nmemb, size_t size); 44 | void *realloc_beebs (void *ptr, size_t size); 45 | void free_beebs (void *ptr); 46 | #endif /* BEEBSC_H */ 47 | 48 | 49 | /* 50 | Local Variables: 51 | mode: C 52 | c-file-style: "gnu" 53 | End: 54 | */ 55 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/led/led.c: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | #include 6 | #define CLK_FIXED_FREQ_HZ (50ULL * 1000 * 1000) 7 | 8 | /** 9 | * Delay loop executing within 8 cycles on ibex 10 | */ 11 | static void delay_loop_ibex(unsigned long loops) { 12 | int out; /* only to notify compiler of modifications to |loops| */ 13 | asm volatile( 14 | "1: nop \n" // 1 cycle 15 | " nop \n" // 1 cycle 16 | " nop \n" // 1 cycle 17 | " nop \n" // 1 cycle 18 | " addi %1, %1, -1 \n" // 1 cycle 19 | " bnez %1, 1b \n" // 3 cycles 20 | : "=&r" (out) 21 | : "0" (loops) 22 | ); 23 | } 24 | 25 | static int usleep_ibex(unsigned long usec) { 26 | unsigned long usec_cycles; 27 | usec_cycles = CLK_FIXED_FREQ_HZ * usec / 1000 / 1000 / 8; 28 | 29 | delay_loop_ibex(usec_cycles); 30 | return 0; 31 | } 32 | 33 | static int usleep(unsigned long usec) { 34 | return usleep_ibex(usec); 35 | } 36 | 37 | int main(int argc, char **argv) { 38 | volatile uint32_t *var = (volatile uint32_t *) 0x10000000; 39 | *var = 0; 40 | 41 | //asm("csrci 0x7c0, 1"); // disable icache 42 | asm("csrsi 0x7c0, 1"); // enable icache 43 | 44 | while (1) { 45 | usleep(1000 * 1000); // 1000 ms 46 | //usleep(1 * 1000); // 1 ms 47 | *var = *var + 1; 48 | } 49 | } 50 | -------------------------------------------------------------------------------- /rtl/wb_if.sv: -------------------------------------------------------------------------------- 1 | /* Classic pipelined bus cycle Wishbone 2 | * 3 | * These modport expressions do not work with Design Compiler: 4 | * 5 | * modport master (.dat_i(dat_s), .dat_o(dat_m), ...); 6 | * modport slave (.dat_i(dat_m), .dat_o(dat_s), ...); 7 | */ 8 | 9 | interface wb_if 10 | (input logic rst, 11 | input logic clk); 12 | 13 | import wb_pkg::*; 14 | 15 | logic ack; 16 | adr_t adr; 17 | logic cyc; 18 | logic stall; 19 | logic stb; 20 | logic we; 21 | sel_t sel; 22 | logic err; 23 | dat_t dat_m; // channel from master 24 | dat_t dat_s; // channel from slave 25 | 26 | modport master 27 | (input clk, 28 | input rst, 29 | input ack, 30 | output adr, 31 | output cyc, 32 | input stall, 33 | output stb, 34 | output we, 35 | output sel, 36 | input err, 37 | `ifdef NO_MODPORT_EXPRESSIONS 38 | input dat_s, 39 | output dat_m 40 | `else 41 | input .dat_i(dat_s), 42 | output .dat_o(dat_m) 43 | `endif 44 | ); 45 | 46 | modport slave 47 | (input clk, 48 | input rst, 49 | output ack, 50 | input adr, 51 | input cyc, 52 | output stall, 53 | input stb, 54 | input we, 55 | input sel, 56 | output err, 57 | `ifdef NO_MODPORT_EXPRESSIONS 58 | input dat_m, 59 | output dat_s 60 | `else 61 | input .dat_i(dat_m), 62 | output .dat_o(dat_s) 63 | `endif 64 | ); 65 | 66 | modport monitor 67 | (input clk, 68 | input rst, 69 | input ack, 70 | input adr, 71 | input cyc, 72 | input stall, 73 | input stb, 74 | input we, 75 | input sel, 76 | input err, 77 | input dat_m, 78 | input dat_s); 79 | endinterface: wb_if 80 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/crc_32/crt0.S: -------------------------------------------------------------------------------- 1 | .section .text 2 | 3 | default_exc_handler: 4 | jal x0, default_exc_handler 5 | 6 | reset_handler: 7 | /* set all registers to zero */ 8 | mv x1, x0 9 | mv x2, x1 10 | mv x3, x1 11 | mv x4, x1 12 | mv x5, x1 13 | mv x6, x1 14 | mv x7, x1 15 | mv x8, x1 16 | mv x9, x1 17 | mv x10, x1 18 | mv x11, x1 19 | mv x12, x1 20 | mv x13, x1 21 | mv x14, x1 22 | mv x15, x1 23 | mv x16, x1 24 | mv x17, x1 25 | mv x18, x1 26 | mv x19, x1 27 | mv x20, x1 28 | mv x21, x1 29 | mv x22, x1 30 | mv x23, x1 31 | mv x24, x1 32 | mv x25, x1 33 | mv x26, x1 34 | mv x27, x1 35 | mv x28, x1 36 | mv x29, x1 37 | mv x30, x1 38 | mv x31, x1 39 | 40 | /* stack initilization */ 41 | la x2, _stack_start 42 | 43 | _start: 44 | .global _start 45 | 46 | /* clear BSS */ 47 | la x26, _bss_start 48 | la x27, _bss_end 49 | 50 | bge x26, x27, zero_loop_end 51 | 52 | zero_loop: 53 | sw x0, 0(x26) 54 | addi x26, x26, 4 55 | ble x26, x27, zero_loop 56 | zero_loop_end: 57 | 58 | 59 | main_entry: 60 | /* jump to main program entry point (argc = argv = 0) */ 61 | addi x10, x0, 0 62 | addi x11, x0, 0 63 | jal x1, main 64 | 65 | /* =================================================== [ exceptions ] === */ 66 | /* This section has to be down here, since we have to disable rvc for it */ 67 | 68 | .section .vectors, "ax" 69 | .option norvc; 70 | 71 | // external interrupts are handled by the same callback 72 | // until compiler supports IRQ routines 73 | .org 0x00 74 | .rept 31 75 | nop 76 | .endr 77 | jal x0, default_exc_handler 78 | 79 | // reset vector 80 | .org 0x80 81 | jal x0, reset_handler 82 | 83 | // illegal instruction exception 84 | .org 0x84 85 | jal x0, default_exc_handler 86 | 87 | // ecall handler 88 | .org 0x88 89 | jal x0, default_exc_handler 90 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/fib/crt0.S: -------------------------------------------------------------------------------- 1 | .section .text 2 | 3 | default_exc_handler: 4 | jal x0, default_exc_handler 5 | 6 | reset_handler: 7 | /* set all registers to zero */ 8 | mv x1, x0 9 | mv x2, x1 10 | mv x3, x1 11 | mv x4, x1 12 | mv x5, x1 13 | mv x6, x1 14 | mv x7, x1 15 | mv x8, x1 16 | mv x9, x1 17 | mv x10, x1 18 | mv x11, x1 19 | mv x12, x1 20 | mv x13, x1 21 | mv x14, x1 22 | mv x15, x1 23 | mv x16, x1 24 | mv x17, x1 25 | mv x18, x1 26 | mv x19, x1 27 | mv x20, x1 28 | mv x21, x1 29 | mv x22, x1 30 | mv x23, x1 31 | mv x24, x1 32 | mv x25, x1 33 | mv x26, x1 34 | mv x27, x1 35 | mv x28, x1 36 | mv x29, x1 37 | mv x30, x1 38 | mv x31, x1 39 | 40 | /* stack initilization */ 41 | la x2, _stack_start 42 | 43 | _start: 44 | .global _start 45 | 46 | /* clear BSS */ 47 | la x26, _bss_start 48 | la x27, _bss_end 49 | 50 | bge x26, x27, zero_loop_end 51 | 52 | zero_loop: 53 | sw x0, 0(x26) 54 | addi x26, x26, 4 55 | ble x26, x27, zero_loop 56 | zero_loop_end: 57 | 58 | 59 | main_entry: 60 | /* jump to main program entry point (argc = argv = 0) */ 61 | addi x10, x0, 0 62 | addi x11, x0, 0 63 | jal x1, main 64 | 65 | /* =================================================== [ exceptions ] === */ 66 | /* This section has to be down here, since we have to disable rvc for it */ 67 | 68 | .section .vectors, "ax" 69 | .option norvc; 70 | 71 | // external interrupts are handled by the same callback 72 | // until compiler supports IRQ routines 73 | .org 0x00 74 | .rept 31 75 | nop 76 | .endr 77 | jal x0, default_exc_handler 78 | 79 | // reset vector 80 | .org 0x80 81 | jal x0, reset_handler 82 | 83 | // illegal instruction exception 84 | .org 0x84 85 | jal x0, default_exc_handler 86 | 87 | // ecall handler 88 | .org 0x88 89 | jal x0, default_exc_handler 90 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/led/crt0.S: -------------------------------------------------------------------------------- 1 | .section .text 2 | 3 | default_exc_handler: 4 | jal x0, default_exc_handler 5 | 6 | reset_handler: 7 | /* set all registers to zero */ 8 | mv x1, x0 9 | mv x2, x1 10 | mv x3, x1 11 | mv x4, x1 12 | mv x5, x1 13 | mv x6, x1 14 | mv x7, x1 15 | mv x8, x1 16 | mv x9, x1 17 | mv x10, x1 18 | mv x11, x1 19 | mv x12, x1 20 | mv x13, x1 21 | mv x14, x1 22 | mv x15, x1 23 | mv x16, x1 24 | mv x17, x1 25 | mv x18, x1 26 | mv x19, x1 27 | mv x20, x1 28 | mv x21, x1 29 | mv x22, x1 30 | mv x23, x1 31 | mv x24, x1 32 | mv x25, x1 33 | mv x26, x1 34 | mv x27, x1 35 | mv x28, x1 36 | mv x29, x1 37 | mv x30, x1 38 | mv x31, x1 39 | 40 | /* stack initilization */ 41 | la x2, _stack_start 42 | 43 | _start: 44 | .global _start 45 | 46 | /* clear BSS */ 47 | la x26, _bss_start 48 | la x27, _bss_end 49 | 50 | bge x26, x27, zero_loop_end 51 | 52 | zero_loop: 53 | sw x0, 0(x26) 54 | addi x26, x26, 4 55 | ble x26, x27, zero_loop 56 | zero_loop_end: 57 | 58 | 59 | main_entry: 60 | /* jump to main program entry point (argc = argv = 0) */ 61 | addi x10, x0, 0 62 | addi x11, x0, 0 63 | jal x1, main 64 | 65 | /* =================================================== [ exceptions ] === */ 66 | /* This section has to be down here, since we have to disable rvc for it */ 67 | 68 | .section .vectors, "ax" 69 | .option norvc; 70 | 71 | // external interrupts are handled by the same callback 72 | // until compiler supports IRQ routines 73 | .org 0x00 74 | .rept 31 75 | nop 76 | .endr 77 | jal x0, default_exc_handler 78 | 79 | // reset vector 80 | .org 0x80 81 | jal x0, reset_handler 82 | 83 | // illegal instruction exception 84 | .org 0x84 85 | jal x0, default_exc_handler 86 | 87 | // ecall handler 88 | .org 0x88 89 | jal x0, default_exc_handler 90 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/crc_32/tb.sv: -------------------------------------------------------------------------------- 1 | /* Testbench */ 2 | 3 | `default_nettype none 4 | 5 | module tb; 6 | timeunit 1ns / 1ps; 7 | 8 | const realtime tclk = 1s / 100.0e6; 9 | 10 | localparam ram_base_addr = 'h00000000; 11 | localparam ram_size = 'h10000; 12 | 13 | bit clk; 14 | bit rst = 1'b1; 15 | 16 | bit test_en; 17 | bit [31:0] hart_id; 18 | bit [31:0] boot_addr; 19 | bit irq_software; 20 | bit irq_timer; 21 | bit irq_external; 22 | bit [14:0] irq_fast; 23 | bit irq_nm; 24 | bit debug_req; 25 | bit fetch_enable = 1'b1; 26 | wire core_sleep; 27 | 28 | wb_if wbm[2](.*); 29 | wb_if wbs[1](.*); 30 | 31 | wb_ibex_core dut 32 | (.rst_n (~rst), 33 | .instr_wb (wbm[0]), 34 | .data_wb (wbm[1]), 35 | .*); 36 | 37 | wb_interconnect_sharedbus 38 | #(.numm (2), 39 | .nums (1), 40 | .base_addr ({ram_base_addr}), 41 | .size ({ram_size}) ) 42 | wb_intercon 43 | (.*); 44 | 45 | wb_spramx32 #(ram_size) wb_spram(.wb(wbs[0])); 46 | 47 | wb_checker wbm0_checker(wbm[0]); 48 | wb_checker wbm1_checker(wbm[1]); 49 | wb_checker wbs0_checker(wbs[0]); 50 | 51 | always #(tclk / 2) clk = ~clk; 52 | 53 | initial 54 | begin:main 55 | string filename; 56 | int status; 57 | 58 | $timeformat(-9, 3, " ns"); 59 | 60 | status = $value$plusargs("filename=%s", filename); 61 | assert(status) else $fatal(1, "No memory file provided. Please use './simv '+filename="); 62 | $readmemh(filename, tb.wb_spram.spram.mem); 63 | 64 | repeat (3) @(negedge clk); 65 | rst = 1'b0; 66 | 67 | repeat (43500) @(negedge clk); 68 | $finish; 69 | end:main 70 | endmodule 71 | 72 | `resetall 73 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/nettle-aes/crt0.S: -------------------------------------------------------------------------------- 1 | .section .text 2 | 3 | default_exc_handler: 4 | jal x0, default_exc_handler 5 | 6 | reset_handler: 7 | /* set all registers to zero */ 8 | mv x1, x0 9 | mv x2, x1 10 | mv x3, x1 11 | mv x4, x1 12 | mv x5, x1 13 | mv x6, x1 14 | mv x7, x1 15 | mv x8, x1 16 | mv x9, x1 17 | mv x10, x1 18 | mv x11, x1 19 | mv x12, x1 20 | mv x13, x1 21 | mv x14, x1 22 | mv x15, x1 23 | mv x16, x1 24 | mv x17, x1 25 | mv x18, x1 26 | mv x19, x1 27 | mv x20, x1 28 | mv x21, x1 29 | mv x22, x1 30 | mv x23, x1 31 | mv x24, x1 32 | mv x25, x1 33 | mv x26, x1 34 | mv x27, x1 35 | mv x28, x1 36 | mv x29, x1 37 | mv x30, x1 38 | mv x31, x1 39 | 40 | /* stack initilization */ 41 | la x2, _stack_start 42 | 43 | _start: 44 | .global _start 45 | 46 | /* clear BSS */ 47 | la x26, _bss_start 48 | la x27, _bss_end 49 | 50 | bge x26, x27, zero_loop_end 51 | 52 | zero_loop: 53 | sw x0, 0(x26) 54 | addi x26, x26, 4 55 | ble x26, x27, zero_loop 56 | zero_loop_end: 57 | 58 | 59 | main_entry: 60 | /* jump to main program entry point (argc = argv = 0) */ 61 | addi x10, x0, 0 62 | addi x11, x0, 0 63 | jal x1, main 64 | 65 | /* =================================================== [ exceptions ] === */ 66 | /* This section has to be down here, since we have to disable rvc for it */ 67 | 68 | .section .vectors, "ax" 69 | .option norvc; 70 | 71 | // external interrupts are handled by the same callback 72 | // until compiler supports IRQ routines 73 | .org 0x00 74 | .rept 31 75 | nop 76 | .endr 77 | jal x0, default_exc_handler 78 | 79 | // reset vector 80 | .org 0x80 81 | jal x0, reset_handler 82 | 83 | // illegal instruction exception 84 | .org 0x84 85 | jal x0, default_exc_handler 86 | 87 | // ecall handler 88 | .org 0x88 89 | jal x0, default_exc_handler 90 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/nettle-aes/tb.sv: -------------------------------------------------------------------------------- 1 | /* Testbench */ 2 | 3 | `default_nettype none 4 | 5 | module tb; 6 | timeunit 1ns / 1ps; 7 | 8 | const realtime tclk = 1s / 100.0e6; 9 | 10 | localparam ram_base_addr = 'h00000000; 11 | localparam ram_size = 'h10000; 12 | 13 | bit clk; 14 | bit rst = 1'b1; 15 | 16 | bit test_en; 17 | bit [31:0] hart_id; 18 | bit [31:0] boot_addr; 19 | bit irq_software; 20 | bit irq_timer; 21 | bit irq_external; 22 | bit [14:0] irq_fast; 23 | bit irq_nm; 24 | bit debug_req; 25 | bit fetch_enable = 1'b1; 26 | wire core_sleep; 27 | 28 | wb_if wbm[2](.*); 29 | wb_if wbs[1](.*); 30 | 31 | wb_ibex_core dut 32 | (.rst_n (~rst), 33 | .instr_wb (wbm[0]), 34 | .data_wb (wbm[1]), 35 | .*); 36 | 37 | wb_interconnect_sharedbus 38 | #(.numm (2), 39 | .nums (1), 40 | .base_addr ({ram_base_addr}), 41 | .size ({ram_size}) ) 42 | wb_intercon 43 | (.*); 44 | 45 | wb_spramx32 #(ram_size) wb_spram(.wb(wbs[0])); 46 | 47 | wb_checker wbm0_checker(wbm[0]); 48 | wb_checker wbm1_checker(wbm[1]); 49 | wb_checker wbs0_checker(wbs[0]); 50 | 51 | always #(tclk / 2) clk = ~clk; 52 | 53 | initial 54 | begin:main 55 | string filename; 56 | int status; 57 | 58 | $timeformat(-9, 3, " ns"); 59 | 60 | status = $value$plusargs("filename=%s", filename); 61 | assert(status) else $fatal(1, "No memory file provided. Please use './simv '+filename="); 62 | $readmemh(filename, tb.wb_spram.spram.mem); 63 | 64 | repeat (3) @(negedge clk); 65 | rst = 1'b0; 66 | 67 | repeat (119000) @(negedge clk); 68 | 69 | // do @(posedge clk); while (wbm[0].ack); 70 | $finish; 71 | end:main 72 | endmodule 73 | 74 | `resetall 75 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | // Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | // -------------------------------------------------------------------------------- 4 | // Tool Version: Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024 5 | // Date : Sun Apr 13 12:16:12 2025 6 | // Host : Bender running 64-bit Ubuntu 24.04.2 LTS 7 | // Command : write_verilog -force -mode synth_stub 8 | // /home/bernd/Projects/github.com/pbing/ibex_wb/soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz_stub.v 9 | // Design : clkgen_50mhz 10 | // Purpose : Stub declaration of top-level module interface 11 | // Device : xc7a100tcsg324-1 12 | // -------------------------------------------------------------------------------- 13 | 14 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 15 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 16 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 17 | (* CORE_GENERATION_INFO = "clkgen_50mhz,clk_wiz_v6_0_15_0_0,{component_name=clkgen_50mhz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 18 | module clkgen_50mhz(clk_out1, clk_in1) 19 | /* synthesis syn_black_box black_box_pad_pin="clk_in1" */ 20 | /* synthesis syn_force_seq_prim="clk_out1" */; 21 | output clk_out1 /* synthesis syn_isclock = 1 */; 22 | input clk_in1; 23 | endmodule 24 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | -- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | -- -------------------------------------------------------------------------------- 4 | -- Tool Version: Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024 5 | -- Date : Sun Apr 13 12:16:12 2025 6 | -- Host : Bender running 64-bit Ubuntu 24.04.2 LTS 7 | -- Command : write_vhdl -force -mode synth_stub 8 | -- /home/bernd/Projects/github.com/pbing/ibex_wb/soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz_stub.vhdl 9 | -- Design : clkgen_50mhz 10 | -- Purpose : Stub declaration of top-level module interface 11 | -- Device : xc7a100tcsg324-1 12 | -- -------------------------------------------------------------------------------- 13 | library IEEE; 14 | use IEEE.STD_LOGIC_1164.ALL; 15 | 16 | entity clkgen_50mhz is 17 | Port ( 18 | clk_out1 : out STD_LOGIC; 19 | clk_in1 : in STD_LOGIC 20 | ); 21 | 22 | attribute CORE_GENERATION_INFO : string; 23 | attribute CORE_GENERATION_INFO of clkgen_50mhz : entity is "clkgen_50mhz,clk_wiz_v6_0_15_0_0,{component_name=clkgen_50mhz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; 24 | end clkgen_50mhz; 25 | 26 | architecture stub of clkgen_50mhz is 27 | attribute syn_black_box : boolean; 28 | attribute black_box_pad_pin : string; 29 | attribute syn_black_box of stub : architecture is true; 30 | attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_in1"; 31 | begin 32 | end; 33 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/crc_32/support.h: -------------------------------------------------------------------------------- 1 | /* Support header for BEEBS. 2 | 3 | Copyright (C) 2014 Embecosm Limited and the University of Bristol 4 | Copyright (C) 2019 Embecosm Limited 5 | 6 | Contributor James Pallister 7 | 8 | Contributor Jeremy Bennett 9 | 10 | This file is part of Embench and was formerly part of the Bristol/Embecosm 11 | Embedded Benchmark Suite. 12 | 13 | SPDX-License-Identifier: GPL-3.0-or-later */ 14 | 15 | #ifndef SUPPORT_H 16 | #define SUPPORT_H 17 | 18 | #ifdef HAVE_CONFIG_H 19 | #include "config.h" 20 | #endif 21 | 22 | /* Include board support header if we have one */ 23 | 24 | #ifdef HAVE_BOARDSUPPORT_H 25 | #include "boardsupport.h" 26 | #endif 27 | 28 | /* Benchmarks must implement verify_benchmark, which must return -1 if no 29 | verification is done. */ 30 | 31 | int verify_benchmark (int result); 32 | 33 | /* Standard functions implemented for each board */ 34 | 35 | void initialise_board (void); 36 | void start_trigger (void); 37 | void stop_trigger (void); 38 | 39 | /* Every benchmark implements this for one-off data initialization. This is 40 | only used for initialization that is independent of how often benchmark () 41 | is called. */ 42 | 43 | void initialise_benchmark (void); 44 | 45 | /* Every benchmark implements this for cache warm up, typically calling 46 | benchmark several times. The argument controls how much warming up is 47 | done, with 0 meaning no warming. */ 48 | 49 | void warm_caches (int temperature); 50 | 51 | /* Every benchmark implements this as its entry point. Don't allow it to be 52 | inlined! */ 53 | 54 | int benchmark (void) __attribute__ ((noinline)); 55 | 56 | /* Every benchmark must implement this to validate the result of the 57 | benchmark. */ 58 | 59 | int verify_benchmark (int res); 60 | 61 | /* Local simplified versions of library functions */ 62 | 63 | #include "beebsc.h" 64 | 65 | #endif /* SUPPORT_H */ 66 | 67 | /* 68 | Local Variables: 69 | mode: C 70 | c-file-style: "gnu" 71 | End: 72 | */ 73 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/nettle-aes/support.h: -------------------------------------------------------------------------------- 1 | /* Support header for BEEBS. 2 | 3 | Copyright (C) 2014 Embecosm Limited and the University of Bristol 4 | Copyright (C) 2019 Embecosm Limited 5 | 6 | Contributor James Pallister 7 | 8 | Contributor Jeremy Bennett 9 | 10 | This file is part of Embench and was formerly part of the Bristol/Embecosm 11 | Embedded Benchmark Suite. 12 | 13 | SPDX-License-Identifier: GPL-3.0-or-later */ 14 | 15 | #ifndef SUPPORT_H 16 | #define SUPPORT_H 17 | 18 | #ifdef HAVE_CONFIG_H 19 | #include "config.h" 20 | #endif 21 | 22 | /* Include board support header if we have one */ 23 | 24 | #ifdef HAVE_BOARDSUPPORT_H 25 | #include "boardsupport.h" 26 | #endif 27 | 28 | /* Benchmarks must implement verify_benchmark, which must return -1 if no 29 | verification is done. */ 30 | 31 | int verify_benchmark (int result); 32 | 33 | /* Standard functions implemented for each board */ 34 | 35 | void initialise_board (void); 36 | void start_trigger (void); 37 | void stop_trigger (void); 38 | 39 | /* Every benchmark implements this for one-off data initialization. This is 40 | only used for initialization that is independent of how often benchmark () 41 | is called. */ 42 | 43 | void initialise_benchmark (void); 44 | 45 | /* Every benchmark implements this for cache warm up, typically calling 46 | benchmark several times. The argument controls how much warming up is 47 | done, with 0 meaning no warming. */ 48 | 49 | void warm_caches (int temperature); 50 | 51 | /* Every benchmark implements this as its entry point. Don't allow it to be 52 | inlined! */ 53 | 54 | int benchmark (void) __attribute__ ((noinline)); 55 | 56 | /* Every benchmark must implement this to validate the result of the 57 | benchmark. */ 58 | 59 | int verify_benchmark (int res); 60 | 61 | /* Local simplified versions of library functions */ 62 | 63 | #include "beebsc.h" 64 | 65 | #endif /* SUPPORT_H */ 66 | 67 | /* 68 | Local Variables: 69 | mode: C 70 | c-file-style: "gnu" 71 | End: 72 | */ 73 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/fib/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright lowRISC contributors. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Generate a baremetal application 6 | 7 | PROGRAM ?= fib 8 | PROGRAM_CFLAGS = -Wall -g -Os 9 | #PROGRAM_CFLAGS = -Wall -g -O0 10 | ARCH = rv32imc_zicsr 11 | #ARCH = rv32im_zicsr # to disable compressed instructions 12 | SRCS = $(PROGRAM).c 13 | 14 | CC = riscv64-unknown-elf-gcc 15 | 16 | OBJCOPY ?= $(subst gcc,objcopy,$(wordlist 1,1,$(CC))) 17 | OBJDUMP ?= $(subst gcc,objdump,$(wordlist 1,1,$(CC))) 18 | 19 | LINKER_SCRIPT ?= link.ld 20 | CRT ?= crt0.S 21 | CFLAGS ?= -march=$(ARCH) -mabi=ilp32 -static -mcmodel=medany \ 22 | -fvisibility=hidden -nostdlib -nostartfiles $(PROGRAM_CFLAGS) 23 | 24 | OBJS := ${SRCS:.c=.o} ${CRT:.S=.o} 25 | DEPS = $(OBJS:%.o=%.d) 26 | 27 | OUTFILES = $(PROGRAM).elf $(PROGRAM).vmem $(PROGRAM).bin $(PROGRAM).dis 28 | 29 | HEX2VMEM = ../../../../../scripts/hex2vmem.pl 30 | 31 | all: $(OUTFILES) 32 | 33 | $(PROGRAM).elf: $(OBJS) $(LINKER_SCRIPT) 34 | $(CC) $(CFLAGS) -T $(LINKER_SCRIPT) $(OBJS) -o $@ $(LIBS) 35 | 36 | %.dis: %.elf 37 | $(OBJDUMP) -SD $^ > $@ 38 | 39 | # Note: this target requires the srecord package to be installed. 40 | # XXX: This could be replaced by objcopy once 41 | # https://sourceware.org/bugzilla/show_bug.cgi?id=19921 42 | # is widely available. 43 | # XXX: Currently the start address 0x00000000 is hardcoded. It could/should be 44 | # read from the elf file, but is lost in the bin file. 45 | # Switching to objcopy will resolve that as well. 46 | # %.vmem: %.bin 47 | # srec_cat $^ -binary -offset 0x0000 -byte-swap 4 -o $@ -vmem 48 | %.vmem: %.hex 49 | $(HEX2VMEM) $< > $@ 50 | 51 | %.hex: %.elf 52 | $(OBJCOPY) -O verilog --interleave-width=4 --interleave=4 --byte=0 $< $@ 53 | 54 | %.bin: %.elf 55 | $(OBJCOPY) -O binary $< $@ 56 | 57 | %.o: %.c 58 | $(CC) $(CFLAGS) -MMD -c $(INCS) -o $@ $< 59 | 60 | %.o: %.S 61 | $(CC) $(CFLAGS) -MMD -c $(INCS) -o $@ $< 62 | 63 | clean: 64 | $(RM) -f *.o *.d *.hex 65 | 66 | distclean: clean 67 | $(RM) -f $(OUTFILES) 68 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/led/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright lowRISC contributors. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Generate a baremetal application 6 | 7 | PROGRAM ?= led 8 | PROGRAM_CFLAGS = -Wall -g -Os 9 | #PROGRAM_CFLAGS = -Wall -g -O0 10 | ARCH = rv32imc_zicsr 11 | #ARCH = rv32im_zicsr # to disable compressed instructions 12 | SRCS = $(PROGRAM).c 13 | 14 | CC = riscv64-unknown-elf-gcc 15 | 16 | OBJCOPY ?= $(subst gcc,objcopy,$(wordlist 1,1,$(CC))) 17 | OBJDUMP ?= $(subst gcc,objdump,$(wordlist 1,1,$(CC))) 18 | 19 | LINKER_SCRIPT ?= link.ld 20 | CRT ?= crt0.S 21 | CFLAGS ?= -march=$(ARCH) -mabi=ilp32 -static -mcmodel=medany \ 22 | -fvisibility=hidden -nostdlib -nostartfiles $(PROGRAM_CFLAGS) 23 | 24 | OBJS := ${SRCS:.c=.o} ${CRT:.S=.o} 25 | DEPS = $(OBJS:%.o=%.d) 26 | 27 | OUTFILES = $(PROGRAM).elf $(PROGRAM).vmem $(PROGRAM).bin $(PROGRAM).dis 28 | 29 | HEX2VMEM = ../../../../../scripts/hex2vmem.pl 30 | 31 | all: $(OUTFILES) 32 | 33 | $(PROGRAM).elf: $(OBJS) $(LINKER_SCRIPT) 34 | $(CC) $(CFLAGS) -T $(LINKER_SCRIPT) $(OBJS) -o $@ $(LIBS) 35 | 36 | %.dis: %.elf 37 | $(OBJDUMP) -SD $^ > $@ 38 | 39 | # Note: this target requires the srecord package to be installed. 40 | # XXX: This could be replaced by objcopy once 41 | # https://sourceware.org/bugzilla/show_bug.cgi?id=19921 42 | # is widely available. 43 | # XXX: Currently the start address 0x00000000 is hardcoded. It could/should be 44 | # read from the elf file, but is lost in the bin file. 45 | # Switching to objcopy will resolve that as well. 46 | # %.vmem: %.bin 47 | # srec_cat $^ -binary -offset 0x0000 -byte-swap 4 -o $@ -vmem 48 | %.vmem: %.hex 49 | $(HEX2VMEM) $< > $@ 50 | 51 | %.hex: %.elf 52 | $(OBJCOPY) -O verilog --interleave-width=4 --interleave=4 --byte=0 $< $@ 53 | 54 | %.bin: %.elf 55 | $(OBJCOPY) -O binary $< $@ 56 | 57 | %.o: %.c 58 | $(CC) $(CFLAGS) -MMD -c $(INCS) -o $@ $< 59 | 60 | %.o: %.S 61 | $(CC) $(CFLAGS) -MMD -c $(INCS) -o $@ $< 62 | 63 | clean: 64 | $(RM) -f *.o *.d *.hex 65 | 66 | distclean: clean 67 | $(RM) -f $(OUTFILES) 68 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/crc_32/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright lowRISC contributors. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Generate a baremetal application 6 | 7 | PROGRAM ?= crc_32 8 | PROGRAM_CFLAGS = -Wall -g -Os -DCPU_MHZ=1 -DWARMUP_HEAT=0 9 | #PROGRAM_CFLAGS = -Wall -g -Os -msave-restore -fdata-sections -ffunction-sections -DCPU_MHZ=1 -DWARMUP_HEAT=0 10 | ARCH = rv32imc_zicsr 11 | #ARCH = rv32im_zicsr # to disable compressed instructions 12 | SRCS = $(PROGRAM).c beebsc.c board.c main.c 13 | 14 | CC = riscv64-unknown-elf-gcc 15 | 16 | OBJCOPY ?= $(subst gcc,objcopy,$(wordlist 1,1,$(CC))) 17 | OBJDUMP ?= $(subst gcc,objdump,$(wordlist 1,1,$(CC))) 18 | 19 | LINKER_SCRIPT ?= link.ld 20 | CRT ?= crt0.S 21 | CFLAGS ?= -march=$(ARCH) -mabi=ilp32 -static -mcmodel=medany \ 22 | -fvisibility=hidden -nostdlib -nostartfiles $(PROGRAM_CFLAGS) 23 | 24 | OBJS := ${SRCS:.c=.o} ${CRT:.S=.o} 25 | DEPS = $(OBJS:%.o=%.d) 26 | 27 | OUTFILES = $(PROGRAM).elf $(PROGRAM).vmem $(PROGRAM).bin $(PROGRAM).dis 28 | 29 | HEX2VMEM = ../../../../../scripts/hex2vmem.pl 30 | 31 | all: $(OUTFILES) 32 | 33 | $(PROGRAM).elf: $(OBJS) $(LINKER_SCRIPT) 34 | $(CC) $(CFLAGS) -T $(LINKER_SCRIPT) $(OBJS) -o $@ $(LIBS) 35 | 36 | %.dis: %.elf 37 | $(OBJDUMP) -SD $^ > $@ 38 | 39 | # Note: this target requires the srecord package to be installed. 40 | # XXX: This could be replaced by objcopy once 41 | # https://sourceware.org/bugzilla/show_bug.cgi?id=19921 42 | # is widely available. 43 | # XXX: Currently the start address 0x00000000 is hardcoded. It could/should be 44 | # read from the elf file, but is lost in the bin file. 45 | # Switching to objcopy will resolve that as well. 46 | # %.vmem: %.bin 47 | # srec_cat $^ -binary -offset 0x0000 -byte-swap 4 -o $@ -vmem 48 | %.vmem: %.hex 49 | $(HEX2VMEM) $< > $@ 50 | 51 | %.hex: %.elf 52 | $(OBJCOPY) -O verilog --interleave-width=4 --interleave=4 --byte=0 $< $@ 53 | 54 | %.bin: %.elf 55 | $(OBJCOPY) -O binary $< $@ 56 | 57 | %.o: %.c 58 | $(CC) $(CFLAGS) -MMD -c $(INCS) -o $@ $< 59 | 60 | %.o: %.S 61 | $(CC) $(CFLAGS) -MMD -c $(INCS) -o $@ $< 62 | 63 | clean: 64 | $(RM) -f *.o *.d *.hex 65 | 66 | distclean: clean 67 | $(RM) -f $(OUTFILES) 68 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/nettle-aes/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright lowRISC contributors. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Generate a baremetal application 6 | 7 | PROGRAM ?= nettle-aes 8 | PROGRAM_CFLAGS = -Wall -g -Os -DCPU_MHZ=1 -DWARMUP_HEAT=0 9 | #PROGRAM_CFLAGS = -Wall -g -Os -msave-restore -fdata-sections -ffunction-sections -DCPU_MHZ=1 -DWARMUP_HEAT=0 10 | ARCH = rv32imc_zicsr 11 | #ARCH = rv32im_zicsr # to disable compressed instructions 12 | SRCS = $(PROGRAM).c beebsc.c board.c main.c 13 | 14 | CC = riscv64-unknown-elf-gcc 15 | 16 | OBJCOPY ?= $(subst gcc,objcopy,$(wordlist 1,1,$(CC))) 17 | OBJDUMP ?= $(subst gcc,objdump,$(wordlist 1,1,$(CC))) 18 | 19 | LINKER_SCRIPT ?= link.ld 20 | CRT ?= crt0.S 21 | CFLAGS ?= -march=$(ARCH) -mabi=ilp32 -static -mcmodel=medany \ 22 | -fvisibility=hidden -nostdlib -nostartfiles $(PROGRAM_CFLAGS) 23 | 24 | OBJS := ${SRCS:.c=.o} ${CRT:.S=.o} 25 | DEPS = $(OBJS:%.o=%.d) 26 | 27 | OUTFILES = $(PROGRAM).elf $(PROGRAM).vmem $(PROGRAM).bin $(PROGRAM).dis 28 | 29 | HEX2VMEM = ../../../../../scripts/hex2vmem.pl 30 | 31 | all: $(OUTFILES) 32 | 33 | $(PROGRAM).elf: $(OBJS) $(LINKER_SCRIPT) 34 | $(CC) $(CFLAGS) -T $(LINKER_SCRIPT) $(OBJS) -o $@ $(LIBS) 35 | 36 | %.dis: %.elf 37 | $(OBJDUMP) -SD $^ > $@ 38 | 39 | # Note: this target requires the srecord package to be installed. 40 | # XXX: This could be replaced by objcopy once 41 | # https://sourceware.org/bugzilla/show_bug.cgi?id=19921 42 | # is widely available. 43 | # XXX: Currently the start address 0x00000000 is hardcoded. It could/should be 44 | # read from the elf file, but is lost in the bin file. 45 | # Switching to objcopy will resolve that as well. 46 | # %.vmem: %.bin 47 | # srec_cat $^ -binary -offset 0x0000 -byte-swap 4 -o $@ -vmem 48 | %.vmem: %.hex 49 | $(HEX2VMEM) $< > $@ 50 | 51 | %.hex: %.elf 52 | $(OBJCOPY) -O verilog --interleave-width=4 --interleave=4 --byte=0 $< $@ 53 | 54 | %.bin: %.elf 55 | $(OBJCOPY) -O binary $< $@ 56 | 57 | %.o: %.c 58 | $(CC) $(CFLAGS) -MMD -c $(INCS) -o $@ $< 59 | 60 | %.o: %.S 61 | $(CC) $(CFLAGS) -MMD -c $(INCS) -o $@ $< 62 | 63 | clean: 64 | $(RM) -f *.o *.d *.hex 65 | 66 | distclean: clean 67 | $(RM) -f $(OUTFILES) 68 | -------------------------------------------------------------------------------- /fv/core2wb/fv_core2wb.sv: -------------------------------------------------------------------------------- 1 | // SVA constraints 2 | 3 | module fv_core2wb 4 | (core_if.monitor core, 5 | wb_if.monitor wb); 6 | 7 | default clocking defclk @(posedge core.clk); 8 | endclocking 9 | 10 | default disable iff (!core.rst_n); 11 | 12 | // -------------------------------------------------------------------------- 13 | // CORE 14 | // -------------------------------------------------------------------------- 15 | 16 | ASM_core_addr_stable: assume property ((core.req && !core.gnt) |=> $stable(core.addr)); 17 | 18 | ASM_core_we_stable: assume property ((core.req && !core.gnt) |=> $stable(core.we)); 19 | 20 | ASM_core_be_stable: assume property ((core.req && !core.gnt && core.we) |=> $stable(core.be)); 21 | 22 | ASM_core_wdata_stable: assume property ((core.req && !core.gnt && core.we) |=> $stable(core.wdata)); 23 | 24 | ASM_core_req_stable: assume property ((core.req && !core.gnt) |=> core.req); 25 | 26 | // -------------------------------------------------------------------------- 27 | // Wishbone 28 | // -------------------------------------------------------------------------- 29 | 30 | AST_wb_adr_stable: assert property ((wb.cyc && wb.stb && wb.stall) |=> $stable(wb.adr)); 31 | 32 | AST_wb_dat_o_stable: assert property ((wb.cyc && wb.stb && wb.stall && wb.we) |=> $stable(wb.dat_m)); 33 | 34 | AST_wb_sel_stable: assert property ((wb.cyc && wb.stb && wb.stall && wb.we) |=> $stable(wb.sel)); 35 | 36 | AST_wb_stb_stable: assert property ((wb.cyc && wb.stb && wb.stall) |=> wb.stb); 37 | 38 | AST_wb_we_stable: assert property ((wb.cyc && wb.stb && wb.stall) |=> $stable(wb.we)); 39 | 40 | AST_wb_cyc_stable: assert property ((wb.cyc && wb.stb && wb.stall) |=> wb.cyc); 41 | 42 | AST_wb_no_stb: assert property (!wb.cyc |-> !wb.stb); 43 | 44 | ASM_wb_no_ack: assume property (!wb.cyc |-> !wb.ack); 45 | 46 | ASM_wb_no_err: assume property (!wb.cyc |-> !wb.err); 47 | 48 | ASM_wb_ack_no_err: assume property ((wb.cyc && wb.ack) |-> !wb.err); 49 | 50 | ASM_wb_err_no_ack: assume property ((wb.cyc && wb.err) |-> !wb.ack); 51 | 52 | // -------------------------------------------------------------------------- 53 | // Covers 54 | // -------------------------------------------------------------------------- 55 | 56 | COV_read: cover property (core.rvalid); 57 | 58 | COV_write: cover property (core.rvalid); 59 | 60 | COV_burst: cover property (core.rvalid[->5]); 61 | endmodule 62 | 63 | bind core2wb fv_core2wb fv(.*); 64 | -------------------------------------------------------------------------------- /fv/wb2core/fv_wb2core.sv: -------------------------------------------------------------------------------- 1 | // SVA constraints 2 | 3 | module fv_wb2core 4 | (core_if.monitor core, 5 | wb_if.monitor wb); 6 | 7 | default clocking defclk @(posedge wb.clk); 8 | endclocking 9 | 10 | //default disable iff (wb.rst); 11 | 12 | // -------------------------------------------------------------------------- 13 | // CORE 14 | // -------------------------------------------------------------------------- 15 | 16 | AST_core_addr_stable: assert property ((core.req && !core.gnt) |=> $stable(core.addr)); 17 | 18 | AST_core_we_stable: assert property ((core.req && !core.gnt) |=> $stable(core.we)); 19 | 20 | AST_core_be_stable: assert property ((core.req && !core.gnt && core.we) |=> $stable(core.be)); 21 | 22 | AST_core_wdata_stable: assert property ((core.req && !core.gnt && core.we) |=> $stable(core.wdata)); 23 | 24 | AST_core_req_stable: assert property ((core.req && !core.gnt) |=> core.req); 25 | 26 | // -------------------------------------------------------------------------- 27 | // Wishbone 28 | // -------------------------------------------------------------------------- 29 | 30 | ASM_wb_adr_stable: assume property ((wb.cyc && wb.stb && wb.stall) |=> $stable(wb.adr)); 31 | 32 | ASM_wb_dat_o_stable: assume property ((wb.cyc && wb.stb && wb.stall && wb.we) |=> $stable(wb.dat_m)); 33 | 34 | ASM_wb_sel_stable: assume property ((wb.cyc && wb.stb && wb.stall && wb.we) |=> $stable(wb.sel)); 35 | 36 | ASM_wb_stb_stable: assume property ((wb.cyc && wb.stb && wb.stall) |=> wb.stb); 37 | 38 | ASM_wb_we_stable: assume property ((wb.cyc && wb.stb && wb.stall) |=> $stable(wb.we)); 39 | 40 | ASM_wb_cyc_stable: assume property ((wb.cyc && wb.stb && wb.stall) |=> wb.cyc); 41 | 42 | ASM_wb_no_stb: assume property (!wb.cyc |-> !wb.stb); 43 | 44 | AST_wb_no_ack: assert property (!wb.cyc |-> !wb.ack); 45 | 46 | AST_wb_no_err: assert property (!wb.cyc |-> !wb.err); 47 | 48 | AST_wb_ack_no_err: assert property ((wb.cyc && wb.ack) |-> !wb.err); 49 | 50 | AST_wb_err_no_ack: assert property ((wb.cyc && wb.err) |-> !wb.ack); 51 | 52 | // -------------------------------------------------------------------------- 53 | // Covers 54 | // -------------------------------------------------------------------------- 55 | 56 | COV_read: cover property (wb.cyc && wb.ack); 57 | 58 | COV_write: cover property (wb.cyc && wb.ack); 59 | 60 | COV_burst: cover property ((wb.cyc && wb.ack)[->5]); 61 | endmodule 62 | 63 | bind wb2core fv_wb2core fv(.*); 64 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/fib/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH(riscv) 2 | 3 | /* required to correctly link newlib */ 4 | GROUP( -lc -lgloss -lgcc -lsupc++ ) 5 | 6 | SEARCH_DIR(.) 7 | __DYNAMIC = 0; 8 | 9 | MEMORY 10 | { 11 | rom : ORIGIN = 0x00000000, LENGTH = 0xC000 /* 48 kB */ 12 | stack : ORIGIN = 0x0000C000, LENGTH = 0x4000 /* 16 kB */ 13 | } 14 | 15 | /* Stack information variables */ 16 | _min_stack = 0x2000; /* 8K - minimum stack space to reserve */ 17 | _stack_len = LENGTH(stack); 18 | _stack_start = ORIGIN(stack) + LENGTH(stack); 19 | 20 | /* We have to align each sector to word boundaries as our current s19->slm 21 | * conversion scripts are not able to handle non-word aligned sections. */ 22 | 23 | SECTIONS 24 | { 25 | .vectors : 26 | { 27 | . = ALIGN(4); 28 | KEEP(*(.vectors)) 29 | } > rom 30 | 31 | .text : { 32 | . = ALIGN(4); 33 | _stext = .; 34 | *(.text) 35 | *(.text.*) 36 | _etext = .; 37 | __CTOR_LIST__ = .; 38 | LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) 39 | *(.ctors) 40 | LONG(0) 41 | __CTOR_END__ = .; 42 | __DTOR_LIST__ = .; 43 | LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) 44 | *(.dtors) 45 | LONG(0) 46 | __DTOR_END__ = .; 47 | *(.lit) 48 | *(.shdata) 49 | . = ALIGN(4); 50 | _endtext = .; 51 | } > rom 52 | 53 | .rodata : { 54 | . = ALIGN(4); 55 | *(.rodata); 56 | *(.rodata.*) 57 | } > rom 58 | 59 | .shbss : 60 | { 61 | . = ALIGN(4); 62 | *(.shbss) 63 | } > rom 64 | 65 | .data : { 66 | . = ALIGN(4); 67 | sdata = .; 68 | _sdata = .; 69 | *(.data); 70 | *(.data.*) 71 | edata = .; 72 | _edata = .; 73 | } > rom 74 | 75 | .bss : 76 | { 77 | . = ALIGN(4); 78 | _bss_start = .; 79 | *(.bss) 80 | *(.bss.*) 81 | *(.sbss) 82 | *(.sbss.*) 83 | *(COMMON) 84 | _bss_end = .; 85 | } > rom 86 | 87 | /* ensure there is enough room for stack */ 88 | .stack (NOLOAD): { 89 | . = ALIGN(4); 90 | . = . + _min_stack ; 91 | . = ALIGN(4); 92 | stack = . ; 93 | _stack = . ; 94 | } > stack 95 | 96 | .stab 0 (NOLOAD) : 97 | { 98 | [ .stab ] 99 | } 100 | 101 | .stabstr 0 (NOLOAD) : 102 | { 103 | [ .stabstr ] 104 | } 105 | } 106 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/led/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH(riscv) 2 | 3 | /* required to correctly link newlib */ 4 | GROUP( -lc -lgloss -lgcc -lsupc++ ) 5 | 6 | SEARCH_DIR(.) 7 | __DYNAMIC = 0; 8 | 9 | MEMORY 10 | { 11 | rom : ORIGIN = 0x00000000, LENGTH = 0xC000 /* 48 kB */ 12 | stack : ORIGIN = 0x0000C000, LENGTH = 0x4000 /* 16 kB */ 13 | } 14 | 15 | /* Stack information variables */ 16 | _min_stack = 0x2000; /* 8K - minimum stack space to reserve */ 17 | _stack_len = LENGTH(stack); 18 | _stack_start = ORIGIN(stack) + LENGTH(stack); 19 | 20 | /* We have to align each sector to word boundaries as our current s19->slm 21 | * conversion scripts are not able to handle non-word aligned sections. */ 22 | 23 | SECTIONS 24 | { 25 | .vectors : 26 | { 27 | . = ALIGN(4); 28 | KEEP(*(.vectors)) 29 | } > rom 30 | 31 | .text : { 32 | . = ALIGN(4); 33 | _stext = .; 34 | *(.text) 35 | *(.text.*) 36 | _etext = .; 37 | __CTOR_LIST__ = .; 38 | LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) 39 | *(.ctors) 40 | LONG(0) 41 | __CTOR_END__ = .; 42 | __DTOR_LIST__ = .; 43 | LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) 44 | *(.dtors) 45 | LONG(0) 46 | __DTOR_END__ = .; 47 | *(.lit) 48 | *(.shdata) 49 | . = ALIGN(4); 50 | _endtext = .; 51 | } > rom 52 | 53 | .rodata : { 54 | . = ALIGN(4); 55 | *(.rodata); 56 | *(.rodata.*) 57 | } > rom 58 | 59 | .shbss : 60 | { 61 | . = ALIGN(4); 62 | *(.shbss) 63 | } > rom 64 | 65 | .data : { 66 | . = ALIGN(4); 67 | sdata = .; 68 | _sdata = .; 69 | *(.data); 70 | *(.data.*) 71 | edata = .; 72 | _edata = .; 73 | } > rom 74 | 75 | .bss : 76 | { 77 | . = ALIGN(4); 78 | _bss_start = .; 79 | *(.bss) 80 | *(.bss.*) 81 | *(.sbss) 82 | *(.sbss.*) 83 | *(COMMON) 84 | _bss_end = .; 85 | } > rom 86 | 87 | /* ensure there is enough room for stack */ 88 | .stack (NOLOAD): { 89 | . = ALIGN(4); 90 | . = . + _min_stack ; 91 | . = ALIGN(4); 92 | stack = . ; 93 | _stack = . ; 94 | } > stack 95 | 96 | .stab 0 (NOLOAD) : 97 | { 98 | [ .stab ] 99 | } 100 | 101 | .stabstr 0 (NOLOAD) : 102 | { 103 | [ .stabstr ] 104 | } 105 | } 106 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/crc_32/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH(riscv) 2 | 3 | /* required to correctly link newlib */ 4 | GROUP( -lc -lgloss -lgcc -lsupc++ ) 5 | 6 | SEARCH_DIR(.) 7 | __DYNAMIC = 0; 8 | 9 | MEMORY 10 | { 11 | rom : ORIGIN = 0x00000000, LENGTH = 0xC000 /* 48 kB */ 12 | stack : ORIGIN = 0x0000C000, LENGTH = 0x4000 /* 16 kB */ 13 | } 14 | 15 | /* Stack information variables */ 16 | _min_stack = 0x2000; /* 8K - minimum stack space to reserve */ 17 | _stack_len = LENGTH(stack); 18 | _stack_start = ORIGIN(stack) + LENGTH(stack); 19 | 20 | /* We have to align each sector to word boundaries as our current s19->slm 21 | * conversion scripts are not able to handle non-word aligned sections. */ 22 | 23 | SECTIONS 24 | { 25 | .vectors : 26 | { 27 | . = ALIGN(4); 28 | KEEP(*(.vectors)) 29 | } > rom 30 | 31 | .text : { 32 | . = ALIGN(4); 33 | _stext = .; 34 | *(.text) 35 | *(.text.*) 36 | _etext = .; 37 | __CTOR_LIST__ = .; 38 | LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) 39 | *(.ctors) 40 | LONG(0) 41 | __CTOR_END__ = .; 42 | __DTOR_LIST__ = .; 43 | LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) 44 | *(.dtors) 45 | LONG(0) 46 | __DTOR_END__ = .; 47 | *(.lit) 48 | *(.shdata) 49 | . = ALIGN(4); 50 | _endtext = .; 51 | } > rom 52 | 53 | .rodata : { 54 | . = ALIGN(4); 55 | *(.rodata); 56 | *(.rodata.*) 57 | } > rom 58 | 59 | .shbss : 60 | { 61 | . = ALIGN(4); 62 | *(.shbss) 63 | } > rom 64 | 65 | .data : { 66 | . = ALIGN(4); 67 | sdata = .; 68 | _sdata = .; 69 | *(.data); 70 | *(.data.*) 71 | edata = .; 72 | _edata = .; 73 | } > rom 74 | 75 | .bss : 76 | { 77 | . = ALIGN(4); 78 | _bss_start = .; 79 | *(.bss) 80 | *(.bss.*) 81 | *(.sbss) 82 | *(.sbss.*) 83 | *(COMMON) 84 | _bss_end = .; 85 | } > rom 86 | 87 | /* ensure there is enough room for stack */ 88 | .stack (NOLOAD): { 89 | . = ALIGN(4); 90 | . = . + _min_stack ; 91 | . = ALIGN(4); 92 | stack = . ; 93 | _stack = . ; 94 | } > stack 95 | 96 | .stab 0 (NOLOAD) : 97 | { 98 | [ .stab ] 99 | } 100 | 101 | .stabstr 0 (NOLOAD) : 102 | { 103 | [ .stabstr ] 104 | } 105 | } 106 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/nettle-aes/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH(riscv) 2 | 3 | /* required to correctly link newlib */ 4 | GROUP( -lc -lgloss -lgcc -lsupc++ ) 5 | 6 | SEARCH_DIR(.) 7 | __DYNAMIC = 0; 8 | 9 | MEMORY 10 | { 11 | rom : ORIGIN = 0x00000000, LENGTH = 0xC000 /* 48 kB */ 12 | stack : ORIGIN = 0x0000C000, LENGTH = 0x4000 /* 16 kB */ 13 | } 14 | 15 | /* Stack information variables */ 16 | _min_stack = 0x2000; /* 8K - minimum stack space to reserve */ 17 | _stack_len = LENGTH(stack); 18 | _stack_start = ORIGIN(stack) + LENGTH(stack); 19 | 20 | /* We have to align each sector to word boundaries as our current s19->slm 21 | * conversion scripts are not able to handle non-word aligned sections. */ 22 | 23 | SECTIONS 24 | { 25 | .vectors : 26 | { 27 | . = ALIGN(4); 28 | KEEP(*(.vectors)) 29 | } > rom 30 | 31 | .text : { 32 | . = ALIGN(4); 33 | _stext = .; 34 | *(.text) 35 | *(.text.*) 36 | _etext = .; 37 | __CTOR_LIST__ = .; 38 | LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) 39 | *(.ctors) 40 | LONG(0) 41 | __CTOR_END__ = .; 42 | __DTOR_LIST__ = .; 43 | LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) 44 | *(.dtors) 45 | LONG(0) 46 | __DTOR_END__ = .; 47 | *(.lit) 48 | *(.shdata) 49 | . = ALIGN(4); 50 | _endtext = .; 51 | } > rom 52 | 53 | .rodata : { 54 | . = ALIGN(4); 55 | *(.rodata); 56 | *(.rodata.*) 57 | } > rom 58 | 59 | .shbss : 60 | { 61 | . = ALIGN(4); 62 | *(.shbss) 63 | } > rom 64 | 65 | .data : { 66 | . = ALIGN(4); 67 | sdata = .; 68 | _sdata = .; 69 | *(.data); 70 | *(.data.*) 71 | edata = .; 72 | _edata = .; 73 | } > rom 74 | 75 | .bss : 76 | { 77 | . = ALIGN(4); 78 | _bss_start = .; 79 | *(.bss) 80 | *(.bss.*) 81 | *(.sbss) 82 | *(.sbss.*) 83 | *(COMMON) 84 | _bss_end = .; 85 | } > rom 86 | 87 | /* ensure there is enough room for stack */ 88 | .stack (NOLOAD): { 89 | . = ALIGN(4); 90 | . = . + _min_stack ; 91 | . = ALIGN(4); 92 | stack = . ; 93 | _stack = . ; 94 | } > stack 95 | 96 | .stab 0 (NOLOAD) : 97 | { 98 | [ .stab ] 99 | } 100 | 101 | .stabstr 0 (NOLOAD) : 102 | { 103 | [ .stabstr ] 104 | } 105 | } 106 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clkgen_50mhz_ooc.xdc 3 | # (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of AMD and is protected under U.S. and international copyright 7 | # and other intellectual property laws. 8 | # 9 | # DISCLAIMER 10 | # This disclaimer is not a license and does not grant any 11 | # rights to the materials distributed herewith. Except as 12 | # otherwise provided in a valid license issued to you by 13 | # AMD, and to the maximum extent permitted by applicable 14 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | # WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 16 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | # (2) AMD shall not be liable (whether in contract or tort, 20 | # including negligence, or under any other theory of 21 | # liability) for any loss or damage of any kind or nature 22 | # related to, arising under or in connection with these 23 | # materials, including for any direct, or any indirect, 24 | # special, incidental, or consequential loss or damage 25 | # (including loss of data, profits, goodwill, or any type of 26 | # loss or damage suffered as a result of any action brought 27 | # by a third party) even if such damage or loss was 28 | # reasonably foreseeable or AMD had been advised of the 29 | # possibility of the same. 30 | # 31 | # CRITICAL APPLICATIONS 32 | # AMD products are not designed or intended to be fail- 33 | # safe, or for use in any application requiring fail-safe 34 | # performance, such as life-support or safety devices or 35 | # systems, Class III medical devices, nuclear facilities, 36 | # applications related to the deployment of airbags, or any 37 | # other applications that could lead to death, personal 38 | # injury, or severe property or environmental damage 39 | # (individually and collectively, "Critical 40 | # Applications"). Customer assumes the sole risk and 41 | # liability of any use of AMD products in Critical 42 | # Applications, subject only to applicable laws and 43 | # regulations governing limitations on product liability. 44 | # 45 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | # PART OF THIS FILE AT ALL TIMES. 47 | 48 | ################# 49 | #DEFAULT CLOCK CONSTRAINTS 50 | 51 | ############################################################ 52 | # Clock Period Constraints # 53 | ############################################################ 54 | #create_clock -period 10.000 [get_ports clk_in1] 55 | 56 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: clkgen_50mhz.xdc 3 | # (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of AMD and is protected under U.S. and international copyright 7 | # and other intellectual property laws. 8 | # 9 | # DISCLAIMER 10 | # This disclaimer is not a license and does not grant any 11 | # rights to the materials distributed herewith. Except as 12 | # otherwise provided in a valid license issued to you by 13 | # AMD, and to the maximum extent permitted by applicable 14 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | # WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 16 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | # (2) AMD shall not be liable (whether in contract or tort, 20 | # including negligence, or under any other theory of 21 | # liability) for any loss or damage of any kind or nature 22 | # related to, arising under or in connection with these 23 | # materials, including for any direct, or any indirect, 24 | # special, incidental, or consequential loss or damage 25 | # (including loss of data, profits, goodwill, or any type of 26 | # loss or damage suffered as a result of any action brought 27 | # by a third party) even if such damage or loss was 28 | # reasonably foreseeable or AMD had been advised of the 29 | # possibility of the same. 30 | # 31 | # CRITICAL APPLICATIONS 32 | # AMD products are not designed or intended to be fail- 33 | # safe, or for use in any application requiring fail-safe 34 | # performance, such as life-support or safety devices or 35 | # systems, Class III medical devices, nuclear facilities, 36 | # applications related to the deployment of airbags, or any 37 | # other applications that could lead to death, personal 38 | # injury, or severe property or environmental damage 39 | # (individually and collectively, "Critical 40 | # Applications"). Customer assumes the sole risk and 41 | # liability of any use of AMD products in Critical 42 | # Applications, subject only to applicable laws and 43 | # regulations governing limitations on product liability. 44 | # 45 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | # PART OF THIS FILE AT ALL TIMES. 47 | 48 | # Input clock periods. These duplicate the values entered for the 49 | # input clocks. You can use these to time your system. If required 50 | # commented constraints can be used in the top level xdc 51 | #---------------------------------------------------------------- 52 | # Connect to input port when clock capable pin is selected for input 53 | create_clock -period 10.000 [get_ports clk_in1] 54 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100 55 | 56 | 57 | set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*] 58 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz.veo: -------------------------------------------------------------------------------- 1 | 2 | // (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of AMD and is protected under U.S. and international copyright 6 | // and other intellectual property laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // AMD, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) AMD shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or AMD had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // AMD products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of AMD products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | //---------------------------------------------------------------------------- 47 | // User entered comments 48 | //---------------------------------------------------------------------------- 49 | // None 50 | // 51 | //---------------------------------------------------------------------------- 52 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 53 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 54 | //---------------------------------------------------------------------------- 55 | // clk_out1__50.00000______0.000______50.0______151.636_____98.575 56 | // 57 | //---------------------------------------------------------------------------- 58 | // Input Clock Freq (MHz) Input Jitter (UI) 59 | //---------------------------------------------------------------------------- 60 | // __primary_________100.000____________0.010 61 | 62 | // The following must be inserted into your Verilog file for this 63 | // core to be instantiated. Change the instance name and port connections 64 | // (in parentheses) to your own signal names. 65 | 66 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 67 | 68 | clkgen_50mhz instance_name 69 | ( 70 | // Clock out ports 71 | .clk_out1(clk_out1), // output clk_out1 72 | // Clock in ports 73 | .clk_in1(clk_in1) // input clk_in1 74 | ); 75 | 76 | // INST_TAG_END ------ End INSTANTIATION Template --------- 77 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz.v: -------------------------------------------------------------------------------- 1 | 2 | // file: clkgen_50mhz.v 3 | // (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of AMD and is protected under U.S. and international copyright 7 | // and other intellectual property laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // AMD, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) AMD shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or AMD had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // AMD products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of AMD products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | //---------------------------------------------------------------------------- 48 | // User entered comments 49 | //---------------------------------------------------------------------------- 50 | // None 51 | // 52 | //---------------------------------------------------------------------------- 53 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 54 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 55 | //---------------------------------------------------------------------------- 56 | // clk_out1__50.00000______0.000______50.0______151.636_____98.575 57 | // 58 | //---------------------------------------------------------------------------- 59 | // Input Clock Freq (MHz) Input Jitter (UI) 60 | //---------------------------------------------------------------------------- 61 | // __primary_________100.000____________0.010 62 | 63 | `timescale 1ps/1ps 64 | 65 | (* CORE_GENERATION_INFO = "clkgen_50mhz,clk_wiz_v6_0_15_0_0,{component_name=clkgen_50mhz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 66 | 67 | module clkgen_50mhz 68 | ( 69 | // Clock out ports 70 | output clk_out1, 71 | // Clock in ports 72 | input clk_in1 73 | ); 74 | 75 | clkgen_50mhz_clk_wiz inst 76 | ( 77 | // Clock out ports 78 | .clk_out1(clk_out1), 79 | // Clock in ports 80 | .clk_in1(clk_in1) 81 | ); 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/verilator.f: -------------------------------------------------------------------------------- 1 | +define+ASSERTS_OFF 2 | +define+NO_MODPORT_EXPRESSIONS 3 | 4 | +incdir+../../../../common_cells/include 5 | ../../../../common_cells/src/cdc_2phase_clearable.sv 6 | ../../../../common_cells/src/cdc_4phase.sv 7 | ../../../../common_cells/src/cdc_reset_ctrlr_pkg.sv 8 | ../../../../common_cells/src/cdc_reset_ctrlr.sv 9 | ../../../../common_cells/src/deprecated/fifo_v2.sv 10 | ../../../../common_cells/src/fifo_v3.sv 11 | ../../../../common_cells/src/spill_register.sv 12 | ../../../../common_cells/src/spill_register_flushable.sv 13 | ../../../../common_cells/src/sync.sv 14 | 15 | ../../../../tech_cells_generic/src/rtl/tc_clk.sv 16 | 17 | +incdir+../../../../ibex/vendor/lowrisc_ip/ip/prim/rtl 18 | +incdir+../../../../ibex/vendor/lowrisc_ip/dv/sv/dv_utils 19 | ../../../../ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv 20 | ../../../../ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv 21 | ../../../../ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_cipher_pkg.sv 22 | ../../../../ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_count_pkg.sv 23 | ../../../../ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_util_pkg.sv 24 | ../../../../ibex/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi_pkg.sv 25 | ../../../../ibex/dv/uvm/core_ibex/common/prim/prim_pkg.sv 26 | ../../../../ibex/dv/uvm/core_ibex/common/prim/prim_clock_gating.sv 27 | ../../../../ibex/dv/uvm/core_ibex/common/prim/prim_buf.sv 28 | ../../../../ibex/dv/uvm/core_ibex/common/prim/prim_ram_1p.sv 29 | ../../../../ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv 30 | ../../../../ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv 31 | ../../../../ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1p.sv 32 | ../../../../ibex/rtl/ibex_pkg.sv 33 | ../../../../ibex/rtl/ibex_alu.sv 34 | ../../../../ibex/rtl/ibex_branch_predict.sv 35 | ../../../../ibex/rtl/ibex_compressed_decoder.sv 36 | ../../../../ibex/rtl/ibex_controller.sv 37 | ../../../../ibex/rtl/ibex_core.sv 38 | ../../../../ibex/rtl/ibex_counter.sv 39 | ../../../../ibex/rtl/ibex_cs_registers.sv 40 | ../../../../ibex/rtl/ibex_csr.sv 41 | ../../../../ibex/rtl/ibex_decoder.sv 42 | ../../../../ibex/rtl/ibex_dummy_instr.sv 43 | ../../../../ibex/rtl/ibex_ex_block.sv 44 | ../../../../ibex/rtl/ibex_fetch_fifo.sv 45 | ../../../../ibex/rtl/ibex_icache.sv 46 | ../../../../ibex/rtl/ibex_id_stage.sv 47 | ../../../../ibex/rtl/ibex_if_stage.sv 48 | ../../../../ibex/rtl/ibex_load_store_unit.sv 49 | ../../../../ibex/rtl/ibex_lockstep.sv 50 | ../../../../ibex/rtl/ibex_multdiv_fast.sv 51 | ../../../../ibex/rtl/ibex_multdiv_slow.sv 52 | ../../../../ibex/rtl/ibex_pmp.sv 53 | ../../../../ibex/rtl/ibex_prefetch_buffer.sv 54 | ../../../../ibex/rtl/ibex_register_file_ff.sv 55 | ../../../../ibex/rtl/ibex_register_file_fpga.sv 56 | ../../../../ibex/rtl/ibex_register_file_latch.sv 57 | ../../../../ibex/rtl/ibex_tracer_pkg.sv 58 | ../../../../ibex/rtl/ibex_tracer.sv 59 | ../../../../ibex/rtl/ibex_wb_stage.sv 60 | ../../../../ibex/rtl/ibex_top.sv 61 | ../../../../ibex/rtl/ibex_top_tracing.sv 62 | 63 | ../../../../riscv-dbg/src/dm_pkg.sv 64 | ../../../../riscv-dbg/src/dm_csrs.sv 65 | ../../../../riscv-dbg/src/dm_mem.sv 66 | ../../../../riscv-dbg/src/dm_obi_top.sv 67 | ../../../../riscv-dbg/src/dm_sba.sv 68 | ../../../../riscv-dbg/src/dm_top.sv 69 | ../../../../riscv-dbg/src/dmi_cdc.sv 70 | ../../../../riscv-dbg/src/dmi_intf.sv 71 | ../../../../riscv-dbg/src/dmi_bscane_tap.sv 72 | ../../../../riscv-dbg/src/dmi_jtag.sv 73 | ../../../../riscv-dbg/debug_rom/debug_rom_one_scratch.sv 74 | ../../../../riscv-dbg/debug_rom/debug_rom.sv 75 | 76 | ../../../../rtl/wb_pkg.sv 77 | ../../../../rtl/core_if.sv 78 | ../../../../rtl/core2wb.sv 79 | ../../../../rtl/wb2core.sv 80 | ../../../../rtl/wb_dm_top.sv 81 | ../../../../rtl/wb_if.sv 82 | ../../../../rtl/wb_ibex_top.sv 83 | 84 | ../../../../wb2axip/rtl/addrdecode.v 85 | ../../../../wb2axip/rtl/skidbuffer.v 86 | ../../../../wb2axip/rtl/wbxbar.v 87 | 88 | ../../../../soc/common/rtl/wb_interconnect_sharedbus.sv 89 | ../../../../soc/common/rtl/wb_interconnect_xbar.sv 90 | ../../../../soc/fpga/arty-a7-100/lib/verilog/clkgen_50mhz.sv 91 | ../../../../soc/fpga/arty-a7-100/lib/verilog/BSCANE2.sv 92 | ../../../../soc/fpga/arty-a7-100/rtl/crg.sv 93 | ../../../../soc/fpga/arty-a7-100/rtl/spramx32.sv 94 | ../../../../soc/fpga/arty-a7-100/rtl/sync_reset.sv 95 | ../../../../soc/fpga/arty-a7-100/rtl/wb_led.sv 96 | ../../../../soc/fpga/arty-a7-100/rtl/wb_spramx32.sv 97 | ../../../../soc/fpga/arty-a7-100/rtl/ibex_soc.sv 98 | -------------------------------------------------------------------------------- /soc/common/rtl/wb_interconnect_xbar.sv: -------------------------------------------------------------------------------- 1 | /* Wrapper around ZipCPU/wbxbar */ 2 | 3 | module wb_interconnect_xbar 4 | #(parameter numm = 3, // number of masters 5 | parameter nums = 3, // number of slaves 6 | parameter [31:0] base_addr[nums] = '{0}, // base addresses of slaves 7 | parameter [31:0] size[nums] = '{0}) // address size of slaves 8 | (wb_if.slave wbm[numm], // Wishbone master interfaces 9 | wb_if.master wbs[nums]); // Wishbone slave interfaces 10 | 11 | import wb_pkg::*; 12 | 13 | localparam aw = $bits(adr_t); 14 | localparam dw = $bits(dat_t); 15 | localparam sw = $bits(sel_t); 16 | 17 | localparam [nums-1:0][aw-1:0] slave_addr = {base_addr[2], base_addr[1], base_addr[0]}; 18 | //localparam [nums-1:0][aw-1:0] slave_mask = {32'hfffff000, 32'hffff0000, 32'hfffff000}; 19 | localparam [nums-1:0][aw-1:0] slave_mask = {~(size[2]-1), ~(size[1]-1), ~(size[0]-1)}; 20 | 21 | logic [numm-1:0] wbm_cyc; 22 | logic [numm-1:0] wbm_stb; 23 | logic [numm-1:0] wbm_we; 24 | logic [numm-1:0][aw-1:0] wbm_adr; 25 | logic [numm-1:0][sw-1:0] wbm_sel; 26 | 27 | logic [numm-1:0] wbm_stall; 28 | logic [numm-1:0] wbm_ack; 29 | logic [numm-1:0] wbm_err; 30 | 31 | `ifdef NO_MODPORT_EXPRESSIONS 32 | logic [numm-1:0][dw-1:0] wbm_dat_m, wbm_dat_s; 33 | `else 34 | logic [numm-1:0][dw-1:0] wbm_dat_i, wbm_dat_o; 35 | `endif 36 | 37 | logic [nums-1:0] wbs_cyc; 38 | logic [nums-1:0] wbs_stb; 39 | logic [nums-1:0] wbs_we; 40 | logic [nums-1:0][aw-1:0] wbs_adr; 41 | logic [nums-1:0][sw-1:0] wbs_sel; 42 | 43 | logic [nums-1:0] wbs_stall; 44 | logic [nums-1:0] wbs_ack; 45 | logic [nums-1:0] wbs_err; 46 | 47 | `ifdef NO_MODPORT_EXPRESSIONS 48 | logic [nums-1:0][dw-1:0] wbs_dat_s, wbs_dat_m; 49 | `else 50 | logic [nums-1:0][dw-1:0] wbs_dat_i, wbs_dat_o; 51 | `endif 52 | 53 | wbxbar 54 | #(.NM (numm), 55 | .NS (nums), 56 | .AW (aw), 57 | .DW (dw), 58 | .SLAVE_ADDR (slave_addr), 59 | .SLAVE_MASK (slave_mask)) 60 | u_wbxbar 61 | (.i_clk (wbm[0].clk), 62 | .i_reset (wbm[0].rst), 63 | 64 | .i_mcyc (wbm_cyc), 65 | .i_mstb (wbm_stb), 66 | .i_mwe (wbm_we), 67 | .i_maddr (wbm_adr), 68 | `ifdef NO_MODPORT_EXPRESSIONS 69 | .i_mdata (wbm_dat_m), 70 | `else 71 | .i_mdata (wbm_dat_i), 72 | `endif 73 | .i_msel (wbm_sel), 74 | 75 | .o_mstall (wbm_stall), 76 | .o_mack (wbm_ack), 77 | `ifdef NO_MODPORT_EXPRESSIONS 78 | .o_mdata (wbm_dat_s), 79 | `else 80 | .o_mdata (wbm_dat_o), 81 | `endif 82 | .o_merr (wbm_err), 83 | 84 | .o_scyc (wbs_cyc), 85 | .o_sstb (wbs_stb), 86 | .o_swe (wbs_we), 87 | .o_saddr (wbs_adr), 88 | `ifdef NO_MODPORT_EXPRESSIONS 89 | .o_sdata (wbs_dat_m), 90 | `else 91 | .o_sdata (wbs_dat_o), 92 | `endif 93 | .o_ssel (wbs_sel), 94 | 95 | .i_sstall (wbs_stall), 96 | .i_sack (wbs_ack), 97 | `ifdef NO_MODPORT_EXPRESSIONS 98 | .i_sdata (wbs_dat_s), 99 | `else 100 | .i_sdata (wbs_dat_i), 101 | `endif 102 | .i_serr (wbs_err)); 103 | 104 | for (genvar i = 0; i < numm; i++) begin 105 | assign 106 | wbm_cyc[i] = wbm[i].cyc, 107 | wbm_stb[i] = wbm[i].stb, 108 | wbm_we[i] = wbm[i].we, 109 | wbm_adr[i] = wbm[i].adr, 110 | wbm_sel[i] = wbm[i].sel, 111 | 112 | wbm[i].stall = wbm_stall[i], 113 | wbm[i].ack = wbm_ack[i], 114 | wbm[i].err = wbm_err[i]; 115 | 116 | `ifdef NO_MODPORT_EXPRESSIONS 117 | assign 118 | wbm_dat_m[i] = wbm[i].dat_m, 119 | wbm[i].dat_s = wbm_dat_s[i]; 120 | `else 121 | assign 122 | wbm_dat_i[i] = wbm[i].dat_i, 123 | wbm[i].dat_o = wbm_dat_o[i]; 124 | `endif 125 | end 126 | 127 | for (genvar i = 0; i < nums; i++) begin 128 | assign 129 | wbs[i].cyc = wbs_cyc[i], 130 | wbs[i].stb = wbs_stb[i], 131 | wbs[i].we = wbs_we[i], 132 | wbs[i].adr = wbs_adr[i], 133 | wbs[i].sel = wbs_sel[i], 134 | 135 | wbs_stall[i] = wbs[i].stall, 136 | wbs_ack[i] = wbs[i].ack, 137 | wbs_err[i] = wbs[i].err; 138 | 139 | `ifdef NO_MODPORT_EXPRESSIONS 140 | assign 141 | wbs[i].dat_m = wbs_dat_m[i], 142 | wbs_dat_s[i] = wbs[i].dat_s; 143 | `else 144 | assign 145 | wbs[i].dat_o = wbs_dat_o[i], 146 | wbs_dat_i[i] = wbs[i].dat_i; 147 | `endif 148 | end 149 | endmodule 150 | -------------------------------------------------------------------------------- /rtl/wb_dm_top.sv: -------------------------------------------------------------------------------- 1 | /* RISC-V debug module with Wishbone interface */ 2 | 3 | module wb_dm_top 4 | #(parameter int NrHarts = 1, 5 | parameter int BusWidth = 32, 6 | parameter int unsigned DmBaseAddress = 'h1000, // default to non-zero page 7 | parameter logic [NrHarts-1:0] SelectableHarts = 1, // Bitmask to select physically available harts for systems that don't use hart numbers in a contiguous fashion. 8 | parameter bit ReadByteEnable = 1) // toggle new behavior to drive master_be_o during a read 9 | (input logic clk, // clock 10 | input logic rst_n, // asynchronous reset active low, connect PoR here, not the system reset 11 | // Subsequent debug modules can be chained by setting the nextdm register value to the offset of 12 | // the next debug module. The RISC-V debug spec mandates that the first debug module located at 13 | // 0x0, and that the last debug module in the chain sets the nextdm register to 0x0. The nextdm 14 | // register is a word address and not a byte address. This value is passed in as a static signal 15 | // so that it becomes possible to assign this value with chiplet tie-offs or straps, if needed. 16 | input logic [31:0] next_dm_addr, 17 | input logic testmode, 18 | output logic ndmreset, // non-debug module reset 19 | input logic ndmreset_ack, // non-debug module reset acknowledgement pulse 20 | output logic dmactive, // debug module is active 21 | output logic [NrHarts-1:0] debug_req, // async debug request 22 | input logic [NrHarts-1:0] unavailable, // communicate whether the hart is unavailable (e.g.: power down) 23 | input dm::hartinfo_t [NrHarts-1:0] hartinfo, 24 | 25 | /* Wishbone interfaces */ 26 | wb_if.slave wbs, 27 | wb_if.master wbm, 28 | 29 | /* Connection to DTM - compatible to RocketChip Debug Module */ 30 | input logic dmi_rst_n, // Synchronous clear request from the DTM to clear the DMI response FIFO. 31 | input logic dmi_req_valid, 32 | output logic dmi_req_ready, 33 | input dm::dmi_req_t dmi_req, 34 | 35 | output logic dmi_resp_valid, 36 | input logic dmi_resp_ready, 37 | output dm::dmi_resp_t dmi_resp); 38 | 39 | core_if slave_core (.rst_n, .clk); 40 | core_if master_core (.rst_n, .clk); 41 | 42 | dm_top 43 | #(.NrHarts (NrHarts), 44 | .BusWidth(BusWidth), 45 | .SelectableHarts(SelectableHarts)) 46 | inst_dm_top 47 | (.clk_i (clk), 48 | .rst_ni (rst_n), 49 | .next_dm_addr_i (next_dm_addr), 50 | .testmode_i (testmode), 51 | .ndmreset_o (ndmreset), 52 | .ndmreset_ack_i (ndmreset_ack), 53 | .dmactive_o (dmactive), 54 | .debug_req_o (debug_req), 55 | .unavailable_i (unavailable), 56 | .hartinfo_i (hartinfo), 57 | 58 | .slave_req_i (slave_core.req), 59 | .slave_we_i (slave_core.we), 60 | .slave_addr_i (slave_core.addr), 61 | .slave_be_i (slave_core.be), 62 | .slave_wdata_i (slave_core.wdata), 63 | .slave_rdata_o (slave_core.rdata), 64 | 65 | .master_req_o (master_core.req), 66 | .master_add_o (master_core.addr), 67 | .master_we_o (master_core.we), 68 | .master_wdata_o (master_core.wdata), 69 | .master_be_o (master_core.be), 70 | .master_gnt_i (master_core.gnt), 71 | .master_r_valid_i (master_core.rvalid), 72 | .master_r_err_i (master_core.err), 73 | .master_r_other_err_i (1'b0), 74 | .master_r_rdata_i (master_core.rdata), 75 | 76 | .dmi_rst_ni (dmi_rst_n), 77 | .dmi_req_valid_i (dmi_req_valid), 78 | .dmi_req_ready_o (dmi_req_ready), 79 | .dmi_req_i (dmi_req), 80 | .dmi_resp_valid_o (dmi_resp_valid), 81 | .dmi_resp_ready_i (dmi_resp_ready), 82 | .dmi_resp_o (dmi_resp)); 83 | 84 | /* Wishbone */ 85 | assign slave_core.gnt = 1'b1; 86 | assign slave_core.rvalid = 1'b1; 87 | assign slave_core.err = 1'b0; 88 | 89 | wb2core u_wb2core 90 | (.core (slave_core), 91 | .wb (wbs)); 92 | 93 | core2wb u_core2wb 94 | (.core (master_core), 95 | .wb (wbm)); 96 | endmodule 97 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/crc_32/beebsc.c: -------------------------------------------------------------------------------- 1 | /* BEEBS local library variants 2 | 3 | Copyright (C) 2019 Embecosm Limited. 4 | 5 | Contributor Jeremy Bennett 6 | 7 | This file is part of Embench and was formerly part of the Bristol/Embecosm 8 | Embedded Benchmark Suite. 9 | 10 | SPDX-License-Identifier: GPL-3.0-or-later */ 11 | 12 | /* These are very simple local versions of library routines, to ensure the 13 | code is compiled with the flags used for the benchmark. Not all library 14 | routines are here, just ones that cause a lot of unecessary load, or where 15 | there is variation between platforms and architectures. */ 16 | 17 | #include 18 | #include 19 | #include "beebsc.h" 20 | 21 | /* Seed for the random number generator */ 22 | 23 | static long int seed = 0; 24 | 25 | /* Heap records and sane initial values */ 26 | 27 | static void *heap_ptr = NULL; 28 | static void *heap_end = NULL; 29 | static size_t heap_requested = 0; 30 | 31 | 32 | /* Yield a sequence of random numbers in the range [0, 2^15-1]. 33 | 34 | long int is guaranteed to be at least 32 bits. The seed only ever uses 31 35 | bits (so is positive). 36 | 37 | For BEEBS this gets round different operating systems using different 38 | multipliers and offsets and RAND_MAX variations. */ 39 | 40 | int 41 | rand_beebs (void) 42 | { 43 | seed = (seed * 1103515245L + 12345) & ((1UL << 31) - 1); 44 | return (int) (seed >> 16); 45 | } 46 | 47 | 48 | /* Initialize the random number generator */ 49 | 50 | void 51 | srand_beebs (unsigned int new_seed) 52 | { 53 | seed = (long int) new_seed; 54 | } 55 | 56 | 57 | /* Initialize the BEEBS heap pointers. Note that the actual memory block is 58 | in the caller code. */ 59 | 60 | void 61 | init_heap_beebs (void *heap, size_t heap_size) 62 | { 63 | heap_ptr = (void *) heap; 64 | heap_end = (void *) ((char *) heap_ptr + heap_size); 65 | heap_requested = 0; 66 | } 67 | 68 | 69 | /* Report if malloc ever failed. 70 | 71 | Return non-zero (TRUE) if malloc did not reqest more than was available 72 | since the last call to init_heap_beebs, zero (FALSE) otherwise. */ 73 | 74 | int 75 | check_heap_beebs (void *heap) 76 | { 77 | return ((void *) ((char *) heap + heap_requested) <= heap_end); 78 | } 79 | 80 | 81 | /* BEEBS version of malloc. 82 | 83 | This is primarily to reduce library and OS dependencies. Malloc is 84 | generally not used in embedded code, or if it is, only in well defined 85 | contexts to pre-allocate a fixed amount of memory. So this simplistic 86 | implementation is just fine. 87 | 88 | Note in particular the assumption that memory will never be freed! */ 89 | 90 | void * 91 | malloc_beebs (size_t size) 92 | { 93 | void *new_ptr = heap_ptr; 94 | 95 | heap_requested += size; 96 | 97 | if (((void *) ((char *) heap_ptr + size) > heap_end) || (0 == size)) 98 | return NULL; 99 | else 100 | { 101 | heap_ptr = (void *) ((char *) heap_ptr + size); 102 | return new_ptr; 103 | } 104 | } 105 | 106 | 107 | /* BEEBS version of calloc. 108 | 109 | Implement as wrapper for malloc */ 110 | 111 | void * 112 | calloc_beebs (size_t nmemb, size_t size) 113 | { 114 | void *new_ptr = malloc_beebs (nmemb * size); 115 | 116 | /* Calloc is defined to zero the memory. OK to use a function here, because 117 | it will be handled specially by the compiler anyway. */ 118 | 119 | if (NULL != new_ptr) 120 | memset (new_ptr, 0, nmemb * size); 121 | 122 | return new_ptr; 123 | } 124 | 125 | 126 | /* BEEBS version of realloc. 127 | 128 | This is primarily to reduce library and OS dependencies. We just have to 129 | allocate new memory and copy stuff across. */ 130 | 131 | void * 132 | realloc_beebs (void *ptr, size_t size) 133 | { 134 | void *new_ptr = heap_ptr; 135 | 136 | heap_requested += size; 137 | 138 | if (((void *) ((char *) heap_ptr + size) > heap_end) || (0 == size)) 139 | return NULL; 140 | else 141 | { 142 | heap_ptr = (void *) ((char *) heap_ptr + size); 143 | 144 | /* This is clunky, since we don't know the size of the original 145 | pointer. However it is a read only action and we know it must 146 | be big enough if we right off the end, or we couldn't have 147 | allocated here. If the size is smaller, it doesn't matter. */ 148 | 149 | if (NULL != ptr) 150 | { 151 | size_t i; 152 | 153 | for (i = 0; i < size; i++) 154 | ((char *) new_ptr)[i] = ((char *) ptr)[i]; 155 | } 156 | 157 | return new_ptr; 158 | } 159 | } 160 | 161 | 162 | /* BEEBS version of free. 163 | 164 | For our simplified version of memory handling, free can just do nothing. */ 165 | 166 | void 167 | free_beebs (void *ptr __attribute__ ((unused))) 168 | { 169 | } 170 | 171 | 172 | /* 173 | Local Variables: 174 | mode: C 175 | c-file-style: "gnu" 176 | End: 177 | */ 178 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/nettle-aes/beebsc.c: -------------------------------------------------------------------------------- 1 | /* BEEBS local library variants 2 | 3 | Copyright (C) 2019 Embecosm Limited. 4 | 5 | Contributor Jeremy Bennett 6 | 7 | This file is part of Embench and was formerly part of the Bristol/Embecosm 8 | Embedded Benchmark Suite. 9 | 10 | SPDX-License-Identifier: GPL-3.0-or-later */ 11 | 12 | /* These are very simple local versions of library routines, to ensure the 13 | code is compiled with the flags used for the benchmark. Not all library 14 | routines are here, just ones that cause a lot of unecessary load, or where 15 | there is variation between platforms and architectures. */ 16 | 17 | #include 18 | #include 19 | #include "beebsc.h" 20 | 21 | /* Seed for the random number generator */ 22 | 23 | static long int seed = 0; 24 | 25 | /* Heap records and sane initial values */ 26 | 27 | static void *heap_ptr = NULL; 28 | static void *heap_end = NULL; 29 | static size_t heap_requested = 0; 30 | 31 | 32 | /* Yield a sequence of random numbers in the range [0, 2^15-1]. 33 | 34 | long int is guaranteed to be at least 32 bits. The seed only ever uses 31 35 | bits (so is positive). 36 | 37 | For BEEBS this gets round different operating systems using different 38 | multipliers and offsets and RAND_MAX variations. */ 39 | 40 | int 41 | rand_beebs (void) 42 | { 43 | seed = (seed * 1103515245L + 12345) & ((1UL << 31) - 1); 44 | return (int) (seed >> 16); 45 | } 46 | 47 | 48 | /* Initialize the random number generator */ 49 | 50 | void 51 | srand_beebs (unsigned int new_seed) 52 | { 53 | seed = (long int) new_seed; 54 | } 55 | 56 | 57 | /* Initialize the BEEBS heap pointers. Note that the actual memory block is 58 | in the caller code. */ 59 | 60 | void 61 | init_heap_beebs (void *heap, size_t heap_size) 62 | { 63 | heap_ptr = (void *) heap; 64 | heap_end = (void *) ((char *) heap_ptr + heap_size); 65 | heap_requested = 0; 66 | } 67 | 68 | 69 | /* Report if malloc ever failed. 70 | 71 | Return non-zero (TRUE) if malloc did not reqest more than was available 72 | since the last call to init_heap_beebs, zero (FALSE) otherwise. */ 73 | 74 | int 75 | check_heap_beebs (void *heap) 76 | { 77 | return ((void *) ((char *) heap + heap_requested) <= heap_end); 78 | } 79 | 80 | 81 | /* BEEBS version of malloc. 82 | 83 | This is primarily to reduce library and OS dependencies. Malloc is 84 | generally not used in embedded code, or if it is, only in well defined 85 | contexts to pre-allocate a fixed amount of memory. So this simplistic 86 | implementation is just fine. 87 | 88 | Note in particular the assumption that memory will never be freed! */ 89 | 90 | void * 91 | malloc_beebs (size_t size) 92 | { 93 | void *new_ptr = heap_ptr; 94 | 95 | heap_requested += size; 96 | 97 | if (((void *) ((char *) heap_ptr + size) > heap_end) || (0 == size)) 98 | return NULL; 99 | else 100 | { 101 | heap_ptr = (void *) ((char *) heap_ptr + size); 102 | return new_ptr; 103 | } 104 | } 105 | 106 | 107 | /* BEEBS version of calloc. 108 | 109 | Implement as wrapper for malloc */ 110 | 111 | void * 112 | calloc_beebs (size_t nmemb, size_t size) 113 | { 114 | void *new_ptr = malloc_beebs (nmemb * size); 115 | 116 | /* Calloc is defined to zero the memory. OK to use a function here, because 117 | it will be handled specially by the compiler anyway. */ 118 | 119 | if (NULL != new_ptr) 120 | memset (new_ptr, 0, nmemb * size); 121 | 122 | return new_ptr; 123 | } 124 | 125 | 126 | /* BEEBS version of realloc. 127 | 128 | This is primarily to reduce library and OS dependencies. We just have to 129 | allocate new memory and copy stuff across. */ 130 | 131 | void * 132 | realloc_beebs (void *ptr, size_t size) 133 | { 134 | void *new_ptr = heap_ptr; 135 | 136 | heap_requested += size; 137 | 138 | if (((void *) ((char *) heap_ptr + size) > heap_end) || (0 == size)) 139 | return NULL; 140 | else 141 | { 142 | heap_ptr = (void *) ((char *) heap_ptr + size); 143 | 144 | /* This is clunky, since we don't know the size of the original 145 | pointer. However it is a read only action and we know it must 146 | be big enough if we right off the end, or we couldn't have 147 | allocated here. If the size is smaller, it doesn't matter. */ 148 | 149 | if (NULL != ptr) 150 | { 151 | size_t i; 152 | 153 | for (i = 0; i < size; i++) 154 | ((char *) new_ptr)[i] = ((char *) ptr)[i]; 155 | } 156 | 157 | return new_ptr; 158 | } 159 | } 160 | 161 | 162 | /* BEEBS version of free. 163 | 164 | For our simplified version of memory handling, free can just do nothing. */ 165 | 166 | void 167 | free_beebs (void *ptr __attribute__ ((unused))) 168 | { 169 | } 170 | 171 | 172 | /* 173 | Local Variables: 174 | mode: C 175 | c-file-style: "gnu" 176 | End: 177 | */ 178 | -------------------------------------------------------------------------------- /soc/common/sim/wb_checker.sv: -------------------------------------------------------------------------------- 1 | /* Classic pipelined Wishbone B4 protocol checker */ 2 | 3 | `default_nettype none 4 | 5 | module wb_checker (wb_if.monitor wb); 6 | import wb_pkg::*; 7 | 8 | localparam MAXWAITS = 16; // max. cycles after which ACK or ERR must be valid 9 | 10 | /************************************************************************ 11 | * Check if every bus signal is valid driven. 12 | ************************************************************************/ 13 | assert_driven 14 | #(.bw (1), 15 | .msg ("CYC must not be X or Z")) 16 | unkown_cyc 17 | (.clk (wb.clk), 18 | .reset_n (~wb.rst), 19 | .exp (wb.cyc)); 20 | 21 | assert_implication 22 | #(.msg ("STB must not be X or Z")) 23 | unkown_stb 24 | (.clk (wb.clk), 25 | .reset_n (~wb.rst), 26 | .antecedent_expr (wb.cyc), 27 | .consequent_expr (!$isunknown(wb.stb))); 28 | 29 | assert_implication 30 | #(.msg ("STALL must not be X or Z")) 31 | unkown_stall 32 | (.clk (wb.clk), 33 | .reset_n (~wb.rst), 34 | .antecedent_expr (wb.cyc), 35 | .consequent_expr (!$isunknown(wb.stall))); 36 | 37 | assert_implication 38 | #(.msg ("ACK must not be X or Z")) 39 | unkown_ack 40 | (.clk (wb.clk), 41 | .reset_n (~wb.rst), 42 | .antecedent_expr (wb.cyc), 43 | .consequent_expr (!$isunknown(wb.ack))); 44 | 45 | assert_implication 46 | #(.msg ("ERR must not be X or Z")) 47 | unkown_err 48 | (.clk (wb.clk), 49 | .reset_n (~wb.rst), 50 | .antecedent_expr (wb.cyc), 51 | .consequent_expr (!$isunknown(wb.err))); 52 | 53 | assert_implication 54 | #(.msg ("ADR must not be X or Z")) 55 | unkown_adr 56 | (.clk (wb.clk), 57 | .reset_n (~wb.rst), 58 | .antecedent_expr (wb.cyc && wb.stb), 59 | .consequent_expr (!$isunknown(wb.adr))); 60 | 61 | assert_implication 62 | #(.msg ("SEL must not be X or Z")) 63 | unkown_sel 64 | (.clk (wb.clk), 65 | .reset_n (~wb.rst), 66 | .antecedent_expr (wb.cyc && wb.stb), 67 | .consequent_expr (!$isunknown(wb.sel))); 68 | 69 | assert_implication 70 | #(.msg ("WE must not be X or Z")) 71 | unkown_we 72 | (.clk (wb.clk), 73 | .reset_n (~wb.rst), 74 | .antecedent_expr (wb.cyc && wb.stb), 75 | .consequent_expr (!$isunknown(wb.we))); 76 | 77 | /************************************************************************ 78 | * There must be exactly one ACK or ERR for each STB. 79 | ************************************************************************/ 80 | assert_req_ack_unique 81 | #(.min_time (1), 82 | .max_time (MAXWAITS), 83 | .max_time_log_2 ($clog2(MAXWAITS)), 84 | .msg ("ACK or ERR hast not been triggered after MAXWAITS cycles.")) 85 | handshake 86 | (.clk (wb.clk), 87 | .reset_n (~wb.rst), 88 | .req (wb.cyc && wb.stb && !wb.stall), 89 | .ack (wb.cyc && (wb.ack || wb.err))); 90 | 91 | /************************************************************************ 92 | * 3.3 BLOCK READ / WRITE Cycles 93 | ************************************************************************/ 94 | assert_window 95 | #(.msg ("CYC must not change during STALL")) 96 | unchange_stall_cyc 97 | (.clk (wb.clk), 98 | .reset_n (~wb.rst), 99 | .start_event (wb.cyc && wb.stb && wb.stall), 100 | .test_expr (wb.cyc), 101 | .end_event (!wb.stall)); 102 | 103 | assert_window 104 | #(.msg ("STB must not change during STALL")) 105 | unchange_stall_stb 106 | (.clk (wb.clk), 107 | .reset_n (~wb.rst), 108 | .start_event (wb.cyc && wb.stb && wb.stall), 109 | .test_expr (wb.stb), 110 | .end_event (!wb.stall)); 111 | 112 | assert_win_unchange 113 | #(.width ($bits(adr_t)), 114 | .msg ("ADR must not change during STALL")) 115 | unchange_stall_adr 116 | (.clk (wb.clk), 117 | .reset_n (~wb.rst), 118 | .start_event (wb.cyc && wb.stb && wb.stall), 119 | .test_expr (wb.adr), 120 | .end_event (!wb.stall)); 121 | 122 | assert_win_unchange 123 | #(.width ($bits(dat_t)), 124 | .msg ("Master DAT_O must not change during STALL")) 125 | unchange_stall_dat_m 126 | (.clk (wb.clk), 127 | .reset_n (~wb.rst), 128 | .start_event (wb.cyc && wb.stb && wb.we && wb.stall), 129 | .test_expr (wb.dat_m), 130 | .end_event (!wb.stall)); 131 | 132 | assert_win_unchange 133 | #(.width ($bits(sel_t)), 134 | .msg ("SEL must not change during STALL")) 135 | unchange_stall_sel 136 | (.clk (wb.clk), 137 | .reset_n (~wb.rst), 138 | .start_event (wb.cyc && wb.stb && wb.we && wb.stall), 139 | .test_expr (wb.sel), 140 | .end_event (!wb.stall)); 141 | endmodule 142 | 143 | `resetall 144 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/common/wb_checker.sv: -------------------------------------------------------------------------------- 1 | /* Classic pipelined Wishbone B4 protocol checker */ 2 | 3 | `default_nettype none 4 | 5 | module wb_checker (wb_if.monitor wb); 6 | import wb_pkg::*; 7 | 8 | localparam MAXWAITS = 16; // max. cycles after which ACK or ERR must be valid 9 | 10 | /************************************************************************ 11 | * Check if every bus signal is valid driven. 12 | ************************************************************************/ 13 | assert_driven 14 | #(.bw (1), 15 | .msg ("CYC must not be X or Z")) 16 | unkown_cyc 17 | (.clk (wb.clk), 18 | .reset_n (~wb.rst), 19 | .exp (wb.cyc)); 20 | 21 | assert_implication 22 | #(.msg ("STB must not be X or Z")) 23 | unkown_stb 24 | (.clk (wb.clk), 25 | .reset_n (~wb.rst), 26 | .antecedent_expr (wb.cyc), 27 | .consequent_expr (!$isunknown(wb.stb))); 28 | 29 | assert_implication 30 | #(.msg ("STALL must not be X or Z")) 31 | unkown_stall 32 | (.clk (wb.clk), 33 | .reset_n (~wb.rst), 34 | .antecedent_expr (wb.cyc), 35 | .consequent_expr (!$isunknown(wb.stall))); 36 | 37 | assert_implication 38 | #(.msg ("ACK must not be X or Z")) 39 | unkown_ack 40 | (.clk (wb.clk), 41 | .reset_n (~wb.rst), 42 | .antecedent_expr (wb.cyc), 43 | .consequent_expr (!$isunknown(wb.ack))); 44 | 45 | assert_implication 46 | #(.msg ("ERR must not be X or Z")) 47 | unkown_err 48 | (.clk (wb.clk), 49 | .reset_n (~wb.rst), 50 | .antecedent_expr (wb.cyc), 51 | .consequent_expr (!$isunknown(wb.err))); 52 | 53 | assert_implication 54 | #(.msg ("ADR must not be X or Z")) 55 | unkown_adr 56 | (.clk (wb.clk), 57 | .reset_n (~wb.rst), 58 | .antecedent_expr (wb.cyc && wb.stb), 59 | .consequent_expr (!$isunknown(wb.adr))); 60 | 61 | assert_implication 62 | #(.msg ("SEL must not be X or Z")) 63 | unkown_sel 64 | (.clk (wb.clk), 65 | .reset_n (~wb.rst), 66 | .antecedent_expr (wb.cyc && wb.stb), 67 | .consequent_expr (!$isunknown(wb.sel))); 68 | 69 | assert_implication 70 | #(.msg ("WE must not be X or Z")) 71 | unkown_we 72 | (.clk (wb.clk), 73 | .reset_n (~wb.rst), 74 | .antecedent_expr (wb.cyc && wb.stb), 75 | .consequent_expr (!$isunknown(wb.we))); 76 | 77 | /************************************************************************ 78 | * There must be exactly one ACK or ERR for each STB. 79 | ************************************************************************/ 80 | assert_req_ack_unique 81 | #(.min_time (1), 82 | .max_time (MAXWAITS), 83 | .max_time_log_2 ($clog2(MAXWAITS)), 84 | .msg ("ACK or ERR hast not been triggered after MAXWAITS cycles.")) 85 | handshake 86 | (.clk (wb.clk), 87 | .reset_n (~wb.rst), 88 | .req (wb.cyc && wb.stb && !wb.stall), 89 | .ack (wb.cyc && (wb.ack || wb.err))); 90 | 91 | /************************************************************************ 92 | * 3.3 BLOCK READ / WRITE Cycles 93 | ************************************************************************/ 94 | assert_window 95 | #(.msg ("CYC must not change during STALL")) 96 | unchange_stall_cyc 97 | (.clk (wb.clk), 98 | .reset_n (~wb.rst), 99 | .start_event (wb.cyc && wb.stb && wb.stall), 100 | .test_expr (wb.cyc), 101 | .end_event (!wb.stall)); 102 | 103 | assert_window 104 | #(.msg ("STB must not change during STALL")) 105 | unchange_stall_stb 106 | (.clk (wb.clk), 107 | .reset_n (~wb.rst), 108 | .start_event (wb.cyc && wb.stb && wb.stall), 109 | .test_expr (wb.stb), 110 | .end_event (!wb.stall)); 111 | 112 | assert_win_unchange 113 | #(.width ($bits(adr_t)), 114 | .msg ("ADR must not change during STALL")) 115 | unchange_stall_adr 116 | (.clk (wb.clk), 117 | .reset_n (~wb.rst), 118 | .start_event (wb.cyc && wb.stb && wb.stall), 119 | .test_expr (wb.adr), 120 | .end_event (!wb.stall)); 121 | 122 | assert_win_unchange 123 | #(.width ($bits(dat_t)), 124 | .msg ("Master DAT_O must not change during STALL")) 125 | unchange_stall_dat_m 126 | (.clk (wb.clk), 127 | .reset_n (~wb.rst), 128 | .start_event (wb.cyc && wb.stb && wb.we && wb.stall), 129 | .test_expr (wb.dat_m), 130 | .end_event (!wb.stall)); 131 | 132 | assert_win_unchange 133 | #(.width ($bits(sel_t)), 134 | .msg ("SEL must not change during STALL")) 135 | unchange_stall_sel 136 | (.clk (wb.clk), 137 | .reset_n (~wb.rst), 138 | .start_event (wb.cyc && wb.stb && wb.we && wb.stall), 139 | .test_expr (wb.sel), 140 | .end_event (!wb.stall)); 141 | endmodule 142 | 143 | `resetall 144 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/crc_32/crc_32.c.vmem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00000013 00000013 00000013 00000013 3 | 00000013 00000013 00000013 00000013 4 | 00000013 00000013 00000013 00000013 5 | 00000013 00000013 00000013 00000013 6 | 00000013 00000013 00000013 00000013 7 | 00000013 00000013 00000013 00000013 8 | 00000013 00000013 00000013 00000013 9 | 00000013 00000013 00000013 1860006F 10 | 1860006F 17E0006F 17A0006F 11 | @00000023 12 | C4221141 C04AC226 0493C606 547D4000 13 | 37C00913 8D2120A5 0FF57513 954A050A 14 | 8021411C 8C3D14FD 4513F4F5 40B2FFF4 15 | 44924422 01414902 11418082 C226C422 16 | 84AAC606 4A634401 40B20094 95134422 17 | 44920117 01418145 45018082 374D2091 18 | 040587AA 8082B7CD 4505BFC9 77F5B7F9 19 | 35778793 3513953E 80820015 78800713 20 | 57B74308 879341C6 0533E6D7 678D02F5 21 | 03978793 0506953E C3088105 80828141 22 | 78A02423 95AA8082 78A02223 78B02023 23 | 76002E23 07938082 439C77C0 0793953E 24 | 439C7800 00A7B533 00154513 07138082 25 | 431877C0 78400793 972A439C 76E02E23 26 | 78000693 87334294 E76300A7 C50900E6 27 | 78E02223 8082853E BFED4781 02B50633 28 | CC221101 8532CE06 37D1C632 C501842A 29 | 45814632 852228C1 446240F2 80826105 30 | 77C00713 07934318 439C7840 2E23972E 31 | 069376E0 42947800 00B78733 02E6E463 32 | 2223C195 CD0978E0 06B34701 C60300E5 33 | 86B30006 070500E7 00C68023 FEE597E3 34 | 8082853E BFED4781 45018082 45018082 35 | 45018082 006F8082 00930000 81060000 36 | 82068186 83068286 84068386 85068486 37 | 86068586 87068686 88068786 89068886 38 | 8A068986 8B068A86 8C068B86 8D068C86 39 | 8E068D86 8F068E86 01178F86 01130001 40 | 0D13DBA1 0D9377C0 576378C0 202301BD 41 | 0D11000D FFADDDE3 00000513 00000593 42 | 0E0000EF 00F00313 00050713 02C37E63 43 | 00F77793 0A079063 08059263 FF067693 44 | 00F67613 00E686B3 00B72023 00B72223 45 | 00B72423 00B72623 01070713 FED766E3 46 | 00061463 00008067 40C306B3 00269693 47 | 00000297 005686B3 00C68067 00B70723 48 | 00B706A3 00B70623 00B705A3 00B70523 49 | 00B704A3 00B70423 00B703A3 00B70323 50 | 00B702A3 00B70223 00B701A3 00B70123 51 | 00B700A3 00B70023 00008067 0FF5F593 52 | 00859693 00D5E5B3 01059693 00D5E5B3 53 | F6DFF06F 00279693 00000297 005686B3 54 | 00008293 FA0680E7 00028093 FF078793 55 | 40F70733 00F60633 F6C378E3 F3DFF06F 56 | CE061101 3345355D 3B794501 3B71354D 57 | 3545C42A 3B614522 0073C62A BFF51050 58 | 00000000 00000000 00000000 00000000 59 | @000000DF 60 | 00000000 77073096 EE0E612C 990951BA 61 | 076DC419 706AF48F E963A535 9E6495A3 62 | 0EDB8832 79DCB8A4 E0D5E91E 97D2D988 63 | 09B64C2B 7EB17CBD E7B82D07 90BF1D91 64 | 1DB71064 6AB020F2 F3B97148 84BE41DE 65 | 1ADAD47D 6DDDE4EB F4D4B551 83D385C7 66 | 136C9856 646BA8C0 FD62F97A 8A65C9EC 67 | 14015C4F 63066CD9 FA0F3D63 8D080DF5 68 | 3B6E20C8 4C69105E D56041E4 A2677172 69 | 3C03E4D1 4B04D447 D20D85FD A50AB56B 70 | 35B5A8FA 42B2986C DBBBC9D6 ACBCF940 71 | 32D86CE3 45DF5C75 DCD60DCF ABD13D59 72 | 26D930AC 51DE003A C8D75180 BFD06116 73 | 21B4F4B5 56B3C423 CFBA9599 B8BDA50F 74 | 2802B89E 5F058808 C60CD9B2 B10BE924 75 | 2F6F7C87 58684C11 C1611DAB B6662D3D 76 | 76DC4190 01DB7106 98D220BC EFD5102A 77 | 71B18589 06B6B51F 9FBFE4A5 E8B8D433 78 | 7807C9A2 0F00F934 9609A88E E10E9818 79 | 7F6A0DBB 086D3D2D 91646C97 E6635C01 80 | 6B6B51F4 1C6C6162 856530D8 F262004E 81 | 6C0695ED 1B01A57B 8208F4C1 F50FC457 82 | 65B0D9C6 12B7E950 8BBEB8EA FCB9887C 83 | 62DD1DDF 15DA2D49 8CD37CF3 FBD44C65 84 | 4DB26158 3AB551CE A3BC0074 D4BB30E2 85 | 4ADFA541 3DD895D7 A4D1C46D D3D6F4FB 86 | 4369E96A 346ED9FC AD678846 DA60B8D0 87 | 44042D73 33031DE5 AA0A4C5F DD0D7CC9 88 | 5005713C 270241AA BE0B1010 C90C2086 89 | 5768B525 206F85B3 B966D409 CE61E49F 90 | 5EDEF90E 29D9C998 B0D09822 C7D7A8B4 91 | 59B33D17 2EB40D81 B7BD5C3B C0BA6CAD 92 | EDB88320 9ABFB3B6 03B6E20C 74B1D29A 93 | EAD54739 9DD277AF 04DB2615 73DC1683 94 | E3630B12 94643B84 0D6D6A3E 7A6A5AA8 95 | E40ECF0B 9309FF9D 0A00AE27 7D079EB1 96 | F00F9344 8708A3D2 1E01F268 6906C2FE 97 | F762575D 806567CB 196C3671 6E6B06E7 98 | FED41B76 89D32BE0 10DA7A5A 67DD4ACC 99 | F9B9DF6F 8EBEEFF9 17B7BE43 60B08ED5 100 | D6D6A3E8 A1D1937E 38D8C2C4 4FDFF252 101 | D1BB67F1 A6BC5767 3FB506DD 48B2364B 102 | D80D2BDA AF0A1B4C 36034AF6 41047A60 103 | DF60EFC3 A867DF55 316E8EEF 4669BE79 104 | CB61B38C BC66831A 256FD2A0 5268E236 105 | CC0C7795 BB0B4703 220216B9 5505262F 106 | C5BA3BBE B2BD0B28 2BB45A92 5CB36A04 107 | C2D7FFA7 B5D0CF31 2CD99E8B 5BDEAE1D 108 | 9B64C2B0 EC63F226 756AA39C 026D930A 109 | 9C0906A9 EB0E363F 72076785 05005713 110 | 95BF4A82 E2B87A14 7BB12BAE 0CB61B38 111 | 92D28E9B E5D5BE0D 7CDCEFB7 0BDBDF21 112 | 86D3D2D4 F1D4E242 68DDB3F8 1FDA836E 113 | 81BE16CD F6B9265B 6FB077E1 18B74777 114 | 88085AE6 FF0F6A70 66063BCA 11010B5C 115 | 8F659EFF F862AE69 616BFFD3 166CCF45 116 | A00AE278 D70DD2EE 4E048354 3903B3C2 117 | A7672661 D06016F7 4969474D 3E6E77DB 118 | AED16A4A D9D65ADC 40DF0B66 37D83BF0 119 | A9BCAE53 DEBB9EC5 47B2CF7F 30B5FFE9 120 | BDBDF21C CABAC28A 53B39330 24B4A3A6 121 | BAD03605 CDD70693 54DE5729 23D967BF 122 | B3667A2E C4614AB8 5D681B02 2A6F2B94 123 | B40BBE37 C30C8EA1 5A05DF1B 2D02EF8D 124 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/rtl/ibex_soc.sv: -------------------------------------------------------------------------------- 1 | /* SoC Toplevel */ 2 | 3 | module ibex_soc 4 | #(parameter bit WBInterconnet = 1'b1, // 0:shared, 1:crossbar 5 | parameter bit ICache = 1'b1) // 0:prefetch buffer, 1:instruction cache 6 | (input wire clk100mhz, 7 | input wire ck_rst_n, 8 | 9 | input logic [3:0] sw, 10 | output logic [3:0] led, 11 | input logic [3:0] btn 12 | `ifndef SYNTHESIS 13 | , 14 | input logic tck, 15 | input logic trst_n, 16 | input logic tms, 17 | input logic tdi, 18 | output wire tdo 19 | `endif 20 | ); 21 | 22 | import ibex_pkg::*; 23 | 24 | localparam [31:0] ram_base_addr = 'h00000000; 25 | localparam [31:0] ram_size = 'h10000; 26 | 27 | localparam [31:0] led_base_addr = 'h10000000; 28 | localparam [31:0] led_size = 'h1000; 29 | 30 | localparam [31:0] dm_base_addr = 'h1A110000; 31 | localparam [31:0] dm_size = 'h1000; 32 | 33 | logic clk; 34 | logic rst, rst_n; 35 | 36 | logic debug_req; 37 | dm::hartinfo_t hartinfo = '{zero1: 0, 38 | nscratch: 2, // Debug module needs at least two scratch regs 39 | zero0: 0, 40 | dataaccess: 1, // data registers are memory mapped in the debugger 41 | datasize: dm::DataCount, 42 | dataaddr: dm::DataAddr}; 43 | logic dmi_rst_n; 44 | logic dmi_req_valid; 45 | logic dmi_req_ready; 46 | dm::dmi_req_t dmi_req; 47 | logic dmi_resp_valid; 48 | logic dmi_resp_ready; 49 | dm::dmi_resp_t dmi_resp; 50 | 51 | assign rst = ~rst_n; 52 | 53 | `ifndef SYNTHESIS 54 | logic tdo_o; 55 | logic tdo_oe; 56 | 57 | assign tdo = tdo_oe ? tdo_o : 1'bz; 58 | `else 59 | logic tck = 1'b0; 60 | logic tms = 1'b1; 61 | logic trst_n = 1'b1; 62 | logic tdi = 1'b0; 63 | logic tdo_o; 64 | logic tdo_oe; 65 | `endif 66 | 67 | wb_if wbm[3] (.rst, .clk); 68 | wb_if wbs[3] (.rst, .clk); 69 | 70 | crg u_crg 71 | (.clk100m (clk100mhz), 72 | .ext_rst_n (ck_rst_n), 73 | .rst_n, 74 | .clk); 75 | 76 | wb_ibex_top 77 | #(.RegFile (RegFileFPGA), 78 | .ICache (ICache)) 79 | u_wb_ibex_top 80 | (.clk, 81 | .rst_n, 82 | .instr_wb (wbm[2]), 83 | .data_wb (wbm[1]), 84 | 85 | .test_en (1'b0), 86 | .ram_cfg ('0), 87 | 88 | .hart_id (32'h00000000), 89 | .boot_addr (32'h00000000), 90 | 91 | .irq_software (1'b0), 92 | .irq_timer (1'b0), 93 | .irq_external (1'b0), 94 | .irq_fast (15'h0000), 95 | .irq_nm (1'b0), 96 | 97 | .scramble_key_valid (1'b0), 98 | .scramble_key ('0), 99 | .scramble_nonce ('0), 100 | .scramble_req (), 101 | 102 | .debug_req, 103 | .crash_dump (), 104 | .double_fault_seen (), 105 | 106 | .fetch_enable ('1), 107 | .alert_minor (), 108 | .alert_major_internal (), 109 | .alert_major_bus (), 110 | .core_sleep (), 111 | 112 | .scan_rst_n (1'b0)); 113 | 114 | wb_dm_top u_dm_top 115 | (.clk, 116 | .rst_n, 117 | 118 | .next_dm_addr (32'h00000000), 119 | .testmode (1'b0), 120 | .ndmreset (), 121 | .ndmreset_ack (1'b0), 122 | .dmactive (), 123 | .debug_req, 124 | .unavailable ('0), 125 | .hartinfo, 126 | 127 | .wbs (wbs[0]), 128 | .wbm (wbm[0]), 129 | 130 | .dmi_rst_n, 131 | .dmi_req_valid, 132 | .dmi_req_ready, 133 | .dmi_req, 134 | 135 | .dmi_resp_valid, 136 | .dmi_resp_ready, 137 | .dmi_resp); 138 | 139 | dmi_jtag u_dmi_jtag 140 | (.clk_i (clk), 141 | .rst_ni (rst_n), 142 | .testmode_i (1'b0), 143 | 144 | .dmi_rst_no (dmi_rst_n), 145 | .dmi_req_o (dmi_req), 146 | .dmi_req_valid_o (dmi_req_valid), 147 | .dmi_req_ready_i (dmi_req_ready), 148 | 149 | .dmi_resp_i (dmi_resp), 150 | .dmi_resp_ready_o (dmi_resp_ready), 151 | .dmi_resp_valid_i (dmi_resp_valid), 152 | 153 | .tck_i (tck), 154 | .tms_i (tms), 155 | .trst_ni (trst_n), 156 | .td_i (tdi), 157 | .td_o (tdo_o), 158 | .tdo_oe_o (tdo_oe)); 159 | 160 | if (WBInterconnet) 161 | wb_interconnect_xbar 162 | #(.numm (3), 163 | .nums (3), 164 | .base_addr ('{dm_base_addr, ram_base_addr, led_base_addr}), 165 | .size ('{dm_size, ram_size, led_size})) 166 | u_wb_interconnect 167 | (.wbm, .wbs); 168 | else 169 | wb_interconnect_sharedbus 170 | #(.numm (3), 171 | .nums (3), 172 | .base_addr ('{dm_base_addr, ram_base_addr, led_base_addr}), 173 | .size ('{dm_size, ram_size, led_size})) 174 | u_wb_interconnect 175 | (.wbm, .wbs); 176 | 177 | wb_spramx32 #(ram_size) u_spram(.wb(wbs[1])); 178 | 179 | wb_led 180 | #(.N (4)) 181 | u_ledg 182 | (.wb (wbs[2]), .led); 183 | endmodule 184 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/debugger/tasks.svh: -------------------------------------------------------------------------------- 1 | task jtag_test_logic_reset(); 2 | tms = 1'b1; 3 | repeat(5) @(negedge tck); 4 | endtask 5 | 6 | task jtag_run_test_idle(input int unsigned n = 1); 7 | tms = 1'b0; 8 | repeat (n) @(negedge tck); 9 | endtask 10 | 11 | task jtag_ir(input ir_t x, output [4:0] resp); 12 | static const bit [1:4] tms1 = 4'b1100; 13 | static const bit [1:2] tms2 = 2'b10; 14 | 15 | foreach(tms1[i]) 16 | begin 17 | tms <= tms1[i]; 18 | @(negedge tck); 19 | end 20 | 21 | for(int i = 0; i < $bits(x); i++) 22 | begin 23 | if(i < $bits(x) - 1) 24 | tms <= 1'b0; 25 | else 26 | tms <= 1'b1; 27 | 28 | tdi <= x[i]; 29 | 30 | @(posedge tck) resp[i] <= tdo; 31 | @(negedge tck); 32 | end 33 | 34 | foreach(tms2[i]) 35 | begin 36 | tms <= tms2[i]; 37 | @(negedge tck); 38 | end 39 | 40 | chk_ir_resp: assert (resp[1:0] == 2'b01); 41 | endtask 42 | 43 | task jtag_dr_idcode (input [31:0] x = '0, output [31:0] resp); 44 | static const bit [1:3] tms1 = 3'b100; 45 | static const bit [1:2] tms2 = 2'b10; 46 | 47 | foreach(tms1[i]) 48 | begin 49 | tms <= tms1[i]; 50 | @(negedge tck); 51 | end 52 | 53 | for(int i = 0; i < $bits(x); i++) 54 | begin 55 | if(i < $bits(x) - 1) 56 | tms <= 1'b0; 57 | else 58 | tms <= 1'b1; 59 | 60 | tdi <= x[i]; 61 | 62 | @(posedge tck) resp[i] <= tdo; 63 | @(negedge tck); 64 | end 65 | 66 | foreach(tms2[i]) 67 | begin 68 | tms <= tms2[i]; 69 | @(negedge tck); 70 | end 71 | endtask 72 | 73 | task jtag_dr_dtmcs (input dtmcs_t x = '0, output dtmcs_t resp); 74 | static const bit [1:3] tms1 = 3'b100; 75 | static const bit [1:2] tms2 = 2'b10; 76 | 77 | foreach(tms1[i]) 78 | begin 79 | tms <= tms1[i]; 80 | @(negedge tck); 81 | end 82 | 83 | for(int i = 0; i < $bits(x); i++) 84 | begin 85 | if(i < $bits(x) - 1) 86 | tms <= 1'b0; 87 | else 88 | tms <= 1'b1; 89 | 90 | tdi <= x[i]; 91 | 92 | @(posedge tck) resp[i] <= tdo; 93 | @(negedge tck); 94 | end 95 | 96 | foreach(tms2[i]) 97 | begin 98 | tms <= tms2[i]; 99 | @(negedge tck); 100 | end 101 | endtask 102 | 103 | task jtag_dr_dmi (input dmi_req_t x = '0, output dmi_resp_t resp); 104 | static const bit [1:3] tms1 = 3'b100; 105 | static const bit [1:2] tms2 = 2'b10; 106 | 107 | jtag_run_test_idle(4); // adjust for CPU clock 108 | 109 | foreach(tms1[i]) 110 | begin 111 | tms <= tms1[i]; 112 | @(negedge tck); 113 | end 114 | 115 | for(int i = 0; i < $bits(x); i++) 116 | begin 117 | if(i < $bits(x) - 1) 118 | tms <= 1'b0; 119 | else 120 | tms <= 1'b1; 121 | 122 | tdi <= x[i]; 123 | 124 | @(posedge tck) resp[i] <= tdo; 125 | @(negedge tck); 126 | end 127 | 128 | foreach(tms2[i]) 129 | begin 130 | tms <= tms2[i]; 131 | @(negedge tck); 132 | end 133 | 134 | chk_dmi_resp: assert (resp.resp == 2'd0); 135 | endtask 136 | 137 | task ac_read_register (input bit [15:0] regno, output [31:0] data); 138 | var dm::ac_ar_cmd_t ac_ar_cmd; 139 | var dm::command_t command; 140 | 141 | ac_ar_cmd = '{transfer: 1'b1, write: 1'b0, regno: regno, default: '0}; 142 | command.cmdtype = dm::AccessRegister; 143 | command.control = ac_ar_cmd; 144 | 145 | dmi_req.addr = dm::Command; 146 | dmi_req.op = dm::DTM_WRITE; 147 | dmi_req.data = command; 148 | jtag_dr_dmi(dmi_req, dmi_resp); 149 | 150 | dmi_req.addr = dm::Data0; 151 | dmi_req.op = dm::DTM_READ; 152 | dmi_req.data = '0; 153 | jtag_dr_dmi(dmi_req, dmi_resp); 154 | 155 | dmi_req = '0; 156 | jtag_dr_dmi(dmi_req, dmi_resp); 157 | data = dmi_resp.data; 158 | endtask 159 | 160 | task ac_write_register (input bit [15:0] regno, input [31:0] data); 161 | var dm::ac_ar_cmd_t ac_ar_cmd; 162 | var dm::command_t command; 163 | 164 | ac_ar_cmd = '{transfer: 1'b1, write: 1'b1, regno: regno, default: '0}; 165 | command.cmdtype = dm::AccessRegister; 166 | command.control = ac_ar_cmd; 167 | 168 | dmi_req.addr = dm::Command; 169 | dmi_req.op = dm::DTM_WRITE; 170 | dmi_req.data = command; 171 | jtag_dr_dmi(dmi_req, dmi_resp); 172 | 173 | dmi_req.addr = dm::Data0; 174 | dmi_req.op = dm::DTM_WRITE; 175 | dmi_req.data = data; 176 | jtag_dr_dmi(dmi_req, dmi_resp); 177 | endtask 178 | 179 | task sb_read_memory32 (input bit [31:0] addr, output [31:0] sbdata); 180 | var dm::sbcs_t sbcs; 181 | 182 | sbcs = '{sbreadonaddr: 1'b1, sbaccess: 2, default: '0}; 183 | dmi_req.addr = dm::SBCS; 184 | dmi_req.op = dm::DTM_WRITE; 185 | dmi_req.data = sbcs; 186 | jtag_dr_dmi(dmi_req, dmi_resp); 187 | 188 | dmi_req.addr = dm::SBAddress0; 189 | dmi_req.op = dm::DTM_WRITE; 190 | dmi_req.data = addr; 191 | jtag_dr_dmi(dmi_req, dmi_resp); 192 | 193 | dmi_req.addr = dm::SBData0; 194 | dmi_req.op = dm::DTM_READ; 195 | dmi_req.data = '0; 196 | jtag_dr_dmi(dmi_req, dmi_resp); 197 | 198 | dmi_req = '0; 199 | jtag_dr_dmi(dmi_req, dmi_resp); 200 | sbdata = dmi_resp.data; 201 | endtask 202 | 203 | task sb_write_memory32 (input bit [31:0] addr, input [31:0] sbdata); 204 | var dm::sbcs_t sbcs; 205 | 206 | sbcs = '{sbaccess: 2, default: '0}; 207 | dmi_req.addr = dm::SBCS; 208 | dmi_req.op = dm::DTM_WRITE; 209 | dmi_req.data = sbcs; 210 | jtag_dr_dmi(dmi_req, dmi_resp); 211 | 212 | dmi_req.addr = dm::SBAddress0; 213 | dmi_req.op = dm::DTM_WRITE; 214 | dmi_req.data = addr; 215 | jtag_dr_dmi(dmi_req, dmi_resp); 216 | 217 | dmi_req.addr = dm::SBData0; 218 | dmi_req.op = dm::DTM_WRITE; 219 | dmi_req.data = sbdata; 220 | jtag_dr_dmi(dmi_req, dmi_resp); 221 | endtask 222 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ibex_wb 2 | [RISC-V Ibex](https://ibex-core.readthedocs.io/en/latest/index.html) core with Wishbone B4 interface. 3 | 4 | ## Design 5 | The instruction and data memory interfaces are converted to Wishbone. 6 | 7 | ## Status 8 | - simulated with Verilator 9 | - implemented in Vivado 10 | - programmed on FPGA board 11 | - use debugger via BSCANE2 12 | 13 | To be done: 14 | - use debugger via JTAG 15 | 16 | ## Linting with Verilator 17 | ```shell 18 | cd soc/fpga/arty-a7-100/lint 19 | ./lint.sh 20 | ``` 21 | 22 | ## Simulation with Verilator 23 | ```shell 24 | cd soc/fpga/arty-a7-100/sim 25 | ./use.sh ../sw/nettle-aes/nettle-aes.vmem 26 | ./build.sh 27 | ./sim.sh 28 | less trace_core_00000000.log 29 | gtkwave dump.fst 30 | ``` 31 | 32 | ## Openocd 33 | ### Via BSCANE2 34 | Start `openocd` 35 | ```shell 36 | arty-a7-100/util% openocd -f arty-a7-openocd-cfg.tcl 37 | Open On-Chip Debugger 0.12.0 38 | Licensed under GNU GPL v2 39 | For bug reports, read 40 | http://openocd.org/doc/doxygen/bugs.html 41 | force hard breakpoints 42 | Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi tdo_sample_edge falling" 43 | Info : clock speed 10000 kHz 44 | Info : JTAG tap: riscv.cpu tap/device found: 0x13631093 (mfg: 0x049 (Xilinx), part: 0x3631, ver: 0x1) 45 | Info : datacount=2 progbufsize=8 46 | Info : Examined RISC-V core; found 1 harts 47 | Info : hart 0: XLEN=32, misa=0x40101104 48 | Info : starting gdb server for riscv.cpu on 3333 49 | Info : Listening on port 3333 for gdb connections 50 | Info : Listening on port 6666 for tcl connections 51 | Info : Listening on port 4444 for telnet connections 52 | ``` 53 | 54 | ## Debugging with GDB 55 | ```shell 56 | sw/led% riscv32-unknown-elf-gdb -ex "target extended-remote localhost:3333" 57 | GNU gdb (crosstool-NG 1.26.0_rc1) 13.2 58 | Copyright (C) 2023 Free Software Foundation, Inc. 59 | License GPLv3+: GNU GPL version 3 or later 60 | This is free software: you are free to change and redistribute it. 61 | There is NO WARRANTY, to the extent permitted by law. 62 | Type "show copying" and "show warranty" for details. 63 | This GDB was configured as "--host=x86_64-build_pc-linux-gnu --target=riscv32-unknown-elf". 64 | Type "show configuration" for configuration details. 65 | For bug reporting instructions, please see: 66 | . 67 | Find the GDB manual and other documentation resources online at: 68 | . 69 | 70 | For help, type "help". 71 | Type "apropos word" to search for commands related to "word"... 72 | Reading symbols from led.elf... 73 | Remote debugging using localhost:3333 74 | ``` 75 | 76 | ## Ibex memory control vs. Wishbone bus 77 | 78 | ### Basic Memory Transaction 79 |

80 | 81 | ### Back-to-back Memory Transaction 82 |

83 | 84 | ### Slow Response Memory Transaction 85 |

86 | 87 | ### Interconnect with Shared Bus 88 | The shared bus interconnect has the lowest latency but long combinational paths. 89 | This can lead to a decrease of the maximum clock frequency. 90 | 91 | An instruction cache does not improve the performance by a large amount. 92 | 93 | #### Timing without ICACHE 94 | | Program | Cycles | Instructions | CPI | 95 | |------------|--------|----------------|------| 96 | | crc_32 | 35032 | 23689 | 1.48 | 97 | | nettle-aes | 93902 | 64380 | 1.46 | 98 | | geom. mean | | | 1.47 | 99 | 100 | #### Timing with ICACHE 101 | | Program | Cycles | Instructions | CPI | 102 | |------------|--------|----------------|------| 103 | | crc_32 | 35044 | 23689 | 1.48 | 104 | | nettle-aes | 87829 | 64380 | 1.36 | 105 | | geom. mean | | | 1.42 | 106 | 107 | ### Interconnect with Crossbar 108 | The [crossbar](https://zipcpu.com/blog/2019/07/17/crossbar.html) interconnect uses skid buffers. 109 | Therefor the latency has been increased. 110 | 111 | The optional [instruction cache](https://ibex-core.readthedocs.io/en/latest/03_reference/icache.html) 112 | is designed to improve CPU performance in systems with high instruction memory latency. 113 | The instruction cache integrates into the 114 | CPU by replacing the prefetch buffer, interfacing directly between the bus and IF stage. 115 | 116 | #### Timing without ICACHE 117 | | Program | Cycles | Instructions | CPI | 118 | |------------|--------|----------------|------| 119 | | crc_32 | 71124 | 23689 | 3.00 | 120 | | nettle-aes | 219912 | 64380 | 3.42 | 121 | | geom. mean | | | 3.20 | 122 | 123 | #### Timing with ICACHE 124 | | Program | Cycles | Instructions | CPI | 125 | |------------|--------|----------------|------| 126 | | crc_32 | 44478 | 23689 | 1.88 | 127 | | nettle-aes | 134913 | 64380 | 2.10 | 128 | | geom. mean | | | 1.98 | 129 | 130 | ## FPGA Implementation 131 | [Arty A7-100T](https://digilent.com/shop/arty-a7-100t-artix-7-fpga-development-board/) 132 | 133 | Two variants were implemented. The clock for the SOC was 50 MHz. 134 | 135 | | WB Interconnect | Icache | LUT | Registers | 136 | |-----------------|--------|------|-----------| 137 | | Shared | no | 3938 | 1987 | 138 | | Crossbar | yes | 5115 | 2848 | 139 | 140 | ## Recources 141 | - [Wishbone at opencores.org](https://opencores.org/howto/wishbone) 142 | - [ZipCPU](http://zipcpu.com/zipcpu/2017/11/07/wb-formal.html) for a deeper understanding of the pipelined mode. 143 | - [WB2AXIP: Bus interconnects, bridges, and other components](https://github.com/ZipCPU/wb2axip/) 144 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/crc_32/crc_32.vmem: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00000013 00000013 00000013 00000013 3 | 00000013 00000013 00000013 00000013 4 | 00000013 00000013 00000013 00000013 5 | 00000013 00000013 00000013 00000013 6 | 00000013 00000013 00000013 00000013 7 | 00000013 00000013 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00000797 33 | 72078793 0007A783 00A7B533 00154513 34 | 00008067 00000717 70470713 00072703 35 | 00000797 70078793 0007A783 00A70733 36 | 00000697 6EE6A423 00000697 6E468693 37 | 0006A683 00A78733 00E6EC63 00050A63 38 | 00000697 6CE6A823 00078513 00008067 39 | 00000793 FF5FF06F 02B50633 FE010113 40 | 00812C23 00112E23 00060513 00C12623 41 | F95FF0EF 00050413 00050863 00C12603 42 | 00000593 15C000EF 00040513 01C12083 43 | 01812403 02010113 00008067 00000717 44 | 66C70713 00072703 00000797 66878793 45 | 0007A783 00B70733 00000697 64E6A823 46 | 00000697 64C68693 0006A683 00B78733 47 | 02E6EC63 02058A63 00000697 62E6AC23 48 | 02050063 00000713 00E506B3 0006C603 49 | 00E786B3 00170713 00C68023 FEE596E3 50 | 00078513 00008067 00000793 FF5FF06F 51 | 00008067 00000513 00008067 00000513 52 | 00008067 00000513 00008067 0000006F 53 | 00000093 00008113 00008193 00008213 54 | 00008293 00008313 00008393 00008413 55 | 00008493 00008513 00008593 00008613 56 | 00008693 00008713 00008793 00008813 57 | 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FFDFF06F 00000000 00000000 82 | 00000000 00000000 83 | @0000013D 84 | 00000000 77073096 EE0E612C 990951BA 85 | 076DC419 706AF48F E963A535 9E6495A3 86 | 0EDB8832 79DCB8A4 E0D5E91E 97D2D988 87 | 09B64C2B 7EB17CBD E7B82D07 90BF1D91 88 | 1DB71064 6AB020F2 F3B97148 84BE41DE 89 | 1ADAD47D 6DDDE4EB F4D4B551 83D385C7 90 | 136C9856 646BA8C0 FD62F97A 8A65C9EC 91 | 14015C4F 63066CD9 FA0F3D63 8D080DF5 92 | 3B6E20C8 4C69105E D56041E4 A2677172 93 | 3C03E4D1 4B04D447 D20D85FD A50AB56B 94 | 35B5A8FA 42B2986C DBBBC9D6 ACBCF940 95 | 32D86CE3 45DF5C75 DCD60DCF ABD13D59 96 | 26D930AC 51DE003A C8D75180 BFD06116 97 | 21B4F4B5 56B3C423 CFBA9599 B8BDA50F 98 | 2802B89E 5F058808 C60CD9B2 B10BE924 99 | 2F6F7C87 58684C11 C1611DAB B6662D3D 100 | 76DC4190 01DB7106 98D220BC EFD5102A 101 | 71B18589 06B6B51F 9FBFE4A5 E8B8D433 102 | 7807C9A2 0F00F934 9609A88E E10E9818 103 | 7F6A0DBB 086D3D2D 91646C97 E6635C01 104 | 6B6B51F4 1C6C6162 856530D8 F262004E 105 | 6C0695ED 1B01A57B 8208F4C1 F50FC457 106 | 65B0D9C6 12B7E950 8BBEB8EA FCB9887C 107 | 62DD1DDF 15DA2D49 8CD37CF3 FBD44C65 108 | 4DB26158 3AB551CE A3BC0074 D4BB30E2 109 | 4ADFA541 3DD895D7 A4D1C46D D3D6F4FB 110 | 4369E96A 346ED9FC AD678846 DA60B8D0 111 | 44042D73 33031DE5 AA0A4C5F DD0D7CC9 112 | 5005713C 270241AA BE0B1010 C90C2086 113 | 5768B525 206F85B3 B966D409 CE61E49F 114 | 5EDEF90E 29D9C998 B0D09822 C7D7A8B4 115 | 59B33D17 2EB40D81 B7BD5C3B C0BA6CAD 116 | EDB88320 9ABFB3B6 03B6E20C 74B1D29A 117 | EAD54739 9DD277AF 04DB2615 73DC1683 118 | E3630B12 94643B84 0D6D6A3E 7A6A5AA8 119 | E40ECF0B 9309FF9D 0A00AE27 7D079EB1 120 | F00F9344 8708A3D2 1E01F268 6906C2FE 121 | F762575D 806567CB 196C3671 6E6B06E7 122 | FED41B76 89D32BE0 10DA7A5A 67DD4ACC 123 | F9B9DF6F 8EBEEFF9 17B7BE43 60B08ED5 124 | D6D6A3E8 A1D1937E 38D8C2C4 4FDFF252 125 | D1BB67F1 A6BC5767 3FB506DD 48B2364B 126 | D80D2BDA AF0A1B4C 36034AF6 41047A60 127 | DF60EFC3 A867DF55 316E8EEF 4669BE79 128 | CB61B38C BC66831A 256FD2A0 5268E236 129 | CC0C7795 BB0B4703 220216B9 5505262F 130 | C5BA3BBE B2BD0B28 2BB45A92 5CB36A04 131 | C2D7FFA7 B5D0CF31 2CD99E8B 5BDEAE1D 132 | 9B64C2B0 EC63F226 756AA39C 026D930A 133 | 9C0906A9 EB0E363F 72076785 05005713 134 | 95BF4A82 E2B87A14 7BB12BAE 0CB61B38 135 | 92D28E9B E5D5BE0D 7CDCEFB7 0BDBDF21 136 | 86D3D2D4 F1D4E242 68DDB3F8 1FDA836E 137 | 81BE16CD F6B9265B 6FB077E1 18B74777 138 | 88085AE6 FF0F6A70 66063BCA 11010B5C 139 | 8F659EFF F862AE69 616BFFD3 166CCF45 140 | A00AE278 D70DD2EE 4E048354 3903B3C2 141 | A7672661 D06016F7 4969474D 3E6E77DB 142 | AED16A4A D9D65ADC 40DF0B66 37D83BF0 143 | A9BCAE53 DEBB9EC5 47B2CF7F 30B5FFE9 144 | BDBDF21C CABAC28A 53B39330 24B4A3A6 145 | BAD03605 CDD70693 54DE5729 23D967BF 146 | B3667A2E C4614AB8 5D681B02 2A6F2B94 147 | B40BBE37 C30C8EA1 5A05DF1B 2D02EF8D 148 | -------------------------------------------------------------------------------- /soc/common/rtl/wb_interconnect_sharedbus.sv: -------------------------------------------------------------------------------- 1 | /* Wishbone interconnect (classic pipelined) 2 | * 3 | * Wishbone B4, section 8.10 "Shared Bus Example" 4 | */ 5 | 6 | module wb_interconnect_sharedbus 7 | #(parameter numm = 3, // number of masters 8 | parameter nums = 3, // number of slaves 9 | parameter [31:0] base_addr[nums] = '{0}, // base addresses of slaves 10 | parameter [31:0] size[nums] = '{0}) // address size of slaves 11 | (wb_if.slave wbm[numm], // Wishbone master interfaces 12 | wb_if.master wbs[nums]); // Wishbone slave interfaces 13 | logic cyc, stb, we, ack, err, stall; 14 | logic [31:0] adr; 15 | logic [3:0] sel; 16 | logic [31:0] dat_wr, dat_rd; 17 | logic [numm-1:0] gnt, gnt1; 18 | logic [nums-1:0] ss, ss1; 19 | 20 | /******************************************************************************** 21 | * Use packed types because of this VCS error message: 22 | * 23 | * Error-[SV-TCF] Type checking failed 24 | * Reason of type check failure : Only constant index is supported here. 25 | ********************************************************************************/ 26 | logic [numm-1:0] wbm_cyc, wbm_stb, wbm_we, wbm_ack, wbm_err, wbm_stall; 27 | logic [numm-1:0][31:0] wbm_adr; 28 | logic [numm-1:0][3:0] wbm_sel; 29 | 30 | `ifdef NO_MODPORT_EXPRESSIONS 31 | logic [numm-1:0][31:0] wbm_dat_m, wbm_dat_s; 32 | `else 33 | logic [numm-1:0][31:0] wbm_dat_i, wbm_dat_o; 34 | `endif 35 | 36 | for (genvar i = 0; i < numm; i++) begin 37 | assign 38 | wbm_cyc[i] = wbm[i].cyc, 39 | wbm_stb[i] = wbm[i].stb, 40 | wbm_we[i] = wbm[i].we, 41 | wbm[i].ack = wbm_ack[i], 42 | wbm[i].err = wbm_err[i], 43 | wbm[i].stall = wbm_stall[i], 44 | wbm_adr[i] = wbm[i].adr, 45 | wbm_sel[i] = wbm[i].sel; 46 | 47 | assign 48 | `ifdef NO_MODPORT_EXPRESSIONS 49 | wbm_dat_m[i] = wbm[i].dat_m, 50 | wbm[i].dat_s = wbm_dat_s[i]; 51 | `else 52 | wbm_dat_i[i] = wbm[i].dat_i, 53 | wbm[i].dat_o = wbm_dat_o[i]; 54 | `endif 55 | end 56 | 57 | logic [nums-1:0] wbs_cyc, wbs_stb, wbs_we, wbs_ack, wbs_err, wbs_stall; 58 | logic [nums-1:0][31:0] wbs_adr; 59 | logic [nums-1:0][3:0] wbs_sel; 60 | `ifdef NO_MODPORT_EXPRESSIONS 61 | logic [nums-1:0][31:0] wbs_dat_s, wbs_dat_m; 62 | `else 63 | logic [nums-1:0][31:0] wbs_dat_i, wbs_dat_o; 64 | `endif 65 | 66 | for (genvar i = 0; i < nums; i++) begin 67 | assign 68 | wbs[i].cyc = wbs_cyc[i], 69 | wbs[i].stb = wbs_stb[i], 70 | wbs[i].we = wbs_we[i], 71 | wbs_ack[i] = wbs[i].ack, 72 | wbs_err[i] = wbs[i].err, 73 | wbs_stall[i] = wbs[i].stall, 74 | wbs[i].adr = wbs_adr[i], 75 | wbs[i].sel = wbs_sel[i]; 76 | 77 | assign 78 | `ifdef NO_MODPORT_EXPRESSIONS 79 | wbs[i].dat_m = wbs_dat_m[i], 80 | wbs_dat_s[i] = wbs[i].dat_s; 81 | `else 82 | wbs[i].dat_o = wbs_dat_o[i], 83 | wbs_dat_i[i] = wbs[i].dat_i; 84 | `endif 85 | end 86 | 87 | /********************************************************************************/ 88 | 89 | /* slave address select */ 90 | always_comb 91 | for (int i = 0; i < nums; i++) 92 | ss[i] = (adr >= base_addr[i]) && (adr < base_addr[i] + size[i]); 93 | 94 | /* Assume, that the response is exactly on cycle after request. */ 95 | always_ff @(posedge wbs[0].clk or posedge wbs[0].rst) 96 | if (wbs[0].rst) 97 | ss1 <= '0; 98 | else 99 | if (cyc && stb) 100 | ss1 <= ss; 101 | 102 | /* priority arbiter */ 103 | always_comb begin 104 | gnt = '0; 105 | for (int i = 0; i < numm; i++) 106 | if (wbm_cyc[i]) begin 107 | gnt[i] = 1'b1; 108 | break; 109 | end 110 | end 111 | 112 | /* Assume, that the response is exactly on cycle after request. */ 113 | always_ff @(posedge wbm[0].clk or posedge wbm[0].rst) 114 | if (wbm[0].rst) 115 | gnt1 <= '0; 116 | else 117 | if (cyc && stb) 118 | gnt1 <= gnt; 119 | 120 | /* shared bus signals */ 121 | always_comb begin 122 | cyc = 1'b0; 123 | adr = '0; 124 | stb = 1'b0; 125 | we = 1'b0; 126 | sel = '0; 127 | dat_wr = '0; 128 | for (int i = 0; i < numm; i++) begin 129 | cyc |= wbm_cyc[i]; 130 | if (gnt[i]) begin 131 | adr = wbm_adr[i]; 132 | stb = wbm_stb[i]; 133 | we = wbm_we[i]; 134 | sel = wbm_sel[i]; 135 | `ifdef NO_MODPORT_EXPRESSIONS 136 | dat_wr = wbm_dat_m[i]; 137 | `else 138 | dat_wr = wbm_dat_i[i]; 139 | `endif 140 | end 141 | end 142 | end 143 | 144 | always_comb begin 145 | ack = 1'b0; 146 | err = 1'b0; 147 | stall = 1'b0; 148 | dat_rd = '0; 149 | for (int i = 0; i < nums; i++) begin 150 | ack |= wbs_ack[i]; 151 | err |= wbs_err[i]; 152 | stall |= wbs_stall[i]; 153 | if (ss1[i]) 154 | `ifdef NO_MODPORT_EXPRESSIONS 155 | dat_rd = wbs_dat_s[i]; 156 | `else 157 | dat_rd = wbs_dat_i[i]; 158 | `endif 159 | end 160 | end 161 | 162 | /* interconnect */ 163 | 164 | /* STALL must respond immediately. */ 165 | always_comb begin 166 | for (int i = 0; i < numm; i++) begin 167 | wbm_stall[i] = 1'b1; 168 | if (gnt[i]) 169 | wbm_stall[i] = stall; 170 | end 171 | end 172 | 173 | /* Response signals are one cycle delayed. */ 174 | always_comb begin 175 | for (int i = 0; i < numm; i++) begin 176 | wbm_ack[i] = 1'b0; 177 | wbm_err[i] = 1'b0; 178 | `ifdef NO_MODPORT_EXPRESSIONS 179 | wbm_dat_s[i] = '0; 180 | `else 181 | wbm_dat_o[i] = '0; 182 | `endif 183 | if (gnt1[i]) begin 184 | wbm_ack[i] = ack; 185 | wbm_err[i] = err; 186 | `ifdef NO_MODPORT_EXPRESSIONS 187 | wbm_dat_s[i] = dat_rd; 188 | `else 189 | wbm_dat_o[i] = dat_rd; 190 | `endif 191 | end 192 | end 193 | end 194 | 195 | always_comb 196 | for (int i = 0; i < nums; i++) begin 197 | wbs_cyc[i] = cyc; 198 | wbs_adr[i] = '0; 199 | wbs_stb[i] = 1'b0; 200 | wbs_we[i] = we; 201 | wbs_sel[i] = '0; 202 | `ifdef NO_MODPORT_EXPRESSIONS 203 | wbs_dat_m[i] = '0; 204 | `else 205 | wbs_dat_o[i] = '0; 206 | `endif 207 | if (ss[i]) begin 208 | wbs_adr[i] = adr; 209 | wbs_stb[i] = cyc & stb; 210 | wbs_sel[i] = sel; 211 | `ifdef NO_MODPORT_EXPRESSIONS 212 | wbs_dat_m[i] = dat_wr; 213 | `else 214 | wbs_dat_o[i] = dat_wr; 215 | `endif 216 | end 217 | end 218 | endmodule 219 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz_clk_wiz.v: -------------------------------------------------------------------------------- 1 | 2 | // file: clkgen_50mhz.v 3 | // (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of AMD and is protected under U.S. and international copyright 7 | // and other intellectual property laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // AMD, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) AMD shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or AMD had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // AMD products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of AMD products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | //---------------------------------------------------------------------------- 48 | // User entered comments 49 | //---------------------------------------------------------------------------- 50 | // None 51 | // 52 | //---------------------------------------------------------------------------- 53 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 54 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 55 | //---------------------------------------------------------------------------- 56 | // clk_out1__50.00000______0.000______50.0______151.636_____98.575 57 | // 58 | //---------------------------------------------------------------------------- 59 | // Input Clock Freq (MHz) Input Jitter (UI) 60 | //---------------------------------------------------------------------------- 61 | // __primary_________100.000____________0.010 62 | 63 | `timescale 1ps/1ps 64 | 65 | module clkgen_50mhz_clk_wiz 66 | 67 | (// Clock in ports 68 | // Clock out ports 69 | output clk_out1, 70 | input clk_in1 71 | ); 72 | // Input buffering 73 | //------------------------------------ 74 | wire clk_in1_clkgen_50mhz; 75 | wire clk_in2_clkgen_50mhz; 76 | IBUF clkin1_ibufg 77 | (.O (clk_in1_clkgen_50mhz), 78 | .I (clk_in1)); 79 | 80 | 81 | 82 | 83 | // Clocking PRIMITIVE 84 | //------------------------------------ 85 | 86 | // Instantiation of the MMCM PRIMITIVE 87 | // * Unused inputs are tied off 88 | // * Unused outputs are labeled unused 89 | 90 | wire clk_out1_clkgen_50mhz; 91 | wire clk_out2_clkgen_50mhz; 92 | wire clk_out3_clkgen_50mhz; 93 | wire clk_out4_clkgen_50mhz; 94 | wire clk_out5_clkgen_50mhz; 95 | wire clk_out6_clkgen_50mhz; 96 | wire clk_out7_clkgen_50mhz; 97 | 98 | wire [15:0] do_unused; 99 | wire drdy_unused; 100 | wire psdone_unused; 101 | wire locked_int; 102 | wire clkfbout_clkgen_50mhz; 103 | wire clkfbout_buf_clkgen_50mhz; 104 | wire clkfboutb_unused; 105 | wire clkout0b_unused; 106 | wire clkout1_unused; 107 | wire clkout1b_unused; 108 | wire clkout2_unused; 109 | wire clkout2b_unused; 110 | wire clkout3_unused; 111 | wire clkout3b_unused; 112 | wire clkout4_unused; 113 | wire clkout5_unused; 114 | wire clkout6_unused; 115 | wire clkfbstopped_unused; 116 | wire clkinstopped_unused; 117 | 118 | MMCME2_ADV 119 | #(.BANDWIDTH ("OPTIMIZED"), 120 | .CLKOUT4_CASCADE ("FALSE"), 121 | .COMPENSATION ("ZHOLD"), 122 | .STARTUP_WAIT ("FALSE"), 123 | .DIVCLK_DIVIDE (1), 124 | .CLKFBOUT_MULT_F (10.000), 125 | .CLKFBOUT_PHASE (0.000), 126 | .CLKFBOUT_USE_FINE_PS ("FALSE"), 127 | .CLKOUT0_DIVIDE_F (20.000), 128 | .CLKOUT0_PHASE (0.000), 129 | .CLKOUT0_DUTY_CYCLE (0.500), 130 | .CLKOUT0_USE_FINE_PS ("FALSE"), 131 | .CLKIN1_PERIOD (10.000)) 132 | mmcm_adv_inst 133 | // Output clocks 134 | ( 135 | .CLKFBOUT (clkfbout_clkgen_50mhz), 136 | .CLKFBOUTB (clkfboutb_unused), 137 | .CLKOUT0 (clk_out1_clkgen_50mhz), 138 | .CLKOUT0B (clkout0b_unused), 139 | .CLKOUT1 (clkout1_unused), 140 | .CLKOUT1B (clkout1b_unused), 141 | .CLKOUT2 (clkout2_unused), 142 | .CLKOUT2B (clkout2b_unused), 143 | .CLKOUT3 (clkout3_unused), 144 | .CLKOUT3B (clkout3b_unused), 145 | .CLKOUT4 (clkout4_unused), 146 | .CLKOUT5 (clkout5_unused), 147 | .CLKOUT6 (clkout6_unused), 148 | // Input clock control 149 | .CLKFBIN (clkfbout_buf_clkgen_50mhz), 150 | .CLKIN1 (clk_in1_clkgen_50mhz), 151 | .CLKIN2 (1'b0), 152 | // Tied to always select the primary input clock 153 | .CLKINSEL (1'b1), 154 | // Ports for dynamic reconfiguration 155 | .DADDR (7'h0), 156 | .DCLK (1'b0), 157 | .DEN (1'b0), 158 | .DI (16'h0), 159 | .DO (do_unused), 160 | .DRDY (drdy_unused), 161 | .DWE (1'b0), 162 | // Ports for dynamic phase shift 163 | .PSCLK (1'b0), 164 | .PSEN (1'b0), 165 | .PSINCDEC (1'b0), 166 | .PSDONE (psdone_unused), 167 | // Other control and status signals 168 | .LOCKED (locked_int), 169 | .CLKINSTOPPED (clkinstopped_unused), 170 | .CLKFBSTOPPED (clkfbstopped_unused), 171 | .PWRDWN (1'b0), 172 | .RST (1'b0)); 173 | 174 | // Clock Monitor clock assigning 175 | //-------------------------------------- 176 | // Output buffering 177 | //----------------------------------- 178 | 179 | BUFG clkf_buf 180 | (.O (clkfbout_buf_clkgen_50mhz), 181 | .I (clkfbout_clkgen_50mhz)); 182 | 183 | 184 | 185 | 186 | 187 | 188 | BUFG clkout1_buf 189 | (.O (clk_out1), 190 | .I (clk_out1_clkgen_50mhz)); 191 | 192 | 193 | 194 | 195 | endmodule 196 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz_sim_netlist.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | -- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | -- -------------------------------------------------------------------------------- 4 | -- Tool Version: Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024 5 | -- Date : Sun Apr 13 12:16:12 2025 6 | -- Host : Bender running 64-bit Ubuntu 24.04.2 LTS 7 | -- Command : write_vhdl -force -mode funcsim 8 | -- /home/bernd/Projects/github.com/pbing/ibex_wb/soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz_sim_netlist.vhdl 9 | -- Design : clkgen_50mhz 10 | -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or 11 | -- synthesized. This netlist cannot be used for SDF annotated simulation. 12 | -- Device : xc7a100tcsg324-1 13 | -- -------------------------------------------------------------------------------- 14 | library IEEE; 15 | use IEEE.STD_LOGIC_1164.ALL; 16 | library UNISIM; 17 | use UNISIM.VCOMPONENTS.ALL; 18 | entity clkgen_50mhz_clk_wiz is 19 | port ( 20 | clk_out1 : out STD_LOGIC; 21 | clk_in1 : in STD_LOGIC 22 | ); 23 | end clkgen_50mhz_clk_wiz; 24 | 25 | architecture STRUCTURE of clkgen_50mhz_clk_wiz is 26 | signal clk_in1_clkgen_50mhz : STD_LOGIC; 27 | signal clk_out1_clkgen_50mhz : STD_LOGIC; 28 | signal clkfbout_buf_clkgen_50mhz : STD_LOGIC; 29 | signal clkfbout_clkgen_50mhz : STD_LOGIC; 30 | signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; 31 | signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; 32 | signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; 33 | signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; 34 | signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; 35 | signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; 36 | signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; 37 | signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; 38 | signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; 39 | signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; 40 | signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; 41 | signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; 42 | signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; 43 | signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; 44 | signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC; 45 | signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; 46 | signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); 47 | attribute BOX_TYPE : string; 48 | attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; 49 | attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; 50 | attribute CAPACITANCE : string; 51 | attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; 52 | attribute IBUF_DELAY_VALUE : string; 53 | attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; 54 | attribute IFD_DELAY_VALUE : string; 55 | attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; 56 | attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; 57 | attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; 58 | begin 59 | clkf_buf: unisim.vcomponents.BUFG 60 | port map ( 61 | I => clkfbout_clkgen_50mhz, 62 | O => clkfbout_buf_clkgen_50mhz 63 | ); 64 | clkin1_ibufg: unisim.vcomponents.IBUF 65 | generic map( 66 | IOSTANDARD => "DEFAULT" 67 | ) 68 | port map ( 69 | I => clk_in1, 70 | O => clk_in1_clkgen_50mhz 71 | ); 72 | clkout1_buf: unisim.vcomponents.BUFG 73 | port map ( 74 | I => clk_out1_clkgen_50mhz, 75 | O => clk_out1 76 | ); 77 | mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV 78 | generic map( 79 | BANDWIDTH => "OPTIMIZED", 80 | CLKFBOUT_MULT_F => 10.000000, 81 | CLKFBOUT_PHASE => 0.000000, 82 | CLKFBOUT_USE_FINE_PS => false, 83 | CLKIN1_PERIOD => 10.000000, 84 | CLKIN2_PERIOD => 0.000000, 85 | CLKOUT0_DIVIDE_F => 20.000000, 86 | CLKOUT0_DUTY_CYCLE => 0.500000, 87 | CLKOUT0_PHASE => 0.000000, 88 | CLKOUT0_USE_FINE_PS => false, 89 | CLKOUT1_DIVIDE => 1, 90 | CLKOUT1_DUTY_CYCLE => 0.500000, 91 | CLKOUT1_PHASE => 0.000000, 92 | CLKOUT1_USE_FINE_PS => false, 93 | CLKOUT2_DIVIDE => 1, 94 | CLKOUT2_DUTY_CYCLE => 0.500000, 95 | CLKOUT2_PHASE => 0.000000, 96 | CLKOUT2_USE_FINE_PS => false, 97 | CLKOUT3_DIVIDE => 1, 98 | CLKOUT3_DUTY_CYCLE => 0.500000, 99 | CLKOUT3_PHASE => 0.000000, 100 | CLKOUT3_USE_FINE_PS => false, 101 | CLKOUT4_CASCADE => false, 102 | CLKOUT4_DIVIDE => 1, 103 | CLKOUT4_DUTY_CYCLE => 0.500000, 104 | CLKOUT4_PHASE => 0.000000, 105 | CLKOUT4_USE_FINE_PS => false, 106 | CLKOUT5_DIVIDE => 1, 107 | CLKOUT5_DUTY_CYCLE => 0.500000, 108 | CLKOUT5_PHASE => 0.000000, 109 | CLKOUT5_USE_FINE_PS => false, 110 | CLKOUT6_DIVIDE => 1, 111 | CLKOUT6_DUTY_CYCLE => 0.500000, 112 | CLKOUT6_PHASE => 0.000000, 113 | CLKOUT6_USE_FINE_PS => false, 114 | COMPENSATION => "ZHOLD", 115 | DIVCLK_DIVIDE => 1, 116 | IS_CLKINSEL_INVERTED => '0', 117 | IS_PSEN_INVERTED => '0', 118 | IS_PSINCDEC_INVERTED => '0', 119 | IS_PWRDWN_INVERTED => '0', 120 | IS_RST_INVERTED => '0', 121 | REF_JITTER1 => 0.010000, 122 | REF_JITTER2 => 0.010000, 123 | SS_EN => "FALSE", 124 | SS_MODE => "CENTER_HIGH", 125 | SS_MOD_PERIOD => 10000, 126 | STARTUP_WAIT => false 127 | ) 128 | port map ( 129 | CLKFBIN => clkfbout_buf_clkgen_50mhz, 130 | CLKFBOUT => clkfbout_clkgen_50mhz, 131 | CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, 132 | CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, 133 | CLKIN1 => clk_in1_clkgen_50mhz, 134 | CLKIN2 => '0', 135 | CLKINSEL => '1', 136 | CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, 137 | CLKOUT0 => clk_out1_clkgen_50mhz, 138 | CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, 139 | CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, 140 | CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, 141 | CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, 142 | CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, 143 | CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, 144 | CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, 145 | CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, 146 | CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, 147 | CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, 148 | DADDR(6 downto 0) => B"0000000", 149 | DCLK => '0', 150 | DEN => '0', 151 | DI(15 downto 0) => B"0000000000000000", 152 | DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), 153 | DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, 154 | DWE => '0', 155 | LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED, 156 | PSCLK => '0', 157 | PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, 158 | PSEN => '0', 159 | PSINCDEC => '0', 160 | PWRDWN => '0', 161 | RST => '0' 162 | ); 163 | end STRUCTURE; 164 | library IEEE; 165 | use IEEE.STD_LOGIC_1164.ALL; 166 | library UNISIM; 167 | use UNISIM.VCOMPONENTS.ALL; 168 | entity clkgen_50mhz is 169 | port ( 170 | clk_out1 : out STD_LOGIC; 171 | clk_in1 : in STD_LOGIC 172 | ); 173 | attribute NotValidForBitStream : boolean; 174 | attribute NotValidForBitStream of clkgen_50mhz : entity is true; 175 | end clkgen_50mhz; 176 | 177 | architecture STRUCTURE of clkgen_50mhz is 178 | begin 179 | inst: entity work.clkgen_50mhz_clk_wiz 180 | port map ( 181 | clk_in1 => clk_in1, 182 | clk_out1 => clk_out1 183 | ); 184 | end STRUCTURE; 185 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sim/debugger/tb.sv: -------------------------------------------------------------------------------- 1 | /* Testbench */ 2 | 3 | `default_nettype none 4 | 5 | module tb; 6 | timeunit 1ns / 1ps; 7 | 8 | const realtime tclk = 1s / 100.0e6; // System clock period 9 | const realtime ttck = 1s / 10.0e6; // JTAG clock period 10 | 11 | localparam dm_base_addr = 'h1A110000; 12 | 13 | typedef enum logic [4:0] {BYPASS0 = 'h0, 14 | IDCODE = 'h1, 15 | DTMCSR = 'h10, 16 | DMIACCESS = 'h11, 17 | BYPASS1 = 'h1f} ir_t; 18 | 19 | typedef struct packed { 20 | logic [31:18] zero1; 21 | logic dmihardreset; 22 | logic dmireset; 23 | logic zero0; 24 | logic [14:12] idle; 25 | logic [11:10] dmistat; 26 | logic [9:4] abits; 27 | logic [3:0] version; 28 | } dtmcs_t; 29 | 30 | typedef struct packed { 31 | logic [6:0] addr; 32 | logic [31:0] data; 33 | dm::dtm_op_e op; 34 | } dmi_req_t; 35 | 36 | typedef struct packed { 37 | logic [6:0] addr; 38 | logic [31:0] data; 39 | logic [1:0] resp; 40 | } dmi_resp_t; 41 | 42 | bit clk100mhz; 43 | bit [3:0] sw; 44 | wire [3:0] led; 45 | bit [3:0] btn; 46 | bit ck_rst_n; 47 | bit tck; 48 | bit trst_n; 49 | bit tms; 50 | bit tdi; 51 | wire tdo; 52 | 53 | logic [4:0] ir_resp = 5'h0; 54 | logic [31:0] idcode = 32'h0; 55 | dtmcs_t dtmcs = '0; 56 | dmi_req_t dmi_req = '0; 57 | dmi_resp_t dmi_resp = '0; 58 | dm::dmstatus_t dmstatus = '0; 59 | dm::hartinfo_t hartinfo = '0; 60 | dm::abstractcs_t abstractcs = '0; 61 | dm::dmcontrol_t dmcontrol = '0; 62 | logic [31:0] data0 = '0; 63 | logic [31:0] sbdata0 = '0; 64 | 65 | `include "tasks.svh" 66 | 67 | glbl glbl(); 68 | ibex_soc dut(.*); 69 | 70 | always #(tclk / 2) clk100mhz = ~clk100mhz; 71 | 72 | always #(ttck / 2) tck = ~tck; 73 | 74 | `ifdef ASSERT_ON 75 | bind dut wb_checker wbm0_checker(wbm[0]); 76 | bind dut wb_checker wbm1_checker(wbm[1]); 77 | bind dut wb_checker wbs0_checker(wbs[0]); 78 | bind dut wb_checker wbs1_checker(wbs[1]); 79 | `endif 80 | 81 | initial 82 | begin:main 83 | string filename; 84 | int status; 85 | 86 | $timeformat(-9, 3, " ns"); 87 | 88 | status = $value$plusargs("filename=%s", filename); 89 | chk_filename: assert (status) else $fatal(1, "No memory file provided. Please use './simv '+filename="); 90 | $readmemh(filename, tb.dut.wb_spram.spram.mem); 91 | 92 | repeat (3) @(negedge clk100mhz); 93 | ck_rst_n = 1'b1; 94 | 95 | repeat (3) @(negedge tck); 96 | trst_n = 1'b1; 97 | 98 | /* JTAG IDCODE */ 99 | jtag_test_logic_reset(); 100 | jtag_run_test_idle(); 101 | jtag_dr_idcode('0, idcode); 102 | chk_idcode: assert (idcode == 32'h00000001); 103 | 104 | /* read DTM Control and Status */ 105 | jtag_ir(DTMCSR, ir_resp); 106 | jtag_dr_dtmcs('0, dtmcs); 107 | chk_dtmcs_idle : assert (dtmcs.idle == 3'd1); // Enter Run-Test/Idle and leave it immediately. 108 | chk_dtmcs_dmistat : assert (dtmcs.dmistat == 2'd0); // No error. 109 | chk_dtmcs_abits : assert (dtmcs.abits == 6'd7); // The size of address in dmi. 110 | chk_dtmcs_version : assert (dtmcs.version == 4'd1); // Version described in spec version 0.13. 111 | 112 | /* access DMI */ 113 | jtag_ir(DMIACCESS, ir_resp); 114 | 115 | /* read dmstatus */ 116 | $display("%t DMI read dmstatus", $realtime); 117 | dmi_req.addr = dm::DMStatus; 118 | dmi_req.op = dm::DTM_READ; 119 | dmi_req.data = 32'h0; 120 | jtag_dr_dmi(dmi_req, dmi_resp); 121 | 122 | /* read hartinfo */ 123 | $display("%t DMI read hartinfo", $realtime); 124 | dmi_req.addr = dm::Hartinfo; 125 | dmi_req.op = dm::DTM_READ; 126 | dmi_req.data = 32'h0; 127 | jtag_dr_dmi(dmi_req, dmi_resp); 128 | 129 | /* check dmstatus */ 130 | $display("%t DMI check dmstatus", $realtime); 131 | dmstatus = dmi_resp.data; 132 | chk_dmstatus_authenticated : assert (dmstatus.authenticated == 1'b1); 133 | chk_dmstatus_authbusy : assert (dmstatus.authbusy == 1'b0); 134 | chk_dmstatus_hasresethaltreq : assert (dmstatus.hasresethaltreq == 1'b0); 135 | chk_dmstatus_confstrptrvalid : assert (dmstatus.devtreevalid == 1'b0); 136 | chk_dmstatus_version : assert (dmstatus.version == dm::DbgVersion013); 137 | 138 | /* read abstractcs */ 139 | $display("%t DMI read abstractcs", $realtime); 140 | dmi_req.addr = dm::AbstractCS; 141 | dmi_req.op = dm::DTM_READ; 142 | dmi_req.data = 32'h0; 143 | jtag_dr_dmi(dmi_req, dmi_resp); 144 | 145 | /* check hartinfo */ 146 | $display("%t DMI check hartinfo", $realtime); 147 | hartinfo = dmi_resp.data; 148 | chk_hartinfo_nscratch : assert (hartinfo.nscratch == 4'd2); 149 | chk_hartinfo_dataaccess : assert (hartinfo.dataaccess == 1'b1); 150 | chk_hartinfo_datasize : assert (hartinfo.datasize == dm::DataCount); 151 | chk_hartinfo_dataaddr : assert (hartinfo.dataaddr == dm::DataAddr); 152 | 153 | /* write dmcontrol */ 154 | $display("%t DMI write dmcontrol", $realtime); 155 | dmcontrol.dmactive = 1'b1; 156 | dmi_req.addr = dm::DMControl; 157 | dmi_req.op = dm::DTM_WRITE; 158 | dmi_req.data = dmcontrol; 159 | jtag_dr_dmi(dmi_req, dmi_resp); 160 | 161 | /* check abstractcs */ 162 | $display("%t DMI check abstractcs", $realtime); 163 | abstractcs = dmi_resp.data; 164 | chk_abstractcs_progbufsize : assert (abstractcs.progbufsize == 5'd8); 165 | chk_abstractcs_busy : assert (abstractcs.busy == 1'b0); 166 | chk_abstractcs_cmderr : assert (abstractcs.cmderr == dm::CmdErrNone); 167 | chk_abstractcs_datacount : assert (abstractcs.datacount == dm::DataCount); 168 | 169 | /* after dmcontrol.dmactive=1 we can halt the hart */ 170 | $display("%t DMI write dmcontrol", $realtime); 171 | dmcontrol.haltreq = 1'b1; 172 | dmi_req.addr = dm::DMControl; 173 | dmi_req.op = dm::DTM_WRITE; 174 | dmi_req.data = dmcontrol; 175 | jtag_dr_dmi(dmi_req, dmi_resp); 176 | 177 | /* read dmcontrol */ 178 | $display("%t DMI read dmcontrol", $realtime); 179 | dmi_req.addr = dm::DMControl; 180 | dmi_req.op = dm::DTM_READ; 181 | dmi_req.data = '0; 182 | jtag_dr_dmi(dmi_req, dmi_resp); 183 | chk_debug_req: assert (tb.dut.wb_ibex_core.debug_req == 1'b1); 184 | $display("%t Hart is halted", $realtime); 185 | 186 | /* check dmcontrol */ 187 | $display("%t DMI check dmcontrol", $realtime); 188 | dmcontrol = dmi_resp.data; 189 | chk_dmcontrol_1: assert (dmcontrol.dmactive == 1'b1); 190 | chk_dmcontrol_2: assert (dmcontrol.haltreq == 1'b1); 191 | 192 | /* read register x13 with abstract command */ 193 | $display("%t AC read register", $realtime); 194 | ac_read_register(16'h100d, data0); 195 | chk_data0_1: assert (data0 == 32'd55); // result of fib(10) 196 | 197 | /* write to address 0x3000 */ 198 | $display("%t SB write memory", $realtime); 199 | sb_write_memory32(32'h3000, 32'h12345678); 200 | 201 | /* read from address 0x3000 */ 202 | $display("%t SB read memory", $realtime); 203 | sb_read_memory32(32'h3000, sbdata0); 204 | chk_sbdata0_1: assert (sbdata0 == 32'h12345678); 205 | 206 | #100ns $finish; 207 | end:main 208 | endmodule 209 | 210 | `resetall 211 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz_sim_netlist.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | // Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | // -------------------------------------------------------------------------------- 4 | // Tool Version: Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024 5 | // Date : Sun Apr 13 12:16:12 2025 6 | // Host : Bender running 64-bit Ubuntu 24.04.2 LTS 7 | // Command : write_verilog -force -mode funcsim 8 | // /home/bernd/Projects/github.com/pbing/ibex_wb/soc/fpga/arty-a7-100/syn/ibex_soc.gen/sources_1/ip/clkgen_50mhz/clkgen_50mhz_sim_netlist.v 9 | // Design : clkgen_50mhz 10 | // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified 11 | // or synthesized. This netlist cannot be used for SDF annotated simulation. 12 | // Device : xc7a100tcsg324-1 13 | // -------------------------------------------------------------------------------- 14 | `timescale 1 ps / 1 ps 15 | 16 | (* NotValidForBitStream *) 17 | module clkgen_50mhz 18 | (clk_out1, 19 | clk_in1); 20 | output clk_out1; 21 | input clk_in1; 22 | 23 | (* IBUF_LOW_PWR *) wire clk_in1; 24 | wire clk_out1; 25 | 26 | clkgen_50mhz_clk_wiz inst 27 | (.clk_in1(clk_in1), 28 | .clk_out1(clk_out1)); 29 | endmodule 30 | 31 | module clkgen_50mhz_clk_wiz 32 | (clk_out1, 33 | clk_in1); 34 | output clk_out1; 35 | input clk_in1; 36 | 37 | wire clk_in1; 38 | wire clk_in1_clkgen_50mhz; 39 | wire clk_out1; 40 | wire clk_out1_clkgen_50mhz; 41 | wire clkfbout_buf_clkgen_50mhz; 42 | wire clkfbout_clkgen_50mhz; 43 | wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; 44 | wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; 45 | wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; 46 | wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; 47 | wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; 48 | wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; 49 | wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; 50 | wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; 51 | wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; 52 | wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; 53 | wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; 54 | wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; 55 | wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; 56 | wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; 57 | wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED; 58 | wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; 59 | wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; 60 | 61 | (* BOX_TYPE = "PRIMITIVE" *) 62 | BUFG clkf_buf 63 | (.I(clkfbout_clkgen_50mhz), 64 | .O(clkfbout_buf_clkgen_50mhz)); 65 | (* BOX_TYPE = "PRIMITIVE" *) 66 | (* CAPACITANCE = "DONT_CARE" *) 67 | (* IBUF_DELAY_VALUE = "0" *) 68 | (* IFD_DELAY_VALUE = "AUTO" *) 69 | IBUF #( 70 | .IOSTANDARD("DEFAULT")) 71 | clkin1_ibufg 72 | (.I(clk_in1), 73 | .O(clk_in1_clkgen_50mhz)); 74 | (* BOX_TYPE = "PRIMITIVE" *) 75 | BUFG clkout1_buf 76 | (.I(clk_out1_clkgen_50mhz), 77 | .O(clk_out1)); 78 | (* BOX_TYPE = "PRIMITIVE" *) 79 | MMCME2_ADV #( 80 | .BANDWIDTH("OPTIMIZED"), 81 | .CLKFBOUT_MULT_F(10.000000), 82 | .CLKFBOUT_PHASE(0.000000), 83 | .CLKFBOUT_USE_FINE_PS("FALSE"), 84 | .CLKIN1_PERIOD(10.000000), 85 | .CLKIN2_PERIOD(0.000000), 86 | .CLKOUT0_DIVIDE_F(20.000000), 87 | .CLKOUT0_DUTY_CYCLE(0.500000), 88 | .CLKOUT0_PHASE(0.000000), 89 | .CLKOUT0_USE_FINE_PS("FALSE"), 90 | .CLKOUT1_DIVIDE(1), 91 | .CLKOUT1_DUTY_CYCLE(0.500000), 92 | .CLKOUT1_PHASE(0.000000), 93 | .CLKOUT1_USE_FINE_PS("FALSE"), 94 | .CLKOUT2_DIVIDE(1), 95 | .CLKOUT2_DUTY_CYCLE(0.500000), 96 | .CLKOUT2_PHASE(0.000000), 97 | .CLKOUT2_USE_FINE_PS("FALSE"), 98 | .CLKOUT3_DIVIDE(1), 99 | .CLKOUT3_DUTY_CYCLE(0.500000), 100 | .CLKOUT3_PHASE(0.000000), 101 | .CLKOUT3_USE_FINE_PS("FALSE"), 102 | .CLKOUT4_CASCADE("FALSE"), 103 | .CLKOUT4_DIVIDE(1), 104 | .CLKOUT4_DUTY_CYCLE(0.500000), 105 | .CLKOUT4_PHASE(0.000000), 106 | .CLKOUT4_USE_FINE_PS("FALSE"), 107 | .CLKOUT5_DIVIDE(1), 108 | .CLKOUT5_DUTY_CYCLE(0.500000), 109 | .CLKOUT5_PHASE(0.000000), 110 | .CLKOUT5_USE_FINE_PS("FALSE"), 111 | .CLKOUT6_DIVIDE(1), 112 | .CLKOUT6_DUTY_CYCLE(0.500000), 113 | .CLKOUT6_PHASE(0.000000), 114 | .CLKOUT6_USE_FINE_PS("FALSE"), 115 | .COMPENSATION("ZHOLD"), 116 | .DIVCLK_DIVIDE(1), 117 | .IS_CLKINSEL_INVERTED(1'b0), 118 | .IS_PSEN_INVERTED(1'b0), 119 | .IS_PSINCDEC_INVERTED(1'b0), 120 | .IS_PWRDWN_INVERTED(1'b0), 121 | .IS_RST_INVERTED(1'b0), 122 | .REF_JITTER1(0.010000), 123 | .REF_JITTER2(0.010000), 124 | .SS_EN("FALSE"), 125 | .SS_MODE("CENTER_HIGH"), 126 | .SS_MOD_PERIOD(10000), 127 | .STARTUP_WAIT("FALSE")) 128 | mmcm_adv_inst 129 | (.CLKFBIN(clkfbout_buf_clkgen_50mhz), 130 | .CLKFBOUT(clkfbout_clkgen_50mhz), 131 | .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), 132 | .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), 133 | .CLKIN1(clk_in1_clkgen_50mhz), 134 | .CLKIN2(1'b0), 135 | .CLKINSEL(1'b1), 136 | .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), 137 | .CLKOUT0(clk_out1_clkgen_50mhz), 138 | .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), 139 | .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), 140 | .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), 141 | .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), 142 | .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), 143 | .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), 144 | .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), 145 | .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), 146 | .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), 147 | .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), 148 | .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), 149 | .DCLK(1'b0), 150 | .DEN(1'b0), 151 | .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), 152 | .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), 153 | .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), 154 | .DWE(1'b0), 155 | .LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED), 156 | .PSCLK(1'b0), 157 | .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), 158 | .PSEN(1'b0), 159 | .PSINCDEC(1'b0), 160 | .PWRDWN(1'b0), 161 | .RST(1'b0)); 162 | endmodule 163 | `ifndef GLBL 164 | `define GLBL 165 | `timescale 1 ps / 1 ps 166 | 167 | module glbl (); 168 | 169 | parameter ROC_WIDTH = 100000; 170 | parameter TOC_WIDTH = 0; 171 | parameter GRES_WIDTH = 10000; 172 | parameter GRES_START = 10000; 173 | 174 | //-------- STARTUP Globals -------------- 175 | wire GSR; 176 | wire GTS; 177 | wire GWE; 178 | wire PRLD; 179 | wire GRESTORE; 180 | tri1 p_up_tmp; 181 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 182 | 183 | wire PROGB_GLBL; 184 | wire CCLKO_GLBL; 185 | wire FCSBO_GLBL; 186 | wire [3:0] DO_GLBL; 187 | wire [3:0] DI_GLBL; 188 | 189 | reg GSR_int; 190 | reg GTS_int; 191 | reg PRLD_int; 192 | reg GRESTORE_int; 193 | 194 | //-------- JTAG Globals -------------- 195 | wire JTAG_TDO_GLBL; 196 | wire JTAG_TCK_GLBL; 197 | wire JTAG_TDI_GLBL; 198 | wire JTAG_TMS_GLBL; 199 | wire JTAG_TRST_GLBL; 200 | 201 | reg JTAG_CAPTURE_GLBL; 202 | reg JTAG_RESET_GLBL; 203 | reg JTAG_SHIFT_GLBL; 204 | reg JTAG_UPDATE_GLBL; 205 | reg JTAG_RUNTEST_GLBL; 206 | 207 | reg JTAG_SEL1_GLBL = 0; 208 | reg JTAG_SEL2_GLBL = 0 ; 209 | reg JTAG_SEL3_GLBL = 0; 210 | reg JTAG_SEL4_GLBL = 0; 211 | 212 | reg JTAG_USER_TDO1_GLBL = 1'bz; 213 | reg JTAG_USER_TDO2_GLBL = 1'bz; 214 | reg JTAG_USER_TDO3_GLBL = 1'bz; 215 | reg JTAG_USER_TDO4_GLBL = 1'bz; 216 | 217 | assign (strong1, weak0) GSR = GSR_int; 218 | assign (strong1, weak0) GTS = GTS_int; 219 | assign (weak1, weak0) PRLD = PRLD_int; 220 | assign (strong1, weak0) GRESTORE = GRESTORE_int; 221 | 222 | initial begin 223 | GSR_int = 1'b1; 224 | PRLD_int = 1'b1; 225 | #(ROC_WIDTH) 226 | GSR_int = 1'b0; 227 | PRLD_int = 1'b0; 228 | end 229 | 230 | initial begin 231 | GTS_int = 1'b1; 232 | #(TOC_WIDTH) 233 | GTS_int = 1'b0; 234 | end 235 | 236 | initial begin 237 | GRESTORE_int = 1'b0; 238 | #(GRES_START); 239 | GRESTORE_int = 1'b1; 240 | #(GRES_WIDTH); 241 | GRESTORE_int = 1'b0; 242 | end 243 | 244 | endmodule 245 | `endif 246 | -------------------------------------------------------------------------------- /soc/fpga/arty-a7-100/sw/crc_32/crc_32.c: -------------------------------------------------------------------------------- 1 | /* This file is part of the Bristol/Embecosm Embedded Benchmark Suite. 2 | 3 | This version, copyright (C) 2013-2019 Embecosm Limited and University of 4 | Bristol 5 | 6 | Contributor James Pallister 7 | Contributor Jeremy Bennett 8 | 9 | This file is part of Embench and was formerly part of the Bristol/Embecosm 10 | Embedded Benchmark Suite. 11 | 12 | SPDX-License-Identifier: GPL-3.0-or-later 13 | 14 | Code originally from: From http://www.snippets.org/. This original code is 15 | FREE with no restrictions. */ 16 | 17 | /* CRC - 32 BIT ANSI X3.66 CRC checksum files */ 18 | 19 | #include "support.h" 20 | 21 | /* This scale factor will be changed to equalise the runtime of the 22 | benchmarks. */ 23 | //#define LOCAL_SCALE_FACTOR 145 24 | #define LOCAL_SCALE_FACTOR 1 25 | 26 | #include 27 | 28 | #ifdef __TURBOC__ 29 | #pragma warn -cln 30 | #endif 31 | 32 | /**********************************************************************\ 33 | |* Demonstration program to compute the 32-bit CRC used as the frame *| 34 | |* check sequence in ADCCP (ANSI X3.66, also known as FIPS PUB 71 *| 35 | |* and FED-STD-1003, the U.S. versions of CCITT's X.25 link-level *| 36 | |* protocol). The 32-bit FCS was added via the Federal Register, *| 37 | |* 1 June 1982, p.23798. I presume but don't know for certain that *| 38 | |* this polynomial is or will be included in CCITT V.41, which *| 39 | |* defines the 16-bit CRC (often called CRC-CCITT) polynomial. FIPS *| 40 | |* PUB 78 says that the 32-bit FCS reduces otherwise undetected *| 41 | |* errors by a factor of 10^-5 over 16-bit FCS. *| 42 | \**********************************************************************/ 43 | 44 | /* Some basic types. */ 45 | typedef unsigned char BYTE; 46 | typedef unsigned long DWORD; 47 | typedef unsigned short WORD; 48 | 49 | #define UPDC32(octet,crc) (crc_32_tab[((crc)^((BYTE)octet)) & 0xff] ^ ((crc) >> 8)) 50 | 51 | /* Need an unsigned type capable of holding 32 bits; */ 52 | 53 | typedef DWORD UNS_32_BITS; 54 | 55 | /* Copyright (C) 1986 Gary S. Brown. You may use this program, or 56 | code or tables extracted from it, as desired without restriction.*/ 57 | 58 | /* First, the polynomial itself and its table of feedback terms. The */ 59 | /* polynomial is */ 60 | /* X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 */ 61 | /* Note that we take it "backwards" and put the highest-order term in */ 62 | /* the lowest-order bit. The X^32 term is "implied"; the LSB is the */ 63 | /* X^31 term, etc. The X^0 term (usually shown as "+1") results in */ 64 | /* the MSB being 1. */ 65 | 66 | /* Note that the usual hardware shift register implementation, which */ 67 | /* is what we're using (we're merely optimizing it by doing eight-bit */ 68 | /* chunks at a time) shifts bits into the lowest-order term. In our */ 69 | /* implementation, that means shifting towards the right. Why do we */ 70 | /* do it this way? Because the calculated CRC must be transmitted in */ 71 | /* order from highest-order term to lowest-order term. UARTs transmit */ 72 | /* characters in order from LSB to MSB. By storing the CRC this way, */ 73 | /* we hand it to the UART in the order low-byte to high-byte; the UART */ 74 | /* sends each low-bit to hight-bit; and the result is transmission bit */ 75 | /* by bit from highest- to lowest-order term without requiring any bit */ 76 | /* shuffling on our part. Reception works similarly. */ 77 | 78 | /* The feedback terms table consists of 256, 32-bit entries. Notes: */ 79 | /* */ 80 | /* 1. The table can be generated at runtime if desired; code to do so */ 81 | /* is shown later. It might not be obvious, but the feedback */ 82 | /* terms simply represent the results of eight shift/xor opera- */ 83 | /* tions for all combinations of data and CRC register values. */ 84 | /* */ 85 | /* 2. The CRC accumulation logic is the same for all CRC polynomials, */ 86 | /* be they sixteen or thirty-two bits wide. You simply choose the */ 87 | /* appropriate table. Alternatively, because the table can be */ 88 | /* generated at runtime, you can start by generating the table for */ 89 | /* the polynomial in question and use exactly the same "updcrc", */ 90 | /* if your application needn't simultaneously handle two CRC */ 91 | /* polynomials. (Note, however, that XMODEM is strange.) */ 92 | /* */ 93 | /* 3. For 16-bit CRCs, the table entries need be only 16 bits wide; */ 94 | /* of course, 32-bit entries work OK if the high 16 bits are zero. */ 95 | /* */ 96 | /* 4. The values must be right-shifted by eight bits by the "updcrc" */ 97 | /* logic; the shift must be unsigned (bring in zeroes). On some */ 98 | /* hardware you could probably optimize the shift in assembler by */ 99 | /* using byte-swap instructions. */ 100 | 101 | /* The BEEBS version of this code uses its own version of rand, to 102 | avoid library/architecture variation. */ 103 | 104 | static const UNS_32_BITS crc_32_tab[] = { /* CRC polynomial 0xedb88320 */ 105 | 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 106 | 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 107 | 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, 108 | 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 109 | 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 110 | 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 111 | 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, 112 | 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 113 | 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 114 | 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 115 | 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, 116 | 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, 117 | 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 118 | 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 119 | 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, 120 | 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, 121 | 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 122 | 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 123 | 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 124 | 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, 125 | 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 126 | 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 127 | 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, 128 | 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 129 | 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 130 | 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 131 | 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, 132 | 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 133 | 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 134 | 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 135 | 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, 136 | 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, 137 | 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 138 | 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 139 | 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, 140 | 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, 141 | 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 142 | 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 143 | 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 144 | 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, 145 | 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 146 | 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 147 | 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d 148 | }; 149 | 150 | 151 | DWORD 152 | crc32pseudo () 153 | { 154 | int i; 155 | register DWORD oldcrc32; 156 | 157 | oldcrc32 = 0xFFFFFFFF; 158 | 159 | for (i = 0; i < 1024; ++i) 160 | { 161 | oldcrc32 = UPDC32 (rand_beebs (), oldcrc32); 162 | } 163 | 164 | return ~oldcrc32; 165 | } 166 | 167 | void 168 | initialise_benchmark (void) 169 | { 170 | } 171 | 172 | 173 | static int benchmark_body (int rpt); 174 | 175 | void 176 | warm_caches (int heat) 177 | { 178 | int res = benchmark_body (heat); 179 | 180 | return; 181 | } 182 | 183 | 184 | int 185 | benchmark (void) 186 | { 187 | return benchmark_body (LOCAL_SCALE_FACTOR * CPU_MHZ); 188 | } 189 | 190 | 191 | static int __attribute__ ((noinline)) 192 | benchmark_body (int rpt) 193 | { 194 | int i; 195 | DWORD r; 196 | 197 | for (i = 0; i < rpt; i++) 198 | { 199 | srand_beebs (0); 200 | r = crc32pseudo (); 201 | } 202 | 203 | return (int) (r % 32768); 204 | } 205 | 206 | 207 | int 208 | verify_benchmark (int r) 209 | { 210 | return 11433 == r; 211 | } 212 | 213 | 214 | /* vim: set ts=3 sw=3 et: */ 215 | 216 | 217 | /* 218 | Local Variables: 219 | mode: C 220 | c-file-style: "gnu" 221 | End: 222 | */ 223 | --------------------------------------------------------------------------------