├── .clang-format ├── .gitignore ├── .gitlab-ci.yml ├── FFT ├── .gitignore ├── CHANGELOG ├── CMakeLists.txt ├── README.md ├── configs │ ├── Bittware_520N_MX_S7.cmake │ ├── Intel_PAC_D5005_S19.cmake │ └── Nallatech_520N_S17.cmake ├── performance │ └── README.md ├── settings │ ├── settings.compile.xilinx.fft1d_float_8.ddr.ini │ ├── settings.compile.xilinx.fft1d_float_8.hbm.ini │ ├── settings.gen.intel.fft1d_float_8.hbm.py │ ├── settings.gen.intel.fft1d_float_8.svm.py │ ├── settings.link.xilinx.fft1d_float_8.ddr.ini │ └── settings.link.xilinx.fft1d_float_8.hbm.generator.ini ├── src │ ├── common │ │ └── parameters.h.in │ ├── device │ │ ├── CMakeLists.txt │ │ ├── custom │ │ │ └── CMakeLists.txt │ │ ├── fft1d_float_8.cl │ │ ├── fft_8.cl │ │ └── twid_radix4_8.cl │ └── host │ │ ├── CMakeLists.txt │ │ ├── execution.h │ │ ├── execution_default.cpp │ │ ├── fft_benchmark.cpp │ │ ├── fft_benchmark.hpp │ │ └── main.cpp ├── synth-scripts │ ├── build_520nmx.sh │ ├── build_pac.sh │ └── synth-fft-noctua.sh └── tests │ ├── CMakeLists.txt │ ├── test_execution_functionality.cpp │ └── test_fft_functionality.cpp ├── GEMM ├── CHANGELOG ├── CMakeLists.txt ├── README.md ├── configs │ ├── Bittware_520N_B256.cmake │ ├── Bittware_520N_B512.cmake │ ├── Bittware_520N_MX_B256.cmake │ └── Intel_PAC_D5005_R5_B256.cmake ├── performance │ ├── README.md │ ├── performance_model_cannon.py │ └── requirements.txt ├── scripts │ ├── build_520n_mx.sh │ └── build_pac.sh ├── settings │ ├── settings.compile.xilinx.gemm_cannon.ddr.ini │ ├── settings.compile.xilinx.gemm_cannon.hbm.ini │ ├── settings.gen.intel.gemm_base.520n_mx.py │ ├── settings.gen.intel.gemm_base.hbm.py │ ├── settings.gen.intel.gemm_base.svm.py │ ├── settings.link.xilinx.gemm_cannon.ddr.generator.ini │ └── settings.link.xilinx.gemm_cannon.hbm.generator.ini ├── src │ ├── common │ │ └── parameters.h.in │ ├── device │ │ ├── CMakeLists.txt │ │ ├── custom │ │ │ └── CMakeLists.txt │ │ └── gemm_base.cl │ └── host │ │ ├── CMakeLists.txt │ │ ├── execution.h │ │ ├── execution_default.cpp │ │ ├── gemm_benchmark.cpp │ │ ├── gemm_benchmark.hpp │ │ ├── half.hpp │ │ └── main.cpp └── tests │ ├── CMakeLists.txt │ └── test_kernel_functionality_and_host_integration.cpp ├── LICENSE ├── LINPACK ├── .gitignore ├── CHANGELOG ├── CMakeLists.txt ├── README.md ├── configs │ ├── Nallatech_520N_B10_SB3_R4.cmake │ ├── Nallatech_520N_B10_SB4.cmake │ ├── Nallatech_520N_B8_SB2_R5_DP_noring.cmake │ ├── Nallatech_520N_B8_SB3_R4.cmake │ ├── Nallatech_520N_B8_SB3_R5.cmake │ ├── Nallatech_520N_B8_SB3_R7.cmake │ ├── Nallatech_520N_B9_SB3_R3.cmake │ ├── Nallatech_520N_B9_SB3_R4.cmake │ ├── Nallatech_520N_B9_SB3_R4_noring.cmake │ ├── Nallatech_520N_B9_SB3_R5_noring.cmake │ ├── Xilinx_U250_B8_SB3_R3.cmake │ ├── Xilinx_U280_B8_SB3_R1_ACCL.cmake │ ├── Xilinx_U280_B8_SB3_R2.cmake │ ├── Xilinx_U280_B8_SB3_R2_DDR_PCIE.cmake │ ├── Xilinx_U280_B8_SB3_R2_HBM_PCIE_profile.cmake │ ├── Xilinx_U280_B8_SB3_R3_HBM_PCIE.cmake │ ├── Xilinx_U55C_B8_SB3_R1_ACCL.cmake │ ├── Xilinx_U55C_B8_SB3_R1_ACCL_profile.cmake │ └── Xilinx_U55C_B8_SB3_R2_HBM_PCIE.cmake ├── scripts │ └── hpl_model.ipynb ├── settings │ ├── pre_synthesis.u250.tcl │ ├── settings.compile.xilinx.hpl_torus_pcie.ddr.ini │ ├── settings.compile.xilinx.hpl_torus_pcie.u250.ini │ ├── settings.link.xilinx.hpl_torus_accl.hbm.generator.ini │ ├── settings.link.xilinx.hpl_torus_accl.hbm.u280.generator.ini │ ├── settings.link.xilinx.hpl_torus_accl.hbm.u55c.generator.ini │ ├── settings.link.xilinx.hpl_torus_accl.hbm.u55c.profile.generator.ini │ ├── settings.link.xilinx.hpl_torus_pcie.ddr.generator.ini │ ├── settings.link.xilinx.hpl_torus_pcie.distribute_kernels.hbm.generator.ini │ ├── settings.link.xilinx.hpl_torus_pcie.hbm.generator.ini │ ├── settings.link.xilinx.hpl_torus_pcie.hbm.u280.profile.generator.ini │ └── settings.link.xilinx.hpl_torus_pcie.u250.generator.ini ├── src │ ├── common │ │ └── parameters.h.in │ ├── device │ │ ├── CMakeLists.txt │ │ ├── custom │ │ │ └── CMakeLists.txt │ │ ├── hpl_torus_ACCL_buffers.cpp │ │ ├── hpl_torus_IEC.cl │ │ ├── hpl_torus_PCIE.cl │ │ └── hpl_torus_PCIE.cpp │ └── host │ │ ├── CMakeLists.txt │ │ ├── blas.c │ │ ├── execution.h │ │ ├── execution_types │ │ ├── execution_accl_buffers.hpp │ │ ├── execution_iec.hpp │ │ ├── execution_pcie.hpp │ │ ├── execution_types.hpp │ │ └── execution_xrt_pcie.hpp │ │ ├── gmres.c │ │ ├── gmres.h │ │ ├── linpack_benchmark.hpp │ │ ├── linpack_data.cpp │ │ ├── linpack_data.hpp │ │ └── main.cpp └── tests │ ├── CMakeLists.txt │ ├── test_host_reference_implementations.cpp │ ├── test_kernel_communication.cpp │ ├── test_kernel_functionality_and_host_integration.cpp │ └── test_torus2x2_operations.cpp ├── PTRANS ├── CHANGELOG ├── CMakeLists.txt ├── README.md ├── configs │ ├── BittWare_520N_MX_pcie.cmake │ ├── Nallatech_520N.cmake │ ├── Nallatech_520N_CPU.cmake │ ├── Nallatech_520N_ch2.cmake │ ├── Nallatech_520N_ch2_interleave.cmake │ ├── Nallatech_520N_interleave.cmake │ ├── Nallatech_520N_pcie.cmake │ ├── Xilinx_U250_DDR_PCIE.cmake │ ├── Xilinx_U250_DDR_PCIE_unroll.cmake │ ├── Xilinx_U280_DDR_ACCL_TCP_buffers.cmake │ ├── Xilinx_U280_DDR_ACCL_buffers.cmake │ ├── Xilinx_U280_DDR_ACCL_stream.cmake │ ├── Xilinx_U280_DDR_PCIE.cmake │ ├── Xilinx_U280_HBM_ACCL_stream.cmake │ ├── Xilinx_U280_HBM_ACCL_stream_profile.cmake │ ├── Xilinx_U55C_HBM_ACCL_stream.cmake │ ├── Xilinx_U55C_HBM_ACCL_stream_profile.cmake │ └── Xilinx_U55C_HBM_PCIE.cmake ├── scripts │ ├── build_520n.sh │ ├── build_520n_ch1.sh │ ├── build_520n_ch2.sh │ ├── build_520n_pcie.sh │ ├── build_u250.sh │ ├── build_u250_unroll.sh │ ├── build_u280_alveo.sh │ ├── build_u280_alveo_ddr_singleloop.sh │ ├── prepare_tests.sh │ ├── run_transpose.sh │ └── run_transpose_gen.sh ├── settings │ ├── settings.compile.xilinx.transpose_pq_pcie.ddr.ini │ ├── settings.compile.xilinx.transpose_pq_pcie.hbm.ini │ ├── settings.compile.xilinx.transpose_pq_pcie.u250.ini │ ├── settings.gen.intel.transpose_pq.s10mxhbm.py │ ├── settings.link.xilinx.transpose_pq_accl_buffers.ddr.ini │ ├── settings.link.xilinx.transpose_pq_accl_stream.ddr.ini │ ├── settings.link.xilinx.transpose_pq_accl_stream.hbm.ini │ ├── settings.link.xilinx.transpose_pq_accl_stream.hbm.profile.ini │ ├── settings.link.xilinx.transpose_pq_accl_stream.hbm.u280.ini │ ├── settings.link.xilinx.transpose_pq_accl_stream.hbm.u280.profile.ini │ ├── settings.link.xilinx.transpose_pq_accl_tcp_buffers.ddr.ini │ ├── settings.link.xilinx.transpose_pq_pcie.ddr.generator.ini │ ├── settings.link.xilinx.transpose_pq_pcie.hbm.generator.ini │ ├── settings.link.xilinx.transpose_pq_pcie.u250.generator.ini │ └── settings.link.xilinx.transpose_pq_pcie_spread_banks.hbm.generator.ini ├── src │ ├── common │ │ └── parameters.h.in │ ├── device │ │ ├── CMakeLists.txt │ │ ├── custom │ │ │ └── CMakeLists.txt │ │ ├── transpose_DIAG_IEC.cl │ │ ├── transpose_DIAG_PCIE.cl │ │ ├── transpose_PQ_ACCL_buffers.cpp │ │ ├── transpose_PQ_ACCL_stream.cpp │ │ ├── transpose_PQ_ACCL_stream_sendrecv.cpp │ │ ├── transpose_PQ_IEC.cl │ │ ├── transpose_PQ_PCIE.cl │ │ ├── transpose_PQ_PCIE.cpp │ │ └── transpose_c2_DIAG_IEC.cl │ └── host │ │ ├── CMakeLists.txt │ │ ├── data_handlers │ │ ├── data_handler_types.h │ │ ├── diagonal.hpp │ │ ├── handler.hpp │ │ └── pq.hpp │ │ ├── execution_types │ │ ├── execution_cpu.hpp │ │ ├── execution_intel.hpp │ │ ├── execution_intel_pq.hpp │ │ ├── execution_pcie.hpp │ │ ├── execution_pcie_pq.hpp │ │ ├── execution_xrt_accl_pq.hpp │ │ ├── execution_xrt_accl_stream_pq.hpp │ │ ├── execution_xrt_accl_stream_pq_sendrecv.hpp │ │ └── execution_xrt_pcie_pq.hpp │ │ ├── main.cpp │ │ ├── transpose_benchmark.hpp │ │ ├── transpose_data.cpp │ │ └── transpose_data.hpp └── tests │ ├── CMakeLists.txt │ ├── test_host_functionality.cpp │ ├── test_kernel_functionality_and_host_integration.cpp │ └── test_transpose_data_handlers.cpp ├── README.md ├── RandomAccess ├── .gitignore ├── CHANGELOG ├── CMakeLists.txt ├── README.md ├── configs │ ├── Bittware_520N_IVDEP_RNG5.cmake │ ├── Xilinx_U280_RNG1_DDR.cmake │ └── Xilinx_U280_RNG4_HBM.cmake ├── results │ ├── README.md │ ├── frandom_single_results.csv │ └── frandom_single_results.jpg ├── scripts │ ├── build_520nmx.sh │ └── build_pac.sh ├── settings │ ├── settings.compile.xilinx.random_access_kernels_single.ddr.ini │ ├── settings.compile.xilinx.random_access_kernels_single.hbm.ini │ ├── settings.gen.intel.random_access_kernels_single.hbm.py │ ├── settings.gen.intel.random_access_kernels_single.svm.py │ ├── settings.link.xilinx.random_access_kernels_single.ddr.ini │ └── settings.link.xilinx.random_access_kernels_single.hbm.generator.ini ├── src │ ├── common │ │ └── parameters.h.in │ ├── device │ │ ├── CMakeLists.txt │ │ ├── custom │ │ │ └── CMakeLists.txt │ │ └── random_access_kernels_single.cl │ └── host │ │ ├── CMakeLists.txt │ │ ├── execution.h │ │ ├── execution_single.cpp │ │ ├── main.cpp │ │ ├── random_access_benchmark.cpp │ │ └── random_access_benchmark.hpp └── tests │ ├── CMakeLists.txt │ ├── test_host_code.cpp │ └── test_kernel_functionality_and_host_integration.cpp ├── STREAM ├── .gitignore ├── CHANGELOG ├── CMakeLists.txt ├── README.md ├── configs │ ├── Bittware_520N_MX_SP_256bit_small.cmake │ ├── Intel_PAC_D5005_SP.cmake │ ├── Nallatech_520N_DP.cmake │ ├── Nallatech_520N_HP.cmake │ ├── Nallatech_520N_SP.cmake │ ├── Xilinx_U280_DP.cmake │ ├── Xilinx_U280_DP_225MHz.cmake │ ├── Xilinx_U280_HP.cmake │ ├── Xilinx_U280_SP.cmake │ └── Xilinx_U280_SP_225MHz.cmake ├── csv_result_export │ ├── README.md │ ├── create_plots.py │ ├── dp_global_ring_plot.jpeg │ ├── dp_plot.jpeg │ ├── parse_data.py │ ├── raw_results │ │ ├── 16-0-2_16_0_2_Intel-BDW+FPGA-hybrid-CPU+FPGA-Arria-10-GX1150.txt │ │ ├── 17-1-2_17-1-2_Bittware-385A-(Intel-Arria-10-GX1150)-Buffer-Reorder_ni.txt │ │ ├── 17-1-2_17-1-2_Bittware-385A-(Intel-Arria-10-GX1150).txt │ │ ├── 17-1-2_17-1-2_Bittware-385A-(Intel-Arria-10-GX1150)_ni.txt │ │ ├── 18-0-1_18-0-1_Bittware-520N-(Intel-Stratix-10-GX2800).txt │ │ ├── 18-0-1_18-0-1_Bittware-520N-(Intel-Stratix-10-GX2800)_ni.txt │ │ ├── 18-1-1_18-1-1_Bittware-520N-(Intel-Stratix-10-GX2800).txt │ │ ├── 18-1-1_18-1-1_Bittware-520N-(Intel-Stratix-10-GX2800)_ni.txt │ │ ├── 19-1_19-1_Bittware-520N-(Intel-Stratix-10-GX2800).txt │ │ ├── 19-1_19-1_Bittware-520N-(Intel-Stratix-10-GX2800)_ni.txt │ │ ├── 19-2_19-2_Bittware-520N-(Intel-Stratix-10-GX2800).txt │ │ ├── 19-2_19-2_Bittware-520N-(Intel-Stratix-10-GX2800)_ni.txt │ │ ├── 19-3_18-1-2_Intel-FPGA-PAC-D5005-(Intel-Stratix-10-SX).txt │ │ ├── 19-3_18-1-2_Intel-FPGA-PAC-D5005-(Intel-Stratix-10-SX)_ni.txt │ │ ├── 19-3_19-2_Bittware-520N-(Intel-Stratix-10-GX2800).txt │ │ ├── 19-3_19-2_Bittware-520N-(Intel-Stratix-10-GX2800)_ni.txt │ │ ├── 19-4_18-1-2_Intel-FPGA-PAC-D5005-(Intel-Stratix-10-SX)-SVM.txt │ │ ├── 19-4_18-1-2_Intel-FPGA-PAC-D5005-(Intel-Stratix-10-SX)-SVM_ni.txt │ │ └── README.md │ ├── requirements.txt │ ├── sp_global_ring_plot.jpeg │ └── sp_plot.jpeg ├── results.txt ├── scripts │ ├── build_520n.sh │ ├── build_520n_mx_hbm.sh │ └── build_u280.sh ├── settings │ ├── settings.compile.xilinx.stream_kernels_single.512bit.hbm.ini │ ├── settings.compile.xilinx.stream_kernels_single.ddr.ini │ ├── settings.compile.xilinx.stream_kernels_single.hbm.ini │ ├── settings.gen.intel.stream_kernels_single.s10mxhbm.py │ ├── settings.gen.intel.stream_kernels_single.svm.py │ ├── settings.link.xilinx.stream_kernels.ddr.ini │ ├── settings.link.xilinx.stream_kernels.hbm.generator.ini │ ├── settings.link.xilinx.stream_kernels_single.ddr.ini │ └── settings.link.xilinx.stream_kernels_single.hbm.generator.ini ├── src │ ├── common │ │ └── parameters.h.in │ ├── device │ │ ├── CMakeLists.txt │ │ ├── custom │ │ │ └── CMakeLists.txt │ │ ├── stream_kernels.cl │ │ └── stream_kernels_single.cl │ └── host │ │ ├── CMakeLists.txt │ │ ├── execution.hpp │ │ ├── execution_default.cpp │ │ ├── half.hpp │ │ ├── main.cpp │ │ ├── stream_benchmark.cpp │ │ └── stream_benchmark.hpp └── tests │ ├── CMakeLists.txt │ └── test_kernel_functionality_and_host_integration.cpp ├── b_eff ├── .gitignore ├── CHANGELOG ├── CMakeLists.txt ├── README.md ├── configs │ ├── Bittware_520N.cmake │ ├── Bittware_520N_PCIE.cmake │ ├── Xilinx_U280_DDR.cmake │ ├── Xilinx_U280_DDR_ACCL_buffers_ddr.cmake │ ├── Xilinx_U280_DDR_ACCL_buffers_hbm.cmake │ ├── Xilinx_U280_HBM.cmake │ ├── Xilinx_U280_HBM_ACCL_pl_profile.cmake │ ├── Xilinx_U280_HBM_VNX.cmake │ ├── Xilinx_U55C_DDR_ACCL_buffers_hbm.cmake │ ├── Xilinx_U55C_DDR_ACCL_pl_hbm.cmake │ └── Xilinx_U55C_HBM_ACCL_pl_profile.cmake ├── performance │ ├── README.md │ ├── bandwidth_compare.jpg │ └── bandwidth_model.jpg ├── scripts │ ├── build_520n.sh │ ├── clean_emulation_output_files.sh │ ├── prepare_tests.sh │ ├── run_u280_pcie_hbm.sh │ └── run_u280_udp.sh ├── settings │ ├── settings.compile.xilinx.accl_buffers.ini │ ├── settings.compile.xilinx.u280.ini │ ├── settings.link.xilinx.accl_buffers.ddr.ini │ ├── settings.link.xilinx.accl_buffers.hbm.ini │ ├── settings.link.xilinx.accl_buffers.u55c.hbm.ini │ ├── settings.link.xilinx.accl_pl.u280.hbm.profile.ini │ ├── settings.link.xilinx.accl_pl.u55c.hbm.ini │ ├── settings.link.xilinx.accl_pl.u55c.hbm.profile.ini │ ├── settings.link.xilinx.u280.ddr.ini │ ├── settings.link.xilinx.u280.hbm.ini │ └── settings.link.xilinx.vnx.u280.hbm.ini ├── src │ ├── common │ │ └── parameters.h.in │ ├── device │ │ ├── CMakeLists.txt │ │ ├── communication_ACCL.cl │ │ ├── communication_ACCL_pl.cpp │ │ ├── communication_ACCL_pl_stream.cpp │ │ ├── communication_PCIE.cl │ │ ├── communication_UDP.cpp │ │ ├── communication_bw520n_IEC.cl │ │ └── custom │ │ │ └── CMakeLists.txt │ └── host │ │ ├── CMakeLists.txt │ │ ├── execution_types │ │ ├── execution.hpp │ │ ├── execution_accl.hpp │ │ ├── execution_accl_pl.hpp │ │ ├── execution_accl_pl_stream.hpp │ │ ├── execution_accl_stream.hpp │ │ ├── execution_cpu.hpp │ │ ├── execution_iec.hpp │ │ ├── execution_pcie.hpp │ │ ├── execution_pcie_reverse.hpp │ │ └── execution_udp.hpp │ │ ├── main.cpp │ │ ├── network_benchmark.cpp │ │ └── network_benchmark.hpp └── tests │ ├── CMakeLists.txt │ └── test_kernel_functionality_and_host_integration.cpp ├── cmake ├── accl.cmake ├── customKernelTargets.cmake ├── general_benchmark_build_setup.cmake ├── kernelTargets.cmake ├── unitTestTargets.cmake └── vnx.cmake ├── docs ├── Makefile ├── doxy.config ├── make.bat ├── requirements.txt ├── scripts │ ├── plot_all_from_csv.ipynb │ └── plot_stream_from_csv.ipynb └── source │ ├── .static │ └── css │ │ └── custom.css │ ├── .templates │ └── layout.html │ ├── FFT │ ├── index.rst │ ├── kernel_data_flow.drawio.png │ ├── kernel_data_flow.drawio.svg │ └── results │ │ ├── fft-1-1.csv │ │ └── index.rst │ ├── GEMM │ ├── index.rst │ ├── kernel_memory_hierarchy.drawio.png │ └── results │ │ ├── gemm-1-0.csv │ │ └── index.rst │ ├── LINPACK │ ├── implementation │ │ ├── external_channel_usage.drawio.png │ │ ├── index.rst │ │ ├── kernel_exchange_step.drawio.png │ │ ├── kernel_update_step.drawio.png │ │ ├── lu_iteration.drawio.png │ │ ├── lu_iteration_block1.drawio.png │ │ ├── torus_data_forward.drawio.png │ │ └── torus_data_forward_rev.drawio.png │ └── index.rst │ ├── PTRANS │ ├── diagonal_data_distribution.drawio.png │ ├── index.rst │ └── transpose_data_class.drawio.png │ ├── RandomAccess │ ├── index.rst │ └── results │ │ ├── index.rst │ │ └── randomaccess-2-2.csv │ ├── STREAM │ ├── index.rst │ ├── results │ │ ├── index.rst │ │ ├── stream-2-3.csv │ │ └── stream_results.png │ └── stream_kernel_data_flow.drawio.png │ ├── b_eff │ ├── index.rst │ ├── network_bandwidth_model.jpg │ └── network_topology_setup.drawio.png │ ├── conf.py │ ├── index.rst │ ├── overall_results.png │ ├── spacial_temporal_memory_access.drawio.png │ └── technical_support │ ├── Basic Setup │ └── index.rst │ ├── Host Input Parameters │ └── index.rst │ ├── Project Structure │ └── index.rst │ ├── json_output │ └── index.rst │ └── multi_fpga │ └── index.rst ├── extern ├── CMakeLists.txt └── README.md ├── scripts ├── README.md ├── code_generator │ ├── README.md │ ├── generator.py │ └── requirements.txt ├── evaluation │ ├── .gitignore │ ├── execute_and_parse.sh │ ├── parse_raw_to_csv.py │ └── requirements.txt ├── power_measurements │ └── pac_s10_dc.fpgainfo.sh └── test_all.sh └── shared ├── CMakeLists.txt ├── README.md ├── hpcc_settings.cpp ├── include ├── base_parameters.h.in ├── communication_types.hpp ├── hpcc_benchmark.hpp ├── hpcc_settings.hpp └── setup │ ├── fpga_setup.hpp │ ├── fpga_setup_accl.hpp │ ├── fpga_setup_udp.hpp │ └── fpga_setup_xrt.hpp ├── setup ├── fpga_setup.cpp ├── fpga_setup_accl.cpp ├── fpga_setup_udp.cpp └── fpga_setup_xrt.cpp └── tests ├── CMakeLists.txt ├── hpcc_base_benchmark_test.cpp ├── main.cpp └── test_program_settings.h /.clang-format: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pc2/HPCC_FPGA/HEAD/.clang-format -------------------------------------------------------------------------------- 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