├── lib ├── hw │ ├── contrib │ │ └── pcores │ │ │ ├── nf10_upb_ofswitch_v1_00_a │ │ │ ├── prj │ │ │ │ └── nf10_upb_ofswitch.sdc │ │ │ ├── data │ │ │ │ └── nf10_upb_ofswitch_v2_1_0.bbd │ │ │ ├── hdl │ │ │ │ └── SystemVerilog │ │ │ │ │ ├── tuple_t.v │ │ │ │ │ ├── statistics_tb.v │ │ │ │ │ ├── parameters.v │ │ │ │ │ └── action_delay.v │ │ │ ├── Makefile │ │ │ └── doc │ │ │ │ ├── README.md │ │ │ │ └── clear_cam.py │ │ │ ├── nf10_upb_switch_v1_00_a │ │ │ ├── data │ │ │ │ ├── nf10_upb_switch_v2_1_0.pao │ │ │ │ ├── nf10_upb_switch_v2_1_0.bbd │ │ │ │ └── nf10_upb_switch_v2_1_0.mpd │ │ │ ├── prj │ │ │ │ ├── nf10_upb_switch.sdc │ │ │ │ └── nf10_upb_switch.prj │ │ │ ├── Makefile │ │ │ └── hdl │ │ │ │ └── SystemVerilog │ │ │ │ ├── ram.v │ │ │ │ └── delay.v │ │ │ ├── nf10_upb_dma_v1_00_a │ │ │ ├── hdl │ │ │ │ ├── verilog │ │ │ │ │ └── xilinx │ │ │ │ │ │ ├── README │ │ │ │ │ │ └── pcie_top.v.patch │ │ │ │ └── SystemVerilog │ │ │ │ │ └── README │ │ │ ├── data │ │ │ │ └── nf10_upb_dma_v2_1_0.bbd │ │ │ ├── netlist │ │ │ │ └── chipscope_ila_128.ngc │ │ │ ├── prj │ │ │ │ └── dma_engine.sdc │ │ │ └── Makefile │ │ │ ├── nf10_upb_10g_interface_v1_00_a │ │ │ ├── data │ │ │ │ ├── nf10_upb_10g_interface_v2_1_0.bbd │ │ │ │ └── nf10_upb_10g_interface_v2_1_0.pao │ │ │ ├── hdl │ │ │ │ └── verilog │ │ │ │ │ └── xilinx │ │ │ │ │ ├── cc_2b_1skp.diff │ │ │ │ │ ├── xaui_block.diff │ │ │ │ │ └── rocketio_wrapper.diff │ │ │ └── xco │ │ │ │ ├── xaui.xco │ │ │ │ └── xgmac.xco │ │ │ ├── nf10_upb_interconnect_v1_00_a │ │ │ ├── data │ │ │ │ ├── nf10_upb_interconnect_v2_1_0.bbd │ │ │ │ └── nf10_upb_interconnect_v2_1_0.pao │ │ │ ├── prj │ │ │ │ └── synplify │ │ │ │ │ └── interconnect.sdc │ │ │ ├── hdl │ │ │ │ └── verilog │ │ │ │ │ └── aurora │ │ │ │ │ └── aurora_8b10b_v5_3_reset_logic.patch │ │ │ ├── chipscope │ │ │ │ ├── gen_nf10_upb_aurora_input_cdc.py │ │ │ │ └── gen_nf10_upb_interconnect_cdc.py │ │ │ └── Makefile │ │ │ ├── nf10_upb_axi_lite_chipscope_v1_00_a │ │ │ ├── netlist │ │ │ │ └── chipscope_ila_256.ngc │ │ │ └── data │ │ │ │ ├── nf10_upb_axi_lite_chipscope_v2_1_0.bbd │ │ │ │ └── nf10_upb_axi_lite_chipscope_v2_1_0.pao │ │ │ ├── nf10_upb_axi_stream_chipscope_v1_00_a │ │ │ ├── netlist │ │ │ │ └── chipscope_ila_512.ngc │ │ │ ├── data │ │ │ │ ├── nf10_upb_axi_stream_chipscope_v2_1_0.bbd │ │ │ │ └── nf10_upb_axi_stream_chipscope_v2_1_0.mpd │ │ │ ├── chipscope │ │ │ │ └── gen_axi_stream_chipscope.py │ │ │ ├── Makefile │ │ │ └── prj │ │ │ │ └── nf10_upb_axi_stream_chipscope.prj │ │ │ ├── nf10_upb_input_arbiter_v1_00_a │ │ │ ├── prj │ │ │ │ ├── nf10_upb_input_arbiter.sdc │ │ │ │ ├── nf10_upb_input_arbiter_5.prj │ │ │ │ ├── nf10_upb_input_arbiter_7.prj │ │ │ │ ├── nf10_upb_input_arbiter_4.prj │ │ │ │ ├── nf10_upb_input_arbiter_6.prj │ │ │ │ └── nf10_upb_input_arbiter_8.prj │ │ │ ├── hdl │ │ │ │ └── verilog │ │ │ │ │ ├── nf10_upb_input_arbiter_tb.prj │ │ │ │ │ ├── nf10_upb_input_arbiter_tb.sh │ │ │ │ │ └── nf10_upb_input_arbiter_tb.tcl │ │ │ ├── data │ │ │ │ └── nf10_upb_input_arbiter_v2_1_0.bbd │ │ │ └── Makefile │ │ │ ├── nf10_upb_lib │ │ │ ├── hdl │ │ │ │ ├── SystemVerilog │ │ │ │ │ ├── axis_if.v │ │ │ │ │ ├── secded.v │ │ │ │ │ ├── qdr2_sram.v │ │ │ │ │ └── tkeep_coder.v │ │ │ │ └── verilog │ │ │ │ │ ├── tkeep_coder.v │ │ │ │ │ ├── flow_ctrl.v │ │ │ │ │ └── frame_gen_tb.v │ │ │ └── prj │ │ │ │ └── upb_packet_fifo_dev │ │ │ │ └── nf10_upb_packet_fifo.ucf │ │ │ ├── nf10_upb_output_queue_v1_00_a │ │ │ ├── testbench │ │ │ │ ├── main_tb.v │ │ │ │ ├── CY7C1515JV18.vhd.patch │ │ │ │ └── README │ │ │ ├── prj │ │ │ │ └── qdr2_test_netfpga │ │ │ │ │ ├── main.v │ │ │ │ │ └── ipcore_dir │ │ │ │ │ ├── icon.xco │ │ │ │ │ └── vio_main.xco │ │ │ ├── hdl │ │ │ │ └── verilog │ │ │ │ │ ├── nf10_upb_output_queue_2.sdc │ │ │ │ │ ├── nf10_upb_output_queue_3.sdc │ │ │ │ │ ├── nf10_upb_output_queue_4.sdc │ │ │ │ │ ├── nf10_upb_output_queue_5.sdc │ │ │ │ │ ├── nf10_upb_output_queue_6.sdc │ │ │ │ │ ├── nf10_upb_output_queue_7.sdc │ │ │ │ │ ├── nf10_upb_output_queue_2.prj │ │ │ │ │ ├── nf10_upb_output_queue_3.prj │ │ │ │ │ ├── nf10_upb_output_queue_4.prj │ │ │ │ │ ├── nf10_upb_output_queue_5.prj │ │ │ │ │ ├── nf10_upb_output_queue_6.prj │ │ │ │ │ └── nf10_upb_output_queue_7.prj │ │ │ ├── data │ │ │ │ └── nf10_upb_output_queue_v2_1_0.bbd │ │ │ └── Makefile │ │ │ ├── nf10_upb_dma_input_v1_00_a │ │ │ └── data │ │ │ │ └── nf10_upb_dma_input_v2_1_0.pao │ │ │ ├── nf10_upb_10g_input_v1_00_a │ │ │ ├── data │ │ │ │ └── nf10_upb_10g_input_v2_1_0.pao │ │ │ └── hdl │ │ │ │ └── verilog │ │ │ │ └── width_div_tb.v │ │ │ ├── nf10_upb_dummy_port_v1_00_a │ │ │ ├── data │ │ │ │ ├── nf10_upb_dummy_port_v2_1_0.pao │ │ │ │ └── nf10_upb_dummy_port_v2_1_0.mpd │ │ │ └── hdl │ │ │ │ └── verilog │ │ │ │ └── nf10_upb_dummy_port.v │ │ │ ├── nf10_upb_chipscope_icon_v1_00_a │ │ │ ├── data │ │ │ │ ├── nf10_upb_chipscope_icon_v2_1_0.pao │ │ │ │ ├── nf10_upb_chipscope_icon_v2_1_0.bbd │ │ │ │ └── nf10_upb_chipscope_icon_v2_1_0.mpd │ │ │ └── xco │ │ │ │ ├── chipscope_icon_1_ports.xco │ │ │ │ ├── chipscope_icon_2_ports.xco │ │ │ │ ├── chipscope_icon_3_ports.xco │ │ │ │ ├── chipscope_icon_4_ports.xco │ │ │ │ ├── chipscope_icon_5_ports.xco │ │ │ │ └── chipscope_icon_6_ports.xco │ │ │ └── nf10_upb_clock_generator_v1_00_a │ │ │ ├── data │ │ │ ├── nf10_upb_clock_generator_v2_1_0.pao │ │ │ └── nf10_upb_clock_generator_v2_1_0.mpd │ │ │ └── testbench │ │ │ └── nf10_upb_clock_generator_tb.v │ ├── xilinx │ │ └── pcores │ │ │ ├── diff_input_buf_v1_00_a │ │ │ ├── data │ │ │ │ ├── diff_input_buf_v2_1_0.pao │ │ │ │ └── diff_input_buf_v2_1_0.mpd │ │ │ └── hdl │ │ │ │ └── vhdl │ │ │ │ └── diff_input_buf.vhd │ │ │ ├── axi_gpio_v1_01_b │ │ │ └── Makefile │ │ │ └── axi_interconnect_v1_05_a │ │ │ └── Makefile │ └── std │ │ └── pcores │ │ └── nf10_mdio_v1_00_a │ │ ├── data │ │ └── nf10_mdio_v2_1_0.pao │ │ └── Makefile └── sw │ └── contrib │ └── drivers │ ├── nf10_upb_dma_v1_00_a │ ├── src │ │ ├── nic_driver │ │ │ ├── nf10config.h │ │ │ ├── nf10iface.h │ │ │ ├── nf10priv.h │ │ │ ├── nf10fops.h │ │ │ └── Makefile │ │ ├── flashprog │ │ │ ├── xparameters.h │ │ │ ├── reg_lib.h │ │ │ ├── Makefile │ │ │ └── reg_lib.c │ │ └── apps │ │ │ └── Makefile │ └── Makefile │ └── nf10_upb_sdn_dataplane_v1_00_a │ ├── src │ ├── libsdn_dataplane │ │ ├── sdn_dp_cwrapper.hpp │ │ ├── errors.h │ │ ├── errors.hpp │ │ ├── logging.hpp │ │ ├── poll_thread.cpp │ │ ├── errors.inc │ │ ├── config_port_associations.cpp │ │ ├── hw_flow.hpp │ │ ├── logging.cpp │ │ ├── config_fpga_addresses.hpp │ │ ├── poll_thread.hpp │ │ ├── config_platform_flash.hpp │ │ ├── errors.cpp │ │ └── hw_flow_table_base.hpp │ └── sdntest │ │ ├── sdntest.hpp │ │ └── Makefile │ └── Makefile ├── contrib-projects ├── upb_l2switch │ ├── sw │ │ ├── rdaxi │ │ ├── stats │ │ ├── wraxi │ │ ├── nf10.ko │ │ ├── ael2005_conf │ │ ├── nf10_configure │ │ ├── nf10_flash_a │ │ └── nf10_flash_b │ └── hw │ │ ├── nf10 │ │ └── bitgen.ut │ │ └── system.xmp └── upb_openflowswitch │ ├── sw │ ├── rdaxi │ ├── stats │ ├── wraxi │ ├── nf10.ko │ ├── ael2005_conf │ ├── nf10_flash_a │ ├── nf10_flash_b │ └── nf10_configure │ └── hw │ ├── nf10 │ └── bitgen.ut │ └── system.xmp ├── docs └── documentation.pdf └── README.md /lib/hw/contrib/pcores/nf10_upb_ofswitch_v1_00_a/prj/nf10_upb_ofswitch.sdc: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_switch_v1_00_a/data/nf10_upb_switch_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_dma_v1_00_a/hdl/verilog/xilinx/README: -------------------------------------------------------------------------------- 1 | This is a place holder. 2 | -------------------------------------------------------------------------------- /contrib-projects/upb_l2switch/sw/rdaxi: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/rdaxi -------------------------------------------------------------------------------- /contrib-projects/upb_l2switch/sw/stats: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/stats -------------------------------------------------------------------------------- /contrib-projects/upb_l2switch/sw/wraxi: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/wraxi -------------------------------------------------------------------------------- /contrib-projects/upb_l2switch/sw/nf10.ko: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/nf10.ko -------------------------------------------------------------------------------- /contrib-projects/upb_openflowswitch/sw/rdaxi: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/rdaxi -------------------------------------------------------------------------------- /contrib-projects/upb_openflowswitch/sw/stats: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/stats -------------------------------------------------------------------------------- /contrib-projects/upb_openflowswitch/sw/wraxi: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/wraxi -------------------------------------------------------------------------------- /docs/documentation.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pc2/NetFPGA-10G-UPB-OpenFlow/HEAD/docs/documentation.pdf -------------------------------------------------------------------------------- /contrib-projects/upb_openflowswitch/sw/nf10.ko: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/nf10.ko -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_dma_v1_00_a/data/nf10_upb_dma_v2_1_0.bbd: -------------------------------------------------------------------------------- 1 | FILES 2 | chipscope_ila_128.ngc 3 | 4 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_switch_v1_00_a/data/nf10_upb_switch_v2_1_0.bbd: -------------------------------------------------------------------------------- 1 | FILES 2 | nf10_upb_switch.edf 3 | -------------------------------------------------------------------------------- /contrib-projects/upb_l2switch/sw/ael2005_conf: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/ael2005_conf -------------------------------------------------------------------------------- /contrib-projects/upb_l2switch/sw/nf10_configure: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/nf10_configure -------------------------------------------------------------------------------- /contrib-projects/upb_l2switch/sw/nf10_flash_a: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/nf10_flash_a -------------------------------------------------------------------------------- /contrib-projects/upb_l2switch/sw/nf10_flash_b: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/nf10_flash_b -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_ofswitch_v1_00_a/data/nf10_upb_ofswitch_v2_1_0.bbd: -------------------------------------------------------------------------------- 1 | FILES 2 | nf10_upb_ofswitch.edf 3 | -------------------------------------------------------------------------------- /contrib-projects/upb_openflowswitch/sw/ael2005_conf: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/ael2005_conf -------------------------------------------------------------------------------- /contrib-projects/upb_openflowswitch/sw/nf10_flash_a: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/nf10_flash_a -------------------------------------------------------------------------------- /contrib-projects/upb_openflowswitch/sw/nf10_flash_b: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/nf10_flash_b -------------------------------------------------------------------------------- /contrib-projects/upb_openflowswitch/sw/nf10_configure: -------------------------------------------------------------------------------- 1 | ../../../lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/bin/nf10_configure -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_10g_interface_v1_00_a/data/nf10_upb_10g_interface_v2_1_0.bbd: -------------------------------------------------------------------------------- 1 | FILES 2 | xgmac.ngc, xaui.ngc 3 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_interconnect_v1_00_a/data/nf10_upb_interconnect_v2_1_0.bbd: -------------------------------------------------------------------------------- 1 | FILES 2 | nf10_upb_interconnect.edf 3 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_dma_v1_00_a/netlist/chipscope_ila_128.ngc: -------------------------------------------------------------------------------- 1 | ../../nf10_upb_chipscope_icon_v1_00_a/netlist/chipscope_ila_128.ngc -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_axi_lite_chipscope_v1_00_a/netlist/chipscope_ila_256.ngc: -------------------------------------------------------------------------------- 1 | ../../nf10_upb_chipscope_icon_v1_00_a/netlist/chipscope_ila_256.ngc -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_axi_stream_chipscope_v1_00_a/netlist/chipscope_ila_512.ngc: -------------------------------------------------------------------------------- 1 | ../../nf10_upb_chipscope_icon_v1_00_a/netlist/chipscope_ila_512.ngc -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/prj/nf10_upb_input_arbiter.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.666 [get_ports clk] 2 | derive_pll_clocks 3 | 4 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/src/nic_driver/nf10config.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #define VPORTS 7 // provide 7 virtual ports (nf10xv0..nf10xv5 + nf10x0) 4 | 5 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_lib/hdl/SystemVerilog/axis_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pc2/NetFPGA-10G-UPB-OpenFlow/HEAD/lib/hw/contrib/pcores/nf10_upb_lib/hdl/SystemVerilog/axis_if.v -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_lib/hdl/SystemVerilog/secded.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pc2/NetFPGA-10G-UPB-OpenFlow/HEAD/lib/hw/contrib/pcores/nf10_upb_lib/hdl/SystemVerilog/secded.v -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_lib/hdl/SystemVerilog/qdr2_sram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pc2/NetFPGA-10G-UPB-OpenFlow/HEAD/lib/hw/contrib/pcores/nf10_upb_lib/hdl/SystemVerilog/qdr2_sram.v -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/hdl/verilog/nf10_upb_input_arbiter_tb.prj: -------------------------------------------------------------------------------- 1 | verilog work "nf10_upb_input_arbiter_flex.v" 2 | verilog work "nf10_upb_input_arbiter_tb.v" 3 | 4 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_lib/hdl/SystemVerilog/tkeep_coder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pc2/NetFPGA-10G-UPB-OpenFlow/HEAD/lib/hw/contrib/pcores/nf10_upb_lib/hdl/SystemVerilog/tkeep_coder.v -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/testbench/main_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pc2/NetFPGA-10G-UPB-OpenFlow/HEAD/lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/testbench/main_tb.v -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/src/flashprog/xparameters.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #define XPAR_AXI_EMC_0_S_AXI_MEM0_BASEADDR 0x80000000 4 | #define XPAR_AXI_CFG_FPGA_0_BASEADDR 0x40000000 5 | 6 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/prj/qdr2_test_netfpga/main.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pc2/NetFPGA-10G-UPB-OpenFlow/HEAD/lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/prj/qdr2_test_netfpga/main.v -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/testbench/CY7C1515JV18.vhd.patch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pc2/NetFPGA-10G-UPB-OpenFlow/HEAD/lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/testbench/CY7C1515JV18.vhd.patch -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_lib/prj/upb_packet_fifo_dev/nf10_upb_packet_fifo.ucf: -------------------------------------------------------------------------------- 1 | 2 | #Created by Constraints Editor (xc5vtx240t-ff1759-2) - 2014/02/26 3 | NET "CLK" TNM_NET = CLK; 4 | TIMESPEC TS_CLK = PERIOD "CLK" 180 MHz HIGH 50%; 5 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_interconnect_v1_00_a/prj/synplify/interconnect.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.666 [get_ports axi_aclk] 2 | create_clock -period 8.000 [get_ports GTXD8_P] 3 | create_clock -period 50.000 [get_ports INIT_CLK] 4 | derive_pll_clocks 5 | 6 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/data/nf10_upb_input_arbiter_v2_1_0.bbd: -------------------------------------------------------------------------------- 1 | FILES 2 | 4_ports/nf10_upb_input_arbiter.edf, 5_ports/nf10_upb_input_arbiter.edf, 6_ports/nf10_upb_input_arbiter.edf, 7_ports/nf10_upb_input_arbiter.edf, 8_ports/nf10_upb_input_arbiter.edf 3 | 4 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_switch_v1_00_a/prj/nf10_upb_switch.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 150MHz [get_ports clk] 2 | create_generated_clock -source [get_ports clk] -multiply_by 2 [get_ports clk2x] 3 | create_generated_clock -source [get_ports clk] -multiply_by 2 -phase 90 [get_ports clk2x90] 4 | derive_pll_clocks -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/testbench/README: -------------------------------------------------------------------------------- 1 | 2 | A VHDL functional model of the CY7C1515JV18 can be downloaded at: 3 | 4 | http://www.cypress.com/?rID=17142 5 | 6 | (filename CY7C1515JV18.zip). Apply the patch CY7C1515JV18.vhd.patch to accurately simulate the QDR2-SRAM. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /contrib-projects/upb_l2switch/hw/nf10/bitgen.ut: -------------------------------------------------------------------------------- 1 | -g TdoPin:PULLNONE 2 | -g DriveDone:No 3 | -g StartUpClk:CCLK 4 | -g DONE_cycle:4 5 | -g GTS_cycle:5 6 | -g TckPin:PULLUP 7 | -g TdiPin:PULLUP 8 | -g TmsPin:PULLUP 9 | -g DonePipe:No 10 | -g GWE_cycle:6 11 | -g LCK_cycle:NoWait 12 | -g Security:NONE 13 | -g Persist:No 14 | -g Match_cycle:NoWait 15 | -g unusedpin:pullnone 16 | -------------------------------------------------------------------------------- /contrib-projects/upb_openflowswitch/hw/nf10/bitgen.ut: -------------------------------------------------------------------------------- 1 | -g TdoPin:PULLNONE 2 | -g DriveDone:No 3 | -g StartUpClk:CCLK 4 | -g DONE_cycle:4 5 | -g GTS_cycle:5 6 | -g TckPin:PULLUP 7 | -g TdiPin:PULLUP 8 | -g TmsPin:PULLUP 9 | -g DonePipe:No 10 | -g GWE_cycle:6 11 | -g LCK_cycle:NoWait 12 | -g Security:NONE 13 | -g Persist:No 14 | -g Match_cycle:NoWait 15 | -g unusedpin:pullnone 16 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/hdl/verilog/nf10_upb_input_arbiter_tb.sh: -------------------------------------------------------------------------------- 1 | cd $(dirname $0) 2 | rm -rf unittest_build 3 | mkdir unittest_build 4 | cd unittest_build 5 | fuse -incremental -prj ../nf10_upb_input_arbiter_tb.prj -o nf10_upb_input_arbiter_tb.exe work.nf10_upb_input_arbiter_tb 6 | ./nf10_upb_input_arbiter_tb.exe -tclbatch ../nf10_upb_input_arbiter_tb.tcl 7 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_switch_v1_00_a/Makefile: -------------------------------------------------------------------------------- 1 | install: synthesize 2 | 3 | synthesize: netlist/nf10_upb_switch.edf 4 | 5 | netlist/nf10_upb_switch.edf: hdl/SystemVerilog/*.v 6 | cd prj && $(SYNPLIFY_CMD) -batch nf10_upb_switch.prj 7 | @mkdir -p netlist 8 | @cp prj/nf10_upb_switch.edf netlist/ 9 | 10 | hdl/SystemVerilog/%.v: 11 | 12 | clean: 13 | -rm -rf netlist 14 | 15 | .INTERMEDIATE: synthesize 16 | .PHONY: clean 17 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue_2.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.666 [get_ports clk] 2 | create_generated_clock -source [get_ports clk] -multiply_by 2 [get_ports clk2x] 3 | create_generated_clock -source [get_ports clk] -multiply_by 2 -phase 90 [get_ports clk2x90] 4 | create_clock -period 6.666 [get_ports m_axis_0_clk] 5 | create_clock -period 6.666 [get_ports m_axis_1_clk] 6 | derive_pll_clocks 7 | 8 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue_3.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.666 [get_ports clk] 2 | create_generated_clock -source [get_ports clk] -multiply_by 2 [get_ports clk2x] 3 | create_generated_clock -source [get_ports clk] -multiply_by 2 -phase 90 [get_ports clk2x90] 4 | create_clock -period 6.666 [get_ports m_axis_0_clk] 5 | create_clock -period 6.666 [get_ports m_axis_1_clk] 6 | create_clock -period 6.666 [get_ports m_axis_2_clk] 7 | derive_pll_clocks 8 | 9 | -------------------------------------------------------------------------------- /lib/hw/xilinx/pcores/diff_input_buf_v1_00_a/data/diff_input_buf_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## File : DIFF_OUTPUT_BUF_v2_1_0.pao 4 | ## Desc : Peripheral Analysis Order 5 | ## : Automatically generated by Import Peripheral Wizard 6 | ## 7 | ## Created : Wed May 26 21:17:54 2004 8 | ## 9 | ################################################################################ 10 | 11 | lib diff_input_buf_v1_00_a diff_input_buf 12 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue_4.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.666 [get_ports clk] 2 | create_generated_clock -source [get_ports clk] -multiply_by 2 [get_ports clk2x] 3 | create_generated_clock -source [get_ports clk] -multiply_by 2 -phase 90 [get_ports clk2x90] 4 | create_clock -period 6.666 [get_ports m_axis_0_clk] 5 | create_clock -period 6.666 [get_ports m_axis_1_clk] 6 | create_clock -period 6.666 [get_ports m_axis_2_clk] 7 | create_clock -period 6.666 [get_ports m_axis_3_clk] 8 | derive_pll_clocks 9 | 10 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue_5.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.666 [get_ports clk] 2 | create_generated_clock -source [get_ports clk] -multiply_by 2 [get_ports clk2x] 3 | create_generated_clock -source [get_ports clk] -multiply_by 2 -phase 90 [get_ports clk2x90] 4 | create_clock -period 6.666 [get_ports m_axis_0_clk] 5 | create_clock -period 6.666 [get_ports m_axis_1_clk] 6 | create_clock -period 6.666 [get_ports m_axis_2_clk] 7 | create_clock -period 6.666 [get_ports m_axis_3_clk] 8 | create_clock -period 6.666 [get_ports m_axis_4_clk] 9 | derive_pll_clocks 10 | 11 | -------------------------------------------------------------------------------- /contrib-projects/upb_l2switch/hw/system.xmp: -------------------------------------------------------------------------------- 1 | #Please do not modify this file by hand 2 | XmpVersion: 14.7 3 | VerMgmt: 14.7 4 | IntStyle: default 5 | Flow: ise 6 | ModuleSearchPath: ../../../lib/hw 7 | MHS File: system.mhs 8 | Architecture: virtex5 9 | Device: xc5vtx240t 10 | Package: ff1759 11 | SpeedGrade: -2 12 | UserCmd1: 13 | UserCmd1Type: 0 14 | UserCmd2: 15 | UserCmd2Type: 0 16 | GenSimTB: 0 17 | SdkExportBmmBit: 1 18 | SdkExportDir: SDK/SDK_Export 19 | InsertNoPads: 0 20 | WarnForEAArch: 1 21 | HdlLang: VHDL 22 | SimModel: BEHAVIORAL 23 | ExternalMemSim: 0 24 | UcfFile: data/system.ucf 25 | EnableParTimingError: 0 26 | ShowLicenseDialog: 1 27 | BInfo: 28 | -------------------------------------------------------------------------------- /contrib-projects/upb_openflowswitch/hw/system.xmp: -------------------------------------------------------------------------------- 1 | #Please do not modify this file by hand 2 | XmpVersion: 14.7 3 | VerMgmt: 14.7 4 | IntStyle: default 5 | Flow: ise 6 | ModuleSearchPath: ../../../lib/hw 7 | MHS File: system.mhs 8 | Architecture: virtex5 9 | Device: xc5vtx240t 10 | Package: ff1759 11 | SpeedGrade: -2 12 | UserCmd1: 13 | UserCmd1Type: 0 14 | UserCmd2: 15 | UserCmd2Type: 0 16 | GenSimTB: 0 17 | SdkExportBmmBit: 1 18 | SdkExportDir: SDK/SDK_Export 19 | InsertNoPads: 0 20 | WarnForEAArch: 1 21 | HdlLang: VHDL 22 | SimModel: BEHAVIORAL 23 | ExternalMemSim: 0 24 | UcfFile: data/system.ucf 25 | EnableParTimingError: 0 26 | ShowLicenseDialog: 1 27 | BInfo: 28 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_ofswitch_v1_00_a/hdl/SystemVerilog/tuple_t.v: -------------------------------------------------------------------------------- 1 | typedef struct packed { 2 | logic valid; // 243 3 | logic[2:0] port; // 242:240 4 | logic[2:0] vport; // 239:237 5 | logic[47:0] dmac; // 236:189 6 | logic[47:0] smac; // 188:141 7 | logic[15:0] typ; // 140:125 8 | logic[11:0] vid; // 124:113 - little endian !!! 9 | logic[2:0] pcp; // 112:110 10 | logic[31:0] sip; // 109:78 11 | logic[31:0] dip; // 77:46 12 | logic[7:0] prot; // 45:38 13 | logic[5:0] tos; // 37:32 14 | logic[15:0] tsp; // 31:16 15 | logic[15:0] tdp; // 15:0 16 | } tuple_t; 17 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue_6.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.666 [get_ports clk] 2 | create_generated_clock -source [get_ports clk] -multiply_by 2 [get_ports clk2x] 3 | create_generated_clock -source [get_ports clk] -multiply_by 2 -phase 90 [get_ports clk2x90] 4 | create_clock -period 6.666 [get_ports m_axis_0_clk] 5 | create_clock -period 6.666 [get_ports m_axis_1_clk] 6 | create_clock -period 6.666 [get_ports m_axis_2_clk] 7 | create_clock -period 6.666 [get_ports m_axis_3_clk] 8 | create_clock -period 6.666 [get_ports m_axis_4_clk] 9 | create_clock -period 6.666 [get_ports m_axis_5_clk] 10 | derive_pll_clocks 11 | 12 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue_7.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 6.666 [get_ports clk] 2 | create_generated_clock -source [get_ports clk] -multiply_by 2 [get_ports clk2x] 3 | create_generated_clock -source [get_ports clk] -multiply_by 2 -phase 90 [get_ports clk2x90] 4 | create_clock -period 6.666 [get_ports m_axis_0_clk] 5 | create_clock -period 6.666 [get_ports m_axis_1_clk] 6 | create_clock -period 6.666 [get_ports m_axis_2_clk] 7 | create_clock -period 6.666 [get_ports m_axis_3_clk] 8 | create_clock -period 6.666 [get_ports m_axis_4_clk] 9 | create_clock -period 6.666 [get_ports m_axis_5_clk] 10 | create_clock -period 6.666 [get_ports m_axis_6_clk] 11 | derive_pll_clocks 12 | 13 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_ofswitch_v1_00_a/hdl/SystemVerilog/statistics_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module statistics_tb; 3 | reg clk=0; 4 | reg we=0; 5 | reg[15:0] addr=1024; 6 | reg[15:0] raddr=1024; 7 | wire[31:0] rdata; 8 | statistics uut( 9 | .clk(clk), 10 | .addr(addr), 11 | .we(we), 12 | .din(1), 13 | .reset(0), 14 | .rclk(clk), 15 | .raddr(raddr), 16 | .rdata(rdata) 17 | ); 18 | 19 | always @(posedge clk) begin 20 | we <= ~we; 21 | end 22 | initial begin 23 | #1000 24 | addr = 42; 25 | #400 26 | @(posedge clk) raddr = 42; 27 | end 28 | always 29 | #5 clk = ~clk; 30 | endmodule 31 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_ofswitch_v1_00_a/hdl/SystemVerilog/parameters.v: -------------------------------------------------------------------------------- 1 | parameter C_IN_PORT_WIDTH = 3; 2 | parameter C_NUM_INPUTS = 2**C_IN_PORT_WIDTH; 3 | parameter C_OUT_PORT_WIDTH = 8; 4 | parameter C_AXIS_TDATA_WIDTH = 256; 5 | parameter C_AXIS_TKEEP_WIDTH = 32; 6 | parameter C_PACKET_LENGTH_WIDTH = 14; 7 | parameter C_MATCH_ADDR_WIDTH = 12; // "4096 Flows ought to be enough for anybody." --nobody, ever 8 | // Make sure this is enough to hold all flow table entries, 9 | // but remember that statistics ram will be scaled to hold 10 | // statistics for 2**C_MATCH_ADDR_WIDTH entries. 11 | parameter C_COUNTER_WIDTH = 32; // Have a look at statistics_ram.v before changeing this 12 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_interconnect_v1_00_a/hdl/verilog/aurora/aurora_8b10b_v5_3_reset_logic.patch: -------------------------------------------------------------------------------- 1 | DISCLAIMER NOTICE 2 | We are not affiliated, associated, authorized, endorsed by, or in any 3 | way officially connected with Xilinx, Inc. or any of its subsidiaries or 4 | its affiliates. In no event whatsoever shall Xilinx, Inc. or any of its 5 | subsidiaries or its affiliates have any warranty or support commitment 6 | for this software or liability for loss, injury or damage in connection 7 | with this software, including but not limited to the use or display 8 | thereof. 9 | --- 10 | 123,128c123 11 | < // Assign an IBUFG to INIT_CLK 12 | < IBUFG init_clk_ibufg_i 13 | < ( 14 | < .I(INIT_CLK), 15 | < .O(init_clk_i) 16 | < ); 17 | --- 18 | > assign init_clk_i = INIT_CLK; 19 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_switch_v1_00_a/hdl/SystemVerilog/ram.v: -------------------------------------------------------------------------------- 1 | module ram 2 | #( 3 | parameter RAM_WIDTH = 310, 4 | parameter RAM_ADDR_BITS = 3 5 | ) 6 | ( 7 | input [RAM_ADDR_BITS-1:0] addrA, 8 | input [RAM_ADDR_BITS-1:0] addrB, 9 | input [RAM_WIDTH-1:0] dinA, 10 | input enA, 11 | input wr_enA, 12 | input enB, 13 | input clk, 14 | output reg [RAM_WIDTH-1:0] doutA=0, doutB=0 15 | ); 16 | reg [RAM_WIDTH-1:0] data [(2**RAM_ADDR_BITS)-1:0]; 17 | reg [RAM_ADDR_BITS-1:0] k; 18 | initial begin 19 | for (k=0; k < (2**RAM_ADDR_BITS)-1; k = k+1) begin 20 | data[k]=0; 21 | end 22 | end 23 | always @(posedge clk) begin 24 | if (enA) begin 25 | if (wr_enA) data[addrA] <= dinA; 26 | doutA <= data[addrA]; 27 | end 28 | if (enB) doutB <= data[addrB]; 29 | end 30 | endmodule 31 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_dma_input_v1_00_a/data/nf10_upb_dma_input_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | ## Filename: /home/lass/NetFPGA-10G-live-clean/lib/hw/contrib/pcores/MyProcessorIPLib/pcores/nf10_upb_dma_input_v1_00_a/data/nf10_upb_dma_input_v2_1_0.pao 3 | ## Description: Peripheral Analysis Order 4 | ## Date: Tue May 27 13:31:51 2014 (by Create and Import Peripheral Wizard) 5 | ############################################################################## 6 | 7 | lib nf10_upb_dma_input_v1_00_a dma_input verilog 8 | lib nf10_upb_dma_input_v1_00_a ../../../nf10_upb_lib/hdl/verilog/nf10_upb_packet_fifo verilog 9 | lib nf10_upb_dma_input_v1_00_a ../../../nf10_upb_10g_input_v1_00_a/hdl/verilog/width_divider verilog 10 | lib nf10_upb_dma_input_v1_00_a ../../../nf10_upb_10g_input_v1_00_a/hdl/verilog/width_multiplier verilog 11 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_10g_input_v1_00_a/data/nf10_upb_10g_input_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | ## Filename: /home/tloecke/pgotfnetworking-netfpga/contrib-projects/upb_loopback/hw/pcores/nf10_upb_10g_input_v1_00_a/data/nf10_upb_10g_input_v2_1_0.pao 3 | ## Description: Peripheral Analysis Order 4 | ## Date: Wed Mar 26 14:24:33 2014 (by Create and Import Peripheral Wizard) 5 | ############################################################################## 6 | 7 | lib nf10_upb_10g_input_v1_00_a nf10_upb_10g_input verilog 8 | lib nf10_upb_10g_input_v1_00_a width_divider verilog 9 | lib nf10_upb_10g_input_v1_00_a ../../../nf10_upb_lib/hdl/verilog/flow_ctrl verilog 10 | lib nf10_upb_10g_input_v1_00_a width_multiplier verilog 11 | lib nf10_upb_10g_input_v1_00_a AsyncWidthConverter verilog 12 | lib nf10_upb_10g_input_v1_00_a ../../../nf10_upb_lib/hdl/verilog/nf10_upb_packet_fifo verilog 13 | -------------------------------------------------------------------------------- /lib/hw/xilinx/pcores/diff_input_buf_v1_00_a/data/diff_input_buf_v2_1_0.mpd: -------------------------------------------------------------------------------- 1 | ################################################################### 2 | ## 3 | ## File : diff_input_buf_v2_1_0.mpd 4 | ## Desc : Microprocessor Peripheral Description 5 | ## : Automatically generated by PsfUtility 6 | ## 7 | ## Created : Wed May 26 21:17:54 2004 8 | ## 9 | ################################################################### 10 | 11 | BEGIN diff_input_buf 12 | 13 | ## Peripheral Options 14 | OPTION IPTYPE = PERIPHERAL 15 | OPTION IMP_NETLIST = TRUE 16 | OPTION HDL = VHDL 17 | OPTION IP_GROUP = 'Clock, Reset and Interrupt:MICROBLAZE:PPC' 18 | OPTION DESC = Differential Clock Input Buffer 19 | OPTION LONG_DESC = 'Differential Clock Input Buffer' 20 | 21 | 22 | ## Bus Interfaces 23 | 24 | ## Generics for VHDL or Parameters for Verilog 25 | 26 | ## Ports 27 | PORT SINGLE_ENDED_INPUT = "", DIR = O 28 | PORT DIFF_INPUT_P = "", DIR = I, IOB_STATE=BUF 29 | PORT DIFF_INPUT_N = "", DIR = I, IOB_STATE=BUF 30 | 31 | END 32 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/Makefile: -------------------------------------------------------------------------------- 1 | install: synthesize 2 | 3 | unittest: 4 | hdl/verilog/nf10_upb_input_arbiter_tb.sh 5 | 6 | synthesize: netlist/4_ports/nf10_upb_input_arbiter.edf netlist/5_ports/nf10_upb_input_arbiter.edf netlist/6_ports/nf10_upb_input_arbiter.edf netlist/7_ports/nf10_upb_input_arbiter.edf netlist/8_ports/nf10_upb_input_arbiter.edf 7 | 8 | netlist/%_ports/nf10_upb_input_arbiter.edf: prj/nf10_upb_input_arbiter_%.prj hdl/verilog/*.v 9 | cd prj && $(SYNPLIFY_CMD) -batch ../$< 10 | 11 | hdl/verilog/%.v: 12 | 13 | 14 | clean: 15 | rm -rf hdl/verilog/unittest_build 16 | rm -rf netlist 17 | -find prj/* ! -name "arbiter.xise" ! -name "nf10_upb_input_arbiter.sdc" ! -name "nf10_upb_input_arbiter_4.prj" ! -name "nf10_upb_input_arbiter_5.prj" ! -name "nf10_upb_input_arbiter_6.prj" ! -name "nf10_upb_input_arbiter_7.prj" ! -name "nf10_upb_input_arbiter_8.prj" ! -exec rm -rf {} \; | true 18 | 19 | all: unittest install 20 | 21 | .PHONY: unittest clean 22 | .INTERMEDIATE: synthesize 23 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_dma_v1_00_a/prj/dma_engine.sdc: -------------------------------------------------------------------------------- 1 | # Synopsys, Inc. constraint file 2 | # /home/bevan/pgotfnetworking-netfpga/lib/hw/contrib/pcores/upb_dma_v1_00_a/prj/dma_engine.sdc 3 | # Written on Mon Mar 17 22:42:46 2014 4 | # by Synplify Premier with Design Planner, G-2012.09-SP1 Scope Editor 5 | 6 | # 7 | # Collections 8 | # 9 | 10 | # 11 | # Clocks 12 | # 13 | define_clock {pcie_clk} -name {pcie_clk} -freq 125 -clockgroup default_clkgroup_0 14 | define_clock {axi_clk} -name {axi_clk} -freq 100 -clockgroup default_clkgroup_1 15 | define_clock {tx_clk} -name {tx_clk} -freq 160 -clockgroup default_clkgroup_2 16 | define_clock {rx_clk} -name {rx_clk} -freq 160 -clockgroup default_clkgroup_3 17 | 18 | # 19 | # Clock to Clock 20 | # 21 | 22 | # 23 | # Inputs/Outputs 24 | # 25 | 26 | # 27 | # Registers 28 | # 29 | 30 | # 31 | # Delay Paths 32 | # 33 | 34 | # 35 | # Attributes 36 | # 37 | 38 | # 39 | # I/O Standards 40 | # 41 | 42 | # 43 | # Compile Points 44 | # 45 | 46 | # 47 | # Other 48 | # 49 | derive_pll_clocks 50 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_10g_interface_v1_00_a/hdl/verilog/xilinx/cc_2b_1skp.diff: -------------------------------------------------------------------------------- 1 | DISCLAIMER NOTICE 2 | We are not affiliated, associated, authorized, endorsed by, or in any 3 | way officially connected with Xilinx, Inc. or any of its subsidiaries or 4 | its affiliates. In no event whatsoever shall Xilinx, Inc. or any of its 5 | subsidiaries or its affiliates have any warranty or support commitment 6 | for this software or liability for loss, injury or damage in connection 7 | with this software, including but not limited to the use or display 8 | thereof. 9 | --- 10 | 172,173c172,174 11 | < reg [3:0] reset_rxrecclk_r = 4'b1111 /* synthesis syn_srlstyle = "registers" */ ; 12 | < reg [3:0] reset_rxusrclk2_r = 4'b1111 /* synthesis syn_srlstyle = "registers" */ ; 13 | --- 14 | > // Modified by James to workaround timing issue 15 | > reg [3:0] reset_rxrecclk_r = 4'b1111 /* synthesis syn_srlstyle = "registers" syn_maxfan = 10*/ ; 16 | > reg [3:0] reset_rxusrclk2_r = 4'b1111 /* synthesis syn_srlstyle = "registers" syn_maxfan = 10*/ ; 17 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_ofswitch_v1_00_a/Makefile: -------------------------------------------------------------------------------- 1 | .NOTPARALLEL: # coregen cannot be run in parallel in the same directory (same tmp filenames) 2 | 3 | install: synthesize 4 | 5 | cores: prj/ipcore_dir/action_fifo.ngc prj/ipcore_dir/fifo.ngc 6 | 7 | prj/ipcore_dir/action_fifo.ngc: prj/action_fifo.xco 8 | mkdir -p prj/ipcore_dir/ 9 | cd prj/ipcore_dir/ && coregen -b ../action_fifo.xco 10 | 11 | prj/ipcore_dir/fifo.ngc: prj/fifo.xco 12 | mkdir -p prj/ipcore_dir/ 13 | cd prj/ipcore_dir/ && coregen -b ../fifo.xco 14 | 15 | %.xco: 16 | 17 | %.v: 18 | 19 | 20 | synthesize: netlist/nf10_upb_ofswitch.edf 21 | 22 | netlist/nf10_upb_ofswitch.edf: cores hdl/SystemVerilog/*.v 23 | cd prj && $(SYNPLIFY_CMD) -batch nf10_upb_ofswitch.prj 24 | @mkdir -p netlist 25 | cp prj/nf10_upb_ofswitch.edf netlist/ 26 | 27 | all: install 28 | 29 | clean: 30 | -rm -rf netlist 31 | -rm prj/nf10_upb_ofswitch.edf 32 | -rm prj/ipcore_dir/action_fifo.ngc 33 | -rm prj/ipcore_dir/action_fifo.v 34 | -rm prj/ipcore_dir/fifo.ngc 35 | -rm prj/ipcore_dir/fifo.v 36 | 37 | .PHONY: clean 38 | 39 | .INTERMEDIATE: synthesize cores 40 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_ofswitch_v1_00_a/doc/README.md: -------------------------------------------------------------------------------- 1 | # Userspace tools 2 | 3 | These tools are provided to ease human interaction 4 | with the OpenFlow core for debugging purposes. 5 | Be aware that they are not thoroughly tested and read 6 | them carefully before execution. 7 | 8 | ####clear_cam.py 9 | The clear_cam.py script takes the device node of a NetFPGA card as parameter and deletes 10 | all contents from the CAM. 11 | 12 | --- 13 | ####tuple_calculator.py 14 | The tuple_calculator.py script opens an interactive shell which provides functions to cre- 15 | ate tuple bitstrings and hash these according to the same polynomial as the lookup engine. It 16 | also is able to generate shell commands to write tuples to the CAM of a connected NetFPGA 17 | card. 18 | 19 | --- 20 | ####cam_switch.py 21 | The cam_switch.py script takes as arguments a list of the NetFPGA’s virtual interfaces. It 22 | generates CAM entries for packets it receives which are broadcasted if it does not know the 23 | destination of a packet. The MAC addresses which are used to forward packets to the correct 24 | port are hardcoded in the script. -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/libsdn_dataplane/sdn_dp_cwrapper.hpp: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | * 6 | * Project Group "On-the-Fly Networking for Big Data" 7 | * SFB 901 "On-The-Fly Computing" 8 | * 9 | * University of Paderborn 10 | * Computer Engineering Group 11 | * Pohlweg 47 - 49 12 | * 33098 Paderborn 13 | * Germany 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the "License"); 16 | * you may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #pragma once 29 | 30 | namespace upb { 31 | 32 | 33 | 34 | } 35 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_axi_lite_chipscope_v1_00_a/data/nf10_upb_axi_lite_chipscope_v2_1_0.bbd: -------------------------------------------------------------------------------- 1 | # UPB AXI-4 Lite ChipScope core 2 | # 3 | # Copyright (c) 2014, 2015 Jörg Niklas 4 | # osjsn@niklasfamily.de 5 | # 6 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 7 | # 8 | # Project Group "On-the-Fly Networking for Big Data" 9 | # SFB 901 "On-The-Fly Computing" 10 | # 11 | # University of Paderborn 12 | # Computer Engineering Group 13 | # Pohlweg 47 - 49 14 | # 33098 Paderborn 15 | # Germany 16 | # 17 | # 18 | # This file is free code: you can redistribute it and/or modify it under 19 | # the terms of the GNU Lesser General Public License version 2.1 as 20 | # published by the Free Software Foundation. 21 | # 22 | # This file is distributed in the hope that it will be useful, 23 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 24 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 | # GNU Lesser General Public License for more details. 26 | # 27 | # You should have received a copy of the GNU Lesser General Public License 28 | # along with this project. If not, see . 29 | # 30 | 31 | FILES 32 | chipscope_ila_256.ngc 33 | 34 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_dummy_port_v1_00_a/data/nf10_upb_dummy_port_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | # 2 | # UPB Dummy Port core 3 | # 4 | # Copyright (c) 2014, 2015 Jörg Niklas 5 | # osjsn@niklasfamily.de 6 | # 7 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 8 | # 9 | # Project Group "On-the-Fly Networking for Big Data" 10 | # SFB 901 "On-The-Fly Computing" 11 | # 12 | # University of Paderborn 13 | # Computer Engineering Group 14 | # Pohlweg 47 - 49 15 | # 33098 Paderborn 16 | # Germany 17 | # 18 | # 19 | # This file is free code: you can redistribute it and/or modify it under 20 | # the terms of the GNU Lesser General Public License version 2.1 as 21 | # published by the Free Software Foundation. 22 | # 23 | # This file is distributed in the hope that it will be useful, 24 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 25 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 | # GNU Lesser General Public License for more details. 27 | # 28 | # You should have received a copy of the GNU Lesser General Public License 29 | # along with this project. If not, see . 30 | # 31 | 32 | lib nf10_upb_dummy_port_v1_00_a nf10_upb_dummy_port 33 | 34 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_chipscope_icon_v1_00_a/data/nf10_upb_chipscope_icon_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | # UPB ChipScope ICON core 2 | # 3 | # Copyright (c) 2014, 2015 Jörg Niklas 4 | # osjsn@niklasfamily.de 5 | # 6 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 7 | # 8 | # Project Group "On-the-Fly Networking for Big Data" 9 | # SFB 901 "On-The-Fly Computing" 10 | # 11 | # University of Paderborn 12 | # Computer Engineering Group 13 | # Pohlweg 47 - 49 14 | # 33098 Paderborn 15 | # Germany 16 | # 17 | # 18 | # This file is free code: you can redistribute it and/or modify it under 19 | # the terms of the GNU Lesser General Public License version 2.1 as 20 | # published by the Free Software Foundation. 21 | # 22 | # This file is distributed in the hope that it will be useful, 23 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 24 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 | # GNU Lesser General Public License for more details. 26 | # 27 | # You should have received a copy of the GNU Lesser General Public License 28 | # along with this project. If not, see . 29 | # 30 | 31 | lib nf10_upb_chipscope_icon_v1_00_a nf10_upb_chipscope_icon 32 | 33 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_clock_generator_v1_00_a/data/nf10_upb_clock_generator_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | # 2 | # UPB Clock Generator core 3 | # 4 | # Copyright (c) 2014, 2015 Jörg Niklas 5 | # osjsn@niklasfamily.de 6 | # 7 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 8 | # 9 | # Project Group "On-the-Fly Networking for Big Data" 10 | # SFB 901 "On-The-Fly Computing" 11 | # 12 | # University of Paderborn 13 | # Computer Engineering Group 14 | # Pohlweg 47 - 49 15 | # 33098 Paderborn 16 | # Germany 17 | # 18 | # 19 | # This file is free code: you can redistribute it and/or modify it under 20 | # the terms of the GNU Lesser General Public License version 2.1 as 21 | # published by the Free Software Foundation. 22 | # 23 | # This file is distributed in the hope that it will be useful, 24 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 25 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 | # GNU Lesser General Public License for more details. 27 | # 28 | # You should have received a copy of the GNU Lesser General Public License 29 | # along with this project. If not, see . 30 | # 31 | 32 | lib nf10_upb_clock_generator_v1_00_a nf10_upb_clock_generator 33 | 34 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_axi_lite_chipscope_v1_00_a/data/nf10_upb_axi_lite_chipscope_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | # UPB AXI-4 Lite ChipScope core 2 | # 3 | # Copyright (c) 2014, 2015 Jörg Niklas 4 | # osjsn@niklasfamily.de 5 | # 6 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 7 | # 8 | # Project Group "On-the-Fly Networking for Big Data" 9 | # SFB 901 "On-The-Fly Computing" 10 | # 11 | # University of Paderborn 12 | # Computer Engineering Group 13 | # Pohlweg 47 - 49 14 | # 33098 Paderborn 15 | # Germany 16 | # 17 | # 18 | # This file is free code: you can redistribute it and/or modify it under 19 | # the terms of the GNU Lesser General Public License version 2.1 as 20 | # published by the Free Software Foundation. 21 | # 22 | # This file is distributed in the hope that it will be useful, 23 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 24 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 | # GNU Lesser General Public License for more details. 26 | # 27 | # You should have received a copy of the GNU Lesser General Public License 28 | # along with this project. If not, see . 29 | # 30 | 31 | lib nf10_upb_axi_lite_chipscope_v1_00_a nf10_upb_axi_lite_chipscope 32 | 33 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/sdntest/sdntest.hpp: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | * 6 | * Project Group "On-the-Fly Networking for Big Data" 7 | * SFB 901 "On-The-Fly Computing" 8 | * 9 | * University of Paderborn 10 | * Computer Engineering Group 11 | * Pohlweg 47 - 49 12 | * 33098 Paderborn 13 | * Germany 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the "License"); 16 | * you may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | namespace upb { 29 | 30 | class sdntest { 31 | 32 | public: 33 | sdntest(); 34 | 35 | }; 36 | 37 | } 38 | 39 | int main(int argc, char *argv[]); 40 | 41 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_axi_stream_chipscope_v1_00_a/data/nf10_upb_axi_stream_chipscope_v2_1_0.bbd: -------------------------------------------------------------------------------- 1 | # UPB AXI-4 Stream ChipScope core 2 | # 3 | # Copyright (c) 2014, 2015 Jörg Niklas 4 | # osjsn@niklasfamily.de 5 | # 6 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 7 | # 8 | # Project Group "On-the-Fly Networking for Big Data" 9 | # SFB 901 "On-The-Fly Computing" 10 | # 11 | # University of Paderborn 12 | # Computer Engineering Group 13 | # Pohlweg 47 - 49 14 | # 33098 Paderborn 15 | # Germany 16 | # 17 | # 18 | # This file is free code: you can redistribute it and/or modify it under 19 | # the terms of the GNU Lesser General Public License version 2.1 as 20 | # published by the Free Software Foundation. 21 | # 22 | # This file is distributed in the hope that it will be useful, 23 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 24 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 | # GNU Lesser General Public License for more details. 26 | # 27 | # You should have received a copy of the GNU Lesser General Public License 28 | # along with this project. If not, see . 29 | # 30 | 31 | FILES 32 | chipscope_ila_512.ngc, nf10_upb_axi_stream_chipscope.edf 33 | 34 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | # 4 | # Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | # 6 | # Project Group "On-the-Fly Networking for Big Data" 7 | # SFB 901 "On-The-Fly Computing" 8 | # 9 | # University of Paderborn 10 | # Computer Engineering Group 11 | # Pohlweg 47 - 49 12 | # 33098 Paderborn 13 | # Germany 14 | # 15 | # Licensed under the Apache License, Version 2.0 (the "License"); 16 | # you may not use this file except in compliance with the License. 17 | # You may obtain a copy of the License at: 18 | # 19 | # http://www.apache.org/licenses/LICENSE-2.0 20 | # 21 | # Unless required by applicable law or agreed to in writing, software 22 | # distributed under the License is distributed on an "AS IS" BASIS, 23 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | # See the License for the specific language governing permissions and 25 | # limitations under the License. 26 | # 27 | 28 | SUBDIRS = src/libsdn_dataplane src/sdntest 29 | 30 | .PHONY: all debug release clean $(SUBDIRS) 31 | 32 | all debug release clean: $(SUBDIRS) 33 | 34 | $(SUBDIRS): 35 | $(MAKE) -C $@ $(MAKECMDGOALS) 36 | 37 | src/sdntest: src/libsdn_dataplane 38 | 39 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_chipscope_icon_v1_00_a/data/nf10_upb_chipscope_icon_v2_1_0.bbd: -------------------------------------------------------------------------------- 1 | # UPB ChipScope ICON core 2 | # 3 | # Copyright (c) 2014, 2015 Jörg Niklas 4 | # osjsn@niklasfamily.de 5 | # 6 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 7 | # 8 | # Project Group "On-the-Fly Networking for Big Data" 9 | # SFB 901 "On-The-Fly Computing" 10 | # 11 | # University of Paderborn 12 | # Computer Engineering Group 13 | # Pohlweg 47 - 49 14 | # 33098 Paderborn 15 | # Germany 16 | # 17 | # 18 | # This file is free code: you can redistribute it and/or modify it under 19 | # the terms of the GNU Lesser General Public License version 2.1 as 20 | # published by the Free Software Foundation. 21 | # 22 | # This file is distributed in the hope that it will be useful, 23 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 24 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 | # GNU Lesser General Public License for more details. 26 | # 27 | # You should have received a copy of the GNU Lesser General Public License 28 | # along with this project. If not, see . 29 | # 30 | 31 | FILES 32 | chipscope_icon_1_ports.ngc, chipscope_icon_2_ports.ngc, chipscope_icon_3_ports.ngc, chipscope_icon_4_ports.ngc, chipscope_icon_5_ports.ngc, chipscope_icon_6_ports.ngc 33 | 34 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # UPB DMA Driver Makefile 3 | # 4 | # Copyright (c) 2014, 2015 Jörg Niklas 5 | # osjsn@niklasfamily.de 6 | # 7 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 8 | # 9 | # Project Group "On-the-Fly Networking for Big Data" 10 | # SFB 901 "On-The-Fly Computing" 11 | # 12 | # University of Paderborn 13 | # Computer Engineering Group 14 | # Pohlweg 47 - 49 15 | # 33098 Paderborn 16 | # Germany 17 | # 18 | # 19 | # This file is free code: you can redistribute it and/or modify it under 20 | # the terms of the GNU Lesser General Public License version 2.1 as 21 | # published by the Free Software Foundation. 22 | # 23 | # This file is distributed in the hope that it will be useful, 24 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 25 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 | # GNU Lesser General Public License for more details. 27 | # 28 | # You should have received a copy of the GNU Lesser General Public License 29 | # along with this project. If not, see . 30 | # 31 | 32 | SUBDIRS = src/nic_driver src/apps src/flashprog 33 | 34 | .PHONY: all debug release clean $(SUBDIRS) 35 | 36 | all debug release clean: $(SUBDIRS) 37 | 38 | $(SUBDIRS): 39 | $(MAKE) -C $@ $(MAKECMDGOALS) 40 | 41 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_axi_stream_chipscope_v1_00_a/chipscope/gen_axi_stream_chipscope.py: -------------------------------------------------------------------------------- 1 | data_bit = 0 2 | def data(name, count = 1): 3 | for i in range (0,count): 4 | global data_bit 5 | print ("Project.unit.0.data<" + str(data_bit) + ">=" + name + ("" if count == 1 else "[" + str(i) + "]")) 6 | data_bit = data_bit + 1 7 | 8 | trig_bit = 0 9 | def trig(name, count = 1): 10 | for i in range (0,count): 11 | global trig_bit 12 | print ("Project.unit.0.trigger<" + str(trig_bit) + ">=" + name + ("" if count == 1 else "[" + str(i) + "]")) 13 | trig_bit = trig_bit + 1 14 | 15 | print ("#ChipScope Core Inserter Project Version 2.0") 16 | 17 | data("reset") 18 | data("axis_tvalid") 19 | data("axis_tready") 20 | data("axis_tdata",256) 21 | data("axis_tkeep",32) 22 | data("axis_tlast") 23 | data("axis_tuser_packet_length",14) 24 | data("axis_tuser_in_port",3) 25 | data("axis_tuser_in_vport",3) 26 | data("axis_tuser_out_port",8) 27 | data("axis_tuser_out_vport",8) 28 | data("err_tvalid_deasserted"); 29 | data("err_tkeep_encoded_wrong"); 30 | data("err_tkeep_not_continuous"); 31 | data("err_too_big"); 32 | data("err_too_small"); 33 | 34 | print ("Project.unit.0.dataWidth=512") 35 | 36 | trig("reset") 37 | trig("axis_tvalid") 38 | trig("axis_tready") 39 | trig("axis_error") 40 | 41 | print ("Project.unit.0.triggerWidth=16") 42 | 43 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_10g_interface_v1_00_a/xco/xaui.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # This file contains the customisation parameters for a 4 | # Xilinx CORE Generator IP GUI. It is strongly recommended 5 | # that you do not manually alter this file as it may cause 6 | # unexpected and unsupported behavior. 7 | # 8 | ############################################################## 9 | # 10 | NEWPROJECT . 11 | SETPROJECT . 12 | # BEGIN Project Options 13 | SET addpads = false 14 | SET asysymbol = true 15 | SET busformat = BusFormatAngleBracketNotRipped 16 | SET createndf = false 17 | SET designentry = Verilog 18 | SET device = xc5vtx240t 19 | SET devicefamily = virtex5 20 | SET flowvendor = Other 21 | SET formalverification = false 22 | SET foundationsym = false 23 | SET implementationfiletype = Ngc 24 | SET package = ff1759 25 | SET removerpms = false 26 | SET simulationfiles = Structural 27 | SET speedgrade = -2 28 | SET verilogsim = true 29 | SET vhdlsim = false 30 | # END Project Options 31 | # BEGIN Select 32 | SELECT XAUI family Xilinx,_Inc. 10.3 33 | # END Select 34 | # BEGIN Parameters 35 | CSET 802_3ae_state_machines=false 36 | CSET component_name=xaui 37 | CSET mdio_management=false 38 | CSET use_tx_elastic_buffer=false 39 | CSET xgmii_interface=Internal 40 | # END Parameters 41 | GENERATE 42 | # CRC: 9d835636 43 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/data/nf10_upb_output_queue_v2_1_0.bbd: -------------------------------------------------------------------------------- 1 | # 2 | # UPB Output Queue core 3 | # 4 | # Copyright (c) 2014, 2015 Jörg Niklas 5 | # osjsn@niklasfamily.de 6 | # 7 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 8 | # 9 | # Project Group "On-the-Fly Networking for Big Data" 10 | # SFB 901 "On-The-Fly Computing" 11 | # 12 | # University of Paderborn 13 | # Computer Engineering Group 14 | # Pohlweg 47 - 49 15 | # 33098 Paderborn 16 | # Germany 17 | # 18 | # 19 | # This file is free code: you can redistribute it and/or modify it under 20 | # the terms of the GNU Lesser General Public License version 2.1 as 21 | # published by the Free Software Foundation. 22 | # 23 | # This file is distributed in the hope that it will be useful, 24 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 25 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 | # GNU Lesser General Public License for more details. 27 | # 28 | # You should have received a copy of the GNU Lesser General Public License 29 | # along with this project. If not, see . 30 | # 31 | 32 | FILES 33 | 2_ports/nf10_upb_output_queue.edf, 3_ports/nf10_upb_output_queue.edf, 4_ports/nf10_upb_output_queue.edf, 5_ports/nf10_upb_output_queue.edf, 6_ports/nf10_upb_output_queue.edf, 7_ports/nf10_upb_output_queue.edf 34 | 35 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/libsdn_dataplane/errors.h: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | * 6 | * Project Group "On-the-Fly Networking for Big Data" 7 | * SFB 901 "On-The-Fly Computing" 8 | * 9 | * University of Paderborn 10 | * Computer Engineering Group 11 | * Pohlweg 47 - 49 12 | * 33098 Paderborn 13 | * Germany 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the "License"); 16 | * you may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #pragma once 29 | 30 | /** 31 | * Enumeration with error codes (plain C version) 32 | * The error codes are inside the file "errors.inc" 33 | */ 34 | enum errors { 35 | 36 | #define UPB_ERROR_PREFIX(x) UPB_ERROR_##x 37 | #include "errors.inc" 38 | #undef UPB_ERROR_PREFIX 39 | 40 | }; 41 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_10g_interface_v1_00_a/xco/xgmac.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # This file contains the customisation parameters for a 4 | # Xilinx CORE Generator IP GUI. It is strongly recommended 5 | # that you do not manually alter this file as it may cause 6 | # unexpected and unsupported behavior. 7 | # 8 | ############################################################## 9 | # 10 | NEWPROJECT . 11 | SETPROJECT . 12 | # BEGIN Project Options 13 | SET addpads = false 14 | SET asysymbol = true 15 | SET busformat = BusFormatAngleBracketNotRipped 16 | SET createndf = false 17 | SET designentry = Verilog 18 | SET device = xc5vtx240t 19 | SET devicefamily = virtex5 20 | SET flowvendor = Other 21 | SET formalverification = false 22 | SET foundationsym = false 23 | SET implementationfiletype = Ngc 24 | SET package = ff1759 25 | SET removerpms = false 26 | SET simulationfiles = Structural 27 | SET speedgrade = -2 28 | SET verilogsim = true 29 | SET vhdlsim = false 30 | # END Project Options 31 | # BEGIN Select 32 | SELECT Ten_Gigabit_Ethernet_MAC family Xilinx,_Inc. 10.3 33 | # END Select 34 | # BEGIN Parameters 35 | CSET component_name=xgmac 36 | CSET management_interface=false 37 | CSET physical_interface=XGMII 38 | CSET simplex_split=None 39 | CSET statistics_gathering=false 40 | # END Parameters 41 | GENERATE 42 | # CRC: 2346bc55 43 | -------------------------------------------------------------------------------- /lib/hw/xilinx/pcores/diff_input_buf_v1_00_a/hdl/vhdl/diff_input_buf.vhd: -------------------------------------------------------------------------------- 1 | -- Differential Input Buffer IP Core VHDL Soure Code 2 | -- Kieran O' Leary - 11th June 2004 3 | 4 | -- Description: This core will take two differential bus inputs "DIFF_INPUT_P" and "DIFF_INPUT_N" and convert it to a single-ended input bus 5 | -- "SINGLE_ENDED_INPUT". SINGLE_ENDED_INPUT<0> will be associated with DIFF_INPUT_P<0> and DIFF_INPUT_N<0> and so on. 6 | -- By default the IOSTANDARD will be LVDS_25 but this can be changed along with the pin location in a UCF file. 7 | 8 | library IEEE; 9 | use IEEE.STD_LOGIC_1164.ALL; 10 | use IEEE.STD_LOGIC_ARITH.ALL; 11 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 12 | 13 | -- Uncomment the following lines to use the declarations that are 14 | -- provided for instantiating Xilinx primitive components. 15 | library UNISIM; 16 | use UNISIM.VComponents.all; 17 | 18 | entity DIFF_INPUT_BUF is 19 | Port ( SINGLE_ENDED_INPUT : out STD_ULOGIC; 20 | DIFF_INPUT_P : in STD_ULOGIC; 21 | DIFF_INPUT_N : in STD_ULOGIC); 22 | end DIFF_INPUT_BUF; 23 | 24 | architecture Behavioral of DIFF_INPUT_BUF is 25 | 26 | component IBUFDS 27 | port (O : out STD_ULOGIC; 28 | IB : in STD_ULOGIC; 29 | I : in STD_ULOGIC); 30 | end component; 31 | begin 32 | U0: IBUFDS 33 | port map (I => DIFF_INPUT_P, IB => DIFF_INPUT_N, O => SINGLE_ENDED_INPUT); 34 | 35 | 36 | end Behavioral; 37 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/libsdn_dataplane/errors.hpp: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | * 6 | * Project Group "On-the-Fly Networking for Big Data" 7 | * SFB 901 "On-The-Fly Computing" 8 | * 9 | * University of Paderborn 10 | * Computer Engineering Group 11 | * Pohlweg 47 - 49 12 | * 33098 Paderborn 13 | * Germany 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the "License"); 16 | * you may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #pragma once 29 | 30 | namespace upb { 31 | 32 | /** 33 | * Enumeration with error codes (C++ version) 34 | * The error codes are inside the file "errors.inc" 35 | */ 36 | enum class errors { 37 | 38 | #define UPB_ERROR_PREFIX(x) x 39 | #include "errors.inc" 40 | #undef UPB_ERROR_PREFIX 41 | 42 | }; 43 | 44 | namespace errors_text { 45 | 46 | extern char const * error_text[]; 47 | 48 | }; 49 | 50 | } 51 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_10g_interface_v1_00_a/hdl/verilog/xilinx/xaui_block.diff: -------------------------------------------------------------------------------- 1 | DISCLAIMER NOTICE 2 | We are not affiliated, associated, authorized, endorsed by, or in any 3 | way officially connected with Xilinx, Inc. or any of its subsidiaries or 4 | its affiliates. In no event whatsoever shall Xilinx, Inc. or any of its 5 | subsidiaries or its affiliates have any warranty or support commitment 6 | for this software or liability for loss, injury or damage in connection 7 | with this software, including but not limited to the use or display 8 | thereof. 9 | --- 10 | 55a56,70 11 | > //////////////////////////////////////////////////////////////////////// 12 | > // 13 | > // NetFPGA-10G http://www.netfpga.org 14 | > // 15 | > // Module: 16 | > // xaui_block.v 17 | > // 18 | > // Description: 19 | > // XAUI block patched with Lane reverse 20 | > // 21 | > // Revision history: 22 | > // 2010/12/8 hyzeng: Initial check-in 23 | > // 24 | > //////////////////////////////////////////////////////////////////////// 25 | > 26 | 59c74,75 27 | < parameter WRAPPER_SIM_GTXRESET_SPEEDUP = 0 28 | --- 29 | > parameter WRAPPER_SIM_GTXRESET_SPEEDUP = 0, 30 | > parameter REVERSE_LANES = 0 31 | 260c276,277 32 | < .WRAPPER_SIM_PLL_PERDIV2 (9'h140) 33 | --- 34 | > .WRAPPER_SIM_PLL_PERDIV2 (9'h140), 35 | > .REVERSE_LANES (REVERSE_LANES) 36 | 535c552 37 | < always @(posedge clk156 or posedge reset_txsync) 38 | --- 39 | > always @(posedge clk156)// or posedge reset_txsync) 40 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_axi_stream_chipscope_v1_00_a/Makefile: -------------------------------------------------------------------------------- 1 | # UPB AXI-4 Stream ChipScope core 2 | # 3 | # Copyright (c) 2014, 2015 Jörg Niklas 4 | # osjsn@niklasfamily.de 5 | # 6 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 7 | # 8 | # Project Group "On-the-Fly Networking for Big Data" 9 | # SFB 901 "On-The-Fly Computing" 10 | # 11 | # University of Paderborn 12 | # Computer Engineering Group 13 | # Pohlweg 47 - 49 14 | # 33098 Paderborn 15 | # Germany 16 | # 17 | # 18 | # This file is free code: you can redistribute it and/or modify it under 19 | # the terms of the GNU Lesser General Public License version 2.1 as 20 | # published by the Free Software Foundation. 21 | # 22 | # This file is distributed in the hope that it will be useful, 23 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 24 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 | # GNU Lesser General Public License for more details. 26 | # 27 | # You should have received a copy of the GNU Lesser General Public License 28 | # along with this project. If not, see . 29 | # 30 | 31 | .PHONY: clean install 32 | 33 | all: install 34 | 35 | install: netlist/nf10_upb_axi_stream_chipscope.edf 36 | 37 | prepare: 38 | mkdir -p $(OUTPUT_DIRS) 39 | 40 | netlist/nf10_upb_axi_stream_chipscope.edf: prj/nf10_upb_axi_stream_chipscope.prj 41 | $(SYNPLIFY_CMD) -batch $< 42 | 43 | clean: 44 | find netlist -mindepth 1 ! -name chipscope_ila_512.ngc -delete 45 | find prj -mindepth 1 ! -name nf10_upb_axi_stream_chipscope.prj -delete 46 | 47 | -------------------------------------------------------------------------------- /lib/hw/std/pcores/nf10_mdio_v1_00_a/data/nf10_mdio_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # NetFPGA-10G http://www.netfpga.org 4 | # 5 | # File: 6 | # nf10_mdio_v2_1_0.pao 7 | # 8 | # Library: 9 | # hw/std/pcores/nf10_mdio_v1_00_a 10 | # 11 | # Description: 12 | # Peripheral Analyze Order File 13 | # 14 | # Copyright notice: 15 | # Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 16 | # Junior University 17 | # 18 | # Licence: 19 | # This file is part of the NetFPGA 10G development base package. 20 | # 21 | # This file is free code: you can redistribute it and/or modify it under 22 | # the terms of the GNU Lesser General Public License version 2.1 as 23 | # published by the Free Software Foundation. 24 | # 25 | # This package is distributed in the hope that it will be useful, but 26 | # WITHOUT ANY WARRANTY; without even the implied warranty of 27 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 28 | # Lesser General Public License for more details. 29 | # 30 | # You should have received a copy of the GNU Lesser General Public 31 | # License along with the NetFPGA source package. If not, see 32 | # http://www.gnu.org/licenses/. 33 | # 34 | # 35 | 36 | lib proc_common_v3_00_a all 37 | lib nf10_mdio_v1_00_a mdio_if.vhd vhdl 38 | lib nf10_mdio_v1_00_a axi_interface.vhd vhdl 39 | lib nf10_mdio_v1_00_a mdio_ipif.vhd vhdl 40 | lib nf10_mdio_v1_00_a nf10_mdio.vhd vhdl 41 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # UPB Output Queue core 3 | # 4 | # Copyright (c) 2014, 2015 Jörg Niklas 5 | # osjsn@niklasfamily.de 6 | # 7 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 8 | # 9 | # Project Group "On-the-Fly Networking for Big Data" 10 | # SFB 901 "On-The-Fly Computing" 11 | # 12 | # University of Paderborn 13 | # Computer Engineering Group 14 | # Pohlweg 47 - 49 15 | # 33098 Paderborn 16 | # Germany 17 | # 18 | # 19 | # This file is free code: you can redistribute it and/or modify it under 20 | # the terms of the GNU Lesser General Public License version 2.1 as 21 | # published by the Free Software Foundation. 22 | # 23 | # This file is distributed in the hope that it will be useful, 24 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 25 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 | # GNU Lesser General Public License for more details. 27 | # 28 | # You should have received a copy of the GNU Lesser General Public License 29 | # along with this project. If not, see . 30 | # 31 | 32 | .PHONY: prepare clean install 33 | 34 | OUTPUT_DIRS = netlist/2_ports netlist/3_ports netlist/4_ports netlist/5_ports netlist/6_ports netlist/7_ports 35 | 36 | all: install 37 | 38 | install: 39 | $(MAKE) prepare 40 | $(MAKE) $(addsuffix /nf10_upb_output_queue.edf, $(OUTPUT_DIRS)) 41 | 42 | prepare: 43 | mkdir -p $(OUTPUT_DIRS) 44 | 45 | netlist/%_ports/nf10_upb_output_queue.edf: hdl/verilog/nf10_upb_output_queue_%.prj 46 | $(SYNPLIFY_CMD) -batch $< 47 | 48 | clean: 49 | rm -rf netlist/* 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/libsdn_dataplane/logging.hpp: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | * 6 | * Project Group "On-the-Fly Networking for Big Data" 7 | * SFB 901 "On-The-Fly Computing" 8 | * 9 | * University of Paderborn 10 | * Computer Engineering Group 11 | * Pohlweg 47 - 49 12 | * 33098 Paderborn 13 | * Germany 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the "License"); 16 | * you may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #pragma once 29 | 30 | namespace upb { 31 | 32 | /** 33 | * This class provides basic loggin functionality 34 | */ 35 | class logging { 36 | 37 | public: 38 | /** 39 | * Initialize the logger 40 | */ 41 | static void init_logging(); 42 | /** 43 | * Set the severity level to "trace" (very verbose) 44 | */ 45 | static void log_level_trace(); 46 | /** 47 | * Set the severity level to "debug" (verbose) 48 | */ 49 | static void log_level_debug(); 50 | /** 51 | * Set the severity level to "info" 52 | */ 53 | static void log_level_info(); 54 | 55 | }; 56 | 57 | 58 | } 59 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/libsdn_dataplane/poll_thread.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | * 6 | * Project Group "On-the-Fly Networking for Big Data" 7 | * SFB 901 "On-The-Fly Computing" 8 | * 9 | * University of Paderborn 10 | * Computer Engineering Group 11 | * Pohlweg 47 - 49 12 | * 33098 Paderborn 13 | * Germany 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the "License"); 16 | * you may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "poll_thread.hpp" 29 | 30 | namespace upb { 31 | 32 | poll_thread::poll_thread(mutex_t &mutex, uint32_t poll_interval_ms) : 33 | mutex(mutex), 34 | poll_interval_ms(poll_interval_ms), 35 | thread(b::ref(*this)) 36 | {} 37 | 38 | poll_thread::~poll_thread() 39 | { 40 | thread.interrupt(); 41 | thread.join(); 42 | } 43 | 44 | void poll_thread::operator()() 45 | { 46 | while (1) { 47 | b::this_thread::sleep_for(boost::chrono::milliseconds(poll_interval_ms)); 48 | { 49 | b::recursive_mutex::scoped_lock lock(*mutex); 50 | signal(); 51 | } 52 | } 53 | } 54 | 55 | } 56 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_lib/hdl/verilog/tkeep_coder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014, 2015 Thomas Löcke 3 | * tloecke@mail.uni-paderborn.de 4 | * 5 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project: 6 | * 7 | * Project Group "On-the-Fly Networking for Big Data" 8 | * SFB 901 "On-The-Fly Computing" 9 | * 10 | * University of Paderborn 11 | * Computer Engineering Group 12 | * Pohlweg 47 - 49 13 | * 33098 Paderborn 14 | * Germany 15 | * 16 | * 17 | * This file is free code: you can redistribute it and/or modify it under 18 | * the terms of the GNU Lesser General Public License version 2.1 as 19 | * published by the Free Software Foundation. 20 | * 21 | * This file is distributed in the hope that it will be useful, 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 | * GNU Lesser General Public License for more details. 25 | * 26 | * You should have received a copy of the GNU Lesser General Public License 27 | * along with this project. If not, see . 28 | * 29 | * Description: encode and decode functions used for tkeep 30 | */ 31 | 32 | 33 | function [4:0] encode; 34 | input [31:0] number; 35 | reg [5:0] i; 36 | begin 37 | encode = 31; 38 | for (i = 31; i > 0; i = i - 1) begin 39 | if (number[i] == 1'b0) begin 40 | encode = i - 1; 41 | end 42 | end 43 | end 44 | endfunction 45 | 46 | function [31:0] decode; 47 | input [4:0] number; 48 | reg [5:0] i; 49 | begin 50 | for (i = 0; i <= 31; i = i + 1) begin 51 | if (i == number) 52 | decode = (2**(i + 1)) - 1; 53 | end 54 | end 55 | endfunction 56 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | The NetFPGA-10G UPB OpenFlow Switch 2 | =================================== 3 | 4 | 5 | Welcome to the NetFPGA-10G-UPB-OpenFlow repository. 6 | 7 | Please read the provided [documentation](docs/documentation.pdf) carefully before 8 | using this code. 9 | 10 | This repository contains the NetFPGA-10G UPB Framework along with two projects: 11 | * upb_l2switch: A simple layer 2 network switch based on the NetFPGA-10G card. 12 | * upb_openflowswitch: The hardware implementation which is part of an OpenFlow Switch. 13 | A modified version of Open vSwitch is required (available [here](https://github.com/pc2/ovs)). 14 | 15 | Please note that the NetFPGA-10G UPB Framework is not compatible with the 16 | Stanford NetFPGA-10G Framework. 17 | 18 | ### Feature Overview 19 | 20 | * Jumbo Frame Support 21 | * Large output queues using the external QDR2-SRAM memory 22 | * Flow Control using ethernet pause frames 23 | * Driver ported to Linux New API 24 | * Support for multiple cards in one host PC 25 | * Support for Samtec high speed port to interconnect multiple cards 26 | 27 | ### Requirements & Prerequisites 28 | To build the projects you will need the following software (different versions 29 | might work): 30 | * Ubuntu 14.04 31 | * Linux Kernel 3.14 32 | * Synplify Premier DP 2012.09-SP1 33 | * Xilinx ISE 14.7 34 | * Xilinx XPS 14.7 35 | 36 | Licenses for the following IP cores are needed: 37 | * Xilinx 10G MAC 38 | * Xilinx Aurora 39 | 40 | 41 | This project was created as part of the project group [On-the-fly Networking 42 | for Big Data](http://www.cs.uni-paderborn.de/fachgebiete/fachgebiet-rechnernetze/lehre/lehreteaching-ss14/pg-on-the-fly-networking-for-big-data.html) 43 | at University of Paderborn. 44 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/src/apps/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # NetFPGA-10G http://www.netfpga.org 4 | # 5 | # File: 6 | # Makefile 7 | # 8 | # Project: 9 | # nic 10 | # 11 | # Author: 12 | # Mario Flajslik 13 | # Jong Hun Han 14 | # 15 | # Description: 16 | # make : Make example applications to read stats and read/write AXI 17 | # registers 18 | # 19 | # 20 | # Copyright notice: 21 | # Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 22 | # Junior University 23 | # 24 | # Licence: 25 | # This file is part of the NetFPGA 10G development base package. 26 | # 27 | # This file is free code: you can redistribute it and/or modify it under 28 | # the terms of the GNU Lesser General Public License version 2.1 as 29 | # published by the Free Software Foundation. 30 | # 31 | # This package is distributed in the hope that it will be useful, but 32 | # WITHOUT ANY WARRANTY; without even the implied warranty of 33 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 34 | # Lesser General Public License for more details. 35 | # 36 | # You should have received a copy of the GNU Lesser General Public 37 | # License along with the NetFPGA source package. If not, see 38 | # http://www.gnu.org/licenses/. 39 | # 40 | # 41 | 42 | all: 43 | @mkdir -p ../../bin 44 | gcc -o ../../bin/stats stats.c 45 | gcc -o ../../bin/rdaxi rdaxi.c 46 | gcc -o ../../bin/wraxi wraxi.c 47 | gcc -o ../../bin/ael2005_conf ael2005_conf.c 48 | 49 | clean: 50 | rm -f ../../bin/stats ../../bin/rdaxi ../../bin/wraxi ../../bin/ael2005_conf 51 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_ofswitch_v1_00_a/hdl/SystemVerilog/action_delay.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014, 2015 Felix Wallaschek 3 | * felix@elektronenversand.de 4 | * 5 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project: 6 | * 7 | * Project Group "On-the-Fly Networking for Big Data" 8 | * SFB 901 "On-The-Fly Computing" 9 | * 10 | * University of Paderborn 11 | * Computer Engineering Group 12 | * Pohlweg 47 - 49 13 | * 33098 Paderborn 14 | * Germany 15 | * 16 | * 17 | * This file is free code: you can redistribute it and/or modify it under 18 | * the terms of the GNU Lesser General Public License version 2.1 as 19 | * published by the Free Software Foundation. 20 | * 21 | * This file is distributed in the hope that it will be useful, 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 | * GNU Lesser General Public License for more details. 25 | * 26 | * You should have received a copy of the GNU Lesser General Public License 27 | * along with this project. If not, see . 28 | */ 29 | 30 | 31 | 32 | `include "parameters.v" 33 | module action_delay #( 34 | parameter C_NUM_DELAY_CYCLES=5, 35 | parameter C_WIDTH=C_IN_PORT_WIDTH*2+2+C_MATCH_ADDR_WIDTH 36 | )( 37 | input clk, 38 | input reset, 39 | 40 | input [C_WIDTH-1:0] inp, 41 | output [C_WIDTH-1:0] outp 42 | ); 43 | 44 | 45 | logic [C_WIDTH-1:0]delay[C_NUM_DELAY_CYCLES-1:0]; 46 | 47 | generate 48 | for(genvar i = 0; i < C_NUM_DELAY_CYCLES-1; i = i+1) begin 49 | always_ff @(posedge clk) begin 50 | delay[i] <= delay[i+1]; 51 | end 52 | end 53 | endgenerate 54 | 55 | 56 | assign delay[C_NUM_DELAY_CYCLES-1] = inp; 57 | assign outp = delay[0]; 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/src/flashprog/reg_lib.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * NetFPGA-10G http://www.netfpga.org 4 | * 5 | * File: 6 | * reg_lib.h 7 | * 8 | * Project: 9 | * flash_configuration 10 | * 11 | * Author: 12 | * Muhammad Shahbaz 13 | * 14 | * Description: 15 | * Set of definitions for the NF10 register access library. 16 | * 17 | * Copyright notice: 18 | * Copyright (C) 2010, 2011 University of Cambridge 19 | * 20 | * Licence: 21 | * This file is part of the NetFPGA 10G development base package. 22 | * 23 | * This file is free code: you can redistribute it and/or modify it under 24 | * the terms of the GNU Lesser General Public License version 2.1 as 25 | * published by the Free Software Foundation. 26 | * 27 | * This package is distributed in the hope that it will be useful, but 28 | * WITHOUT ANY WARRANTY; without even the implied warranty of 29 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | * Lesser General Public License for more details. 31 | * 32 | * You should have received a copy of the GNU Lesser General Public 33 | * License along with the NetFPGA source package. If not, see 34 | * http://www.gnu.org/licenses/. 35 | * 36 | * This file was developed by SRI International and the University of 37 | * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 38 | * ("CTSRD"), as part of the DARPA CRASH research programme. 39 | */ 40 | 41 | #ifndef _REG_LIB_H_ 42 | #define _REG_LIB_H_ 43 | 44 | #include 45 | #include 46 | 47 | inline uint32_t reg_rd(int dev, uint64_t addr); 48 | inline int reg_wr(int dev, uint64_t addr, uint32_t val); 49 | 50 | #endif 51 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/prj/qdr2_test_netfpga/ipcore_dir/icon.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Wed Mar 19 17:13:15 2014 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:chipscope_icon:1.06.a 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc5vtx240t 26 | SET devicefamily = virtex5 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ff1759 32 | SET removerpms = false 33 | SET simulationfiles = Structural 34 | SET speedgrade = -2 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a 40 | # END Select 41 | # BEGIN Parameters 42 | CSET component_name=icon 43 | CSET constraint_type=external 44 | CSET enable_jtag_bufg=true 45 | CSET example_design=false 46 | CSET number_control_ports=4 47 | CSET use_ext_bscan=false 48 | CSET use_softbscan=false 49 | CSET use_unused_bscan=false 50 | CSET user_scan_chain=USER1 51 | # END Parameters 52 | # BEGIN Extra information 53 | MISC pkg_timestamp=2013-10-13T14:12:40Z 54 | # END Extra information 55 | GENERATE 56 | # CRC: ea93389c 57 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/libsdn_dataplane/errors.inc: -------------------------------------------------------------------------------- 1 | 2 | UPB_ERROR_PREFIX(OK), //!< No error 3 | UPB_ERROR_PREFIX(COULD_NOT_OPEN_NETFPGA_DEVICE),//!< The NetFPGA device could not be opened 4 | UPB_ERROR_PREFIX(COULD_NOT_MAP_TO_USER_SPACE),//!< Could not map NetFPGA IO memory space to user space 5 | UPB_ERROR_PREFIX(ERROR_ERASING_FLASH_BLOCK),//!< Error during erase of flash block 6 | UPB_ERROR_PREFIX(ERROR_VERIFYING_FLASH_CONTENTS),//!< Error during verification of flash contents 7 | UPB_ERROR_PREFIX(ERROR_PROGRAMMING_FLASH_BUFFER),//!< Error during programming of a flash buffer 8 | UPB_ERROR_PREFIX(ERROR_COULD_NOT_OPEN_FILE_FOR_FLASH_PROG), //!< Could not open the file for flash programming 9 | UPB_ERROR_PREFIX(FLASH_TIMEOUT), //!< Timeout while waiting for flash ready 10 | UPB_ERROR_PREFIX(TCAM_COULD_NOT_BE_IDENTIFIED), //!< TCAM could not be identified 11 | UPB_ERROR_PREFIX(FLOW_NOT_INSTALLED), //!< Tried to do operations on a flow which is not installed 12 | UPB_ERROR_PREFIX(FLOW_ALREADY_INSTALLED), //!< Tried to modify a already installed flow 13 | UPB_ERROR_PREFIX(UNUSED_BITS_SET_IN_HEADER_FIELD), //!< Tried to set unused bits in key/mask 14 | UPB_ERROR_PREFIX(INVALID_PORT_NUMBER), //!< An invalid port number was given 15 | UPB_ERROR_PREFIX(CPP_EXCEPTION), //!< A C++ exception was raised 16 | UPB_ERROR_PREFIX(UNKNOWN_EXCEPTION), //!< An unknown exception was raised 17 | UPB_ERROR_PREFIX(DATAPLANE_ALREADY_EXISTS), //!< The dataplane already exists 18 | UPB_ERROR_PREFIX(INVALID_PORT_NAME), //!< The specified port does not follow the UPB NetFPGA port scheme 19 | UPB_ERROR_PREFIX(DATA_PLANE_DOES_NOT_EXIST), //!< The specified data plane does not exist 20 | UPB_ERROR_PREFIX(COULD_NOT_INSERT_INTO_FLOW_TABLE), //!< Internal error: Could not insert into flow table 21 | UPB_ERROR_PREFIX(COULD_NOT_FIND_FLOW_BY_REF_ID), //!< Reference id of flow unknown 22 | UPB_ERROR_PREFIX(CAM_COULD_NOT_BE_IDENTIFIED), //!< CAM could not be identified 23 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_chipscope_icon_v1_00_a/xco/chipscope_icon_1_ports.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Tue Sep 2 01:54:43 2014 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:chipscope_icon:1.06.a 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | NEWPROJECT . 21 | SETPROJECT . 22 | SET addpads = false 23 | SET asysymbol = true 24 | SET busformat = BusFormatAngleBracketNotRipped 25 | SET createndf = false 26 | SET designentry = Verilog 27 | SET device = xc5vtx240t 28 | SET devicefamily = virtex5 29 | SET flowvendor = Other 30 | SET formalverification = false 31 | SET foundationsym = false 32 | SET implementationfiletype = Ngc 33 | SET package = ff1759 34 | SET removerpms = false 35 | SET simulationfiles = Behavioral 36 | SET speedgrade = -2 37 | SET verilogsim = false 38 | SET vhdlsim = false 39 | # END Project Options 40 | # BEGIN Select 41 | SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a 42 | # END Select 43 | # BEGIN Parameters 44 | CSET component_name=chipscope_icon_1_ports 45 | CSET constraint_type=external 46 | CSET enable_jtag_bufg=true 47 | CSET example_design=false 48 | CSET number_control_ports=1 49 | CSET use_ext_bscan=false 50 | CSET use_softbscan=false 51 | CSET use_unused_bscan=false 52 | CSET user_scan_chain=USER1 53 | # END Parameters 54 | # BEGIN Extra information 55 | MISC pkg_timestamp=2013-10-13T14:12:40Z 56 | # END Extra information 57 | GENERATE 58 | # CRC: b7765cb7 59 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_chipscope_icon_v1_00_a/xco/chipscope_icon_2_ports.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Tue Sep 2 01:54:43 2014 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:chipscope_icon:1.06.a 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | NEWPROJECT . 21 | SETPROJECT . 22 | SET addpads = false 23 | SET asysymbol = true 24 | SET busformat = BusFormatAngleBracketNotRipped 25 | SET createndf = false 26 | SET designentry = Verilog 27 | SET device = xc5vtx240t 28 | SET devicefamily = virtex5 29 | SET flowvendor = Other 30 | SET formalverification = false 31 | SET foundationsym = false 32 | SET implementationfiletype = Ngc 33 | SET package = ff1759 34 | SET removerpms = false 35 | SET simulationfiles = Behavioral 36 | SET speedgrade = -2 37 | SET verilogsim = false 38 | SET vhdlsim = false 39 | # END Project Options 40 | # BEGIN Select 41 | SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a 42 | # END Select 43 | # BEGIN Parameters 44 | CSET component_name=chipscope_icon_2_ports 45 | CSET constraint_type=external 46 | CSET enable_jtag_bufg=true 47 | CSET example_design=false 48 | CSET number_control_ports=2 49 | CSET use_ext_bscan=false 50 | CSET use_softbscan=false 51 | CSET use_unused_bscan=false 52 | CSET user_scan_chain=USER1 53 | # END Parameters 54 | # BEGIN Extra information 55 | MISC pkg_timestamp=2013-10-13T14:12:40Z 56 | # END Extra information 57 | GENERATE 58 | # CRC: b7765cb7 59 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_chipscope_icon_v1_00_a/xco/chipscope_icon_3_ports.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Tue Sep 2 01:54:43 2014 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:chipscope_icon:1.06.a 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | NEWPROJECT . 21 | SETPROJECT . 22 | SET addpads = false 23 | SET asysymbol = true 24 | SET busformat = BusFormatAngleBracketNotRipped 25 | SET createndf = false 26 | SET designentry = Verilog 27 | SET device = xc5vtx240t 28 | SET devicefamily = virtex5 29 | SET flowvendor = Other 30 | SET formalverification = false 31 | SET foundationsym = false 32 | SET implementationfiletype = Ngc 33 | SET package = ff1759 34 | SET removerpms = false 35 | SET simulationfiles = Behavioral 36 | SET speedgrade = -2 37 | SET verilogsim = false 38 | SET vhdlsim = false 39 | # END Project Options 40 | # BEGIN Select 41 | SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a 42 | # END Select 43 | # BEGIN Parameters 44 | CSET component_name=chipscope_icon_3_ports 45 | CSET constraint_type=external 46 | CSET enable_jtag_bufg=true 47 | CSET example_design=false 48 | CSET number_control_ports=3 49 | CSET use_ext_bscan=false 50 | CSET use_softbscan=false 51 | CSET use_unused_bscan=false 52 | CSET user_scan_chain=USER1 53 | # END Parameters 54 | # BEGIN Extra information 55 | MISC pkg_timestamp=2013-10-13T14:12:40Z 56 | # END Extra information 57 | GENERATE 58 | # CRC: b7765cb7 59 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_chipscope_icon_v1_00_a/xco/chipscope_icon_4_ports.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Tue Sep 2 01:54:43 2014 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:chipscope_icon:1.06.a 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | NEWPROJECT . 21 | SETPROJECT . 22 | SET addpads = false 23 | SET asysymbol = true 24 | SET busformat = BusFormatAngleBracketNotRipped 25 | SET createndf = false 26 | SET designentry = Verilog 27 | SET device = xc5vtx240t 28 | SET devicefamily = virtex5 29 | SET flowvendor = Other 30 | SET formalverification = false 31 | SET foundationsym = false 32 | SET implementationfiletype = Ngc 33 | SET package = ff1759 34 | SET removerpms = false 35 | SET simulationfiles = Behavioral 36 | SET speedgrade = -2 37 | SET verilogsim = false 38 | SET vhdlsim = false 39 | # END Project Options 40 | # BEGIN Select 41 | SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a 42 | # END Select 43 | # BEGIN Parameters 44 | CSET component_name=chipscope_icon_4_ports 45 | CSET constraint_type=external 46 | CSET enable_jtag_bufg=true 47 | CSET example_design=false 48 | CSET number_control_ports=4 49 | CSET use_ext_bscan=false 50 | CSET use_softbscan=false 51 | CSET use_unused_bscan=false 52 | CSET user_scan_chain=USER1 53 | # END Parameters 54 | # BEGIN Extra information 55 | MISC pkg_timestamp=2013-10-13T14:12:40Z 56 | # END Extra information 57 | GENERATE 58 | # CRC: b7765cb7 59 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_chipscope_icon_v1_00_a/xco/chipscope_icon_5_ports.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Tue Sep 2 01:54:43 2014 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:chipscope_icon:1.06.a 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | NEWPROJECT . 21 | SETPROJECT . 22 | SET addpads = false 23 | SET asysymbol = true 24 | SET busformat = BusFormatAngleBracketNotRipped 25 | SET createndf = false 26 | SET designentry = Verilog 27 | SET device = xc5vtx240t 28 | SET devicefamily = virtex5 29 | SET flowvendor = Other 30 | SET formalverification = false 31 | SET foundationsym = false 32 | SET implementationfiletype = Ngc 33 | SET package = ff1759 34 | SET removerpms = false 35 | SET simulationfiles = Behavioral 36 | SET speedgrade = -2 37 | SET verilogsim = false 38 | SET vhdlsim = false 39 | # END Project Options 40 | # BEGIN Select 41 | SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a 42 | # END Select 43 | # BEGIN Parameters 44 | CSET component_name=chipscope_icon_5_ports 45 | CSET constraint_type=external 46 | CSET enable_jtag_bufg=true 47 | CSET example_design=false 48 | CSET number_control_ports=5 49 | CSET use_ext_bscan=false 50 | CSET use_softbscan=false 51 | CSET use_unused_bscan=false 52 | CSET user_scan_chain=USER1 53 | # END Parameters 54 | # BEGIN Extra information 55 | MISC pkg_timestamp=2013-10-13T14:12:40Z 56 | # END Extra information 57 | GENERATE 58 | # CRC: b7765cb7 59 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_chipscope_icon_v1_00_a/xco/chipscope_icon_6_ports.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Tue Sep 2 01:54:43 2014 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:chipscope_icon:1.06.a 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | NEWPROJECT . 21 | SETPROJECT . 22 | SET addpads = false 23 | SET asysymbol = true 24 | SET busformat = BusFormatAngleBracketNotRipped 25 | SET createndf = false 26 | SET designentry = Verilog 27 | SET device = xc5vtx240t 28 | SET devicefamily = virtex5 29 | SET flowvendor = Other 30 | SET formalverification = false 31 | SET foundationsym = false 32 | SET implementationfiletype = Ngc 33 | SET package = ff1759 34 | SET removerpms = false 35 | SET simulationfiles = Behavioral 36 | SET speedgrade = -2 37 | SET verilogsim = false 38 | SET vhdlsim = false 39 | # END Project Options 40 | # BEGIN Select 41 | SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a 42 | # END Select 43 | # BEGIN Parameters 44 | CSET component_name=chipscope_icon_6_ports 45 | CSET constraint_type=external 46 | CSET enable_jtag_bufg=true 47 | CSET example_design=false 48 | CSET number_control_ports=6 49 | CSET use_ext_bscan=false 50 | CSET use_softbscan=false 51 | CSET use_unused_bscan=false 52 | CSET user_scan_chain=USER1 53 | # END Parameters 54 | # BEGIN Extra information 55 | MISC pkg_timestamp=2013-10-13T14:12:40Z 56 | # END Extra information 57 | GENERATE 58 | # CRC: b7765cb7 59 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_clock_generator_v1_00_a/testbench/nf10_upb_clock_generator_tb.v: -------------------------------------------------------------------------------- 1 | /* 2 | * UPB Clock Generator core testbench 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas 5 | * osjsn@niklasfamily.de 6 | * 7 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 8 | * 9 | * Project Group "On-the-Fly Networking for Big Data" 10 | * SFB 901 "On-The-Fly Computing" 11 | * 12 | * University of Paderborn 13 | * Computer Engineering Group 14 | * Pohlweg 47 - 49 15 | * 33098 Paderborn 16 | * Germany 17 | * 18 | * 19 | * This file is free code: you can redistribute it and/or modify it under 20 | * the terms of the GNU Lesser General Public License version 2.1 as 21 | * published by the Free Software Foundation. 22 | * 23 | * This file is distributed in the hope that it will be useful, 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 | * GNU Lesser General Public License for more details. 27 | * 28 | * You should have received a copy of the GNU Lesser General Public License 29 | * along with this project. If not, see . 30 | */ 31 | 32 | `timescale 1ns / 1ps 33 | `default_nettype none 34 | 35 | module nf10_upb_clock_generator_tb; 36 | 37 | // 100 MHz input clock 38 | logic clk100_in = '0; 39 | always #5 clk100_in = ~clk100_in; 40 | 41 | logic async_reset_in_n = '1; 42 | 43 | wire clk_out, clk2x_out, clk2x90_out, clk100_out, reset_out, reset_n_out; 44 | 45 | 46 | nf10_upb_clock_generator #( 47 | 48 | .use_dci(1), 49 | .wait_for_dci_locked(1), 50 | .use_iodelay_control(1) 51 | 52 | ) clockgen_0 ( 53 | .* 54 | ); 55 | 56 | initial begin 57 | 58 | 59 | #100000000; // wait 100 ms 60 | 61 | async_reset_in_n <= '0; 62 | 63 | #100; // wait 100ns 64 | 65 | async_reset_in_n <= '1; 66 | 67 | #100000000; // wait 100 ms 68 | 69 | end 70 | 71 | endmodule 72 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/libsdn_dataplane/config_port_associations.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | * 6 | * Project Group "On-the-Fly Networking for Big Data" 7 | * SFB 901 "On-The-Fly Computing" 8 | * 9 | * University of Paderborn 10 | * Computer Engineering Group 11 | * Pohlweg 47 - 49 12 | * 33098 Paderborn 13 | * Germany 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the "License"); 16 | * you may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include 29 | #include 30 | 31 | namespace upb { 32 | 33 | constexpr uint8_t config_port_associations::egress_port_association[config_port_associations::netfpga_nic_virtual_ports]; 34 | constexpr uint8_t config_port_associations::egress_vport_association[config_port_associations::netfpga_nic_virtual_ports]; 35 | constexpr uint8_t config_port_associations::ingress_port_association[config_port_associations::netfpga_nic_virtual_ports]; 36 | constexpr uint8_t config_port_associations::ingress_vport_association[config_port_associations::netfpga_nic_virtual_ports]; 37 | constexpr const char* config_port_associations::port_friendly_names[config_port_associations::netfpga_nic_virtual_ports]; 38 | constexpr const char* config_port_associations::port_interface_names[config_port_associations::netfpga_nic_virtual_ports]; 39 | 40 | } 41 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_dummy_port_v1_00_a/hdl/verilog/nf10_upb_dummy_port.v: -------------------------------------------------------------------------------- 1 | /* 2 | * UPB Dummy Port core 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas 5 | * osjsn@niklasfamily.de 6 | * 7 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 8 | * 9 | * Project Group "On-the-Fly Networking for Big Data" 10 | * SFB 901 "On-The-Fly Computing" 11 | * 12 | * University of Paderborn 13 | * Computer Engineering Group 14 | * Pohlweg 47 - 49 15 | * 33098 Paderborn 16 | * Germany 17 | * 18 | * 19 | * This file is free code: you can redistribute it and/or modify it under 20 | * the terms of the GNU Lesser General Public License version 2.1 as 21 | * published by the Free Software Foundation. 22 | * 23 | * This file is distributed in the hope that it will be useful, 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 | * GNU Lesser General Public License for more details. 27 | * 28 | * You should have received a copy of the GNU Lesser General Public License 29 | * along with this project. If not, see . 30 | */ 31 | 32 | `default_nettype none 33 | 34 | module nf10_upb_dummy_port #( 35 | 36 | parameter peripheral_port_width = 32, 37 | parameter external_port_width = 32 38 | 39 | ) ( 40 | 41 | input wire [(peripheral_port_width-1):0] peripheral_connection_I, 42 | output wire [(peripheral_port_width-1):0] peripheral_connection_O, 43 | input wire [(peripheral_port_width-1):0] peripheral_connection_T, 44 | 45 | input wire [(external_port_width-1):0] external_connection_I, 46 | output wire [(external_port_width-1):0] external_connection_O, 47 | output wire [(external_port_width-1):0] external_connection_T 48 | 49 | ); 50 | 51 | assign external_connection_O = peripheral_connection_I; 52 | assign external_connection_T = peripheral_connection_T; 53 | assign peripheral_connection_O = external_connection_I; 54 | 55 | endmodule 56 | 57 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/sdntest/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | # 4 | # Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | # 6 | # Project Group "On-the-Fly Networking for Big Data" 7 | # SFB 901 "On-The-Fly Computing" 8 | # 9 | # University of Paderborn 10 | # Computer Engineering Group 11 | # Pohlweg 47 - 49 12 | # 33098 Paderborn 13 | # Germany 14 | # 15 | # Licensed under the Apache License, Version 2.0 (the "License"); 16 | # you may not use this file except in compliance with the License. 17 | # You may obtain a copy of the License at: 18 | # 19 | # http://www.apache.org/licenses/LICENSE-2.0 20 | # 21 | # Unless required by applicable law or agreed to in writing, software 22 | # distributed under the License is distributed on an "AS IS" BASIS, 23 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | # See the License for the specific language governing permissions and 25 | # limitations under the License. 26 | # 27 | 28 | SRCS = sdntest.cpp 29 | LIBPATHS = ../../lib 30 | INCLUDEPATHS = ../../include 31 | LIBS = sdn_dataplane_1.00 32 | EXEPATH = ../../bin 33 | EXE = $(EXEPATH)/sdntest 34 | OBJS = $(patsubst %.c,%.o,$(patsubst %.cpp,%.o,$(SRCS))) 35 | LIBMONITORPATHS = $(patsubst %,$(LIBPATHS)/lib%.la, $(OWNLIBS)) 36 | 37 | CXXFLAGS = -std=c++11 -DBOOST_ALL_DYN_LINK 38 | DBGCXXFLAGS = -g -O0 39 | RELCXXFLAGS = -O3 -DNDEBUG 40 | 41 | ifeq ($(DEBUG),1) 42 | CXXFLAGS += $(DBGCXXFLAGS) 43 | else 44 | CXXFLAGS += $(RELCXXFLAGS) 45 | endif 46 | 47 | .PHONY: all clean 48 | 49 | all: $(EXE) 50 | 51 | $(EXE): $(OBJS) $(LIBMONITORPATHS) 52 | @mkdir -p $(EXEPATH) 53 | @libtool --mode=link $(CXX) $(addprefix -L, $(LIBPATHS)) $(addprefix -l, $(LIBS)) -g -O -o $@ $^ 54 | 55 | -include $(patsubst %.cpp,%.d,$(SRCS)) 56 | 57 | $(OBJS): $(SRCS) 58 | $(CXX) $(CXXFLAGS) -MD -MP $(addprefix -I, $(INCLUDEPATHS)) -c -o $@ $< 59 | 60 | clean: 61 | rm -f $(EXE) $(OBJS) 62 | 63 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/src/flashprog/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # NetFPGA-10G http://www.netfpga.org 4 | # 5 | # File: 6 | # Makefile 7 | # 8 | # Project: 9 | # nic 10 | # 11 | # Author: 12 | # Jong Han 13 | # 14 | # Description: 15 | # NF10 Netfpga Configuration. 16 | # 17 | # 18 | # Copyright notice: 19 | # Copyright (C) 2013 University of Cambridge 20 | # 21 | # Licence: 22 | # This file is part of the NetFPGA 10G development base package. 23 | # 24 | # This file is free code: you can redistribute it and/or modify it under 25 | # the terms of the GNU Lesser General Public License version 2.1 as 26 | # published by the Free Software Foundation. 27 | # 28 | # This package is distributed in the hope that it will be useful, but 29 | # WITHOUT ANY WARRANTY; without even the implied warranty of 30 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 31 | # Lesser General Public License for more details. 32 | # 33 | # You should have received a copy of the GNU Lesser General Public 34 | # License along with the NetFPGA source package. If not, see 35 | # http://www.gnu.org/licenses/. 36 | # 37 | # 38 | 39 | all: nf10_configure 40 | 41 | nf10_configure: 42 | gcc nf10_configure.c ../../../../../xilinx/drivers/emc_v4_00_a/src/emc_flash_lib.c reg_lib.c -I . -I ../../../../../xilinx/drivers/emc_v4_00_a/src -o ../../bin/nf10_configure 43 | gcc nf10_flash_a.c ../../../../../xilinx/drivers/emc_v4_00_a/src/emc_flash_lib.c reg_lib.c -I . -I ../../../../../xilinx/drivers/emc_v4_00_a/src -o ../../bin/nf10_flash_a 44 | gcc nf10_flash_b.c ../../../../../xilinx/drivers/emc_v4_00_a/src/emc_flash_lib.c reg_lib.c -I . -I ../../../../../xilinx/drivers/emc_v4_00_a/src -o ../../bin/nf10_flash_b 45 | 46 | clean: 47 | rm -f ../../bin/nf10_configure ../../bin/nf10_flash_a ../../bin/nf10_flash_b 48 | 49 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_chipscope_icon_v1_00_a/data/nf10_upb_chipscope_icon_v2_1_0.mpd: -------------------------------------------------------------------------------- 1 | # UPB ChipScope ICON core 2 | # 3 | # Copyright (c) 2014, 2015 Jörg Niklas 4 | # osjsn@niklasfamily.de 5 | # 6 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 7 | # 8 | # Project Group "On-the-Fly Networking for Big Data" 9 | # SFB 901 "On-The-Fly Computing" 10 | # 11 | # University of Paderborn 12 | # Computer Engineering Group 13 | # Pohlweg 47 - 49 14 | # 33098 Paderborn 15 | # Germany 16 | # 17 | # 18 | # This file is free code: you can redistribute it and/or modify it under 19 | # the terms of the GNU Lesser General Public License version 2.1 as 20 | # published by the Free Software Foundation. 21 | # 22 | # This file is distributed in the hope that it will be useful, 23 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 24 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 | # GNU Lesser General Public License for more details. 26 | # 27 | # You should have received a copy of the GNU Lesser General Public License 28 | # along with this project. If not, see . 29 | # 30 | 31 | BEGIN nf10_upb_chipscope_icon 32 | 33 | OPTION IPTYPE = PERIPHERAL 34 | OPTION STYLE = MIX 35 | OPTION IMP_NETLIST = TRUE 36 | OPTION HDL = VERILOG 37 | OPTION IP_GROUP = UPB 38 | OPTION DESC = NetFPGA-10G UPB ICON/ILA Core 39 | 40 | PARAMETER icon_ports = 1, DT = integer, RANGE = (1:6) 41 | 42 | PORT control0 = "", DIR = IO, THREE_STATE = FALSE, VEC = [35:0], ASSIGNMENT = REQUIRE 43 | PORT control1 = "", DIR = IO, THREE_STATE = FALSE, VEC = [35:0], ISVALID = (icon_ports > 1) 44 | PORT control2 = "", DIR = IO, THREE_STATE = FALSE, VEC = [35:0], ISVALID = (icon_ports > 2) 45 | PORT control3 = "", DIR = IO, THREE_STATE = FALSE, VEC = [35:0], ISVALID = (icon_ports > 3) 46 | PORT control4 = "", DIR = IO, THREE_STATE = FALSE, VEC = [35:0], ISVALID = (icon_ports > 4) 47 | PORT control5 = "", DIR = IO, THREE_STATE = FALSE, VEC = [35:0], ISVALID = (icon_ports > 5) 48 | 49 | END 50 | 51 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_ofswitch_v1_00_a/doc/clear_cam.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python2 2 | 3 | """ 4 | * Copyright (c) 2014, 2015 Felix Wallaschek 5 | * felix@elektronenversand.de 6 | * 7 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project: 8 | * 9 | * Project Group "On-the-Fly Networking for Big Data" 10 | * SFB 901 "On-The-Fly Computing" 11 | * 12 | * University of Paderborn 13 | * Computer Engineering Group 14 | * Pohlweg 47 - 49 15 | * 33098 Paderborn 16 | * Germany 17 | * 18 | * 19 | * This file is free code: you can redistribute it and/or modify it under 20 | * the terms of the GNU Lesser General Public License version 2.1 as 21 | * published by the Free Software Foundation. 22 | * 23 | * This file is distributed in the hope that it will be useful, 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 | * GNU Lesser General Public License for more details. 27 | * 28 | * You should have received a copy of the GNU Lesser General Public License 29 | * along with this project. If not, see . 30 | 31 | Parameter for this script is NetFPGA-10G interface. 32 | """ 33 | 34 | from tuple_calculator import tuple_funs 35 | import subprocess 36 | import sys 37 | WRAXI = "../../../../../../contrib-projects/upb_openflowswitch/sw/wraxi" 38 | RDAXI = "../../../../../../contrib-projects/upb_openflowswitch/sw/rdaxi" 39 | dev = sys.argv[1] 40 | num_entries = int(tuple_funs.td(subprocess.check_output("sudo "+RDAXI+" "+dev+" 0xB0000008",shell=True).strip().split("=")[1])) 41 | print "Deleting CAM Contents. This might take a while..." 42 | sys.stdout.write(" 0/"+str(num_entries)) 43 | for i in range(0,num_entries): 44 | cmds = tuple_funs.gen_wr_commands(0,0,dev=dev,cmd = WRAXI, hashh=i) 45 | sys.stdout.write("\b\b\b\b\b"+("\b"*len(str(num_entries)))+str(i+1).rjust(4)+"/"+str(num_entries)) 46 | sys.stdout.flush() 47 | for cmd in cmds: 48 | subprocess.check_output(cmd.split()) 49 | print "" 50 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_interconnect_v1_00_a/chipscope/gen_nf10_upb_aurora_input_cdc.py: -------------------------------------------------------------------------------- 1 | data_bit = 0 2 | def data(name, count = 1): 3 | for i in range (0,count): 4 | global data_bit 5 | print ("Project.unit.0.data<" + str(data_bit) + ">=" + name + ("" if count == 1 else "[" + str(i) + "]")) 6 | data_bit = data_bit + 1 7 | 8 | trig_bit = 0 9 | def trig(name, count = 1): 10 | for i in range (0,count): 11 | global trig_bit 12 | print ("Project.unit.0.trigger<" + str(trig_bit) + ">=" + name + ("" if count == 1 else "[" + str(i) + "]")) 13 | trig_bit = trig_bit + 1 14 | 15 | print ("#ChipScope Core Inserter Project Version 2.0") 16 | 17 | data("channel_up_i") 18 | data("lane_up_i", 10) 19 | data("soft_err_i") 20 | data("hard_err_i") 21 | data("tx_stopped") 22 | data("m_axis_tvalid") 23 | data("m_axis_tlast") 24 | data("m_axis_tkeep", 32) 25 | data("s_axis_tvalid") 26 | data("s_axis_tready") 27 | data("s_axis_tlast") 28 | data("s_axis_tkeep", 32) 29 | data("flow_control_pause_req") 30 | data("flow_control_pause_val") 31 | data("error") 32 | data("tx_d_i",320) 33 | data("tx_src_rdy_n_i") 34 | data("tx_dst_rdy_n_i") 35 | data("rx_d_i", 320) 36 | data("rx_src_rdy_n_i") 37 | 38 | data("err_tvalid_deasserted_0"); 39 | data("err_tkeep_encoded_wrong_0"); 40 | data("err_tkeep_not_continuous_0"); 41 | data("err_too_big_0"); 42 | data("err_too_small_0"); 43 | 44 | data("err_tvalid_deasserted_1"); 45 | data("err_tkeep_encoded_wrong_1"); 46 | data("err_tkeep_not_continuous_1"); 47 | data("err_too_big_1"); 48 | data("err_too_small_1"); 49 | 50 | print ("Project.unit.0.dataWidth=1024") 51 | 52 | trig("channel_up_i") 53 | trig("soft_err_i") 54 | trig("hard_err_i") 55 | trig("tx_stopped") 56 | trig("m_axis_tvalid") 57 | trig("m_axis_tlast") 58 | trig("s_axis_tvalid") 59 | trig("s_axis_tready") 60 | trig("s_axis_tlast") 61 | trig("flow_control_pause_req") 62 | trig("flow_control_pause_val") 63 | trig("tx_src_rdy_n_i") 64 | trig("tx_dst_rdy_n_i") 65 | trig("rx_src_rdy_n_i") 66 | trig("axis_error_0") 67 | trig("axis_error_1") 68 | 69 | print ("Project.unit.0.triggerWidth=16") 70 | 71 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_switch_v1_00_a/hdl/SystemVerilog/delay.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2014, 2015 Felix Wallaschek 3 | * felix@elektronenversand.de 4 | * 5 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project: 6 | * 7 | * Project Group "On-the-Fly Networking for Big Data" 8 | * SFB 901 "On-The-Fly Computing" 9 | * 10 | * University of Paderborn 11 | * Computer Engineering Group 12 | * Pohlweg 47 - 49 13 | * 33098 Paderborn 14 | * Germany 15 | * 16 | * 17 | * This file is free code: you can redistribute it and/or modify it under 18 | * the terms of the GNU Lesser General Public License version 2.1 as 19 | * published by the Free Software Foundation. 20 | * 21 | * This file is distributed in the hope that it will be useful, 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 | * GNU Lesser General Public License for more details. 25 | * 26 | * You should have received a copy of the GNU Lesser General Public License 27 | * along with this project. If not, see . 28 | */ 29 | 30 | module delay 31 | #( 32 | parameter C_DATA_WIDTH=310, 33 | parameter C_DELAY_CYCLES=5 34 | ) 35 | ( 36 | input clk, 37 | input reset, 38 | input en, 39 | input [C_DATA_WIDTH-1:0] data_in, 40 | output [C_DATA_WIDTH-1:0] data_out 41 | ); 42 | function integer log2; 43 | input integer number; 44 | begin 45 | log2=0; 46 | while(2**log2=C_DELAY_CYCLES) addr <= 0; 64 | end 65 | end 66 | endmodule 67 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_interconnect_v1_00_a/Makefile: -------------------------------------------------------------------------------- 1 | 2 | COREGEN_DIR:= coregen 3 | 4 | install: hdl/verilog/aurora/aurora_8b10b_v5_3.v netlist/nf10_upb_interconnect.edf 5 | 6 | .NOTPARALLEL: hdl/verilog/aurora/aurora_8b10b_v5_3.v netlist/nf10_upb_interconnect.edf 7 | 8 | hdl/verilog/aurora/aurora_8b10b_v5_3.v: xco/aurora_8b10b_v5_3.xco 9 | @mkdir -p netlist; 10 | @mkdir -p $(COREGEN_DIR); 11 | @cd $(COREGEN_DIR) && coregen -b ../xco/aurora_8b10b_v5_3.xco 12 | @cp $(COREGEN_DIR)/aurora_8b10b_v5_3.v hdl/verilog/aurora 13 | @cp $(COREGEN_DIR)/aurora_8b10b_v5_3/src/*.v hdl/verilog/aurora 14 | @cp $(COREGEN_DIR)/aurora_8b10b_v5_3/example_design/cc_manager/aurora_8b10b_v5_3_standard_cc_module.v hdl/verilog/aurora 15 | @cp $(COREGEN_DIR)/aurora_8b10b_v5_3/example_design/clock_module/aurora_8b10b_v5_3_clock_module.v hdl/verilog/aurora 16 | @cp $(COREGEN_DIR)/aurora_8b10b_v5_3/example_design/gt/aurora_8b10b_v5_3_tile.v hdl/verilog/aurora 17 | @cp $(COREGEN_DIR)/aurora_8b10b_v5_3/example_design/gt/aurora_8b10b_v5_3_transceiver_wrapper.v hdl/verilog/aurora 18 | @cp $(COREGEN_DIR)/aurora_8b10b_v5_3/example_design/aurora_8b10b_v5_3_reset_logic.v hdl/verilog/aurora 19 | @patch hdl/verilog/aurora/aurora_8b10b_v5_3_reset_logic.v hdl/verilog/aurora/aurora_8b10b_v5_3_reset_logic.patch 20 | @echo "/////////////////////////////////////////"; 21 | @echo "//Aurora core installed."; 22 | @echo "/////////////////////////////////////////"; 23 | @rm -rf $(COREGEN_DIR); 24 | 25 | netlist/nf10_upb_interconnect.edf: 26 | cd prj/synplify && $(SYNPLIFY_CMD) -batch interconnect.prj 27 | mkdir -p netlist 28 | cp prj/synplify/nf10_upb_interconnect/nf10_upb_interconnect.edf netlist/ 29 | @echo "/////////////////////////////////////////"; 30 | @echo "//Interconnect edif created."; 31 | @echo "/////////////////////////////////////////"; 32 | 33 | clean: 34 | @rm -rf $(COREGEN_DIR); 35 | @rm -rf netlist; 36 | @rm -rf hdl/verilog/aurora/*.v 37 | @echo "/////////////////////////////////////////"; 38 | @echo "//Xilinx files removed."; 39 | @echo "/////////////////////////////////////////"; 40 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_interconnect_v1_00_a/chipscope/gen_nf10_upb_interconnect_cdc.py: -------------------------------------------------------------------------------- 1 | data_bit = 0 2 | def data(name, count = 1): 3 | for i in range (0,count): 4 | global data_bit 5 | print ("Project.unit.0.data<" + str(data_bit) + ">=" + name + ("" if count == 1 else "[" + str(i) + "]")) 6 | data_bit = data_bit + 1 7 | 8 | trig_bit = 0 9 | def trig(name, count = 1): 10 | for i in range (0,count): 11 | global trig_bit 12 | print ("Project.unit.0.trigger<" + str(trig_bit) + ">=" + name + ("" if count == 1 else "[" + str(i) + "]")) 13 | trig_bit = trig_bit + 1 14 | 15 | print ("#ChipScope Core Inserter Project Version 2.0") 16 | 17 | data("pa_fifo_di", 256) 18 | data("pa_fifo_mi", 19) 19 | data("pa_fifo_wren") 20 | data("pa_fifo_commit") 21 | data("pa_fifo_revert") 22 | data("pa_fifo_mo", 19) 23 | data("pa_fifo_eop") 24 | data("pa_fifo_full") 25 | data("pa_fifo_empty") 26 | data("pa_fifo_below_low") 27 | data("pa_fifo_above_high") 28 | data("wide_fifo_error") 29 | data("wide_fifo_dop", 32) 30 | data("wide_fifo_empty") 31 | data("wide_fifo_almost_emtpy") 32 | data("dropping") 33 | data("pkt_length", 14) 34 | data("next_pkt_length", 14) 35 | data("length_check_ok") 36 | data("wide_fifo_pkt_length", 14) 37 | data("wide_fifo_almost_full_reg") 38 | data("wide_fifo_rderr") 39 | data("wide_fifo_wrerr") 40 | data("pa_fifo_rderr") 41 | data("pa_fifo_wrerr") 42 | data("wide_fifo_full") 43 | 44 | data("err_tvalid_deasserted_0"); 45 | data("err_tkeep_encoded_wrong_0"); 46 | data("err_tkeep_not_continuous_0"); 47 | data("err_too_big_0"); 48 | data("err_too_small_0"); 49 | 50 | print ("Project.unit.0.dataWidth=512") 51 | 52 | trig("wide_fifo_error") 53 | trig("wide_fifo_empty") 54 | trig("dropping") 55 | trig("length_check_ok") 56 | trig("pa_fifo_wren") 57 | trig("pa_fifo_commit") 58 | trig("pa_fifo_revert") 59 | trig("pa_fifo_full") 60 | trig("pa_fifo_empty") 61 | trig("pa_fifo_below_low") 62 | trig("pa_fifo_above_high") 63 | trig("wide_fifo_rdwrerr") 64 | trig("pa_fifo_rdwrerr") 65 | trig("wide_fifo_full") 66 | trig("axis_error_0") 67 | 68 | print ("Project.unit.0.triggerWidth=16") 69 | 70 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/prj/qdr2_test_netfpga/ipcore_dir/vio_main.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Wed Mar 19 16:42:17 2014 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:chipscope_vio:1.05.a 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc5vtx240t 26 | SET devicefamily = virtex5 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ff1759 32 | SET removerpms = false 33 | SET simulationfiles = Structural 34 | SET speedgrade = -2 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a 40 | # END Select 41 | # BEGIN Parameters 42 | CSET asynchronous_input_port_width=9 43 | CSET asynchronous_output_port_width=2 44 | CSET component_name=vio_main 45 | CSET constraint_type=external 46 | CSET enable_asynchronous_input_port=true 47 | CSET enable_asynchronous_output_port=true 48 | CSET enable_synchronous_input_port=false 49 | CSET enable_synchronous_output_port=false 50 | CSET example_design=false 51 | CSET invert_clock_input=false 52 | CSET synchronous_input_port_width=8 53 | CSET synchronous_output_port_width=8 54 | # END Parameters 55 | # BEGIN Extra information 56 | MISC pkg_timestamp=2013-10-13T14:13:48Z 57 | # END Extra information 58 | GENERATE 59 | # CRC: 760a66bf 60 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_axi_stream_chipscope_v1_00_a/prj/nf10_upb_axi_stream_chipscope.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/jsn/repos/upb/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_axi_stream_chipscope_v1_00_a/prj/f10_upb_axi_stream_chipscope.prj 4 | #-- Written on Fri Oct 3 12:03:50 2014 5 | 6 | 7 | #project files 8 | add_file -verilog "../../nf10_upb_lib/hdl/SystemVerilog/axis_conform_check.v" 9 | add_file -verilog "../hdl/verilog/nf10_upb_axi_stream_chipscope.v" 10 | 11 | 12 | #implementation: "netlist" 13 | impl -add netlist -type fpga 14 | 15 | # 16 | #implementation attributes 17 | 18 | set_option -vlog_std sysv 19 | set_option -project_relative_includes 1 20 | 21 | #device options 22 | set_option -technology Virtex5 23 | set_option -part XC5VTX240T 24 | set_option -package FF1759 25 | set_option -speed_grade -2 26 | set_option -part_companion "" 27 | 28 | #compilation/mapping options 29 | set_option -use_fsm_explorer 1 30 | 31 | # mapper_options 32 | set_option -frequency auto 33 | set_option -write_verilog 0 34 | set_option -write_vhdl 0 35 | set_option -srs_instrumentation 1 36 | 37 | # xilinx_options 38 | set_option -RWCheckOnRam 1 39 | 40 | # Xilinx Virtex2 41 | set_option -run_prop_extract 1 42 | set_option -maxfan 10000 43 | set_option -disable_io_insertion 1 44 | set_option -pipe 1 45 | set_option -update_models_cp 0 46 | set_option -retiming 1 47 | set_option -no_sequential_opt 0 48 | set_option -fix_gated_and_generated_clocks 1 49 | 50 | # Xilinx Virtex5 51 | set_option -enable_prepacking 1 52 | 53 | # sequential_optimization_options 54 | set_option -symbolic_fsm_compiler 1 55 | 56 | # Compiler Options 57 | set_option -compiler_compatible 0 58 | set_option -resource_sharing 1 59 | set_option -multi_file_compilation_unit 1 60 | 61 | #VIF options 62 | set_option -write_vif 0 63 | 64 | #automatic place and route (vendor) options 65 | set_option -write_apr_constraint 1 66 | 67 | #set result format/file last 68 | project -result_file "../netlist/nf10_upb_axi_stream_chipscope.edf" 69 | 70 | #design plan options 71 | impl -active "netlist" 72 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/src/nic_driver/nf10iface.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * NetFPGA-10G http://www.netfpga.org 4 | * 5 | * File: 6 | * nf10iface.h 7 | * 8 | * Project: 9 | * nic 10 | * 11 | * Author: 12 | * Mario Flajslik 13 | * 14 | * Modifications for the UPB OpenFlow Switch project: 15 | * Jörg Niklas, osjsn@niklasfamily.de 16 | * Project Group "On-the-Fly Networking for Big Data" 17 | * Computer Engineering Group, University of Paderborn 18 | * 19 | * Description: 20 | * Header file for the interfaces. Contains MTU definitino. 21 | * 22 | * Copyright notice: 23 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 24 | * Junior University 25 | * 26 | * Modifications for the UPB OpenFlow Switch project: 27 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 28 | * 29 | * Licence: 30 | * This file is part of the NetFPGA 10G development base package. 31 | * 32 | * This file is free code: you can redistribute it and/or modify it under 33 | * the terms of the GNU Lesser General Public License version 2.1 as 34 | * published by the Free Software Foundation. 35 | * 36 | * This package is distributed in the hope that it will be useful, but 37 | * WITHOUT ANY WARRANTY; without even the implied warranty of 38 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 39 | * Lesser General Public License for more details. 40 | * 41 | * You should have received a copy of the GNU Lesser General Public 42 | * License along with the NetFPGA source package. If not, see 43 | * http://www.gnu.org/licenses/. 44 | * 45 | */ 46 | 47 | #ifndef NF10IFACE_H 48 | #define NF10IFACE_H 49 | 50 | #include 51 | #include "nf10driver.h" 52 | 53 | int nf10iface_probe(struct pci_dev *pdev, struct nf10_card *card); 54 | int nf10iface_remove(struct pci_dev *pdev, struct nf10_card *card); 55 | 56 | #endif 57 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_dma_v1_00_a/hdl/SystemVerilog/README: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # NetFPGA-10G http://www.netfpga.org 4 | # 5 | # File: 6 | # README 7 | # 8 | # Library: 9 | # hw/contrib/pcores/dma_v1_00_a 10 | # 11 | # Author: 12 | # Mario Flajslik 13 | # 14 | # Description: 15 | # Readme for the SystemVerilog source code. 16 | # 17 | # For more information about how Xilinx EDK works, please visit 18 | # http://www.xilinx.com/support/documentation/dt_edk.htm 19 | # 20 | # Copyright notice: 21 | # Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 22 | # Junior University 23 | # 24 | # Licence: 25 | # This file is part of the NetFPGA 10G development base package. 26 | # 27 | # This file is free code: you can redistribute it and/or modify it under 28 | # the terms of the GNU Lesser General Public License version 2.1 as 29 | # published by the Free Software Foundation. 30 | # 31 | # This package is distributed in the hope that it will be useful, but 32 | # WITHOUT ANY WARRANTY; without even the implied warranty of 33 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 34 | # Lesser General Public License for more details. 35 | # 36 | # You should have received a copy of the GNU Lesser General Public 37 | # License along with the NetFPGA source package. If not, see 38 | # http://www.gnu.org/licenses/. 39 | # 40 | # 41 | 42 | These are SystemVerilog source files that were used to generate the 43 | dma_engine.edf netlist (250MHz version). They are provided for documentation 44 | purposes only, and changing these files will have no effect on the pcore, 45 | unless a new netlist is synthesised. One can do that with any tool that supports 46 | SystemVerilog. Throughout the code only three features of SystemVerilog are 47 | used: 'logic' type, 'always_ff' and 'always_comb' constructs. 48 | 49 | A mapped verilog file (as generated by synopsis tool) of the dma engine is 50 | provided under name dma_engine.vm. -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/prj/nf10_upb_input_arbiter_5.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/felixw/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/prj/nf10_upb_input_arbiter_all.prj 4 | 5 | #project files 6 | add_file -verilog "../hdl/verilog/nf10_upb_input_arbiter_flex.v" 7 | add_file -verilog "../hdl/verilog/nf10_upb_input_arbiter.v" 8 | add_file -constraint "./nf10_upb_input_arbiter.sdc" 9 | 10 | 11 | 12 | #implementation: "nf10_upb_input_arbiter_5" 13 | impl -add nf10_upb_input_arbiter_5 -type fpga 14 | 15 | # 16 | #implementation attributes 17 | 18 | set_option -vlog_std v2001 19 | set_option -num_critical_paths 0 20 | set_option -num_startend_points 0 21 | 22 | # 23 | #implementation parameter settings 24 | set_option -hdl_param -set C_NUM_INPUTS 5 25 | 26 | #device options 27 | set_option -technology Virtex5 28 | set_option -part XC5VTX240T 29 | set_option -package FF1759 30 | set_option -speed_grade -2 31 | set_option -part_companion "" 32 | 33 | #compilation/mapping options 34 | set_option -use_fsm_explorer 0 35 | set_option -top_module "nf10_upb_input_arbiter" 36 | 37 | # mapper_options 38 | set_option -frequency auto 39 | set_option -write_verilog 0 40 | set_option -write_vhdl 0 41 | set_option -srs_instrumentation 1 42 | 43 | # xilinx_options 44 | set_option -RWCheckOnRam 1 45 | 46 | # Xilinx Virtex2 47 | set_option -run_prop_extract 1 48 | set_option -maxfan 100 49 | set_option -disable_io_insertion 1 50 | set_option -pipe 1 51 | set_option -update_models_cp 0 52 | set_option -retiming 1 53 | set_option -no_sequential_opt 0 54 | set_option -fix_gated_and_generated_clocks 1 55 | 56 | # Xilinx Virtex5 57 | set_option -enable_prepacking 1 58 | 59 | # sequential_optimization_options 60 | set_option -symbolic_fsm_compiler 1 61 | 62 | # Compiler Options 63 | set_option -compiler_compatible 1 64 | set_option -resource_sharing 1 65 | 66 | #VIF options 67 | set_option -write_vif 0 68 | 69 | #automatic place and route (vendor) options 70 | set_option -write_apr_constraint 1 71 | 72 | #set result format/file last 73 | project -result_file "../netlist/5_ports/nf10_upb_input_arbiter.edf" 74 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/prj/nf10_upb_input_arbiter_7.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/felixw/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/prj/nf10_upb_input_arbiter_all.prj 4 | 5 | #project files 6 | add_file -verilog "../hdl/verilog/nf10_upb_input_arbiter_flex.v" 7 | add_file -verilog "../hdl/verilog/nf10_upb_input_arbiter.v" 8 | add_file -constraint "./nf10_upb_input_arbiter.sdc" 9 | 10 | 11 | 12 | #implementation: "nf10_upb_input_arbiter_7" 13 | impl -add nf10_upb_input_arbiter_7 -type fpga 14 | 15 | # 16 | #implementation attributes 17 | 18 | set_option -vlog_std v2001 19 | set_option -num_critical_paths 0 20 | set_option -num_startend_points 0 21 | 22 | # 23 | #implementation parameter settings 24 | set_option -hdl_param -set C_NUM_INPUTS 7 25 | 26 | #device options 27 | set_option -technology Virtex5 28 | set_option -part XC5VTX240T 29 | set_option -package FF1759 30 | set_option -speed_grade -2 31 | set_option -part_companion "" 32 | 33 | #compilation/mapping options 34 | set_option -use_fsm_explorer 0 35 | set_option -top_module "nf10_upb_input_arbiter" 36 | 37 | # mapper_options 38 | set_option -frequency auto 39 | set_option -write_verilog 0 40 | set_option -write_vhdl 0 41 | set_option -srs_instrumentation 1 42 | 43 | # xilinx_options 44 | set_option -RWCheckOnRam 1 45 | 46 | # Xilinx Virtex2 47 | set_option -run_prop_extract 1 48 | set_option -maxfan 100 49 | set_option -disable_io_insertion 1 50 | set_option -pipe 1 51 | set_option -update_models_cp 0 52 | set_option -retiming 1 53 | set_option -no_sequential_opt 0 54 | set_option -fix_gated_and_generated_clocks 1 55 | 56 | # Xilinx Virtex5 57 | set_option -enable_prepacking 1 58 | 59 | # sequential_optimization_options 60 | set_option -symbolic_fsm_compiler 1 61 | 62 | # Compiler Options 63 | set_option -compiler_compatible 1 64 | set_option -resource_sharing 1 65 | 66 | #VIF options 67 | set_option -write_vif 0 68 | 69 | #automatic place and route (vendor) options 70 | set_option -write_apr_constraint 1 71 | 72 | #set result format/file last 73 | project -result_file "../netlist/7_ports/nf10_upb_input_arbiter.edf" 74 | 75 | #design plan options 76 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/prj/nf10_upb_input_arbiter_4.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/felixw/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/prj/nf10_upb_input_arbiter_all.prj 4 | 5 | #project files 6 | add_file -verilog "../hdl/verilog/nf10_upb_input_arbiter_flex.v" 7 | add_file -verilog "../hdl/verilog/nf10_upb_input_arbiter.v" 8 | add_file -constraint "./nf10_upb_input_arbiter.sdc" 9 | 10 | 11 | 12 | #implementation: "nf10_upb_input_arbiter_4" 13 | impl -add nf10_upb_input_arbiter_4 -type fpga 14 | 15 | 16 | # 17 | #implementation attributes 18 | 19 | set_option -vlog_std v2001 20 | set_option -num_critical_paths 0 21 | set_option -num_startend_points 0 22 | 23 | # 24 | #implementation parameter settings 25 | set_option -hdl_param -set C_NUM_INPUTS 4 26 | 27 | #device options 28 | set_option -technology Virtex5 29 | set_option -part XC5VTX240T 30 | set_option -package FF1759 31 | set_option -speed_grade -2 32 | set_option -part_companion "" 33 | 34 | #compilation/mapping options 35 | set_option -use_fsm_explorer 0 36 | set_option -top_module "nf10_upb_input_arbiter" 37 | 38 | # mapper_options 39 | set_option -frequency auto 40 | set_option -write_verilog 0 41 | set_option -write_vhdl 0 42 | set_option -srs_instrumentation 1 43 | 44 | # xilinx_options 45 | set_option -RWCheckOnRam 1 46 | 47 | # Xilinx Virtex2 48 | set_option -run_prop_extract 1 49 | set_option -maxfan 100 50 | set_option -disable_io_insertion 1 51 | set_option -pipe 1 52 | set_option -update_models_cp 0 53 | set_option -retiming 1 54 | set_option -no_sequential_opt 0 55 | set_option -fix_gated_and_generated_clocks 1 56 | 57 | # Xilinx Virtex5 58 | set_option -enable_prepacking 1 59 | 60 | # sequential_optimization_options 61 | set_option -symbolic_fsm_compiler 1 62 | 63 | # Compiler Options 64 | set_option -compiler_compatible 1 65 | set_option -resource_sharing 1 66 | 67 | #VIF options 68 | set_option -write_vif 0 69 | 70 | #automatic place and route (vendor) options 71 | set_option -write_apr_constraint 1 72 | 73 | #set result format/file last 74 | project -result_file "../netlist/4_ports/nf10_upb_input_arbiter.edf" 75 | 76 | #design plan options 77 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/prj/nf10_upb_input_arbiter_6.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/felixw/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/prj/nf10_upb_input_arbiter_all.prj 4 | 5 | #project files 6 | add_file -verilog "../hdl/verilog/nf10_upb_input_arbiter_flex.v" 7 | add_file -verilog "../hdl/verilog/nf10_upb_input_arbiter.v" 8 | add_file -constraint "./nf10_upb_input_arbiter.sdc" 9 | 10 | 11 | #implementation: "nf10_upb_input_arbiter_6" 12 | impl -add nf10_upb_input_arbiter_6 -type fpga 13 | 14 | # 15 | #implementation attributes 16 | 17 | set_option -vlog_std v2001 18 | set_option -num_critical_paths 0 19 | set_option -num_startend_points 0 20 | 21 | # 22 | #implementation parameter settings 23 | set_option -hdl_param -set C_NUM_INPUTS 6 24 | 25 | #device options 26 | set_option -technology Virtex5 27 | set_option -part XC5VTX240T 28 | set_option -package FF1759 29 | set_option -speed_grade -2 30 | set_option -part_companion "" 31 | 32 | #compilation/mapping options 33 | set_option -use_fsm_explorer 0 34 | set_option -top_module "nf10_upb_input_arbiter" 35 | 36 | # mapper_options 37 | set_option -frequency auto 38 | set_option -write_verilog 0 39 | set_option -write_vhdl 0 40 | set_option -srs_instrumentation 1 41 | 42 | # xilinx_options 43 | set_option -RWCheckOnRam 1 44 | 45 | # Xilinx Virtex2 46 | set_option -run_prop_extract 1 47 | set_option -maxfan 100 48 | set_option -disable_io_insertion 1 49 | set_option -pipe 1 50 | set_option -update_models_cp 0 51 | set_option -retiming 1 52 | set_option -no_sequential_opt 0 53 | set_option -fix_gated_and_generated_clocks 1 54 | 55 | # Xilinx Virtex5 56 | set_option -enable_prepacking 1 57 | 58 | # sequential_optimization_options 59 | set_option -symbolic_fsm_compiler 1 60 | 61 | # Compiler Options 62 | set_option -compiler_compatible 1 63 | set_option -resource_sharing 1 64 | 65 | #VIF options 66 | set_option -write_vif 0 67 | 68 | #automatic place and route (vendor) options 69 | set_option -write_apr_constraint 1 70 | 71 | #set result format/file last 72 | project -result_file "../netlist/6_ports/nf10_upb_input_arbiter.edf" 73 | 74 | #design plan options 75 | 76 | 77 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/prj/nf10_upb_input_arbiter_8.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/felixw/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/prj/nf10_upb_input_arbiter_all.prj 4 | 5 | #project files 6 | add_file -verilog "../hdl/verilog/nf10_upb_input_arbiter_flex.v" 7 | add_file -verilog "../hdl/verilog/nf10_upb_input_arbiter.v" 8 | add_file -constraint "./nf10_upb_input_arbiter.sdc" 9 | 10 | 11 | 12 | #implementation: "nf10_upb_input_arbiter_8" 13 | impl -add nf10_upb_input_arbiter_8 -type fpga 14 | 15 | # 16 | #implementation attributes 17 | 18 | set_option -vlog_std v2001 19 | set_option -num_critical_paths 0 20 | set_option -num_startend_points 0 21 | 22 | # 23 | #implementation parameter settings 24 | set_option -hdl_param -set C_NUM_INPUTS 8 25 | 26 | #device options 27 | set_option -technology Virtex5 28 | set_option -part XC5VTX240T 29 | set_option -package FF1759 30 | set_option -speed_grade -2 31 | set_option -part_companion "" 32 | 33 | #compilation/mapping options 34 | set_option -use_fsm_explorer 0 35 | set_option -top_module "nf10_upb_input_arbiter" 36 | 37 | # mapper_options 38 | set_option -frequency auto 39 | set_option -write_verilog 0 40 | set_option -write_vhdl 0 41 | set_option -srs_instrumentation 1 42 | 43 | # xilinx_options 44 | set_option -RWCheckOnRam 1 45 | 46 | # Xilinx Virtex2 47 | set_option -run_prop_extract 1 48 | set_option -maxfan 100 49 | set_option -disable_io_insertion 1 50 | set_option -pipe 1 51 | set_option -update_models_cp 0 52 | set_option -retiming 1 53 | set_option -no_sequential_opt 0 54 | set_option -fix_gated_and_generated_clocks 1 55 | 56 | # Xilinx Virtex5 57 | set_option -enable_prepacking 1 58 | 59 | # sequential_optimization_options 60 | set_option -symbolic_fsm_compiler 1 61 | 62 | # Compiler Options 63 | set_option -compiler_compatible 1 64 | set_option -resource_sharing 1 65 | 66 | #VIF options 67 | set_option -write_vif 0 68 | 69 | #automatic place and route (vendor) options 70 | set_option -write_apr_constraint 1 71 | 72 | #set result format/file last 73 | project -result_file "../netlist/8_ports/nf10_upb_input_arbiter.edf" 74 | 75 | #design plan options 76 | 77 | 78 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_10g_interface_v1_00_a/data/nf10_upb_10g_interface_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # NetFPGA-10G http://www.netfpga.org 4 | # 5 | # File: 6 | # nf10_10g_interface_v2_1_0.pao 7 | # 8 | # Library: 9 | # hw/std/pcores/nf10_10g_interface_v1_20_a 10 | # 11 | # Author: 12 | # James Hongyi Zeng 13 | # 14 | # Description: 15 | # Peripheral Analyze Order File 16 | # 17 | # Copyright notice: 18 | # Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 19 | # Junior University 20 | # 21 | # Licence: 22 | # This file is part of the NetFPGA 10G development base package. 23 | # 24 | # This file is free code: you can redistribute it and/or modify it under 25 | # the terms of the GNU Lesser General Public License version 2.1 as 26 | # published by the Free Software Foundation. 27 | # 28 | # This package is distributed in the hope that it will be useful, but 29 | # WITHOUT ANY WARRANTY; without even the implied warranty of 30 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 31 | # Lesser General Public License for more details. 32 | # 33 | # You should have received a copy of the GNU Lesser General Public 34 | # License along with the NetFPGA source package. If not, see 35 | # http://www.gnu.org/licenses/. 36 | # 37 | # 38 | 39 | 40 | lib proc_common_v3_00_a all 41 | lib nf10_upb_10g_interface_v1_00_a xilinx/xaui_rocketio_wrapper.v verilog 42 | lib nf10_upb_10g_interface_v1_00_a xilinx/xaui_rocketio_wrapper_tile.v verilog 43 | lib nf10_upb_10g_interface_v1_00_a xilinx/xaui_block.v verilog 44 | lib nf10_upb_10g_interface_v1_00_a nf10/nf10_upb_10g_interface.v verilog 45 | lib nf10_upb_10g_interface_v1_00_a nf10/xgmac_to_axi_converter.v verilog 46 | lib nf10_upb_10g_interface_v1_00_a xilinx/xaui_tx_sync.v verilog 47 | lib nf10_upb_10g_interface_v1_00_a xilinx/xaui_chanbond_monitor.v verilog 48 | lib nf10_upb_10g_interface_v1_00_a xilinx/xaui_cc_2b_1skp.v verilog 49 | lib nf10_upb_10g_interface_v1_00_a xilinx/xgmac.v verilog 50 | lib nf10_upb_10g_interface_v1_00_a xilinx/xaui.v verilog 51 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/src/nic_driver/nf10priv.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * NetFPGA-10G http://www.netfpga.org 4 | * 5 | * File: 6 | * nf10priv.h 7 | * 8 | * Project: 9 | * nic 10 | * 11 | * Author: 12 | * Mario Flajslik 13 | * 14 | * Modifications for the UPB OpenFlow Switch project: 15 | * Jörg Niklas, osjsn@niklasfamily.de 16 | * Project Group "On-the-Fly Networking for Big Data" 17 | * Computer Engineering Group, University of Paderborn 18 | * 19 | * Description: 20 | * Prototypes for the tx/rx operation functions. 21 | * 22 | * Copyright notice: 23 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 24 | * Junior University 25 | * 26 | * Modifications for the UPB OpenFlow Switch project: 27 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 28 | * 29 | * Licence: 30 | * This file is part of the NetFPGA 10G development base package. 31 | * 32 | * This file is free code: you can redistribute it and/or modify it under 33 | * the terms of the GNU Lesser General Public License version 2.1 as 34 | * published by the Free Software Foundation. 35 | * 36 | * This package is distributed in the hope that it will be useful, but 37 | * WITHOUT ANY WARRANTY; without even the implied warranty of 38 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 39 | * Lesser General Public License for more details. 40 | * 41 | * You should have received a copy of the GNU Lesser General Public 42 | * License along with the NetFPGA source package. If not, see 43 | * http://www.gnu.org/licenses/. 44 | * 45 | */ 46 | 47 | #ifndef NF10PRIV_H 48 | #define NF10PRIV_H 49 | 50 | #include "nf10driver.h" 51 | 52 | netdev_tx_t nf10priv_xmit(struct nf10_card *card, struct sk_buff *skb, int port); 53 | void nf10_handle_rx_irq(struct nf10_card *card, unsigned int *work_done, unsigned int work_to_do); 54 | void nf10_handle_tx_irq(struct nf10_card *card); 55 | int nf10priv_send_rx_dsc(struct nf10_card *card); 56 | 57 | 58 | #endif 59 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_switch_v1_00_a/prj/nf10_upb_switch.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/felixw/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_switch_v1_00_a/prj/nf10_upb_switch.prj 4 | 5 | #project files 6 | add_file -verilog "../hdl/SystemVerilog/delay.v" 7 | add_file -verilog "../hdl/SystemVerilog/ram.v" 8 | add_file -verilog "../hdl/SystemVerilog/crc.v" 9 | add_file -verilog "../../nf10_upb_lib/hdl/SystemVerilog/qdr2_sram.v" 10 | add_file -verilog "../hdl/SystemVerilog/nf10_upb_switch.v" 11 | add_file -constraint "./nf10_upb_switch.sdc" 12 | 13 | 14 | #implementation: "prj" 15 | impl -add prj -type fpga 16 | 17 | # 18 | #implementation attributes 19 | 20 | set_option -vlog_std sysv 21 | set_option -num_critical_paths 0 22 | set_option -num_startend_points 0 23 | 24 | # 25 | #implementation parameter settings 26 | set_option -hdl_param -set dma_port_id 5 27 | 28 | #device options 29 | set_option -technology VIRTEX5 30 | set_option -part xc5vtx240t 31 | set_option -package ff1759 32 | set_option -speed_grade -2 33 | set_option -part_companion "" 34 | 35 | #compilation/mapping options 36 | set_option -use_fsm_explorer 0 37 | set_option -top_module "nf10_upb_switch" 38 | 39 | # mapper_options 40 | set_option -frequency auto 41 | set_option -write_verilog 0 42 | set_option -write_vhdl 0 43 | set_option -srs_instrumentation 1 44 | 45 | # xilinx_options 46 | set_option -RWCheckOnRam 1 47 | 48 | # Xilinx Virtex2 49 | set_option -run_prop_extract 1 50 | set_option -maxfan 100 51 | set_option -disable_io_insertion 1 52 | set_option -pipe 1 53 | set_option -update_models_cp 0 54 | set_option -retiming 1 55 | set_option -no_sequential_opt 0 56 | set_option -fix_gated_and_generated_clocks 1 57 | 58 | # Xilinx Virtex5 59 | set_option -enable_prepacking 1 60 | 61 | # sequential_optimization_options 62 | set_option -symbolic_fsm_compiler 1 63 | 64 | # Compiler Options 65 | set_option -compiler_compatible 1 66 | set_option -resource_sharing 1 67 | 68 | #VIF options 69 | set_option -write_vif 0 70 | 71 | #automatic place and route (vendor) options 72 | set_option -write_apr_constraint 1 73 | 74 | #set result format/file last 75 | project -result_file "./nf10_upb_switch.edf" 76 | 77 | #design plan options 78 | impl -active "prj" 79 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/libsdn_dataplane/hw_flow.hpp: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | * 6 | * Project Group "On-the-Fly Networking for Big Data" 7 | * SFB 901 "On-The-Fly Computing" 8 | * 9 | * University of Paderborn 10 | * Computer Engineering Group 11 | * Pohlweg 47 - 49 12 | * 33098 Paderborn 13 | * Germany 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the "License"); 16 | * you may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #pragma once 29 | 30 | #include 31 | #include 32 | #include 33 | 34 | #define div_round_up(x,y) (x/y + (x%y?1:0)) 35 | 36 | namespace upb { 37 | 38 | /** 39 | * Objects of this class hold the hardware representation of the flow entry 40 | */ 41 | class hw_flow { 42 | 43 | public: 44 | /** 45 | * Size of the tuple 46 | */ 47 | const static uint32_t hw_tuple_size_bits = 243; 48 | const static uint32_t hw_tuple_size_32bits = div_round_up(hw_tuple_size_bits, 32); 49 | 50 | typedef uint32_t hw_tuple[hw_tuple_size_32bits]; // a hardware flow has 243 bits => use 8 * uint_32 (256 bit) in software; the size of this array must ALWAYS be a multiple of 32 bits 51 | 52 | /** 53 | * The key part of the flow entry 54 | */ 55 | hw_tuple key; 56 | /** 57 | * The mask part of the flow entry 58 | */ 59 | hw_tuple mask; // each set bit in the mask specifies an exact match with the corresponding bit in the key ('0' = wildcard) 60 | 61 | /** 62 | * Constructs a hardware flow from a (software) flow 63 | */ 64 | hw_flow(const flow &flow); 65 | 66 | private: 67 | void convert_tuple(hw_tuple &tuple_hw, const flow::tuple &tuple_sw); 68 | 69 | }; 70 | 71 | #undef div_round_up 72 | 73 | } 74 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_lib/hdl/verilog/flow_ctrl.v: -------------------------------------------------------------------------------- 1 | /* 2 | * UPB flow_ctrl 3 | * 4 | * Copyright (c) 2014, 2015 Thomas Löcke 5 | * tloecke@mail.uni-paderborn.de 6 | * 7 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project: 8 | * 9 | * Project Group "On-the-Fly Networking for Big Data" 10 | * SFB 901 "On-The-Fly Computing" 11 | * 12 | * University of Paderborn 13 | * Computer Engineering Group 14 | * Pohlweg 47 - 49 15 | * 33098 Paderborn 16 | * Germany 17 | * 18 | * 19 | * This file is free code: you can redistribute it and/or modify it under 20 | * the terms of the GNU Lesser General Public License version 2.1 as 21 | * published by the Free Software Foundation. 22 | * 23 | * This file is distributed in the hope that it will be useful, 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 | * GNU Lesser General Public License for more details. 27 | * 28 | * You should have received a copy of the GNU Lesser General Public License 29 | * along with this project. If not, see . 30 | * 31 | */ 32 | module flow_ctrl( 33 | input reset, 34 | 35 | // Packet FIFO side // 36 | input clk, 37 | input below_low, 38 | input above_high, 39 | 40 | // MAC side // 41 | input clk156, 42 | output reg pause_req = 0, 43 | output reg [15:0] pause_val 44 | ); 45 | 46 | reg state = 0; 47 | reg state156 = 0; 48 | reg state156_old = 0; 49 | 50 | always @(posedge clk) begin 51 | if (reset) 52 | state <= 0; 53 | else if (!state && above_high) 54 | state <= 1; 55 | else if (state && below_low) 56 | state <= 0; 57 | end 58 | 59 | always @(posedge clk156) begin 60 | if (!reset) begin 61 | state156 <= state; 62 | state156_old <= state156; 63 | end else begin 64 | state156 <= 0; 65 | state156_old <= 0; 66 | end 67 | end 68 | 69 | always @(posedge clk156) begin 70 | pause_req <= 0; 71 | if (state156 && !state156_old) begin 72 | pause_req <= 1; 73 | pause_val <= 16'hFFFF; 74 | end 75 | else if (!state156 && state156_old) begin 76 | pause_req <= 1; 77 | pause_val <= 16'h0000; 78 | end 79 | end 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_dummy_port_v1_00_a/data/nf10_upb_dummy_port_v2_1_0.mpd: -------------------------------------------------------------------------------- 1 | # 2 | # UPB Dummy Port core 3 | # 4 | # Copyright (c) 2014, 2015 Jörg Niklas 5 | # osjsn@niklasfamily.de 6 | # 7 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 8 | # 9 | # Project Group "On-the-Fly Networking for Big Data" 10 | # SFB 901 "On-The-Fly Computing" 11 | # 12 | # University of Paderborn 13 | # Computer Engineering Group 14 | # Pohlweg 47 - 49 15 | # 33098 Paderborn 16 | # Germany 17 | # 18 | # 19 | # This file is free code: you can redistribute it and/or modify it under 20 | # the terms of the GNU Lesser General Public License version 2.1 as 21 | # published by the Free Software Foundation. 22 | # 23 | # This file is distributed in the hope that it will be useful, 24 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 25 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 | # GNU Lesser General Public License for more details. 27 | # 28 | # You should have received a copy of the GNU Lesser General Public License 29 | # along with this project. If not, see . 30 | # 31 | 32 | BEGIN nf10_upb_dummy_port 33 | 34 | ## Peripheral Options 35 | OPTION IPTYPE = PERIPHERAL 36 | OPTION IMP_NETLIST = TRUE 37 | OPTION HDL = VERILOG 38 | OPTION IP_GROUP = UPB 39 | OPTION DESC = NetFPGA-10G dummy port 40 | 41 | PARAMETER peripheral_port_width = 32, DT = integer 42 | PARAMETER external_port_width = 32, DT = integer 43 | 44 | PORT peripheral_connection_O = "", DIR = O, VEC = [(peripheral_port_width-1):0] 45 | PORT peripheral_connection_I = "", DIR = I, VEC = [(peripheral_port_width-1):0] 46 | PORT peripheral_connection_T = "", DIR = I, VEC = [(peripheral_port_width-1):0] 47 | PORT peripheral_connection = "", TRI_I = peripheral_connection_O, TRI_O = peripheral_connection_I, TRI_T = peripheral_connection_T, DIR = IO, VEC = [(peripheral_port_width-1):0], THREE_STATE = TRUE, ENABLE = MULTI 48 | 49 | PORT external_connection_O = "", DIR = O, VEC = [(external_port_width-1):0] 50 | PORT external_connection_I = "", DIR = I, VEC = [(external_port_width-1):0] 51 | PORT external_connection_T = "", DIR = O, VEC = [(external_port_width-1):0] 52 | PORT external_connection = "", TRI_I = external_connection_I, TRI_O = external_connection_O, TRI_T = external_connection_T, DIR = IO, VEC = [(external_port_width-1):0], THREE_STATE = TRUE, ENABLE = MULTI 53 | 54 | END 55 | 56 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_input_arbiter_v1_00_a/hdl/verilog/nf10_upb_input_arbiter_tb.tcl: -------------------------------------------------------------------------------- 1 | run 800ns 2 | if {! ([test /nf10_upb_input_arbiter_tb/uut/m_axis_tlast 1] & [test /nf10_upb_input_arbiter_tb/uut/m_axis_tvalid 1] & [test /nf10_upb_input_arbiter_tb/uut/m_axis_tdata(255:0) c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0c0 -radix hex])} { 3 | puts "Test Failed" 4 | quit 5 | } 6 | run 3200ns #4000 7 | if {! ([test /nf10_upb_input_arbiter_tb/uut/m_axis_tlast 0] & [test /nf10_upb_input_arbiter_tb/uut/m_axis_tvalid 1] & [test /nf10_upb_input_arbiter_tb/uut/m_axis_tdata(255:0) b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0 -radix hex])} { 8 | puts "Test Failed" 9 | quit 10 | } 11 | run 6000ns #10000 12 | if {! ([test /nf10_upb_input_arbiter_tb/uut/m_axis_tlast 0] & [test /nf10_upb_input_arbiter_tb/uut/m_axis_tvalid 1] & [test /nf10_upb_input_arbiter_tb/uut/m_axis_tdata(255:0) b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2 -radix hex])} { 13 | puts "Test Failed" 14 | quit 15 | } 16 | run 7400ns #17400 17 | if {! ([test /nf10_upb_input_arbiter_tb/uut/m_axis_tlast 1] & [test /nf10_upb_input_arbiter_tb/uut/m_axis_tvalid 1] & [test /nf10_upb_input_arbiter_tb/uut/m_axis_tdata(255:0) c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2 -radix hex])} { 18 | puts "Test Failed" 19 | quit 20 | } 21 | run 13200ns #30600 22 | if {! ([test /nf10_upb_input_arbiter_tb/uut/m_axis_tvalid 1] & [test /nf10_upb_input_arbiter_tb/uut/m_axis_tdata(255:0) c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2 -radix hex])} { 23 | puts "Test Failed" 24 | quit 25 | } 26 | run 200ns #30800 27 | if {! ([test /nf10_upb_input_arbiter_tb/uut/m_axis_tvalid 1] & [test /nf10_upb_input_arbiter_tb/uut/m_axis_tdata(255:0) a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0 -radix hex])} { 28 | puts "Test Failed" 29 | quit 30 | } 31 | run 11400ns #42200 32 | if {! ([test /nf10_upb_input_arbiter_tb/uut/m_axis_tlast 0] & [test /nf10_upb_input_arbiter_tb/uut/m_axis_tvalid 1] & [test /nf10_upb_input_arbiter_tb/uut/m_axis_tdata(255:0) a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0 -radix hex])} { 33 | puts "Test Failed" 34 | quit 35 | } 36 | run 2000ns #44200 37 | if {! ([test /nf10_upb_input_arbiter_tb/uut/m_axis_tvalid 0])} { 38 | puts "Test Failed" 39 | quit 40 | } 41 | puts "Test Passed" 42 | quit 43 | 44 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/libsdn_dataplane/logging.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | * 6 | * Project Group "On-the-Fly Networking for Big Data" 7 | * SFB 901 "On-The-Fly Computing" 8 | * 9 | * University of Paderborn 10 | * Computer Engineering Group 11 | * Pohlweg 47 - 49 12 | * 33098 Paderborn 13 | * Germany 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the "License"); 16 | * you may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "logging.hpp" 29 | #include 30 | #include 31 | #include 32 | #include 33 | #include 34 | #include 35 | 36 | namespace upb { 37 | 38 | namespace bl = boost::log; 39 | namespace ble = boost::log::expressions; 40 | namespace bpt = boost::posix_time; 41 | 42 | void logging::init_logging() 43 | { 44 | bl::core::get()->add_global_attribute("TimeStamp", bl::attributes::local_clock()); 45 | 46 | bl::add_console_log ( 47 | std::clog, 48 | bl::keywords::format = 49 | ( 50 | ble::stream 51 | << ble::format_date_time< bpt::ptime >("TimeStamp", "%Y-%m-%d %H:%M:%S") 52 | << ": <" << bl::trivial::severity 53 | << "> " << ble::smessage 54 | ) 55 | ); 56 | } 57 | 58 | void logging::log_level_trace() 59 | { 60 | bl::core::get()->set_filter 61 | ( 62 | bl::trivial::severity >= bl::trivial::trace 63 | ); 64 | } 65 | 66 | void logging::log_level_debug() 67 | { 68 | bl::core::get()->set_filter 69 | ( 70 | bl::trivial::severity >= bl::trivial::debug 71 | ); 72 | } 73 | 74 | void logging::log_level_info() 75 | { 76 | bl::core::get()->set_filter 77 | ( 78 | bl::trivial::severity >= bl::trivial::info 79 | ); 80 | } 81 | 82 | 83 | } 84 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/libsdn_dataplane/config_fpga_addresses.hpp: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | * 6 | * Project Group "On-the-Fly Networking for Big Data" 7 | * SFB 901 "On-The-Fly Computing" 8 | * 9 | * University of Paderborn 10 | * Computer Engineering Group 11 | * Pohlweg 47 - 49 12 | * 33098 Paderborn 13 | * Germany 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the "License"); 16 | * you may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #pragma once 29 | 30 | namespace upb { 31 | 32 | class config_fpga_addresses { 33 | 34 | public: 35 | /** 36 | * AXI-4 Lite bus address of the TCAM 37 | */ 38 | const uint32_t tcam_address = 0xa0000000; 39 | /** 40 | * Hardware priority of the TCAM 41 | */ 42 | const uint32_t tcam_hw_priority = 0; 43 | /** 44 | * AXI-4 Lite bus address of the CAM 45 | */ 46 | const uint32_t cam_address = 0xb0000000; 47 | /** 48 | * Hardware priority of the CAM 49 | */ 50 | const uint32_t cam_hw_priority = 1; // the cam has a higher priority 51 | /** 52 | * Clock frequency of the OpenFlow core on the FPGA 53 | */ 54 | const float clock_frequency_hz_statistics_counters = 120e6f; 55 | /** 56 | * Polling interval for the statistics. Must be chosen such that the 32 bit counters cannot overrun on the FPGA 57 | */ 58 | const uint32_t default_statistics_poll_interval_ms = 10000; 59 | /** 60 | * AXI-4 Lite bus address of the statistics module 61 | */ 62 | const uint32_t statistics_module_address = 0xc0000000; 63 | /** 64 | * Number of static lookup entries in the lookup table engine 65 | */ 66 | const uint32_t action_processor_static_lookup_entries = 8; 67 | /** 68 | * Number of vport lookup entries in the lookup table engine 69 | */ 70 | const uint32_t action_processor_vport_lookup_entries = 8; 71 | 72 | }; 73 | 74 | } 75 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/libsdn_dataplane/poll_thread.hpp: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | * 6 | * Project Group "On-the-Fly Networking for Big Data" 7 | * SFB 901 "On-The-Fly Computing" 8 | * 9 | * University of Paderborn 10 | * Computer Engineering Group 11 | * Pohlweg 47 - 49 12 | * 33098 Paderborn 13 | * Germany 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the "License"); 16 | * you may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #pragma once 29 | 30 | #include 31 | #include 32 | #include 33 | #include 34 | #include 35 | #include 36 | 37 | namespace upb { 38 | 39 | namespace b = boost; 40 | namespace bs2 = boost::signals2; 41 | 42 | /** 43 | * Helper class the provide a thread which periodically calls a signal 44 | */ 45 | class poll_thread { 46 | 47 | public: 48 | typedef b::shared_ptr mutex_t; 49 | typedef bs2::signal signal_t; 50 | 51 | /** 52 | * Construct the polling thread 53 | * @param mutex A boost recursive_mutex which is locked during the signal invcation 54 | * @param poll_interval_ms The polling interval in milliseconds 55 | */ 56 | poll_thread(mutex_t &mutex, uint32_t poll_interval_ms); 57 | 58 | /** 59 | * The destuctor terminates the thread 60 | */ 61 | ~poll_thread(); 62 | 63 | private: 64 | mutex_t mutex; 65 | uint32_t poll_interval_ms; 66 | b::thread thread; 67 | signal_t signal; 68 | 69 | public: 70 | /** 71 | * The "run"-function must be public for boost::thread 72 | */ 73 | void operator()(); 74 | 75 | public: 76 | /** 77 | * Returns the signal that new slots can be added 78 | * @return The boost::signals2 signal 79 | */ 80 | signal_t& get_signal() { 81 | return signal; 82 | } 83 | 84 | }; 85 | 86 | 87 | } 88 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_sdn_dataplane_v1_00_a/src/libsdn_dataplane/config_platform_flash.hpp: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project 3 | * 4 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 5 | * 6 | * Project Group "On-the-Fly Networking for Big Data" 7 | * SFB 901 "On-The-Fly Computing" 8 | * 9 | * University of Paderborn 10 | * Computer Engineering Group 11 | * Pohlweg 47 - 49 12 | * 33098 Paderborn 13 | * Germany 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the "License"); 16 | * you may not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at: 18 | * 19 | * http://www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an "AS IS" BASIS, 23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #pragma once 29 | 30 | #include 31 | #include 32 | 33 | namespace upb { 34 | 35 | class config_platform_flash { 36 | 37 | public: 38 | 39 | constexpr const static uint32_t flash_chip_count = 2; 40 | 41 | // Flash parameters (taken from Xilinx DS617) 42 | 43 | constexpr const static uint32_t main_blocks = 127; 44 | constexpr const static uint32_t main_block_size_words = 0x10000; 45 | constexpr const static uint32_t parameter_blocks = 4; 46 | constexpr const static uint32_t parameter_block_size_words = 0x4000; 47 | constexpr const static uint32_t flash_blocks = main_blocks + parameter_blocks; 48 | constexpr const static uint32_t buffer_size_words = 0x20; 49 | constexpr const static uint32_t blocks_per_bank = 8; 50 | constexpr const static uint32_t bank_size = main_block_size_words * blocks_per_bank; 51 | constexpr const static uint32_t banks = 16; 52 | constexpr const static uint32_t flash_size_words = bank_size * banks; 53 | constexpr const static uint32_t bank_mask = ~(bank_size - 1); 54 | 55 | enum { 56 | FLASH_CMD_BLOCK_ERASE = 0x20, 57 | FLASH_CMD_CLEAR_STATUS_REG = 0x50, 58 | FLASH_CMD_LOCK_SETUP = 0x60, 59 | FLASH_CMD_READ_ELEC_SIG = 0x90, 60 | FLASH_CMD_WRITE_CONFIRM = 0xd0, 61 | FLASH_CMD_BUFFER_PROGRAM = 0xe8, 62 | FLASH_CMD_READ_ARRAY = 0xff 63 | }; 64 | 65 | constexpr const static uint8_t FLASH_STATUS_OK_MASK = 0x7f; 66 | 67 | enum { 68 | FLASH_STATUS_PEC_READY = 0x80 69 | }; 70 | }; 71 | 72 | } 73 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_lib/hdl/verilog/frame_gen_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | * Copyright (c) 2014, 2015 Felix Wallaschek 4 | * felix@elektronenversand.de 5 | * 6 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project: 7 | * 8 | * Project Group "On-the-Fly Networking for Big Data" 9 | * SFB 901 "On-The-Fly Computing" 10 | * 11 | * University of Paderborn 12 | * Computer Engineering Group 13 | * Pohlweg 47 - 49 14 | * 33098 Paderborn 15 | * Germany 16 | * 17 | * 18 | * This file is free code: you can redistribute it and/or modify it under 19 | * the terms of the GNU Lesser General Public License version 2.1 as 20 | * published by the Free Software Foundation. 21 | * 22 | * This file is distributed in the hope that it will be useful, 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 | * GNU Lesser General Public License for more details. 26 | * 27 | * You should have received a copy of the GNU Lesser General Public License 28 | * along with this project. If not, see . 29 | */ 30 | module frame_gen_tb; 31 | 32 | // Inputs 33 | reg clk; 34 | reg axi_resetn; 35 | reg m_axis_tready; 36 | 37 | // Outputs 38 | wire [255:0] m_axis_tdata; 39 | wire [31:0] m_axis_tkeep; 40 | wire [13:0] m_axis_tuser_packet_length; 41 | wire [2:0] m_axis_tuser_in_port; 42 | wire [7:0] m_axis_tuser_out_port; 43 | wire [2:0] m_axis_tuser_in_vport; 44 | wire [7:0] m_axis_tuser_out_vport; 45 | wire m_axis_tvalid; 46 | wire m_axis_tlast; 47 | 48 | // Instantiate the Unit Under Test (UUT) 49 | frame_gen uut ( 50 | .clk(clk), 51 | .axi_resetn(axi_resetn), 52 | .m_axis_tdata(m_axis_tdata), 53 | .m_axis_tkeep(m_axis_tkeep), 54 | .m_axis_tuser_packet_length(m_axis_tuser_packet_length), 55 | .m_axis_tuser_in_port(m_axis_tuser_in_port), 56 | .m_axis_tuser_out_port(m_axis_tuser_out_port), 57 | .m_axis_tuser_in_vport(m_axis_tuser_in_vport), 58 | .m_axis_tuser_out_vport(m_axis_tuser_out_vport), 59 | .m_axis_tvalid(m_axis_tvalid), 60 | .m_axis_tready(1), 61 | .m_axis_tlast(m_axis_tlast) 62 | ); 63 | 64 | initial begin 65 | // Initialize Inputs 66 | clk = 0; 67 | axi_resetn = 0; 68 | m_axis_tready = 0; 69 | 70 | // Wait 100 ns for global reset to finish 71 | #100; 72 | 73 | // Add stimulus here 74 | 75 | end 76 | always 77 | #5 clk = ~clk; 78 | endmodule 79 | 80 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/src/nic_driver/nf10fops.h: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * NetFPGA-10G http://www.netfpga.org 4 | * 5 | * File: 6 | * nf10fops.h 7 | * 8 | * Project: 9 | * nic 10 | * 11 | * Author: 12 | * Mario Flajslik 13 | * 14 | * Modifications for the UPB OpenFlow Switch project: 15 | * Jörg Niklas, osjsn@niklasfamily.de 16 | * Project Group "On-the-Fly Networking for Big Data" 17 | * Computer Engineering Group, University of Paderborn 18 | * 19 | * Description: 20 | * Function prototypes for nf10fops.c 21 | * 22 | * Copyright notice: 23 | * Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 24 | * Junior University 25 | * 26 | * Modifications for the UPB OpenFlow Switch project: 27 | * Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 28 | * 29 | * Licence: 30 | * This file is part of the NetFPGA 10G development base package. 31 | * 32 | * This file is free code: you can redistribute it and/or modify it under 33 | * the terms of the GNU Lesser General Public License version 2.1 as 34 | * published by the Free Software Foundation. 35 | * 36 | * This package is distributed in the hope that it will be useful, but 37 | * WITHOUT ANY WARRANTY; without even the implied warranty of 38 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 39 | * Lesser General Public License for more details. 40 | * 41 | * You should have received a copy of the GNU Lesser General Public 42 | * License along with the NetFPGA source package. If not, see 43 | * http://www.gnu.org/licenses/. 44 | * 45 | */ 46 | 47 | #ifndef NF10FOPS_H 48 | #define NF10FOPS_H 49 | 50 | #include 51 | #include "nf10driver.h" 52 | 53 | #define NF10_IOCTL_CMD_READ_STAT (SIOCDEVPRIVATE+0) 54 | #define NF10_IOCTL_CMD_WRITE_REG (SIOCDEVPRIVATE+1) 55 | #define NF10_IOCTL_CMD_READ_REG (SIOCDEVPRIVATE+2) 56 | 57 | struct ioctl_write { 58 | uint32_t value; 59 | uint32_t address; 60 | }; 61 | 62 | int nf10fops_open (struct inode *n, struct file *f); 63 | long nf10fops_ioctl (struct file *f, unsigned int cmd, unsigned long arg); 64 | int nf10fops_release (struct inode *n, struct file *f); 65 | 66 | int nf10_mmap(struct file *filp, struct vm_area_struct *vma); 67 | 68 | int nf10fops_probe(struct pci_dev *pdev, struct nf10_card *card); 69 | int nf10fops_remove(struct pci_dev *pdev, struct nf10_card *card); 70 | 71 | #endif 72 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_interconnect_v1_00_a/data/nf10_upb_interconnect_v2_1_0.pao: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | ## Filename: /home/tloecke/Desktop/peripheral_repo/MyProcessorIPLib/pcores/nf10_upb_interconnect_v1_00_a/data/nf10_upb_interconnect_v2_1_0.pao 3 | ## Description: Peripheral Analysis Order 4 | ## Date: Wed Jun 25 16:53:18 2014 (by Create and Import Peripheral Wizard) 5 | ############################################################################## 6 | 7 | #lib nf10_upb_interconnect_v1_00_a ./nf10/crc802_3 verilog 8 | #lib nf10_upb_interconnect_v1_00_a ../../../nf10_upb_lib/hdl/verilog/flow_ctrl verilog 9 | #lib nf10_upb_interconnect_v1_00_a ./nf10/nf10_upb_aurora_input verilog 10 | #lib nf10_upb_interconnect_v1_00_a ./nf10/nf10_upb_interconnect verilog 11 | #lib nf10_upb_interconnect_v1_00_a ./nf10/wide_fifo verilog 12 | #lib nf10_upb_interconnect_v1_00_a ../../../nf10_upb_lib/hdl/verilog/nf10_upb_packet_fifo verilog 13 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_aurora_lane_4byte verilog 14 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_channel_err_detect verilog 15 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_channel_init_sm verilog 16 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_chbond_count_dec_4byte verilog 17 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_clock_module verilog 18 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_err_detect_4byte verilog 19 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_global_logic verilog 20 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_idle_and_ver_gen verilog 21 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_lane_init_sm_4byte verilog 22 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_reset_logic verilog 23 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_rx_stream verilog 24 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_standard_cc_module verilog 25 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_sym_dec_4byte verilog 26 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_sym_gen_4byte verilog 27 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_tile verilog 28 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_transceiver_wrapper verilog 29 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3_tx_stream verilog 30 | #lib nf10_upb_interconnect_v1_00_a ./aurora/aurora_8b10b_v5_3 verilog 31 | 32 | lib nf10_upb_interconnect_v1_00_a ./nf10/nf10_upb_interconnect_wrapper verilog 33 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/src/flashprog/reg_lib.c: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * NetFPGA-10G http://www.netfpga.org 4 | * 5 | * File: 6 | * reg_lib.c 7 | * 8 | * Project: 9 | * flash_configuration 10 | * 11 | * Author: 12 | * Muhammad Shahbaz 13 | * 14 | * Description: 15 | * Set of definitions for the NF10 register access library. 16 | * 17 | * Copyright notice: 18 | * Copyright (C) 2010, 2011 University of Cambridge 19 | * 20 | * Licence: 21 | * This file is part of the NetFPGA 10G development base package. 22 | * 23 | * This file is free code: you can redistribute it and/or modify it under 24 | * the terms of the GNU Lesser General Public License version 2.1 as 25 | * published by the Free Software Foundation. 26 | * 27 | * This package is distributed in the hope that it will be useful, but 28 | * WITHOUT ANY WARRANTY; without even the implied warranty of 29 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | * Lesser General Public License for more details. 31 | * 32 | * You should have received a copy of the GNU Lesser General Public 33 | * License along with the NetFPGA source package. If not, see 34 | * http://www.gnu.org/licenses/. 35 | * 36 | * This file was developed by SRI International and the University of 37 | * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 38 | * ("CTSRD"), as part of the DARPA CRASH research programme. 39 | */ 40 | 41 | #include "reg_lib.h" 42 | #include 43 | #include 44 | #include 45 | #include 46 | #include 47 | 48 | #define IOCTL_CMD_READ_STAT (SIOCDEVPRIVATE+0) 49 | #define IOCTL_CMD_WRITE_REG (SIOCDEVPRIVATE+1) 50 | #define IOCTL_CMD_READ_REG (SIOCDEVPRIVATE+2) 51 | 52 | inline uint32_t reg_rd(int dev, uint64_t addr) 53 | { 54 | if(ioctl(dev, IOCTL_CMD_READ_REG, &addr) < 0){ 55 | perror("ioctl failed"); 56 | return 0; 57 | } 58 | return addr & 0xffffffff; 59 | } 60 | 61 | inline int reg_wr(int dev, uint64_t addr, uint32_t val) 62 | { 63 | addr = (addr << 32) + val; 64 | if(ioctl(dev, IOCTL_CMD_WRITE_REG, &addr) < 0){ 65 | perror("ioctl failed"); 66 | return 0; 67 | } 68 | return -1; 69 | } 70 | 71 | /* 72 | // Code for opening nf10 device 73 | int dev_open() 74 | { 75 | int dev = open("/dev/nf10", O_RDWR); 76 | if(dev < 0){ 77 | perror("/dev/nf10"); 78 | return 0; 79 | } 80 | return dev; 81 | } 82 | */ 83 | -------------------------------------------------------------------------------- /lib/hw/xilinx/pcores/axi_gpio_v1_01_b/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # NetFPGA-10G http://www.netfpga.org 4 | # 5 | # File: 6 | # Makefile 7 | # 8 | # Library: 9 | # hw/xilinx/pcores/axi_gpio_v1_01_b 10 | # 11 | # Description: 12 | # make install : Copy Xilinx files into NetFPGA-10G library 13 | # 14 | # For more information about how Xilinx EDK works, please visit 15 | # http://www.xilinx.com/support/documentation/dt_edk.htm 16 | # 17 | # Copyright notice: 18 | # Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 19 | # Junior University 20 | # 21 | # Modifications for the UPB OpenFlow Switch project: 22 | # Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 23 | # Project Group "On-the-Fly Networking for Big Data" 24 | # Computer Engineering Group, University of Paderborn 25 | # 26 | # DISCLAIMER NOTICE 27 | # We are not affiliated, associated, authorized, endorsed by, or in any way 28 | # officially connected with Xilinx, Inc. or any of its subsidiaries or its 29 | # affiliates. In no event whatsoever shall Xilinx, Inc. or any of its 30 | # subsidiaries or its affiliates have any warranty or support commitment 31 | # for this software or liability for loss, injury or damage in connection 32 | # with this software, including but not limited to the use or display thereof. 33 | # 34 | # Licence: 35 | # This file is part of the NetFPGA 10G development base package. 36 | # 37 | # This file is free code: you can redistribute it and/or modify it under 38 | # the terms of the GNU Lesser General Public License version 2.1 as 39 | # published by the Free Software Foundation. 40 | # 41 | # This package is distributed in the hope that it will be useful, but 42 | # WITHOUT ANY WARRANTY; without even the implied warranty of 43 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 44 | # Lesser General Public License for more details. 45 | # 46 | # You should have received a copy of the GNU Lesser General Public 47 | # License along with the NetFPGA source package. If not, see 48 | # http://www.gnu.org/licenses/. 49 | # 50 | # 51 | 52 | XILINX_HW_LIB_DIR = $(XILINX_EDK)/hw/XilinxProcessorIPLib/pcores 53 | HW_LIB_INSTANCE = $(shell basename $(shell pwd)) 54 | 55 | all: install 56 | 57 | install: 58 | false | cp -ri $(XILINX_HW_LIB_DIR)/$(HW_LIB_INSTANCE)/* . > /dev/null 2>&1 59 | sed -i '/OPTION ARCH_SUPPORT_MAP .*/d' data/axi_gpio_v2_1_0.mpd 60 | 61 | clean: 62 | rm -rf data doc hdl 63 | 64 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue_2.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/jsn/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue.prj 4 | 5 | #project files 6 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/axis_if.v" 7 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/qdr2_sram.v" 8 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/secded.v" 9 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/simple_packet_fifo.v" 10 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/tkeep_coder.v" 11 | add_file -verilog "./output_queue.v" 12 | add_file -verilog "./nf10_upb_output_queue.v" 13 | add_file -constraint "./nf10_upb_output_queue_2.sdc" 14 | 15 | 16 | #implementation: "netlist" 17 | impl -add netlist -type fpga 18 | 19 | # 20 | #implementation attributes 21 | 22 | set_option -vlog_std sysv 23 | set_option -num_critical_paths 5 24 | set_option -num_startend_points 5 25 | set_option -project_relative_includes 1 26 | 27 | # 28 | #implementation parameter settings 29 | set_option -hdl_param -set output_ports 2 30 | set_option -hdl_param -set store_and_forward_ports 2b'11 31 | 32 | #device options 33 | set_option -technology Virtex5 34 | set_option -part XC5VTX240T 35 | set_option -package FF1759 36 | set_option -speed_grade -2 37 | set_option -part_companion "" 38 | 39 | #compilation/mapping options 40 | set_option -use_fsm_explorer 1 41 | set_option -top_module "nf10_upb_output_queue" 42 | 43 | # mapper_options 44 | set_option -frequency auto 45 | set_option -write_verilog 0 46 | set_option -write_vhdl 0 47 | set_option -srs_instrumentation 1 48 | 49 | # xilinx_options 50 | set_option -RWCheckOnRam 1 51 | 52 | # Xilinx Virtex2 53 | set_option -run_prop_extract 1 54 | set_option -maxfan 10000 55 | set_option -disable_io_insertion 1 56 | set_option -pipe 1 57 | set_option -update_models_cp 0 58 | set_option -retiming 1 59 | set_option -no_sequential_opt 0 60 | set_option -fix_gated_and_generated_clocks 1 61 | 62 | # Xilinx Virtex5 63 | set_option -enable_prepacking 1 64 | 65 | # sequential_optimization_options 66 | set_option -symbolic_fsm_compiler 1 67 | 68 | # Compiler Options 69 | set_option -compiler_compatible 0 70 | set_option -resource_sharing 1 71 | set_option -multi_file_compilation_unit 1 72 | 73 | #VIF options 74 | set_option -write_vif 0 75 | 76 | #automatic place and route (vendor) options 77 | set_option -write_apr_constraint 0 78 | 79 | #set result format/file last 80 | project -result_file "../../netlist/2_ports/nf10_upb_output_queue.edf" 81 | 82 | #design plan options 83 | impl -active "netlist" 84 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue_3.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/jsn/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue.prj 4 | 5 | #project files 6 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/axis_if.v" 7 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/qdr2_sram.v" 8 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/secded.v" 9 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/simple_packet_fifo.v" 10 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/tkeep_coder.v" 11 | add_file -verilog "./output_queue.v" 12 | add_file -verilog "./nf10_upb_output_queue.v" 13 | add_file -constraint "./nf10_upb_output_queue_3.sdc" 14 | 15 | 16 | #implementation: "netlist" 17 | impl -add netlist -type fpga 18 | 19 | # 20 | #implementation attributes 21 | 22 | set_option -vlog_std sysv 23 | set_option -num_critical_paths 5 24 | set_option -num_startend_points 5 25 | set_option -project_relative_includes 1 26 | 27 | # 28 | #implementation parameter settings 29 | set_option -hdl_param -set output_ports 3 30 | set_option -hdl_param -set store_and_forward_ports 3b'111 31 | 32 | #device options 33 | set_option -technology Virtex5 34 | set_option -part XC5VTX240T 35 | set_option -package FF1759 36 | set_option -speed_grade -2 37 | set_option -part_companion "" 38 | 39 | #compilation/mapping options 40 | set_option -use_fsm_explorer 1 41 | set_option -top_module "nf10_upb_output_queue" 42 | 43 | # mapper_options 44 | set_option -frequency auto 45 | set_option -write_verilog 0 46 | set_option -write_vhdl 0 47 | set_option -srs_instrumentation 1 48 | 49 | # xilinx_options 50 | set_option -RWCheckOnRam 1 51 | 52 | # Xilinx Virtex2 53 | set_option -run_prop_extract 1 54 | set_option -maxfan 10000 55 | set_option -disable_io_insertion 1 56 | set_option -pipe 1 57 | set_option -update_models_cp 0 58 | set_option -retiming 1 59 | set_option -no_sequential_opt 0 60 | set_option -fix_gated_and_generated_clocks 1 61 | 62 | # Xilinx Virtex5 63 | set_option -enable_prepacking 1 64 | 65 | # sequential_optimization_options 66 | set_option -symbolic_fsm_compiler 1 67 | 68 | # Compiler Options 69 | set_option -compiler_compatible 0 70 | set_option -resource_sharing 1 71 | set_option -multi_file_compilation_unit 1 72 | 73 | #VIF options 74 | set_option -write_vif 0 75 | 76 | #automatic place and route (vendor) options 77 | set_option -write_apr_constraint 0 78 | 79 | #set result format/file last 80 | project -result_file "../../netlist/3_ports/nf10_upb_output_queue.edf" 81 | 82 | #design plan options 83 | impl -active "netlist" 84 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue_4.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/jsn/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue.prj 4 | 5 | #project files 6 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/axis_if.v" 7 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/qdr2_sram.v" 8 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/secded.v" 9 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/simple_packet_fifo.v" 10 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/tkeep_coder.v" 11 | add_file -verilog "./output_queue.v" 12 | add_file -verilog "./nf10_upb_output_queue.v" 13 | add_file -constraint "./nf10_upb_output_queue_4.sdc" 14 | 15 | 16 | #implementation: "netlist" 17 | impl -add netlist -type fpga 18 | 19 | # 20 | #implementation attributes 21 | 22 | set_option -vlog_std sysv 23 | set_option -num_critical_paths 5 24 | set_option -num_startend_points 5 25 | set_option -project_relative_includes 1 26 | 27 | # 28 | #implementation parameter settings 29 | set_option -hdl_param -set output_ports 4 30 | set_option -hdl_param -set store_and_forward_ports 4b'1111 31 | 32 | #device options 33 | set_option -technology Virtex5 34 | set_option -part XC5VTX240T 35 | set_option -package FF1759 36 | set_option -speed_grade -2 37 | set_option -part_companion "" 38 | 39 | #compilation/mapping options 40 | set_option -use_fsm_explorer 1 41 | set_option -top_module "nf10_upb_output_queue" 42 | 43 | # mapper_options 44 | set_option -frequency auto 45 | set_option -write_verilog 0 46 | set_option -write_vhdl 0 47 | set_option -srs_instrumentation 1 48 | 49 | # xilinx_options 50 | set_option -RWCheckOnRam 1 51 | 52 | # Xilinx Virtex2 53 | set_option -run_prop_extract 1 54 | set_option -maxfan 10000 55 | set_option -disable_io_insertion 1 56 | set_option -pipe 1 57 | set_option -update_models_cp 0 58 | set_option -retiming 1 59 | set_option -no_sequential_opt 0 60 | set_option -fix_gated_and_generated_clocks 1 61 | 62 | # Xilinx Virtex5 63 | set_option -enable_prepacking 1 64 | 65 | # sequential_optimization_options 66 | set_option -symbolic_fsm_compiler 1 67 | 68 | # Compiler Options 69 | set_option -compiler_compatible 0 70 | set_option -resource_sharing 1 71 | set_option -multi_file_compilation_unit 1 72 | 73 | #VIF options 74 | set_option -write_vif 0 75 | 76 | #automatic place and route (vendor) options 77 | set_option -write_apr_constraint 0 78 | 79 | #set result format/file last 80 | project -result_file "../../netlist/4_ports/nf10_upb_output_queue.edf" 81 | 82 | #design plan options 83 | impl -active "netlist" 84 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue_5.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/jsn/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue.prj 4 | 5 | #project files 6 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/axis_if.v" 7 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/qdr2_sram.v" 8 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/secded.v" 9 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/simple_packet_fifo.v" 10 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/tkeep_coder.v" 11 | add_file -verilog "./output_queue.v" 12 | add_file -verilog "./nf10_upb_output_queue.v" 13 | add_file -constraint "./nf10_upb_output_queue_5.sdc" 14 | 15 | 16 | #implementation: "netlist" 17 | impl -add netlist -type fpga 18 | 19 | # 20 | #implementation attributes 21 | 22 | set_option -vlog_std sysv 23 | set_option -num_critical_paths 5 24 | set_option -num_startend_points 5 25 | set_option -project_relative_includes 1 26 | 27 | # 28 | #implementation parameter settings 29 | set_option -hdl_param -set output_ports 5 30 | set_option -hdl_param -set store_and_forward_ports 5b'01111 31 | 32 | #device options 33 | set_option -technology Virtex5 34 | set_option -part XC5VTX240T 35 | set_option -package FF1759 36 | set_option -speed_grade -2 37 | set_option -part_companion "" 38 | 39 | #compilation/mapping options 40 | set_option -use_fsm_explorer 1 41 | set_option -top_module "nf10_upb_output_queue" 42 | 43 | # mapper_options 44 | set_option -frequency auto 45 | set_option -write_verilog 0 46 | set_option -write_vhdl 0 47 | set_option -srs_instrumentation 1 48 | 49 | # xilinx_options 50 | set_option -RWCheckOnRam 1 51 | 52 | # Xilinx Virtex2 53 | set_option -run_prop_extract 1 54 | set_option -maxfan 10000 55 | set_option -disable_io_insertion 1 56 | set_option -pipe 1 57 | set_option -update_models_cp 0 58 | set_option -retiming 1 59 | set_option -no_sequential_opt 0 60 | set_option -fix_gated_and_generated_clocks 1 61 | 62 | # Xilinx Virtex5 63 | set_option -enable_prepacking 1 64 | 65 | # sequential_optimization_options 66 | set_option -symbolic_fsm_compiler 1 67 | 68 | # Compiler Options 69 | set_option -compiler_compatible 0 70 | set_option -resource_sharing 1 71 | set_option -multi_file_compilation_unit 1 72 | 73 | #VIF options 74 | set_option -write_vif 0 75 | 76 | #automatic place and route (vendor) options 77 | set_option -write_apr_constraint 0 78 | 79 | #set result format/file last 80 | project -result_file "../../netlist/5_ports/nf10_upb_output_queue.edf" 81 | 82 | #design plan options 83 | impl -active "netlist" 84 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue_6.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/jsn/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue.prj 4 | 5 | #project files 6 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/axis_if.v" 7 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/qdr2_sram.v" 8 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/secded.v" 9 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/simple_packet_fifo.v" 10 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/tkeep_coder.v" 11 | add_file -verilog "./output_queue.v" 12 | add_file -verilog "./nf10_upb_output_queue.v" 13 | add_file -constraint "./nf10_upb_output_queue_6.sdc" 14 | 15 | 16 | #implementation: "netlist" 17 | impl -add netlist -type fpga 18 | 19 | # 20 | #implementation attributes 21 | 22 | set_option -vlog_std sysv 23 | set_option -num_critical_paths 5 24 | set_option -num_startend_points 5 25 | set_option -project_relative_includes 1 26 | 27 | # 28 | #implementation parameter settings 29 | set_option -hdl_param -set output_ports 6 30 | set_option -hdl_param -set store_and_forward_ports 6b'001111 31 | 32 | #device options 33 | set_option -technology Virtex5 34 | set_option -part XC5VTX240T 35 | set_option -package FF1759 36 | set_option -speed_grade -2 37 | set_option -part_companion "" 38 | 39 | #compilation/mapping options 40 | set_option -use_fsm_explorer 1 41 | set_option -top_module "nf10_upb_output_queue" 42 | 43 | # mapper_options 44 | set_option -frequency auto 45 | set_option -write_verilog 0 46 | set_option -write_vhdl 0 47 | set_option -srs_instrumentation 1 48 | 49 | # xilinx_options 50 | set_option -RWCheckOnRam 1 51 | 52 | # Xilinx Virtex2 53 | set_option -run_prop_extract 1 54 | set_option -maxfan 10000 55 | set_option -disable_io_insertion 1 56 | set_option -pipe 1 57 | set_option -update_models_cp 0 58 | set_option -retiming 1 59 | set_option -no_sequential_opt 0 60 | set_option -fix_gated_and_generated_clocks 1 61 | 62 | # Xilinx Virtex5 63 | set_option -enable_prepacking 1 64 | 65 | # sequential_optimization_options 66 | set_option -symbolic_fsm_compiler 1 67 | 68 | # Compiler Options 69 | set_option -compiler_compatible 0 70 | set_option -resource_sharing 1 71 | set_option -multi_file_compilation_unit 1 72 | 73 | #VIF options 74 | set_option -write_vif 0 75 | 76 | #automatic place and route (vendor) options 77 | set_option -write_apr_constraint 0 78 | 79 | #set result format/file last 80 | project -result_file "../../netlist/6_ports/nf10_upb_output_queue.edf" 81 | 82 | #design plan options 83 | impl -active "netlist" 84 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue_7.prj: -------------------------------------------------------------------------------- 1 | #-- Synopsys, Inc. 2 | #-- Version G-2012.09-SP1 3 | #-- Project file /home/jsn/pgotfnetworking-netfpga/lib/hw/contrib/pcores/nf10_upb_output_queue_v1_00_a/hdl/verilog/nf10_upb_output_queue.prj 4 | 5 | #project files 6 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/axis_if.v" 7 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/qdr2_sram.v" 8 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/secded.v" 9 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/simple_packet_fifo.v" 10 | add_file -verilog "../../../nf10_upb_lib/hdl/SystemVerilog/tkeep_coder.v" 11 | add_file -verilog "./output_queue.v" 12 | add_file -verilog "./nf10_upb_output_queue.v" 13 | add_file -constraint "./nf10_upb_output_queue_7.sdc" 14 | 15 | 16 | #implementation: "netlist" 17 | impl -add netlist -type fpga 18 | 19 | # 20 | #implementation attributes 21 | 22 | set_option -vlog_std sysv 23 | set_option -num_critical_paths 5 24 | set_option -num_startend_points 5 25 | set_option -project_relative_includes 1 26 | 27 | # 28 | #implementation parameter settings 29 | set_option -hdl_param -set output_ports 7 30 | set_option -hdl_param -set store_and_forward_ports 7b'0001111 31 | 32 | #device options 33 | set_option -technology Virtex5 34 | set_option -part XC5VTX240T 35 | set_option -package FF1759 36 | set_option -speed_grade -2 37 | set_option -part_companion "" 38 | 39 | #compilation/mapping options 40 | set_option -use_fsm_explorer 1 41 | set_option -top_module "nf10_upb_output_queue" 42 | 43 | # mapper_options 44 | set_option -frequency auto 45 | set_option -write_verilog 0 46 | set_option -write_vhdl 0 47 | set_option -srs_instrumentation 1 48 | 49 | # xilinx_options 50 | set_option -RWCheckOnRam 1 51 | 52 | # Xilinx Virtex2 53 | set_option -run_prop_extract 1 54 | set_option -maxfan 10000 55 | set_option -disable_io_insertion 1 56 | set_option -pipe 1 57 | set_option -update_models_cp 0 58 | set_option -retiming 1 59 | set_option -no_sequential_opt 0 60 | set_option -fix_gated_and_generated_clocks 1 61 | 62 | # Xilinx Virtex5 63 | set_option -enable_prepacking 1 64 | 65 | # sequential_optimization_options 66 | set_option -symbolic_fsm_compiler 1 67 | 68 | # Compiler Options 69 | set_option -compiler_compatible 0 70 | set_option -resource_sharing 1 71 | set_option -multi_file_compilation_unit 1 72 | 73 | #VIF options 74 | set_option -write_vif 0 75 | 76 | #automatic place and route (vendor) options 77 | set_option -write_apr_constraint 0 78 | 79 | #set result format/file last 80 | project -result_file "../../netlist/7_ports/nf10_upb_output_queue.edf" 81 | 82 | #design plan options 83 | impl -active "netlist" 84 | -------------------------------------------------------------------------------- /lib/sw/contrib/drivers/nf10_upb_dma_v1_00_a/src/nic_driver/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # NetFPGA-10G http://www.netfpga.org 4 | # 5 | # File: 6 | # Makefile 7 | # 8 | # Project: 9 | # nic 10 | # 11 | # Author: 12 | # Mario Flajslik 13 | # 14 | # Modifications for the UPB OpenFlow Switch project: 15 | # Jörg Niklas, osjsn@niklasfamily.de 16 | # Project Group "On-the-Fly Networking for Big Data" 17 | # Computer Engineering Group, University of Paderborn 18 | # 19 | # Description: 20 | # make : Make the nic host driver. Load the driver with "insmod nf10.ko" 21 | # 22 | # 23 | # Copyright notice: 24 | # Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 25 | # Junior University 26 | # 27 | # Modifications for the UPB OpenFlow Switch project: 28 | # Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 29 | # 30 | # Licence: 31 | # This file is part of the NetFPGA 10G development base package. 32 | # 33 | # This file is free code: you can redistribute it and/or modify it under 34 | # the terms of the GNU Lesser General Public License version 2.1 as 35 | # published by the Free Software Foundation. 36 | # 37 | # This package is distributed in the hope that it will be useful, but 38 | # WITHOUT ANY WARRANTY; without even the implied warranty of 39 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 40 | # Lesser General Public License for more details. 41 | # 42 | # You should have received a copy of the GNU Lesser General Public 43 | # License along with the NetFPGA source package. If not, see 44 | # http://www.gnu.org/licenses/. 45 | # 46 | # 47 | 48 | obj-m += nf10.o 49 | nf10-objs += nf10driver.o 50 | nf10-objs += nf10iface.o 51 | nf10-objs += nf10fops.o 52 | nf10-objs += nf10priv.o 53 | nf10-objs += nf10_phy_conf.o 54 | 55 | ifeq ($(DEBUG),1) 56 | $(info *************** Building debug version of kernel module... ***************) 57 | ccflags-y=-g -ggdb -gdwarf-4 -fvar-tracking-assignments -O0 58 | endif 59 | 60 | ifndef $(KERNEL_VERSION) 61 | KERNEL_VERSION=$(shell uname -r) 62 | endif 63 | 64 | .PHONY: all modules clean install modules_install 65 | 66 | all: modules 67 | 68 | modules: 69 | make -C /lib/modules/$(KERNEL_VERSION)/build M=$(CURDIR) modules 70 | 71 | clean: 72 | make -C /lib/modules/$(KERNEL_VERSION)/build M=$(CURDIR) clean 73 | 74 | install: modules_install 75 | modules_install: 76 | make -C /lib/modules/$(KERNEL_VERSION)/build M=$(CURDIR) modules_install 77 | /sbin/depmod -a $(KERNEL_VERSION) 78 | 79 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_dma_v1_00_a/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # NetFPGA-10G http://www.netfpga.org 4 | # 5 | # File: 6 | # Makefile 7 | # 8 | # Library: 9 | # hw/contrib/pcores/upb_dma_v1_00_a 10 | # 11 | # Author: 12 | # Mario Flajslik 13 | # Modified by Michael Lass 14 | # 15 | # Description: 16 | # make synthesize125: regen netlist for 125MHz 17 | # make synthesize250: regen netlist for 250MHz 18 | # make install : Copy Xilinx files into NetFPGA-10G library 19 | # 20 | # For more information about how Xilinx EDK works, please visit 21 | # http://www.xilinx.com/support/documentation/dt_edk.htm 22 | # 23 | # Copyright notice: 24 | # Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 25 | # Junior University 26 | # 27 | # Licence: 28 | # This file is part of the NetFPGA 10G development base package. 29 | # 30 | # This file is free code: you can redistribute it and/or modify it under 31 | # the terms of the GNU Lesser General Public License version 2.1 as 32 | # published by the Free Software Foundation. 33 | # 34 | # This package is distributed in the hope that it will be useful, but 35 | # WITHOUT ANY WARRANTY; without even the implied warranty of 36 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 37 | # Lesser General Public License for more details. 38 | # 39 | # You should have received a copy of the GNU Lesser General Public 40 | # License along with the NetFPGA source package. If not, see 41 | # http://www.gnu.org/licenses/. 42 | # 43 | # 44 | 45 | COREGEN_DIR:= coregen 46 | 47 | all: synthesize hdl/verilog/xilinx/pcie_top.v 48 | 49 | synthesize: 50 | mkdir -p hdl/vhdl 51 | cd prj && ${SYNPLIFY_CMD} -batch dma_engine.prj 52 | sed -i '/library synplify;/d;/use synplify.components.all;/d' prj/dma_engine.vhm 53 | 54 | hdl/verilog/xilinx/pcie_top.v: xco/endpoint_blk_plus_v1_15.xco 55 | @mkdir -p $(COREGEN_DIR); 56 | @cd $(COREGEN_DIR) && coregen -b ../xco/endpoint_blk_plus_v1_15.xco 57 | @cp $(COREGEN_DIR)/endpoint_blk_plus_v1_15/source/*.v hdl/verilog/xilinx/ 58 | @patch hdl/verilog/xilinx/pcie_top.v 31 | #include 32 | #include 33 | #include 34 | 35 | namespace upb { 36 | 37 | namespace b = boost; 38 | 39 | class flow; 40 | 41 | class hw_flow_table_base { 42 | 43 | public: 44 | virtual ~hw_flow_table_base() {} 45 | 46 | /** 47 | * Attaches a flow_statistics (shared) object to the hardware lookup table (CAM/TCAM) class. This has to be done right after constructing a hardware lookup table object 48 | * @param stat Shared pointer to an instance of the flow_statistics class 49 | * @param stat_offset Table position offset for the entries associated with this lookup table 50 | */ 51 | virtual void set_flow_statistics(const b::shared_ptr &stat, uint32_t stat_offset) = 0; 52 | 53 | typedef uint32_t table_size_t; 54 | 55 | /** 56 | * Returns the hardware table (CAM/TCAM) size which was retrieved from the FPGA core 57 | * @return The table size in lines 58 | */ 59 | virtual table_size_t table_size() = 0; 60 | 61 | typedef uint32_t hw_priority_t; 62 | 63 | 64 | /** 65 | * Returns the hardware priority of the lookup table (CAM/TCAM) 66 | * @return The hardware priority 67 | */ 68 | virtual hw_priority_t hw_priority() = 0; 69 | 70 | const static hw_priority_t highest_priority = (hw_priority_t)-1; 71 | const static hw_priority_t lowest_priority = 0; 72 | 73 | /** 74 | * Adds a flow table entry to the hardware lookup table (CAM or TCAM) 75 | * @param new_flow Shared pointer to the flow object 76 | * @return true if successful 77 | */ 78 | virtual bool add_flow(const b::shared_ptr &new_flow) = 0; 79 | 80 | }; 81 | 82 | } 83 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_clock_generator_v1_00_a/data/nf10_upb_clock_generator_v2_1_0.mpd: -------------------------------------------------------------------------------- 1 | # 2 | # UPB Clock Generator core 3 | # 4 | # Copyright (c) 2014, 2015 Jörg Niklas 5 | # osjsn@niklasfamily.de 6 | # 7 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 8 | # 9 | # Project Group "On-the-Fly Networking for Big Data" 10 | # SFB 901 "On-The-Fly Computing" 11 | # 12 | # University of Paderborn 13 | # Computer Engineering Group 14 | # Pohlweg 47 - 49 15 | # 33098 Paderborn 16 | # Germany 17 | # 18 | # 19 | # This file is free code: you can redistribute it and/or modify it under 20 | # the terms of the GNU Lesser General Public License version 2.1 as 21 | # published by the Free Software Foundation. 22 | # 23 | # This file is distributed in the hope that it will be useful, 24 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 25 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 | # GNU Lesser General Public License for more details. 27 | # 28 | # You should have received a copy of the GNU Lesser General Public License 29 | # along with this project. If not, see . 30 | # 31 | 32 | BEGIN nf10_upb_clock_generator 33 | 34 | ## Peripheral Options 35 | OPTION IPTYPE = PERIPHERAL 36 | OPTION IMP_NETLIST = TRUE 37 | OPTION HDL = VERILOG 38 | OPTION IP_GROUP = UPB 39 | OPTION DESC = NetFPGA-10G Clock Generator 40 | 41 | ## Generics for VHDL or Parameters for Verilog 42 | PARAMETER reduce_clk_to_120mhz = 0, DT = integer, RANGE = (0:1) 43 | PARAMETER use_dci = 1, DT = integer, RANGE = (0:1) 44 | PARAMETER wait_for_dci_locked = 1, DT = integer, RANGE = (0:1) 45 | PARAMETER use_iodelay_control = 1, DT = integer, RANGE = (0:1) 46 | 47 | PARAMETER C_CLKIN_FREQ = 100000000, ASSIGNMENT = CONSTANT, DT = INTEGER, TYPE = NON_HDL 48 | PARAMETER C_CLKOUT_FREQ = 150000000, ASSIGNMENT = CONSTANT, DT = INTEGER, TYPE = NON_HDL 49 | 50 | ## Ports 51 | PORT clk100_in = "", DIR = I, SIGIS = CLK, ASSIGNMENT = REQUIRE 52 | PORT async_reset_in_n = "", DIR = I, ASSIGNMENT = REQUIRE 53 | 54 | PORT clk_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = clk100_in, CLK_FACTOR = 1.0 * (C_CLKOUT_FREQ - reduce_clk_to_120mhz * 30000000) / C_CLKIN_FREQ 55 | PORT clk2x_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = clk100_in, CLK_FACTOR = 2.0 * (C_CLKOUT_FREQ - reduce_clk_to_120mhz * 30000000) / C_CLKIN_FREQ 56 | PORT clk2x90_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = clk100_in, CLK_FACTOR = 2.0 * (C_CLKOUT_FREQ - reduce_clk_to_120mhz * 30000000) / C_CLKIN_FREQ 57 | PORT clk100_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = clk100_in, CLK_FACTOR = 1.0 58 | PORT clk20_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = clk100_in, CLK_FACTOR = 0.2 59 | 60 | port reset_out = "", DIR = O, SIGIS = RST 61 | port reset_n_out = "", DIR = O, SIGIS = RST 62 | 63 | END 64 | 65 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_10g_interface_v1_00_a/hdl/verilog/xilinx/rocketio_wrapper.diff: -------------------------------------------------------------------------------- 1 | DISCLAIMER NOTICE 2 | We are not affiliated, associated, authorized, endorsed by, or in any 3 | way officially connected with Xilinx, Inc. or any of its subsidiaries or 4 | its affiliates. In no event whatsoever shall Xilinx, Inc. or any of its 5 | subsidiaries or its affiliates have any warranty or support commitment 6 | for this software or liability for loss, injury or damage in connection 7 | with this software, including but not limited to the use or display 8 | thereof. 9 | --- 10 | 62c62,75 11 | < 12 | --- 13 | > //////////////////////////////////////////////////////////////////////// 14 | > // 15 | > // NetFPGA-10G http://www.netfpga.org 16 | > // 17 | > // Module: 18 | > // rocketio_wrapper.v 19 | > // 20 | > // Description: 21 | > // RocketIO wrapper patched with Lane reverse 22 | > // 23 | > // Revision history: 24 | > // 2010/12/8 hyzeng: Initial check-in 25 | > // 26 | > //////////////////////////////////////////////////////////////////////// 27 | 70c83 28 | < (* CORE_GENERATION_INFO = "1.7" *) 29 | --- 30 | > 31 | 76c89,90 32 | < parameter WRAPPER_SIM_PLL_PERDIV2 = 9'h140 // Set to the VCO Unit Interval time 33 | --- 34 | > parameter WRAPPER_SIM_PLL_PERDIV2 = 9'h140, // Set to the VCO Unit Interval time 35 | > parameter REVERSE_LANES = 0 36 | 306a321,322 37 | > //synthesis attribute X_CORE_INFO of ROCKETIO_WRAPPER is "gtxwizard_v1_6, Coregen v11.2"; 38 | > 39 | 659c675,677 40 | < .TILE_CHAN_BOND_LEVEL_1 (0) 41 | --- 42 | > .TILE_CHAN_BOND_LEVEL_1 (0), 43 | > 44 | > .REVERSE_LANES (REVERSE_LANES) 45 | 785c803 46 | < //TILE0 GTX0 47 | --- 48 | > //TILE0 GTP0 49 | 791c809 50 | < ) tile0_gtx0_cc_2b_1skp_i ( 51 | --- 52 | > ) tile0_gtp0_cc_2b_1skp_i ( 53 | 839c857 54 | < //TILE0 GTX1 55 | --- 56 | > //TILE0 GTP1 57 | 845c863 58 | < ) tile0_gtx1_cc_2b_1skp_i ( 59 | --- 60 | > ) tile0_gtp1_cc_2b_1skp_i ( 61 | 904c922,924 62 | < .TILE_CHAN_BOND_LEVEL_1 (1) 63 | --- 64 | > .TILE_CHAN_BOND_LEVEL_1 (1), 65 | > 66 | > .REVERSE_LANES (REVERSE_LANES) 67 | 1030c1050 68 | < BUFG tile1_rxrecclk0_bufg0_i 69 | --- 70 | > /*BUFG tile1_rxrecclk0_bufg0_i 71 | 1034c1054,1055 72 | < ); 73 | --- 74 | > );*/ 75 | > assign tile1_rxrecclk0_bufg_i = tile1_rxrecclk0_i; 76 | 1038c1059 77 | < //TILE1 GTX0 78 | --- 79 | > //TILE1 GTP0 80 | 1044c1065 81 | < ) tile1_gtx0_cc_2b_1skp_i ( 82 | --- 83 | > ) tile1_gtp0_cc_2b_1skp_i ( 84 | 1098c1119 85 | < //TILE1 GTX1 86 | --- 87 | > //TILE1 GTP1 88 | 1104c1125 89 | < ) tile1_gtx1_cc_2b_1skp_i ( 90 | --- 91 | > ) tile1_gtp1_cc_2b_1skp_i ( 92 | -------------------------------------------------------------------------------- /lib/hw/xilinx/pcores/axi_interconnect_v1_05_a/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # NetFPGA-10G http://www.netfpga.org 4 | # 5 | # File: 6 | # Makefile 7 | # 8 | # Library: 9 | # hw/xilinx/pcores/axi_interconnect_v1_05_a 10 | # 11 | # Description: 12 | # make install : Copy Xilinx files into NetFPGA-10G library 13 | # 14 | # For more information about how Xilinx EDK works, please visit 15 | # http://www.xilinx.com/support/documentation/dt_edk.htm 16 | # 17 | # Copyright notice: 18 | # Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford 19 | # Junior University 20 | # 21 | # Modifications for the UPB OpenFlow Switch project: 22 | # Copyright (c) 2014, 2015 Jörg Niklas, osjsn@niklasfamily.de 23 | # Project Group "On-the-Fly Networking for Big Data" 24 | # Computer Engineering Group, University of Paderborn 25 | # 26 | # DISCLAIMER NOTICE 27 | # We are not affiliated, associated, authorized, endorsed by, or in any way 28 | # officially connected with Xilinx, Inc. or any of its subsidiaries or its 29 | # affiliates. In no event whatsoever shall Xilinx, Inc. or any of its 30 | # subsidiaries or its affiliates have any warranty or support commitment 31 | # for this software or liability for loss, injury or damage in connection 32 | # with this software, including but not limited to the use or display thereof. 33 | # 34 | # Licence: 35 | # This file is part of the NetFPGA 10G development base package. 36 | # 37 | # This file is free code: you can redistribute it and/or modify it under 38 | # the terms of the GNU Lesser General Public License version 2.1 as 39 | # published by the Free Software Foundation. 40 | # 41 | # This package is distributed in the hope that it will be useful, but 42 | # WITHOUT ANY WARRANTY; without even the implied warranty of 43 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 44 | # Lesser General Public License for more details. 45 | # 46 | # You should have received a copy of the GNU Lesser General Public 47 | # License along with the NetFPGA source package. If not, see 48 | # http://www.gnu.org/licenses/. 49 | # 50 | # 51 | 52 | XILINX_HW_LIB_DIR = $(XILINX_EDK)/hw/XilinxProcessorIPLib/pcores 53 | HW_LIB_INSTANCE = $(shell basename $(shell pwd)) 54 | 55 | all: install 56 | 57 | install: 58 | false | cp -ri $(XILINX_HW_LIB_DIR)/$(HW_LIB_INSTANCE)/* . > /dev/null 2>&1 59 | sed -i '/OPTION ARCH_SUPPORT_MAP .*/d' data/axi_interconnect_v2_1_0.mpd 60 | sed -i 's/OPTION IMP_NETLIST = TRUE/OPTION IMP_NETLIST = FALSE/g' data/axi_interconnect_v2_1_0.mpd 61 | 62 | clean: 63 | rm -rf data doc hdl simmodels 64 | rm -f data/*.ui data/*.pao data/*.mui data/*.txt 65 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_10g_input_v1_00_a/hdl/verilog/width_div_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 10ns / 10ps 2 | 3 | /* 4 | * Copyright (c) 2014, 2015 Thomas Löcke 5 | * tloecke@mail.uni-paderborn.de 6 | * 7 | * This file is part of the NetFPGA 10G UPB OpenFlow Switch project: 8 | * 9 | * Project Group "On-the-Fly Networking for Big Data" 10 | * SFB 901 "On-The-Fly Computing" 11 | * 12 | * University of Paderborn 13 | * Computer Engineering Group 14 | * Pohlweg 47 - 49 15 | * 33098 Paderborn 16 | * Germany 17 | * 18 | * 19 | * This file is free code: you can redistribute it and/or modify it under 20 | * the terms of the GNU Lesser General Public License version 2.1 as 21 | * published by the Free Software Foundation. 22 | * 23 | * This file is distributed in the hope that it will be useful, 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 | * GNU Lesser General Public License for more details. 27 | * 28 | * You should have received a copy of the GNU Lesser General Public License 29 | * along with this project. If not, see . 30 | * 31 | */ 32 | 33 | module width_div_tb; 34 | 35 | // Inputs 36 | reg clk; 37 | reg reset; 38 | reg m_axis_tready; 39 | reg [255:0] s_axis_tdata; 40 | reg [31:0] s_axis_tkeep; 41 | reg s_axis_tvalid; 42 | reg [0:0] s_axis_tuser; 43 | reg s_axis_tlast; 44 | 45 | // Outputs 46 | wire [63:0] m_axis_tdata; 47 | wire [7:0] m_axis_tkeep; 48 | wire m_axis_tvalid; 49 | wire [0:0] m_axis_tuser; 50 | wire m_axis_tlast; 51 | wire s_axis_tready; 52 | 53 | // Instantiate the Unit Under Test (UUT) 54 | width_divider uut ( 55 | .clk(clk), 56 | .reset(reset), 57 | .m_axis_tdata(m_axis_tdata), 58 | .m_axis_tkeep(m_axis_tkeep), 59 | .m_axis_tvalid(m_axis_tvalid), 60 | .m_axis_tready(m_axis_tready), 61 | .m_axis_tuser(m_axis_tuser), 62 | .m_axis_tlast(m_axis_tlast), 63 | .s_axis_tdata(s_axis_tdata), 64 | .s_axis_tkeep(s_axis_tkeep), 65 | .s_axis_tvalid(s_axis_tvalid), 66 | .s_axis_tready(s_axis_tready), 67 | .s_axis_tuser(s_axis_tuser), 68 | .s_axis_tlast(s_axis_tlast) 69 | ); 70 | 71 | initial begin 72 | // Initialize Inputs 73 | clk = 0; 74 | reset = 0; 75 | m_axis_tready = 0; 76 | s_axis_tdata = 0; 77 | s_axis_tkeep = 0; 78 | s_axis_tvalid = 0; 79 | s_axis_tuser = 0; 80 | s_axis_tlast = 0; 81 | 82 | // Wait 100 ns for global reset to finish 83 | #100; 84 | 85 | // Add stimulus here 86 | @(posedge clk) 87 | m_axis_tready = 1; 88 | s_axis_tdata = {2{128'hDEADBEEFDEADBEEFAFFEDEADAFFEDEAD}}; 89 | s_axis_tkeep = 32'hFFFFFFFF; 90 | s_axis_tvalid = 1; 91 | 92 | 93 | end 94 | 95 | always 96 | #1 clk = ~clk; 97 | 98 | endmodule 99 | 100 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_axi_stream_chipscope_v1_00_a/data/nf10_upb_axi_stream_chipscope_v2_1_0.mpd: -------------------------------------------------------------------------------- 1 | # UPB AXI-4 Stream ChipScope core 2 | # 3 | # Copyright (c) 2014, 2015 Jörg Niklas 4 | # osjsn@niklasfamily.de 5 | # 6 | # This file is part of the NetFPGA 10G UPB OpenFlow Switch project. 7 | # 8 | # Project Group "On-the-Fly Networking for Big Data" 9 | # SFB 901 "On-The-Fly Computing" 10 | # 11 | # University of Paderborn 12 | # Computer Engineering Group 13 | # Pohlweg 47 - 49 14 | # 33098 Paderborn 15 | # Germany 16 | # 17 | # 18 | # This file is free code: you can redistribute it and/or modify it under 19 | # the terms of the GNU Lesser General Public License version 2.1 as 20 | # published by the Free Software Foundation. 21 | # 22 | # This file is distributed in the hope that it will be useful, 23 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 24 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 | # GNU Lesser General Public License for more details. 26 | # 27 | # You should have received a copy of the GNU Lesser General Public License 28 | # along with this project. If not, see . 29 | # 30 | 31 | BEGIN nf10_upb_axi_stream_chipscope 32 | 33 | OPTION IPTYPE = PERIPHERAL 34 | OPTION STYLE = BLACKBOX 35 | OPTION IP_GROUP = UPB 36 | OPTION DESC = NetFPGA-10G AXI Stream ChipScope Core 37 | 38 | BUS_INTERFACE BUS = AXIS, BUS_STD = AXIS, BUS_TYPE = MONITOR 39 | 40 | PARAMETER registered_bus = 1, DT = INTEGER, RANGE = (0:1) 41 | PARAMETER registered_chipscope = 0, DT = INTEGER, RANGE = (0:1) 42 | PARAMETER axis_data_width = 256, DT = integer 43 | PARAMETER axis_tkeep_width = 32, DT = integer 44 | PARAMETER axis_tuser_in_port_width = 3, DT = integer 45 | PARAMETER axis_tuser_out_port_width = 8, DT = integer 46 | PARAMETER axis_tuser_packet_length_width = 14, DT = integer 47 | PORT clk = "", DIR = I, SIGIS = CLK, ASSIGNMENT = REQUIRE 48 | PORT reset = "", DIR = I, SIGIS = RST 49 | PORT axis_tvalid = TVALID, BUS=AXIS, DIR = I 50 | PORT axis_tready = TREADY, BUS=AXIS, DIR = I 51 | PORT axis_tdata = TDATA, BUS=AXIS, DIR = I, VEC = [(axis_data_width-1):0] 52 | PORT axis_tkeep = TKEEP, BUS=AXIS, DIR = I, VEC = [(axis_tkeep_width-1):0] 53 | PORT axis_tlast = TLAST, BUS=AXIS, DIR = I 54 | PORT axis_tuser_packet_length = TUSER_PACKET_LENGTH, BUS=AXIS, DIR = I, VEC = [(axis_tuser_packet_length_width-1):0] 55 | PORT axis_tuser_in_port = TUSER_IN_PORT, BUS=AXIS, DIR = I, VEC = [(axis_tuser_in_port_width-1):0] 56 | PORT axis_tuser_in_vport = TUSER_IN_VPORT, BUS=AXIS, DIR = I, VEC = [(axis_tuser_in_port_width-1):0] 57 | PORT axis_tuser_out_port = TUSER_OUT_PORT, BUS=AXIS, DIR = I, VEC = [(axis_tuser_out_port_width-1):0] 58 | PORT axis_tuser_out_vport = TUSER_OUT_VPORT, BUS=AXIS, DIR = I, VEC = [(axis_tuser_out_port_width-1):0] 59 | PORT chipscope_control = "", DIR = IO, THREE_STATE = FALSE, VEC = [35:0], ASSIGNMENT = REQUIRE 60 | 61 | END 62 | 63 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_switch_v1_00_a/data/nf10_upb_switch_v2_1_0.mpd: -------------------------------------------------------------------------------- 1 | BEGIN nf10_upb_switch 2 | 3 | ## Peripheral Options 4 | OPTION IPTYPE = PERIPHERAL 5 | OPTION IMP_NETLIST = FALSE 6 | OPTION HDL = MIXED 7 | #OPTION USAGE_LEVEL = BASE_USER 8 | OPTION RUN_NGCBUILD = TRUE 9 | OPTION STYLE = BLACKBOX 10 | OPTION IP_GROUP = UPB 11 | OPTION DESC = NetFPGA-10G Layer 2 learning Switch Implementation 12 | 13 | 14 | ## Bus Interfaces 15 | BUS_INTERFACE BUS = M_AXIS, BUS_STD = AXIS, BUS_TYPE = INITIATOR 16 | BUS_INTERFACE BUS = S_AXIS, BUS_STD = AXIS, BUS_TYPE = TARGET 17 | 18 | ## Ports 19 | PARAMETER dma_port_id = 998, DT = integer, ASSIGNMENT = REQUIRE 20 | 21 | #PORT axi_aclk = "", DIR = I, SIGIS = CLK, BUS = M_AXIS:S_AXIS 22 | PORT clk = "", DIR = I, ASSIGNMENT = REQUIRE 23 | PORT clk2x = "", DIR = I, ASSIGNMENT = REQUIRE 24 | PORT clk2x90 = "", DIR = I, ASSIGNMENT = REQUIRE 25 | PORT reset = "", DIR = I 26 | 27 | 28 | 29 | 30 | 31 | PORT qdr_c_k = "", DIR = O 32 | PORT qdr_c_k_n = "", DIR = O 33 | PORT qdr_c_c = "", DIR = O 34 | PORT qdr_c_c_n = "", DIR = O 35 | PORT qdr_c_sa = "", DIR = O, VEC = [18:0] 36 | PORT qdr_c_r_n = "", DIR = O 37 | PORT qdr_c_w_n = "", DIR = O 38 | PORT qdr_c_bw_n = "", DIR = O, VEC = [3:0] 39 | PORT qdr_c_d = "", DIR = O, VEC = [35:0] 40 | PORT qdr_c_dll_off_n = "", DIR = O 41 | PORT qdr_c_cq = "", DIR = I 42 | PORT qdr_c_cq_n = "", DIR = I 43 | PORT qdr_c_q = "", DIR = I, VEC = [35:0] 44 | 45 | 46 | PORT m_axis_tdata = TDATA, DIR = O, VEC = [255:0], BUS = M_AXIS 47 | PORT m_axis_tkeep = TKEEP, DIR = O, VEC = [31:0], BUS = M_AXIS 48 | PORT m_axis_tuser_in_port = TUSER_IN_PORT, DIR = O, VEC = [2:0], BUS = M_AXIS 49 | PORT m_axis_tuser_in_vport = TUSER_IN_VPORT, DIR = O, VEC = [2:0], BUS = M_AXIS 50 | PORT m_axis_tuser_out_port = TUSER_OUT_PORT, DIR = O, VEC = [7:0], BUS = M_AXIS 51 | PORT m_axis_tuser_out_vport = TUSER_OUT_VPORT, DIR = O, VEC = [7:0], BUS = M_AXIS 52 | PORT m_axis_tuser_packet_length = TUSER_PACKET_LENGTH, DIR = O, VEC = [13:0], BUS = M_AXIS 53 | PORT m_axis_tvalid = TVALID, DIR = O, BUS = M_AXIS 54 | PORT m_axis_tready = TREADY, DIR = I, BUS = M_AXIS 55 | PORT m_axis_tlast = TLAST, DIR = O, BUS = M_AXIS 56 | 57 | PORT s_axis_tdata = TDATA, DIR = I, VEC = [255:0], BUS = S_AXIS 58 | PORT s_axis_tkeep = TKEEP, DIR = I, VEC = [31:0], BUS = S_AXIS 59 | PORT s_axis_tuser_in_port = TUSER_IN_PORT, DIR = I, VEC = [2:0], BUS = S_AXIS 60 | PORT s_axis_tuser_in_vport = TUSER_IN_VPORT, DIR = I, VEC = [2:0], BUS = S_AXIS 61 | PORT s_axis_tuser_out_port = TUSER_OUT_PORT, DIR = I, VEC = [7:0], BUS = S_AXIS 62 | PORT s_axis_tuser_out_vport = TUSER_OUT_VPORT, DIR = I, VEC = [7:0], BUS = S_AXIS 63 | PORT s_axis_tuser_packet_length = TUSER_PACKET_LENGTH, DIR = I, VEC = [13:0], BUS = S_AXIS 64 | PORT s_axis_tvalid = TVALID, DIR = I, BUS = S_AXIS 65 | PORT s_axis_tready = TREADY, DIR = O, BUS = S_AXIS 66 | PORT s_axis_tlast = TLAST, DIR = I, BUS = S_AXIS 67 | 68 | END 69 | -------------------------------------------------------------------------------- /lib/hw/contrib/pcores/nf10_upb_dma_v1_00_a/hdl/verilog/xilinx/pcie_top.v.patch: -------------------------------------------------------------------------------- 1 | DISCLAIMER NOTICE 2 | We are not affiliated, associated, authorized, endorsed by, or in any 3 | way officially connected with Xilinx, Inc. or any of its subsidiaries or 4 | its affiliates. In no event whatsoever shall Xilinx, Inc. or any of its 5 | subsidiaries or its affiliates have any warranty or support commitment 6 | for this software or liability for loss, injury or damage in connection 7 | with this software, including but not limited to the use or display 8 | thereof. 9 | --- 10 | 658c658 11 | < localparam [1:0] LINKCAPABILITYASPMSUPPORT_CALC = LINKCAPABILITYASPMSUPPORTEN ? 2'b11:2'b01; 12 | --- 13 | > localparam [1:0] LINKCAPABILITYASPMSUPPORT_CALC = 2'b00; // disable ASPM as the pcie block has too much problems with it 14 | 1251c1251 15 | < wire trn_reset_n; 16 | --- 17 | > reg trn_reset_n; 18 | 2008c2008,2010 19 | < assign trn_reset_n = PLLLKDET_OUT[0] && clock_lock && user_reset_workaround_n; //d_user_reset_n; 20 | --- 21 | > always@(posedge core_clk) 22 | > trn_reset_n <= PLLLKDET_OUT[0] && clock_lock && user_reset_workaround_n; //d_user_reset_n; 23 | > 24 | 2021a2024,2040 25 | > reg [7:0] pipe_rx_data_l0_ff, pipe_rx_data_l1_ff, pipe_rx_data_l2_ff, pipe_rx_data_l3_ff, pipe_rx_data_l4_ff, pipe_rx_data_l5_ff, pipe_rx_data_l6_ff, pipe_rx_data_l7_ff; 26 | > reg [7:0] pipe_rx_valid_ff; 27 | > reg [7:0] pipe_rx_data_k_ff; 28 | > 29 | > always @ (posedge core_clk) begin 30 | > pipe_rx_data_l0_ff <= pipe_rx_data_l0; 31 | > pipe_rx_data_l1_ff <= pipe_rx_data_l1; 32 | > pipe_rx_data_l2_ff <= pipe_rx_data_l2; 33 | > pipe_rx_data_l3_ff <= pipe_rx_data_l3; 34 | > pipe_rx_data_l4_ff <= pipe_rx_data_l4; 35 | > pipe_rx_data_l5_ff <= pipe_rx_data_l5; 36 | > pipe_rx_data_l6_ff <= pipe_rx_data_l6; 37 | > pipe_rx_data_l7_ff <= pipe_rx_data_l7; 38 | > pipe_rx_valid_ff <= pipe_rx_valid; 39 | > pipe_rx_data_k_ff <= pipe_rx_data_k; 40 | > end 41 | > 42 | 2028,2029c2047,2048 43 | < .pipe_rx_data_k(pipe_rx_data_k), 44 | < .pipe_rx_valid(pipe_rx_valid), 45 | --- 46 | > .pipe_rx_data_k(pipe_rx_data_k_ff), 47 | > .pipe_rx_valid(pipe_rx_valid_ff), 48 | 2034,2041c2053,2060 49 | < .pipe_rx_data_l0(pipe_rx_data_l0), 50 | < .pipe_rx_data_l1(pipe_rx_data_l1), 51 | < .pipe_rx_data_l2(pipe_rx_data_l2), 52 | < .pipe_rx_data_l3(pipe_rx_data_l3), 53 | < .pipe_rx_data_l4(pipe_rx_data_l4), 54 | < .pipe_rx_data_l5(pipe_rx_data_l5), 55 | < .pipe_rx_data_l6(pipe_rx_data_l6), 56 | < .pipe_rx_data_l7(pipe_rx_data_l7), 57 | --- 58 | > .pipe_rx_data_l0(pipe_rx_data_l0_ff), 59 | > .pipe_rx_data_l1(pipe_rx_data_l1_ff), 60 | > .pipe_rx_data_l2(pipe_rx_data_l2_ff), 61 | > .pipe_rx_data_l3(pipe_rx_data_l3_ff), 62 | > .pipe_rx_data_l4(pipe_rx_data_l4_ff), 63 | > .pipe_rx_data_l5(pipe_rx_data_l5_ff), 64 | > .pipe_rx_data_l6(pipe_rx_data_l6_ff), 65 | > .pipe_rx_data_l7(pipe_rx_data_l7_ff), 66 | --------------------------------------------------------------------------------